From 1f36f73fe70560a2bd286a7abc8530fdc93af9ae Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Thu, 12 Aug 2010 13:52:54 +0700
Subject: avr32: Add simple paging support

Use the MMU hardware to set up 1:1 mappings between physical and virtual
addresses. This allows us to bypass the cache when accessing the flash
without having to do any physical-to-virtual address mapping in the CFI
driver.

The virtual memory mappings are defined at compile time through a sorted
array of virtual memory range objects. When a TLB miss exception
happens, the exception handler does a binary search through the array
until it finds a matching entry and loads it into the TLB. The u-boot
image itself is covered by a fixed TLB entry which is never replaced.

This makes the 'saveenv' command work again on ATNGW100 and other boards
using the CFI driver, hopefully without breaking any rules.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 include/configs/atngw100.h      | 3 +++
 include/configs/atstk1002.h     | 3 +++
 include/configs/atstk1003.h     | 3 +++
 include/configs/atstk1004.h     | 3 +++
 include/configs/atstk1006.h     | 3 +++
 include/configs/favr-32-ezkit.h | 3 +++
 include/configs/hammerhead.h    | 3 +++
 include/configs/mimc200.h       | 3 +++
 8 files changed, 24 insertions(+)

(limited to 'include')

diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 4ed5514..83056b6 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -49,6 +49,9 @@
 #define CONFIG_SYS_CLKDIV_PBA			2
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index b258f2d..6416d17 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -73,6 +73,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index 2ef2552..a4d9b0b 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -73,6 +73,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index 195be82..06bb5da 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -73,6 +73,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
index f93118e..d3cbee6 100644
--- a/include/configs/atstk1006.h
+++ b/include/configs/atstk1006.h
@@ -73,6 +73,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h
index 739ff0d..1c381c7 100644
--- a/include/configs/favr-32-ezkit.h
+++ b/include/configs/favr-32-ezkit.h
@@ -70,6 +70,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h
index 0c70af5..8ca04ea 100644
--- a/include/configs/hammerhead.h
+++ b/include/configs/hammerhead.h
@@ -47,6 +47,9 @@
 #define CONFIG_SYS_CLKDIV_PBA			2
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h
index 36488b3..6ed9e75 100644
--- a/include/configs/mimc200.h
+++ b/include/configs/mimc200.h
@@ -51,6 +51,9 @@
 #define CONFIG_SYS_CLKDIV_PBA			2
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM, NOR flash and FRAM */
+#define CONFIG_SYS_NR_VM_REGIONS		3
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
-- 
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