From e436525a70fe47623d346bc7d9f08f12ff8ad787 Mon Sep 17 00:00:00 2001 From: Anish Trivedi Date: Fri, 9 Sep 2011 14:01:24 -0500 Subject: ENGR00156405 ESDHC: Add workaround for auto-clock gate errata ENGcm03648 The errata, not applicable to USDHC, causes ESDHC to shut off clock to the card when auto-clock gating is enabled for commands with busy signalling and no data phase. The card might require the clock to exit the busy state, so the workaround is to disable the auto-clock gate bits in SYSCTL register for such commands. The workaround also entails polling on DAT0 bit in the PRSSTAT register to learn when busy state is complete. Auto-clock gating is re-enabled at the end of busy state. Signed-off-by: Anish Trivedi --- include/fsl_esdhc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index fe62c01..df73e22 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -85,6 +85,7 @@ #define IRQSTATEN_CC (0x00000001) #define PRSSTAT 0x0002e024 +#define PRSSTAT_DAT0 (0x01000000) #define PRSSTAT_CLSL (0x00800000) #define PRSSTAT_WPSPL (0x00080000) #define PRSSTAT_CDPL (0x00040000) -- cgit v1.1