From d83b47b778805e2d3cfc9f6b14437f389f9da49f Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Feb 2016 13:04:17 -0800 Subject: arm: ls1021aqds: Convert to driver model and enable serial support Split duart configuration as device tree file. Move /chosen node out of board commone device tree. Convert ls1021aqds nor and SD configurations to driver model support (qspi already uses DM). Enable ns16550 DM serial driver for nor configurations. Signed-off-by: York Sun CC: Alison Wang CC: Bin Meng Reviewed-by: Bin Meng Reviewed-by: Alison Wang --- include/configs/ls1021aqds.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index f6efc55..5bdc124 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -375,7 +375,9 @@ unsigned long get_board_ddr_clk(void); #else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 +#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif -- cgit v1.1 From 9e71bb9ca232038e8cdc1090cf218871afb6904a Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Thu, 14 Jan 2016 18:12:29 +0530 Subject: armv8: ls2080a: Increase default hugepage count Increase default hugepage count to 256 from 16 Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index def0a6f..31c6e85 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -269,7 +269,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" + " hugepagesz=2m hugepages=256" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 10 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 116dbcd..356d254 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -333,7 +333,7 @@ unsigned long get_board_sys_clk(void); #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0600" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" + " hugepagesz=2m hugepages=256" /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET -- cgit v1.1 From 70097027d299e3486831396d3c02e37dc6dff66d Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 2 Feb 2016 15:16:23 +0800 Subject: arm: ls1021a: Add QSPI or IFC support in SD boot for LS1021AQDS board As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in SD boot now. For the customer's demand, QSPI needs to be supported in SD boot too. This patch adds QSPI or IFC support in SD boot according to the corresponding defconfig. For detail, ls1021aqds_sdcard_ifc_defconfig is used to support IFC in SD boot and ls1021aqds_sdcard_qspi_defconfig is used to support QSPI in SD boot. Signed-off-by: Alison Wang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5bdc124..39d747f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -42,7 +42,7 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_QIXIS_I2C_ACCESS @@ -56,7 +56,13 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg +#endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT @@ -87,6 +93,9 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_QSPI_BOOT #define CONFIG_SYS_TEXT_BASE 0x40010000 +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NO_FLASH #endif @@ -162,7 +171,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -412,7 +421,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION /* SPI */ -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) /* QSPI */ #define QSPI0_AMBA_BASE 0x40000000 #define FSL_QSPI_FLASH_SIZE (1 << 24) @@ -557,6 +566,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#undef CONFIG_CMD_IMLS +#endif + #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN -- cgit v1.1 From 16ed85601918cff4b99ac01afa4cfa0581eb2588 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Wed, 3 Feb 2016 17:03:51 +0530 Subject: armv8: ls2080: Add mcinitcmd env variable in default env Define mcinitcmd env variable to load Management complex during u-boot boot sequence. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 4 +++- include/configs/ls2080aqds.h | 4 +++- include/configs/ls2080ardb.h | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 31c6e85..51c3a17 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -264,7 +264,9 @@ unsigned long long get_qixis_addr(void); "kernel_start=0x581200000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" + "console=ttyAMA0,38400n8\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" \ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index a402c06..dab3820 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -346,7 +346,9 @@ unsigned long get_board_ddr_clk(void); "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" + "kernel_size=0x2800000\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" #ifdef CONFIG_FSL_MC_ENET #define CONFIG_FSL_MEMAC diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 356d254..b2c0181 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -327,7 +327,9 @@ unsigned long get_board_sys_clk(void); "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" + "kernel_size=0x2800000\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ -- cgit v1.1 From 9f3e1b8a55060bcb2c52e2e3a828a70c7e106219 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Wed, 3 Feb 2016 17:04:07 +0530 Subject: armv8: ls2080: Update bootcmd env variable Before Linux boot DPL must be deployed to DPAA2 interface. So update bootcmd env variable to make sure DPL deployment before Linux boot. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 51c3a17..64b82e8 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -272,8 +272,9 @@ unsigned long long get_qixis_addr(void); "earlycon=uart8250,mmio,0x21c0500" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=256" -#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ - "$kernel_size && bootm $kernel_load" +#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ + " cp.b $kernel_start $kernel_load" \ + " $kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ -- cgit v1.1 From 2459afb1a783e34d37c0f7aeec43c77f4de4d480 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Thu, 18 Feb 2016 13:01:59 +0800 Subject: qe: move drivers/qe/qe.h to include/fsl_qe.h As the QE firmware struct is shared with Fman, move the header file out of drivers/qe/. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/fsl_qe.h | 299 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 299 insertions(+) create mode 100644 include/fsl_qe.h (limited to 'include') diff --git a/include/fsl_qe.h b/include/fsl_qe.h new file mode 100644 index 0000000..77b18e9 --- /dev/null +++ b/include/fsl_qe.h @@ -0,0 +1,299 @@ +/* + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __QE_H__ +#define __QE_H__ + +#include "common.h" +#ifdef CONFIG_U_QE +#include +#endif + +#define QE_NUM_OF_BRGS 16 +#define UCC_MAX_NUM 8 + +#define QE_DATAONLY_BASE 0 +#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE) + +/* QE threads SNUM +*/ +typedef enum qe_snum_state { + QE_SNUM_STATE_USED, /* used */ + QE_SNUM_STATE_FREE /* free */ +} qe_snum_state_e; + +typedef struct qe_snum { + u8 num; /* snum */ + qe_snum_state_e state; /* state */ +} qe_snum_t; + +/* QE RISC allocation +*/ +#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ +#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ +#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ +#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2) +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2 | \ + QE_RISC_ALLOCATION_RISC3 | \ + QE_RISC_ALLOCATION_RISC4) + +/* QE CECR commands for UCC fast. +*/ +#define QE_CR_FLG 0x00010000 +#define QE_RESET 0x80000000 +#define QE_INIT_TX_RX 0x00000000 +#define QE_INIT_RX 0x00000001 +#define QE_INIT_TX 0x00000002 +#define QE_ENTER_HUNT_MODE 0x00000003 +#define QE_STOP_TX 0x00000004 +#define QE_GRACEFUL_STOP_TX 0x00000005 +#define QE_RESTART_TX 0x00000006 +#define QE_SWITCH_COMMAND 0x00000007 +#define QE_SET_GROUP_ADDRESS 0x00000008 +#define QE_INSERT_CELL 0x00000009 +#define QE_ATM_TRANSMIT 0x0000000a +#define QE_CELL_POOL_GET 0x0000000b +#define QE_CELL_POOL_PUT 0x0000000c +#define QE_IMA_HOST_CMD 0x0000000d +#define QE_ATM_MULTI_THREAD_INIT 0x00000011 +#define QE_ASSIGN_PAGE 0x00000012 +#define QE_START_FLOW_CONTROL 0x00000014 +#define QE_STOP_FLOW_CONTROL 0x00000015 +#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 +#define QE_GRACEFUL_STOP_RX 0x0000001a +#define QE_RESTART_RX 0x0000001b + +/* QE CECR Sub Block Code - sub block code of QE command. +*/ +#define QE_CR_SUBBLOCK_INVALID 0x00000000 +#define QE_CR_SUBBLOCK_USB 0x03200000 +#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 +#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 +#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 +#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 +#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 +#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 +#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 +#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 +#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 +#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 +#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 +#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 +#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 +#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 +#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 +#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 +#define QE_CR_SUBBLOCK_MCC1 0x03800000 +#define QE_CR_SUBBLOCK_MCC2 0x03a00000 +#define QE_CR_SUBBLOCK_MCC3 0x03000000 +#define QE_CR_SUBBLOCK_IDMA1 0x02800000 +#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 +#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 +#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 +#define QE_CR_SUBBLOCK_HPAC 0x01e00000 +#define QE_CR_SUBBLOCK_SPI1 0x01400000 +#define QE_CR_SUBBLOCK_SPI2 0x01600000 +#define QE_CR_SUBBLOCK_RAND 0x01c00000 +#define QE_CR_SUBBLOCK_TIMER 0x01e00000 +#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 + +/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command. +*/ +#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ +#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 +#define QE_CR_PROTOCOL_ATM_POS 0x0A +#define QE_CR_PROTOCOL_ETHERNET 0x0C +#define QE_CR_PROTOCOL_L2_SWITCH 0x0D +#define QE_CR_PROTOCOL_SHIFT 6 + +/* QE ASSIGN PAGE command +*/ +#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17 + +/* Communication Direction. +*/ +typedef enum comm_dir { + COMM_DIR_NONE = 0, + COMM_DIR_RX = 1, + COMM_DIR_TX = 2, + COMM_DIR_RX_AND_TX = 3 +} comm_dir_e; + +/* Clocks and BRG's +*/ +typedef enum qe_clock { + QE_CLK_NONE = 0, + QE_BRG1, /* Baud Rate Generator 1 */ + QE_BRG2, /* Baud Rate Generator 2 */ + QE_BRG3, /* Baud Rate Generator 3 */ + QE_BRG4, /* Baud Rate Generator 4 */ + QE_BRG5, /* Baud Rate Generator 5 */ + QE_BRG6, /* Baud Rate Generator 6 */ + QE_BRG7, /* Baud Rate Generator 7 */ + QE_BRG8, /* Baud Rate Generator 8 */ + QE_BRG9, /* Baud Rate Generator 9 */ + QE_BRG10, /* Baud Rate Generator 10 */ + QE_BRG11, /* Baud Rate Generator 11 */ + QE_BRG12, /* Baud Rate Generator 12 */ + QE_BRG13, /* Baud Rate Generator 13 */ + QE_BRG14, /* Baud Rate Generator 14 */ + QE_BRG15, /* Baud Rate Generator 15 */ + QE_BRG16, /* Baud Rate Generator 16 */ + QE_CLK1, /* Clock 1 */ + QE_CLK2, /* Clock 2 */ + QE_CLK3, /* Clock 3 */ + QE_CLK4, /* Clock 4 */ + QE_CLK5, /* Clock 5 */ + QE_CLK6, /* Clock 6 */ + QE_CLK7, /* Clock 7 */ + QE_CLK8, /* Clock 8 */ + QE_CLK9, /* Clock 9 */ + QE_CLK10, /* Clock 10 */ + QE_CLK11, /* Clock 11 */ + QE_CLK12, /* Clock 12 */ + QE_CLK13, /* Clock 13 */ + QE_CLK14, /* Clock 14 */ + QE_CLK15, /* Clock 15 */ + QE_CLK16, /* Clock 16 */ + QE_CLK17, /* Clock 17 */ + QE_CLK18, /* Clock 18 */ + QE_CLK19, /* Clock 19 */ + QE_CLK20, /* Clock 20 */ + QE_CLK21, /* Clock 21 */ + QE_CLK22, /* Clock 22 */ + QE_CLK23, /* Clock 23 */ + QE_CLK24, /* Clock 24 */ + QE_CLK_DUMMY +} qe_clock_e; + +/* QE CMXGCR register +*/ +#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000 +#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 + +/* QE CMXUCR registers + */ +#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F + +/* QE BRG configuration register +*/ +#define QE_BRGC_ENABLE 0x00010000 +#define QE_BRGC_DIVISOR_SHIFT 1 +#define QE_BRGC_DIVISOR_MAX 0xFFF +#define QE_BRGC_DIV16 1 + +/* QE SDMA registers +*/ +#define QE_SDSR_BER1 0x02000000 +#define QE_SDSR_BER2 0x01000000 + +#define QE_SDMR_GLB_1_MSK 0x80000000 +#define QE_SDMR_ADR_SEL 0x20000000 +#define QE_SDMR_BER1_MSK 0x02000000 +#define QE_SDMR_BER2_MSK 0x01000000 +#define QE_SDMR_EB1_MSK 0x00800000 +#define QE_SDMR_ER1_MSK 0x00080000 +#define QE_SDMR_ER2_MSK 0x00040000 +#define QE_SDMR_CEN_MASK 0x0000E000 +#define QE_SDMR_SBER_1 0x00000200 +#define QE_SDMR_SBER_2 0x00000200 +#define QE_SDMR_EB1_PR_MASK 0x000000C0 +#define QE_SDMR_ER1_PR 0x00000008 + +#define QE_SDMR_CEN_SHIFT 13 +#define QE_SDMR_EB1_PR_SHIFT 6 + +#define QE_SDTM_MSNUM_SHIFT 24 + +#define QE_SDEBCR_BA_MASK 0x01FFFFFF + +/* Communication Processor */ +#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ +#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ +#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ + +/* I-RAM */ +#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ +#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ +#define QE_IRAM_READY 0x80000000 + +/* Structure that defines QE firmware binary files. + * + * See doc/README.qe_firmware for a description of these fields. + */ +struct qe_firmware { + struct qe_header { + u32 length; /* Length of the entire structure, in bytes */ + u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ + u8 version; /* Version of this layout. First ver is '1' */ + } header; + u8 id[62]; /* Null-terminated identifier string */ + u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ + u8 count; /* Number of microcode[] structures */ + struct { + u16 model; /* The SOC model */ + u8 major; /* The SOC revision major */ + u8 minor; /* The SOC revision minor */ + } __attribute__ ((packed)) soc; + u8 padding[4]; /* Reserved, for alignment */ + u64 extended_modes; /* Extended modes */ + u32 vtraps[8]; /* Virtual trap addresses */ + u8 reserved[4]; /* Reserved, for future expansion */ + struct qe_microcode { + u8 id[32]; /* Null-terminated identifier */ + u32 traps[16]; /* Trap addresses, 0 == ignore */ + u32 eccr; /* The value for the ECCR register */ + u32 iram_offset;/* Offset into I-RAM for the code */ + u32 count; /* Number of 32-bit words of the code */ + u32 code_offset;/* Offset of the actual microcode */ + u8 major; /* The microcode version major */ + u8 minor; /* The microcode version minor */ + u8 revision; /* The microcode version revision */ + u8 padding; /* Reserved, for alignment */ + u8 reserved[4]; /* Reserved, for future expansion */ + } __attribute__ ((packed)) microcode[1]; + /* All microcode binaries should be located here */ + /* CRC32 should be located here, after the microcode binaries */ +} __attribute__ ((packed)); + +struct qe_firmware_info { + char id[64]; /* Firmware name */ + u32 vtraps[8]; /* Virtual trap addresses */ + u64 extended_modes; /* Extended modes */ +}; + +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); +void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); +uint qe_muram_alloc(uint size, uint align); +void *qe_muram_addr(uint offset); +int qe_get_snum(void); +void qe_put_snum(u8 snum); +void qe_init(uint qe_base); +void qe_reset(void); +void qe_assign_page(uint snum, uint para_ram_base); +int qe_set_brg(uint brg, uint rate); +int qe_set_mii_clk_src(int ucc_num); +int qe_upload_firmware(const struct qe_firmware *firmware); +struct qe_firmware_info *qe_get_firmware_info(void); +void ft_qe_setup(void *blob); +void qe_init(uint qe_base); +void qe_reset(void); + +#ifdef CONFIG_U_QE +void u_qe_init(void); +int u_qe_upload_firmware(const struct qe_firmware *firmware); +void u_qe_resume(void); +int u_qe_firmware_resume(const struct qe_firmware *firmware, + qe_map_t *qe_immrr); +#endif + +#endif /* __QE_H__ */ -- cgit v1.1 From 075affb1ac0cc72e4d599df5f39bd40389312d6a Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Thu, 18 Feb 2016 13:02:00 +0800 Subject: fm: fdt: Move fman ucode fixup to driver code Not only powerpc/mpc85xx but also Freescale Layerscape platforms will use fdt_fixup_fman_firmware() to insert Fman ucode blob into the device tree. So move the function to Fman driver code. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/fsl_fman.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fsl_fman.h b/include/fsl_fman.h index 4d04415..f3e35f8 100644 --- a/include/fsl_fman.h +++ b/include/fsl_fman.h @@ -460,4 +460,5 @@ typedef struct ccsr_fman { u8 res5[4*1024]; } ccsr_fman_t; +void fdt_fixup_fman_firmware(void *blob); #endif /*__FSL_FMAN_H__*/ -- cgit v1.1 From 5a7c40bea618dfa50c6ae5f171782b49fd8250a6 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Tue, 16 Feb 2016 13:12:53 +0800 Subject: armv8/ls1043aqds: Add USB support for ls1043aqds Add USB XHCI support for ls1043qds board. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1043aqds.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4ab8e13..158cf02 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -379,6 +379,19 @@ unsigned long get_board_ddr_clk(void); #endif #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + /* * Miscellaneous configurable options */ -- cgit v1.1 From d3e6d30cef41d929dcab2ce8dcb93d92319a49a2 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 5 Feb 2016 10:04:17 +0800 Subject: board: ls1043ardb: Add micro QE support for ls1043ardb Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- include/configs/ls1043ardb.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 506f50d..bc40b06 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -268,6 +268,13 @@ #define CONFIG_ETHPRIME "FM1@DTSEC3" #endif +/* QE */ +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) +#define CONFIG_U_QE +#endif +#define CONFIG_SYS_QE_FW_ADDR 0x60600000 + /* USB */ #define CONFIG_HAS_FSL_XHCI_USB #ifdef CONFIG_HAS_FSL_XHCI_USB -- cgit v1.1