From bd6578e46d1ba93ffe6e00147704d7d18c7e5573 Mon Sep 17 00:00:00 2001 From: Terry Lv Date: Wed, 24 Feb 2010 18:34:13 +0800 Subject: ENGR00120520: Enable MMU for mx51 and mx35 MMU enable code is missed in mx51 and mx35 u-boot. So add these codes. Signed-off-by: Terry Lv --- include/asm-arm/arch-mx35/mmu.h | 39 +++++++++++++++- include/asm-arm/arch-mx51/mmu.h | 82 +++++++++++++++++++++++++++++++- include/asm-arm/cache-cp15.h | 88 +++++++++++++++++++++++++++++++++++ include/asm-arm/fec.h | 7 ++- include/asm-arm/io.h | 2 +- include/asm-arm/mmu.h | 41 +++++++++++++++- include/configs/mx35_3stack.h | 4 +- include/configs/mx35_3stack_mmc.h | 4 +- include/configs/mx51_3stack.h | 4 +- include/configs/mx51_3stack_android.h | 4 +- include/configs/mx51_bbg.h | 4 +- include/configs/mx51_bbg_android.h | 4 +- 12 files changed, 268 insertions(+), 15 deletions(-) create mode 100644 include/asm-arm/cache-cp15.h (limited to 'include') diff --git a/include/asm-arm/arch-mx35/mmu.h b/include/asm-arm/arch-mx35/mmu.h index a701c72..1e9a96f 100644 --- a/include/asm-arm/arch-mx35/mmu.h +++ b/include/asm-arm/arch-mx35/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -132,4 +132,41 @@ union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { ARM_ACCESS_TYPE_NO_ACCESS(14) | \ ARM_ACCESS_TYPE_NO_ACCESS(15)) +/* + * Translate the virtual address of ram space to physical address + * It is dependent on the implementation of mmu_init + */ +inline void *iomem_to_phys(unsigned long virt) +{ + if (virt < 0x08000000) + return (void *)(virt | PHYS_SDRAM_1); + + if ((virt & 0xF0000000) == PHYS_SDRAM_1) + return (void *)(virt & (~0x08000000)); + + return (void *)virt; +} + +/* + * Remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void __iounmap(void *addr) +{ + return; +} + +void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + if (1 == flags) { + /* 0x88000000~0x87FFFFFF is uncacheable meory + space which is mapped to SDRAM */ + if ((offset & 0xF0000000) == PHYS_SDRAM_1) + return (void *)(offset | 0x08000000); + else + return NULL; + } else + return (void *)offset; +} + #endif diff --git a/include/asm-arm/arch-mx51/mmu.h b/include/asm-arm/arch-mx51/mmu.h index a701c72..e80cfc9 100644 --- a/include/asm-arm/arch-mx51/mmu.h +++ b/include/asm-arm/arch-mx51/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -14,6 +14,8 @@ #ifndef __ARM_ARCH_MMU_H #define __ARM_ARCH_MMU_H +#include + /* * Translation Table Base Bit Masks */ @@ -132,4 +134,82 @@ union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { ARM_ACCESS_TYPE_NO_ACCESS(14) | \ ARM_ACCESS_TYPE_NO_ACCESS(15)) +#if defined(CONFIG_MX51_3DS) + +/* + * Translate the virtual address of ram space to physical address + * It is dependent on the implementation of mmu_init + */ +inline void *iomem_to_phys(unsigned long virt) +{ + if (virt < 0x08000000) + return (void *)(virt | PHYS_SDRAM_1); + + if ((virt & 0xF0000000) == PHYS_SDRAM_1) + return (void *)(virt & (~0x08000000)); + + return (void *)virt; +} + +/* + * remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + if (1 == flags) { + /* 0x98000000~0x9FFFFFFF is uncacheable meory + space which is mapped to SDRAM */ + if ((offset & 0xF0000000) == PHYS_SDRAM_1) + return (void *)(offset |= 0x08000000); + else + return NULL; + } else + return (void *)offset; +} + +#elif defined(CONFIG_MX51_BBG) + +/* + * Translate the virtual address of ram space to physical address + * It is dependent on the implementation of mmu_init + */ +inline void *iomem_to_phys(unsigned long virt) +{ + if (virt < (PHYS_SDRAM_1_SIZE - 0x100000)) + return (void *)(virt + PHYS_SDRAM_1); + + if (virt >= 0xE0000000) + return (void *)((virt - 0xE0000000) + PHYS_SDRAM_1); + + return (void *)virt; +} + +/* + * Remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void __iounmap(void *addr) +{ + return; +} + +void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + if (1 == flags) { + /* 0xE0000000~0xFFFFFFFF is uncacheable + meory space which is mapped to SDRAM */ + if (offset >= PHYS_SDRAM_1 && + offset < (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + return (void *)(offset - PHYS_SDRAM_1) + 0xE0000000; + else + return NULL; + } else + return (void *)offset; +} + +#else + #error "No such platforms for MMU!" +#endif + #endif diff --git a/include/asm-arm/cache-cp15.h b/include/asm-arm/cache-cp15.h new file mode 100644 index 0000000..4996ee0 --- /dev/null +++ b/include/asm-arm/cache-cp15.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) +#define cp_delay() \ +{ \ + volatile int i; \ + /* copro seems to need some delay between reading and writing */ \ + for (i = 0; i < 100; i++) \ + nop(); \ +} + +/* cache_bit must be either CR_I or CR_C */ +#define cache_enable(cache_bit) \ +{ \ + uint32_t reg; \ + reg = get_cr(); /* get control reg. */ \ + set_cr(reg | cache_bit); \ + cp_delay(); \ +} + +/* cache_bit must be either CR_I or CR_C */ +#define cache_disable(cache_bit) \ +{ \ + uint32_t reg; \ + reg = get_cr(); \ + set_cr(reg & ~cache_bit); \ + cp_delay(); \ +} + +#endif + +#ifdef CONFIG_SYS_NO_ICACHE +#define icache_enable() + +#define icache_disable() + +#define icache_status() +#else +#define icache_enable() (cache_enable(CR_I)) + +#define icache_disable() (cache_disable(CR_I)) + +#define icache_status() ((get_cr() & CR_I) != 0) +#endif + +#ifdef CONFIG_SYS_NO_DCACHE +#define dcache_enable() + +#define dcache_disable() + +#define dcache_status() +#else +#define dcache_enable() (cache_enable(CR_C)) + +#define dcache_disable() \ +{ \ + cache_disable(CR_C); \ +} + +#define dcache_status() ((get_cr() & CR_C) != 0) + +#endif diff --git a/include/asm-arm/fec.h b/include/asm-arm/fec.h index fd2cc10..4e81fa0 100644 --- a/include/asm-arm/fec.h +++ b/include/asm-arm/fec.h @@ -6,7 +6,7 @@ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) * * Add FEC Structure and definitions - * Copyright 2004-2009 Freescale Semiconductor, Inc. + * Copyright 2004-2010 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -31,6 +31,8 @@ #ifndef fec_h #define fec_h +#include + /* Buffer descriptors used FEC. */ typedef struct cpm_buf_desc { @@ -111,6 +113,9 @@ struct fec_info_s { uint rxIdx; uint txIdx; char *txbuf; +#ifdef CONFIG_ARCH_MMU + char *rxbuf[PKTBUFSRX]; +#endif int initialized; struct fec_info_s *next; }; diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index fec3a7e..b8881f1 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -198,7 +198,7 @@ extern void __iounmap(void *addr); unsigned long _off = (off), _size = (sz); \ void *_ret = (void *)0; \ if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ + _ret = __ioremap(iomem_to_phys(_off), _size, nocache); \ _ret; \ }) diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h index 668dfc9..f1b7574 100644 --- a/include/asm-arm/mmu.h +++ b/include/asm-arm/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -14,6 +14,7 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H +#include #define MMU_L1_TYPE 0x03 /* Descriptor type */ #define MMU_L1_TYPE_Fault 0x00 /* Invalid */ @@ -76,4 +77,42 @@ #define MMU_Control_Z 0x800 /* Enable branch predicion */ #define MMU_Control_RR 0x4000 /* Select non-random cache replacement */ +#ifdef CONFIG_ARCH_MMU + +#define MMU_ON() \ + { \ + unsigned long cr = 0; \ + asm volatile ("mrc p15, 0, %0, c1, c0;" : "=r"(cr) : /*:*/); \ + cr |= (CR_M | CR_A | CR_C | CR_Z); \ + asm volatile ("mcr p15, 0, %0, c1, c0;" : : "r"(cr) /*:*/); \ + /* Clean instruction pipeline */ \ + asm volatile ( \ + "b skip;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "skip:" \ + ); \ + } + +#define MMU_OFF() \ + { \ + unsigned long cr = 0; \ + asm volatile ("mrc p15, 0, %0, c1, c0;" : "=r"(cr) /*: :*/); \ + cr &= (~(CR_M | CR_A | CR_C | CR_I)); \ + asm volatile ("mcr p15, 0, %0, c1, c0;" : : "r"(cr) /*:*/); \ + asm volatile ( \ + "nop;" /* flush i+d-TLBs */ \ + "nop;" /* flush i+d-TLBs */ \ + "nop;" /* flush i+d-TLBs */ \ + ); \ + } + +#else + +#define MMU_ON() +#define MMU_OFF() + +#endif + #endif diff --git a/include/configs/mx35_3stack.h b/include/configs/mx35_3stack.h index 21e5acf..bc420b2 100644 --- a/include/configs/mx35_3stack.h +++ b/include/configs/mx35_3stack.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2007, Guennadi Liakhovetski * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. * * Configuration settings for the MX31ADS Freescale board. * @@ -182,6 +182,8 @@ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/mx35_3stack_mmc.h b/include/configs/mx35_3stack_mmc.h index 9a1dd70..c9cc157 100644 --- a/include/configs/mx35_3stack_mmc.h +++ b/include/configs/mx35_3stack_mmc.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2007, Guennadi Liakhovetski * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. * * Configuration settings for the MX31ADS Freescale board. * @@ -183,6 +183,8 @@ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) /* * MMC Configs diff --git a/include/configs/mx51_3stack.h b/include/configs/mx51_3stack.h index f6083c5..a942bfe 100644 --- a/include/configs/mx51_3stack.h +++ b/include/configs/mx51_3stack.h @@ -213,9 +213,9 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE_ADDR -/* TO1 boards */ -/* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */ #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/mx51_3stack_android.h b/include/configs/mx51_3stack_android.h index 52e7b99..fabb718 100644 --- a/include/configs/mx51_3stack_android.h +++ b/include/configs/mx51_3stack_android.h @@ -268,9 +268,9 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE_ADDR -/* TO1 boards */ -/* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */ #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/mx51_bbg.h b/include/configs/mx51_bbg.h index b2961a2..c17c82c 100644 --- a/include/configs/mx51_bbg.h +++ b/include/configs/mx51_bbg.h @@ -209,9 +209,9 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE_ADDR -/* TO1 boards */ -/* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */ #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/mx51_bbg_android.h b/include/configs/mx51_bbg_android.h index a7685c7..07663be 100644 --- a/include/configs/mx51_bbg_android.h +++ b/include/configs/mx51_bbg_android.h @@ -260,9 +260,9 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE_ADDR -/* TO1 boards */ -/* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */ #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) /*----------------------------------------------------------------------- * FLASH and environment organization -- cgit v1.1