From e443c944cf4050daffb46d4788446d6c2df8ac6c Mon Sep 17 00:00:00 2001
From: Markus Klotzbuecher <mk@denx.de>
Date: Mon, 20 Mar 2006 18:02:44 +0100
Subject: Support for redundant environment in NAND Flash.

---
 include/configs/delta.h |  1 +
 include/environment.h   | 12 ++++++++++++
 2 files changed, 13 insertions(+)

(limited to 'include')

diff --git a/include/configs/delta.h b/include/configs/delta.h
index b42a7e2..f230b03 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -282,6 +282,7 @@
 /* #define CFG_ENV_IS_NOWHERE */
 #define CFG_ENV_IS_IN_NAND	1
 #define CFG_ENV_OFFSET		0x40000
+#define CFG_ENV_OFFSET_REDUND	0x44000
 #define CFG_ENV_SIZE		0x4000
 
 #endif	/* __CONFIG_H */
diff --git a/include/environment.h b/include/environment.h
index bb10964..422f800 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -69,6 +69,18 @@
 # endif
 #endif	/* CFG_ENV_IS_IN_FLASH */
 
+#if defined(CFG_ENV_IS_IN_NAND)
+# ifndef CFG_ENV_OFFSET
+#  error "Need to define CFG_ENV_OFFSET when using CFG_ENV_IS_IN_NAND"
+# endif
+# ifndef CFG_ENV_SIZE
+#  error "Need to define CFG_ENV_SIZE when using CFG_ENV_IS_IN_NAND"
+# endif
+# ifdef CFG_ENV_OFFSET_REDUND
+#  define CFG_REDUNDAND_ENVIRONMENT
+# endif
+#endif /* CFG_ENV_IS_IN_NAND */
+
 
 #ifdef CFG_REDUNDAND_ENVIRONMENT
 # define ENV_HEADER_SIZE	(sizeof(unsigned long) + 1)
-- 
cgit v1.1


From 552fc624f28d5db7b25f38c4e104fb7255d7df6b Mon Sep 17 00:00:00 2001
From: Markus Klotzbuecher <mk@denx.de>
Date: Mon, 20 Mar 2006 20:19:37 +0100
Subject: Cleanup of the monahans cpu and delta board port.

---
 include/asm-arm/arch-pxa/pxa-regs.h | 117 ++++++++++++++++++------------------
 include/configs/delta.h             | 100 ++++--------------------------
 2 files changed, 72 insertions(+), 145 deletions(-)

(limited to 'include')

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 83ae5e3..a92a450 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -821,21 +821,21 @@ typedef void		(*ExcpHndlr) (void) ;
 #define RTAR		__REG(0x40900004)  /* RTC Alarm Register */
 #define RTSR		__REG(0x40900008)  /* RTC Status Register */
 #define RTTR		__REG(0x4090000C)  /* RTC Timer Trim Register */
-#define RDAR1	   __REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */
-#define RDAR2	   __REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */
-#define RYAR1	   __REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
-#define RYAR2	   __REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */
-#define SWAR1	   __REG(0x4090002C)  /* Stopwatch Alarm Register 1 */
-#define SWAR2	   __REG(0x40900030)  /* Stopwatch Alarm Register 2 */
-#define PIAR	   __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
-#define RDCR	   __REG(0x40900010)  /* RTC Day Count Register. */
-#define RYCR	   __REG(0x40900014)  /* RTC Year Count Register. */
-#define SWCR	   __REG(0x40900028)  /* Stopwatch Count Register */
-#define RTCPICR	   __REG(0x40900034)  /* Periodic Interrupt Counter Register */
-
-#define RTSR_PICE  (1 << 15)   /* Peridoc interrupt count enable */
-#define RTSR_PIALE (1 << 14)   /* Peridoc interrupt Alarm enable */
-#define RTSR_PIAL  (1 << 13)   /* Peridoc  interrupt Alarm status */
+#define RDAR1		__REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2		__REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1		__REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2		__REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1		__REG(0x4090002C)  /* Stopwatch Alarm Register 1 */
+#define SWAR2		__REG(0x40900030)  /* Stopwatch Alarm Register 2 */
+#define PIAR		__REG(0x40900038)  /* Periodic Interrupt Alarm Register */
+#define RDCR		__REG(0x40900010)  /* RTC Day Count Register. */
+#define RYCR		__REG(0x40900014)  /* RTC Year Count Register. */
+#define SWCR		__REG(0x40900028)  /* Stopwatch Count Register */
+#define RTCPICR		__REG(0x40900034)  /* Periodic Interrupt Counter Register */
+
+#define RTSR_PICE	(1 << 15)	/* Peridoc interrupt count enable */
+#define RTSR_PIALE	(1 << 14)	/* Peridoc interrupt Alarm enable */
+#define RTSR_PIAL	(1 << 13)	/* Peridoc  interrupt Alarm status */
 #define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
 #define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
 #define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
@@ -921,9 +921,10 @@ typedef void		(*ExcpHndlr) (void) ;
 
 #ifdef CONFIG_CPU_MONAHANS
 #define ICHP		__REG(0x40D00018)  /* Interrupt Controller Highest Priority Register */
-/* Missing: 32 Interrupt priority registers */
-/* mk@tbd: These are the same as beneath for PXA27x: maybe can be
- * merged if GPIO Stuff is same too. */
+/* Missing: 32 Interrupt priority registers
+ * These are the same as beneath for PXA27x: maybe can be merged if
+ * GPIO Stuff is same too. 
+ */
 #define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
 #define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
 #define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
@@ -983,24 +984,24 @@ typedef void		(*ExcpHndlr) (void) ;
 #define GCDR3		__REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
 
 #define GSRER0		__REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
-#define GSRER1  	__REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER1		__REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
 #define GSRER2		__REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
-#define GSRER3  	__REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
+#define GSRER3		__REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
 
 #define GCRER0		__REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
-#define GCRER1  	__REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER1		__REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
 #define GCRER2		__REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
-#define GCRER3  	__REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
+#define GCRER3		__REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
 
 #define GSFER0		__REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
-#define GSFER1  	__REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER1		__REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
 #define GSFER2		__REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
-#define GSFER3  	__REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
+#define GSFER3		__REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
 
 #define GCFER0		__REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
-#define GCFER1  	__REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER1		__REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
 #define GCFER2		__REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
-#define GCFER3  	__REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
+#define GCFER3		__REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
 
 #define GSDR(x)		__REG2(0x40E00400, ((x) & 0x60) >> 3)
 #define GCDR(x)		__REG2(0x40300420, ((x) & 0x60) >> 3)
@@ -1488,8 +1489,8 @@ typedef void		(*ExcpHndlr) (void) ;
 #define GPIO79_nCS_3_MD		(79 | GPIO_ALT_FN_2_OUT)
 #define GPIO80_nCS_4_MD		(80 | GPIO_ALT_FN_2_OUT)
 
-#define GPIO117_SCL	     (117 | GPIO_ALT_FN_1_OUT)
-#define GPIO118_SDA	     (118 | GPIO_ALT_FN_1_OUT)
+#define GPIO117_SCL		(117 | GPIO_ALT_FN_1_OUT)
+#define GPIO118_SDA		(118 | GPIO_ALT_FN_1_OUT)
 
 /*
  * Power Manager
@@ -1709,10 +1710,10 @@ typedef void		(*ExcpHndlr) (void) ;
 #define ACCR_13MEND2	(1 << 21)
 #define ACCR_PCCE	(1 << 11)
 
-#define CKENA_30_MSL0	(1 << 30) 	/* MSL0 Interface Unit Clock Enable */
-#define CKENA_29_SSP4	(1 << 29) 	/* SSP3 Unit Clock Enable */
-#define CKENA_28_SSP3	(1 << 28) 	/* SSP2 Unit Clock Enable */
-#define CKENA_27_SSP2	(1 << 27)  	/* SSP1 Unit Clock Enable */
+#define CKENA_30_MSL0	(1 << 30)	/* MSL0 Interface Unit Clock Enable */
+#define CKENA_29_SSP4	(1 << 29)	/* SSP3 Unit Clock Enable */
+#define CKENA_28_SSP3	(1 << 28)	/* SSP2 Unit Clock Enable */
+#define CKENA_27_SSP2	(1 << 27)	/* SSP1 Unit Clock Enable */
 #define CKENA_26_SSP1	(1 << 26)	/* SSP0 Unit Clock Enable */
 #define CKENA_25_TSI	(1 << 25)	/* TSI Clock Enable */
 #define CKENA_24_AC97	(1 << 24)	/* AC97 Unit Clock Enable */
@@ -1720,27 +1721,27 @@ typedef void		(*ExcpHndlr) (void) ;
 #define CKENA_22_FFUART	(1 << 22)	/* FFUART Unit Clock Enable */
 #define CKENA_21_BTUART	(1 << 21)	/* BTUART Unit Clock Enable */
 #define CKENA_20_UDC	(1 << 20)	/* UDC Clock Enable */
-#define CKENA_19_TPM	(1 << 19) 	/* TPM Unit Clock Enable */
-#define CKENA_18_USIM1	(1 << 18) 	/* USIM1 Unit Clock Enable */
-#define CKENA_17_USIM0	(1 << 17) 	/* USIM0 Unit Clock Enable */
-#define CKENA_15_CIR	(1 << 15) 	/* Consumer IR Clock Enable */
-#define CKENA_14_KEY	(1 << 14) 	/* Keypad Controller Clock Enable */
-#define CKENA_13_MMC1	(1 << 13) 	/* MMC1 Clock Enable */
-#define CKENA_12_MMC0	(1 << 12) 	/* MMC0 Clock Enable */
-#define CKENA_11_FLASH	(1 << 11) 	/* Boot ROM Clock Enable */
-#define CKENA_10_SRAM	(1 << 10) 	/* SRAM Controller Clock Enable */
-#define CKENA_9_SMC	(1 << 9) 	/* Static Memory Controller */
-#define CKENA_8_DMC	(1 << 8) 	/* Dynamic Memory Controller */
-#define CKENA_7_GRAPHICS (1 << 7) 	/* 2D Graphics Clock Enable */
+#define CKENA_19_TPM	(1 << 19)	/* TPM Unit Clock Enable */
+#define CKENA_18_USIM1	(1 << 18)	/* USIM1 Unit Clock Enable */
+#define CKENA_17_USIM0	(1 << 17)	/* USIM0 Unit Clock Enable */
+#define CKENA_15_CIR	(1 << 15)	/* Consumer IR Clock Enable */
+#define CKENA_14_KEY	(1 << 14)	/* Keypad Controller Clock Enable */
+#define CKENA_13_MMC1	(1 << 13)	/* MMC1 Clock Enable */
+#define CKENA_12_MMC0	(1 << 12)	/* MMC0 Clock Enable */
+#define CKENA_11_FLASH	(1 << 11)	/* Boot ROM Clock Enable */
+#define CKENA_10_SRAM	(1 << 10)	/* SRAM Controller Clock Enable */
+#define CKENA_9_SMC	(1 << 9)	/* Static Memory Controller */
+#define CKENA_8_DMC	(1 << 8)	/* Dynamic Memory Controller */
+#define CKENA_7_GRAPHICS (1 << 7)	/* 2D Graphics Clock Enable */
 #define CKENA_6_USBCLI	(1 << 6)	/* USB Client Unit Clock Enable */
-#define CKENA_4_NAND	(1 << 4) 	/* NAND Flash Controller Clock Enable */
-#define CKENA_3_CAMERA	(1 << 3) 	/* Camera Interface Clock Enable */
+#define CKENA_4_NAND	(1 << 4)	/* NAND Flash Controller Clock Enable */
+#define CKENA_3_CAMERA	(1 << 3)	/* Camera Interface Clock Enable */
 #define CKENA_2_USBHOST	(1 << 2)	/* USB Host Unit Clock Enable */
 #define CKENA_1_LCD	(1 << 1)	/* LCD Unit Clock Enable */
 
 #define CKENB_8_1WIRE	((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */
-#define CKENB_7_GPIO	((1 << 7) + 32) 	/* GPIO Clock Enable */
-#define CKENB_6_IRQ	((1 << 6) + 32) 	/* Interrupt Controller Clock Enable */
+#define CKENB_7_GPIO	((1 << 7) + 32)	/* GPIO Clock Enable */
+#define CKENB_6_IRQ	((1 << 6) + 32)	/* Interrupt Controller Clock Enable */
 #define CKENB_4_I2C	((1 << 4) + 32)	/* I2C Unit Clock Enable */
 #define CKENB_1_PWM1	((1 << 1) + 32)	/* PWM2 & PWM3 Clock Enable */
 #define CKENB_0_PWM0	((1 << 0) + 32)	/* PWM0 & PWM1 Clock Enable */
@@ -2382,16 +2383,16 @@ typedef void		(*ExcpHndlr) (void) ;
 #define KPAS_SO		(0x1 << 31)
 #define KPASMKPx_SO	(0x1 << 31)
 
-#define GPIO113_BIT	   (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
-#define PSLR	   __REG(0x40F00034)
-#define PSTR	   __REG(0x40F00038)  /* Power Manager Standby Configuration Reg */
-#define PSNR	   __REG(0x40F0003C)  /* Power Manager Sense Configuration Reg */
-#define PVCR	   __REG(0x40F00040)  /* Power Manager Voltage Change Control Reg */
-#define PKWR	   __REG(0x40F00050)  /* Power Manager KB Wake-Up Enable Reg */
-#define PKSR	   __REG(0x40F00054)  /* Power Manager KB Level-Detect Status Reg */
-#define OSMR4	    __REG(0x40A00080)  /* */
-#define OSCR4	    __REG(0x40A00040)  /* OS Timer Counter Register */
-#define OMCR4	    __REG(0x40A000C0)  /* */
+#define GPIO113_BIT	(1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
+#define PSLR		__REG(0x40F00034)
+#define PSTR		__REG(0x40F00038)  /* Power Manager Standby Configuration Reg */
+#define PSNR		__REG(0x40F0003C)  /* Power Manager Sense Configuration Reg */
+#define PVCR		__REG(0x40F00040)  /* Power Manager Voltage Change Control Reg */
+#define PKWR		__REG(0x40F00050)  /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR		__REG(0x40F00054)  /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4		__REG(0x40A00080)  /* */
+#define OSCR4		__REG(0x40A00040)  /* OS Timer Counter Register */
+#define OMCR4		__REG(0x40A000C0)  /* */
 
 #endif	/* CONFIG_PXA27X */
 
diff --git a/include/configs/delta.h b/include/configs/delta.h
index f230b03..cb002f7 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -62,7 +62,7 @@
 /*
  * select serial console configuration
  */
-#define CONFIG_FFUART	       1
+#define CONFIG_FFUART		1
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -168,8 +168,6 @@
 
 #define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE }
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-#define SECTORSIZE 		512
-#define NAND_DELAY_US		25	/* mk@tbd: could be 0, I guess */
 
 /* nand timeout values */
 #define CFG_NAND_PROG_ERASE_TO	3000
@@ -178,16 +176,15 @@
 #undef NAND_ALLOW_ERASE_ALL	/* Allow erasing bad blocks - don't use */
 
 /* NAND Timing Parameters (in ns) */
-#define NAND_TIMING_tCH 	10
-#define NAND_TIMING_tCS 	0
+#define NAND_TIMING_tCH		10
+#define NAND_TIMING_tCS		0
 #define NAND_TIMING_tWH		20
-#define NAND_TIMING_tWP 	40
+#define NAND_TIMING_tWP		40
 
-#define NAND_TIMING_tRH 	20
-#define NAND_TIMING_tRP 	40
+#define NAND_TIMING_tRH		20
+#define NAND_TIMING_tRP		40
 
-#define NAND_TIMING_tR  	11123
-/* #define NAND_TIMING_tWHR	110 */
+#define NAND_TIMING_tR		11123
 #define NAND_TIMING_tWHR	100
 #define NAND_TIMING_tAR		10
 
@@ -199,87 +196,16 @@
 #define CONFIG_MTD_DEBUG
 #define CONFIG_MTD_DEBUG_VERBOSE 1
 
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
+#define ADDR_COLUMN		1
+#define ADDR_PAGE		2
+#define ADDR_COLUMN_PAGE	3
 
 #define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-#define CFG_NO_FLASH	1
-#ifndef CGF_NO_FLASH
-/* these are required by the environment code */
-#define PHYS_FLASH_1            CFG_NAND0_BASE /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE         0x04000000 /* 64 MB */
-#define PHYS_FLASH_BANK_SIZE    0x04000000 /* 64 MB Banks */
-#define PHYS_FLASH_SECT_SIZE    (SECTORSIZE*1024) /*  KB sectors (x2) */
-#endif
+#define NAND_MAX_FLOORS		1
+#define NAND_MAX_CHIPS		1
 
-/*
- * GPIO settings
- */
-#define CFG_GPSR0_VAL		0x00008000
-#define CFG_GPSR1_VAL		0x00FC0382
-#define CFG_GPSR2_VAL		0x0001FFFF
-#define CFG_GPCR0_VAL		0x00000000
-#define CFG_GPCR1_VAL		0x00000000
-#define CFG_GPCR2_VAL		0x00000000
-#define CFG_GPDR0_VAL		0x0060A800
-#define CFG_GPDR1_VAL		0x00FF0382
-#define CFG_GPDR2_VAL		0x0001C000
-#define CFG_GAFR0_L_VAL		0x98400000
-#define CFG_GAFR0_U_VAL		0x00002950
-#define CFG_GAFR1_L_VAL		0x000A9558
-#define CFG_GAFR1_U_VAL		0x0005AAAA
-#define CFG_GAFR2_L_VAL		0xA0000000
-#define CFG_GAFR2_U_VAL		0x00000002
-
-#define CFG_PSSR_VAL		0x20
-
-/*
- * Memory settings
- */
-#define CFG_MSC0_VAL		0x23F223F2
-#define CFG_MSC1_VAL		0x3FF1A441
-#define CFG_MSC2_VAL		0x7FF97FF1
-#define CFG_MDCNFG_VAL		0x00001AC9
-#define CFG_MDREFR_VAL		0x00018018
-#define CFG_MDMRS_VAL		0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CFG_MECR_VAL		0x00000000
-#define CFG_MCMEM0_VAL		0x00010504
-#define CFG_MCMEM1_VAL		0x00010504
-#define CFG_MCATT0_VAL		0x00010504
-#define CFG_MCATT1_VAL		0x00010504
-#define CFG_MCIO0_VAL		0x00004715
-#define CFG_MCIO1_VAL		0x00004715
-
-#define _LED			0x08000010
-#define LED_BLANK		0x08000040
-
-/*
- * FLASH and environment organization
- */
-#ifndef CFG_NO_FLASH
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
-
-/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
-
-
-/* NOTE: many default partitioning schemes assume the kernel starts at the
- * second sector, not an environment.  You have been warned!
- */
-#define	CFG_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
-#endif /* #ifndef CFG_NO_FLASH */
+#define CFG_NO_FLASH		1
 
-/* #define CFG_ENV_IS_NOWHERE */
 #define CFG_ENV_IS_IN_NAND	1
 #define CFG_ENV_OFFSET		0x40000
 #define CFG_ENV_OFFSET_REDUND	0x44000
-- 
cgit v1.1


From 5725f94aace1ed75bbeb9f3c528f34d1ae4dbe69 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue, 21 Mar 2006 01:58:07 +0100
Subject: Cleanup MCC200 board configuration; omit non-existent stuff.

---
 include/configs/mcc200.h | 25 +++----------------------
 1 file changed, 3 insertions(+), 22 deletions(-)

(limited to 'include')

diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index d4dee3b..b9b54eb 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -67,13 +67,8 @@
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				ADD_USB_CMD	| \
 				CFG_CMD_BEDBUG	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_EEPROM	| \
 				CFG_CMD_FAT	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_SNTP	)
+				CFG_CMD_I2C)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -131,26 +126,12 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
 
 #define CFG_I2C_SPEED		100000 /* 100 kHz */
 #define CFG_I2C_SLAVE		0x7F
 
 /*
- * EEPROM configuration
- */
-#define CFG_I2C_EEPROM_ADDR		0x58
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
-
-/*
  * Flash configuration (8,16 or 32 MB)
  * TEXT base always at 0xFFF00000
  * ENV_ADDR always at  0xFFF40000
@@ -231,7 +212,7 @@
  */
 /* 0x10000004 = 32MB SDRAM */
 /* 0x90000004 = 64MB SDRAM */
-#define CFG_GPS_PORT_CONFIG	0x10000004
+#define CFG_GPS_PORT_CONFIG	0x00000004
 
 /*
  * Miscellaneous configurable options
-- 
cgit v1.1


From 05d8dce9d07cf4073ea15fbc448c1ce22b6baf0f Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Thu, 23 Mar 2006 17:10:30 +0100
Subject: Enable Quad UART om MCC200 board.

---
 include/configs/mcc200.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'include')

diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index b9b54eb..67c2483 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -247,6 +247,11 @@
 #define CFG_CS0_START		CFG_FLASH_BASE
 #define CFG_CS0_SIZE		CFG_FLASH_SIZE
 
+/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
+#define CFG_CS2_START		0x80000000
+#define CFG_CS2_SIZE		0x00001000
+#define CFG_CS2_CFG		0x1d800
+
 #define CFG_CS_BURST		0x00000000
 #define CFG_CS_DEADCYCLE	0x33333333
 
-- 
cgit v1.1


From ba70d6a4170ebbec5513f01ceae66a200102ba9a Mon Sep 17 00:00:00 2001
From: Markus Klotzbuecher <mk@denx.de>
Date: Fri, 24 Mar 2006 12:23:27 +0100
Subject: delta board: DA9030 initialization and i2c support. Some minor
 changes to make the pxa i2c driver work with the monahans cpu.

---
 include/asm-arm/arch-pxa/pxa-regs.h |   6 +-
 include/configs/delta.h             |  18 ++++--
 include/da9030.h                    | 106 ++++++++++++++++++++++++++++++++++++
 3 files changed, 123 insertions(+), 7 deletions(-)
 create mode 100644 include/da9030.h

(limited to 'include')

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index a92a450..ebda719 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -475,11 +475,11 @@ typedef void		(*ExcpHndlr) (void) ;
 #define ICR_ACKNAK	0x4		/* send ACK(0) or NAK(1) */
 #define ICR_TB		0x8		/* transfer byte bit */
 #define ICR_MA		0x10		/* master abort */
-#define ICR_SCLE	0x20		/* master clock enable */
+#define ICR_SCLE	0x20		/* master clock enable, mona SCLEA */
 #define ICR_IUE		0x40		/* unit enable */
 #define ICR_GCD		0x80		/* general call disable */
 #define ICR_ITEIE	0x100		/* enable tx interrupts */
-#define ICR_IRFIE	0x200		/* enable rx interrupts */
+#define ICR_IRFIE	0x200		/* enable rx interrupts, mona: DRFIE */
 #define ICR_BEIE	0x400		/* enable bus error ints */
 #define ICR_SSDIE	0x800		/* slave STOP detected int enable */
 #define ICR_ALDIE	0x1000		/* enable arbitration interrupt */
@@ -923,7 +923,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define ICHP		__REG(0x40D00018)  /* Interrupt Controller Highest Priority Register */
 /* Missing: 32 Interrupt priority registers
  * These are the same as beneath for PXA27x: maybe can be merged if
- * GPIO Stuff is same too. 
+ * GPIO Stuff is same too.
  */
 #define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
 #define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
diff --git a/include/configs/delta.h b/include/configs/delta.h
index cb002f7..eaa4c43 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -49,7 +49,6 @@
 /*
  * Hardware drivers
  */
-
 #undef TURN_ON_ETHERNET
 #ifdef TURN_ON_ETHERNET
 # define CONFIG_DRIVER_SMC91111 1
@@ -59,6 +58,12 @@
 # undef CONFIG_SMC_USE_IOFUNCS          /* just for use with the kernel */
 #endif
 
+#define CONFIG_HARD_I2C		1	/* required for DA9030 access */
+#define CFG_I2C_SPEED		400000	/* I2C speed */
+#define CFG_I2C_SLAVE		1	/* I2C controllers address */
+#define DA9030_I2C_ADDR		0x49	/* I2C address of DA9030 */
+/* #define CONFIG_HW_WATCHDOG	1	/\* Required for hitting the DA9030 WD *\/ */
+
 /*
  * select serial console configuration
  */
@@ -73,8 +78,13 @@
 #ifdef TURN_ON_ETHERNET
 # define CONFIG_COMMANDS        (CONFIG_CMD_DFL | CFG_CMD_PING)
 #else
-# define CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \
-				& ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS))
+# define CONFIG_COMMANDS	((CONFIG_CMD_DFL \
+				  | CFG_CMD_ENV \
+				  | CFG_CMD_NAND \
+				  | CFG_CMD_I2C) \
+				 & ~(CFG_CMD_NET \
+				     | CFG_CMD_FLASH \
+				     | CFG_CMD_IMLS))
 #endif
 
 
@@ -121,7 +131,7 @@
 
 #define CFG_LOAD_ADDR	(CFG_DRAM_BASE + 0x8000) /* default load address */
 
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_HZ			3250000		/* incrementer freq: 3.25 MHz */
 #define CFG_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
 
 						/* valid baudrates */
diff --git a/include/da9030.h b/include/da9030.h
new file mode 100644
index 0000000..41108b9
--- /dev/null
+++ b/include/da9030.h
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* DA9030 register definitions */
+#define CID			0x00
+#define EVENT_A			0x01
+#define EVENT_B			0x02
+#define EVENT_C			0x03
+#define STATUS			0x04
+#define IRQ_MASK_A		0x05
+#define IRQ_MASK_B		0x06
+#define IRQ_MASK_C		0x07
+#define SYS_CONTROL_A		0x08
+#define SYS_CONTROL_B		0x09
+#define FAULT_LOG		0x0A
+#define LDO_10_11		0x10
+#define LDO_15			0x11
+#define LDO_14_16		0x12
+#define LDO_18_19		0x13
+#define LDO_17_SIMCP0		0x14
+#define BUCK2_DVC1		0x15
+#define BUCK2_DVC2		0x16
+#define REG_CONTROL_1_17	0x17
+#define REG_CONTROL_2_18	0x18
+#define USBPUMP			0x19
+#define SLEEP_CONTROL		0x1A
+#define STARTUP_CONTROL		0x1B
+#define LED1_CONTROL		0x20
+#define LED2_CONTROL		0x21
+#define LED3_CONTROL		0x22
+#define LED4_CONTROL		0x23
+#define LEDPC_CONTROL		0x24
+#define WLED_CONTROL		0x25
+#define MISC_CONTROLA		0x26
+#define MISC_CONTROLB		0x27
+#define CHARGE_CONTROL		0x28
+#define CCTR_CONTROL		0x29
+#define TCTR_CONTROL		0x2A
+#define CHARGE_PULSE		0x2B
+
+/* ... some missing ...*/
+
+#define LDO1			0x90
+#define LDO2_3			0x91
+#define LDO4_5			0x92
+#define LDO6_SIMCP		0x93
+#define LDO7_8			0x94
+#define LDO9_12			0x95
+#define BUCK			0x96
+#define REG_CONTROL_1_97	0x97
+#define REG_CONTROL_2_98	0x98
+#define REG_SLEEP_CONTROL1	0x99
+#define REG_SLEEP_CONTROL2	0x9A
+#define REG_SLEEP_CONTROL3	0x9B
+#define ADC_MAN_CONTROL		0xA0
+#define ADC_AUTO_CONTROL	0xA1
+#define VBATMON			0xA2
+#define VBATMONTXMON		0xA3
+#define TBATHIGHP		0xA4
+#define TBATHIGHN		0xA5
+#define TBATLOW			0xA6
+#define MAN_RES			0xB0
+#define VBAT_RES		0xB1
+#define VBATMIN_RES		0xB2
+#define VBATMINTXON_RES		0xB3
+#define ICHMAX_RES		0xB4
+#define ICHMIN_RES		0xB5
+#define ICHAVERAGE_RES		0xB6
+#define VCHMAX_RES		0xB7
+#define VCHMIN_RES		0xB8
+#define TBAT_RES		0xB9
+#define ADC_IN4_RES		0xBA
+
+#define STATUS_ONKEY_N		0x1	/* current ONKEY_N value */
+#define STATUS_PWREN1		(1<<1)	/* PWREN1 value */
+#define STATUS_EXTON		(1<<2)	/* EXTON value */
+#define STATUS_CHDET		(1<<3)	/* Charger detection status */
+#define STATUS_TBAT		(1<<4)	/* Battery over/under temperature status */
+#define STATUS_VBATMON		(1<<5)	/* VBATMON comparison status */
+#define STATUS_VBATMONTXON	(1<<6)	/* VBATMONTXON comparison status */
+#define STATUS_CHIOVER		(1<<7)	/* Charge overcurrent */
+
+#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE	0x1
+#define SYS_CONTROL_A_SHUT_DOWN			(1<<1)
+#define SYS_CONTROL_A_HWRES_ENABLE		(1<<2)
+#define SYS_CONTROL_A_WDOG_ACTION		(1<<3)
+#define SYS_CONTROL_A_WATCHDOG			(1<<7)
-- 
cgit v1.1


From 40b0bafbb282a8fd2d705be0623948ff551bf26a Mon Sep 17 00:00:00 2001
From: Markus Klotzbuecher <mk@denx.de>
Date: Fri, 24 Mar 2006 14:35:25 +0100
Subject: Added config options CFG_MONAHANS_RUN_MODE_OSC_RATIO and
 CFG_MONAHANS_TURBO_RUN_MODE_RATIO for configuring the Monahans core
 frequency.

---
 include/configs/delta.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/delta.h b/include/configs/delta.h
index eaa4c43..776ee15 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -132,7 +132,13 @@
 #define CFG_LOAD_ADDR	(CFG_DRAM_BASE + 0x8000) /* default load address */
 
 #define CFG_HZ			3250000		/* incrementer freq: 3.25 MHz */
-#define CFG_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
+
+/* Monahans Core Frequency = 
+ * 
+ */
+#define CFG_MONAHANS_RUN_MODE_OSC_RATIO		16 /* valid values: 8, 16, 24, 31 */
+#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO	1  /* valid values: 1, 2 */
+
 
 						/* valid baudrates */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-- 
cgit v1.1


From c855ef6768cf9cb0bc12f4965592dcd5f353686a Mon Sep 17 00:00:00 2001
From: Markus Klotzbuecher <mk@denx.de>
Date: Mon, 27 Mar 2006 16:01:03 +0200
Subject: delta board: fix DA9030 reset procedure.

---
 include/configs/delta.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

(limited to 'include')

diff --git a/include/configs/delta.h b/include/configs/delta.h
index 776ee15..6329c25 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -62,6 +62,7 @@
 #define CFG_I2C_SPEED		400000	/* I2C speed */
 #define CFG_I2C_SLAVE		1	/* I2C controllers address */
 #define DA9030_I2C_ADDR		0x49	/* I2C address of DA9030 */
+#define CFG_DA9030_EXTON_DELAY	0	/* wait x us after DA9030 reset via EXTON */
 /* #define CONFIG_HW_WATCHDOG	1	/\* Required for hitting the DA9030 WD *\/ */
 
 /*
@@ -133,9 +134,7 @@
 
 #define CFG_HZ			3250000		/* incrementer freq: 3.25 MHz */
 
-/* Monahans Core Frequency = 
- * 
- */
+/* Monahans Core Frequency */
 #define CFG_MONAHANS_RUN_MODE_OSC_RATIO		16 /* valid values: 8, 16, 24, 31 */
 #define CFG_MONAHANS_TURBO_RUN_MODE_RATIO	1  /* valid values: 1, 2 */
 
-- 
cgit v1.1


From b66a9383421805c705654ce9456ec28c202819fb Mon Sep 17 00:00:00 2001
From: Rafal Jaworowski <raj@pollux.denx.de>
Date: Wed, 29 Mar 2006 13:17:09 +0200
Subject: Set SDelay register in the DDR controller for the MPC5200B chip.

---
 include/configs/IceCube.h | 8 +++++---
 include/mpc5xxx.h         | 1 +
 2 files changed, 6 insertions(+), 3 deletions(-)

(limited to 'include')

diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 596e52c..1152f83 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -56,7 +56,9 @@
  * 0x40000000 - 0x4fffffff - PCI Memory
  * 0x50000000 - 0x50ffffff - PCI IO Space
  */
-#define CONFIG_PCI		1
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
 #define CONFIG_PCI_PNP		1
 #define CONFIG_PCI_SCAN_SHOW	1
 
@@ -67,6 +69,8 @@
 #define CONFIG_PCI_IO_BUS	0x50000000
 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE	0x01000000
+#define ADD_PCI_CMD 		CFG_CMD_PCI
+#endif
 
 #define CFG_XLB_PIPELINING	1
 
@@ -76,8 +80,6 @@
 #define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 
-#define ADD_PCI_CMD 		CFG_CMD_PCI
-
 #else	/* MPC5100 */
 
 #define CONFIG_MII		1
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index f33d858..50a6ac1 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -131,6 +131,7 @@
 #if defined(CONFIG_MGT5100)
 #define MPC5XXX_SDRAM_XLBSEL	(MPC5XXX_SDRAM + 0x0010)
 #endif
+#define MPC5XXX_SDRAM_SDELAY	(MPC5XXX_SDRAM + 0x0090)
 
 /* Clock Distribution Module */
 #define MPC5XXX_CDM_JTAGID	(MPC5XXX_CDM + 0x0000)
-- 
cgit v1.1


From 89f2dfa4c349ae3b040779ac0ab1c9baa1ef025d Mon Sep 17 00:00:00 2001
From: Markus Klotzbuecher <mk@denx.de>
Date: Wed, 29 Mar 2006 17:49:27 +0200
Subject: delta board: minor update to DA9030 code.

---
 include/configs/delta.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/delta.h b/include/configs/delta.h
index 6329c25..f2e0a8c 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -62,7 +62,7 @@
 #define CFG_I2C_SPEED		400000	/* I2C speed */
 #define CFG_I2C_SLAVE		1	/* I2C controllers address */
 #define DA9030_I2C_ADDR		0x49	/* I2C address of DA9030 */
-#define CFG_DA9030_EXTON_DELAY	0	/* wait x us after DA9030 reset via EXTON */
+#define CFG_DA9030_EXTON_DELAY	100000	/* wait x us after DA9030 reset via EXTON */
 /* #define CONFIG_HW_WATCHDOG	1	/\* Required for hitting the DA9030 WD *\/ */
 
 /*
-- 
cgit v1.1


From eeaab720f66f0281b9a1ea3c1f8765bf34e4411e Mon Sep 17 00:00:00 2001
From: Markus Klotzbuecher <mk@denx.de>
Date: Wed, 29 Mar 2006 17:59:20 +0200
Subject: Change delta board memory map to start at 0x80000000.

---
 include/configs/delta.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'include')

diff --git a/include/configs/delta.h b/include/configs/delta.h
index f2e0a8c..053a8f7 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -125,8 +125,8 @@
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CFG_DEVICE_NULLDEV	1
 
-#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+#define CFG_MEMTEST_START	0x80400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x80800000	/* 4 ... 8 MB in DRAM	*/
 
 #undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
@@ -159,16 +159,16 @@
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1		0x80000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x1000000  /* 64 MB */
-#define PHYS_SDRAM_2		0xa1000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2		0x81000000 /* SDRAM Bank #2 */
 #define PHYS_SDRAM_2_SIZE	0x1000000  /* 64 MB */
-#define PHYS_SDRAM_3		0xa2000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3		0x82000000 /* SDRAM Bank #3 */
 #define PHYS_SDRAM_3_SIZE	0x1000000  /* 64 MB */
-#define PHYS_SDRAM_4		0xa3000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4		0x83000000 /* SDRAM Bank #4 */
 #define PHYS_SDRAM_4_SIZE	0x1000000  /* 64 MB */
 
-#define CFG_DRAM_BASE		0xa0000000 /* at CS0 */
+#define CFG_DRAM_BASE		0x80000000 /* at CS0 */
 #define CFG_DRAM_SIZE		0x04000000 /* 64 MB Ram */
 
 #undef CFG_SKIP_DRAM_SCRUB
-- 
cgit v1.1


From f2841d377060cb2c3bedfcdfda6aab3066d6c4f1 Mon Sep 17 00:00:00 2001
From: Markus Klotzbuecher <mk@denx.de>
Date: Thu, 30 Mar 2006 13:40:55 +0200
Subject: Add support for ymodem protocol (loady command). Patch by Stefano
 Babic, 29 Mar 2006

---
 include/crc.h      | 101 +++++++++++++++++++++++++++++++++++++++++++++++
 include/xyzModem.h | 112 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 213 insertions(+)
 create mode 100644 include/crc.h
 create mode 100644 include/xyzModem.h

(limited to 'include')

diff --git a/include/crc.h b/include/crc.h
new file mode 100644
index 0000000..63399bf
--- /dev/null
+++ b/include/crc.h
@@ -0,0 +1,101 @@
+//==========================================================================
+//
+//      crc.h
+//
+//      Interface for the CRC algorithms.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2002 Andrew Lunn
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    Andrew Lunn
+// Contributors: Andrew Lunn
+// Date:         2002-08-06
+// Purpose:      
+// Description:  
+//              
+// This code is part of eCos (tm).
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#ifndef _SERVICES_CRC_CRC_H_
+#define _SERVICES_CRC_CRC_H_
+
+#include <linux/types.h>
+
+#ifndef __externC
+# ifdef __cplusplus
+#  define __externC extern "C"
+# else
+#  define __externC extern
+# endif
+#endif
+
+// Compute a CRC, using the POSIX 1003 definition
+extern uint32_t 
+cyg_posix_crc32(unsigned char *s, int len);
+
+// Gary S. Brown's 32 bit CRC
+
+extern uint32_t 
+cyg_crc32(unsigned char *s, int len);
+
+// Gary S. Brown's 32 bit CRC, but accumulate the result from a
+// previous CRC calculation
+
+extern uint32_t 
+cyg_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
+
+// Ethernet FCS Algorithm
+
+extern uint32_t 
+cyg_ether_crc32(unsigned char *s, int len);
+
+// Ethernet FCS algorithm, but accumulate the result from a previous
+// CRC calculation.
+
+extern uint32_t 
+cyg_ether_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
+
+// 16 bit CRC with polynomial x^16+x^12+x^5+1
+
+extern uint16_t cyg_crc16(unsigned char *s, int len);
+
+#endif // _SERVICES_CRC_CRC_H_
+
+
+
diff --git a/include/xyzModem.h b/include/xyzModem.h
new file mode 100644
index 0000000..a62a174
--- /dev/null
+++ b/include/xyzModem.h
@@ -0,0 +1,112 @@
+//==========================================================================
+//
+//      xyzModem.h
+//
+//      RedBoot stream handler for xyzModem protocol
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2000-07-14
+// Purpose:      
+// Description:  
+//              
+// This code is part of RedBoot (tm).
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#ifndef _XYZMODEM_H_
+#define _XYZMODEM_H_
+
+#define xyzModem_xmodem 1
+#define xyzModem_ymodem 2
+// Don't define this until the protocol support is in place
+//#define xyzModem_zmodem 3
+
+#define xyzModem_access   -1
+#define xyzModem_noZmodem -2
+#define xyzModem_timeout  -3
+#define xyzModem_eof      -4
+#define xyzModem_cancel   -5
+#define xyzModem_frame    -6
+#define xyzModem_cksum    -7
+#define xyzModem_sequence -8
+
+#define xyzModem_close 1
+#define xyzModem_abort 2
+
+
+#ifdef REDBOOT
+extern getc_io_funcs_t xyzModem_io;
+#else
+#define CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT
+#define CYGACC_CALL_IF_SET_CONSOLE_COMM(x)
+
+#define diag_vprintf vprintf
+#define diag_printf printf
+#define diag_vsprintf vsprintf
+
+#define CYGACC_CALL_IF_DELAY_US(x) udelay(x)
+
+typedef struct {
+    char *filename;
+    int   mode;
+    int   chan;
+#ifdef CYGPKG_REDBOOT_NETWORKING
+    struct sockaddr_in *server;
+#endif
+} connection_info_t;
+
+typedef unsigned int bool;
+
+#define false 0
+#define true 1
+
+#endif
+
+
+int   xyzModem_stream_open(connection_info_t *info, int *err);    
+void  xyzModem_stream_close(int *err);    
+void  xyzModem_stream_terminate(bool method, int (*getc)(void));    
+int   xyzModem_stream_read(char *buf, int size, int *err);    
+char *xyzModem_error(int err);
+
+#endif // _XYZMODEM_H_
-- 
cgit v1.1


From 9e7b5ce61b2641e726a38505ffc077642bff44fa Mon Sep 17 00:00:00 2001
From: Markus Klotzbuecher <mk@denx.de>
Date: Thu, 30 Mar 2006 17:00:39 +0200
Subject: delta board: one more DA9030 fix.

---
 include/configs/delta.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/configs/delta.h b/include/configs/delta.h
index 053a8f7..5edea95 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -63,6 +63,7 @@
 #define CFG_I2C_SLAVE		1	/* I2C controllers address */
 #define DA9030_I2C_ADDR		0x49	/* I2C address of DA9030 */
 #define CFG_DA9030_EXTON_DELAY	100000	/* wait x us after DA9030 reset via EXTON */
+#define CFG_I2C_INIT_BOARD	1
 /* #define CONFIG_HW_WATCHDOG	1	/\* Required for hitting the DA9030 WD *\/ */
 
 /*
-- 
cgit v1.1


From 62534beb2fdd67490c3723f22b8982e7d64fc104 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 17 Mar 2006 10:28:24 +0100
Subject: Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)

405 SDRAM: - The SDRAM parameters can now be defined in the board
             config file and the 405 SDRAM controller values will
             be calculated upon bootup (see PPChameleonEVB).
             When those settings are not defined in the board
             config file, the register setup will be as it is now,
             so this implementation should not break any current
             design using this code.

             Thanks to Andrea Marson from DAVE for this patch.

440 DDR:   - Added function sdram_tr1_set to auto calculate the
             TR1 value for the DDR.
           - Added ECC support (see p3p440).

Patch by Stefan Roese, 17 Mar 2006
---
 include/configs/PPChameleonEVB.h | 10 ++++++++++
 include/configs/p3p440.h         | 12 ++++++++----
 2 files changed, 18 insertions(+), 4 deletions(-)

(limited to 'include')

diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index e1155e2..16e2cc6 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -139,8 +139,18 @@
 #define CFG_I2C_RTC_ADDR	0x68
 #define CFG_M41T11_BASE_YEAR	1900
 
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
+/* SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL            2
+#define CFG_SDRAM_tRP           20
+#define CFG_SDRAM_tRC           65
+#define CFG_SDRAM_tRCD          20
+#undef  CFG_SDRAM_tRFC
+
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index 831d018..0662544 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2006
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
@@ -71,9 +71,10 @@
  * DDR SDRAM
  *----------------------------------------------------------------------*/
 #define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0*/
-#define CFG_SDRAM_TABLE	{	\
-		{(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */	\
-		{(64 << 20),  0x00082001}} /* 64MB mode 2, 12x9(4)   */
+#define CONFIG_SDRAM_ECC		/* enable ECC support		*/
+#define CFG_SDRAM_TABLE	{ \
+		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
+		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -275,6 +276,9 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_PROTECTION	1	/* hardware flash protection		*/
+
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 #define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
-- 
cgit v1.1


From 2662b40cace272da5759040622561d821c878d56 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Sat, 1 Apr 2006 13:41:03 +0200
Subject: * Changes/fixes for drivers/cfi_flash.c:

  - Add Intel legacy lock/unlock support to common CFI driver

    On some Intel flash's (e.g. Intel J3) legacy unlocking is
    supported, meaning that unlocking of one sector will unlock
    all sectors of this bank. Using this feature, unlocking
    of all sectors upon startup (via env var "unlock=yes") will
    get much faster.

  - Fixed problem with multiple reads of envronment variable
    "unlock" as pointed out by Reinhard Arlt & Anders Larsen.

  - Removed unwanted linefeeds from "protect" command when
    CFG_FLASH_PROTECTION is enabled.

  - Changed p3p400 board to use CFG_FLASH_PROTECTION

  Patch by Stefan Roese, 01 Apr 2006

* Changes/fixes for drivers/cfi_flash.c:
  - Correctly handle the cases where CFG_HZ != 1000 (several
    XScale-based boards)
  - Fix the timeout calculation of buffered writes (off by a
    factor of 1000)
  Patch by Anders Larsen, 31 Mar 2006
---
 include/configs/p3p440.h | 4 ++++
 include/flash.h          | 1 +
 2 files changed, 5 insertions(+)

(limited to 'include')

diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index 831d018..19656fc 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -146,6 +146,7 @@
 		"cp.b 100000 fffc0000 40000;"			        \
 		"setenv filesize;saveenv\0"				\
 	"upd=run load;run update\0"					\
+	"unlock=yes\0"							\
 	""
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
 
@@ -275,6 +276,9 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
+#define CFG_FLASH_PROTECTION	1	   /* use hardware protection		*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	   /* use buffered writes (20x faster)	*/
+
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 #define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
diff --git a/include/flash.h b/include/flash.h
index 4c68c68..a84dc68 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -45,6 +45,7 @@ typedef struct {
 	ushort	vendor;			/* the primary vendor id		*/
 	ushort	cmd_reset;		/* Vendor specific reset command	*/
 	ushort	interface;		/* used for x8/x16 adjustments		*/
+	ushort	legacy_unlock;		/* support Intel legacy (un)locking	*/
 #endif
 } flash_info_t;
 
-- 
cgit v1.1


From 2fc000d756920b340945a74ec1214a34d9e84858 Mon Sep 17 00:00:00 2001
From: Marian Balakowicz <m8@semihalf.com>
Date: Wed, 5 Apr 2006 20:46:41 +0200
Subject: Remove dependencies between DoC code and old legacy NAND driver.
 Necessary defines and data structures were copied to DoC specific files so
 that legacy NAND code could be entirely removed from u-boot tree in the near
 future.

---
 include/linux/mtd/doc2000.h | 65 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

(limited to 'include')

diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
index ebf9a76..eeb1d7e 100644
--- a/include/linux/mtd/doc2000.h
+++ b/include/linux/mtd/doc2000.h
@@ -91,6 +91,13 @@ struct DiskOnChip;
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
+struct Nand {
+	char floor, chip;
+	unsigned long curadr;
+	unsigned char curmode;
+	/* Also some erase/write/pipeline info when we get that far */
+};
+
 struct DiskOnChip {
 	unsigned long physadr;
 	unsigned long virtadr;
@@ -148,4 +155,62 @@ void doc_probe(unsigned long physadr);
 
 void doc_print(struct DiskOnChip*);
 
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0		0
+#define NAND_CMD_READ1		1
+#define NAND_CMD_PAGEPROG	0x10
+#define NAND_CMD_READOOB	0x50
+#define NAND_CMD_ERASE1		0x60
+#define NAND_CMD_STATUS		0x70
+#define NAND_CMD_SEQIN		0x80
+#define NAND_CMD_READID		0x90
+#define NAND_CMD_ERASE2		0xd0
+#define NAND_CMD_RESET		0xff
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA	0x98
+#define NAND_MFR_SAMSUNG	0xec
+
+/*
+ * NAND Flash Device ID Structure
+ *
+ * Structure overview:
+ *
+ *  name - Complete name of device
+ *
+ *  manufacture_id - manufacturer ID code of device.
+ *
+ *  model_id - model ID code of device.
+ *
+ *  chipshift - total number of address bits for the device which
+ *              is used to calculate address offsets and the total
+ *              number of bytes the device is capable of.
+ *
+ *  page256 - denotes if flash device has 256 byte pages or not.
+ *
+ *  pageadrlen - number of bytes minus one needed to hold the
+ *               complete address into the flash array. Keep in
+ *               mind that when a read or write is done to a
+ *               specific address, the address is input serially
+ *               8 bits at a time. This structure member is used
+ *               by the read/write routines as a loop index for
+ *               shifting the address out 8 bits at a time.
+ *
+ *  erasesize - size of an erase block in the flash device.
+ */
+struct nand_flash_dev {
+	char * name;
+	int manufacture_id;
+	int model_id;
+	int chipshift;
+	char page256;
+	char pageadrlen;
+	unsigned long erasesize;
+	int bus16;
+};
+
 #endif /* __MTD_DOC2000_H__ */
-- 
cgit v1.1


From 6db39708117d6391a72f3fc3ea7860231b630270 Mon Sep 17 00:00:00 2001
From: Marian Balakowicz <m8@semihalf.com>
Date: Sat, 8 Apr 2006 19:08:06 +0200
Subject: Fix JFFS2 support for legacy NAND driver.

Some more NAND cleanup and small fixes.
---
 include/configs/CATcenter.h  | 19 ++++++++++---------
 include/configs/CPU86.h      |  2 --
 include/configs/IDS8247.h    |  1 +
 include/configs/NC650.h      |  2 ++
 include/configs/NETTA.h      |  1 +
 include/configs/RBC823.h     |  2 --
 include/configs/VCMA9.h      |  1 +
 include/configs/delta.h      |  3 ++-
 include/configs/omap2420h4.h |  1 +
 include/configs/stxxtc.h     |  1 +
 10 files changed, 19 insertions(+), 14 deletions(-)

(limited to 'include')

diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index ffe89cb..7ec4599 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -193,6 +193,8 @@
  */
 #define CFG_NAND0_BASE 0xFF400000
 #define CFG_NAND1_BASE 0xFF000000
+#define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE }
+#define NAND_BIG_DELAY_US	25
 
 /* For CATcenter there is only NAND on the module */
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
@@ -218,9 +220,9 @@
 #define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 
 
-#define NAND_DISABLE_CE(nand) do \
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
 { \
-	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+	switch((unsigned long)nandptr) \
 	{ \
 	    case CFG_NAND0_BASE: \
 		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
@@ -231,9 +233,9 @@
 	} \
 } while(0)
 
-#define NAND_ENABLE_CE(nand) do \
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
 { \
-	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+	switch((unsigned long)nandptr) \
 	{ \
 	    case CFG_NAND0_BASE: \
 		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
@@ -244,8 +246,7 @@
 	} \
 } while(0)
 
-
-#define NAND_CTL_CLRALE(nandptr) do \
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
 { \
 	switch((unsigned long)nandptr) \
 	{ \
@@ -258,7 +259,7 @@
 	} \
 } while(0)
 
-#define NAND_CTL_SETALE(nandptr) do \
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
 { \
 	switch((unsigned long)nandptr) \
 	{ \
@@ -271,7 +272,7 @@
 	} \
 } while(0)
 
-#define NAND_CTL_CLRCLE(nandptr) do \
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
 { \
 	switch((unsigned long)nandptr) \
 	{ \
@@ -284,7 +285,7 @@
 	} \
 } while(0)
 
-#define NAND_CTL_SETCLE(nandptr) do { \
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
 	switch((unsigned long)nandptr) { \
 	case CFG_NAND0_BASE: \
 		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 1e9a99e..16a9ea5 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -178,8 +178,6 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-#define CFG_NAND_LEGACY
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index aaa44c5..29eb874 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -236,6 +236,7 @@
  */
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 
+#define CFG_NAND_LEGACY
 #define CFG_NAND0_BASE 0xE1000000
 
 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 371ea17..3c59df4 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -217,6 +217,8 @@
 /*
  * NAND flash support
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE	1
 #define NAND_ChipID_UNKNOWN	0x00
 #define SECTORSIZE		512
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 1bcd88d..25b6345 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -609,6 +609,7 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE			NAND_BASE
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_MTD_NAND_UNSAFE
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index 21945a3..242c837 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -326,8 +326,6 @@
 /************************************************************
  * Disk-On-Chip configuration
  ************************************************************/
-#define CFG_NAND_LEGACY
-
 #define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
 #define CFG_DOC_SHORT_TIMEOUT
 #define CFG_DOC_SUPPORT_2000
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 3f29190..5f48a70 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -248,6 +248,7 @@
  */
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 
+#define CFG_NAND_LEGACY
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
diff --git a/include/configs/delta.h b/include/configs/delta.h
index b42a7e2..31feaa3 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -162,7 +162,8 @@
  * NAND Flash
  */
 /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
-#define CONFIG_NEW_NAND_CODE
+#undef CFG_NAND_LEGACY
+
 #define CFG_NAND0_BASE		0x0 /* 0x43100040 */ /* 0x10000000 */
 #undef CFG_NAND1_BASE
 
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 12252ac..5837461 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -132,6 +132,7 @@
 /*
  *  Board NAND Info.
  */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_ADDR 0x04000000  /* physical address to access nand at CS0*/
 
 #define CFG_MAX_NAND_DEVICE 1	/* Max number of NAND devices */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index be6c36c..614a046 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -436,6 +436,7 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE		NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE
-- 
cgit v1.1


From ad88297e2f14220f34417d1304d256285887aed4 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@pollux.denx.de>
Date: Tue, 11 Apr 2006 14:53:29 +0200
Subject: * Fix dbau1x00 Board   - Fix dbau1x00 boards broken by dbau1550 patch
     PLL:s were not set for boards other than 1550.     Flash CFI caused card
 to hang due to undefined CFG_FLASH_BANKS_LIST.     Default boot is now bootp
 for cards other than 1550.   Patch by Thomas Lange Aug 10 2005

---
 include/configs/dbau1x00.h | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'include')

diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 0a10e3c..4cc5085 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -81,8 +81,7 @@
 				   CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \
 				   CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C))
 #else /* CONFIG_DBAU1550 */
-/* Boot from Compact flash partition 2 as default */
-#define CONFIG_BOOTCOMMAND	"ide reset;disk 0x81000000 0:2;bootm"
+#define CONFIG_BOOTCOMMAND	"bootp;bootm"
 
 #define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \
 				 ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
@@ -133,8 +132,6 @@
 #define PHYS_FLASH_1		0xb8000000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0xbc000000 /* Flash Bank #2 */
 
-#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
-
 #else /* CONFIG_DBAU1550 */
 
 #define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
@@ -145,6 +142,8 @@
 
 #endif /* CONFIG_DBAU1550 */
 
+#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
+
 #define CFG_FLASH_CFI           1
 #define CFG_FLASH_CFI_DRIVER    1
 
-- 
cgit v1.1


From b81a4630a3914d611ca3e72b451c4509c60ae9b1 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Thu, 13 Apr 2006 16:35:22 +0200
Subject: Fix Quad UART mapping on MCC200 board due to new HW revision

---
 include/configs/mcc200.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index 67c2483..2b1c0d0 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -250,7 +250,7 @@
 /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 #define CFG_CS2_START		0x80000000
 #define CFG_CS2_SIZE		0x00001000
-#define CFG_CS2_CFG		0x1d800
+#define CFG_CS2_CFG		0x1d300
 
 #define CFG_CS_BURST		0x00000000
 #define CFG_CS_DEADCYCLE	0x33333333
-- 
cgit v1.1


From cf48eb9abd76e5a056937a4e49be094826026abc Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Sun, 16 Apr 2006 10:51:58 +0200
Subject: Some code cleanup

---
 include/configs/MPC8349EMDS.h |   4 +-
 include/crc.h                 | 139 +++++++++++++++++++++---------------------
 include/xyzModem.h            | 124 +++++++++++++++++++------------------
 3 files changed, 134 insertions(+), 133 deletions(-)

(limited to 'include')

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 39e3d95..1a47980 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -75,13 +75,13 @@
 
 /*
  * 32-bit data path mode.
- * 
+ *
  * Please note that using this mode for devices with the real density of 64-bit
  * effectively reduces the amount of available memory due to the effect of
  * wrapping around while translating address to row/columns, for example in the
  * 256MB module the upper 128MB get aliased with contents of the lower
  * 128MB); normally this define should be used for devices with real 32-bit
- * data path. 
+ * data path.
  */
 #undef CONFIG_DDR_32BIT
 
diff --git a/include/crc.h b/include/crc.h
index 63399bf..10560c9 100644
--- a/include/crc.h
+++ b/include/crc.h
@@ -1,56 +1,58 @@
-//==========================================================================
-//
-//      crc.h
-//
-//      Interface for the CRC algorithms.
-//
-//==========================================================================
-//####ECOSGPLCOPYRIGHTBEGIN####
-// -------------------------------------------
-// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 2002 Andrew Lunn
-//
-// eCos is free software; you can redistribute it and/or modify it under
-// the terms of the GNU General Public License as published by the Free
-// Software Foundation; either version 2 or (at your option) any later version.
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-// for more details.
-//
-// You should have received a copy of the GNU General Public License along
-// with eCos; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-//
-// As a special exception, if other files instantiate templates or use macros
-// or inline functions from this file, or you compile this file and link it
-// with other works to produce a work based on this file, this file does not
-// by itself cause the resulting work to be covered by the GNU General Public
-// License. However the source code for this file must still be made available
-// in accordance with section (3) of the GNU General Public License.
-//
-// This exception does not invalidate any other reasons why a work based on
-// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
-// -------------------------------------------
-//####ECOSGPLCOPYRIGHTEND####
-//==========================================================================
-//#####DESCRIPTIONBEGIN####
-//
-// Author(s):    Andrew Lunn
-// Contributors: Andrew Lunn
-// Date:         2002-08-06
-// Purpose:      
-// Description:  
-//              
-// This code is part of eCos (tm).
-//
-//####DESCRIPTIONEND####
-//
-//==========================================================================
+/*
+ *==========================================================================
+ *
+ *      crc.h
+ *
+ *      Interface for the CRC algorithms.
+ *
+ *==========================================================================
+ *####ECOSGPLCOPYRIGHTBEGIN####
+ * -------------------------------------------
+ * This file is part of eCos, the Embedded Configurable Operating System.
+ * Copyright (C) 2002 Andrew Lunn
+ *
+ * eCos is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 or (at your option) any later version.
+ *
+ * eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+ * WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with eCos; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * As a special exception, if other files instantiate templates or use macros
+ * or inline functions from this file, or you compile this file and link it
+ * with other works to produce a work based on this file, this file does not
+ * by itself cause the resulting work to be covered by the GNU General Public
+ * License. However the source code for this file must still be made available
+ * in accordance with section (3) of the GNU General Public License.
+ *
+ * This exception does not invalidate any other reasons why a work based on
+ * this file might be covered by the GNU General Public License.
+ *
+ * Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+ * at http: *sources.redhat.com/ecos/ecos-license/
+ * -------------------------------------------
+ *####ECOSGPLCOPYRIGHTEND####
+ *==========================================================================
+ *#####DESCRIPTIONBEGIN####
+ *
+ * Author(s):    Andrew Lunn
+ * Contributors: Andrew Lunn
+ * Date:         2002-08-06
+ * Purpose:
+ * Description:
+ *
+ * This code is part of eCos (tm).
+ *
+ *####DESCRIPTIONEND####
+ *
+ *==========================================================================
+ */
 
 #ifndef _SERVICES_CRC_CRC_H_
 #define _SERVICES_CRC_CRC_H_
@@ -65,37 +67,34 @@
 # endif
 #endif
 
-// Compute a CRC, using the POSIX 1003 definition
-extern uint32_t 
+/* Compute a CRC, using the POSIX 1003 definition */
+extern uint32_t
 cyg_posix_crc32(unsigned char *s, int len);
 
-// Gary S. Brown's 32 bit CRC
+/* Gary S. Brown's 32 bit CRC */
 
-extern uint32_t 
+extern uint32_t
 cyg_crc32(unsigned char *s, int len);
 
-// Gary S. Brown's 32 bit CRC, but accumulate the result from a
-// previous CRC calculation
+/* Gary S. Brown's 32 bit CRC, but accumulate the result from a */
+/* previous CRC calculation */
 
-extern uint32_t 
+extern uint32_t
 cyg_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
 
-// Ethernet FCS Algorithm
+/* Ethernet FCS Algorithm */
 
-extern uint32_t 
+extern uint32_t
 cyg_ether_crc32(unsigned char *s, int len);
 
-// Ethernet FCS algorithm, but accumulate the result from a previous
-// CRC calculation.
+/* Ethernet FCS algorithm, but accumulate the result from a previous */
+/* CRC calculation. */
 
-extern uint32_t 
+extern uint32_t
 cyg_ether_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
 
-// 16 bit CRC with polynomial x^16+x^12+x^5+1
+/* 16 bit CRC with polynomial x^16+x^12+x^5+1 */
 
 extern uint16_t cyg_crc16(unsigned char *s, int len);
 
-#endif // _SERVICES_CRC_CRC_H_
-
-
-
+#endif /* _SERVICES_CRC_CRC_H_ */
diff --git a/include/xyzModem.h b/include/xyzModem.h
index a62a174..4ec10b5 100644
--- a/include/xyzModem.h
+++ b/include/xyzModem.h
@@ -1,65 +1,67 @@
-//==========================================================================
-//
-//      xyzModem.h
-//
-//      RedBoot stream handler for xyzModem protocol
-//
-//==========================================================================
-//####ECOSGPLCOPYRIGHTBEGIN####
-// -------------------------------------------
-// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-// Copyright (C) 2002 Gary Thomas
-//
-// eCos is free software; you can redistribute it and/or modify it under
-// the terms of the GNU General Public License as published by the Free
-// Software Foundation; either version 2 or (at your option) any later version.
-//
-// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-// for more details.
-//
-// You should have received a copy of the GNU General Public License along
-// with eCos; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-//
-// As a special exception, if other files instantiate templates or use macros
-// or inline functions from this file, or you compile this file and link it
-// with other works to produce a work based on this file, this file does not
-// by itself cause the resulting work to be covered by the GNU General Public
-// License. However the source code for this file must still be made available
-// in accordance with section (3) of the GNU General Public License.
-//
-// This exception does not invalidate any other reasons why a work based on
-// this file might be covered by the GNU General Public License.
-//
-// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-// at http://sources.redhat.com/ecos/ecos-license/
-// -------------------------------------------
-//####ECOSGPLCOPYRIGHTEND####
-//==========================================================================
-//#####DESCRIPTIONBEGIN####
-//
-// Author(s):    gthomas
-// Contributors: gthomas
-// Date:         2000-07-14
-// Purpose:      
-// Description:  
-//              
-// This code is part of RedBoot (tm).
-//
-//####DESCRIPTIONEND####
-//
-//==========================================================================
+/*
+ *==========================================================================
+ *
+ *      xyzModem.h
+ *
+ *      RedBoot stream handler for xyzModem protocol
+ *
+ *==========================================================================
+ *####ECOSGPLCOPYRIGHTBEGIN####
+ * -------------------------------------------
+ * This file is part of eCos, the Embedded Configurable Operating System.
+ * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+ * Copyright (C) 2002 Gary Thomas
+ *
+ * eCos is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 or (at your option) any later version.
+ *
+ * eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+ * WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with eCos; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * As a special exception, if other files instantiate templates or use macros
+ * or inline functions from this file, or you compile this file and link it
+ * with other works to produce a work based on this file, this file does not
+ * by itself cause the resulting work to be covered by the GNU General Public
+ * License. However the source code for this file must still be made available
+ * in accordance with section (3) of the GNU General Public License.
+ *
+ * This exception does not invalidate any other reasons why a work based on
+ * this file might be covered by the GNU General Public License.
+ *
+ * Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+ * at http: *sources.redhat.com/ecos/ecos-license/
+ * -------------------------------------------
+ *####ECOSGPLCOPYRIGHTEND####
+ *==========================================================================
+ *#####DESCRIPTIONBEGIN####
+ *
+ * Author(s):    gthomas
+ * Contributors: gthomas
+ * Date:         2000-07-14
+ * Purpose:
+ * Description:
+ *
+ * This code is part of RedBoot (tm).
+ *
+ *####DESCRIPTIONEND####
+ *
+ *==========================================================================
+ */
 
 #ifndef _XYZMODEM_H_
 #define _XYZMODEM_H_
 
 #define xyzModem_xmodem 1
 #define xyzModem_ymodem 2
-// Don't define this until the protocol support is in place
-//#define xyzModem_zmodem 3
+/* Don't define this until the protocol support is in place */
+/*#define xyzModem_zmodem 3 */
 
 #define xyzModem_access   -1
 #define xyzModem_noZmodem -2
@@ -103,10 +105,10 @@ typedef unsigned int bool;
 #endif
 
 
-int   xyzModem_stream_open(connection_info_t *info, int *err);    
-void  xyzModem_stream_close(int *err);    
-void  xyzModem_stream_terminate(bool method, int (*getc)(void));    
-int   xyzModem_stream_read(char *buf, int size, int *err);    
+int   xyzModem_stream_open(connection_info_t *info, int *err);
+void  xyzModem_stream_close(int *err);
+void  xyzModem_stream_terminate(bool method, int (*getc)(void));
+int   xyzModem_stream_read(char *buf, int size, int *err);
 char *xyzModem_error(int err);
 
-#endif // _XYZMODEM_H_
+#endif /* _XYZMODEM_H_ */
-- 
cgit v1.1


From a367d42640e3cb10afeb4950bd5beb1c7f6cf107 Mon Sep 17 00:00:00 2001
From: "dzu@denx.de" <dzu@eddie.localdomain>
Date: Wed, 19 Apr 2006 11:52:46 +0200
Subject: Update for NC650 board.  Add NC650 based CP850 configuration.

Signed-off-by: dzu@denx.de <dzu@denx.de>
---
 include/configs/NC650.h | 66 +++++++++++++++++++++++++++++++++++--------------
 1 file changed, 48 insertions(+), 18 deletions(-)

(limited to 'include')

diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 3c59df4..8da29c4 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -1,4 +1,5 @@
 /*
+ * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  * (C) Copyright 2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -65,6 +66,11 @@
 #define CFG_8XX_XIN			CONFIG_8xx_OSCLK
 
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		"\nEnter password - autoboot in %d seconds...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"ids"
+#define CONFIG_BOOT_RETRY_TIME		900
+#define CONFIG_BOOT_RETRY_MIN		30
 
 #define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
 
@@ -75,7 +81,7 @@
 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
 	"bootm"
 
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_WATCHDOG			/* watchdog enabled 		*/
 
 #undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
 
@@ -96,12 +102,26 @@
 /*
  * Software (bit-bang) I2C driver configuration
  */
+#if defined(CONFIG_IDS852_REV1)
+
 #define SCL		0x1000		/* PA 3 */
 #define SDA		0x2000		/* PA 2 */
 
 #define __I2C_DIR	immr->im_ioport.iop_padir
 #define __I2C_DAT	immr->im_ioport.iop_padat
 #define __I2C_PAR	immr->im_ioport.iop_papar
+
+#elif defined(CONFIG_IDS852_REV2)
+
+#define SCL		0x0002		/* PB 30 */
+#define SDA		0x0001		/* PB 31 */
+
+#define __I2C_PAR	immr->im_cpm.cp_pbpar
+#define __I2C_DIR	immr->im_cpm.cp_pbdir
+#define __I2C_DAT	immr->im_cpm.cp_pbdat
+
+#endif
+
 #define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
 			  __I2C_DIR |= (SDA|SCL);	}
 #define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
@@ -229,17 +249,6 @@
 #define ADDR_COLUMN		1
 #define NAND_NO_RB
 
-#define NAND_WAIT_READY(nand)		udelay(12)
-#define WRITE_NAND_COMMAND(d, adr)	WRITE_NAND(d, adr + 2)
-#define WRITE_NAND_ADDRESS(d, adr)	WRITE_NAND(d, adr + 1)
-#define WRITE_NAND(d, adr)		(*(volatile uint8_t *)(adr) = (uint8_t)(d))
-#define READ_NAND(adr)			(*(volatile uint8_t *)(adr))
-#define NAND_DISABLE_CE(nand)		/* nop */
-#define NAND_ENABLE_CE(nand)		/* nop */
-#define NAND_CTL_CLRALE(nandptr)	/* nop */
-#define NAND_CTL_SETALE(nandptr)	/* nop */
-#define NAND_CTL_CLRCLE(nandptr)	/* nop */
-#define NAND_CTL_SETCLE(nandptr)	/* nop */
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control					11-9
@@ -312,7 +321,8 @@
 #define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
- * BR2 and OR2 (NAND Flash) - now addressed through UPMB
+ * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
+ * rev2 only uses the chipselect
  */
 #define CFG_NAND_BASE		0x50000000
 #define CFG_NAND_SIZE		0x04000000
@@ -338,6 +348,18 @@
 #define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 
 /*
+ * BR4 and OR4 (CPLD)
+ */
+#define CFG_CPLD_BASE           0x80000000      /* CPLD                 */
+#define CFG_CPLD_SIZE           0x10000         /* only 16 used         */
+
+#define CFG_OR_TIMING_CPLD	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+				 OR_SCY_1_CLK)
+
+#define CFG_BR4_PRELIM  ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CFG_OR4_PRELIM  (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD)
+
+/*
  * BR5 and OR5 (SRAM)
  */
 #define CFG_SRAM_BASE		0x60000000
@@ -349,6 +371,16 @@
 #define CFG_BR5_PRELIM  ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 #define CFG_OR5_PRELIM  (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
 
+#if defined(CONFIG_CP850)
+/*
+ *  BR6 and OR6 (DPRAM) - only on CP850
+ */
+#define CFG_OR6_PRELIM          0xffff8170
+#define CFG_BR6_PRELIM          0xa0000401
+#define DPRAM_BASE_ADDR         0xa0000000
+
+#define CONFIG_MISC_INIT_R      1
+#endif
 
 /*
  * 4096 Rows from SDRAM example configuration
@@ -413,14 +445,12 @@
 #define CONFIG_JFFS2_PART_OFFSET	0x00000000
 
 /* mtdparts command line support */
-/*
 #define CONFIG_JFFS2_CMDLINE
 #define MTDIDS_DEFAULT		"nor0=nc650-0,nand0=nc650-nand"
 
 #define MTDPARTS_DEFAULT	"mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
-					"2560k(cramfs1),2560k(cramfs2)," \
-					"256k(u-boot),256k(env);" \
-				"nc650-nand:4m(nand1),28m(nand2)"
-*/
+					"4m(cramfs1),1m(cramfs2)," \
+					"256k(u-boot),128k(env);" \
+				"nc650-nand:4m(jffs1),28m(jffs2)"
 
 #endif	/* __CONFIG_H */
-- 
cgit v1.1