From 3b4dbd37dcd0b851f39dda1ff212d6ef902d4db7 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 19 Jul 2016 14:05:47 +0530 Subject: board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET qixis_reset altbank usagge ~QIXIS_LBMAP_MASK in code. So define inverse value QIXIS_LBMAP_MASK. Also, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD] as 0b11 i.e. PORESET during qixis_reset Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/configs/ls1012aqds.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index fcf402c..6e31ca0 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -28,11 +28,11 @@ #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_BRDCFG_REG 0x04 #define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0xf7 +#define QIXIS_LBMAP_MASK 0x08 #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x08 -#define QIXIS_RST_CTL_RESET 0x41 +#define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -- cgit v1.1 From 9c3fca2a79be3d9d67d7766bbd85efc941bcb237 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 19 Jul 2016 15:54:22 +0530 Subject: armv8: ls1012a: Enable DDR row-bank-column decoding Enable DDR row-bank-column decoding to decode DDR address as row-bank-column instead of bank-row-column for improving performance of serial data transfers. Signed-off-by: Calvin Johnson Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/fsl_mmdc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h index 281a819..833696b 100644 --- a/include/fsl_mmdc.h +++ b/include/fsl_mmdc.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64 #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db -#define CONFIG_SYS_MMDC_CORE_MISC 0x00000680 +#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680 #define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800 #define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000 #define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a -- cgit v1.1 From 37eac3f4609c4a6b7c8c3a2f4046fbc5deb07299 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 19 Jul 2016 15:54:33 +0530 Subject: armv8: ls1012a: Update Refresh cycle for DDR Refresh cycle value must be selected based on the frequency of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT] should be based on round up (tREFI/tCK) formula. For 500MHz, mdref value should be 0x0f3c8000. Signed-off-by: Calvin Johnson Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/fsl_mmdc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h index 833696b..a939d89 100644 --- a/include/fsl_mmdc.h +++ b/include/fsl_mmdc.h @@ -43,7 +43,7 @@ #define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067 -#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000 +#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000 #define START_REFRESH 0x00000001 -- cgit v1.1 From 6ffc490541cd464ac3340742fa278c13ac7b9d13 Mon Sep 17 00:00:00 2001 From: Wenbin Song Date: Fri, 15 Jul 2016 17:17:46 +0800 Subject: armv8: ls1043a: enable pxe commands Enable pxe command for ls1043ardb and ls1043aqds. Signed-off-by: Wenbin Song Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 0ad5261..e55fcb2 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -175,6 +175,8 @@ /* Command line configuration */ #define CONFIG_CMD_ENV +#define CONFIG_MENU +#define CONFIG_CMD_PXE /* MMC */ #define CONFIG_MMC -- cgit v1.1 From ab01ef5fa617444fd95543ee04ea53ccda273269 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 29 Jul 2016 19:26:34 +0800 Subject: ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIP The PPA binary may be stored on QSPI flash instead of NOR. So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code by addition of a new QSPI specific flag. Signed-off-by: Hou Zhiqiang Signed-off-by: Abhimanyu Saini Reviewed-by: York Sun --- include/configs/ls1043ardb.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 44f86fa..857ad7b 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -14,8 +14,8 @@ #define SEC_FIRMWARE_ERET_ADDR_REVERT #define CONFIG_ARMV8_PSCI -#define CONFIG_SYS_LS_PPA_FW_IN_NOR -#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR +#define CONFIG_SYS_LS_PPA_FW_IN_XIP +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP #define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 #endif #endif -- cgit v1.1