From fd428c05c863aefb575b12b2a1916b02d5bfa759 Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Fri, 12 Mar 2010 10:01:12 +0100 Subject: mpc5xxx: Remove all references to MGT5100 We do not support a processor that never reached a real customer. Signed-off-by: Detlev Zundel --- include/configs/BC3450.h | 9 +--- include/configs/IceCube.h | 13 +----- include/configs/PM520.h | 11 ----- include/configs/TB5200.h | 5 --- include/configs/TQM5200.h | 5 --- include/configs/Total5200.h | 23 +--------- include/configs/aev.h | 5 --- include/configs/cpci5200.h | 11 ----- include/configs/hmi1001.h | 5 --- include/configs/inka4x0.h | 5 --- include/configs/ipek01.h | 5 --- include/configs/manroland/mpc5200-common.h | 5 --- include/configs/mecp5200.h | 14 ------ include/configs/o2dnt.h | 7 --- include/configs/pf5200.h | 11 ----- include/configs/smmaco4.h | 5 --- include/configs/spieval.h | 5 --- include/configs/v38b.h | 2 - include/mpc5xxx.h | 69 +----------------------------- 19 files changed, 6 insertions(+), 209 deletions(-) (limited to 'include') diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 8c5a742..44befe9 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -471,13 +471,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) -# define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -# define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -# define CONFIG_SYS_HID0_INIT 0 -# define CONFIG_SYS_HID0_FINAL 0 -#endif +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 5ef0b77..5d3a744 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -30,6 +30,7 @@ */ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -47,7 +48,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -77,10 +77,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#else -#define CONFIG_MII 1 -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -169,7 +165,6 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ @@ -178,7 +173,6 @@ #else #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif -#endif /* CONFIG_MPC5200 */ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -338,13 +332,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #if defined(CONFIG_LITE5200B) #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE diff --git a/include/configs/PM520.h b/include/configs/PM520.h index f9687d2..22de207 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -75,7 +74,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #undef CONFIG_NS8382X -#endif /* Partitions */ #define CONFIG_DOS_PARTITION @@ -111,9 +109,7 @@ #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB -#if defined(CONFIG_MPC5200) #define CONFIG_CMD_PCI -#endif /* @@ -147,12 +143,10 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -301,13 +295,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #if defined(CONFIG_BOOT_ROM) #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 3438aba..6da18eb 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -430,13 +430,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 2154c78..107bff1 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -633,13 +633,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 1daa574..7510ab1 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -41,6 +41,7 @@ */ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -73,7 +74,6 @@ #define CONFIG_SPLASH_SCREEN -#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -98,12 +98,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#else /* MGT5100 */ - -#define CONFIG_MII 1 - -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -127,9 +121,7 @@ */ #include -#if defined(CONFIG_MPC5200) - #define CONFIG_CMD_PCI -#endif +#define CONFIG_CMD_PCI #define CONFIG_CMD_BMP #define CONFIG_CMD_EEPROM @@ -176,12 +168,10 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration @@ -326,17 +316,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif - -#if defined (CONFIG_MGT5100) -# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */ -#endif #if CONFIG_TOTAL5200_REV==1 # define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE diff --git a/include/configs/aev.h b/include/configs/aev.h index 2b4826d..98958a6 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -362,13 +362,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index 52df16a..f7290d6 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -59,7 +59,6 @@ #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -90,8 +89,6 @@ #define CONFIG_NS8382X 1 #endif -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -169,8 +166,6 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) - #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000 #define CONFIG_SYS_NVRAM_SIZE 32*1024 @@ -179,7 +174,6 @@ * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -303,13 +297,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index a81527e..f9cdcbc 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -261,13 +261,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 14f7826..c5b1565 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -366,13 +366,8 @@ static inline void tws_data_config_output(unsigned output) /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index d0cb1e1..6903b36 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -324,13 +324,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h index b29ef9b..d25e093 100644 --- a/include/configs/manroland/mpc5200-common.h +++ b/include/configs/manroland/mpc5200-common.h @@ -170,13 +170,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 4a93b58..73405ea 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -63,9 +63,6 @@ #endif #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ - #define CONFIG_MII #if 0 /* test-only !!! */ #define CONFIG_NET_MULTI 1 @@ -74,10 +71,6 @@ #define CONFIG_NS8382X 1 #endif -#else /* MPC5100 */ - -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -152,12 +145,10 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -288,13 +279,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 18e7cc2..bdc0f79 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -138,7 +138,6 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ @@ -154,7 +153,6 @@ */ #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif -#endif /* * I2C configuration @@ -276,13 +274,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 8ca55d7..80a0bc6 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -61,7 +61,6 @@ #endif #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -87,7 +86,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 #endif -#endif /* Partitions */ #define CONFIG_MAC_PARTITION @@ -121,9 +119,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE -#ifdef CONFIG_MPC5200 #define CONFIG_CMD_PCI -#endif #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ @@ -166,12 +162,10 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -289,13 +283,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 5a2ef3a..060026b 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -358,13 +358,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 27dda25..d377e19 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -438,13 +438,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 92bcdb3..d462ed0 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -170,12 +170,10 @@ #define CONFIG_BOOTCOMMAND "run net_nfs" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 4dcf90c..2d343c7 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -1,7 +1,7 @@ /* * include/asm-ppc/mpc5xxx.h * - * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx + * Prototypes, etc. for the Motorola MPC5xxx * embedded cpu chips * * 2003 (c) MontaVista, Software, Inc. @@ -33,24 +33,15 @@ #include /* Processor name */ -#if defined(CONFIG_MPC5200) #define CPU_ID_STR "MPC5200" -#elif defined(CONFIG_MGT5100) -#define CPU_ID_STR "MGT5100" -#endif /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 #define _START_OFFSET EXC_OFF_SYS_RESET /* useful macros for manipulating CSx_START/STOP */ -#if defined(CONFIG_MGT5100) -#define START_REG(start) ((start) >> 15) -#define STOP_REG(start, size) (((start) + (size) - 1) >> 15) -#elif defined(CONFIG_MPC5200) #define START_REG(start) ((start) >> 16) #define STOP_REG(start, size) (((start) + (size) - 1) >> 16) -#endif /* Internal memory map */ @@ -70,21 +61,12 @@ #define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050) #define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SDRAM_START (CONFIG_SYS_MBAR + 0x0034) -#define MPC5XXX_SDRAM_STOP (CONFIG_SYS_MBAR + 0x0038) -#define MPC5XXX_PCI1_START (CONFIG_SYS_MBAR + 0x003c) -#define MPC5XXX_PCI1_STOP (CONFIG_SYS_MBAR + 0x0040) -#define MPC5XXX_PCI2_START (CONFIG_SYS_MBAR + 0x0044) -#define MPC5XXX_PCI2_STOP (CONFIG_SYS_MBAR + 0x0048) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058) #define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c) #define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060) #define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064) #define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034) #define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038) -#endif #define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100) #define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200) @@ -99,18 +81,12 @@ #define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200) #define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) -#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2400) -#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2800) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200) #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400) #define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600) #define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800) #define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00) -#endif #define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000) #define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00) @@ -118,22 +94,14 @@ #define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00) #define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x4000) -#define MPC5XXX_SRAM_SIZE (8*1024) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000) #define MPC5XXX_SRAM_SIZE (16*1024) -#endif /* SDRAM Controller */ #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010) -#endif #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) /* Clock Distribution Module */ @@ -155,19 +123,15 @@ #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) -#if defined(CONFIG_MPC5200) #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) -#endif -#if defined(CONFIG_MPC5200) /* XLB Arbiter registers */ #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) -#endif /* GPIO registers */ #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) @@ -242,14 +206,6 @@ #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68) -#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c) -#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70) -#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74) -#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78) -#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) @@ -262,7 +218,6 @@ #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) -#endif /* Interrupt Controller registers */ #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) @@ -495,31 +450,16 @@ struct mpc5xxx_mmap_ctl { volatile u32 cs4_stop; volatile u32 cs5_start; /* 0x002c */ volatile u32 cs5_stop; -#if defined(CONFIG_MGT5100) - volatile u32 sdram_start; /* 0x0034 */ - volatile u32 sdram_stop; /* 0x0038 */ - volatile u32 pci1_start; /* 0x003c */ - volatile u32 pci1_stop; /* 0x0040 */ - volatile u32 pci2_start; /* 0x0044 */ - volatile u32 pci2_stop; /* 0x0048 */ -#elif defined(CONFIG_MPC5200) volatile u32 sdram0; /* 0x0034 */ volatile u32 sdram1; /* 0x0038 */ volatile u32 dummy1[4]; /* 0x003c */ -#endif volatile u32 boot_start; /* 0x004c */ volatile u32 boot_stop; -#if defined(CONFIG_MGT5100) - volatile u32 addecr; /* 0x0054 */ -#elif defined(CONFIG_MPC5200) volatile u32 ipbi_ws_ctrl; /* 0x0054 */ -#endif -#if defined(CONFIG_MPC5200) volatile u32 cs6_start; /* 0x0058 */ volatile u32 cs6_stop; volatile u32 cs7_start; /* 0x0060 */ volatile u32 cs7_stop; -#endif }; /* Clock distribution module */ @@ -546,12 +486,7 @@ struct mpc5xxx_sdram { volatile u32 ctrl; volatile u32 config1; volatile u32 config2; -#if defined(CONFIG_MGT5100) - volatile u32 xlbsel; - volatile u32 dummy[31]; -#else volatile u32 dummy[32]; -#endif volatile u32 sdelay; }; @@ -564,12 +499,10 @@ struct mpc5xxx_lpb { volatile u32 cs5_cfg; volatile u32 cs_ctrl; volatile u32 cs_status; -#if defined(CONFIG_MPC5200) volatile u32 cs6_cfg; volatile u32 cs7_cfg; volatile u32 cs_burst; volatile u32 cs_deadcycle; -#endif }; -- cgit v1.1 From 352745ad487f72e839986ddbb020e1fe86c1d482 Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Tue, 16 Mar 2010 12:12:48 -0400 Subject: nios2: use generic unaligned.h Signed-off-by: Scott McNutt --- include/asm-nios2/unaligned.h | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 include/asm-nios2/unaligned.h (limited to 'include') diff --git a/include/asm-nios2/unaligned.h b/include/asm-nios2/unaligned.h new file mode 100644 index 0000000..779117c --- /dev/null +++ b/include/asm-nios2/unaligned.h @@ -0,0 +1,6 @@ +#ifndef _ASM_NIOS2_UNALIGNED_H +#define _ASM_NIOS2_UNALIGNED_H + +#include + +#endif /* _ASM_NIOS2_UNALIGNED_H */ -- cgit v1.1 From a6a04967bc2957d20799f4bb2a6b3dd0353c1cfd Mon Sep 17 00:00:00 2001 From: Renato Andreola Date: Tue, 16 Mar 2010 16:01:29 -0400 Subject: nios2: Added support to YANU UART Signed-off-by: Scott McNutt --- include/nios2-yanu.h | 115 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 include/nios2-yanu.h (limited to 'include') diff --git a/include/nios2-yanu.h b/include/nios2-yanu.h new file mode 100644 index 0000000..1c9a967 --- /dev/null +++ b/include/nios2-yanu.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2006, Imagos S.a.s + * Renato Andreola + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera NiosII YANU serial interface by Imagos + * please see http://www.opencores.org/project,yanu for + * information/downloads + ************************************************************************/ + +#ifndef __NIOS2_YANU_H__ +#define __NIOS2_YANU_H__ + +#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ +#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */ +#define YANU_FIFO_SIZE (16) +#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) +#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) + +#define YANU_RXFIFO_DLY (10*11) +#define YANU_TXFIFO_THR (10) +#define YANU_DATA_CHAR_MASK (0xFF) + +/* data register */ +#define YANU_DATA_OFFSET (0) /* data register offset */ + +#define YANU_CONTROL_OFFSET (4) /* control register offset */ +/* interrupt enable */ +#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */ +#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */ +#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */ +#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */ +#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */ +#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */ +/* control bits */ +#define YANU_CONTROL_BITS_POS (6) /* bits number pos */ +#define YANU_CONTROL_BITS (1< Date: Mon, 1 Mar 2010 11:47:36 +0200 Subject: POST: add progress API Add POST progress API implemented as weak calls before and after each call to the POST test callback in the post_run_single routine of the post.c file. Signed-off-by: Michael Zaidman Acked-by: Detlev Zundel --- include/post.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/post.h b/include/post.h index 9fcd3ce..ff83bce 100644 --- a/include/post.h +++ b/include/post.h @@ -53,6 +53,11 @@ #define POST_FAIL_SAVE 0x80 +#define POST_BEFORE 1 +#define POST_AFTER 0 +#define POST_PASSED 1 +#define POST_FAILED 0 + #ifndef __ASSEMBLY__ struct post_test { -- cgit v1.1 From 3c950e2ebfde083084cc926b020e3a22a536bf85 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Tue, 16 Mar 2010 17:10:05 +0100 Subject: fdt_support: add partitions fixup in mtd node Allow overwriting defined partitions in the device tree blob using partition info defined in the 'mtdparts' environment variable. Signed-off-by: Anatolij Gustschin Cc: Gerald Van Baren --- include/fdt_support.h | 2 ++ include/jffs2/load_kernel.h | 1 + include/mtd_node.h | 11 +++++++++++ 3 files changed, 14 insertions(+) create mode 100644 include/mtd_node.h (limited to 'include') diff --git a/include/fdt_support.h b/include/fdt_support.h index 0a9dd0d..a3d5f8c 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -81,5 +81,7 @@ int fdt_resize(void *blob); int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size); +void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); + #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h index 8b2720e..906eb3d 100644 --- a/include/jffs2/load_kernel.h +++ b/include/jffs2/load_kernel.h @@ -78,5 +78,6 @@ struct mtdids { extern int mtdparts_init(void); extern int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part); +extern struct mtd_device *device_find(u8 type, u8 num); #endif /* load_kernel_h */ diff --git a/include/mtd_node.h b/include/mtd_node.h new file mode 100644 index 0000000..5aae085 --- /dev/null +++ b/include/mtd_node.h @@ -0,0 +1,11 @@ +#ifndef _NODE_INFO +#define _NODE_INFO + +/* + * Info we use to search for a flash node in DTB. + */ +struct node_info { + const char *compat; /* compatible string */ + int type; /* mtd flash type */ +}; +#endif -- cgit v1.1 From cc41a59a74ca9095d518d6d69655c6735dd00809 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Wed, 17 Mar 2010 10:03:10 -0400 Subject: TI: Davinci: NAND Driver Cleanup Modified to use IO accessor routines consistently. Eliminated volatile usage to keep checkpatch.pl happy. Signed-off-by: Cyril Chemparathy --- include/asm-arm/arch-davinci/emif_defs.h | 77 +++++++++++++++----------------- 1 file changed, 36 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h index aa57703..b48ec17 100644 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -24,47 +24,42 @@ #include -typedef struct davinci_emif_regs { - dv_reg ERCSR; - dv_reg AWCCR; - dv_reg SDBCR; - dv_reg SDRCR; - dv_reg AB1CR; - dv_reg AB2CR; - dv_reg AB3CR; - dv_reg AB4CR; - dv_reg SDTIMR; - dv_reg DDRSR; - dv_reg DDRPHYCR; - dv_reg DDRPHYSR; - dv_reg TOTAR; - dv_reg TOTACTR; - dv_reg DDRPHYID_REV; - dv_reg SDSRETR; - dv_reg EIRR; - dv_reg EIMR; - dv_reg EIMSR; - dv_reg EIMCR; - dv_reg IOCTRLR; - dv_reg IOSTATR; - u_int8_t RSVD0[8]; - dv_reg NANDFCR; - dv_reg NANDFSR; - u_int8_t RSVD1[8]; - dv_reg NANDFECC[4]; - u_int8_t RSVD2[60]; - dv_reg NAND4BITECCLOAD; - dv_reg NAND4BITECC1; - dv_reg NAND4BITECC2; - dv_reg NAND4BITECC3; - dv_reg NAND4BITECC4; - dv_reg NANDERRADD1; - dv_reg NANDERRADD2; - dv_reg NANDERRVAL1; - dv_reg NANDERRVAL2; -} emif_registers; - -typedef emif_registers *emifregs; +struct davinci_emif_regs { + u_int32_t ercsr; + u_int32_t awccr; + u_int32_t sdbcr; + u_int32_t sdrcr; + u_int32_t ab1cr; + u_int32_t ab2cr; + u_int32_t ab3cr; + u_int32_t ab4cr; + u_int32_t sdtimr; + u_int32_t ddrsr; + u_int32_t ddrphycr; + u_int32_t ddrphysr; + u_int32_t totar; + u_int32_t totactr; + u_int32_t ddrphyid_rev; + u_int32_t sdsretr; + u_int32_t eirr; + u_int32_t eimr; + u_int32_t eimsr; + u_int32_t eimcr; + u_int32_t ioctrlr; + u_int32_t iostatr; + u_int8_t rsvd0[8]; + u_int32_t nandfcr; + u_int32_t nandfsr; + u_int8_t rsvd1[8]; + u_int32_t nandfecc[4]; + u_int8_t rsvd2[60]; + u_int32_t nand4biteccload; + u_int32_t nand4bitecc[4]; + u_int32_t nanderradd1; + u_int32_t nanderradd2; + u_int32_t nanderrval1; + u_int32_t nanderrval2; +}; #define davinci_emif_regs \ ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) -- cgit v1.1 From fb508b8b39a52a4063d098f5a9b4355bc5b30c14 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Wed, 24 Mar 2010 10:16:20 +0100 Subject: at91: Get rid of some warnings when building for otc570 The soft-i2c code for AT91 defines I2C_SOFT_DECLARATIONS for direct access by dereferencing a pio pointer. The OTC570 platform uses the AT91 gpio API so it does not need the pio variable. Signed-off-by: Matthias Fuchs --- include/configs/otc570.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/otc570.h b/include/configs/otc570.h index 8e27eba..4fde012 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -102,6 +102,7 @@ at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \ at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \ } +#define I2C_SOFT_DECLARATIONS /* Configure data pin as output */ #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0) /* Configure data pin as input */ -- cgit v1.1 From c550afada5fcad426aa6a219a329feb9eedae8b2 Mon Sep 17 00:00:00 2001 From: Rupjyoti Sarmah Date: Wed, 24 Mar 2010 16:52:02 +0530 Subject: ppc4xx fix unstable 440EPx bootstrap options 440EPx fixed bootstrap options A, B, D, and E sets PLL FWDVA to a value = 1. This results in the PLLOUTB being greater than the CPU clock frequency resulting unstable 440EPx operation resulting in various software hang conditions. This patch reprograms the FWDVA satisfying the requirement of setting FWDVB to a value greater than 1 while using one of the four deafult bootstrap options. Signed-off-by: Rupjyoti Sarmah Acked-by : Victor Gallardo Signed-off-by: Stefan Roese --- include/ppc440.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/ppc440.h b/include/ppc440.h index e60fa13..5f87d2c 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -68,6 +68,12 @@ #define CPR0_SPCID 0x0120 #define CPR0_ICFG 0x0140 +/* 440EPX boot strap options */ +#define BOOT_STRAP_OPTION_A 0x00000000 +#define BOOT_STRAP_OPTION_B 0x00000001 +#define BOOT_STRAP_OPTION_D 0x00000003 +#define BOOT_STRAP_OPTION_E 0x00000004 + /* 440gx sdr register definations */ #define SDR0_SDSTP0 0x0020 /* */ #define SDR0_SDSTP1 0x0021 /* */ -- cgit v1.1 From 9d79e5758c3a6776be9a86856823d28e7154a481 Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Mon, 25 Jan 2010 11:27:44 +0100 Subject: add ASTRO MCF5373L board This patch adds support for ASTRO board(s) based on MCF5373L. Signed-off-by: Wolfgang Wegner --- include/configs/astro_mcf5373l.h | 389 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 389 insertions(+) create mode 100644 include/configs/astro_mcf5373l.h (limited to 'include') diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h new file mode 100644 index 0000000..1fe42f6 --- /dev/null +++ b/include/configs/astro_mcf5373l.h @@ -0,0 +1,389 @@ +/* + * Configuration settings for the Sentec Cobra Board. + * + * (C) Copyright 2003 Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * configuration for ASTRO "Urmel" board. + * Originating from Cobra5272 configuration, messed up by + * Wolfgang Wegner + * Please do not bother the original author with bug reports + * concerning this file. + */ + +#ifndef _CONFIG_ASTRO_MCF5373L_H +#define _CONFIG_ASTRO_MCF5373L_H + +/* + * set the card type to actually compile for; either of + * the possibilities listed below has to be used! + */ +#define CONFIG_ASTRO_V532 1 + +#if CONFIG_ASTRO_V532 +#define ASTRO_ID 0xF8 +#elif CONFIG_ASTRO_V512 +#define ASTRO_ID 0xFA +#elif CONFIG_ASTRO_TWIN7S2 +#define ASTRO_ID 0xF9 +#elif CONFIG_ASTRO_V912 +#define ASTRO_ID 0xFC +#elif CONFIG_ASTRO_COFDMDUOS2 +#define ASTRO_ID 0xFB +#else +#error No card type defined! +#endif + +/* + * Define processor + * possible values for Urmel board: only Coldfire M5373 processor supported + * (please do not change) + */ + +/* it seems not clear yet which processor defines we should use */ +#define CONFIG_MCF537x /* define processor family */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5373 /* define processor type */ +#define CONFIG_ASTRO5373L /* define board type */ + +/* Command line configuration */ +#include + +/* + * CONFIG_MK_RAM defines if u-boot is loaded via BDM (or started from + * a different bootloader that has already performed RAM setup) or + * started directly from flash, which is the regular case for production + * boards. + */ +#ifdef CONFIG_MK_RAM +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_TEXT_BASE 0x40020000 +#define ENABLE_JFFS 0 +#else +#define CONFIG_TEXT_BASE 0x00000000 +#define ENABLE_JFFS 1 +#endif + +/* Define which commmands should be available at u-boot command prompt */ + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_XIMG +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#if ENABLE_JFFS +#define CONFIG_CMD_JFFS2 +#endif +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_FPGA +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* + * Defines processor clock - important for correct timings concerning serial + * interface etc. + * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms + */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ + +#define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 +#define CONFIG_SYS_CORE_SRAM 0x80000000 + +#define CONFIG_SYS_UNIFY_CACHE + +/* + * Define baudrate for UART1 (console output, tftp, ...) + * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud + * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected + * in u-boot command interface + */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (2) +#define CONFIG_SYS_UART2_ALT3_GPIO + +/* + * Watchdog configuration; Watchdog is disabled for running from RAM + * and set to highest possible value else. Beware there is no check + * in the watchdog code to validate the timeout value set here! + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ +#endif + +/* + * Configuration for environment + * Environment is located in the last sector of the flash + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_ENV_OFFSET 0x1FF8000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#else +/* + * environment in RAM - This is used to use a single PC-based application + * to load an image, load U-Boot, load an environment and then start U-Boot + * to execute the commands from the environment. Feedback is done via setting + * and reading memory locations. + */ +#define CONFIG_ENV_ADDR 0x40060000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +/* here we put our FPGA configuration... */ +#define CONFIG_MISC_INIT_R 1 + +/* Define user parameters that have to be customized most likely */ + +/* AUTOBOOT settings - booting images automatically by u-boot after power on */ + +/* + * used for autoboot, delay in seconds u-boot will wait before starting + * defined (auto-)boot command, setting to -1 disables delay, setting to + * 0 will too prevent access to u-boot command interface: u-boot then has + * to be reflashed + * beware - watchdog is not serviced during autoboot delay time! + */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTDELAY 1 +#else +#define CONFIG_BOOTDELAY 1 +#endif + +/* + * The following settings will be contained in the environment block ; if you + * want to use a neutral environment all those settings can be manually set in + * u-boot: 'set' command + */ + +#define _QUOTEME(x) #x +#define QUOTEME(x) _QUOTEME(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loaderversion=11\0" \ + "card_id="QUOTEME(ASTRO_ID)"\0" \ + "alterafile=0\0" \ + "xilinxfile=0\0" \ + "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ + "fpga load 0 0x41000000 $filesize\0" \ + "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ + "fpga load 1 0x41000000 $filesize\0" \ + "env_default=1\0" \ + "env_check=if test $env_default -eq 1;"\ + " then setenv env_default 0;saveenv;fi\0" + +/* + * "update" is a non-standard command that has to be supplied + * by external update.c; This is not included in mainline because + * it needs non-blocking CFI routines. + */ +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ +#else +#if CONFIG_ASTRO_V532 +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&run alteraload&&bootm 0x80000;"\ + "update;reset" +#else +#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ + "run xilinxload&&bootm 0x80000;update;reset" +#endif +#endif + +/* default bootargs that are considered during boot */ +#define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs"\ + " loaderversion=$loaderversion" + +#define CONFIG_SYS_PROMPT "URMEL > " + +/* default RAM address for user programs */ +#define CONFIG_SYS_LOAD_ADDR 0x20000 + +#define CONFIG_SYS_LONGHELP + +#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 +#else +#define CONFIG_SYS_CBSIZE 256 +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_WAIT 1000 + +/* End of user parameters to be customized */ + +/* Defines memory range for test */ + +#define CONFIG_SYS_MEMTEST_START 0x40020000 +#define CONFIG_SYS_MEMTEST_END 0x41ffffff + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/* Base register address */ + +#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ + +/* System Conf. Reg. & System Protection Reg. */ + +#define CONFIG_SYS_SCR 0x0003; +#define CONFIG_SYS_SPR 0xffff; + +/* + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_END 0x8000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* + * Chipselect bank definitions + * + * CS0 - Flash 32MB (first 16MB) + * CS1 - Flash 32MB (second half) + * CS2 - FPGA + * CS3 - FPGA + * CS4 - unused + * CS5 - unused + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x00ff0001 +#define CONFIG_SYS_CS0_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS1_BASE 0x01000000 +#define CONFIG_SYS_CS1_MASK 0x00ff0001 +#define CONFIG_SYS_CS1_CTRL 0x00001fc0 + +#define CONFIG_SYS_CS2_BASE 0x20000000 +#define CONFIG_SYS_CS2_MASK 0x00ff0001 +#define CONFIG_SYS_CS2_CTRL 0x0000fec0 + +#define CONFIG_SYS_CS3_BASE 0x21000000 +#define CONFIG_SYS_CS3_MASK 0x00ff0001 +#define CONFIG_SYS_CS3_CTRL 0x0000fec0 + +#define CONFIG_SYS_FLASH_BASE 0x00000000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_BASE CONFIG_TEXT_BASE +#else +/* This is mainly used during relocation in start.S */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* FLASH organization */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 +#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_SIZE 0x2000000 +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 + +#if ENABLE_JFFS +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 +#endif + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#endif /* _CONFIG_ASTRO_MCF5373L_H */ -- cgit v1.1 From 89083346d0627a5e6e271e61bd34ab5121f9462b Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Fri, 30 Oct 2009 16:55:02 +0100 Subject: add block write function to spartan3 slave serial load Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner --- include/spartan3.h | 1 + include/xilinx.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/spartan3.h b/include/spartan3.h index 30b1c2d..d5a589d 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -57,6 +57,7 @@ typedef struct { Xilinx_done_fn done; Xilinx_wr_fn wr; Xilinx_post_fn post; + Xilinx_bwr_fn bwr; /* block write function */ } Xilinx_Spartan3_Slave_Serial_fns; /* Device Image Sizes diff --git a/include/xilinx.h b/include/xilinx.h index d0799bc..2cb2e5b 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -100,5 +100,6 @@ typedef int (*Xilinx_busy_fn)( int cookie ); typedef int (*Xilinx_abort_fn)( int cookie ); typedef int (*Xilinx_pre_fn)( int cookie ); typedef int (*Xilinx_post_fn)( int cookie ); +typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie ); #endif /* _XILINX_H_ */ -- cgit v1.1 From d04c1efae3d834db6e21e9976e338bf1e588e987 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Tue, 9 Mar 2010 18:32:16 -0600 Subject: ColdFire: Correct bit definition Use correct definition for _MASK and _UNMASK. It was combined in the previous used and causes confusion. Signed-off-by: TsiChung Liew --- include/asm-m68k/m520x.h | 89 ++++++++++++++++++------------------ include/asm-m68k/m5227x.h | 108 ++++++++++++++++++++++---------------------- include/asm-m68k/m5235.h | 4 +- include/asm-m68k/m5301x.h | 112 +++++++++++++++++++++++----------------------- include/asm-m68k/m5445x.h | 56 +++++++++++------------ 5 files changed, 183 insertions(+), 186 deletions(-) (limited to 'include') diff --git a/include/asm-m68k/m520x.h b/include/asm-m68k/m520x.h index 267bfd9..71f147e 100644 --- a/include/asm-m68k/m520x.h +++ b/include/asm-m68k/m520x.h @@ -70,7 +70,6 @@ #define PACR_TP 1 #define SCM_BMT_BME (0x00000008) -#define SCM_BMT_BMT_MASK (0x07) #define SCM_BMT_BMT(x) ((x) & 0x07) #define SCM_BMT_BMT1024 (0x0000) #define SCM_BMT_BMT512 (0x0001) @@ -179,7 +178,7 @@ #define CCM_CCR_PLL_MODE (0x0002) #define CCM_CCR_RESERVED (0x0001) -#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) #define CCM_CIR_PRN(x) ((x) & 0x003F) /* *** General Purpose I/O (GPIO) *** */ @@ -196,7 +195,7 @@ #define GPIO_PAR_FBCTL_OE (0x10) #define GPIO_PAR_FBCTL_TA (0x08) #define GPIO_PAR_FBCTL_RWB (0x04) -#define GPIO_PAR_FBCTL_TS_MASK (0xFC) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC) #define GPIO_PAR_FBCTL_TS_TS (0x03) #define GPIO_PAR_FBCTL_TS_DMA (0x02) @@ -207,39 +206,39 @@ #define GPIO_PAR_CS3 (0x08) #define GPIO_PAR_CS2 (0x04) -#define GPIO_PAR_CS1_MASK (0xFC) +#define GPIO_PAR_CS1_UNMASK (0xFC) #define GPIO_PAR_CS1_CS1 (0x03) #define GPIO_PAR_CS1_SDCS1 (0x02) -#define GPIO_PAR_FECI2C_RMII_MASK (0x0F) -#define GPIO_PAR_FECI2C_MDC_MASK (0x3F) +#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F) +#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F) #define GPIO_PAR_FECI2C_MDC_MDC (0xC0) #define GPIO_PAR_FECI2C_MDC_SCL (0x80) #define GPIO_PAR_FECI2C_MDC_U2TXD (0x40) -#define GPIO_PAR_FECI2C_MDIO_MASK (0xCF) +#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF) #define GPIO_PAR_FECI2C_MDIO_MDIO (0x30) #define GPIO_PAR_FECI2C_MDIO_SDA (0x20) #define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10) -#define GPIO_PAR_FECI2C_I2C_MASK (0xF0) -#define GPIO_PAR_FECI2C_SCL_MASK (0xF3) +#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3) #define GPIO_PAR_FECI2C_SCL_SCL (0x0C) #define GPIO_PAR_FECI2C_SCL_U2RXD (0x04) -#define GPIO_PAR_FECI2C_SDA_MASK (0xFC) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC) #define GPIO_PAR_FECI2C_SDA_SDA (0x03) #define GPIO_PAR_FECI2C_SDA_U2TXD (0x01) -#define GPIO_PAR_QSPI_PCS2_MASK (0x3F) +#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F) #define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0) #define GPIO_PAR_QSPI_PCS2_DACK0 (0x80) #define GPIO_PAR_QSPI_PCS2_U2RTS (0x40) -#define GPIO_PAR_QSPI_DIN_MASK (0xCF) +#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF) #define GPIO_PAR_QSPI_DIN_DIN (0x30) #define GPIO_PAR_QSPI_DIN_DREQ0 (0x20) #define GPIO_PAR_QSPI_DIN_U2CTS (0x10) -#define GPIO_PAR_QSPI_DOUT_MASK (0xF3) +#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3) #define GPIO_PAR_QSPI_DOUT_DOUT (0x0C) #define GPIO_PAR_QSPI_DOUT_SDA (0x08) -#define GPIO_PAR_QSPI_SCK_MASK (0xFC) +#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC) #define GPIO_PAR_QSPI_SCK_SCK (0x03) #define GPIO_PAR_QSPI_SCK_SCL (0x02) @@ -247,50 +246,50 @@ #define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4) #define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2) #define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03) -#define GPIO_PAR_TMR_TIN3_MASK (0x3F) +#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F) #define GPIO_PAR_TMR_TIN3_TIN3 (0xC0) #define GPIO_PAR_TMR_TIN3_TOUT3 (0x80) #define GPIO_PAR_TMR_TIN3_U2CTS (0x40) -#define GPIO_PAR_TMR_TIN2_MASK (0xCF) +#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF) #define GPIO_PAR_TMR_TIN2_TIN2 (0x30) #define GPIO_PAR_TMR_TIN2_TOUT2 (0x20) #define GPIO_PAR_TMR_TIN2_U2RTS (0x10) -#define GPIO_PAR_TMR_TIN1_MASK (0xF3) +#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3) #define GPIO_PAR_TMR_TIN1_TIN1 (0x0C) #define GPIO_PAR_TMR_TIN1_TOUT1 (0x08) #define GPIO_PAR_TMR_TIN1_U2RXD (0x04) -#define GPIO_PAR_TMR_TIN0_MASK (0xFC) +#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC) #define GPIO_PAR_TMR_TIN0_TIN0 (0x03) #define GPIO_PAR_TMR_TIN0_TOUT0 (0x02) #define GPIO_PAR_TMR_TIN0_U2TXD (0x01) -#define GPIO_PAR_UART1_MASK (0xF03F) -#define GPIO_PAR_UART0_MASK (0xFFC0) -#define GPIO_PAR_UART_U1CTS_MASK (0xF3FF) +#define GPIO_PAR_UART1_UNMASK (0xF03F) +#define GPIO_PAR_UART0_UNMASK (0xFFC0) +#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF) #define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00) #define GPIO_PAR_UART_U1CTS_TIN1 (0x0800) #define GPIO_PAR_UART_U1CTS_PCS1 (0x0400) -#define GPIO_PAR_UART_U1RTS_MASK (0xFCFF) +#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF) #define GPIO_PAR_UART_U1RTS_U1RTS (0x0300) #define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200) #define GPIO_PAR_UART_U1RTS_PCS1 (0x0100) #define GPIO_PAR_UART_U1TXD (0x0080) #define GPIO_PAR_UART_U1RXD (0x0040) -#define GPIO_PAR_UART_U0CTS_MASK (0xFFCF) +#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF) #define GPIO_PAR_UART_U0CTS_U0CTS (0x0030) #define GPIO_PAR_UART_U0CTS_TIN0 (0x0020) #define GPIO_PAR_UART_U0CTS_PCS0 (0x0010) -#define GPIO_PAR_UART_U0RTS_MASK (0xFFF3) +#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3) #define GPIO_PAR_UART_U0RTS_U0RTS (0x000C) #define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008) #define GPIO_PAR_UART_U0RTS_PCS0 (0x0004) #define GPIO_PAR_UART_U0TXD (0x0002) #define GPIO_PAR_UART_U0RXD (0x0001) -#define GPIO_PAR_FEC_7W_MASK (0xF3) +#define GPIO_PAR_FEC_7W_UNMASK (0xF3) #define GPIO_PAR_FEC_7W_FEC (0x0C) #define GPIO_PAR_FEC_7W_U1RTS (0x04) -#define GPIO_PAR_FEC_MII_MASK (0xFC) +#define GPIO_PAR_FEC_MII_UNMASK (0xFC) #define GPIO_PAR_FEC_MII_FEC (0x03) #define GPIO_PAR_FEC_MII_UnCTS (0x01) @@ -300,17 +299,17 @@ #define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4) #define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2) #define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03) -#define GPIO_MSCR_FB_FBCLK_MASK (0x3F) -#define GPIO_MSCR_FB_DUP_MASK (0xCF) -#define GPIO_MSCR_FB_DLO_MASK (0xF3) -#define GPIO_MSCR_FB_ADRCTL_MASK (0xFC) +#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F) +#define GPIO_MSCR_FB_DUP_UNMASK (0xCF) +#define GPIO_MSCR_FB_DLO_UNMASK (0xF3) +#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC) #define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4) #define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2) #define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03) -#define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF) -#define GPIO_MSCR_SDR_SDCLK_MASK (0xF3) -#define GPIO_MSCR_SDR_SDRAM_MASK (0xFC) +#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF) +#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3) +#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC) #define MSCR_25VDDR (0x03) #define MSCR_18VDDR_FULL (0x02) @@ -318,27 +317,27 @@ #define MSCR_18VDDR_HALF (0x00) #define GPIO_DSCR_I2C(x) ((x) & 0x03) -#define GPIO_DSCR_I2C_MASK (0xFC) +#define GPIO_DSCR_I2C_UNMASK (0xFC) #define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_MISC_DBG_MASK (0xCF) +#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF) #define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3) +#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3) #define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03) -#define GPIO_DSCR_MISC_TIMER_MASK (0xFC) +#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC) #define GPIO_DSCR_FEC(x) ((x) & 0x03) -#define GPIO_DSCR_FEC_MASK (0xFC) +#define GPIO_DSCR_FEC_UNMASK (0xFC) #define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_UART_UART1_MASK (0xCF) +#define GPIO_DSCR_UART_UART1_UNMASK (0xCF) #define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_UART_UART0_MASK (0xF3) +#define GPIO_DSCR_UART_UART0_UNMASK (0xF3) #define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03) -#define GPIO_DSCR_UART_IRQ_MASK (0xFC) +#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC) #define GPIO_DSCR_QSPI(x) ((x) & 0x03) -#define GPIO_DSCR_QSPI_MASK (0xFC) +#define GPIO_DSCR_QSPI_UNMASK (0xFC) #define DSCR_50PF (0x03) #define DSCR_30PF (0x02) @@ -347,12 +346,12 @@ /* *** Phase Locked Loop (PLL) *** */ #define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4) -#define PLL_PODR_CPUDIV_MASK (0x0F) +#define PLL_PODR_CPUDIV_UNMASK (0x0F) #define PLL_PODR_BUSDIV(x) ((x) & 0x0F) -#define PLL_PODR_BUSDIV_MASK (0xF0) +#define PLL_PODR_BUSDIV_UNMASK (0xF0) #define PLL_PCR_DITHEN (0x80) #define PLL_PCR_DITHDEV(x) ((x) & 0x07) -#define PLL_PCR_DITHDEV_MASK (0xF8) +#define PLL_PCR_DITHDEV_UNMASK (0xF8) #endif /* __M520X__ */ diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h index 824d333..c77d5dd 100644 --- a/include/asm-m68k/m5227x.h +++ b/include/asm-m68k/m5227x.h @@ -117,36 +117,34 @@ /* Bit definitions and macros for CCR */ #define CCM_CCR_DRAMSEL (0x0100) -#define CCM_CCR_CSC_MASK (0xFF3F) +#define CCM_CCR_CSC_UNMASK (0xFF3F) #define CCM_CCR_CSC_FBCS5_CS4 (0x00C0) #define CCM_CCR_CSC_FBCS5_A22 (0x0080) #define CCM_CCR_CSC_FB_A23_A22 (0x0040) #define CCM_CCR_LIMP (0x0020) #define CCM_CCR_LOAD (0x0010) -#define CCM_CCR_BOOTPS_MASK (0xFFF3) +#define CCM_CCR_BOOTPS_UNMASK (0xFFF3) #define CCM_CCR_BOOTPS_PS16 (0x0008) #define CCM_CCR_BOOTPS_PS8 (0x0004) #define CCM_CCR_BOOTPS_PS32 (0x0000) #define CCM_CCR_OSCMODE_OSCBYPASS (0x0002) /* Bit definitions and macros for RCON */ -#define CCM_RCON_CSC_MASK (0xFF3F) +#define CCM_RCON_CSC_UNMASK (0xFF3F) #define CCM_RCON_CSC_FBCS5_CS4 (0x00C0) #define CCM_RCON_CSC_FBCS5_A22 (0x0080) #define CCM_RCON_CSC_FB_A23_A22 (0x0040) #define CCM_RCON_LIMP (0x0020) #define CCM_RCON_LOAD (0x0010) -#define CCM_RCON_BOOTPS_MASK (0xFFF3) +#define CCM_RCON_BOOTPS_UNMASK (0xFFF3) #define CCM_RCON_BOOTPS_PS16 (0x0008) #define CCM_RCON_BOOTPS_PS8 (0x0004) #define CCM_RCON_BOOTPS_PS32 (0x0000) #define CCM_RCON_OSCMODE_OSCBYPASS (0x0002) /* Bit definitions and macros for CIR */ -#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ -#define CCM_CIR_PIN_MASK (0xFFC0) -#define CCM_CIR_PRN_MASK (0x003F) +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) #define CCM_CIR_PIN_MCF52277 (0x0000) /* Bit definitions and macros for MISCCR */ @@ -195,7 +193,7 @@ * General Purpose I/O Module (GPIO) *********************************************************************/ /* Bit definitions and macros for PAR_BE */ -#define GPIO_PAR_BE_MASK (0x0F) +#define GPIO_PAR_BE_UNMASK (0x0F) #define GPIO_PAR_BE_BE3_BE3 (0x08) #define GPIO_PAR_BE_BE3_GPIO (0x00) #define GPIO_PAR_BE_BE2_BE2 (0x04) @@ -217,111 +215,111 @@ #define GPIO_PAR_FBCTL_OE (0x80) #define GPIO_PAR_FBCTL_TA (0x40) #define GPIO_PAR_FBCTL_RW (0x20) -#define GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) #define GPIO_PAR_FBCTL_TS_FBTS (0x18) #define GPIO_PAR_FBCTL_TS_DMAACK (0x10) #define GPIO_PAR_FBCTL_TS_GPIO (0x00) /* Bit definitions and macros for PAR_FECI2C */ -#define GPIO_PAR_I2C_SCL_MASK (0xF3) +#define GPIO_PAR_I2C_SCL_UNMASK (0xF3) #define GPIO_PAR_I2C_SCL_SCL (0x0C) #define GPIO_PAR_I2C_SCL_CANTXD (0x08) #define GPIO_PAR_I2C_SCL_U2TXD (0x04) #define GPIO_PAR_I2C_SCL_GPIO (0x00) -#define GPIO_PAR_I2C_SDA_MASK (0xFC) +#define GPIO_PAR_I2C_SDA_UNMASK (0xFC) #define GPIO_PAR_I2C_SDA_SDA (0x03) #define GPIO_PAR_I2C_SDA_CANRXD (0x02) #define GPIO_PAR_I2C_SDA_U2RXD (0x01) #define GPIO_PAR_I2C_SDA_GPIO (0x00) /* Bit definitions and macros for PAR_UART */ -#define GPIO_PAR_UART_U1CTS_MASK (0x3FFF) +#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF) #define GPIO_PAR_UART_U1CTS_U1CTS (0xC000) #define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000) #define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000) #define GPIO_PAR_UART_U1CTS_GPIO (0x0000) -#define GPIO_PAR_UART_U1RTS_MASK (0xCFFF) +#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF) #define GPIO_PAR_UART_U1RTS_U1RTS (0x3000) #define GPIO_PAR_UART_U1RTS_SSIFS (0x2000) #define GPIO_PAR_UART_U1RTS_LCDPS (0x1000) #define GPIO_PAR_UART_U1RTS_GPIO (0x0000) -#define GPIO_PAR_UART_U1RXD_MASK (0xF3FF) +#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF) #define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) #define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800) #define GPIO_PAR_UART_U1RXD_GPIO (0x0000) -#define GPIO_PAR_UART_U1TXD_MASK (0xFCFF) +#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF) #define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) #define GPIO_PAR_UART_U1TXD_SSITXD (0x0200) #define GPIO_PAR_UART_U1TXD_GPIO (0x0000) -#define GPIO_PAR_UART_U0CTS_MASK (0xFF3F) +#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F) #define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0) #define GPIO_PAR_UART_U0CTS_T1OUT (0x0080) #define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040) #define GPIO_PAR_UART_U0CTS_GPIO (0x0000) -#define GPIO_PAR_UART_U0RTS_MASK (0xFFCF) +#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF) #define GPIO_PAR_UART_U0RTS_U0RTS (0x0030) #define GPIO_PAR_UART_U0RTS_T1IN (0x0020) #define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010) #define GPIO_PAR_UART_U0RTS_GPIO (0x0000) -#define GPIO_PAR_UART_U0RXD_MASK (0xFFF3) +#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3) #define GPIO_PAR_UART_U0RXD_U0RXD (0x000C) #define GPIO_PAR_UART_U0RXD_CANRX (0x0008) #define GPIO_PAR_UART_U0RXD_GPIO (0x0000) -#define GPIO_PAR_UART_U0TXD_MASK (0xFFFC) +#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC) #define GPIO_PAR_UART_U0TXD_U0TXD (0x0003) #define GPIO_PAR_UART_U0TXD_CANTX (0x0002) #define GPIO_PAR_UART_U0TXD_GPIO (0x0000) /* Bit definitions and macros for PAR_DSPI */ -#define GPIO_PAR_DSPI_PCS0_MASK (0x3F) +#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F) #define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0) #define GPIO_PAR_DSPI_PCS0_U2RTS (0x80) #define GPIO_PAR_DSPI_PCS0_GPIO (0x00) -#define GPIO_PAR_DSPI_SIN_MASK (0xCF) +#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF) #define GPIO_PAR_DSPI_SIN_SIN (0x30) #define GPIO_PAR_DSPI_SIN_U2RXD (0x20) #define GPIO_PAR_DSPI_SIN_GPIO (0x00) -#define GPIO_PAR_DSPI_SOUT_MASK (0xF3) +#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3) #define GPIO_PAR_DSPI_SOUT_SOUT (0x0C) #define GPIO_PAR_DSPI_SOUT_U2TXD (0x08) #define GPIO_PAR_DSPI_SOUT_GPIO (0x00) -#define GPIO_PAR_DSPI_SCK_MASK (0xFC) +#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC) #define GPIO_PAR_DSPI_SCK_SCK (0x03) #define GPIO_PAR_DSPI_SCK_U2CTS (0x02) #define GPIO_PAR_DSPI_SCK_GPIO (0x00) /* Bit definitions and macros for PAR_TIMER */ -#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) #define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40) #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) #define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10) #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) #define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04) #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) #define GPIO_PAR_TIMER_T0IN_LCDREV (0x01) #define GPIO_PAR_TIMER_T0IN_GPIO (0x00) /* Bit definitions and macros for GPIO_PAR_LCDCTL */ -#define GPIO_PAR_LCDCTL_ACDOE_MASK (0xE7) +#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7) #define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18) #define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10) #define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00) @@ -330,141 +328,141 @@ #define GPIO_PAR_LCDCTL_LSCLK (0x01) /* Bit definitions and macros for PAR_IRQ */ -#define GPIO_PAR_IRQ_IRQ4_MASK (0xF3) +#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3) #define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C) #define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08) #define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) -#define GPIO_PAR_IRQ_IRQ1_MASK (0xFC) +#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC) #define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03) #define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02) #define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01) #define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) /* Bit definitions and macros for GPIO_PAR_LCDH */ -#define GPIO_PAR_LCDH_LD17_MASK (0xFFFFF3FF) +#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF) #define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00) #define GPIO_PAR_LCDH_LD17_LD11 (0x00000800) #define GPIO_PAR_LCDH_LD17_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD16_MASK (0xFFFFFCFF) +#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF) #define GPIO_PAR_LCDH_LD16_LD16 (0x00000300) #define GPIO_PAR_LCDH_LD16_LD10 (0x00000200) #define GPIO_PAR_LCDH_LD16_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD15_MASK (0xFFFFFF3F) +#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F) #define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0) #define GPIO_PAR_LCDH_LD15_LD9 (0x00000080) #define GPIO_PAR_LCDH_LD15_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD14_MASK (0xFFFFFFCF) +#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF) #define GPIO_PAR_LCDH_LD14_LD14 (0x00000030) #define GPIO_PAR_LCDH_LD14_LD8 (0x00000020) #define GPIO_PAR_LCDH_LD14_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD13_MASK (0xFFFFFFF3) +#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3) #define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C) #define GPIO_PAR_LCDH_LD13_CANTX (0x00000008) #define GPIO_PAR_LCDH_LD13_GPIO (0x00000000) -#define GPIO_PAR_LCDH_LD12_MASK (0xFFFFFFFC) +#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC) #define GPIO_PAR_LCDH_LD12_LD12 (0x00000003) #define GPIO_PAR_LCDH_LD12_CANRX (0x00000002) #define GPIO_PAR_LCDH_LD12_GPIO (0x00000000) /* Bit definitions and macros for GPIO_PAR_LCDL */ -#define GPIO_PAR_LCDL_LD11_MASK (0x3FFFFFFF) +#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF) #define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000) #define GPIO_PAR_LCDL_LD11_LD7 (0x80000000) #define GPIO_PAR_LCDL_LD11_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD10_MASK (0xCFFFFFFF) +#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF) #define GPIO_PAR_LCDL_LD10_LD10 (0x30000000) #define GPIO_PAR_LCDL_LD10_LD6 (0x20000000) #define GPIO_PAR_LCDL_LD10_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD9_MASK (0xF3FFFFFF) +#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF) #define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000) #define GPIO_PAR_LCDL_LD9_LD5 (0x08000000) #define GPIO_PAR_LCDL_LD9_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD8_MASK (0xFCFFFFFF) +#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF) #define GPIO_PAR_LCDL_LD8_LD8 (0x03000000) #define GPIO_PAR_LCDL_LD8_LD4 (0x02000000) #define GPIO_PAR_LCDL_LD8_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD7_MASK (0xFF3FFFFF) +#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF) #define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000) #define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000) #define GPIO_PAR_LCDL_LD7_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD6_MASK (0xFFCFFFFF) +#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF) #define GPIO_PAR_LCDL_LD6_LD6 (0x00300000) #define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000) #define GPIO_PAR_LCDL_LD6_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD5_MASK (0xFFF3FFFF) +#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF) #define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000) #define GPIO_PAR_LCDL_LD5_LD3 (0x00080000) #define GPIO_PAR_LCDL_LD5_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD4_MASK (0xFFFCFFFF) +#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF) #define GPIO_PAR_LCDL_LD4_LD4 (0x00030000) #define GPIO_PAR_LCDL_LD4_LD2 (0x00020000) #define GPIO_PAR_LCDL_LD4_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD3_MASK (0xFFFF3FFF) +#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF) #define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000) #define GPIO_PAR_LCDL_LD3_LD1 (0x00008000) #define GPIO_PAR_LCDL_LD3_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD2_MASK (0xFFFFCFFF) +#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF) #define GPIO_PAR_LCDL_LD2_LD2 (0x00003000) #define GPIO_PAR_LCDL_LD2_LD0 (0x00002000) #define GPIO_PAR_LCDL_LD2_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD1_MASK (0xFFFFF3FF) +#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF) #define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00) #define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800) #define GPIO_PAR_LCDL_LD1_GPIO (0x00000000) -#define GPIO_PAR_LCDL_LD0_MASK (0xFFFFFCFF) +#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF) #define GPIO_PAR_LCDL_LD0_LD0 (0x00000300) #define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200) #define GPIO_PAR_LCDL_LD0_GPIO (0x00000000) /* Bit definitions and macros for MSCR_FB */ -#define GPIO_MSCR_FB_DUPPER_MASK (0xCF) +#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF) #define GPIO_MSCR_FB_DUPPER_25V_33V (0x30) #define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20) #define GPIO_MSCR_FB_DUPPER_OD (0x10) #define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00) -#define GPIO_MSCR_FB_DLOWER_MASK (0xF3) +#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3) #define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C) #define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08) #define GPIO_MSCR_FB_DLOWER_OD (0x04) #define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00) -#define GPIO_MSCR_FB_ADDRCTL_MASK (0xFC) +#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC) #define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03) #define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02) #define GPIO_MSCR_FB_ADDRCTL_OD (0x01) #define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00) /* Bit definitions and macros for MSCR_SDRAM */ -#define GPIO_MSCR_SDRAM_SDCLKB_MASK (0xCF) +#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF) #define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30) #define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20) #define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10) #define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00) -#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) #define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C) #define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08) #define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04) #define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00) -#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) #define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03) #define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02) #define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01) diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h index 22987ac..71a40d3 100644 --- a/include/asm-m68k/m5235.h +++ b/include/asm-m68k/m5235.h @@ -557,8 +557,8 @@ #define CCM_RCON_MODE (0x0001) /* Bit definitions and macros for CCM_CIR */ -#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) -#define CCM_CIR_PRN(x) ((x)&0x003F) +#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) /********************************************************************* * PLL Clock Module diff --git a/include/asm-m68k/m5301x.h b/include/asm-m68k/m5301x.h index 80cefc4..0920a0d 100644 --- a/include/asm-m68k/m5301x.h +++ b/include/asm-m68k/m5301x.h @@ -254,7 +254,7 @@ #define CCM_MISCCR_PLL_LOCK (0x2000) #define CCM_MISCCR_LIMP (0x1000) #define CCM_MISCCR_BME (0x8000) -#define CCM_MISCCR_BMT_MASK (0xF8FF) +#define CCM_MISCCR_BMT_UNMASK (0xF8FF) #define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) #define CCM_MISCCR_BMT_512 (0x0700) #define CCM_MISCCR_BMT_1024 (0x0600) @@ -330,32 +330,32 @@ #define GPIO_PAR_CS5 (0x40) #define GPIO_PAR_CS4 (0x10) -#define GPIO_PAR_CS1_MASK (0xF3) +#define GPIO_PAR_CS1_UNMASK (0xF3) #define GPIO_PAR_CS1_CS1 (0x0C) #define GPIO_PAR_CS1_SDCS1 (0x08) -#define GPIO_PAR_CS0_MASK (0xFC) +#define GPIO_PAR_CS0_UNMASK (0xFC) #define GPIO_PAR_CS0_CS0 (0x03) #define GPIO_PAR_CS0_CS4 (0x02) -#define GPIO_PAR_DSPIH_SIN_MASK (0x3F) +#define GPIO_PAR_DSPIH_SIN_UNMASK (0x3F) #define GPIO_PAR_DSPIH_SIN (0xC0) #define GPIO_PAR_DSPIH_SIN_U2RXD (0x80) -#define GPIO_PAR_DSPIH_SOUT_MASK (0xCF) +#define GPIO_PAR_DSPIH_SOUT_UNMASK (0xCF) #define GPIO_PAR_DSPIH_SOUT (0x30) #define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20) -#define GPIO_PAR_DSPIH_SCK_MASK (0xF3) +#define GPIO_PAR_DSPIH_SCK_UNMASK (0xF3) #define GPIO_PAR_DSPIH_SCK (0x0C) #define GPIO_PAR_DSPIH_SCK_U2CTS (0x08) -#define GPIO_PAR_DSPIH_PCS0_MASK (0xFC) +#define GPIO_PAR_DSPIH_PCS0_UNMASK (0xFC) #define GPIO_PAR_DSPIH_PCS0 (0x03) #define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02) -#define GPIO_PAR_DSPIL_PCS1_MASK (0x3F) +#define GPIO_PAR_DSPIL_PCS1_UNMASK (0x3F) #define GPIO_PAR_DSPIL_PCS1 (0xC0) -#define GPIO_PAR_DSPIL_PCS2_MASK (0xCF) +#define GPIO_PAR_DSPIL_PCS2_UNMASK (0xCF) #define GPIO_PAR_DSPIL_PCS2 (0x30) #define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20) -#define GPIO_PAR_DSPIL_PCS3_MASK (0xF3) +#define GPIO_PAR_DSPIL_PCS3_UNMASK (0xF3) #define GPIO_PAR_DSPIL_PCS3 (0x0C) #define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08) @@ -365,30 +365,30 @@ #define GPIO_PAR_FEC0_RMII_FEC (0x01) /* GPIO_PAR_FECI2C */ -#define GPIO_PAR_FECI2C_RMII0_MASK (0x3F) +#define GPIO_PAR_FECI2C_RMII0_UNMASK (0x3F) #define GPIO_PAR_FECI2C_MDC0 (0x80) #define GPIO_PAR_FECI2C_MDIO0 (0x40) -#define GPIO_PAR_FECI2C_RMII1_MASK (0xCF) +#define GPIO_PAR_FECI2C_RMII1_UNMASK (0xCF) #define GPIO_PAR_FECI2C_MDC1 (0x20) #define GPIO_PAR_FECI2C_MDIO1 (0x10) -#define GPIO_PAR_FECI2C_SDA_MASK (0xF3) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xF3) #define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2) #define GPIO_PAR_FECI2C_SDA_SDA (0x0C) #define GPIO_PAR_FECI2C_SDA_U2TXD (0x08) #define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04) -#define GPIO_PAR_FECI2C_SCL_MASK (0xFC) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFC) #define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03) #define GPIO_PAR_FECI2C_SCL_SCL (0x03) #define GPIO_PAR_FECI2C_SCL_U2RXD (0x02) #define GPIO_PAR_FECI2C_SCL_MDC1 (0x01) -#define GPIO_PAR_IRQ0H_IRQ07_MASK (0x3F) -#define GPIO_PAR_IRQ0H_IRQ06_MASK (0xCF) +#define GPIO_PAR_IRQ0H_IRQ07_UNMASK (0x3F) +#define GPIO_PAR_IRQ0H_IRQ06_UNMASK (0xCF) #define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10) -#define GPIO_PAR_IRQ0H_IRQ04_MASK (0xFC) +#define GPIO_PAR_IRQ0H_IRQ04_UNMASK (0xFC) #define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02) -#define GPIO_PAR_IRQ0L_IRQ01_MASK (0xF3) +#define GPIO_PAR_IRQ0L_IRQ01_UNMASK (0xF3) #define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08) #define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40) @@ -401,24 +401,24 @@ #define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04) #define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01) -#define GPIO_PAR_SIMP1H_DATA1_MASK (0x3F) +#define GPIO_PAR_SIMP1H_DATA1_UNMASK (0x3F) #define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0) #define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80) #define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40) -#define GPIO_PAR_SIMP1H_VEN1_MASK (0xCF) +#define GPIO_PAR_SIMP1H_VEN1_UNMASK (0xCF) #define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30) #define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20) #define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10) -#define GPIO_PAR_SIMP1H_RST1_MASK (0xF3) +#define GPIO_PAR_SIMP1H_RST1_UNMASK (0xF3) #define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C) #define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08) #define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04) -#define GPIO_PAR_SIMP1H_PD1_MASK (0xFC) +#define GPIO_PAR_SIMP1H_PD1_UNMASK (0xFC) #define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03) #define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02) #define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01) -#define GPIO_PAR_SIMP1L_CLK_MASK (0x3F) +#define GPIO_PAR_SIMP1L_CLK_UNMASK (0x3F) #define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0) #define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80) @@ -432,19 +432,19 @@ #define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4) #define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2) #define GPIO_PAR_TIN0(x) ((x) & 0x03) -#define GPIO_PAR_TIN3_MASK (0x3F) +#define GPIO_PAR_TIN3_UNMASK (0x3F) #define GPIO_PAR_TIN3_TIN3 (0xC0) #define GPIO_PAR_TIN3_TOUT3 (0x80) #define GPIO_PAR_TIN3_IRQ03 (0x40) -#define GPIO_PAR_TIN2_MASK (0xCF) +#define GPIO_PAR_TIN2_UNMASK (0xCF) #define GPIO_PAR_TIN2_TIN2 (0x30) #define GPIO_PAR_TIN2_TOUT2 (0x20) #define GPIO_PAR_TIN2_IRQ02 (0x10) -#define GPIO_PAR_TIN1_MASK (0xF3) +#define GPIO_PAR_TIN1_UNMASK (0xF3) #define GPIO_PAR_TIN1_TIN1 (0x0C) #define GPIO_PAR_TIN1_TOUT1 (0x08) #define GPIO_PAR_TIN1_DACK1 (0x04) -#define GPIO_PAR_TIN0_MASK (0xFC) +#define GPIO_PAR_TIN0_UNMASK (0xFC) #define GPIO_PAR_TIN0_TIN0 (0x03) #define GPIO_PAR_TIN0_TOUT0 (0x02) #define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01) @@ -455,10 +455,10 @@ #define GPIO_PAR_UART_U0RXD (0x10) #define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2) #define GPIO_PAR_UART_CTS0(x) ((x) & 0x03) -#define GPIO_PAR_UART_RTS0_MASK (0xF3) +#define GPIO_PAR_UART_RTS0_UNMASK (0xF3) #define GPIO_PAR_UART_RTS0_U0RTS (0x0C) #define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08) -#define GPIO_PAR_UART_CTS0_MASK (0xFC) +#define GPIO_PAR_UART_CTS0_UNMASK (0xFC) #define GPIO_PAR_UART_CTS0_U0CTS (0x03) #define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02) #define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01) @@ -476,20 +476,20 @@ #define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4) #define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2) #define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03) -#define GPIO_PAR_SSIH_RXD_MASK (0x3F) +#define GPIO_PAR_SSIH_RXD_UNMASK (0x3F) #define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0) #define GPIO_PAR_SSIH_RXD_U1RXD (0x40) -#define GPIO_PAR_SSIH_TXD_MASK (0xCF) +#define GPIO_PAR_SSIH_TXD_UNMASK (0xCF) #define GPIO_PAR_SSIH_TXD_SSIRXD (0x30) #define GPIO_PAR_SSIH_TXD_U1TXD (0x10) -#define GPIO_PAR_SSIH_FS_MASK (0xF3) +#define GPIO_PAR_SSIH_FS_UNMASK (0xF3) #define GPIO_PAR_SSIH_FS_SSIFS (0x0C) #define GPIO_PAR_SSIH_FS_U1RTS (0x04) -#define GPIO_PAR_SSIH_MCLK_MASK (0xFC) +#define GPIO_PAR_SSIH_MCLK_UNMASK (0xFC) #define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03) #define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01) -#define GPIO_PAR_SSIL_MASK (0x3F) +#define GPIO_PAR_SSIL_UNMASK (0x3F) #define GPIO_PAR_SSIL_BCLK (0xC0) #define GPIO_PAR_SSIL_U1CTS (0x40) @@ -497,40 +497,40 @@ #define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5) #define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5) #define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5) -#define GPIO_MSCR_MSCRn_MASK (0x1F) +#define GPIO_MSCR_MSCRn_UNMASK (0x1F) #define GPIO_MSCR_MSCRn_SDR (0xE0) #define GPIO_MSCR_MSCRn_25VDDR (0x60) #define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20) #define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00) #define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2) -#define GPIO_MSCR_MSCR5_MASK (0xE3) +#define GPIO_MSCR_MSCR5_UNMASK (0xE3) #define GPIO_MSCR_MSCR5_SDR (0x1C) #define GPIO_MSCR_MSCR5_25VDDR (0x0C) #define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04) #define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00) -#define GPIO_SRCR_DSPI_MASK (0xFC) +#define GPIO_SRCR_DSPI_UNMASK (0xFC) #define GPIO_SRCR_DSPI(x) ((x) & 0x03) -#define GPIO_SRCR_I2C_MASK (0xFC) +#define GPIO_SRCR_I2C_UNMASK (0xFC) #define GPIO_SRCR_I2C(x) ((x) & 0x03) -#define GPIO_SRCR_IRQ_IRQ0_MASK (0xF3) +#define GPIO_SRCR_IRQ_IRQ0_UNMASK (0xF3) #define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_IRQ_IRQ1DBG_MASK (0xFC) +#define GPIO_SRCR_IRQ_IRQ1DBG_UNMASK (0xFC) #define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03) -#define GPIO_SRCR_SIM_SIMP0_MASK (0xF3) +#define GPIO_SRCR_SIM_SIMP0_UNMASK (0xF3) #define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_SIM_SIMP1_MASK (0xFC) +#define GPIO_SRCR_SIM_SIMP1_UNMASK (0xFC) #define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03) -#define GPIO_SRCR_TIMER_MASK (0xFC) +#define GPIO_SRCR_TIMER_UNMASK (0xFC) #define GPIO_SRCR_TIMER(x) ((x) & 0x03) -#define GPIO_SRCR_UART2_MASK (0xF3) +#define GPIO_SRCR_UART2_UNMASK (0xF3) #define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2) -#define GPIO_SRCR_UART0_MASK (0xFC) +#define GPIO_SRCR_UART0_UNMASK (0xFC) #define GPIO_SRCR_UART0(x) ((x) & 0x03) -#define GPIO_SRCR_SDHC_MASK (0xFC) +#define GPIO_SRCR_SDHC_UNMASK (0xFC) #define GPIO_SRCR_SDHC(x) ((x) & 0x03) -#define GPIO_SRCR_SSI_MASK (0xFC) +#define GPIO_SRCR_SSI_UNMASK (0xFC) #define GPIO_SRCR_SSI(x) ((x) & 0x03) #define SRCR_HIGHEST (0x03) @@ -538,11 +538,11 @@ #define SRCR_LOW (0x01) #define SRCR_LOWEST (0x00) -#define GPIO_DSCR_FEC_RMIICLK_MASK (0xCF) +#define GPIO_DSCR_FEC_RMIICLK_UNMASK (0xCF) #define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_FEC_RMII0_MASK (0xF3) +#define GPIO_DSCR_FEC_RMII0_UNMASK (0xF3) #define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_FEC_RMII1_MASK (0xFC) +#define GPIO_DSCR_FEC_RMII1_UNMASK (0xFC) #define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03) #define DSCR_50PF (0x03) @@ -572,18 +572,18 @@ #define PLL_PCR_LOL_IRQ (0x00004000) #define PLL_PCR_LOL_RE (0x00002000) #define PLL_PCR_LOL_EN (0x00001000) -#define PLL_PCR_REFDIV_MASK (0xFFFFF8FF) +#define PLL_PCR_REFDIV_UNMASK (0xFFFFF8FF) #define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8) -#define PLL_PCR_FBDIV_MASK (0xFFFFFFC0) +#define PLL_PCR_FBDIV_UNMASK (0xFFFFFFC0) #define PLL_PCR_FBDIV(x) ((x) & 0x3F) -#define PLL_PDR_OUTDIV4_MASK (0x0FFF) +#define PLL_PDR_OUTDIV4_UNMASK (0x0FFF) #define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12) -#define PLL_PDR_OUTDIV3_MASK (0xF0FF) +#define PLL_PDR_OUTDIV3_UNMASK (0xF0FF) #define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8) -#define PLL_PDR_OUTDIV2_MASK (0xFF0F) +#define PLL_PDR_OUTDIV2_UNMASK (0xFF0F) #define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4) -#define PLL_PDR_OUTDIV1_MASK (0xFFF0) +#define PLL_PDR_OUTDIV1_UNMASK (0xFFF0) #define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F) #define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x) #define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x) diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h index 5966621..dfddde6 100644 --- a/include/asm-m68k/m5445x.h +++ b/include/asm-m68k/m5445x.h @@ -286,13 +286,13 @@ /* Bit definitions and macros for PAR_FEC */ #define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) #define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) -#define GPIO_PAR_FEC_FEC1_MASK (0x8F) +#define GPIO_PAR_FEC_FEC1_UNMASK (0x8F) #define GPIO_PAR_FEC_FEC1_MII (0x70) #define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) #define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) #define GPIO_PAR_FEC_FEC1_ATA (0x10) #define GPIO_PAR_FEC_FEC1_GPIO (0x00) -#define GPIO_PAR_FEC_FEC0_MASK (0xF8) +#define GPIO_PAR_FEC_FEC0_UNMASK (0xF8) #define GPIO_PAR_FEC_FEC0_MII (0x07) #define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) #define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) @@ -304,15 +304,15 @@ #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) -#define GPIO_PAR_DMA_DACK1_MASK (0x3F) +#define GPIO_PAR_DMA_DACK1_UNMASK (0x3F) #define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) #define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) #define GPIO_PAR_DMA_DACK1_GPIO (0x00) -#define GPIO_PAR_DMA_DREQ1_MASK (0xCF) +#define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF) #define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) #define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) #define GPIO_PAR_DMA_DREQ1_GPIO (0x00) -#define GPIO_PAR_DMA_DACK0_MASK (0xF3) +#define GPIO_PAR_DMA_DACK0_UNMASK (0xF3) #define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) #define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) #define GPIO_PAR_DMA_DACK0_GPIO (0x00) @@ -330,7 +330,7 @@ #define GPIO_PAR_FBCTL_TA_GPIO (0x00) #define GPIO_PAR_FBCTL_RW_RW (0x20) #define GPIO_PAR_FBCTL_RW_GPIO (0x00) -#define GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) #define GPIO_PAR_FBCTL_TS_TS (0x18) #define GPIO_PAR_FBCTL_TS_ALE (0x10) #define GPIO_PAR_FBCTL_TS_TBST (0x08) @@ -364,11 +364,11 @@ #define GPIO_PAR_BE_BS1 (0x04) #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) -#define GPIO_PAR_BE_BE3_MASK (0x3F) +#define GPIO_PAR_BE_BE3_UNMASK (0x3F) #define GPIO_PAR_BE_BE3_BE3 (0xC0) #define GPIO_PAR_BE_BE3_TSIZ1 (0x80) #define GPIO_PAR_BE_BE3_GPIO (0x00) -#define GPIO_PAR_BE_BE2_MASK (0xCF) +#define GPIO_PAR_BE_BE2_UNMASK (0xCF) #define GPIO_PAR_BE_BE2_BE2 (0x30) #define GPIO_PAR_BE_BE2_TSIZ0 (0x20) #define GPIO_PAR_BE_BE2_GPIO (0x00) @@ -393,22 +393,22 @@ #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) -#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) #define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) #define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) #define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) #define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) @@ -417,12 +417,12 @@ /* Bit definitions and macros for PAR_USB */ #define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) #define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) -#define GPIO_PAR_USB_VBUSEN_MASK (0xF3) +#define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3) #define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) #define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) #define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) #define GPIO_PAR_USB_VBUSEN_GPIO (0x00) -#define GPIO_PAR_USB_VBUSOC_MASK (0xFC) +#define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC) #define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) #define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) #define GPIO_PAR_USB_VBUSOC_GPIO (0x00) @@ -460,11 +460,11 @@ #define GPIO_PAR_FECI2C_MDC0 (0x0040) #define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) #define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) -#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF) +#define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF) #define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) #define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) #define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) -#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF) +#define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF) #define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) #define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) #define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) @@ -472,11 +472,11 @@ #define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) #define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) #define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) -#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3) +#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3) #define GPIO_PAR_FECI2C_SCL_SCL (0x000C) #define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) #define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) -#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC) +#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC) #define GPIO_PAR_FECI2C_SDA_SDA (0x0003) #define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) #define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) @@ -487,19 +487,19 @@ #define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) -#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF) +#define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF) #define GPIO_PAR_SSI_BCLK_BCLK (0x0300) #define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) #define GPIO_PAR_SSI_BCLK_GPIO (0x0000) -#define GPIO_PAR_SSI_FS_MASK (0xFF3F) +#define GPIO_PAR_SSI_FS_UNMASK (0xFF3F) #define GPIO_PAR_SSI_FS_FS (0x00C0) #define GPIO_PAR_SSI_FS_U1RTS (0x0080) #define GPIO_PAR_SSI_FS_GPIO (0x0000) -#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF) +#define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF) #define GPIO_PAR_SSI_SRXD_SRXD (0x0030) #define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) #define GPIO_PAR_SSI_SRXD_GPIO (0x0000) -#define GPIO_PAR_SSI_STXD_MASK (0xFFF3) +#define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3) #define GPIO_PAR_SSI_STXD_STXD (0x000C) #define GPIO_PAR_SSI_STXD_U1TXD (0x0008) #define GPIO_PAR_SSI_STXD_GPIO (0x0000) @@ -552,7 +552,7 @@ #define GPIO_PAR_PCI_GNT1 (0x0400) #define GPIO_PAR_PCI_GNT2 (0x1000) #define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) -#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF) +#define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF) #define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) #define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) #define GPIO_PAR_PCI_GNT3_GPIO (0x0000) @@ -562,7 +562,7 @@ #define GPIO_PAR_PCI_GNT1_GPIO (0x0000) #define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) #define GPIO_PAR_PCI_GNT0_GPIO (0x0000) -#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F) +#define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F) #define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) #define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) #define GPIO_PAR_PCI_REQ3_GPIO (0x0000) @@ -578,22 +578,22 @@ #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) #define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) #define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) -#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F) +#define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F) #define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) #define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) #define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) #define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF) +#define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF) #define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) #define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) #define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) #define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) #define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) #define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) #define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) #define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) -#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) #define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) #define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) #define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) -- cgit v1.1 From 52affe04fa5493597d8a5f6202507190950a32e6 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Tue, 9 Mar 2010 19:17:52 -0600 Subject: ColdFire: Update processors' serial port configuration Provide parameter passing to uart_port_config(). Update port configuration - un-mask it before enable the bits. Signed-off-by: TsiChung Liew --- include/asm-m68k/immap_5253.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h index b5a4cb5..28cd107 100644 --- a/include/asm-m68k/immap_5253.h +++ b/include/asm-m68k/immap_5253.h @@ -37,6 +37,7 @@ #define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) #define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) +#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C) #define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) #define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) -- cgit v1.1 From ac265f7fcab1a09b9a837a34ef8b10acc101695e Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Wed, 10 Mar 2010 11:56:36 -0600 Subject: ColdFire: Update M5253DEMO configuration file Fix incorrect default environment for flash erase or protect range. Change offset from 0 to 0xff80nnnn. Remove default ethernet setup and MAC address. Signed-off-by: TsiChung Liew --- include/configs/M5253DEMO.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 5e86e4c..f813f88 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -95,11 +95,6 @@ # define DM9000_DATA (CONFIG_DM9000_BASE + 4) # undef CONFIG_DM9000_DEBUG -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 10.82.121.249 -# define CONFIG_NETMASK 255.255.252.0 -# define CONFIG_SERVERIP 10.82.120.80 -# define CONFIG_GATEWAYIP 10.82.123.254 # define CONFIG_OVERWRITE_ETHADDR_ONCE # define CONFIG_EXTRA_ENV_SETTINGS \ @@ -109,8 +104,8 @@ "u-boot=u-boot.bin\0" \ "load=tftp ${loadaddr) ${u-boot}\0" \ "upd=run load; run prog\0" \ - "prog=prot off 0 2ffff;" \ - "era 0 2ffff;" \ + "prog=prot off 0xff800000 0xff82ffff;" \ + "era 0xff800000 0xff82ffff;" \ "cp.b ${loadaddr} 0 ${filesize};" \ "save\0" \ "" -- cgit v1.1 From 0e8a75550695aba9d8cfe9c7f7713da42c1f3e89 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Wed, 10 Mar 2010 16:33:03 -0600 Subject: ColdFire: Update Extra environment Data for M5275EVB Provide extra environment Data. Remove default network address and MAC address. Signed-off-by: TsiChung Liew --- include/configs/M5275EVB.h | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index b380159..f8d43f0 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -121,11 +121,6 @@ #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) -#ifdef CONFIG_MCFFEC -#define CONFIG_ETHADDR 00:06:3b:01:41:55 -#define CONFIG_ETH1ADDR 00:0e:0c:bc:e5:60 -#endif - #define CONFIG_SYS_PROMPT "-> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -145,6 +140,23 @@ #define CONFIG_SYS_MEMTEST_START 0x400 #define CONFIG_SYS_MEMTEST_END 0x380000 +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_RETRY_COUNT 5 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${uboot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 150000000 -- cgit v1.1 From 9e8e927023582231b034e199568e49f84ac032a9 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Wed, 10 Mar 2010 18:24:07 -0600 Subject: ColdFire: Misc update for M53017 Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update DRAM control and SRAM control register setting. Update cache setting where size does not write to proper region. Signed-off-by: TsiChung Liew Signed-off-by: Jason Jin --- include/configs/M53017EVB.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 30855bd..c351d41 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -69,6 +69,8 @@ # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY # define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_TX_ETH_BUFFER 8 +# define CONFIG_SYS_FEC_BUF_USE_SRAM # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_HAS_ETH1 @@ -166,7 +168,7 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET @@ -180,7 +182,7 @@ #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ #define CONFIG_SYS_SDRAM_CFG1 0x43711630 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 -- cgit v1.1 From f628e2f72daee810aa568619b6629da68ad042d6 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Wed, 10 Mar 2010 18:50:22 -0600 Subject: ColdFire: Fix SDRAM size on M5208evb rev E The proper SDRAM size is 32MB not 64MB Signed-off-by: Jingchang Lu --- include/configs/M5208EVBE.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 32123d2..3cc259f 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -158,7 +158,7 @@ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ #define CONFIG_SYS_SDRAM_CFG1 0x43711630 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 -- cgit v1.1 From dd9f054ede433de73b137987fb3dc066e8d24ebb Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Thu, 11 Mar 2010 22:12:53 -0600 Subject: ColdFire: Cache update for all platforms The CF will call cache functions in lib_m68/cache.c and the cache settings are defined in platform configuration file. Signed-off-by: TsiChung Liew --- include/asm-m68k/cache.h | 210 +++++++++++++++++++++++++++++++++++++++ include/configs/EB+MCF-EV123.h | 12 +++ include/configs/M5208EVBE.h | 13 +++ include/configs/M52277EVB.h | 13 +++ include/configs/M5235EVB.h | 12 +++ include/configs/M5249EVB.h | 15 +++ include/configs/M5253DEMO.h | 15 +++ include/configs/M5253EVBE.h | 15 +++ include/configs/M5271EVB.h | 14 +++ include/configs/M5272C3.h | 14 +++ include/configs/M5275EVB.h | 14 +++ include/configs/M5282EVB.h | 13 +++ include/configs/M53017EVB.h | 11 ++ include/configs/M5329EVB.h | 11 ++ include/configs/M5373EVB.h | 11 ++ include/configs/M54451EVB.h | 15 +++ include/configs/M54455EVB.h | 17 +++- include/configs/M5475EVB.h | 16 +++ include/configs/M5485EVB.h | 16 +++ include/configs/TASREG.h | 11 ++ include/configs/astro_mcf5373l.h | 11 ++ include/configs/cobra5272.h | 13 +++ include/configs/idmr.h | 13 +++ 23 files changed, 504 insertions(+), 1 deletion(-) create mode 100644 include/asm-m68k/cache.h (limited to 'include') diff --git a/include/asm-m68k/cache.h b/include/asm-m68k/cache.h new file mode 100644 index 0000000..7c84e48 --- /dev/null +++ b/include/asm-m68k/cache.h @@ -0,0 +1,210 @@ +/* + * ColdFire cache + * + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CACHE_H +#define __CACHE_H + +#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ + defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x) +#define CONFIG_CF_V2 +#endif + +#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) +#define CONFIG_CF_V3 +#endif + +#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) +#define CONFIG_CF_V4 +#if defined(CONFIG_MCF5441x) +#define CONFIG_CF_V4E /* Four Extra ACRn */ +#endif +#endif + +/* ***** CACR ***** */ +/* V2 Core */ +#ifdef CONFIG_CF_V2 + +#define CF_CACR_CENB (1 << 31) +#define CF_CACR_CPD (1 << 28) +#define CF_CACR_CFRZ (1 << 27) +#define CF_CACR_CEIB (1 << 10) +#define CF_CACR_DCM (1 << 9) +#define CF_CACR_DBWE (1 << 8) + +#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253) +#define CF_CACR_DWP (1 << 6) +#else +#define CF_CACR_CINV (1 << 24) +#define CF_CACR_DISI (1 << 23) +#define CF_CACR_DISD (1 << 22) +#define CF_CACR_INVI (1 << 21) +#define CF_CACR_INVD (1 << 20) +#define CF_CACR_DWP (1 << 5) +#define CF_CACR_EUSP (1 << 4) +#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ + +#endif /* CONFIG_CF_V2 */ + +/* V3 Core */ +#ifdef CONFIG_CF_V3 + +#define CF_CACR_EC (1 << 31) +#define CF_CACR_ESB (1 << 29) +#define CF_CACR_DPI (1 << 28) +#define CF_CACR_HLCK (1 << 27) +#define CF_CACR_CINVA (1 << 24) +#define CF_CACR_DNFB (1 << 10) +#define CF_CACR_DCM_UNMASK 0xFFFFFCFF +#define CF_CACR_DCM_WT (0 << 8) +#define CF_CACR_DCM_CB (1 << 8) +#define CF_CACR_DCM_P (2 << 8) +#define CF_CACR_DCM_IP (3 << 8) +#define CF_CACR_DW (1 << 5) +#define CF_CACR_EUSP (1 << 4) + +#endif /* CONFIG_CF_V3 */ + +/* V4 Core */ +#ifdef CONFIG_CF_V4 + +#define CF_CACR_DEC (1 << 31) +#define CF_CACR_DW (1 << 30) +#define CF_CACR_DESB (1 << 29) +#define CF_CACR_DDPI (1 << 28) +#define CF_CACR_DHLCK (1 << 27) +#define CF_CACR_DDCM_UNMASK (0xF9FFFFFF) +#define CF_CACR_DDCM_WT (0 << 25) +#define CF_CACR_DDCM_CB (1 << 25) +#define CF_CACR_DDCM_P (2 << 25) +#define CF_CACR_DDCM_IP (3 << 25) +#define CF_CACR_DCINVA (1 << 24) + +#define CF_CACR_DDSP (1 << 23) +#define CF_CACR_BEC (1 << 19) +#define CF_CACR_BCINVA (1 << 18) +#define CF_CACR_IEC (1 << 15) +#define CF_CACR_DNFB (1 << 13) +#define CF_CACR_IDPI (1 << 12) +#define CF_CACR_IHLCK (1 << 11) +#define CF_CACR_IDCM (1 << 10) +#define CF_CACR_ICINVA (1 << 8) +#define CF_CACR_IDSP (1 << 7) +#define CF_CACR_EUSP (1 << 5) + +#ifdef CONFIG_MCF5445x +#define CF_CACR_IVO (1 << 20) +#define CF_CACR_SPA (1 << 14) +#else +#define CF_CACR_DF (1 << 4) +#endif + +#endif /* CONFIG_CF_V4 */ + +/* ***** ACR ***** */ +#define CF_ACR_ADR_UNMASK (0x00FFFFFF) +#define CF_ACR_ADR(x) ((x & 0xFF) << 24) +#define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF) +#define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16) +#define CF_ACR_EN (1 << 15) +#define CF_ACR_SM_UNMASK (0xFFFF9FFF) +#define CF_ACR_SM_UM (0 << 13) +#define CF_ACR_SM_SM (1 << 13) +#define CF_ACR_SM_ALL (3 << 13) +#define CF_ACR_WP (1 << 2) + +/* V2 Core */ +#ifdef CONFIG_CF_V2 +#define CF_ACR_CM (1 << 6) +#define CF_ACR_BWE (1 << 5) +#else +/* V3 & V4 */ +#define CF_ACR_CM_UNMASK (0xFFFFFF9F) +#define CF_ACR_CM_WT (0 << 5) +#define CF_ACR_CM_CB (1 << 5) +#define CF_ACR_CM_P (2 << 5) +#define CF_ACR_CM_IP (3 << 5) +#endif /* CONFIG_CF_V2 */ + +/* V4 Core */ +#ifdef CONFIG_CF_V4 +#define CF_ACR_AMM (1 << 10) +#define CF_ACR_SP (1 << 3) +#endif /* CONFIG_CF_V4 */ + + +#ifndef CONFIG_SYS_CACHE_ICACR +#define CONFIG_SYS_CACHE_ICACR 0 +#endif + +#ifndef CONFIG_SYS_CACHE_DCACR +#ifdef CONFIG_SYS_CACHE_ICACR +#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR +#else +#define CONFIG_SYS_CACHE_DCACR 0 +#endif +#endif + +#ifndef CONFIG_SYS_CACHE_ACR0 +#define CONFIG_SYS_CACHE_ACR0 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR1 +#define CONFIG_SYS_CACHE_ACR1 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR2 +#define CONFIG_SYS_CACHE_ACR2 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR3 +#define CONFIG_SYS_CACHE_ACR3 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR4 +#define CONFIG_SYS_CACHE_ACR4 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR5 +#define CONFIG_SYS_CACHE_ACR5 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR6 +#define CONFIG_SYS_CACHE_ACR6 0 +#endif + +#ifndef CONFIG_SYS_CACHE_ACR7 +#define CONFIG_SYS_CACHE_ACR7 0 +#endif + +#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16) + +#ifndef __ASSEMBLY__ /* put C only stuff in this section */ + +void icache_invalid(void); +void dcache_invalid(void); + +#endif + +#endif /* __CACHE_H */ diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index a0b27a8..880cb4e 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -208,6 +208,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DBWE | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 3cc259f..e6632ac 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -207,6 +207,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Chipselect bank definitions */ /* * CS0 - NOR Flash diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 1801d9d..6c6b5d6 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -302,6 +302,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 2b816ce..5c0dc84 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -237,6 +237,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index e3830e5..33ac285 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -60,6 +60,7 @@ * Command line configuration. */ #include +#define CONFIG_CMD_CACHE #undef CONFIG_CMD_NET #define CONFIG_SYS_PROMPT "=> " @@ -165,6 +166,20 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(2) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index f813f88..9944e12 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -57,6 +57,7 @@ */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS #define CONFIG_CMD_EXT2 @@ -226,6 +227,20 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(8) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index df6970c..206d115 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -64,6 +64,7 @@ * Command line configuration. */ #include +#define CONFIG_CMD_CACHE #undef CONFIG_CMD_NET #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS @@ -179,6 +180,20 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ + CF_ADDRMASK(2) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 50b3ab2..798949c 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -72,6 +72,7 @@ */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_NET #define CONFIG_CMD_MII @@ -229,6 +230,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Chip Select 0 : Boot Flash */ #define CONFIG_SYS_CS0_BASE 0xFFE00000 #define CONFIG_SYS_CS0_MASK 0x001F0001 diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index f824158..f704bb3 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -74,6 +74,7 @@ */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_CMD_PING @@ -211,6 +212,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index f8d43f0..981670a 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -72,6 +72,7 @@ /* Available command configuration */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_MII #define CONFIG_CMD_NET @@ -220,6 +221,19 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 15590cf..6e0aa14 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -64,6 +64,7 @@ * Command line configuration. */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_MII @@ -209,6 +210,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DBWE | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index c351d41..d983a8f 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -233,6 +233,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 8180c05..159b178 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -237,6 +237,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 8652a80..af1988c 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -237,6 +237,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index a5acfd2..a80d330 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -309,6 +309,21 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 7737284..5b4bba8 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -279,7 +279,7 @@ * Definitions for initial stack pointer and data area (in DPRAM) */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32) @@ -408,6 +408,21 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index 4534002..d007766 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -286,6 +286,22 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ + CF_CACR_IDCM) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ + CF_CACR_IEC | CF_CACR_ICINVA) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 971cb67..f23b8b0 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -272,6 +272,22 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ + CF_CACR_IDCM) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ + CF_CACR_IEC | CF_CACR_ICINVA) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 25f3a26..b69f015 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -252,6 +252,17 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ + CF_CACR_DBWE) + /*----------------------------------------------------------------------- * Memory bank definitions */ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 1fe42f6..7c8281c 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -386,4 +386,15 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ + CF_CACR_DCM_P) + #endif /* _CONFIG_ASTRO_MCF5373L_H */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 1c3ea23..330e3ac 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -331,6 +331,19 @@ from which user programs will be started */ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Memory bank definitions * diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 841affb..61e3bad 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -224,6 +224,19 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_END - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ + CF_CACR_DISD | CF_CACR_INVI | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 -- cgit v1.1 From f26a247308568e32857a5cc054f7219510a7d44e Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Mon, 15 Mar 2010 19:39:21 -0500 Subject: ColdFire: Fix incorrect M5253DEMO default environment The flash location is at 0xff800000, not 0 Signed-off-by: TsiChung Liew --- include/configs/M5253DEMO.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 9944e12..b5af493 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -107,7 +107,7 @@ "upd=run load; run prog\0" \ "prog=prot off 0xff800000 0xff82ffff;" \ "era 0xff800000 0xff82ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "cp.b ${loadaddr} 0xff800000 ${filesize};" \ "save\0" \ "" #endif -- cgit v1.1 From a574cff121b1479c8e962b7a2a29310020387260 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 24 Mar 2010 12:19:19 +0100 Subject: ml300: remove support for broken, orphaned board The ml300 board has a number of issues, but nobody cares about this long-orphaned board any more. Remove it. Signed-off-by: Wolfgang Denk Acked-by: Michal Simek --- include/configs/ml300.h | 181 ------------------------------------------------ 1 file changed, 181 deletions(-) delete mode 100644 include/configs/ml300.h (limited to 'include') diff --git a/include/configs/ml300.h b/include/configs/ml300.h deleted file mode 100644 index 68d0c85..0000000 --- a/include/configs/ml300.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * ML300.h: ML300 specific config options - * - * http://www.xilinx.com/ml300 - * - * Derived from : ML2.h - * - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR - * OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * - * - * (c) Copyright 2002 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* #define DEBUG */ -/* #define ET_DEBUG 1 */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_XILINX_405 1 -#define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */ - -#define CONFIG_SYSTEMACE 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_SYSTEMACE_BASE XPAR_OPB_SYSACE_0_BASEADDR -#define CONFIG_SYS_SYSTEMACE_WIDTH XPAR_XSYSACE_MEM_WIDTH - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* environment is in EEPROM */ - -/* following are used only if env is in EEPROM */ -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR XPAR_PERSISTENT_0_IIC_0_EEPROMADDR -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_ENV_OFFSET XPAR_PERSISTENT_0_IIC_0_BASEADDR -#define CONFIG_MISC_INIT_R 1 /* used to call out convert_env() */ -#define CONFIG_ENV_OVERWRITE 1 /* allow users to update ethaddr and serial# */ -#endif - -#include "../board/xilinx/ml300/xparameters.h" - -#define CONFIG_SYS_NO_FLASH 1 /* no flash */ -#define CONFIG_ENV_SIZE XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ - -#define CONFIG_BOOTARGS "console=ttyS0,9600 ip=off " \ - "root=/dev/xsysace/disc0/part3 rw" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_NET - -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_FAT -#undef CONFIG_CMD_IMLS - - -/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */ -/* 300000000 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_DUART_CHAN 0 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550 1 -#define CONFIG_SYS_INIT_CHAN1 1 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE 0x04000000 -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ -- cgit v1.1 From fd03ea89641d6f6ade6d1a8580c1bb9f52b8542c Mon Sep 17 00:00:00 2001 From: Frans Meulenbroeks Date: Fri, 26 Mar 2010 09:46:42 +0100 Subject: i2c: made unused function i2c_mux_add_device static and removed it from the .h file Signed-off-by: Frans Meulenbroeks --- include/i2c.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/i2c.h b/include/i2c.h index 31088b6..d828964 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -127,8 +127,6 @@ typedef struct _mux_device { struct _mux_device *next; } I2C_MUX_DEVICE; -int i2c_mux_add_device(I2C_MUX_DEVICE *dev); - I2C_MUX_DEVICE *i2c_mux_search_device(int id); I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf); int i2x_mux_select_mux(int bus); -- cgit v1.1 From 33f57bd553edf29dffef5a6c7d76e169c79a6049 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 26 Mar 2010 15:14:43 -0500 Subject: 85xx: Fix enabling of L1 cache parity on secondary cores Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: Kumar Gala --- include/asm-ppc/processor.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index c6da411..9b3d616 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -485,10 +485,12 @@ #define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ +#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ +#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ -- cgit v1.1 From 9ff32d8ccf0e23b5577c25610f001af8d761b4a2 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 29 Mar 2010 12:51:07 -0500 Subject: mpc86xx: set the DDR BATs after calculating true DDR size After determining how much DDR is actually in the system, set DBAT0 and IBAT0 accordingly. This ensures that the CPU won't attempt to access (via speculation) addresses outside of actual memory. On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB and kept that way. If the system has less than 2GB of memory (typical for an MPC8610 HPCD), the CPU may attempt to access this memory during speculation. The zlib code is notorious for generating such memory reads, and indeed on the MPC8610, uncompressing the Linux kernel causes a machine check (without this patch). Currently we are limited to power of two sized DDR since we only use a single bat. If a non-power of two size is used that is less than CONFIG_MAX_MEM_MAPPED u-boot will crash. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- include/asm-ppc/mmu.h | 6 +++++- include/configs/MPC8610HPCD.h | 6 ++---- include/configs/MPC8641HPCN.h | 4 +--- include/mpc86xx.h | 2 ++ 4 files changed, 10 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index fd10249..ce7f081 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -213,7 +213,11 @@ extern void print_bats(void); #define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \ | ((x & 0x0e00ULL) << 24) \ | ((x & 0x04ULL) << 30))) -#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17)) +#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17)) + +/* bytes into BATU_BL */ +#define TO_BATU_BL(x) \ + (u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4) /* Used to set up SDR1 register */ #define HASH_TABLE_SIZE_64K 0x00010000 diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 1d2d659..fed441e 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -341,10 +341,8 @@ * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ -#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U +#define CONFIG_SYS_DBAT0L (BATL_PP_RW) +#define CONFIG_SYS_IBAT0L (BATL_PP_RW) /* * BAT1 1G Cache-inhibited, guarded diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 12a8f60..94e4d24 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -482,9 +482,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * BAT0 DDR */ #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U +#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) /* * BAT1 LBC (PIXIS/CF) diff --git a/include/mpc86xx.h b/include/mpc86xx.h index c6f30f9..eb85d60 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -83,5 +83,7 @@ static __inline__ unsigned long get_l2cr (void) return l2cr_val; } +void setup_ddr_bat(phys_addr_t dram_size); + #endif /* _ASMLANGUAGE */ #endif /* __MPC86xx_H__ */ -- cgit v1.1 From c9d4f46b5d639a45747d5eaabd31d35856cb918f Mon Sep 17 00:00:00 2001 From: Scott McNutt Date: Fri, 19 Mar 2010 19:03:28 -0400 Subject: nios2: Move serial drivers to individual files in drivers/serial The standard Altera UART & JTAG UART as well as the OpenCores YANU driver are now in individual files in drivers/serial rather than a single file uner cpu/nios2. Signed-off-by: Scott McNutt --- include/configs/EP1C20.h | 3 ++- include/configs/EP1S10.h | 3 ++- include/configs/EP1S40.h | 3 ++- include/configs/PCI5441.h | 3 ++- include/configs/PK1C20.h | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index 61d8e20..dc82e54 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -94,7 +94,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 41e64e6..498f26d 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 5b332e4..4ad65d8 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 831a60d..d06b7f8 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -92,7 +92,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index cf6f7a9..165dde0 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -94,7 +94,8 @@ /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) +#define CONFIG_ALTERA_UART 1 /* Use altera uart */ +#if defined(CONFIG_ALTERA_JTAG_UART) #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ #else #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ -- cgit v1.1 From 54d809e7553939629e8941ab9eef1f762463a2b3 Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Sat, 20 Mar 2010 07:05:44 +0800 Subject: nios2: add asm-nios2/errno.h Just pull in asm-generic. Signed-off-by: Thomas Chou Signed-off-by: Scott McNutt --- include/asm-nios2/errno.h | 1 + 1 file changed, 1 insertion(+) create mode 100644 include/asm-nios2/errno.h (limited to 'include') diff --git a/include/asm-nios2/errno.h b/include/asm-nios2/errno.h new file mode 100644 index 0000000..4c82b50 --- /dev/null +++ b/include/asm-nios2/errno.h @@ -0,0 +1 @@ +#include -- cgit v1.1 From d8b73dffa9866d6de3c05c8a2d07ecd4bc0d5d7e Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Sat, 20 Mar 2010 07:05:45 +0800 Subject: nios2: add local_irq_enable/disable to asm-nios2/system.h Copy from linux header. This is needed for generic bitops. Signed-off-by: Thomas Chou Signed-off-by: Scott McNutt --- include/asm-nios2/system.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'include') diff --git a/include/asm-nios2/system.h b/include/asm-nios2/system.h index ec84f59..bb03ca5 100644 --- a/include/asm-nios2/system.h +++ b/include/asm-nios2/system.h @@ -23,4 +23,37 @@ #ifndef __ASM_NIOS2_SYSTEM_H_ #define __ASM_NIOS2_SYSTEM_H_ +#define local_irq_enable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "ori r8, r8, 1\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_irq_disable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "andi r8, r8, 0xfffe\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_save_flags(x) __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "mov %0, r8\n" \ + : "=r" (x) : : "r8", "memory") + +#define local_irq_restore(x) __asm__ __volatile__ ( \ + "mov r8, %0\n" \ + "wrctl status, r8\n" \ + : : "r" (x) : "r8", "memory") + +/* For spinlocks etc */ +#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \ + while (0) + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ +}) + #endif /* __ASM_NIOS2_SYSTEM_H */ -- cgit v1.1 From 3bef253f0802c6292b8e2acc0089894019e99e62 Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Sat, 20 Mar 2010 07:05:46 +0800 Subject: nios2: use bitops from linux-2.6 asm-generic These are needed to use ubi/ubifs. Signed-off-by: Thomas Chou Signed-off-by: Scott McNutt --- include/asm-nios2/bitops.h | 14 +-- include/asm-nios2/bitops/atomic.h | 189 ++++++++++++++++++++++++++++++++++ include/asm-nios2/bitops/ffs.h | 41 ++++++++ include/asm-nios2/bitops/non-atomic.h | 108 +++++++++++++++++++ 4 files changed, 342 insertions(+), 10 deletions(-) create mode 100644 include/asm-nios2/bitops/atomic.h create mode 100644 include/asm-nios2/bitops/ffs.h create mode 100644 include/asm-nios2/bitops/non-atomic.h (limited to 'include') diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h index 5776bda..cf48ff7 100644 --- a/include/asm-nios2/bitops.h +++ b/include/asm-nios2/bitops.h @@ -24,15 +24,9 @@ #ifndef __ASM_NIOS2_BITOPS_H_ #define __ASM_NIOS2_BITOPS_H_ - -extern void set_bit(int nr, volatile void * a); -extern void clear_bit(int nr, volatile void * a); -extern int test_and_clear_bit(int nr, volatile void * a); -extern void change_bit(unsigned long nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void * a); -extern int test_and_change_bit(int nr, volatile void * addr); -extern int test_bit(int nr, volatile void * a); -extern int ffs(int i); -#define PLATFORM_FFS +/* copied from linux-2.6/include/asm-generic/bitops */ +#include +#include +#include #endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-nios2/bitops/atomic.h b/include/asm-nios2/bitops/atomic.h new file mode 100644 index 0000000..c894646 --- /dev/null +++ b/include/asm-nios2/bitops/atomic.h @@ -0,0 +1,189 @@ +#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_ATOMIC_H_ + +#include +#include + +#ifdef CONFIG_SMP +#include +#include /* we use L1_CACHE_BYTES */ + +/* Use an array of spinlocks for our atomic_ts. + * Hash function to index into a different SPINLOCK. + * Since "a" is usually an address, use one spinlock per cacheline. + */ +# define ATOMIC_HASH_SIZE 4 +# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) + +extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; + +/* Can't use raw_spin_lock_irq because of #include problems, so + * this is the substitute */ +#define _atomic_spin_lock_irqsave(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + local_irq_save(f); \ + __raw_spin_lock(s); \ +} while(0) + +#define _atomic_spin_unlock_irqrestore(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + __raw_spin_unlock(s); \ + local_irq_restore(f); \ +} while(0) + + +#else +# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) +# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) +#endif + +/* + * NMI events can occur at any time, including when interrupts have been + * disabled by *_irqsave(). So you can get NMI events occurring while a + * *_bit function is holding a spin lock. If the NMI handler also wants + * to do bit manipulation (and they do) then you can get a deadlock + * between the original caller of *_bit() and the NMI handler. + * + * by Keith Owens + */ + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p |= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +static inline void clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p &= ~mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * change_bit - Toggle a bit in memory + * @nr: Bit to change + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. It may be + * reordered on other architectures than x86. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p ^= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It may be reordered on other architectures than x86. + * It also implies a memory barrier. + */ +static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old | mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It can be reorderdered on other architectures other than x86. + * It also implies a memory barrier. + */ +static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old & ~mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old ^ mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ diff --git a/include/asm-nios2/bitops/ffs.h b/include/asm-nios2/bitops/ffs.h new file mode 100644 index 0000000..fbbb43a --- /dev/null +++ b/include/asm-nios2/bitops/ffs.h @@ -0,0 +1,41 @@ +#ifndef _ASM_GENERIC_BITOPS_FFS_H_ +#define _ASM_GENERIC_BITOPS_FFS_H_ + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +static inline int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */ diff --git a/include/asm-nios2/bitops/non-atomic.h b/include/asm-nios2/bitops/non-atomic.h new file mode 100644 index 0000000..697cc2b --- /dev/null +++ b/include/asm-nios2/bitops/non-atomic.h @@ -0,0 +1,108 @@ +#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ + +#include + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static inline void __clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} + +/** + * __change_bit - Toggle a bit in memory + * @nr: the bit to change + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p ^= mask; +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old | mask; + return (old & mask) != 0; +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old & ~mask; + return (old & mask) != 0; +} + +/* WARNING: non atomic and it can be reordered! */ +static inline int __test_and_change_bit(int nr, + volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old ^ mask; + return (old & mask) != 0; +} + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static inline int test_bit(int nr, const volatile unsigned long *addr) +{ + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); +} + +#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */ -- cgit v1.1 From c72bfafbc94e61ea3ff3915c84aa7f9d91a045a0 Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Sat, 20 Mar 2010 07:05:47 +0800 Subject: nios2: add struct stat support in linux/stat.h This is needed for jffs2 support. Signed-off-by: Thomas Chou Signed-off-by: Scott McNutt --- include/linux/stat.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/stat.h b/include/linux/stat.h index 2ce1c25..cef6369 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -68,7 +68,7 @@ struct stat { #endif /* __PPC__ */ #if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\ - defined (__microblaze__) + defined (__microblaze__) || defined (__nios2__) struct stat { unsigned short st_dev; -- cgit v1.1 From 3ea0037f2337de692b5fd2b6a4449db1de3067a2 Mon Sep 17 00:00:00 2001 From: Scott McNutt Date: Sun, 21 Mar 2010 21:24:43 -0400 Subject: nios2: Fix outx/writex parameter order in io.h The outx/writex macros were using writex(addr, val) rather than the standard writex(val, addr), resulting in incompatibilty with architecture independent components. This change set uses standard parameter order. Signed-off-by: Scott McNutt --- include/asm-nios2/io.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index 01d11ef..121405c 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -80,19 +80,19 @@ extern unsigned inl (unsigned port); ({unsigned long val;\ asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) -#define writeb(addr,val)\ - asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val)) -#define writew(addr,val)\ - asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val)) -#define writel(addr,val)\ - asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val)) +#define writeb(val,addr)\ + asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr)) +#define writew(val,addr)\ + asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr)) +#define writel(val,addr)\ + asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr)) #define inb(addr) readb(addr) #define inw(addr) readw(addr) #define inl(addr) readl(addr) -#define outb(addr,val) writeb(addr,val) -#define outw(addr,val) writew(addr,val) -#define outl(addr,val) writel(addr,val) +#define outb(val, addr) writeb(val,addr) +#define outw(val, addr) writew(val,addr) +#define outl(val, addr) writel(val,addr) static inline void insb (unsigned long port, void *dst, unsigned long count) { -- cgit v1.1 From 3a89a91a10fed545af458418e63d911953a9849c Mon Sep 17 00:00:00 2001 From: Scott McNutt Date: Tue, 30 Mar 2010 20:23:04 -0400 Subject: nios2: Set CONFIG_SYS_HZ to 1000 all nios2 boards. CONFIG_SYS_HZ was being calculated (incorrectly) in nios2 configuration headers. Updated comments to accurately describe timebase macros. Signed-off-by: Scott McNutt --- include/configs/EP1C20.h | 14 ++++++++------ include/configs/EP1S10.h | 14 ++++++++------ include/configs/EP1S40.h | 14 ++++++++------ include/configs/PCI5441.h | 14 ++++++++------ include/configs/PK1C20.h | 14 ++++++++------ 5 files changed, 40 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index dc82e54..3920d35 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -124,14 +124,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 498f26d..bfbf8c1 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -119,14 +119,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 4ad65d8..4d905fe 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -119,14 +119,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec) */ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index d06b7f8..c60a9f7 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -114,14 +114,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /* diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index 165dde0..874c20b 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -124,14 +124,16 @@ * TIMEBASE -- * * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. + * registers, the interrupt frequency can be reduced using TMRCNT. + * If the default period is acceptable, TMRCNT can be left undefined. + * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ +#define CONFIG_SYS_HZ 1000 /* Always 1000 */ #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */ +#define CONFIG_SYS_NIOS_TMRCNT \ + (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board -- cgit v1.1 From 6c71a8fec95a9e0f90fbc47469c389c6f35d96bc Mon Sep 17 00:00:00 2001 From: Naveen Krishna CH Date: Thu, 4 Feb 2010 14:17:38 +0900 Subject: S5PC100: Moves the Macros to a common header file The get_pll_clk(int) API returns the PLL frequency based on the (int) argument which is defined locally in clock.c Moving that #define to common header file (clk.h) would be helpful when using the API from other files. Signed-off-by: Naveen Krishna Ch Signed-off-by: Minkyu Kang --- include/asm-arm/arch-s5pc1xx/clk.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h index f1aa44f..3e59abe 100644 --- a/include/asm-arm/arch-s5pc1xx/clk.h +++ b/include/asm-arm/arch-s5pc1xx/clk.h @@ -23,6 +23,12 @@ #ifndef __ASM_ARM_ARCH_CLK_H_ #define __ASM_ARM_ARCH_CLK_H_ +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 + void s5pc1xx_clock_init(void); extern unsigned long (*get_pll_clk)(int pllreg); -- cgit v1.1 From ab693e9c4c06b42d1746a0d7a03541968fb55bb9 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Fri, 12 Feb 2010 18:17:52 +0900 Subject: s5pc1xx: support the GPIO interface This patch adds support the GPIO interface Signed-off-by: Minkyu Kang --- include/asm-arm/arch-s5pc1xx/gpio.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h index afbc7ea..8e4bb86 100644 --- a/include/asm-arm/arch-s5pc1xx/gpio.h +++ b/include/asm-arm/arch-s5pc1xx/gpio.h @@ -124,6 +124,35 @@ struct s5pc110_gpio { struct s5pc1xx_gpio_bank gpio_h2; struct s5pc1xx_gpio_bank gpio_h3; }; + +/* functions */ +void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg); +void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en); +void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio); +void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en); +unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio); +void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); #endif +/* Pin configurations */ +#define GPIO_INPUT 0x0 +#define GPIO_OUTPUT 0x1 +#define GPIO_IRQ 0xf +#define GPIO_FUNC(x) (x) + +/* Pull mode */ +#define GPIO_PULL_NONE 0x0 +#define GPIO_PULL_DOWN 0x1 +#define GPIO_PULL_UP 0x2 + +/* Drive Strength level */ +#define GPIO_DRV_1X 0x0 +#define GPIO_DRV_2X 0x1 +#define GPIO_DRV_3X 0x2 +#define GPIO_DRV_4X 0x3 +#define GPIO_DRV_FAST 0x0 +#define GPIO_DRV_SLOW 0x1 + #endif -- cgit v1.1 From a28bec89ccc17b56a50d841c8f0778e927434d1c Mon Sep 17 00:00:00 2001 From: Naveen Krishna CH Date: Fri, 5 Mar 2010 17:15:13 +0900 Subject: S5PC100: Memory SubSystem Header file, register description(SROMC). Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand, NAND Flash, DDRs. smc.h is a common place for the register description of Memory subsystem of S5PC100. Note: Only SROM related registers are descibed now. Signed-off-by: Naveen Krishna Ch Signed-off-by: Minkyu Kang --- include/asm-arm/arch-s5pc1xx/smc.h | 50 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 include/asm-arm/arch-s5pc1xx/smc.h (limited to 'include') diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/include/asm-arm/arch-s5pc1xx/smc.h new file mode 100644 index 0000000..e1a5399 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/smc.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for Memory subsystem + * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. + * + * Only SROMC is defined as of now + */ + +#ifndef __ASM_ARCH_SMC_H_ +#define __ASM_ARCH_SMC_H_ + +#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ +#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ +#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ +#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ +#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ +#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ +#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5pc1xx_smc { + unsigned int bw; + unsigned int bc[6]; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_SMC_H_ */ -- cgit v1.1 From 01802e0d22a4bb3903b342ff2357ea3bbcccd289 Mon Sep 17 00:00:00 2001 From: Naveen Krishna CH Date: Fri, 5 Mar 2010 17:15:38 +0900 Subject: S5PC100: Function to configure the SROMC registers. Nand Flash, Ethernet, other features might need to configure the SROMC registers accordingly. The config_sromc() functions helps with this. Signed-off-by: Naveen Krishna Ch Signed-off-by: Minkyu Kang --- include/asm-arm/arch-s5pc1xx/smc.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/include/asm-arm/arch-s5pc1xx/smc.h index e1a5399..88f4ffe 100644 --- a/include/asm-arm/arch-s5pc1xx/smc.h +++ b/include/asm-arm/arch-s5pc1xx/smc.h @@ -47,4 +47,7 @@ struct s5pc1xx_smc { }; #endif /* __ASSEMBLY__ */ +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf); + #endif /* __ASM_ARCH_SMC_H_ */ -- cgit v1.1 From 2528dc52361bea49e6bd4a95ce2374d0004ca56f Mon Sep 17 00:00:00 2001 From: Naveen Krishna CH Date: Fri, 5 Mar 2010 17:16:05 +0900 Subject: SAMSUNG: SMDKC100: Adds ethernet support. Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be loaded over tftp. The preinit function will configure GPIO (GPK0CON) & SROMC to look for environment in SROM Bank 3. Signed-off-by: Naveen Krishna Ch Signed-off-by: Minkyu Kang --- include/configs/smdkc100.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index a8ba052..09bce6d 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -83,7 +83,6 @@ #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_NAND -#undef CONFIG_CMD_NET #define CONFIG_CMD_CACHE #define CONFIG_CMD_REGINFO @@ -235,4 +234,15 @@ #define CONFIG_DOS_PARTITION 1 +/* + * Ethernet Contoller driver + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 /* we have a SMC9115 on-board */ +#define CONFIG_SMC911X_16_BIT 1 /* SMC911X_16_BIT Mode */ +#define CONFIG_SMC911X_BASE 0x98800300 /* SMC911X Drive Base */ +#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ +#endif /* CONFIG_CMD_NET */ + #endif /* __CONFIG_H */ -- cgit v1.1 From c9f72b3da8855c3c9679c821127cccd91e0380ed Mon Sep 17 00:00:00 2001 From: Daniel Gorsulowski Date: Wed, 17 Mar 2010 08:21:11 +0100 Subject: at91: boards cleanup for deprecated CONFIG_CMD_AUTOSCRIPT CONFIG_CMD_AUTOSCRIPT support is deprecated and non-existing This clean up patch removes the references for esd boards Signed-off-by: Daniel Gorsulowski --- include/configs/meesc.h | 1 - include/configs/otc570.h | 1 - 2 files changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/meesc.h b/include/configs/meesc.h index d002b97..e085f4a 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -82,7 +82,6 @@ */ #include #undef CONFIG_CMD_BDI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS diff --git a/include/configs/otc570.h b/include/configs/otc570.h index 4fde012..fb0f576 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -131,7 +131,6 @@ * Command line configuration. */ #include -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -- cgit v1.1 From 0701f730cebc8dd065b70812ca0332055dcf10f8 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Thu, 25 Mar 2010 14:30:13 +0100 Subject: at91: use C structs for AT91 OHCI code This patch is part of migrating the AT91 support towards using C struct for all SOC access. It removes one more CONFIG_AT91_LEGACY warning. at91_pmc.h needs cleanup after migration of the drivers has been done. Signed-off-by: Matthias Fuchs --- include/asm-arm/arch-at91/at91_pmc.h | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index 680fe33..5b1a85d 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -108,11 +108,12 @@ typedef struct at91_pmc { #define AT91_PMC_IXR_PCKRDY3 0x00000800 #ifdef CONFIG_AT91_LEGACY - #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ +#endif + #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ @@ -128,27 +129,34 @@ typedef struct at91_pmc { #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ +#endif + #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ +#ifdef CONFIG_AT91_LEGACY #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ +#endif #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ - +#ifdef CONFIG_AT91_LEGACY #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ +#endif #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ - +#ifdef CONFIG_AT91_LEGACY #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ +#endif #define AT91_PMC_DIV (0xff << 0) /* Divider */ #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ @@ -160,7 +168,9 @@ typedef struct at91_pmc { #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ #define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ +#endif #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ #define AT91_PMC_CSS_SLOW (0 << 0) #define AT91_PMC_CSS_MAIN (1 << 0) @@ -188,11 +198,13 @@ typedef struct at91_pmc { #define AT91_PMC_PDIV_1 (0 << 12) #define AT91_PMC_PDIV_2 (1 << 12) +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ +#endif #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ @@ -203,12 +215,13 @@ typedef struct at91_pmc { #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +#endif #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ - +#ifdef CONFIG_AT91_LEGACY #define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ - #endif /* CONFIG_AT91_LEGACY */ #endif -- cgit v1.1 From d0b0dcaa220549999d6ea74cf87487846c186a0f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 1 Apr 2010 14:37:24 +0200 Subject: i2c: Move PPC4xx I2C driver into drivers/i2c directory This patch moves the PPC4xx specific I2C device driver into the I2C drivers directory. All 4xx config headers are updated to include this driver. Signed-off-by: Stefan Roese --- include/configs/ASH405.h | 1 + include/configs/CANBT.h | 1 + include/configs/CMS700.h | 1 + include/configs/CPCI2DP.h | 1 + include/configs/CPCI405.h | 1 + include/configs/CPCI4052.h | 1 + include/configs/CPCI405AB.h | 1 + include/configs/CPCI405DT.h | 1 + include/configs/CPCIISER4.h | 1 + include/configs/CRAYL1.h | 1 + include/configs/DP405.h | 1 + include/configs/DU405.h | 1 + include/configs/DU440.h | 1 + include/configs/ERIC.h | 1 + include/configs/G2000.h | 1 + include/configs/HH405.h | 1 + include/configs/HUB405.h | 1 + include/configs/JSE.h | 1 + include/configs/KAREF.h | 1 + include/configs/METROBOX.h | 1 + include/configs/MIP405.h | 1 + include/configs/OCRTC.h | 1 + include/configs/ORSG.h | 1 + include/configs/PCI405.h | 1 + include/configs/PIP405.h | 1 + include/configs/PLU405.h | 1 + include/configs/PMC405.h | 1 + include/configs/PMC405DE.h | 1 + include/configs/PMC440.h | 1 + include/configs/PPChameleonEVB.h | 1 + include/configs/VOH405.h | 1 + include/configs/VOM405.h | 1 + include/configs/W7OLMC.h | 1 + include/configs/W7OLMG.h | 1 + include/configs/WUH405.h | 1 + include/configs/XPEDITE1000.h | 1 + include/configs/alpr.h | 1 + include/configs/amcc-common.h | 1 + include/configs/csb272.h | 1 + include/configs/csb472.h | 1 + include/configs/korat.h | 1 + include/configs/lwmon5.h | 1 + include/configs/netstal-common.h | 1 + include/configs/p3p440.h | 1 + include/configs/pcs440ep.h | 1 + include/configs/quad100hd.h | 1 + include/configs/sbc405.h | 1 + include/configs/sc3.h | 1 + include/configs/zeus.h | 1 + 49 files changed, 49 insertions(+) (limited to 'include') diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 5cb0f1e..4cb8052 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -244,6 +244,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index e3e6e75..cdba81d 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -173,6 +173,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index ae8494d..2b6786b 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -224,6 +224,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 5c88c47..9221211 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -207,6 +207,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index d131aea..3e7020d 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -256,6 +256,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 07c4e35..d3000f6 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -283,6 +283,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index c78552b..d376344 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -259,6 +259,7 @@ * I2C EEPROM (CAT24WC32) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 59e0778..07acab0 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -278,6 +278,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index b2679e5..5b50bcf 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -189,6 +189,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 96bf161..9ab30ec 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -65,6 +65,7 @@ #define CONFIG_ETHADDR 00:40:a6:80:14:5 */ #define CONFIG_HARD_I2C 1 /* hardware support for i2c */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SDRAM_BANK0 1 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 49ecb6f..4423f2a 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -174,6 +174,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU405.h b/include/configs/DU405.h index cfb3023..8f1fc78 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -212,6 +212,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 65dc235..830466f 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -169,6 +169,7 @@ */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_I2C_MULTI_BUS 1 diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 023f33e..e07f9a1 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -54,6 +54,7 @@ #endif /* total size of a X1240 is 2048 bytes */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 6819c3e..d2883eb 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -295,6 +295,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 9233523..01e0bc6 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -331,6 +331,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #if 0 /* test-only */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #else diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index ea502d4..8c6d5ed 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -244,6 +244,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 80c70e4..98f5661 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -217,6 +217,7 @@ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 4b67c94..49a7378 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -132,6 +132,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C hardware support */ #undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 518173a..e7429dd 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -194,6 +194,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C hardware support */ #undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 7ac9342..7e6484e 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -97,6 +97,7 @@ ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 860ec52..55471af 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -210,6 +210,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index b2e2d41..1424713 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -208,6 +208,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 4e39799..0d443ea 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -204,6 +204,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 962b29e..3e57c0b 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -86,6 +86,7 @@ * The Atmel EEPROM uses 16Bit addressing. ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 3d59454..f917eb5 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -278,6 +278,7 @@ * I2C EEPROM (24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 87ea7b6..00a12fb 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -235,6 +235,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 7198632..2c048dd 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -215,6 +215,7 @@ * I2C EEPROM (24W16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 89799af..c2fb56c 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -226,6 +226,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 8e9d928..44f03dc 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -414,6 +414,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 38a1d0d..9c91fcc 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -277,6 +277,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 4717869..871e4c3 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -203,6 +203,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index c017915..f06bfe5 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -273,6 +273,7 @@ * I2C EEPROM (CAT24WC08) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 1d4ad13..be8c9f8 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -280,6 +280,7 @@ * I2C EEPROM (ATMEL 24C04N) */ #define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 5c281a1..be9ac62 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -241,6 +241,7 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/XPEDITE1000.h b/include/configs/XPEDITE1000.h index 658e947..cf39aea 100644 --- a/include/configs/XPEDITE1000.h +++ b/include/configs/XPEDITE1000.h @@ -141,6 +141,7 @@ extern void out32(unsigned int, unsigned long); * I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 0fed9ad..f2392f6 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -118,6 +118,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 8cd97b8..13a941e 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -40,6 +40,7 @@ * I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* diff --git a/include/configs/csb272.h b/include/configs/csb272.h index aed6f50..9ded330 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -171,6 +171,7 @@ * */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 24b961f..71eb083 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -170,6 +170,7 @@ * */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 026dd08..f95df68 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -153,6 +153,7 @@ */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 011dd5c..6461124 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -258,6 +258,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h index 4bed7ae..cb7efe7 100644 --- a/include/configs/netstal-common.h +++ b/include/configs/netstal-common.h @@ -42,6 +42,7 @@ * I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 729ca6a..d6b9207 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -92,6 +92,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 000ae5c..1f744b8 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -138,6 +138,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index b08dcd4..403837e 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -150,6 +150,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 242f42f..429b11c 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -166,6 +166,7 @@ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/sc3.h b/include/configs/sc3.h index a5eca39..d00f248 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -251,6 +251,7 @@ */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define I2C_INIT #define I2C_ACTIVE 0 diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 1a77c71..3b2aede 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -167,6 +167,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F -- cgit v1.1 From cc4d1226585fa2544b5116702b02eacbb7aa48a1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 18 Mar 2010 15:51:05 -0500 Subject: fsl_esdhc: Always stop clock before changing frequency We need to stop the clocks on 83xx/85xx as well as imx. No need to make this code conditional to just imx. Signed-off-by: Kumar Gala Acked-by: Stefano Babic --- include/fsl_esdhc.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 01b7dec..57a08cd 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008, Freescale Semiconductor, Inc + * Copyright 2007-2008,2010 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -148,7 +148,6 @@ struct fsl_esdhc_cfg { u32 esdhc_base; u32 no_snoop; - u32 clk_enable; }; /* Select the correct accessors depending on endianess */ -- cgit v1.1 From 48bb3bb5ac4dd21e931ae157caad6449bcb2d0d4 Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Thu, 18 Mar 2010 15:57:06 -0500 Subject: fsl_esdhc: Add function to reset the eSDHC controller To support multiple block read command we must set abort or use auto CMD12. If we booted from eSDHC controller neither of these are used and thus we need to reset the controller to allow multiple block read to function. Signed-off-by: Jerry Huang Signed-off-by: Roy Zang Acked-by: Stefano Babic Signed-off-by: Kumar Gala --- include/fsl_esdhc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 57a08cd..5f02018 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -39,6 +39,7 @@ #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 +#define SYSCTL_RSTA 0x01000000 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) -- cgit v1.1 From ab467c512e79dbd14f02352655f054a4304c457e Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Tue, 9 Feb 2010 18:23:33 +0800 Subject: fsl_esdhc: Only modify the field we are changing in WML When we set the read or write watermark in WML we should maintain the rest of the register as is, rather than using some hard coded value. Signed-off-by: Roy Zang Acked-by: Stefano Babic Signed-off-by: Kumar Gala --- include/fsl_esdhc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 5f02018..f9ae15a 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -133,6 +133,8 @@ #define WML 0x2e044 #define WML_WRITE 0x00010000 +#define WML_RD_WML_MASK 0xff +#define WML_WR_WML_MASK 0xff0000 #define BLKATTR 0x2e004 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) -- cgit v1.1 From 69bcf5bc80a47acbd62b8cfff932cb12d47997d7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 29 Mar 2010 13:50:31 -0500 Subject: 85xx: Add defines for BUCSR bits to make code more readable Signed-off-by: Kumar Gala --- include/asm-ppc/processor.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9b3d616..4134f18 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -533,6 +533,9 @@ #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */ +#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */ +#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN) #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ #define SPRN_PID1 0x279 /* Process ID Register 1 */ -- cgit v1.1 From 459c41a8e1be96edeba1c0afeccacafd93b2c4e6 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 3 Nov 2009 15:53:12 -0500 Subject: Blackfin: disable NetBSD bootm support by default There is no Blackfin/NetBSD port, so enabling support for it by default doesn't make any sense. Signed-off-by: Mike Frysinger --- include/asm-blackfin/config-pre.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/asm-blackfin/config-pre.h b/include/asm-blackfin/config-pre.h index 1170a2a..4531519 100644 --- a/include/asm-blackfin/config-pre.h +++ b/include/asm-blackfin/config-pre.h @@ -71,6 +71,9 @@ static inline const char *get_bfin_boot_mode(int bfin_boot) # define BFIN_BOOT_SPI_SSEL 1 #endif +/* There is no Blackfin/NetBSD port */ +#undef CONFIG_BOOTM_NETBSD + /* We rarely use interrupts, so favor throughput over latency */ #define CONFIG_BFIN_INS_LOWOVERHEAD -- cgit v1.1 From 49b97d9c8ea7b11c4fc9e457cc2cd9fd6ebf0c21 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 30 Mar 2010 10:19:26 -0500 Subject: fdt: Add fdt_del_node_and_alias helper Add a helper function that given an alias will delete both the node the alias points to and the alias itself Signed-off-by: Kumar Gala Acked-by: Gerald Van Baren --- include/fdt_support.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fdt_support.h b/include/fdt_support.h index a3d5f8c..9a453af 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -82,6 +82,7 @@ int fdt_resize(void *blob); int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size); void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size); +void fdt_del_node_and_alias(void *blob, const char *alias); #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ -- cgit v1.1 From 216818c1a2d03b1c0994f00993c99af38c5b1e83 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 21 Jan 2010 23:29:18 -0500 Subject: Blackfin: bf537-stamp: add board test defines We tweak the configs a little when doing automated hardware tests. Signed-off-by: Mike Frysinger --- include/configs/bf537-stamp.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index de2add7..d3159e5 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -277,6 +277,15 @@ #define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ #endif +/* These are for board tests */ +#if 0 +#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100" +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT \ + "autoboot in %d seconds: press space to stop\n", bootdelay +#define CONFIG_AUTOBOOT_STOP_STR " " +#endif + /* * Pull in common ADI header for remaining command/environment setup -- cgit v1.1 From 6a0be8f8fe6d72a30e69d08decb72dc3bec5484c Mon Sep 17 00:00:00 2001 From: Harald Krapfenbauer Date: Fri, 22 Jan 2010 17:15:55 -0500 Subject: Blackfin: cm-bf561: update network/env settings Switch to the SMC911X driver by default now, and fix LDR env settings. Signed-off-by: Harald Krapfenbauer Signed-off-by: Mike Frysinger --- include/configs/cm-bf561.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 1741ed4..c60401c 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -63,14 +63,10 @@ * Network Settings */ #define ADI_CMDS_NETWORK 1 -/* The next 2 lines are for use with DEV-BF5xx */ #define CONFIG_NET_MULTI -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x28000300 -/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */ -/* #define CONFIG_DRIVER_SMC911X 1 */ -/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 /! AMS1 */ -/* #define CONFIG_DRIVER_SMC911X_32_BIT 1 */ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_BASE 0x24008000 /* AMS1 */ +#define CONFIG_SMC911X_16_BIT #define CONFIG_HOSTNAME cm-bf561 /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */ @@ -94,6 +90,7 @@ #define CONFIG_ENV_OFFSET 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR /* -- cgit v1.1 From dd97022cbeaae5fd4bce25cf7e86019101a040ef Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 29 Jan 2010 15:48:28 -0500 Subject: Blackfin: sync ptrace headers with linux Scrub a lot of dead cruft in the process. Signed-off-by: Mike Frysinger --- include/asm-blackfin/ptrace.h | 297 ++++++++++++++++-------------------------- include/asm-blackfin/traps.h | 62 ++------- 2 files changed, 126 insertions(+), 233 deletions(-) (limited to 'include') diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h index f1b7d00..251d5e6 100644 --- a/include/asm-blackfin/ptrace.h +++ b/include/asm-blackfin/ptrace.h @@ -1,31 +1,11 @@ /* - * U-boot - ptrace.h + * Copyright 2004-2008 Analog Devices Inc. * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ -#ifndef _BLACKFIN_PTRACE_H -#define _BLACKFIN_PTRACE_H - -#define NEW_PT_REGS +#ifndef _BFIN_PTRACE_H +#define _BFIN_PTRACE_H /* * GCC defines register number like this: @@ -35,128 +15,30 @@ * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3 * 32 - 33 A registers A0 & A1 * 34 - status register + * ----------------------------- * * We follows above, except: * 32-33 --- Low 32-bit of A0&1 * 34-35 --- High 8-bit of A0&1 */ -#if defined(NEW_PT_REGS) - -#define PT_IPEND 0 -#define PT_SYSCFG (PT_IPEND+4) -#define PT_SEQSTAT (PT_SYSCFG+4) -#define PT_RETE (PT_SEQSTAT+4) -#define PT_RETN (PT_RETE+4) -#define PT_RETX (PT_RETN+4) -#define PT_RETI (PT_RETX+4) -#define PT_PC PT_RETI -#define PT_RETS (PT_RETI+4) -#define PT_RESERVED (PT_RETS+4) -#define PT_ASTAT (PT_RESERVED+4) -#define PT_LB1 (PT_ASTAT+4) -#define PT_LB0 (PT_LB1+4) -#define PT_LT1 (PT_LB0+4) -#define PT_LT0 (PT_LT1+4) -#define PT_LC1 (PT_LT0+4) -#define PT_LC0 (PT_LC1+4) -#define PT_A1W (PT_LC0+4) -#define PT_A1X (PT_A1W+4) -#define PT_A0W (PT_A1X+4) -#define PT_A0X (PT_A0W+4) -#define PT_B3 (PT_A0X+4) -#define PT_B2 (PT_B3+4) -#define PT_B1 (PT_B2+4) -#define PT_B0 (PT_B1+4) -#define PT_L3 (PT_B0+4) -#define PT_L2 (PT_L3+4) -#define PT_L1 (PT_L2+4) -#define PT_L0 (PT_L1+4) -#define PT_M3 (PT_L0+4) -#define PT_M2 (PT_M3+4) -#define PT_M1 (PT_M2+4) -#define PT_M0 (PT_M1+4) -#define PT_I3 (PT_M0+4) -#define PT_I2 (PT_I3+4) -#define PT_I1 (PT_I2+4) -#define PT_I0 (PT_I1+4) -#define PT_USP (PT_I0+4) -#define PT_FP (PT_USP+4) -#define PT_P5 (PT_FP+4) -#define PT_P4 (PT_P5+4) -#define PT_P3 (PT_P4+4) -#define PT_P2 (PT_P3+4) -#define PT_P1 (PT_P2+4) -#define PT_P0 (PT_P1+4) -#define PT_R7 (PT_P0+4) -#define PT_R6 (PT_R7+4) -#define PT_R5 (PT_R6+4) -#define PT_R4 (PT_R5+4) -#define PT_R3 (PT_R4+4) -#define PT_R2 (PT_R3+4) -#define PT_R1 (PT_R2+4) -#define PT_R0 (PT_R1+4) -#define PT_ORIG_R0 (PT_R0+4) -#define PT_SR PT_SEQSTAT - -#else -/* - * Here utilize blackfin : dpregs = [pregs + imm16s4] - * [pregs + imm16s4] = dpregs - * to access defferent saved reg in stack - */ -#define PT_R3 0 -#define PT_R4 4 -#define PT_R2 8 -#define PT_R1 12 -#define PT_P5 16 -#define PT_P4 20 -#define PT_P3 24 -#define PT_P2 28 -#define PT_P1 32 -#define PT_P0 36 -#define PT_R7 40 -#define PT_R6 44 -#define PT_R5 48 -#define PT_PC 52 -#define PT_SEQSTAT 56 /* so-called SR reg */ -#define PT_SR PT_SEQSTAT -#define PT_ASTAT 60 -#define PT_RETS 64 -#define PT_A1w 68 -#define PT_A0w 72 -#define PT_A1x 76 -#define PT_A0x 80 -#define PT_ORIG_R0 84 -#define PT_R0 88 -#define PT_USP 92 -#define PT_FP 96 -#define PT_SP 100 - -/* Added by HuTao, May26 2003 3:18PM */ -#define PT_IPEND 100 - -/* Add SYSCFG register for single stepping support */ -#define PT_SYSCFG 104 - -#endif - #ifndef __ASSEMBLY__ -#if defined(NEW_PT_REGS) +struct task_struct; + /* this struct defines the way the registers are stored on the - * stack during a system call. - */ + stack during a system call. */ + struct pt_regs { + long orig_pc; long ipend; - long syscfg; long seqstat; long rete; long retn; long retx; - long pc; + long pc; /* PC == RETI */ long rets; - long reserved; + long reserved; /* Used as scratch during system calls */ long astat; long lb1; long lb0; @@ -201,69 +83,116 @@ struct pt_regs { long r1; long r0; long orig_r0; -}; - -#else -/* now we don't know what regs the system call will use */ -struct pt_regs { - long r3; - long r4; - long r2; - long r1; - long p5; - long p4; - long p3; - long p2; - long p1; - long p0; - long r7; - long r6; - long r5; - unsigned long pc; - unsigned long seqstat; - unsigned long astat; - unsigned long rets; - long a1w; - long a0w; - long a1x; - long a0x; - long orig_r0; - long r0; - long usp; - long fp; -/* - * Added for supervisor/user mode switch. - * - * HuTao May26 03 3:23PM - */ - long ipend; + long orig_p0; long syscfg; }; -#endif - /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 /* ptrace signal */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 /* ptrace signal */ + +#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ +#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ +#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ + +#define PS_S (0x0002) #ifdef __KERNEL__ -#ifndef PS_S -#define PS_S (0x0c00) +/* user_mode returns true if only one bit is set in IPEND, other than the + master interrupt enable. */ +#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1))) +#define instruction_pointer(regs) ((regs)->pc) +#define user_stack_pointer(regs) ((regs)->usp) +#define profile_pc(regs) instruction_pointer(regs) +extern void show_regs(struct pt_regs *); + +#define arch_has_single_step() (1) +extern void user_enable_single_step(struct task_struct *); +/* see arch/blackfin/kernel/ptrace.c about this redirect */ +#define user_disable_single_step(child) ptrace_disable(child) -/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode - * 00: user - * 01: supervisor - * 1x: debug +/* + * Get the address of the live pt_regs for the specified task. + * These are saved onto the top kernel stack when the process + * is not running. + * + * Note: if a user thread is execve'd from kernel space, the + * kernel stack will not be empty on entry to the kernel, so + * ptracing these tasks will fail. */ +#define task_pt_regs(task) \ + (struct pt_regs *) \ + ((unsigned long)task_stack_page(task) + \ + (THREAD_SIZE - sizeof(struct pt_regs))) -#define PS_M (0x1000) /* I am not sure why this is required here Akbar */ -#endif +#endif /* __KERNEL__ */ -#define user_mode(regs) (!((regs)->seqstat & PS_S)) -#define instruction_pointer(regs) ((regs)->pc) -extern void show_regs(struct pt_regs *); +#endif /* __ASSEMBLY__ */ + +/* + * Offsets used by 'ptrace' system call interface. + */ -#endif -#endif -#endif +#define PT_R0 204 +#define PT_R1 200 +#define PT_R2 196 +#define PT_R3 192 +#define PT_R4 188 +#define PT_R5 184 +#define PT_R6 180 +#define PT_R7 176 +#define PT_P0 172 +#define PT_P1 168 +#define PT_P2 164 +#define PT_P3 160 +#define PT_P4 156 +#define PT_P5 152 +#define PT_FP 148 +#define PT_USP 144 +#define PT_I0 140 +#define PT_I1 136 +#define PT_I2 132 +#define PT_I3 128 +#define PT_M0 124 +#define PT_M1 120 +#define PT_M2 116 +#define PT_M3 112 +#define PT_L0 108 +#define PT_L1 104 +#define PT_L2 100 +#define PT_L3 96 +#define PT_B0 92 +#define PT_B1 88 +#define PT_B2 84 +#define PT_B3 80 +#define PT_A0X 76 +#define PT_A0W 72 +#define PT_A1X 68 +#define PT_A1W 64 +#define PT_LC0 60 +#define PT_LC1 56 +#define PT_LT0 52 +#define PT_LT1 48 +#define PT_LB0 44 +#define PT_LB1 40 +#define PT_ASTAT 36 +#define PT_RESERVED 32 +#define PT_RETS 28 +#define PT_PC 24 +#define PT_RETX 20 +#define PT_RETN 16 +#define PT_RETE 12 +#define PT_SEQSTAT 8 +#define PT_IPEND 4 + +#define PT_ORIG_R0 208 +#define PT_ORIG_P0 212 +#define PT_SYSCFG 216 +#define PT_TEXT_ADDR 220 +#define PT_TEXT_END_ADDR 224 +#define PT_DATA_ADDR 228 +#define PT_FDPIC_EXEC 232 +#define PT_FDPIC_INTERP 236 + +#endif /* _BFIN_PTRACE_H */ diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h index b90ceda..7422d3d 100644 --- a/include/asm-blackfin/traps.h +++ b/include/asm-blackfin/traps.h @@ -1,42 +1,14 @@ /* - * U-boot - traps.h + * Copyright 2004-2009 Analog Devices Inc. + * 2001 Lineo, Inc + * Tony Kou + * 1993 Hamish Macdonald * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * linux/include/asm/traps.h - * Copyright (C) 1993 Hamish Macdonald - * Lineo, Inc Jul 2001 Tony Kou - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Licensed under the GPL-2 */ -/* - */ - -#ifndef _BLACKFIN_TRAPS_H -#define _BLACKFIN_TRAPS_H - -#ifndef __ASSEMBLY__ -typedef void (*e_vector) (void); -extern e_vector vectors[]; -#endif +#ifndef _BFIN_TRAPS_H +#define _BFIN_TRAPS_H #define VEC_SYS (0) #define VEC_EXCPT01 (1) @@ -64,23 +36,15 @@ extern e_vector vectors[]; #define VEC_CPLB_M (38) #define VEC_CPLB_MHIT (39) #define VEC_WATCH (40) -#define VEC_ISTRU_VL (41) +#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */ #define VEC_MISALI_I (42) #define VEC_CPLB_I_VL (43) #define VEC_CPLB_I_M (44) #define VEC_CPLB_I_MHIT (45) #define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ +/* The hardware reserves (63) for future use - we use it to tell our + * normal exception handling code we have a hardware error + */ +#define VEC_HWERR (63) -#define VECOFF(vec) ((vec)<<2) - -#ifndef __ASSEMBLY__ - -/* Status register bits */ -#define PS_T (0x8000) -#define PS_S (0x0c00) /* Supervisor mode = 0b01 */ -#define PS_D (0x0c00) /* Debug mode = 0b1x */ -#define PS_M (0x1000) -#define PS_C (0x0001) - -#endif -#endif +#endif /* _BFIN_TRAPS_H */ -- cgit v1.1 From 3f1a5c1655d32b7ab8ae74c79934ce100ebcd2bf Mon Sep 17 00:00:00 2001 From: Brent Kandetzki Date: Wed, 24 Mar 2010 17:41:33 -0400 Subject: Blackfin: IP04: new board port A low cost 4 port IP-PBX board. Signed-off-by: Brent Kandetzki Signed-off-by: Mike Frysinger --- include/configs/ip04.h | 157 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 include/configs/ip04.h (limited to 'include') diff --git a/include/configs/ip04.h b/include/configs/ip04.h new file mode 100644 index 0000000..425a745 --- /dev/null +++ b/include/configs/ip04.h @@ -0,0 +1,157 @@ +/* + * U-boot - Configuration file for IP04 board (having BF532 processor) + * + * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com + * + * Copyright (c) 2005-2010 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __CONFIG_IP04_H__ +#define __CONFIG_IP04_H__ + +#include + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf532-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 10000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 40 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 3 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL 0x408 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 +#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_HOSTNAME IP04 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_NO_SROM +#define CONFIG_DM9000_BASE 0x20100000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 2) + + +/* + * Flash Settings + */ +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_SYS_NO_FLASH /* we have only NAND */ + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_WINBOND + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_PREBOOT "echo starting from spi flash" +#define CONFIG_ENV_OFFSET 0x30000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 + + +/* + * NAND Settings + */ +#define CONFIG_NAND_PLAT +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_READY PF10 +#define BFIN_NAND_WRITE(addr, cmd) \ + do { \ + bfin_write8(addr, cmd); \ + SSYNC(); \ + } while (0) + +#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) +#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY) +#define NAND_PLAT_INIT() \ + do { \ + bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \ + bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \ + bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \ + bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \ + } while (0) + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R /* needed for MAC address */ +#define CONFIG_UART_CONSOLE 0 + +#undef CONFIG_SHOW_BOOT_PROGRESS +/* Enable this if bootretry required; currently it's disabled */ +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOTCOMMAND "run nandboot" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include + +#endif -- cgit v1.1 From 216082754f6da5359ea0db9b0cc03ad531ac6e45 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 30 Mar 2010 23:06:53 -0500 Subject: 85xx: Added various P1012/P1013/P1021/P1022 defines There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list * Added number of LAWs for P1012/P1013/P1021/P1022 * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 * PCI port config Signed-off-by: Haiying Wang Signed-off-by: Srikanth Srinivasan Signed-off-by: Kumar Gala --- include/asm-ppc/config.h | 3 ++- include/asm-ppc/processor.h | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 0d78aa4..fc3facb 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -41,6 +41,7 @@ #endif #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ defined(CONFIG_P2020) || defined(CONFIG_MPC8641) #define CONFIG_MAX_CPUS 2 #elif defined(CONFIG_PPC_P4080) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 4134f18..2b02774 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1035,8 +1035,16 @@ #define SVR_8572_E 0x80E800 #define SVR_P1011 0x80E500 #define SVR_P1011_E 0x80ED00 +#define SVR_P1012 0x80E501 +#define SVR_P1012_E 0x80ED01 +#define SVR_P1013 0x80E700 +#define SVR_P1013_E 0x80EF00 #define SVR_P1020 0x80E400 #define SVR_P1020_E 0x80EC00 +#define SVR_P1021 0x80E401 +#define SVR_P1021_E 0x80EC01 +#define SVR_P1022 0x80E600 +#define SVR_P1022_E 0x80EE00 #define SVR_P2010 0x80E300 #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 -- cgit v1.1 From ff8473e90a018c2bb19a196176c1f2e9602d6354 Mon Sep 17 00:00:00 2001 From: Sandeep Gopalpet Date: Fri, 12 Mar 2010 10:45:02 +0530 Subject: 85xx: Set HID1[mbdd] on e500v2 rev5.0 or greater The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize the performance of mbar/eieio instructions. Signed-off-by: Sandeep Gopalpet --- include/asm-ppc/processor.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 2b02774..9ec319a 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -265,6 +265,7 @@ #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ #define HID1_ASTME (1<<13) /* Address bus streaming mode */ #define HID1_ABE (1<<12) /* Address broadcast enable */ +#define HID1_MBDD (1<<6) /* optimized sync instruction */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ -- cgit v1.1 From 2feb4af001a0be5ccad6e6a6eb072207cbef6e3f Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Wed, 31 Mar 2010 17:44:13 -0500 Subject: fsl: improve the PIXIS code and fix a few bugs Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx boards. This makes the code easier to read and more flexible. Delete pixis.h, because none of the exported functions were actually being used by any other file. Make all of the functions in pixis.c 'static'. Remove "#include pixis.h" from every file that has it. Remove some unnecessary #includes. Make 'pixis_base' into a macro, so that we don't need to define it in every function. Add "while(1);" loops at the end of functions that reset the board, so that execution doesn't continue while the reset is in progress. Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where appropriate. Replace ulong/uint with their spelled-out equivalents. Remove unnecessary typecasts, changing the types of some variables if necessary. Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make it easier for specific boards to support variations in the PIXIS registers sets. No current boards appears to need this feature. Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD. Apparently, "pixis_reset altbank" has never worked on this board. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- include/configs/MPC8610HPCD.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index fed441e..8382e3c 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -177,7 +177,7 @@ #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ +#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -- cgit v1.1 From 5a4696088376fff82629e7e4a2444294dc589c96 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Thu, 1 Apr 2010 10:49:42 -0500 Subject: p2020ds: add alternate boot bank support using the ngPIXIS FPGA The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS. The ngPIXIS has one distinct new feature: the values of the on-board switches can be selectively overridden with shadow registers. This feature is used to boot from a different NOR flash bank, instead of having a register dedicated for this purpose. Because the ngPIXIS is so different from the previous PIXIS, a new file is introduced: ngpixis.c. Also update the P2020DS checkboard() function to use the new macros defined in the header file. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 62 ++++++----------------------------------------- 1 file changed, 8 insertions(+), 54 deletions(-) (limited to 'include') diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 30a5a31..66be725 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -238,7 +238,9 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#ifdef CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull @@ -249,59 +251,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_PWR 0x5 /* PIXIS Power status register */ -#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VSTAT 0x11 /* VELA Status Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ -#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */ -#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */ -#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */ -#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */ -#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */ -#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */ - -#define PIXIS_VWATCH 0x24 /* Watchdog Register */ -#define PIXIS_LED 0x25 /* LED Register */ - -#define PIXIS_SW(x) 0x20 + (x - 1) * 2 -#define PIXIS_EN(x) 0x21 + (x - 1) * 2 -#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */ -#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */ - -/* old pixis referenced names */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 -#define PIXIS_VSPEED2_TSEC1SER 0x8 -#define PIXIS_VSPEED2_TSEC2SER 0x4 -#define PIXIS_VSPEED2_TSEC3SER 0x2 -#define PIXIS_VSPEED2_TSEC4SER 0x1 -#define PIXIS_VCFGEN1_TSEC1SER 0x20 -#define PIXIS_VCFGEN1_TSEC2SER 0x20 -#define PIXIS_VCFGEN1_TSEC3SER 0x20 -#define PIXIS_VCFGEN1_TSEC4SER 0x20 -#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ - | PIXIS_VSPEED2_TSEC2SER \ - | PIXIS_VSPEED2_TSEC3SER \ - | PIXIS_VSPEED2_TSEC4SER) -#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ - | PIXIS_VCFGEN1_TSEC2SER \ - | PIXIS_VCFGEN1_TSEC3SER \ - | PIXIS_VCFGEN1_TSEC4SER) +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x20 +#endif #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -- cgit v1.1 From 933419096e857275b8b01f1ae577162231b143ff Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 7 Apr 2010 01:34:11 -0500 Subject: ppc/85xx: Use CONFIG_NS16550_MIN_FUNCTIONS to reduce NAND_SPL size The MPC8536DS_NAND SPL build was failing due to code size increase introduced by commit: commit 33f57bd553edf29dffef5a6c7d76e169c79a6049 Author: Kumar Gala Date: Fri Mar 26 15:14:43 2010 -0500 85xx: Fix enabling of L1 cache parity on secondary cores We built in some NS16550 functions that we dont need and can get rid of them via CONFIG_NS16550_MIN_FUNCTIONS. Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 3 +++ include/configs/MPC8569MDS.h | 3 +++ include/configs/P1_P2_RDB.h | 3 +++ 3 files changed, 9 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 87901b3..da4313a 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -413,6 +413,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9b81703..0c43b2b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -284,6 +284,9 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 405e6d5..a9b4004 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -286,6 +286,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ -- cgit v1.1 From 1f2463d7642c582339c9f9d96471d5d2a169b9bb Mon Sep 17 00:00:00 2001 From: Andre Schwarz Date: Thu, 1 Apr 2010 21:26:55 +0200 Subject: Add initial support for Matrix Vision mvSMR board based on MPC5200B. Signed-off-by: Andre Schwarz --- include/configs/MVSMR.h | 295 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 295 insertions(+) create mode 100644 include/configs/MVSMR.h (limited to 'include') diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h new file mode 100644 index 0000000..6492068 --- /dev/null +++ b/include/configs/MVSMR.h @@ -0,0 +1,295 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2010 + * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_MPC5xxx 1 +#define CONFIG_MPC5200 1 + +#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 + +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 + +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_SYS_CACHELINE_SIZE 32 +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 +#endif + +#define CONFIG_PSC_CONSOLE 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\ + 230400} + +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#undef CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_SYS_XLB_PIPELINING 1 +#define CONFIG_HIGH_BATS 1 + +#define MV_CI mvSMR +#define MV_VCI mvSMR +#define MV_FPGA_DATA 0xff840000 +#define MV_FPGA_SIZE 0x1ff88 +#define MV_KERNEL_ADDR 0xfff00000 +#define MV_SCRIPT_ADDR 0xff806000 +#define MV_INITRD_ADDR 0xff880000 +#define MV_INITRD_LENGTH 0x00240000 +#define MV_SCRATCH_ADDR 0xffcc0000 +#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define MV_KERNEL_ADDR_RAM 0x00100000 +#define MV_INITRD_ADDR_RAM 0x00400000 + +/* + * Supported commands + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SDRAM + +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_RANDOM_DELAY +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_VENDOREX + +/* + * Autoboot + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "abcdefg" +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_BOOTCOMMAND "source ${script_addr}" +#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \ + " allocate=6M" + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console_nr=0\0" \ + "console=no\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "fpga=0\0" \ + "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \ + "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \ + "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \ + "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \ + "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \ + "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \ + "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \ + "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \ + "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \ + "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \ + "mv_version=" U_BOOT_VERSION "\0" \ + "dhcp_client_id=" MK_STR(MV_CI) "\0" \ + "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \ + "netretry=no\0" \ + "use_static_ipaddr=no\0" \ + "static_ipaddr=192.168.0.101\0" \ + "static_netmask=255.255.255.0\0" \ + "static_gateway=0.0.0.0\0" \ + "initrd_name=uInitrd.mvsmr-rfs\0" \ + "zcip=yes\0" \ + "netboot=no\0" \ + "" + +#undef XMK_STR +#undef MK_STR + +/* + * IPB Bus clocking configuration. + */ +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK + +/* + * Flash configuration + */ +#undef CONFIG_FLASH_16BIT +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_SYS_FLASH_ERASE_TOUT 50000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_LOWBOOT +#define CONFIG_SYS_FLASH_BASE TEXT_BASE +#define CONFIG_SYS_FLASH_SIZE 0x00800000 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_HAS_UID +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x2000 + +/* used by linker script to wrap code around */ +#define CONFIG_SCRIPT_OFFSET 0x6000 +#define CONFIG_SCRIPT_SECT_SIZE 0x2000 + +/* + * Memory map + */ +#define CONFIG_SYS_MBAR 0xF0000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 + +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE + +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT 1 +#endif + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (512 << 10) +#define CONFIG_SYS_MALLOC_LEN (512 << 10) +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_MODULE 1 +#define CONFIG_SYS_I2C_SPEED 86000 +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* + * Ethernet configuration + */ +#define CONFIG_NET_RETRY_COUNT 5 + +#define CONFIG_MPC5xxx_FEC +#define CONFIG_MPC5xxx_FEC_MII100 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_NETDEV eth0 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#undef CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 +#else +#define CONFIG_SYS_CBSIZE 256 +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x02f00000 + +#define CONFIG_SYS_HZ 1000 + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x02000000 +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 0x00200000 + +/* + * Various low-level settings + */ +#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044 + +#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) +#define CONFIG_SYS_HID0_FINAL HID0_ICE + +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE +#define CONFIG_SYS_BOOTCS_CFG 0x00047800 +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + +#define CONFIG_SYS_CS_BURST 0x000000f0 +#define CONFIG_SYS_CS_DEADCYCLE 0x33333303 + +#define CONFIG_SYS_RESET_ADDRESS 0x00000100 + +#undef FPGA_DEBUG +#undef CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_FPGA CONFIG_SYS_XILINX_SPARTAN2 +#define CONFIG_FPGA_XILINX 1 +#define CONFIG_FPGA_SPARTAN2 1 +#define CONFIG_FPGA_COUNT 1 + +#endif -- cgit v1.1 From 9157e9c40ab3a942bdd0679bb433cd9ed485f434 Mon Sep 17 00:00:00 2001 From: Frans Meulenbroeks Date: Thu, 8 Apr 2010 17:55:47 +0200 Subject: config_cmd_all.h: added missing CONFIG_CMD_UBI and CONFIG_CMD_UBIFS Signed-off-by: Frans Meulenbroeks --- include/config_cmd_all.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 058fdf1..1cb7067 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -79,6 +79,8 @@ #define CONFIG_CMD_SOURCE /* "source" command support */ #define CONFIG_CMD_SPI /* SPI utility */ #define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */ +#define CONFIG_CMD_UBI /* UBI Support */ +#define CONFIG_CMD_UBIFS /* UBIFS Support */ #define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */ #define CONFIG_CMD_UNZIP /* unzip from memory to memory */ #define CONFIG_CMD_USB /* USB Support */ -- cgit v1.1 From 8178110bc28249f3ff1c22b15d7dcdee50be69eb Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Thu, 8 Apr 2010 17:55:48 +0200 Subject: config_cmd_all.h: Sort entries alphabetically Signed-off-by: Detlev Zundel --- include/config_cmd_all.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 1cb7067..746bf18 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -15,6 +15,7 @@ #define CONFIG_CMD_AMBAPP /* AMBA Plug & Play Bus print utility */ #define CONFIG_CMD_ASKENV /* ask for env variable */ +#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */ #define CONFIG_CMD_BDI /* bdinfo */ #define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */ #define CONFIG_CMD_BMP /* BMP support */ @@ -33,7 +34,6 @@ #define CONFIG_CMD_EDITENV /* editenv */ #define CONFIG_CMD_EEPROM /* EEPROM read/write support */ #define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */ -#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_FDC /* Floppy Disk Support */ @@ -55,6 +55,7 @@ #define CONFIG_CMD_LOADS /* loads */ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ #define CONFIG_CMD_MFSL /* FSL support for Microblaze */ +#define CONFIG_CMD_MG_DISK /* mGine m(g)flash IO node support */ #define CONFIG_CMD_MII /* MII support */ #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ #define CONFIG_CMD_MMC /* MMC support */ @@ -70,6 +71,7 @@ #define CONFIG_CMD_REGINFO /* Register dump */ #define CONFIG_CMD_REISER /* Reiserfs support */ #define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SAVES /* save S record dump */ #define CONFIG_CMD_SCSI /* SCSI Support */ #define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ @@ -86,7 +88,5 @@ #define CONFIG_CMD_USB /* USB Support */ #define CONFIG_CMD_VFD /* VFD support (TRAB) */ #define CONFIG_CMD_XIMG /* Load part of Multi Image */ -#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */ -#define CONFIG_CMD_MG_DISK /* mGine m(g)flash IO node support */ #endif /* _CONFIG_CMD_ALL_H */ -- cgit v1.1 From ea0364f1bbfed1e3ea711147420875cf338fe77a Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 12 Apr 2010 22:28:04 -0500 Subject: Move lib_$ARCH directories to arch/$ARCH/lib Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk This change is intended to clean up the top-level directory structure and more closely mimic Linux's directory organization. Signed-off-by: Peter Tyser --- include/asm-i386/interrupt.h | 2 +- include/asm-i386/u-boot-i386.h | 4 ++-- include/common.h | 8 ++++---- include/configs/B2.h | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/asm-i386/interrupt.h b/include/asm-i386/interrupt.h index 3e2674a..8d324d9 100644 --- a/include/asm-i386/interrupt.h +++ b/include/asm-i386/interrupt.h @@ -30,7 +30,7 @@ /* cpu/i386/interrupts.c */ void set_vector(u8 intnum, void *routine); -/* lib_i386/interupts.c */ +/* arch/i386/lib/interupts.c */ void disable_irq(int irq); void enable_irq(int irq); diff --git a/include/asm-i386/u-boot-i386.h b/include/asm-i386/u-boot-i386.h index 7c99c8c..a08632d 100644 --- a/include/asm-i386/u-boot-i386.h +++ b/include/asm-i386/u-boot-i386.h @@ -33,7 +33,7 @@ void timer_isr(void *); typedef void (timer_fnc_t) (void); int register_timer_isr (timer_fnc_t *isr_func); -/* Architecture specific - can be in cpu/i386/, lib_i386/, or $(BOARD)/ */ +/* Architecture specific - can be in cpu/i386/, arch/i386/lib/, or $(BOARD)/ */ int timer_init(void); /* cpu/.../interrupts.c */ @@ -46,7 +46,7 @@ int dram_init(void); void isa_unmap_rom(u32 addr); u32 isa_map_rom(u32 bus_addr, int size); -/* lib_i386/... */ +/* arch/i386/lib/... */ int video_bios_init(void); int video_init(void); diff --git a/include/common.h b/include/common.h index a133e34..7aa910d 100644 --- a/include/common.h +++ b/include/common.h @@ -230,7 +230,7 @@ int parse_line (char *, char *[]); void init_cmd_timeout(void); void reset_cmd_timeout(void); -/* lib_$(ARCH)/board.c */ +/* arch/$(ARCH)/lib/board.c */ void board_init_f (ulong) __attribute__ ((noreturn)); void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); int checkboard (void); @@ -604,17 +604,17 @@ ulong vfd_setmem (ulong); /* $(CPU)/.../video.c */ ulong video_setmem (ulong); -/* lib_$(ARCH)/cache.c */ +/* arch/$(ARCH)/lib/cache.c */ void flush_cache (unsigned long, unsigned long); void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); -/* lib_$(ARCH)/ticks.S */ +/* arch/$(ARCH)/lib/ticks.S */ unsigned long long get_ticks(void); void wait_ticks (unsigned long); -/* lib_$(ARCH)/time.c */ +/* arch/$(ARCH)/lib/time.c */ void __udelay (unsigned long); ulong usec2ticks (unsigned long usec); ulong ticks2usec (unsigned long ticks); diff --git a/include/configs/B2.h b/include/configs/B2.h index f51a261..ca7350d 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -207,7 +207,7 @@ */ /* - Linux TAGs (see lib_arm/armlinux.c) + Linux TAGs (see arch/arm/lib/armlinux.c) */ #define CONFIG_CMDLINE_TAG #undef CONFIG_SETUP_MEMORY_TAGS -- cgit v1.1 From 78acc472d9719316f22e002a009a998d9ceec29d Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 12 Apr 2010 22:28:05 -0500 Subject: Rename lib_generic/ to lib/ Now that the other architecture-specific lib directories have been moved out of the top-level directory there's not much reason to have the '_generic' suffix on the common lib directory. Signed-off-by: Peter Tyser --- include/common.h | 12 ++++++------ include/configs/bf533-stamp.h | 2 +- include/configs/bf537-pnav.h | 2 +- include/configs/bf537-stamp.h | 2 +- include/configs/bf538f-ezkit.h | 2 +- include/configs/bf561-ezkit.h | 4 ++-- include/configs/cm-bf537e.h | 2 +- include/configs/cm-bf537u.h | 2 +- include/configs/ibf-dsp561.h | 4 ++-- include/configs/tcm-bf537.h | 2 +- include/lzma/LzmaDec.h | 2 +- include/lzma/LzmaTools.h | 2 +- include/lzma/LzmaTypes.h | 2 +- include/u-boot/crc.h | 2 +- 14 files changed, 21 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 7aa910d..df956bb 100644 --- a/include/common.h +++ b/include/common.h @@ -620,22 +620,22 @@ ulong usec2ticks (unsigned long usec); ulong ticks2usec (unsigned long ticks); int init_timebase (void); -/* lib_generic/gunzip.c */ +/* lib/gunzip.c */ int gunzip(void *, int, unsigned char *, unsigned long *); int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, int stoponerr, int offset); -/* lib_generic/net_utils.c */ +/* lib/net_utils.c */ #include static inline IPaddr_t getenv_IPaddr (char *var) { return (string_to_ip(getenv(var))); } -/* lib_generic/time.c */ +/* lib/time.c */ void udelay (unsigned long); -/* lib_generic/vsprintf.c */ +/* lib/vsprintf.c */ ulong simple_strtoul(const char *cp,char **endp,unsigned int base); unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); long simple_strtol(const char *cp,char **endp,unsigned int base); @@ -645,10 +645,10 @@ int sprintf(char * buf, const char *fmt, ...) __attribute__ ((format (__printf__, 2, 3))); int vsprintf(char *buf, const char *fmt, va_list args); -/* lib_generic/strmhz.c */ +/* lib/strmhz.c */ char * strmhz(char *buf, long hz); -/* lib_generic/crc32.c */ +/* lib/crc32.c */ #include /* common/console.c */ diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 083c030..0b94f55 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -130,7 +130,7 @@ cpu/blackfin/interrupt.o (.text .text.*); \ cpu/blackfin/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 6627a04..8038c40 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -116,7 +116,7 @@ cpu/blackfin/interrupt.o (.text .text.*); \ cpu/blackfin/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index d3159e5..0f8679b 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -126,7 +126,7 @@ cpu/blackfin/interrupt.o (.text .text.*); \ cpu/blackfin/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index 4ea2300..696fe29 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -123,7 +123,7 @@ cpu/blackfin/interrupt.o (.text .text.*); \ cpu/blackfin/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 8ab38bb..fca6e43 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -100,8 +100,8 @@ cpu/blackfin/interrupt.o (.text .text.*); \ cpu/blackfin/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ - lib_generic/zlib.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ + lib/zlib.o (.text .text.*); \ board/bf561-ezkit/bf561-ezkit.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 0d68eba..d86409f 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -108,7 +108,7 @@ cpu/blackfin/interrupt.o (.text .text.*); \ cpu/blackfin/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index c1179b0..6be9dba 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -109,7 +109,7 @@ cpu/blackfin/interrupt.o (.text .text.*); \ cpu/blackfin/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 7c9f71e..6fa8cf7 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -88,8 +88,8 @@ cpu/blackfin/interrupt.o (.text .text.*); \ cpu/blackfin/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ - lib_generic/zlib.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ + lib/zlib.o (.text .text.*); \ board/ibf-dsp561/ibf-dsp561.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 5a5fbdd..e9dfcc9 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -109,7 +109,7 @@ cpu/blackfin/interrupt.o (.text .text.*); \ cpu/blackfin/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text .text.*); #endif diff --git a/include/lzma/LzmaDec.h b/include/lzma/LzmaDec.h index 967cdd1..b7ef6d6 100644 --- a/include/lzma/LzmaDec.h +++ b/include/lzma/LzmaDec.h @@ -26,6 +26,6 @@ #ifndef __LZMADEC_H__FAKE__ #define __LZMADEC_H__FAKE__ -#include "../../lib_generic/lzma/LzmaDec.h" +#include "../../lib/lzma/LzmaDec.h" #endif diff --git a/include/lzma/LzmaTools.h b/include/lzma/LzmaTools.h index 87943c0..48b0af8 100644 --- a/include/lzma/LzmaTools.h +++ b/include/lzma/LzmaTools.h @@ -26,6 +26,6 @@ #ifndef __LZMATOOLS_H__FAKE__ #define __LZMATOOLS_H__FAKE__ -#include "../../lib_generic/lzma/LzmaTools.h" +#include "../../lib/lzma/LzmaTools.h" #endif diff --git a/include/lzma/LzmaTypes.h b/include/lzma/LzmaTypes.h index 86160a4..740720c 100644 --- a/include/lzma/LzmaTypes.h +++ b/include/lzma/LzmaTypes.h @@ -31,6 +31,6 @@ */ #define Byte LZByte -#include "../../lib_generic/lzma/Types.h" +#include "../../lib/lzma/Types.h" #endif diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h index 61bce67..07badbf 100644 --- a/include/u-boot/crc.h +++ b/include/u-boot/crc.h @@ -25,7 +25,7 @@ #ifndef _UBOOT_CRC_H #define _UBOOT_CRC_H -/* lib_generic/crc32.c */ +/* lib/crc32.c */ uint32_t crc32 (uint32_t, const unsigned char *, uint); uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint); -- cgit v1.1 From 61f2b38a17f5b21c59f2afe6cf1cbb5f28638cf9 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 12 Apr 2010 22:28:07 -0500 Subject: Replace "#include " with "#include " The appropriate include/asm-$ARCH directory should already by symlinked to include/asm so using the whole "asm-$ARCH" path is unnecessary. This change should also allow us to move the include/asm-$ARCH directories into their appropriate lib/$ARCH/ directories. Signed-off-by: Peter Tyser --- include/asm-arm/arch-arm720t/hardware.h | 2 +- include/asm-arm/arch-lpc2292/hardware.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h index ec053c9..9bee19f 100644 --- a/include/asm-arm/arch-arm720t/hardware.h +++ b/include/asm-arm/arch-arm720t/hardware.h @@ -25,7 +25,7 @@ */ #if defined(CONFIG_NETARM) -#include +#include #elif defined(CONFIG_IMPA7) /* include IMPA7 specific hardware file if there was one */ #elif defined(CONFIG_EP7312) diff --git a/include/asm-arm/arch-lpc2292/hardware.h b/include/asm-arm/arch-lpc2292/hardware.h index fd2b464..5e227e3 100644 --- a/include/asm-arm/arch-lpc2292/hardware.h +++ b/include/asm-arm/arch-lpc2292/hardware.h @@ -25,7 +25,7 @@ */ #if defined(CONFIG_LPC2292) -#include +#include #else #error No hardware file defined for this configuration #endif -- cgit v1.1 From 819833af39a91fa1c1e8252862bbda6f5a602f7b Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 12 Apr 2010 22:28:08 -0500 Subject: Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser --- include/asm-arm/arch-a320/a320.h | 34 - include/asm-arm/arch-a320/ftpmu010.h | 146 - include/asm-arm/arch-a320/ftsdmc020.h | 103 - include/asm-arm/arch-a320/ftsmc020.h | 79 - include/asm-arm/arch-a320/fttmr010.h | 73 - include/asm-arm/arch-arm720t/hardware.h | 41 - include/asm-arm/arch-arm720t/netarm_dma_module.h | 182 - include/asm-arm/arch-arm720t/netarm_eni_module.h | 121 - include/asm-arm/arch-arm720t/netarm_eth_module.h | 160 - include/asm-arm/arch-arm720t/netarm_gen_module.h | 186 - include/asm-arm/arch-arm720t/netarm_mem_module.h | 184 - include/asm-arm/arch-arm720t/netarm_registers.h | 96 - include/asm-arm/arch-arm720t/netarm_ser_module.h | 347 - include/asm-arm/arch-arm925t/sizes.h | 50 - include/asm-arm/arch-arm926ejs/sizes.h | 51 - include/asm-arm/arch-at91/at91_common.h | 39 - include/asm-arm/arch-at91/at91_emac.h | 143 - include/asm-arm/arch-at91/at91_matrix.h | 116 - include/asm-arm/arch-at91/at91_mc.h | 97 - include/asm-arm/arch-at91/at91_pdc.h | 39 - include/asm-arm/arch-at91/at91_pio.h | 160 - include/asm-arm/arch-at91/at91_pit.h | 47 - include/asm-arm/arch-at91/at91_pmc.h | 227 - include/asm-arm/arch-at91/at91_rstc.h | 69 - include/asm-arm/arch-at91/at91_spi.h | 126 - include/asm-arm/arch-at91/at91_st.h | 46 - include/asm-arm/arch-at91/at91_tc.h | 77 - include/asm-arm/arch-at91/at91_wdt.h | 67 - include/asm-arm/arch-at91/at91cap9.h | 150 - include/asm-arm/arch-at91/at91cap9_matrix.h | 132 - include/asm-arm/arch-at91/at91rm9200.h | 135 - include/asm-arm/arch-at91/at91sam9260.h | 147 - include/asm-arm/arch-at91/at91sam9260_matrix.h | 80 - include/asm-arm/arch-at91/at91sam9261.h | 119 - include/asm-arm/arch-at91/at91sam9261_matrix.h | 64 - include/asm-arm/arch-at91/at91sam9263.h | 152 - include/asm-arm/arch-at91/at91sam9263_matrix.h | 129 - include/asm-arm/arch-at91/at91sam9_matrix.h | 30 - include/asm-arm/arch-at91/at91sam9_sdramc.h | 100 - include/asm-arm/arch-at91/at91sam9_smc.h | 139 - include/asm-arm/arch-at91/at91sam9g45.h | 152 - include/asm-arm/arch-at91/at91sam9g45_matrix.h | 153 - include/asm-arm/arch-at91/at91sam9rl.h | 130 - include/asm-arm/arch-at91/at91sam9rl_matrix.h | 96 - include/asm-arm/arch-at91/clk.h | 63 - include/asm-arm/arch-at91/gpio.h | 238 - include/asm-arm/arch-at91/hardware.h | 77 - include/asm-arm/arch-at91/io.h | 43 - include/asm-arm/arch-at91/memory-map.h | 35 - include/asm-arm/arch-at91rm9200/AT91RM9200.h | 812 - include/asm-arm/arch-at91rm9200/hardware.h | 75 - include/asm-arm/arch-davinci/emac_defs.h | 393 - include/asm-arm/arch-davinci/emif_defs.h | 87 - include/asm-arm/arch-davinci/gpio_defs.h | 66 - include/asm-arm/arch-davinci/hardware.h | 446 - include/asm-arm/arch-davinci/i2c_defs.h | 99 - include/asm-arm/arch-davinci/nand_defs.h | 45 - include/asm-arm/arch-ep93xx/ep93xx.h | 596 - include/asm-arm/arch-imx/imx-regs.h | 634 - include/asm-arm/arch-ixp/ixp425.h | 543 - include/asm-arm/arch-ixp/ixp425pci.h | 312 - include/asm-arm/arch-kirkwood/cpu.h | 169 - include/asm-arm/arch-kirkwood/gpio.h | 65 - include/asm-arm/arch-kirkwood/kirkwood.h | 71 - include/asm-arm/arch-kirkwood/kw88f6192.h | 37 - include/asm-arm/arch-kirkwood/kw88f6281.h | 37 - include/asm-arm/arch-kirkwood/mpp.h | 317 - include/asm-arm/arch-kirkwood/spi.h | 56 - include/asm-arm/arch-ks8695/platform.h | 306 - include/asm-arm/arch-lpc2292/hardware.h | 33 - include/asm-arm/arch-lpc2292/lpc2292_registers.h | 225 - include/asm-arm/arch-lpc2292/spi.h | 82 - include/asm-arm/arch-mx25/clock.h | 36 - include/asm-arm/arch-mx25/imx-regs.h | 316 - include/asm-arm/arch-mx25/imx25-pinmux.h | 421 - include/asm-arm/arch-mx27/asm-offsets.h | 16 - include/asm-arm/arch-mx27/clock.h | 42 - include/asm-arm/arch-mx27/imx-regs.h | 519 - include/asm-arm/arch-mx27/mxcmmc.h | 25 - include/asm-arm/arch-mx31/mx31-regs.h | 297 - include/asm-arm/arch-mx31/mx31.h | 54 - include/asm-arm/arch-mx51/asm-offsets.h | 50 - include/asm-arm/arch-mx51/clock.h | 43 - include/asm-arm/arch-mx51/crm_regs.h | 192 - include/asm-arm/arch-mx51/imx-regs.h | 261 - include/asm-arm/arch-mx51/iomux.h | 193 - include/asm-arm/arch-mx51/mx51_pins.h | 374 - include/asm-arm/arch-mx51/sys_proto.h | 30 - include/asm-arm/arch-nomadik/gpio.h | 42 - include/asm-arm/arch-nomadik/mtu.h | 66 - include/asm-arm/arch-omap/sizes.h | 52 - include/asm-arm/arch-omap24xx/bits.h | 48 - include/asm-arm/arch-omap24xx/clocks.h | 112 - include/asm-arm/arch-omap24xx/i2c.h | 172 - include/asm-arm/arch-omap24xx/mem.h | 156 - include/asm-arm/arch-omap24xx/mux.h | 176 - include/asm-arm/arch-omap24xx/omap2420.h | 246 - include/asm-arm/arch-omap24xx/sizes.h | 49 - include/asm-arm/arch-omap24xx/sys_info.h | 82 - include/asm-arm/arch-omap24xx/sys_proto.h | 54 - include/asm-arm/arch-omap3/clocks.h | 62 - include/asm-arm/arch-omap3/clocks_omap3.h | 285 - include/asm-arm/arch-omap3/cpu.h | 461 - include/asm-arm/arch-omap3/gpio.h | 86 - include/asm-arm/arch-omap3/i2c.h | 203 - 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delete mode 100644 include/asm-sparc/stack.h delete mode 100644 include/asm-sparc/string.h delete mode 100644 include/asm-sparc/types.h delete mode 100644 include/asm-sparc/u-boot.h delete mode 100644 include/asm-sparc/winmacro.h (limited to 'include') diff --git a/include/asm-arm/arch-a320/a320.h b/include/asm-arm/arch-a320/a320.h deleted file mode 100644 index fbd1583..0000000 --- a/include/asm-arm/arch-a320/a320.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __A320_H -#define __A320_H - -/* - * Hardware register bases - */ -#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */ -#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */ -#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */ -#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ -#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ -#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */ -#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/ - -#endif /* __A320_H */ diff --git a/include/asm-arm/arch-a320/ftpmu010.h b/include/asm-arm/arch-a320/ftpmu010.h deleted file mode 100644 index 8ef7a37..0000000 --- a/include/asm-arm/arch-a320/ftpmu010.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Power Management Unit - */ -#ifndef __FTPMU010_H -#define __FTPMU010_H - -struct ftpmu010 { - unsigned int IDNMBR0; /* 0x00 */ - unsigned int reserved0; /* 0x04 */ - unsigned int OSCC; /* 0x08 */ - unsigned int PMODE; /* 0x0C */ - unsigned int PMCR; /* 0x10 */ - unsigned int PED; /* 0x14 */ - unsigned int PEDSR; /* 0x18 */ - unsigned int reserved1; /* 0x1C */ - unsigned int PMSR; /* 0x20 */ - unsigned int PGSR; /* 0x24 */ - unsigned int MFPSR; /* 0x28 */ - unsigned int MISC; /* 0x2C */ - unsigned int PDLLCR0; /* 0x30 */ - unsigned int PDLLCR1; /* 0x34 */ - unsigned int AHBMCLKOFF; /* 0x38 */ - unsigned int APBMCLKOFF; /* 0x3C */ - unsigned int DCSRCR0; /* 0x40 */ - unsigned int DCSRCR1; /* 0x44 */ - unsigned int DCSRCR2; /* 0x48 */ - unsigned int SDRAMHTC; /* 0x4C */ - unsigned int PSPR0; /* 0x50 */ - unsigned int PSPR1; /* 0x54 */ - unsigned int PSPR2; /* 0x58 */ - unsigned int PSPR3; /* 0x5C */ - unsigned int PSPR4; /* 0x60 */ - unsigned int PSPR5; /* 0x64 */ - unsigned int PSPR6; /* 0x68 */ - unsigned int PSPR7; /* 0x6C */ - unsigned int PSPR8; /* 0x70 */ - unsigned int PSPR9; /* 0x74 */ - unsigned int PSPR10; /* 0x78 */ - unsigned int PSPR11; /* 0x7C */ - unsigned int PSPR12; /* 0x80 */ - unsigned int PSPR13; /* 0x84 */ - unsigned int PSPR14; /* 0x88 */ - unsigned int PSPR15; /* 0x8C */ - unsigned int AHBDMA_RACCS; /* 0x90 */ - unsigned int reserved2; /* 0x94 */ - unsigned int reserved3; /* 0x98 */ - unsigned int JSS; /* 0x9C */ - unsigned int CFC_RACC; /* 0xA0 */ - unsigned int SSP1_RACC; /* 0xA4 */ - unsigned int UART1TX_RACC; /* 0xA8 */ - unsigned int UART1RX_RACC; /* 0xAC */ - unsigned int UART2TX_RACC; /* 0xB0 */ - unsigned int UART2RX_RACC; /* 0xB4 */ - unsigned int SDC_RACC; /* 0xB8 */ - unsigned int I2SAC97_RACC; /* 0xBC */ - unsigned int IRDATX_RACC; /* 0xC0 */ - unsigned int reserved4; /* 0xC4 */ - unsigned int USBD_RACC; /* 0xC8 */ - unsigned int IRDARX_RACC; /* 0xCC */ - unsigned int IRDA_RACC; /* 0xD0 */ - unsigned int ED0_RACC; /* 0xD4 */ - unsigned int ED1_RACC; /* 0xD8 */ -}; - -/* - * ID Number 0 Register - */ -#define FTPMU010_ID_A320A 0x03200000 -#define FTPMU010_ID_A320C 0x03200010 -#define FTPMU010_ID_A320D 0x03200030 - -/* - * OSC Control Register - */ -#define FTPMU010_OSCC_OSCH_TRI (1 << 11) -#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) -#define FTPMU010_OSCC_OSCH_OFF (1 << 8) - -#define FTPMU010_OSCC_OSCL_TRI (1 << 3) -#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) -#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) -#define FTPMU010_OSCC_OSCL_OFF (1 << 0) - -/* - * Power Mode Register - */ -#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) -#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) -#define FTPMU010_PMODE_FCS (1 << 2) -#define FTPMU010_PMODE_TURBO (1 << 1) -#define FTPMU010_PMODE_SLEEP (1 << 0) - -/* - * Power Manager Status Register - */ -#define FTPMU010_PMSR_SMR (1 << 10) - -#define FTPMU010_PMSR_RDH (1 << 2) -#define FTPMU010_PMSR_PH (1 << 1) -#define FTPMU010_PMSR_CKEHLOW (1 << 0) - -/* - * Multi-Function Port Setting Register - */ -#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) -#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) -#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) - -/* - * PLL/DLL Control Register 0 - */ -#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf) -#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19) -#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) -#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) -#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) -#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff) -#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) -#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) -#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) - -#endif /* __FTPMU010_H */ diff --git a/include/asm-arm/arch-a320/ftsdmc020.h b/include/asm-arm/arch-a320/ftsdmc020.h deleted file mode 100644 index 0699772..0000000 --- a/include/asm-arm/arch-a320/ftsdmc020.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * SDRAM Controller - */ -#ifndef __FTSDMC020_H -#define __FTSDMC020_H - -#define FTSDMC020_OFFSET_TP0 0x00 -#define FTSDMC020_OFFSET_TP1 0x04 -#define FTSDMC020_OFFSET_CR 0x08 -#define FTSDMC020_OFFSET_BANK0_BSR 0x0C -#define FTSDMC020_OFFSET_BANK1_BSR 0x10 -#define FTSDMC020_OFFSET_BANK2_BSR 0x14 -#define FTSDMC020_OFFSET_BANK3_BSR 0x18 -#define FTSDMC020_OFFSET_BANK4_BSR 0x1C -#define FTSDMC020_OFFSET_BANK5_BSR 0x20 -#define FTSDMC020_OFFSET_BANK6_BSR 0x24 -#define FTSDMC020_OFFSET_BANK7_BSR 0x28 -#define FTSDMC020_OFFSET_ACR 0x34 - -/* - * Timing Parametet 0 Register - */ -#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) -#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) -#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) -#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) -#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parametet 1 Register - */ -#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) -#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * Configuration Register - */ -#define FTSDMC020_CR_SREF (1 << 0) -#define FTSDMC020_CR_PWDN (1 << 1) -#define FTSDMC020_CR_ISMR (1 << 2) -#define FTSDMC020_CR_IREF (1 << 3) -#define FTSDMC020_CR_IPREC (1 << 4) -#define FTSDMC020_CR_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC020_BANK_ENABLE (1 << 28) - -#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) - -#define FTSDMC020_BANK_DDW_X4 (0 << 12) -#define FTSDMC020_BANK_DDW_X8 (1 << 12) -#define FTSDMC020_BANK_DDW_X16 (2 << 12) -#define FTSDMC020_BANK_DDW_X32 (3 << 12) - -#define FTSDMC020_BANK_DSZ_16M (0 << 8) -#define FTSDMC020_BANK_DSZ_64M (1 << 8) -#define FTSDMC020_BANK_DSZ_128M (2 << 8) -#define FTSDMC020_BANK_DSZ_256M (3 << 8) - -#define FTSDMC020_BANK_MBW_8 (0 << 4) -#define FTSDMC020_BANK_MBW_16 (1 << 4) -#define FTSDMC020_BANK_MBW_32 (2 << 4) - -#define FTSDMC020_BANK_SIZE_1M 0x0 -#define FTSDMC020_BANK_SIZE_2M 0x1 -#define FTSDMC020_BANK_SIZE_4M 0x2 -#define FTSDMC020_BANK_SIZE_8M 0x3 -#define FTSDMC020_BANK_SIZE_16M 0x4 -#define FTSDMC020_BANK_SIZE_32M 0x5 -#define FTSDMC020_BANK_SIZE_64M 0x6 -#define FTSDMC020_BANK_SIZE_128M 0x7 -#define FTSDMC020_BANK_SIZE_256M 0x8 - -/* - * Arbiter Control Register - */ -#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) -#define FTSDMC020_ACR_TOE (1 << 8) - -#endif /* __FTSDMC020_H */ diff --git a/include/asm-arm/arch-a320/ftsmc020.h b/include/asm-arm/arch-a320/ftsmc020.h deleted file mode 100644 index 95d9500..0000000 --- a/include/asm-arm/arch-a320/ftsmc020.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Static Memory Controller - */ -#ifndef __FTSMC020_H -#define __FTSMC020_H - -#ifndef __ASSEMBLY__ - -struct ftsmc020 { - struct { - unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ - unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ - } bank[4]; - unsigned int pad[8]; /* 0x20 - 0x3c */ - unsigned int ssr; /* 0x40 */ -}; - -void ftsmc020_init(void); - -#endif /* __ASSEMBLY__ */ - -/* - * Memory Bank Configuration Register - */ -#define FTSMC020_BANK_ENABLE (1 << 28) -#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) - -#define FTSMC020_BANK_WPROT (1 << 11) - -#define FTSMC020_BANK_SIZE_32K (0xb << 4) -#define FTSMC020_BANK_SIZE_64K (0xc << 4) -#define FTSMC020_BANK_SIZE_128K (0xd << 4) -#define FTSMC020_BANK_SIZE_256K (0xe << 4) -#define FTSMC020_BANK_SIZE_512K (0xf << 4) -#define FTSMC020_BANK_SIZE_1M (0x0 << 4) -#define FTSMC020_BANK_SIZE_2M (0x1 << 4) -#define FTSMC020_BANK_SIZE_4M (0x2 << 4) -#define FTSMC020_BANK_SIZE_8M (0x3 << 4) -#define FTSMC020_BANK_SIZE_16M (0x4 << 4) -#define FTSMC020_BANK_SIZE_32M (0x5 << 4) - -#define FTSMC020_BANK_MBW_8 (0x0 << 0) -#define FTSMC020_BANK_MBW_16 (0x1 << 0) -#define FTSMC020_BANK_MBW_32 (0x2 << 0) - -/* - * Memory Bank Timing Parameter Register - */ -#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) -#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) -#define FTSMC020_TPR_RBE (1 << 20) -#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) -#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) -#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) -#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) -#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) -#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) -#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) - -#endif /* __FTSMC020_H */ diff --git a/include/asm-arm/arch-a320/fttmr010.h b/include/asm-arm/arch-a320/fttmr010.h deleted file mode 100644 index 72abcb3..0000000 --- a/include/asm-arm/arch-a320/fttmr010.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Timer - */ -#ifndef __FTTMR010_H -#define __FTTMR010_H - -struct fttmr010 { - unsigned int timer1_counter; /* 0x00 */ - unsigned int timer1_load; /* 0x04 */ - unsigned int timer1_match1; /* 0x08 */ - unsigned int timer1_match2; /* 0x0c */ - unsigned int timer2_counter; /* 0x10 */ - unsigned int timer2_load; /* 0x14 */ - unsigned int timer2_match1; /* 0x18 */ - unsigned int timer2_match2; /* 0x1c */ - unsigned int timer3_counter; /* 0x20 */ - unsigned int timer3_load; /* 0x24 */ - unsigned int timer3_match1; /* 0x28 */ - unsigned int timer3_match2; /* 0x2c */ - unsigned int cr; /* 0x30 */ - unsigned int interrupt_state; /* 0x34 */ - unsigned int interrupt_mask; /* 0x38 */ -}; - -/* - * Timer Control Register - */ -#define FTTMR010_TM3_UPDOWN (1 << 11) -#define FTTMR010_TM2_UPDOWN (1 << 10) -#define FTTMR010_TM1_UPDOWN (1 << 9) -#define FTTMR010_TM3_OFENABLE (1 << 8) -#define FTTMR010_TM3_CLOCK (1 << 7) -#define FTTMR010_TM3_ENABLE (1 << 6) -#define FTTMR010_TM2_OFENABLE (1 << 5) -#define FTTMR010_TM2_CLOCK (1 << 4) -#define FTTMR010_TM2_ENABLE (1 << 3) -#define FTTMR010_TM1_OFENABLE (1 << 2) -#define FTTMR010_TM1_CLOCK (1 << 1) -#define FTTMR010_TM1_ENABLE (1 << 0) - -/* - * Timer Interrupt State & Mask Registers - */ -#define FTTMR010_TM3_OVERFLOW (1 << 8) -#define FTTMR010_TM3_MATCH2 (1 << 7) -#define FTTMR010_TM3_MATCH1 (1 << 6) -#define FTTMR010_TM2_OVERFLOW (1 << 5) -#define FTTMR010_TM2_MATCH2 (1 << 4) -#define FTTMR010_TM2_MATCH1 (1 << 3) -#define FTTMR010_TM1_OVERFLOW (1 << 2) -#define FTTMR010_TM1_MATCH2 (1 << 1) -#define FTTMR010_TM1_MATCH1 (1 << 0) - -#endif /* __FTTMR010_H */ diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h deleted file mode 100644 index 9bee19f..0000000 --- a/include/asm-arm/arch-arm720t/hardware.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef __ARM7_HW_H -#define __ARM7_HW_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if defined(CONFIG_NETARM) -#include -#elif defined(CONFIG_IMPA7) -/* include IMPA7 specific hardware file if there was one */ -#elif defined(CONFIG_EP7312) -/* include EP7312 specific hardware file if there was one */ -#elif defined(CONFIG_ARMADILLO) -/* include armadillo specific hardware file if there was one */ -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) -/* include IntegratorCP/CM720T specific hardware file if there was one */ -#else -#error No hardware file defined for this configuration -#endif - -#endif /* __ARM7_HW_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_dma_module.h b/include/asm-arm/arch-arm720t/netarm_dma_module.h deleted file mode 100644 index 328eaf0..0000000 --- a/include/asm-arm/arch-arm720t/netarm_dma_module.h +++ /dev/null @@ -1,182 +0,0 @@ -/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * David Smith - */ - -#ifndef __NETARM_DMA_MODULE_REGISTERS_H -#define __NETARM_DMA_MODULE_REGISTERS_H - -/* GEN unit register offsets */ - -#define NETARM_DMA_MODULE_BASE (0xFF900000) - -#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c))) - -#define NETARM_DMA1A_BFR_DESCRPTOR_PTR (0x00) -#define NETARM_DMA1A_CONTROL (0x10) -#define NETARM_DMA1A_STATUS (0x14) -#define NETARM_DMA1B_BFR_DESCRPTOR_PTR (0x20) -#define NETARM_DMA1B_CONTROL (0x30) -#define NETARM_DMA1B_STATUS (0x34) -#define NETARM_DMA1C_BFR_DESCRPTOR_PTR (0x40) -#define NETARM_DMA1C_CONTROL (0x50) -#define NETARM_DMA1C_STATUS (0x54) -#define NETARM_DMA1D_BFR_DESCRPTOR_PTR (0x60) -#define NETARM_DMA1D_CONTROL (0x70) -#define NETARM_DMA1D_STATUS (0x74) - -#define NETARM_DMA2_BFR_DESCRPTOR_PTR (0x80) -#define NETARM_DMA2_CONTROL (0x90) -#define NETARM_DMA2_STATUS (0x94) - -#define NETARM_DMA3_BFR_DESCRPTOR_PTR (0xA0) -#define NETARM_DMA3_CONTROL (0xB0) -#define NETARM_DMA3_STATUS (0xB4) - -#define NETARM_DMA4_BFR_DESCRPTOR_PTR (0xC0) -#define NETARM_DMA4_CONTROL (0xD0) -#define NETARM_DMA4_STATUS (0xD4) - -#define NETARM_DMA5_BFR_DESCRPTOR_PTR (0xE0) -#define NETARM_DMA5_CONTROL (0xF0) -#define NETARM_DMA5_STATUS (0xF4) - -#define NETARM_DMA6_BFR_DESCRPTOR_PTR (0x100) -#define NETARM_DMA6_CONTROL (0x110) -#define NETARM_DMA6_STATUS (0x114) - -#define NETARM_DMA7_BFR_DESCRPTOR_PTR (0x120) -#define NETARM_DMA7_CONTROL (0x130) -#define NETARM_DMA7_STATUS (0x134) - -#define NETARM_DMA8_BFR_DESCRPTOR_PTR (0x140) -#define NETARM_DMA8_CONTROL (0x150) -#define NETARM_DMA8_STATUS (0x154) - -#define NETARM_DMA9_BFR_DESCRPTOR_PTR (0x160) -#define NETARM_DMA9_CONTROL (0x170) -#define NETARM_DMA9_STATUS (0x174) - -#define NETARM_DMA10_BFR_DESCRPTOR_PTR (0x180) -#define NETARM_DMA10_CONTROL (0x190) -#define NETARM_DMA10_STATUS (0x194) - -/* select bitfield defintions */ - -/* DMA Control Register ( 0xFF90_0XX0 ) */ - -#define NETARM_DMA_CTL_ENABLE (0x80000000) - -#define NETARM_DMA_CTL_ABORT (0x40000000) - -#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000) -#define NETARM_DMA_CTL_BUS_75_PERCENT (0x10000000) -#define NETARM_DMA_CTL_BUS_50_PERCENT (0x20000000) -#define NETARM_DMA_CTL_BUS_25_PERCENT (0x30000000) - -#define NETARM_DMA_CTL_BUS_MASK (0x30000000) - -#define NETARM_DMA_CTL_MODE_FB_TO_MEM (0x00000000) -#define NETARM_DMA_CTL_MODE_FB_FROM_MEM (0x04000000) -#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000) - -#define NETARM_DMA_CTL_BURST_NONE (0x00000000) -#define NETARM_DMA_CTL_BURST_8_BYTE (0x01000000) -#define NETARM_DMA_CTL_BURST_16_BYTE (0x02000000) - -#define NETARM_DMA_CTL_BURST_MASK (0x03000000) - -#define NETARM_DMA_CTL_SRC_INCREMENT (0x00200000) - -#define NETARM_DMA_CTL_DST_INCREMENT (0x00100000) - -/* these apply only to ext xfers on DMA 3 or 4 */ - -#define NETARM_DMA_CTL_CH_3_4_REQ_EXT (0x00800000) - -#define NETARM_DMA_CTL_CH_3_4_DATA_32 (0x00000000) -#define NETARM_DMA_CTL_CH_3_4_DATA_16 (0x00010000) -#define NETARM_DMA_CTL_CH_3_4_DATA_8 (0x00020000) - -#define NETARM_DMA_CTL_STATE(X) ((X) & 0xFC00) -#define NETARM_DMA_CTL_INDEX(X) ((X) & 0x03FF) - -/* DMA Status Register ( 0xFF90_0XX4 ) */ - -#define NETARM_DMA_STAT_NC_INTPEN (0x80000000) -#define NETARM_DMA_STAT_EC_INTPEN (0x40000000) -#define NETARM_DMA_STAT_NR_INTPEN (0x20000000) -#define NETARM_DMA_STAT_CA_INTPEN (0x10000000) -#define NETARM_DMA_STAT_INTPEN_MASK (0xF0000000) - -#define NETARM_DMA_STAT_NC_INT_EN (0x00800000) -#define NETARM_DMA_STAT_EC_INT_EN (0x00400000) -#define NETARM_DMA_STAT_NR_INT_EN (0x00200000) -#define NETARM_DMA_STAT_CA_INT_EN (0x00100000) -#define NETARM_DMA_STAT_INT_EN_MASK (0x00F00000) - -#define NETARM_DMA_STAT_WRAP (0x00080000) -#define NETARM_DMA_STAT_IDONE (0x00040000) -#define NETARM_DMA_STAT_LAST (0x00020000) -#define NETARM_DMA_STAT_FULL (0x00010000) - -#define NETARM_DMA_STAT_BUFLEN(X) ((X) & 0x7FFF) - -/* DMA Buffer Descriptor Word 0 bitfields. */ - -#define NETARM_DMA_BD0_WRAP (0x80000000) -#define NETARM_DMA_BD0_IDONE (0x40000000) -#define NETARM_DMA_BD0_LAST (0x20000000) -#define NETARM_DMA_BD0_BUFPTR_MASK (0x1FFFFFFF) - -/* DMA Buffer Descriptor Word 1 bitfields. */ - -#define NETARM_DMA_BD1_STATUS_MASK (0xFFFF0000) -#define NETARM_DMA_BD1_FULL (0x00008000) -#define NETARM_DMA_BD1_BUFLEN_MASK (0x00007FFF) - -#ifndef __ASSEMBLER__ - -typedef struct __NETARM_DMA_Buff_Desc_FlyBy -{ - unsigned int word0; - unsigned int word1; -} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ; - -typedef struct __NETARM_DMA_Buff_Desc_M_to_M -{ - unsigned int word0; - unsigned int word1; - unsigned int word2; - unsigned int word3; -} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ; - -#endif - -#endif diff --git a/include/asm-arm/arch-arm720t/netarm_eni_module.h b/include/asm-arm/arch-arm720t/netarm_eni_module.h deleted file mode 100644 index 317b354..0000000 --- a/include/asm-arm/arch-arm720t/netarm_eni_module.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_eni_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : David Smith - */ - -#ifndef __NETARM_ENI_MODULE_REGISTERS_H -#define __NETARM_ENI_MODULE_REGISTERS_H - -/* ENI unit register offsets */ - -/* #ifdef CONFIG_ARCH_NETARM */ -#define NETARM_ENI_MODULE_BASE (0xFFA00000) -/* #endif / * CONFIG_ARCH_NETARM */ - -#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c))) -#define get_eni_ctl_reg_addr(minor) \ - (get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor)) - -#define NETARM_ENI_GENERAL_CONTROL (0x00) -#define NETARM_ENI_STATUS_CONTROL (0x04) -#define NETARM_ENI_FIFO_MODE_DATA (0x08) - -#define NETARM_ENI_1284_PORT1_CONTROL (0x10) -#define NETARM_ENI_1284_PORT2_CONTROL (0x14) -#define NETARM_ENI_1284_PORT3_CONTROL (0x18) -#define NETARM_ENI_1284_PORT4_CONTROL (0x1c) - -#define NETARM_ENI_1284_CHANNEL1_DATA (0x20) -#define NETARM_ENI_1284_CHANNEL2_DATA (0x24) -#define NETARM_ENI_1284_CHANNEL3_DATA (0x28) -#define NETARM_ENI_1284_CHANNEL4_DATA (0x2c) - -#define NETARM_ENI_ENI_CONTROL (0x30) -#define NETARM_ENI_ENI_PULSED_INTR (0x34) -#define NETARM_ENI_ENI_SHARED_RAM_ADDR (0x38) -#define NETARM_ENI_ENI_SHARED (0x3c) - -/* select bitfield defintions */ - -/* General Control Register (0xFFA0_0000) */ - -#define NETARM_ENI_GCR_ENIMODE_IEEE1284 (0x00000001) -#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004) -#define NETARM_ENI_GCR_ENIMODE_SHRAM8 (0x00000005) -#define NETARM_ENI_GCR_ENIMODE_FIFO16 (0x00000006) -#define NETARM_ENI_GCR_ENIMODE_FIFO8 (0x00000007) - -#define NETARM_ENI_GCR_ENIMODE_MASK (0x00000007) - -/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014, - 0xFFA0_0018, 0xFFA0_001c) */ - -#define NETARM_ENI_1284PC_PORT_ENABLE (0x80000000) -#define NETARM_ENI_1284PC_DMA_ENABLE (0x40000000) -#define NETARM_ENI_1284PC_OBE_INT_EN (0x20000000) -#define NETARM_ENI_1284PC_ACK_INT_EN (0x10000000) -#define NETARM_ENI_1284PC_ECP_MODE (0x08000000) -#define NETARM_ENI_1284PC_LOOPBACK_MODE (0x04000000) - -#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */ -#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */ -#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */ -#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */ -#define NETARM_ENI_1284PC_STROBE_MASK (0x03000000) - -#define NETARM_ENI_1284PC_MAN_STROBE_EN (0x00800000) -#define NETARM_ENI_1284PC_FAST_MODE (0x00400000) -#define NETARM_ENI_1284PC_BIDIR_MODE (0x00200000) - -#define NETARM_ENI_1284PC_MAN_STROBE (0x00080000) -#define NETARM_ENI_1284PC_AUTO_FEED (0x00040000) -#define NETARM_ENI_1284PC_INIT (0x00020000) -#define NETARM_ENI_1284PC_HSELECT (0x00010000) -#define NETARM_ENI_1284PC_FE_INT_EN (0x00008000) -#define NETARM_ENI_1284PC_EPP_MODE (0x00004000) -#define NETARM_ENI_1284PC_IBR_INT_EN (0x00002000) -#define NETARM_ENI_1284PC_IBR (0x00001000) - -#define NETARM_ENI_1284PC_RXFDB_1BYTE (0x00000400) -#define NETARM_ENI_1284PC_RXFDB_2BYTE (0x00000800) -#define NETARM_ENI_1284PC_RXFDB_3BYTE (0x00000c00) -#define NETARM_ENI_1284PC_RXFDB_4BYTE (0x00000000) - -#define NETARM_ENI_1284PC_RBCC (0x00000200) -#define NETARM_ENI_1284PC_RBCT (0x00000100) -#define NETARM_ENI_1284PC_ACK (0x00000080) -#define NETARM_ENI_1284PC_FIFO_E (0x00000040) -#define NETARM_ENI_1284PC_OBE (0x00000020) -#define NETARM_ENI_1284PC_ACK_INT (0x00000010) -#define NETARM_ENI_1284PC_BUSY (0x00000008) -#define NETARM_ENI_1284PC_PE (0x00000004) -#define NETARM_ENI_1284PC_PSELECT (0x00000002) -#define NETARM_ENI_1284PC_FAULT (0x00000001) - -#endif /* __NETARM_ENI_MODULE_REGISTERS_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_eth_module.h b/include/asm-arm/arch-arm720t/netarm_eth_module.h deleted file mode 100644 index 8f2f369..0000000 --- a/include/asm-arm/arch-arm720t/netarm_eth_module.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_eth_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Jackie Smith Cashion - * David Smith - */ - -#ifndef __NETARM_ETH_MODULE_REGISTERS_H -#define __NETARM_ETH_MODULE_REGISTERS_H - -/* ETH unit register offsets */ - -#define NETARM_ETH_MODULE_BASE (0xFF800000) - -#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c))) - -#define NETARM_ETH_GEN_CTRL (0x000) /* Ethernet Gen Control Reg */ -#define NETARM_ETH_GEN_STAT (0x004) /* Ethernet Gen Status Reg */ -#define NETARM_ETH_FIFO_DAT1 (0x008) /* Fifo Data Reg 1 */ -#define NETARM_ETH_FIFO_DAT2 (0x00C) /* Fifo Data Reg 2 */ -#define NETARM_ETH_TX_STAT (0x010) /* Transmit Status Reg */ -#define NETARM_ETH_RX_STAT (0x014) /* Receive Status Reg */ - -#define NETARM_ETH_MAC_CFG (0x400) /* MAC Configuration Reg */ -#define NETARM_ETH_PCS_CFG (0x408) /* PCS Configuration Reg */ -#define NETARM_ETH_STL_CFG (0x410) /* STL Configuration Reg */ -#define NETARM_ETH_B2B_IPG_GAP_TMR (0x440) /* Back-to-back IPG - Gap Timer Reg */ -#define NETARM_ETH_NB2B_IPG_GAP_TMR (0x444) /* Non Back-to-back - IPG Gap Timer Reg */ -#define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */ -#define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */ -#define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */ -#define NETARM_ETH_MII_READ (0x54C) /* MII Read Data Reg */ -#define NETARM_ETH_MII_IND (0x550) /* MII Indicators Reg */ -#define NETARM_ETH_MIB_CRCEC (0x580) /* (MIB) CRC Error Counter */ -#define NETARM_ETH_MIB_AEC (0x584) /* Alignment Error Counter */ -#define NETARM_ETH_MIB_CEC (0x588) /* Code Error Counter */ -#define NETARM_ETH_MIB_LFC (0x58C) /* Long Frame Counter */ -#define NETARM_ETH_MIB_SFC (0x590) /* Short Frame Counter */ -#define NETARM_ETH_MIB_LCC (0x594) /* Late Collision Counter */ -#define NETARM_ETH_MIB_EDC (0x598) /* Excessive Deferral - Counter */ -#define NETARM_ETH_MIB_MCC (0x59C) /* Maximum Collision Counter */ -#define NETARM_ETH_SAL_FILTER (0x5C0) /* SAL Station Address - Filter Reg */ -#define NETARM_ETH_SAL_STATION_ADDR_1 (0x5C4) /* SAL Station Address - Reg */ -#define NETARM_ETH_SAL_STATION_ADDR_2 (0x5C8) -#define NETARM_ETH_SAL_STATION_ADDR_3 (0x5CC) -#define NETARM_ETH_SAL_HASH_TBL_1 (0x5D0) /* SAL Multicast Hash Table*/ -#define NETARM_ETH_SAL_HASH_TBL_2 (0x5D4) -#define NETARM_ETH_SAL_HASH_TBL_3 (0x5D8) -#define NETARM_ETH_SAL_HASH_TBL_4 (0x5DC) - -/* select bitfield defintions */ - -/* Ethernet General Control Register (0xFF80_0000) */ - -#define NETARM_ETH_GCR_ERX (0x80000000) /* Enable Receive FIFO */ -#define NETARM_ETH_GCR_ERXDMA (0x40000000) /* Enable Receive DMA */ -#define NETARM_ETH_GCR_ETX (0x00800000) /* Enable Transmit FIFO */ -#define NETARM_ETH_GCR_ETXDMA (0x00400000) /* Enable Transmit DMA */ -#define NETARM_ETH_GCR_ETXWM_50 (0x00100000) /* Transmit FIFO Water - Mark. Start transmit - when FIFO is 50% - full. */ -#define NETARM_ETH_GCR_PNA (0x00000400) /* pSOS pNA Buffer - Descriptor Format */ - -/* Ethernet General Status Register (0xFF80_0004) */ - -#define NETARM_ETH_GST_RXFDB (0x30000000) -#define NETARM_ETH_GST_RXREGR (0x08000000) /* Receive Register - Ready */ -#define NETARM_ETH_GST_RXFIFOH (0x04000000) -#define NETARM_ETH_GST_RXBR (0x02000000) -#define NETARM_ETH_GST_RXSKIP (0x01000000) - -#define NETARM_ETH_GST_TXBC (0x00020000) - - -/* Ethernet Transmit Status Register (0xFF80_0010) */ - -#define NETARM_ETH_TXSTAT_TXOK (0x00008000) - - -/* Ethernet Receive Status Register (0xFF80_0014) */ - -#define NETARM_ETH_RXSTAT_SIZE (0xFFFF0000) -#define NETARM_ETH_RXSTAT_RXOK (0x00002000) - - -/* PCS Configuration Register (0xFF80_0408) */ - -#define NETARM_ETH_PCSC_NOCFR (0x1) /* Disable Ciphering */ -#define NETARM_ETH_PCSC_ENJAB (0x2) /* Enable Jabber Protection */ -#define NETARM_ETH_PCSC_CLKS_25M (0x0) /* 25 MHz Clock Speed Select */ -#define NETARM_ETH_PCSC_CLKS_33M (0x4) /* 33 MHz Clock Speed Select */ - -/* STL Configuration Register (0xFF80_0410) */ - -#define NETARM_ETH_STLC_RXEN (0x2) /* Enable Packet Receiver */ -#define NETARM_ETH_STLC_AUTOZ (0x4) /* Auto Zero Statistics */ - -/* MAC Configuration Register (0xFF80_0400) */ - -#define NETARM_ETH_MACC_HUGEN (0x1) /* Enable Unlimited Transmit - Frame Sizes */ -#define NETARM_ETH_MACC_PADEN (0x4) /* Automatic Pad Fill Frames - to 64 Bytes */ -#define NETARM_ETH_MACC_CRCEN (0x8) /* Append CRC to Transmit - Frames */ - -/* MII (PHY) Command Register (0xFF80_0540) */ - -#define NETARM_ETH_MIIC_RSTAT (0x1) /* Single Scan for Read Data */ - -/* MII Indicators Register (0xFF80_0550) */ - -#define NETARM_ETH_MIII_BUSY (0x1) /* MII I/F Busy with - Read/Write */ - -/* SAL Station Address Filter Register (0xFF80_05C0) */ - -#define NETARM_ETH_SALF_PRO (0x8) /* Enable Promiscuous Mode */ -#define NETARM_ETH_SALF_PRM (0x4) /* Accept All Multicast - Packets */ -#define NETARM_ETH_SALF_PRA (0x2) /* Accept Mulitcast Packets - using Hash Table */ -#define NETARM_ETH_SALF_BROAD (0x1) /* Accept All Broadcast - Packets */ - - -#endif /* __NETARM_GEN_MODULE_REGISTERS_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_gen_module.h b/include/asm-arm/arch-arm720t/netarm_gen_module.h deleted file mode 100644 index 13656a3..0000000 --- a/include/asm-arm/arch-arm720t/netarm_gen_module.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_gen_module.h - * - * Copyright (C) 2005 - * Art Shipkowski, Videon Central, Inc., - * - * Copyright (C) 2000, 2001 NETsilicon, Inc. - * Copyright (C) 2000, 2001 Red Hat, Inc. - * - * This software is copyrighted by Red Hat. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall Red Hat - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * - * Modified to support NS7520 by Art Shipkowski. - */ - -#ifndef __NETARM_GEN_MODULE_REGISTERS_H -#define __NETARM_GEN_MODULE_REGISTERS_H - -/* GEN unit register offsets */ - -#define NETARM_GEN_MODULE_BASE (0xFFB00000) - -#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c))) - -#define NETARM_GEN_SYSTEM_CONTROL (0x00) -#define NETARM_GEN_STATUS_CONTROL (0x04) -#define NETARM_GEN_PLL_CONTROL (0x08) -#define NETARM_GEN_SOFTWARE_SERVICE (0x0c) - -#define NETARM_GEN_TIMER1_CONTROL (0x10) -#define NETARM_GEN_TIMER1_STATUS (0x14) -#define NETARM_GEN_TIMER2_CONTROL (0x18) -#define NETARM_GEN_TIMER2_STATUS (0x1c) - -#define NETARM_GEN_PORTA (0x20) -#ifndef CONFIG_NETARM_NS7520 -#define NETARM_GEN_PORTB (0x24) -#endif -#define NETARM_GEN_PORTC (0x28) - -#define NETARM_GEN_INTR_ENABLE (0x30) -#define NETARM_GEN_INTR_ENABLE_SET (0x34) -#define NETARM_GEN_INTR_ENABLE_CLR (0x38) -#define NETARM_GEN_INTR_STATUS_EN (0x34) -#define NETARM_GEN_INTR_STATUS_RAW (0x38) - -#define NETARM_GEN_CACHE_CONTROL1 (0x40) -#define NETARM_GEN_CACHE_CONTROL2 (0x44) - -/* select bitfield definitions */ - -/* System Control Register ( 0xFFB0_0000 ) */ - -#define NETARM_GEN_SYS_CFG_LENDIAN (0x80000000) -#define NETARM_GEN_SYS_CFG_BENDIAN (0x00000000) - -#define NETARM_GEN_SYS_CFG_BUSQRTR (0x00000000) -#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000) -#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000) - -#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000) - -#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000) -#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000) -#define NETARM_GEN_SYS_CFG_WDOG_FIQ (0x00400000) -#define NETARM_GEN_SYS_CFG_WDOG_RST (0x00800000) -#define NETARM_GEN_SYS_CFG_WDOG_24 (0x00000000) -#define NETARM_GEN_SYS_CFG_WDOG_26 (0x00100000) -#define NETARM_GEN_SYS_CFG_WDOG_28 (0x00200000) -#define NETARM_GEN_SYS_CFG_WDOG_29 (0x00300000) - -#define NETARM_GEN_SYS_CFG_BUSMON_EN (0x00040000) -#define NETARM_GEN_SYS_CFG_BUSMON_128 (0x00000000) -#define NETARM_GEN_SYS_CFG_BUSMON_64 (0x00010000) -#define NETARM_GEN_SYS_CFG_BUSMON_32 (0x00020000) -#define NETARM_GEN_SYS_CFG_BUSMON_16 (0x00030000) - -#define NETARM_GEN_SYS_CFG_USER_EN (0x00008000) -#define NETARM_GEN_SYS_CFG_BUSER_EN (0x00004000) - -#define NETARM_GEN_SYS_CFG_BUSARB_INT (0x00002000) -#define NETARM_GEN_SYS_CFG_BUSARB_EXT (0x00000000) - -#define NETARM_GEN_SYS_CFG_DMATST (0x00001000) - -#define NETARM_GEN_SYS_CFG_TEALAST (0x00000800) - -#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400) - -#define NETARM_GEN_SYS_CFG_CACHE_EN (0x00000200) - -#define NETARM_GEN_SYS_CFG_WRI_BUF_EN (0x00000100) - -#define NETARM_GEN_SYS_CFG_CACHE_INIT (0x00000080) - -/* PLL Control Register ( 0xFFB0_0008 ) */ - -#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000) - -#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \ - NETARM_GEN_PLL_CTL_PLLCNT_MASK) - -/* Defaults for POLTST and ICP Fields in PLL CTL */ -#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x) -#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6) -#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00) -#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C) - - -/* Software Service Register ( 0xFFB0_000C ) */ - -#define NETARM_GEN_SW_SVC_RESETA (0x123) -#define NETARM_GEN_SW_SVC_RESETB (0x321) - -/* PORT C Register ( 0xFFB0_0028 ) */ - -#ifndef CONFIG_NETARM_NS7520 -#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00)) -#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00)) -#else -#define NETARM_GEN_PORT_MODE(x) ((x)<<24) -#define NETARM_GEN_PORT_DIR(x) ((x)<<16) -#define NETARM_GEN_PORT_CSF(x) ((x)<<8) -#endif - -/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */ - -#define NETARM_GEN_TCTL_ENABLE (0x80000000) -#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000) - -#define NETARM_GEN_TCTL_USE_IRQ (0x00000000) -#define NETARM_GEN_TCTL_USE_FIQ (0x20000000) - -#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000) -#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF) - -#define NETARM_GEN_TSTAT_INTPEN (0x40000000) -#if ~defined(CONFIG_NETARM_NS7520) -#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF) -#else -#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF) -#endif - -/* prescale to msecs conversion */ - -#if !defined(CONFIG_NETARM_PLL_BYPASS) -#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \ - NETARM_GEN_TSTAT_CTC_MASK ) + \ - 1 ) ) / (NETARM_XTAL_FREQ/1000) ) - -#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \ - NETARM_GEN_TSTAT_CTC_MASK ) | \ - NETARM_GEN_TCTL_USE_PRESCALE ) - -#else -#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \ - NETARM_GEN_TSTAT_CTC_MASK ) + \ - 1 ) ) / (NETARM_XTAL_FREQ/1000) ) - -#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \ - NETARM_GEN_TSTAT_CTC_MASK ) | \ - NETARM_GEN_TCTL_USE_PRESCALE ) -#endif - -#endif diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h deleted file mode 100644 index c650c3b..0000000 --- a/include/asm-arm/arch-arm720t/netarm_mem_module.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_mem_module.h - * - * Copyright (C) 2005 - * Art Shipkowski, Videon Central, Inc., - * - * Copyright (C) 2000, 2001 NETsilicon, Inc. - * Copyright (C) 2000, 2001 Red Hat, Inc. - * - * This software is copyrighted by Red Hat. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall Red Hat - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * - * Modified to support NS7520 by Art Shipkowski. - */ - -#ifndef __NETARM_MEM_MODULE_REGISTERS_H -#define __NETARM_MEM_MODULE_REGISTERS_H - -/* GEN unit register offsets */ - -#define NETARM_MEM_MODULE_BASE (0xFFC00000) - -#define NETARM_MEM_MODULE_CONFIG (0x00) -#define NETARM_MEM_CS0_BASE_ADDR (0x10) -#define NETARM_MEM_CS0_OPTIONS (0x14) -#define NETARM_MEM_CS1_BASE_ADDR (0x20) -#define NETARM_MEM_CS1_OPTIONS (0x24) -#define NETARM_MEM_CS2_BASE_ADDR (0x30) -#define NETARM_MEM_CS2_OPTIONS (0x34) -#define NETARM_MEM_CS3_BASE_ADDR (0x40) -#define NETARM_MEM_CS3_OPTIONS (0x44) -#define NETARM_MEM_CS4_BASE_ADDR (0x50) -#define NETARM_MEM_CS4_OPTIONS (0x54) - -/* select bitfield defintions */ - -/* Module Configuration Register ( 0xFFC0_0000 ) */ - -#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000) -#define NETARM_MEM_CFG_REFRESH_EN (0x00800000) - -#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000) -#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000) -#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000) -#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000) - -#define NETARM_MEM_CFG_PORTC_AMUX (0x00100000) - -#define NETARM_MEM_CFG_A27_ADDR (0x00080000) -#define NETARM_MEM_CFG_A27_CS0OE (0x00000000) - -#define NETARM_MEM_CFG_A26_ADDR (0x00040000) -#define NETARM_MEM_CFG_A26_CS0WE (0x00000000) - -#define NETARM_MEM_CFG_A25_ADDR (0x00020000) -#define NETARM_MEM_CFG_A25_BLAST (0x00000000) - -#define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000) - - -/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ -/* the expression will round down, so make sure to reverse it to verify */ -/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */ -/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */ - -#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ - (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \ - ) - (1) ) << (24))) - -#if 0 -/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ -/* the expression will round down, so make sure to reverse it toverify */ -/* it is what you want. period = [( count + 1 ) * 4] / Fxtal */ - -#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ - (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \ - ) - (1) ) << (24))) -#endif - -/* Base Address Registers (0xFFC0_00X0) */ - -#define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000) - -/* macro to define base */ - -#define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) - -#define NETARM_MEM_BAR_DRAM_FP (0x00000000) -#define NETARM_MEM_BAR_DRAM_EDO (0x00000100) -#define NETARM_MEM_BAR_DRAM_SYNC (0x00000200) - -#define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000) -#define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080) - -#define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000) -#define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020) - -#define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010) - -#define NETARM_MEM_BAR_DRAM_SEL (0x00000008) - -#define NETARM_MEM_BAR_BURST_EN (0x00000004) - -#define NETARM_MEM_BAR_WRT_PROT (0x00000002) - -#define NETARM_MEM_BAR_VALID (0x00000001) - -/* Option Registers (0xFFC0_00X4) */ - -/* macro to define which bits of the base are significant */ - -#define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) - -#define NETARM_MEM_OPT_WAIT_MASK (0x00000F00) - -#define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK ) - -#define NETARM_MEM_OPT_BCYC_1 (0x00000000) -#define NETARM_MEM_OPT_BCYC_2 (0x00000040) -#define NETARM_MEM_OPT_BCYC_3 (0x00000080) -#define NETARM_MEM_OPT_BCYC_4 (0x000000C0) - -#define NETARM_MEM_OPT_BSIZE_2 (0x00000000) -#define NETARM_MEM_OPT_BSIZE_4 (0x00000010) -#define NETARM_MEM_OPT_BSIZE_8 (0x00000020) -#define NETARM_MEM_OPT_BSIZE_16 (0x00000030) - -#define NETARM_MEM_OPT_32BIT (0x00000000) -#define NETARM_MEM_OPT_16BIT (0x00000004) -#define NETARM_MEM_OPT_8BIT (0x00000008) -#define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C) - -#define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C) - -#define NETARM_MEM_OPT_READ_ASYNC (0x00000000) -#define NETARM_MEM_OPT_READ_SYNC (0x00000002) - -#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000) -#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001) - -#ifdef CONFIG_NETARM_NS7520 -/* The NS7520 has a second options register for each chip select */ -#define NETARM_MEM_CS0_OPTIONS_B (0x18) -#define NETARM_MEM_CS1_OPTIONS_B (0x28) -#define NETARM_MEM_CS2_OPTIONS_B (0x38) -#define NETARM_MEM_CS3_OPTIONS_B (0x48) -#define NETARM_MEM_CS4_OPTIONS_B (0x58) - -/* Option B Registers (0xFFC0_00x8) */ -#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001) -#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002) -#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) -#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) -#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) - -#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) -#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) -#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) -#endif - -#endif diff --git a/include/asm-arm/arch-arm720t/netarm_registers.h b/include/asm-arm/arch-arm720t/netarm_registers.h deleted file mode 100644 index fa88128..0000000 --- a/include/asm-arm/arch-arm720t/netarm_registers.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * linux/include/asm-arm/arch-netarm/netarm_registers.h - * - * Copyright (C) 2005 - * Art Shipkowski, Videon Central, Inc., - * - * Copyright (C) 2000, 2001 NETsilicon, Inc. - * Copyright (C) 2000, 2001 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * - * Modified to support NS7520 by Art Shipkowski. - */ - -#ifndef __NET_ARM_REGISTERS_H -#define __NET_ARM_REGISTERS_H - -#include - -/* fundamental constants : */ -/* the input crystal/clock frequency ( in Hz ) */ -#define NETARM_XTAL_FREQ_25MHz (18432000) -#define NETARM_XTAL_FREQ_33MHz (23698000) -#define NETARM_XTAL_FREQ_48MHz (48000000) -#define NETARM_XTAL_FREQ_55MHz (55000000) -#define NETARM_XTAL_FREQ_EMLIN1 (20000000) - -/* the frequency of SYS_CLK */ -#if defined(CONFIG_NETARM_EMLIN) - -/* EMLIN board: 33 MHz (exp.) */ -#define NETARM_PLL_COUNT_VAL 6 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#elif defined(CONFIG_NETARM_NET40_REV2) - -/* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */ -#define NETARM_PLL_COUNT_VAL 6 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#elif defined(CONFIG_NETARM_NET40_REV4) - -/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with - NETARM_XTAL_FREQ_25MHz) 4 */ -#define NETARM_PLL_COUNT_VAL 4 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#elif defined(CONFIG_NETARM_NET50) - -/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */ -#define NETARM_PLL_COUNT_VAL 8 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#else /* CONFIG_NETARM_NS7520 */ - -#define NETARM_PLL_COUNT_VAL 0 - -#if defined(CONFIG_BOARD_UNC20) -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz -#else -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz -#endif - -#endif - -/* #include "arm_registers.h" */ -#include -#include -#include -#include -#include -#include - -#endif diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/include/asm-arm/arch-arm720t/netarm_ser_module.h deleted file mode 100644 index 6fbae11..0000000 --- a/include/asm-arm/arch-arm720t/netarm_ser_module.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * linux/include/asm-arm/arch-netarm/netarm_ser_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 Red Hat, Inc. - * - * This software is copyrighted by Red Hat. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall Red Hat - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * Clark Williams - */ - -#ifndef __NETARM_SER_MODULE_REGISTERS_H -#define __NETARM_SER_MODULE_REGISTERS_H - -#ifndef __ASSEMBLER__ - -/* (--sub)#include "types.h" */ - -/* serial channel control structure */ -typedef struct { - u32 ctrl_a; - u32 ctrl_b; - u32 status_a; - u32 bitrate; - u32 fifo; - u32 rx_buf_timer; - u32 rx_char_timer; - u32 rx_match; - u32 rx_match_mask; - u32 ctrl_c; - u32 status_b; - u32 status_c; - u32 fifo_last; - u32 unused[3]; -} netarm_serial_channel_t; - -#endif - -/* SER unit register offsets */ - -/* #ifdef CONFIG_ARCH_NETARM */ -#define NETARM_SER_MODULE_BASE (0xFFD00000) -/* #else */ -/* extern serial_channel_t netarm_dummy_registers[]; */ -/* #define NETARM_SER_MODULE_BASE (netarm_dummy_registers) */ -/* #ifndef NETARM_XTAL_FREQ */ -/* #define NETARM_XTAL_FREQ 18432000 */ -/* #endif */ -/* #endif */ - -/* calculate the sysclk value from the pll setting */ -#define NETARM_PLLED_SYSCLK_FREQ (( NETARM_XTAL_FREQ / 5 ) * \ - ( NETARM_PLL_COUNT_VAL + 3 )) - -#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c])) - -#define NETARM_SER_CH1_CTRL_A (0x00) -#define NETARM_SER_CH1_CTRL_B (0x04) -#define NETARM_SER_CH1_STATUS_A (0x08) -#define NETARM_SER_CH1_BITRATE (0x0C) -#define NETARM_SER_CH1_FIFO (0x10) -#define NETARM_SER_CH1_RX_BUF_TMR (0x14) -#define NETARM_SER_CH1_RX_CHAR_TMR (0x18) -#define NETARM_SER_CH1_RX_MATCH (0x1c) -#define NETARM_SER_CH1_RX_MATCH_MASK (0x20) -#define NETARM_SER_CH1_CTRL_C (0x24) -#define NETARM_SER_CH1_STATUS_B (0x28) -#define NETARM_SER_CH1_STATUS_C (0x2c) -#define NETARM_SER_CH1_FIFO_LAST (0x30) - -#define NETARM_SER_CH2_CTRL_A (0x40) -#define NETARM_SER_CH2_CTRL_B (0x44) -#define NETARM_SER_CH2_STATUS_A (0x48) -#define NETARM_SER_CH2_BITRATE (0x4C) -#define NETARM_SER_CH2_FIFO (0x50) -#define NETARM_SER_CH2_RX_BUF_TMR (0x54) -#define NETARM_SER_CH2_RX_CHAR_TMR (0x58) -#define NETARM_SER_CH2_RX_MATCH (0x5c) -#define NETARM_SER_CH2_RX_MATCH_MASK (0x60) -#define NETARM_SER_CH2_CTRL_C (0x64) -#define NETARM_SER_CH2_STATUS_B (0x68) -#define NETARM_SER_CH2_STATUS_C (0x6c) -#define NETARM_SER_CH2_FIFO_LAST (0x70) - -/* select bitfield defintions */ - -/* Control Register A */ - -#define NETARM_SER_CTLA_ENABLE (0x80000000) -#define NETARM_SER_CTLA_BRK (0x40000000) - -#define NETARM_SER_CTLA_STICKP (0x20000000) - -#define NETARM_SER_CTLA_P_EVEN (0x18000000) -#define NETARM_SER_CTLA_P_ODD (0x08000000) -#define NETARM_SER_CTLA_P_NONE (0x00000000) - -/* if you read the errata, you will find that the STOP bits don't work right */ -#define NETARM_SER_CTLA_2STOP (0x00000000) -#define NETARM_SER_CTLA_3STOP (0x04000000) - -#define NETARM_SER_CTLA_5BITS (0x00000000) -#define NETARM_SER_CTLA_6BITS (0x01000000) -#define NETARM_SER_CTLA_7BITS (0x02000000) -#define NETARM_SER_CTLA_8BITS (0x03000000) - -#define NETARM_SER_CTLA_CTSTX (0x00800000) -#define NETARM_SER_CTLA_RTSRX (0x00400000) - -#define NETARM_SER_CTLA_LOOP_REM (0x00200000) -#define NETARM_SER_CTLA_LOOP_LOC (0x00100000) - -#define NETARM_SER_CTLA_GPIO2 (0x00080000) -#define NETARM_SER_CTLA_GPIO1 (0x00040000) - -#define NETARM_SER_CTLA_DTR_EN (0x00020000) -#define NETARM_SER_CTLA_RTS_EN (0x00010000) - -#define NETARM_SER_CTLA_IE_RX_BRK (0x00008000) -#define NETARM_SER_CTLA_IE_RX_FRMERR (0x00004000) -#define NETARM_SER_CTLA_IE_RX_PARERR (0x00002000) -#define NETARM_SER_CTLA_IE_RX_OVERRUN (0x00001000) -#define NETARM_SER_CTLA_IE_RX_RDY (0x00000800) -#define NETARM_SER_CTLA_IE_RX_HALF (0x00000400) -#define NETARM_SER_CTLA_IE_RX_FULL (0x00000200) -#define NETARM_SER_CTLA_IE_RX_DMAEN (0x00000100) -#define NETARM_SER_CTLA_IE_RX_DCD (0x00000080) -#define NETARM_SER_CTLA_IE_RX_RI (0x00000040) -#define NETARM_SER_CTLA_IE_RX_DSR (0x00000020) - -#define NETARM_SER_CTLA_IE_RX_ALL (NETARM_SER_CTLA_IE_RX_BRK \ - |NETARM_SER_CTLA_IE_RX_FRMERR \ - |NETARM_SER_CTLA_IE_RX_PARERR \ - |NETARM_SER_CTLA_IE_RX_OVERRUN \ - |NETARM_SER_CTLA_IE_RX_RDY \ - |NETARM_SER_CTLA_IE_RX_HALF \ - |NETARM_SER_CTLA_IE_RX_FULL \ - |NETARM_SER_CTLA_IE_RX_DMAEN \ - |NETARM_SER_CTLA_IE_RX_DCD \ - |NETARM_SER_CTLA_IE_RX_RI \ - |NETARM_SER_CTLA_IE_RX_DSR) - -#define NETARM_SER_CTLA_IE_TX_CTS (0x00000010) -#define NETARM_SER_CTLA_IE_TX_EMPTY (0x00000008) -#define NETARM_SER_CTLA_IE_TX_HALF (0x00000004) -#define NETARM_SER_CTLA_IE_TX_FULL (0x00000002) -#define NETARM_SER_CTLA_IE_TX_DMAEN (0x00000001) - -#define NETARM_SER_CTLA_IE_TX_ALL (NETARM_SER_CTLA_IE_TX_CTS \ - |NETARM_SER_CTLA_IE_TX_EMPTY \ - |NETARM_SER_CTLA_IE_TX_HALF \ - |NETARM_SER_CTLA_IE_TX_FULL \ - |NETARM_SER_CTLA_IE_TX_DMAEN) - -/* Control Register B */ - -#define NETARM_SER_CTLB_MATCH1_EN (0x80000000) -#define NETARM_SER_CTLB_MATCH2_EN (0x40000000) -#define NETARM_SER_CTLB_MATCH3_EN (0x20000000) -#define NETARM_SER_CTLB_MATCH4_EN (0x10000000) - -#define NETARM_SER_CTLB_RBGT_EN (0x08000000) -#define NETARM_SER_CTLB_RCGT_EN (0x04000000) - -#define NETARM_SER_CTLB_UART_MODE (0x00000000) -#define NETARM_SER_CTLB_HDLC_MODE (0x00100000) -#define NETARM_SER_CTLB_SPI_MAS_MODE (0x00200000) -#define NETARM_SER_CTLB_SPI_SLV_MODE (0x00300000) - -#define NETARM_SER_CTLB_REV_BIT_ORDER (0x00080000) - -#define NETARM_SER_CTLB_MAM1 (0x00040000) -#define NETARM_SER_CTLB_MAM2 (0x00020000) - -/* Status Register A */ - -#define NETARM_SER_STATA_MATCH1 (0x80000000) -#define NETARM_SER_STATA_MATCH2 (0x40000000) -#define NETARM_SER_STATA_MATCH3 (0x20000000) -#define NETARM_SER_STATA_MATCH4 (0x10000000) - -#define NETARM_SER_STATA_BGAP (0x80000000) -#define NETARM_SER_STATA_CGAP (0x40000000) - -#define NETARM_SER_STATA_RX_1B (0x00100000) -#define NETARM_SER_STATA_RX_2B (0x00200000) -#define NETARM_SER_STATA_RX_3B (0x00300000) -#define NETARM_SER_STATA_RX_4B (0x00000000) - -/* downshifted values */ - -#define NETARM_SER_STATA_RXFDB_1BYTES (0x001) -#define NETARM_SER_STATA_RXFDB_2BYTES (0x002) -#define NETARM_SER_STATA_RXFDB_3BYTES (0x003) -#define NETARM_SER_STATA_RXFDB_4BYTES (0x000) - -#define NETARM_SER_STATA_RXFDB_MASK (0x00300000) -#define NETARM_SER_STATA_RXFDB(x) (((x) & NETARM_SER_STATA_RXFDB_MASK) \ - >> 20) - -#define NETARM_SER_STATA_DCD (0x00080000) -#define NETARM_SER_STATA_RI (0x00040000) -#define NETARM_SER_STATA_DSR (0x00020000) -#define NETARM_SER_STATA_CTS (0x00010000) - -#define NETARM_SER_STATA_RX_BRK (0x00008000) -#define NETARM_SER_STATA_RX_FRMERR (0x00004000) -#define NETARM_SER_STATA_RX_PARERR (0x00002000) -#define NETARM_SER_STATA_RX_OVERRUN (0x00001000) -#define NETARM_SER_STATA_RX_RDY (0x00000800) -#define NETARM_SER_STATA_RX_HALF (0x00000400) -#define NETARM_SER_STATA_RX_CLOSED (0x00000200) -#define NETARM_SER_STATA_RX_FULL (0x00000100) -#define NETARM_SER_STATA_RX_DCD (0x00000080) -#define NETARM_SER_STATA_RX_RI (0x00000040) -#define NETARM_SER_STATA_RX_DSR (0x00000020) - -#define NETARM_SER_STATA_TX_CTS (0x00000010) -#define NETARM_SER_STATA_TX_RDY (0x00000008) -#define NETARM_SER_STATA_TX_HALF (0x00000004) -#define NETARM_SER_STATA_TX_FULL (0x00000002) -#define NETARM_SER_STATA_TX_DMAEN (0x00000001) - -/* you have to clear all receive signals to get the fifo to move forward */ -#define NETARM_SER_STATA_CLR_ALL (NETARM_SER_STATA_RX_BRK | \ - NETARM_SER_STATA_RX_FRMERR | \ - NETARM_SER_STATA_RX_PARERR | \ - NETARM_SER_STATA_RX_OVERRUN | \ - NETARM_SER_STATA_RX_HALF | \ - NETARM_SER_STATA_RX_CLOSED | \ - NETARM_SER_STATA_RX_FULL | \ - NETARM_SER_STATA_RX_DCD | \ - NETARM_SER_STATA_RX_RI | \ - NETARM_SER_STATA_RX_DSR | \ - NETARM_SER_STATA_TX_CTS ) - -/* Bit Rate Registers */ - -#define NETARM_SER_BR_EN (0x80000000) -#define NETARM_SER_BR_TMODE (0x40000000) - -#define NETARM_SER_BR_RX_CLK_INT (0x00000000) -#define NETARM_SER_BR_RX_CLK_EXT (0x20000000) -#define NETARM_SER_BR_TX_CLK_INT (0x00000000) -#define NETARM_SER_BR_TX_CLK_EXT (0x10000000) - -#define NETARM_SER_BR_RX_CLK_DRV (0x08000000) -#define NETARM_SER_BR_TX_CLK_DRV (0x04000000) - -#define NETARM_SER_BR_CLK_EXT_5 (0x00000000) -#define NETARM_SER_BR_CLK_SYSTEM (0x01000000) -#define NETARM_SER_BR_CLK_OUT1A (0x02000000) -#define NETARM_SER_BR_CLK_OUT2A (0x03000000) - -#define NETARM_SER_BR_TX_CLK_INV (0x00800000) -#define NETARM_SER_BR_RX_CLK_INV (0x00400000) - -/* complete settings assuming system clock input is 18MHz */ - -#define NETARM_SER_BR_MASK (0x000007FF) - -/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */ -/* from section 7.5.4 of HW Ref Guide */ - -/* #ifdef CONFIG_NETARM_PLL_BYPASS */ -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_EXT_5 | \ - ( ( ( ( NETARM_XTAL_FREQ / \ - ( x * 10 ) ) - 1 ) / 16 ) & \ - NETARM_SER_BR_MASK ) ) -/* -#else -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_SYSTEM | \ - ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ - ( x * 2 ) ) - 1 ) / 16 ) & \ - NETARM_SER_BR_MASK ) ) -#endif -*/ - -/* Receive Buffer Gap Timer */ - -#define NETARM_SER_RX_GAP_TIMER_EN (0x80000000) -#define NETARM_SER_RX_GAP_MASK (0x00003FFF) - -/* rx gap is a function of bit rate x */ - -/* #ifdef CONFIG_NETARM_PLL_BYPASS */ -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -/* -#else -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -#endif -*/ - -#if 0 -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -#endif - -#define MIN_BAUD_RATE 600 -#define MAX_BAUD_RATE 115200 - -/* the default BAUD rate for the BOOTLOADER, there is a separate */ -/* setting in the serial driver */ -#define DEFAULT_BAUD_RATE 9600 -#define NETARM_SER_FIFO_SIZE 32 -#define MIN_GAP 0 - -#endif diff --git a/include/asm-arm/arch-arm925t/sizes.h b/include/asm-arm/arch-arm925t/sizes.h deleted file mode 100644 index 7319bd9..0000000 --- a/include/asm-arm/arch-arm925t/sizes.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/include/asm-arm/arch-arm926ejs/sizes.h b/include/asm-arm/arch-arm926ejs/sizes.h deleted file mode 100644 index ef0b99b..0000000 --- a/include/asm-arm/arch-arm926ejs/sizes.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307 - * USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/include/asm-arm/arch-at91/at91_common.h b/include/asm-arm/arch-at91/at91_common.h deleted file mode 100644 index 01840ee..0000000 --- a/include/asm-arm/arch-at91/at91_common.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef AT91_COMMON_H -#define AT91_COMMON_H - -void at91_can_hw_init(void); -void at91_macb_hw_init(void); -void at91_serial_hw_init(void); -void at91_serial0_hw_init(void); -void at91_serial1_hw_init(void); -void at91_serial2_hw_init(void); -void at91_serial3_hw_init(void); -void at91_spi0_hw_init(unsigned long cs_mask); -void at91_spi1_hw_init(unsigned long cs_mask); -void at91_uhp_hw_init(void); - -#endif /* AT91_COMMON_H */ diff --git a/include/asm-arm/arch-at91/at91_emac.h b/include/asm-arm/arch-at91/at91_emac.h deleted file mode 100644 index 45ae333..0000000 --- a/include/asm-arm/arch-at91/at91_emac.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC)) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef AT91_H -#define AT91_H - -typedef struct at91_emac { - u32 ctl; - u32 cfg; - u32 sr; - u32 tar; - u32 tcr; - u32 tsr; - u32 rbqp; - u32 reserved0; - u32 rsr; - u32 isr; - u32 ier; - u32 idr; - u32 imr; - u32 man; - u32 reserved1[2]; - u32 fra; - u32 scol; - u32 mocl; - u32 ok; - u32 seqe; - u32 ale; - u32 dte; - u32 lcol; - u32 ecol; - u32 cse; - u32 tue; - u32 cde; - u32 elr; - u32 rjb; - u32 usf; - u32 sqee; - u32 drfc; - u32 reserved2[3]; - u32 hsh; - u32 hsl; - u32 sh1l; - u32 sa1h; - u32 sa2l; - u32 sa2h; - u32 sa3l; - u32 sa3h; - u32 sa4l; - u32 sa4h; -} at91_emac_t; - -#define AT91_EMAC_CTL_LB 0x0001 -#define AT91_EMAC_CTL_LBL 0x0002 -#define AT91_EMAC_CTL_RE 0x0004 -#define AT91_EMAC_CTL_TE 0x0008 -#define AT91_EMAC_CTL_MPE 0x0010 -#define AT91_EMAC_CTL_CSR 0x0020 -#define AT91_EMAC_CTL_ISR 0x0040 -#define AT91_EMAC_CTL_WES 0x0080 -#define AT91_EMAC_CTL_BP 0x1000 - -#define AT91_EMAC_CFG_SPD 0x0001 -#define AT91_EMAC_CFG_FD 0x0002 -#define AT91_EMAC_CFG_BR 0x0004 -#define AT91_EMAC_CFG_CAF 0x0010 -#define AT91_EMAC_CFG_NBC 0x0020 -#define AT91_EMAC_CFG_MTI 0x0040 -#define AT91_EMAC_CFG_UNI 0x0080 -#define AT91_EMAC_CFG_BIG 0x0100 -#define AT91_EMAC_CFG_EAE 0x0200 -#define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF -#define AT91_EMAC_CFG_MCLK_8 0x0000 -#define AT91_EMAC_CFG_MCLK_16 0x0400 -#define AT91_EMAC_CFG_MCLK_32 0x0800 -#define AT91_EMAC_CFG_MCLK_64 0x0C00 -#define AT91_EMAC_CFG_RTY 0x1000 -#define AT91_EMAC_CFG_RMII 0x2000 - -#define AT91_EMAC_SR_LINK 0x0001 -#define AT91_EMAC_SR_MDIO 0x0002 -#define AT91_EMAC_SR_IDLE 0x0004 - -#define AT91_EMAC_TCR_LEN(x) (x & 0x7FF) -#define AT91_EMAC_TCR_NCRC 0x8000 - -#define AT91_EMAC_TSR_OVR 0x0001 -#define AT91_EMAC_TSR_COL 0x0002 -#define AT91_EMAC_TSR_RLE 0x0004 -#define AT91_EMAC_TSR_TXIDLE 0x0008 -#define AT91_EMAC_TSR_BNQ 0x0010 -#define AT91_EMAC_TSR_COMP 0x0020 -#define AT91_EMAC_TSR_UND 0x0040 - -#define AT91_EMAC_RSR_BNA 0x0001 -#define AT91_EMAC_RSR_REC 0x0002 -#define AT91_EMAC_RSR_OVR 0x0004 - -/* ISR, IER, IDR, IMR use the same bits */ -#define AT91_EMAC_IxR_DONE 0x0001 -#define AT91_EMAC_IxR_RCOM 0x0002 -#define AT91_EMAC_IxR_RBNA 0x0004 -#define AT91_EMAC_IxR_TOVR 0x0008 -#define AT91_EMAC_IxR_TUND 0x0010 -#define AT91_EMAC_IxR_RTRY 0x0020 -#define AT91_EMAC_IxR_TBRE 0x0040 -#define AT91_EMAC_IxR_TCOM 0x0080 -#define AT91_EMAC_IxR_TIDLE 0x0100 -#define AT91_EMAC_IxR_LINK 0x0200 -#define AT91_EMAC_IxR_ROVR 0x0400 -#define AT91_EMAC_IxR_HRESP 0x0800 - -#define AT91_EMAC_MAN_DATA_MASK 0xFFFF -#define AT91_EMAC_MAN_CODE_802_3 0x00020000 -#define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18) -#define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23) -#define AT91_EMAC_MAN_RW_R 0x20000000 -#define AT91_EMAC_MAN_RW_W 0x10000000 -#define AT91_EMAC_MAN_HIGH 0x40000000 -#define AT91_EMAC_MAN_LOW 0x80000000 - -#endif diff --git a/include/asm-arm/arch-at91/at91_matrix.h b/include/asm-arm/arch-at91/at91_matrix.h deleted file mode 100644 index 981ec20..0000000 --- a/include/asm-arm/arch-at91/at91_matrix.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef AT91_MATRIX_H -#define AT91_MATRIX_H - -#ifdef __ASSEMBLY__ - -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x11C) -#elif defined(CONFIG_AT91SAM9261) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x30) -#elif defined(CONFIG_AT91SAM9263) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x120) -#elif defined(CONFIG_AT91SAM9G45) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x128) -#else -#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU -#endif - -#define AT91_ASM_MATRIX_MCFG AT91_MATRIX_BASE - -#else -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#define AT91_MATRIX_MASTERS 6 -#define AT91_MATRIX_SLAVES 5 -#elif defined(CONFIG_AT91SAM9261) -#define AT91_MATRIX_MASTERS 1 -#define AT91_MATRIX_SLAVES 5 -#elif defined(CONFIG_AT91SAM9263) -#define AT91_MATRIX_MASTERS 9 -#define AT91_MATRIX_SLAVES 7 -#elif defined(CONFIG_AT91SAM9G45) -#define AT91_MATRIX_MASTERS 11 -#define AT91_MATRIX_SLAVES 8 -#else -#error CPU not supported. Please update at91_matrix.h -#endif - -typedef struct at91_priority { - u32 a; - u32 b; -} at91_priority_t; - -typedef struct at91_matrix { - u32 mcfg[AT91_MATRIX_MASTERS]; -#if defined(CONFIG_AT91SAM9261) - u32 scfg[AT91_MATRIX_SLAVES]; - u32 res61_1[3]; - u32 tcr; - u32 res61_2[2]; - u32 csa; - u32 pucr; - u32 res61_3[114]; -#else - u32 reserve1[16 - AT91_MATRIX_MASTERS]; - u32 scfg[AT91_MATRIX_SLAVES]; - u32 reserve2[16 - AT91_MATRIX_SLAVES]; - at91_priority_t pr[AT91_MATRIX_SLAVES]; - u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)]; - u32 mrcr; /* 0x100 Master Remap Control */ - u32 reserve4[3]; -#if defined(CONFIG_AT91SAM9G45) - u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ - u32 womr; /* 0x1E4 Write Protect Mode */ - u32 wpsr; /* 0x1E8 Write Protect Status */ - u32 resg45_1[10]; -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) - u32 res60_1[3]; - u32 csa; - u32 res60_2[56]; -#elif defined(CONFIG_AT91SAM9263) - u32 res63_1; - u32 tcmr; - u32 res63_2[2]; - u32 csa[2]; - u32 res63_3[54]; -#else - u32 reserve5[60]; -#endif -#endif -} at91_matrix_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_MATRIX_CSA_DBPUC 0x00000100 -#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000 -#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000 - -#define AT91_MATRIX_CSA_EBI_CS1A 0x00000002 -#define AT91_MATRIX_CSA_EBI_CS3A 0x00000008 -#define AT91_MATRIX_CSA_EBI_CS4A 0x00000010 -#define AT91_MATRIX_CSA_EBI_CS5A 0x00000020 - -#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 - -#endif diff --git a/include/asm-arm/arch-at91/at91_mc.h b/include/asm-arm/arch-at91/at91_mc.h deleted file mode 100644 index acfbd10..0000000 --- a/include/asm-arm/arch-at91/at91_mc.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef AT91_MC_H -#define AT91_MC_H - -#define AT91_ASM_MC_EBI_CSA (AT91_MC_BASE + 0x60) -#define AT91_ASM_MC_EBI_CFG (AT91_MC_BASE + 0x64) -#define AT91_ASM_MC_SMC_CSR0 (AT91_MC_BASE + 0x70) -#define AT91_ASM_MC_SDRAMC_MR (AT91_MC_BASE + 0x90) -#define AT91_ASM_MC_SDRAMC_TR (AT91_MC_BASE + 0x94) -#define AT91_ASM_MC_SDRAMC_CR (AT91_MC_BASE + 0x98) - -#ifndef __ASSEMBLY__ - -typedef struct at91_ebi { - u32 csa; /* 0x00 Chip Select Assignment Register */ - u32 cfgr; /* 0x04 Configuration Register */ - u32 reserved[2]; -} __attribute__ ((packed)) at91_ebi_t; - -#define AT91_EBI_CSA_CS0A 0x0001 -#define AT91_EBI_CSA_CS1A 0x0002 - -#define AT91_EBI_CSA_CS3A 0x0008 -#define AT91_EBI_CSA_CS4A 0x0010 - -typedef struct at91_sdramc { - u32 mr; /* 0x00 SDRAMC Mode Register */ - u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ - u32 cr; /* 0x08 SDRAMC Configuration Register */ - u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ - u32 lpr; /* 0x10 SDRAMC Low Power Register */ - u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ - u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ - u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ - u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ - u32 reserved[3]; -} __attribute__ ((packed)) at91_sdramc_t; - -typedef struct at91_smc { - u32 csr[8]; /* 0x00 SDRAMC Mode Register */ -} __attribute__ ((packed)) at91_smc_t; - -#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) -#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24) -#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000 -#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000 -#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000 -#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000 -#define AT91_SMC_CSR_DRP 0x00008000 -#define AT91_SMC_CSR_DBW_8 0x00004000 -#define AT91_SMC_CSR_DBW_16 0x00002000 -#define AT91_SMC_CSR_BAT_8 0x00000000 -#define AT91_SMC_CSR_BAT_16 0x00001000 -#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8) -#define AT91_SMC_CSR_WSEN 0x00000080 -#define AT91_SMC_CSR_NWS(x) (x & 0x7F) - -typedef struct at91_bfc { - u32 mr; /* 0x00 SDRAMC Mode Register */ -} __attribute__ ((packed)) at91_bfc_t; - -typedef struct at91_mc { - u32 rcr; /* 0x00 MC Remap Control Register */ - u32 asr; /* 0x04 MC Abort Status Register */ - u32 aasr; /* 0x08 MC Abort Address Status Reg */ - u32 mpr; /* 0x0C MC Master Priority Register */ - u32 reserved1[20]; /* 0x10-0x5C */ - at91_ebi_t ebi; /* 0x60 - 0x6C EBI */ - at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */ - at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */ - at91_bfc_t bfc; /* 0xC0 BFC User Interface */ - u32 reserved2[15]; -} __attribute__ ((packed)) at91_mc_t; - -#endif -#endif diff --git a/include/asm-arm/arch-at91/at91_pdc.h b/include/asm-arm/arch-at91/at91_pdc.h deleted file mode 100644 index 42f87ca..0000000 --- a/include/asm-arm/arch-at91/at91_pdc.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef AT91_PDC_H -#define AT91_PDC_H - -typedef struct at91_pdc { - u32 rpr; /* 0x100 Receive Pointer Register */ - u32 rcr; /* 0x104 Receive Counter Register */ - u32 tpr; /* 0x108 Transmit Pointer Register */ - u32 tcr; /* 0x10C Transmit Counter Register */ - u32 pnpr; /* 0x110 Receive Next Pointer Register */ - u32 pncr; /* 0x114 Receive Next Counter Register */ - u32 tnpr; /* 0x118 Transmit Next Pointer Register */ - u32 tncr; /* 0x11C Transmit Next Counter Register */ - u32 ptcr; /* 0x120 Transfer Control Register */ - u32 ptsr; /* 0x124 Transfer Status Register */ -} at91_pdc_t; - -#endif diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h deleted file mode 100644 index f7915a3..0000000 --- a/include/asm-arm/arch-at91/at91_pio.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * Parallel I/O Controller (PIO) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PIO_H -#define AT91_PIO_H - - -#define AT91_ASM_PIO_RANGE 0x200 -#define AT91_ASM_PIOC_ASR \ - (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) -#define AT91_ASM_PIOC_BSR \ - (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74) -#define AT91_ASM_PIOC_PDR \ - (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04) -#define AT91_ASM_PIOC_PUDR \ - (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60) - -#define AT91_ASM_PIOD_PDR \ - (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04) -#define AT91_ASM_PIOD_PUDR \ - (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60) -#define AT91_ASM_PIOD_ASR \ - (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) - -#ifndef __ASSEMBLY__ - -typedef struct at91_port { - u32 per; /* 0x00 PIO Enable Register */ - u32 pdr; /* 0x04 PIO Disable Register */ - u32 psr; /* 0x08 PIO Status Register */ - u32 reserved0; - u32 oer; /* 0x10 Output Enable Register */ - u32 odr; /* 0x14 Output Disable Registerr */ - u32 osr; /* 0x18 Output Status Register */ - u32 reserved1; - u32 ifer; /* 0x20 Input Filter Enable Register */ - u32 ifdr; /* 0x24 Input Filter Disable Register */ - u32 ifsr; /* 0x28 Input Filter Status Register */ - u32 reserved2; - u32 sodr; /* 0x30 Set Output Data Register */ - u32 codr; /* 0x34 Clear Output Data Register */ - u32 odsr; /* 0x38 Output Data Status Register */ - u32 pdsr; /* 0x3C Pin Data Status Register */ - u32 ier; /* 0x40 Interrupt Enable Register */ - u32 idr; /* 0x44 Interrupt Disable Register */ - u32 imr; /* 0x48 Interrupt Mask Register */ - u32 isr; /* 0x4C Interrupt Status Register */ - u32 mder; /* 0x50 Multi-driver Enable Register */ - u32 mddr; /* 0x54 Multi-driver Disable Register */ - u32 mdsr; /* 0x58 Multi-driver Status Register */ - u32 reserved3; - u32 pudr; /* 0x60 Pull-up Disable Register */ - u32 puer; /* 0x64 Pull-up Enable Register */ - u32 pusr; /* 0x68 Pad Pull-up Status Register */ - u32 reserved4; - u32 asr; /* 0x70 Select A Register */ - u32 bsr; /* 0x74 Select B Register */ - u32 absr; /* 0x78 AB Select Status Register */ - u32 reserved5[9]; /* */ - u32 ower; /* 0xA0 Output Write Enable Register */ - u32 owdr; /* 0xA4 Output Write Disable Register */ - u32 owsr; /* OxA8 utput Write Status Register */ - u32 reserved6[85]; -} at91_port_t; - -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ - defined(CONFIG_AT91SAM9G10) || defined(CONFIG_AT91SAM9G20) -#define AT91_PIO_PORTS 3 -#elif defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \ - defined(CONFIG_AT91SAM9M10G45) -#define AT91_PIO_PORTS 5 -#elif defined(CONFIG_AT91RM9200) || defined(CONFIG_AT91CAP9) || \ - defined(CONFIG_AT91SAM9RL) -#define AT91_PIO_PORTS 4 -#else -#error "Unsupported cpu. Please update at91_pio.h" -#endif - -typedef union at91_pio { - struct { - at91_port_t pioa; - at91_port_t piob; - at91_port_t pioc; - #if (AT91_PIO_PORTS > 3) - at91_port_t piod; - #endif - #if (AT91_PIO_PORTS > 4) - at91_port_t pioe; - #endif - } ; - at91_port_t port[AT91_PIO_PORTS]; -} at91_pio_t; - -#ifdef CONFIG_AT91_GPIO -int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); -int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); -int at91_set_pio_output(unsigned port, unsigned pin, int value); -int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); -int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on); -int at91_set_pio_value(unsigned port, unsigned pin, int value); -int at91_get_pio_value(unsigned port, unsigned pin); -#endif -#endif - -#define AT91_PIO_PORTA 0x0 -#define AT91_PIO_PORTB 0x1 -#define AT91_PIO_PORTC 0x2 -#define AT91_PIO_PORTD 0x3 -#define AT91_PIO_PORTE 0x4 - -#ifdef CONFIG_AT91_LEGACY - -#define PIO_PER 0x00 /* Enable Register */ -#define PIO_PDR 0x04 /* Disable Register */ -#define PIO_PSR 0x08 /* Status Register */ -#define PIO_OER 0x10 /* Output Enable Register */ -#define PIO_ODR 0x14 /* Output Disable Register */ -#define PIO_OSR 0x18 /* Output Status Register */ -#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ -#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ -#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ -#define PIO_SODR 0x30 /* Set Output Data Register */ -#define PIO_CODR 0x34 /* Clear Output Data Register */ -#define PIO_ODSR 0x38 /* Output Data Status Register */ -#define PIO_PDSR 0x3c /* Pin Data Status Register */ -#define PIO_IER 0x40 /* Interrupt Enable Register */ -#define PIO_IDR 0x44 /* Interrupt Disable Register */ -#define PIO_IMR 0x48 /* Interrupt Mask Register */ -#define PIO_ISR 0x4c /* Interrupt Status Register */ -#define PIO_MDER 0x50 /* Multi-driver Enable Register */ -#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ -#define PIO_MDSR 0x58 /* Multi-driver Status Register */ -#define PIO_PUDR 0x60 /* Pull-up Disable Register */ -#define PIO_PUER 0x64 /* Pull-up Enable Register */ -#define PIO_PUSR 0x68 /* Pull-up Status Register */ -#define PIO_ASR 0x70 /* Peripheral A Select Register */ -#define PIO_BSR 0x74 /* Peripheral B Select Register */ -#define PIO_ABSR 0x78 /* AB Status Register */ -#define PIO_OWER 0xa0 /* Output Write Enable Register */ -#define PIO_OWDR 0xa4 /* Output Write Disable Register */ -#define PIO_OWSR 0xa8 /* Output Write Status Register */ -#endif - -#endif diff --git a/include/asm-arm/arch-at91/at91_pit.h b/include/asm-arm/arch-at91/at91_pit.h deleted file mode 100644 index 5615a02..0000000 --- a/include/asm-arm/arch-at91/at91_pit.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Periodic Interval Timer (PIT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PIT_H -#define AT91_PIT_H - -typedef struct at91_pit { - u32 mr; /* 0x00 Mode Register */ - u32 sr; /* 0x04 Status Register */ - u32 pivr; /* 0x08 Periodic Interval Value Register */ - u32 piir; /* 0x0C Periodic Interval Image Register */ -} at91_pit_t; - -#define AT91_PIT_MR_IEN 0x02000000 -#define AT91_PIT_MR_EN 0x01000000 -#define AT91_PIT_MR_PIV_MASK (x & 0x000fffff) -#define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK) - -#ifdef CONFIG_AT91_LEGACY - -#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ -#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ -#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ -#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ - -#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ -#define AT91_PIT_PITS (1 << 0) /* Timer Status */ - -#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ -#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ -#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ - -#endif /* CONFIG_AT91_LEGACY */ -#endif diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h deleted file mode 100644 index 5b1a85d..0000000 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * Power Management Controller (PMC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PMC_H -#define AT91_PMC_H - -#define AT91_ASM_PMC_MOR (AT91_PMC_BASE + 0x20) -#define AT91_ASM_PMC_PLLAR (AT91_PMC_BASE + 0x28) -#define AT91_ASM_PMC_PLLBR (AT91_PMC_BASE + 0x2c) -#define AT91_ASM_PMC_MCKR (AT91_PMC_BASE + 0x30) -#define AT91_ASM_PMC_SR (AT91_PMC_BASE + 0x68) - -#ifndef __ASSEMBLY__ - -#include - -typedef struct at91_pmc { - u32 scer; /* 0x00 System Clock Enable Register */ - u32 scdr; /* 0x04 System Clock Disable Register */ - u32 scsr; /* 0x08 System Clock Status Register */ - u32 reserved0; - u32 pcer; /* 0x10 Peripheral Clock Enable Register */ - u32 pcdr; /* 0x14 Peripheral Clock Disable Register */ - u32 pcsr; /* 0x18 Peripheral Clock Status Register */ - u32 reserved1; - u32 mor; /* 0x20 Main Oscilator Register */ - u32 mcfr; /* 0x24 Main Clock Frequency Register */ - u32 pllar; /* 0x28 PLL A Register */ - u32 pllbr; /* 0x2C PLL B Register */ - u32 mckr; /* 0x30 Master Clock Register */ - u32 reserved2[3]; - u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */ - u32 reserved3[4]; - u32 ier; /* 0x60 Interrupt Enable Register */ - u32 idr; /* 0x64 Interrupt Disable Register */ - u32 sr; /* 0x68 Status Register */ - u32 imr; /* 0x6C Interrupt Mask Register */ - u32 reserved4[4]; - u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */ - u32 reserved5[21]; - u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */ - u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */ - u32 reserved8[5]; -} at91_pmc_t; - -#endif /* end not assembly */ - -#define AT91_PMC_MOR_MOSCEN 0x01 -#define AT91_PMC_MOR_OSCBYPASS 0x02 -#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) - -#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) -#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) -#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) -#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) -#define AT91_PMC_PLLAR_29 0x20000000 -#define AT91_PMC_PLLBR_USBDIV_1 0x00000000 -#define AT91_PMC_PLLBR_USBDIV_2 0x10000000 -#define AT91_PMC_PLLBR_USBDIV_4 0x20000000 - -#define AT91_PMC_MCFR_MAINRDY 0x00010000 -#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF - -#define AT91_PMC_MCKR_CSS_SLOW 0x00000000 -#define AT91_PMC_MCKR_CSS_MAIN 0x00000001 -#define AT91_PMC_MCKR_CSS_PLLA 0x00000002 -#define AT91_PMC_MCKR_CSS_PLLB 0x00000003 -#define AT91_PMC_MCKR_CSS_MASK 0x00000003 - -#define AT91_PMC_MCKR_PRES_1 0x00000000 -#define AT91_PMC_MCKR_PRES_2 0x00000004 -#define AT91_PMC_MCKR_PRES_4 0x00000008 -#define AT91_PMC_MCKR_PRES_8 0x0000000C -#define AT91_PMC_MCKR_PRES_16 0x00000010 -#define AT91_PMC_MCKR_PRES_32 0x00000014 -#define AT91_PMC_MCKR_PRES_64 0x00000018 -#define AT91_PMC_MCKR_PRES_MASK 0x0000001C - -#define AT91_PMC_MCKR_MDIV_1 0x00000000 -#define AT91_PMC_MCKR_MDIV_2 0x00000100 -#define AT91_PMC_MCKR_MDIV_4 0x00000200 -#define AT91_PMC_MCKR_MDIV_MASK 0x00000300 - -#define AT91_PMC_MCKR_PLLADIV_1 0x00001000 -#define AT91_PMC_MCKR_PLLADIV_2 0x00002000 - -#define AT91_PMC_IXR_MOSCS 0x00000001 -#define AT91_PMC_IXR_LOCKA 0x00000002 -#define AT91_PMC_IXR_LOCKB 0x00000004 -#define AT91_PMC_IXR_MCKRDY 0x00000008 -#define AT91_PMC_IXR_LOCKU 0x00000040 -#define AT91_PMC_IXR_PCKRDY0 0x00000100 -#define AT91_PMC_IXR_PCKRDY1 0x00000200 -#define AT91_PMC_IXR_PCKRDY2 0x00000400 -#define AT91_PMC_IXR_PCKRDY3 0x00000800 - -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ -#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ - -#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ -#endif - -#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ -#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ -#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ -#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ -#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ -#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ -#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ -#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ - -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ - -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ -#endif - -#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ -#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ -#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ - -#ifdef CONFIG_AT91_LEGACY -#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ -#endif -#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ -#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ -#endif -#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ -#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ -#endif -#define AT91_PMC_DIV (0xff << 0) /* Divider */ -#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ -#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ -#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ -#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ -#define AT91_PMC_USBDIV_1 (0 << 28) -#define AT91_PMC_USBDIV_2 (1 << 28) -#define AT91_PMC_USBDIV_4 (2 << 28) -#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ -#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ - -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ -#endif -#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ -#define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) -#define AT91_PMC_CSS_PLLA (2 << 0) -#define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ -#define AT91_PMC_PRES_1 (0 << 2) -#define AT91_PMC_PRES_2 (1 << 2) -#define AT91_PMC_PRES_4 (2 << 2) -#define AT91_PMC_PRES_8 (3 << 2) -#define AT91_PMC_PRES_16 (4 << 2) -#define AT91_PMC_PRES_32 (5 << 2) -#define AT91_PMC_PRES_64 (6 << 2) -#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ -#define AT91RM9200_PMC_MDIV_2 (1 << 8) -#define AT91RM9200_PMC_MDIV_3 (2 << 8) -#define AT91RM9200_PMC_MDIV_4 (3 << 8) -#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ -#define AT91SAM9_PMC_MDIV_2 (1 << 8) -#define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ -#define AT91SAM9_PMC_MDIV_6 (3 << 8) -#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ -#define AT91_PMC_PDIV_1 (0 << 12) -#define AT91_PMC_PDIV_2 (1 << 12) - -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ - -#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ -#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ -#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ -#endif -#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ -#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ -#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ -#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ -#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ -#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ - -#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ -#endif -#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ -#endif /* CONFIG_AT91_LEGACY */ -#endif diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h deleted file mode 100644 index 9ff2c5b..0000000 --- a/include/asm-arm/arch-at91/at91_rstc.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Reset Controller (RSTC) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_RSTC_H -#define AT91_RSTC_H - -#define AT91_ASM_RSTC_MR (AT91_RSTC_BASE + 0x08) - -#ifndef __ASSEMBLY__ - -typedef struct at91_rstc { - u32 cr; /* Reset Controller Control Register */ - u32 sr; /* Reset Controller Status Register */ - u32 mr; /* Reset Controller Mode Register */ -} at91_rstc_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_RSTC_KEY 0xA5000000 - -#define AT91_RSTC_CR_PROCRST 0x00000001 -#define AT91_RSTC_CR_PERRST 0x00000004 -#define AT91_RSTC_CR_EXTRST 0x00000008 - -#define AT91_RSTC_MR_URSTEN 0x00000001 -#define AT91_RSTC_MR_URSTIEN 0x00000010 -#define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8) -#define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00 - -#define AT91_RSTC_SR_NRSTL 0x00010000 - -#ifdef CONFIG_AT91_LEGACY - -#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ -#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ -#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ -#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ - -#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ -#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ -#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ -#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) -#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) -#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) -#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) -#define AT91_RSTC_RSTTYP_USER (4 << 8) -#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ -#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ - -#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ -#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ -#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ -#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ - -#endif /* CONFIG_AT91_LEGACY */ - -#endif diff --git a/include/asm-arm/arch-at91/at91_spi.h b/include/asm-arm/arch-at91/at91_spi.h deleted file mode 100644 index c520e89..0000000 --- a/include/asm-arm/arch-at91/at91_spi.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Serial Peripheral Interface (SPI) registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_SPI_H -#define AT91_SPI_H - -#include - -typedef struct at91_spi { - u32 cr; /* 0x00 Control Register */ - u32 mr; /* 0x04 Mode Register */ - u32 rdr; /* 0x08 Receive Data Register */ - u32 tdr; /* 0x0C Transmit Data Register */ - u32 sr; /* 0x10 Status Register */ - u32 ier; /* 0x14 Interrupt Enable Register */ - u32 idr; /* 0x18 Interrupt Disable Register */ - u32 imr; /* 0x1C Interrupt Mask Register */ - u32 reserve1[4]; - u32 csr[4]; /* 0x30 Chip Select Register 0-3 */ - u32 reserve2[48]; - at91_pdc_t pdc; -} at91_spi_t; - -#ifdef CONFIG_AT91_LEGACY - -#define AT91_SPI_CR 0x00 /* Control Register */ -#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ -#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ -#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ -#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ - -#define AT91_SPI_MR 0x04 /* Mode Register */ -#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ -#define AT91_SPI_PS (1 << 1) /* Peripheral Select */ -#define AT91_SPI_PS_FIXED (0 << 1) -#define AT91_SPI_PS_VARIABLE (1 << 1) -#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ -#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ -#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ -#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ -#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ -#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ - -#define AT91_SPI_RDR 0x08 /* Receive Data Register */ -#define AT91_SPI_RD (0xffff << 0) /* Receive Data */ -#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ - -#define AT91_SPI_TDR 0x0c /* Transmit Data Register */ -#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ -#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ -#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ - -#define AT91_SPI_SR 0x10 /* Status Register */ -#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ -#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ -#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ -#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ -#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ -#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ -#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ -#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ -#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ -#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ -#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ - -#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ -#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ -#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ - -#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ -#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ -#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ -#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ -#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ -#define AT91_SPI_BITS_8 (0 << 4) -#define AT91_SPI_BITS_9 (1 << 4) -#define AT91_SPI_BITS_10 (2 << 4) -#define AT91_SPI_BITS_11 (3 << 4) -#define AT91_SPI_BITS_12 (4 << 4) -#define AT91_SPI_BITS_13 (5 << 4) -#define AT91_SPI_BITS_14 (6 << 4) -#define AT91_SPI_BITS_15 (7 << 4) -#define AT91_SPI_BITS_16 (8 << 4) -#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ -#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ -#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ - -#define AT91_SPI_RPR 0x0100 /* Receive Pointer Register */ - -#define AT91_SPI_RCR 0x0104 /* Receive Counter Register */ - -#define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */ - -#define AT91_SPI_TCR 0x010c /* Transmit Counter Register */ - -#define AT91_SPI_RNPR 0x0110 /* Receive Next Pointer Register */ - -#define AT91_SPI_RNCR 0x0114 /* Receive Next Counter Register */ - -#define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */ - -#define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */ - -#define AT91_SPI_PTCR 0x0120 /* PDC Transfer Control Register */ -#define AT91_SPI_RXTEN (0x1 << 0) /* Receiver Transfer Enable */ -#define AT91_SPI_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */ -#define AT91_SPI_TXTEN (0x1 << 8) /* Transmitter Transfer Enable */ -#define AT91_SPI_TXTDIS (0x1 << 9) /* Transmitter Transfer Disable */ - -#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */ - -#endif /* CONFIG_AT91_LEGACY */ - -#endif diff --git a/include/asm-arm/arch-at91/at91_st.h b/include/asm-arm/arch-at91/at91_st.h deleted file mode 100644 index 53f9320..0000000 --- a/include/asm-arm/arch-at91/at91_st.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef AT91_ST_H -#define AT91_ST_H - -typedef struct at91_st { - - u32 cr; - u32 pimr; - u32 wdmr; - u32 rtmr; - u32 sr; - u32 ier; - u32 idr; - u32 imr; - u32 rtar; - u32 crtr; -} __attribute__ ((packed)) at91_st_t ; - -#define AT91_ST_CR_WDRST 1 - -#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF) -#define AT91_ST_WDMR_RSTEN 0x00010000 -#define AT91_ST_WDMR_EXTEN 0x00020000 - -#endif diff --git a/include/asm-arm/arch-at91/at91_tc.h b/include/asm-arm/arch-at91/at91_tc.h deleted file mode 100644 index 1e180ad..0000000 --- a/include/asm-arm/arch-at91/at91_tc.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef AT91_TC_H -#define AT91_TC_H - -typedef struct at91_tcc { - u32 ccr; /* 0x00 Channel Control Register */ - u32 cmr; /* 0x04 Channel Mode Register */ - u32 reserved1[2]; - u32 cv; /* 0x10 Counter Value */ - u32 ra; /* 0x14 Register A */ - u32 rb; /* 0x18 Register B */ - u32 rc; /* 0x1C Register C */ - u32 sr; /* 0x20 Status Register */ - u32 ier; /* 0x24 Interrupt Enable Register */ - u32 idr; /* 0x28 Interrupt Disable Register */ - u32 imr; /* 0x2C Interrupt Mask Register */ - u32 reserved3[4]; -} __attribute__ ((packed)) at91_tcc_t; - -#define AT91_TC_CCR_CLKEN 0x00000001 -#define AT91_TC_CCR_CLKDIS 0x00000002 -#define AT91_TC_CCR_SWTRG 0x00000004 - -#define AT91_TC_CMR_CPCTRG 0x00004000 - -#define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000 -#define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001 -#define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002 -#define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003 -#define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004 -#define AT91_TC_CMR_TCCLKS_XC0 0x00000005 -#define AT91_TC_CMR_TCCLKS_XC1 0x00000006 -#define AT91_TC_CMR_TCCLKS_XC2 0x00000007 - -typedef struct at91_tc { - at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */ - u32 bcr; /* 0xC0 TC Block Control Register */ - u32 bmr; /* 0xC4 TC Block Mode Register */ -} __attribute__ ((packed)) at91_tc_t; - -#define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000 -#define AT91_TC_BMR_TC0XC0S_NONE 0x00000001 -#define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002 -#define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003 - -#define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000 -#define AT91_TC_BMR_TC1XC1S_NONE 0x00000004 -#define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008 -#define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C - -#define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000 -#define AT91_TC_BMR_TC2XC2S_NONE 0x00000010 -#define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020 -#define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030 - -#endif diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h deleted file mode 100644 index cf08daf..0000000 --- a/include/asm-arm/arch-at91/at91_wdt.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] - * - * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Watchdog Timer (WDT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_WDT_H -#define AT91_WDT_H - -#ifdef __ASSEMBLY__ - -#define AT91_ASM_WDT_MR (AT91_WDT_BASE + 0x04) - -#else - -typedef struct at91_wdt { - u32 cr; - u32 mr; - u32 sr; -} at91_wdt_t; - -#endif - -#define AT91_WDT_CR_WDRSTT 1 -#define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ - -#define AT91_WDT_MR_WDV(x) (x & 0xfff) -#define AT91_WDT_MR_WDFIEN 0x00001000 -#define AT91_WDT_MR_WDRSTEN 0x00002000 -#define AT91_WDT_MR_WDRPROC 0x00004000 -#define AT91_WDT_MR_WDDIS 0x00008000 -#define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16) -#define AT91_WDT_MR_WDDBGHLT 0x10000000 -#define AT91_WDT_MR_WDIDLEHLT 0x20000000 - -#ifdef CONFIG_AT91_LEGACY - -#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ -#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ -#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ - -#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ -#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ -#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ -#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ -#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ -#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ -#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ -#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ -#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ - -#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ -#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ -#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ - -#endif /* CONFIG_AT91_LEGACY */ -#endif diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h deleted file mode 100644 index 5af6fdc..0000000 --- a/include/asm-arm/arch-at91/at91cap9.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h] - * - * Copyright (C) 2007 Stelian Pop - * Copyright (C) 2007 Lead Tech Design - * Copyright (C) 2007 Atmel Corporation. - * - * Common definitions. - * Based on AT91CAP9 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91CAP9_H -#define AT91CAP9_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */ -#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */ -#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */ -#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */ -#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */ -#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */ -#define AT91CAP9_ID_US0 8 /* USART 0 */ -#define AT91CAP9_ID_US1 9 /* USART 1 */ -#define AT91CAP9_ID_US2 10 /* USART 2 */ -#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */ -#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */ -#define AT91CAP9_ID_CAN 13 /* CAN */ -#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */ -#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */ -#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */ -#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */ -#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */ -#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */ -#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */ -#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */ -#define AT91CAP9_ID_EMAC 22 /* Ethernet */ -#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */ -#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */ -#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */ -#define AT91CAP9_ID_LCDC 26 /* LCD Controller */ -#define AT91CAP9_ID_DMA 27 /* DMA Controller */ -#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */ -#define AT91CAP9_ID_UHP 29 /* USB Host Port */ -#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - -#define AT91_PIO_BASE 0xfffff200 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 - -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91CAP9_BASE_UDPHS 0xfff78000 -#define AT91CAP9_BASE_TCB0 0xfff7c000 -#define AT91CAP9_BASE_TC0 0xfff7c000 -#define AT91CAP9_BASE_TC1 0xfff7c040 -#define AT91CAP9_BASE_TC2 0xfff7c080 -#define AT91CAP9_BASE_MCI0 0xfff80000 -#define AT91CAP9_BASE_MCI1 0xfff84000 -#define AT91CAP9_BASE_TWI 0xfff88000 -#define AT91CAP9_BASE_US0 0xfff8c000 -#define AT91CAP9_BASE_US1 0xfff90000 -#define AT91CAP9_BASE_US2 0xfff94000 -#define AT91CAP9_BASE_SSC0 0xfff98000 -#define AT91CAP9_BASE_SSC1 0xfff9c000 -#define AT91CAP9_BASE_AC97C 0xfffa0000 -#define AT91CAP9_BASE_SPI0 0xfffa4000 -#define AT91CAP9_BASE_SPI1 0xfffa8000 -#define AT91CAP9_BASE_CAN 0xfffac000 -#define AT91CAP9_BASE_PWMC 0xfffb8000 -#define AT91CAP9_BASE_EMAC 0xfffbc000 -#define AT91CAP9_BASE_ADC 0xfffc0000 -#define AT91CAP9_BASE_ISI 0xfffc4000 -#define AT91_BASE_SYS 0xffffe200 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) -#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) -#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS) - -#define AT91_USART0 AT91CAP9_BASE_US0 -#define AT91_USART1 AT91CAP9_BASE_US1 -#define AT91_USART2 AT91CAP9_BASE_US2 - -/* - * SCKCR flags - */ -#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */ -#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */ -#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */ -#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */ -#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3) -#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3) - -#endif /* CONFIG_AT91_LEGACY */ -/* - * Internal Memory. - */ -#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ -#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */ - -#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ - -#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */ -#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ - -#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 - -/* - * Cpu Name - */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9" - -#endif diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h deleted file mode 100644 index 22b7e9b..0000000 --- a/include/asm-arm/arch-at91/at91cap9_matrix.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h] - * - * Copyright (C) 2007 Stelian Pop - * Copyright (C) 2007 Lead Tech Design - * Copyright (C) 2006 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91CAP9 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91CAP9_MATRIX_H -#define AT91CAP9_MATRIX_H - -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ -#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ -#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ -#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */ -#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */ -#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */ -#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */ -#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) -#define AT91_MATRIX_RCB11 (1 << 11) - -#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */ -#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */ - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */ -#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) - -#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */ -#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */ -#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */ - -#endif diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h deleted file mode 100644 index 1bee6f2..0000000 --- a/include/asm-arm/arch-at91/at91rm9200.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __AT91RM9200_H__ -#define __AT91RM9200_H__ - -/* Periperial Identifiers */ - -#define AT91_ID_SYS 1 /* System Peripheral */ -#define AT91_ID_PIOA 2 /* PIO port A */ -#define AT91_ID_PIOB 3 /* PIO port B */ -#define AT91_ID_PIOC 4 /* PIO port C */ -#define AT91_ID_PIOD 5 /* PIO port D BGA only */ -#define AT91_ID_USART0 6 /* USART 0 */ -#define AT91_ID_USART1 7 /* USART 1 */ -#define AT91_ID_USART2 8 /* USART 2 */ -#define AT91_ID_USART3 9 /* USART 3 */ -#define AT91_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91_ID_UDP 11 /* USB Device Port */ -#define AT91_ID_TWI 12 /* Two Wire Interface */ -#define AT91_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91_ID_SSC0 14 /* Synch. Serial Controller 0 */ -#define AT91_ID_SSC1 15 /* Synch. Serial Controller 1 */ -#define AT91_ID_SSC2 16 /* Synch. Serial Controller 2 */ -#define AT91_ID_TC0 17 /* Timer Counter 0 */ -#define AT91_ID_TC1 18 /* Timer Counter 1 */ -#define AT91_ID_TC2 19 /* Timer Counter 2 */ -#define AT91_ID_TC3 20 /* Timer Counter 3 */ -#define AT91_ID_TC4 21 /* Timer Counter 4 */ -#define AT91_ID_TC5 22 /* Timer Counter 5 */ -#define AT91_ID_UHP 23 /* OHCI USB Host Port */ -#define AT91_ID_EMAC 24 /* Ethernet MAC */ -#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller */ - -#define AT91_USB_HOST_BASE 0x00300000 - -#define AT91_TC_BASE 0xFFFA0000 -#define AT91_UDP_BASE 0xFFFB0000 -#define AT91_MCI_BASE 0xFFFB4000 -#define AT91_TWI_BASE 0xFFFB8000 -#define AT91_EMAC_BASE 0xFFFBC000 -#define AT91_USART_BASE 0xFFFC0000 /* 4x 0x4000 Offset */ -#define AT91_SCC_BASE 0xFFFD0000 /* 4x 0x4000 Offset */ -#define AT91_SPI_BASE 0xFFFE0000 - -#define AT91_AIC_BASE 0xFFFFF000 -#define AT91_DBGU_BASE 0xFFFFF200 -#define AT91_PIO_BASE 0xFFFFF400 /* 4x 0x200 Offset */ -#define AT91_PMC_BASE 0xFFFFFC00 -#define AT91_ST_BASE 0xFFFFFD00 -#define AT91_ST_BASE 0xFFFFFD00 -#define AT91_RTC_BASE 0xFFFFFE00 -#define AT91_MC_BASE 0xFFFFFF00 - - -/* AT91RM9200 Periperial Multiplexing A */ -/* Port A */ -#define AT91_PMX_AA_EREFCK 0x00000080 -#define AT91_PMX_AA_ETXCK 0x00000080 -#define AT91_PMX_AA_ETXEN 0x00000100 -#define AT91_PMX_AA_ETX0 0x00000200 -#define AT91_PMX_AA_ETX1 0x00000400 -#define AT91_PMX_AA_ECRS 0x00000800 -#define AT91_PMX_AA_ECRSDV 0x00000800 -#define AT91_PMX_AA_ERX0 0x00001000 -#define AT91_PMX_AA_ERX1 0x00002000 -#define AT91_PMX_AA_ERXER 0x00004000 -#define AT91_PMX_AA_EMDC 0x00008000 -#define AT91_PMX_AA_EMDIO 0x00010000 - -#define AT91_PMX_AA_TXD2 0x00810000 - -#define AT91_PMX_AA_TWD 0x02000000 -#define AT91_PMX_AA_TWCK 0x04000000 - -/* Port B */ -#define AT91_PMX_BA_ERXCK 0x00080000 -#define AT91_PMX_BA_ECOL 0x00040000 -#define AT91_PMX_BA_ERXDV 0x00020000 -#define AT91_PMX_BA_ERX3 0x00010000 -#define AT91_PMX_BA_ERX2 0x00008000 -#define AT91_PMX_BA_ETXER 0x00004000 -#define AT91_PMX_BA_ETX3 0x00002000 -#define AT91_PMX_BA_ETX2 0x00001000 - -/* Port B */ - -#define AT91_PMX_CA_BFCK 0x00000001 -#define AT91_PMX_CA_BFRDY 0x00000002 -#define AT91_PMX_CA_SMOE 0x00000002 -#define AT91_PMX_CA_BFAVD 0x00000004 -#define AT91_PMX_CA_BFBAA 0x00000008 -#define AT91_PMX_CA_SMWE 0x00000008 -#define AT91_PMX_CA_BFOE 0x00000010 -#define AT91_PMX_CA_BFWE 0x00000020 -#define AT91_PMX_CA_NWAIT 0x00000040 -#define AT91_PMX_CA_A23 0x00000080 -#define AT91_PMX_CA_A24 0x00000100 -#define AT91_PMX_CA_A25 0x00000200 -#define AT91_PMX_CA_CFRNW 0x00000200 -#define AT91_PMX_CA_NCS4 0x00000400 -#define AT91_PMX_CA_CFCS 0x00000400 -#define AT91_PMX_CA_NCS5 0x00000800 -#define AT91_PMX_CA_CFCE1 0x00001000 -#define AT91_PMX_CA_NCS6 0x00001000 -#define AT91_PMX_CA_CFCE2 0x00002000 -#define AT91_PMX_CA_NCS7 0x00002000 -#define AT91_PMX_CA_D16_31 0xFFFF0000 - -#define CONFIG_SYS_AT91_CPU_NAME "AT91RM9200" - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h deleted file mode 100644 index a60a081..0000000 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] - * - * (C) 2006 Andrew Victor - * - * Common definitions. - * Based on AT91SAM9260 datasheet revision A (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_H -#define AT91SAM9260_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - -#define AT91_EMAC_BASE 0xfffc4000 -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 -#define AT91_BASE_SYS 0xffffe800 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9260_BASE_US0 -#define AT91_USART1 AT91SAM9260_BASE_US1 -#define AT91_USART2 AT91SAM9260_BASE_US2 -#define AT91_USART3 AT91SAM9260_BASE_US3 -#define AT91_USART4 AT91SAM9260_BASE_US4 -#define AT91_USART5 AT91SAM9260_BASE_US5 - -#endif /* CONFIG_AT91_LEGACY */ - -/* - * Internal Memory. - */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ - -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ - -#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ -#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ - -/* - * Cpu Name - */ -#if defined(CONFIG_AT91SAM9260) -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260" -#elif defined(CONFIG_AT91SAM9G20) -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20" -#endif - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h deleted file mode 100644 index f8b023d..0000000 --- a/include/asm-arm/arch-at91/at91sam9260_matrix.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h] - * - * Copyright (C) 2007 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9260 datasheet revision B. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_MATRIX_H -#define AT91SAM9260_MATRIX_H - -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h deleted file mode 100644 index 2952292..0000000 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] - * - * Copyright (C) SAN People - * - * Common definitions. - * Based on AT91SAM9261 datasheet revision E. (Preliminary) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9261_H -#define AT91SAM9261_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9261_ID_US0 6 /* USART 0 */ -#define AT91SAM9261_ID_US1 7 /* USART 1 */ -#define AT91SAM9261_ID_US2 8 /* USART 2 */ -#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9261_ID_UHP 20 /* USB Host port */ -#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ -#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9261_BASE_TCB0 0xfffa0000 -#define AT91SAM9261_BASE_TC0 0xfffa0000 -#define AT91SAM9261_BASE_TC1 0xfffa0040 -#define AT91SAM9261_BASE_TC2 0xfffa0080 -#define AT91SAM9261_BASE_UDP 0xfffa4000 -#define AT91SAM9261_BASE_MCI 0xfffa8000 -#define AT91SAM9261_BASE_TWI 0xfffac000 -#define AT91SAM9261_BASE_US0 0xfffb0000 -#define AT91SAM9261_BASE_US1 0xfffb4000 -#define AT91SAM9261_BASE_US2 0xfffb8000 -#define AT91SAM9261_BASE_SSC0 0xfffbc000 -#define AT91SAM9261_BASE_SSC1 0xfffc0000 -#define AT91SAM9261_BASE_SSC2 0xfffc4000 -#define AT91SAM9261_BASE_SPI0 0xfffc8000 -#define AT91SAM9261_BASE_SPI1 0xfffcc000 -#define AT91_BASE_SYS 0xffffea00 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9261_BASE_US0 -#define AT91_USART1 AT91SAM9261_BASE_US1 -#define AT91_USART2 AT91SAM9261_BASE_US2 - -#endif /* CONFIG_AT91_LEGACY */ - -/* - * Internal Memory. - */ -#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ - -#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ - -/* - * Cpu Name - */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9261_matrix.h b/include/asm-arm/arch-at91/at91sam9261_matrix.h deleted file mode 100644 index e2bfc4b..0000000 --- a/include/asm-arm/arch-at91/at91sam9261_matrix.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h] - * - * Copyright (C) 2007 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9261_MATRIX_H -#define AT91SAM9261_MATRIX_H - -#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ - -#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_ITCM_64 (7 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) -#define AT91_MATRIX_DTCM_64 (7 << 4) - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ - -#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ -#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h deleted file mode 100644 index c177bd0..0000000 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] - * - * (C) 2007 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9263_H -#define AT91SAM9263_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ -#define AT91SAM9263_ID_US0 7 /* USART 0 */ -#define AT91SAM9263_ID_US1 8 /* USART 1 */ -#define AT91SAM9263_ID_US2 9 /* USART 2 */ -#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define AT91SAM9263_ID_CAN 12 /* CAN */ -#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ -#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ -#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ -#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ -#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ -#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ -#define AT91SAM9263_ID_UHP 29 /* USB Host port */ -#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - -#define AT91_EMAC_BASE 0xfffbc000 -#define AT91_ECC0_BASE 0xffffe000 -#define AT91_SDRAMC0_BASE 0xffffe200 -#define AT91_SMC0_BASE 0xffffe400 -#define AT91_ECC1_BASE 0xffffe600 -#define AT91_SDRAMC1_BASE 0xffffe800 -#define AT91_SMC1_BASE 0xffffea00 -#define AT91_MATRIX_BASE 0xffffec00 -#define AT91_CCFG_BASE 0xffffed10 -#define AT91_DBGU_BASE 0xffffee00 -#define AT91_AIC_BASE 0xfffff000 -#define AT91_PIO_BASE 0xfffff200 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9263_BASE_UDP 0xfff78000 -#define AT91SAM9263_BASE_TCB0 0xfff7c000 -#define AT91SAM9263_BASE_TC0 0xfff7c000 -#define AT91SAM9263_BASE_TC1 0xfff7c040 -#define AT91SAM9263_BASE_TC2 0xfff7c080 -#define AT91SAM9263_BASE_MCI0 0xfff80000 -#define AT91SAM9263_BASE_MCI1 0xfff84000 -#define AT91SAM9263_BASE_TWI 0xfff88000 -#define AT91SAM9263_BASE_US0 0xfff8c000 -#define AT91SAM9263_BASE_US1 0xfff90000 -#define AT91SAM9263_BASE_US2 0xfff94000 -#define AT91SAM9263_BASE_SSC0 0xfff98000 -#define AT91SAM9263_BASE_SSC1 0xfff9c000 -#define AT91SAM9263_BASE_AC97C 0xfffa0000 -#define AT91SAM9263_BASE_SPI0 0xfffa4000 -#define AT91SAM9263_BASE_SPI1 0xfffa8000 -#define AT91SAM9263_BASE_CAN 0xfffac000 -#define AT91SAM9263_BASE_PWMC 0xfffb8000 -#define AT91SAM9263_BASE_EMAC 0xfffbc000 -#define AT91SAM9263_BASE_ISI 0xfffc4000 -#define AT91SAM9263_BASE_2DGE 0xfffc8000 -#define AT91_BASE_SYS 0xffffe000 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) -#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) -#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) -#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9263_BASE_US0 -#define AT91_USART1 AT91SAM9263_BASE_US1 -#define AT91_USART2 AT91SAM9263_BASE_US2 - -#define AT91_SMC AT91_SMC0 -#define AT91_SDRAMC AT91_SDRAMC0 - -#endif /* CONFIG_AT91_LEGACY */ - -/* - * Internal Memory. - */ -#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ -#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ - -#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ -#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ - -#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ -#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ -#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ - -/* - * Cpu Name - */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h deleted file mode 100644 index 83aaaab..0000000 --- a/include/asm-arm/arch-at91/at91sam9263_matrix.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] - * - * Copyright (C) 2006 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9263_MATRIX_H -#define AT91SAM9263_MATRIX_H - -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) - -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) - -#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ -#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) - -#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ -#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) -#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9_matrix.h b/include/asm-arm/arch-at91/at91sam9_matrix.h deleted file mode 100644 index 6d97189..0000000 --- a/include/asm-arm/arch-at91/at91sam9_matrix.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H -#define __ASM_ARCH_AT91SAM9_MATRIX_H - -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#include -#elif defined(CONFIG_AT91SAM9261) -#include -#elif defined(CONFIG_AT91SAM9263) -#include -#elif defined(CONFIG_AT91SAM9RL) -#include -#elif defined(CONFIG_AT91CAP9) -#include -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) -#include -#else -#error "Unsupported AT91SAM9/CAP9 processor" -#endif - -#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */ diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h deleted file mode 100644 index c3da3a6..0000000 --- a/include/asm-arm/arch-at91/at91sam9_sdramc.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] - * - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * SDRAM Controllers (SDRAMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9_SDRAMC_H -#define AT91SAM9_SDRAMC_H - -#ifdef __ASSEMBLY__ - -#ifndef AT91_SDRAMC_BASE -#define AT91_SDRAMC_BASE AT91_SDRAMC0_BASE -#endif - -#define AT91_ASM_SDRAMC_MR AT91_SDRAMC_BASE -#define AT91_ASM_SDRAMC_TR (AT91_SDRAMC_BASE + 0x04) -#define AT91_ASM_SDRAMC_CR (AT91_SDRAMC_BASE + 0x08) -#define AT91_ASM_SDRAMC_MDR (AT91_SDRAMC_BASE + 0x24) - -#endif - -/* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ -#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ -#define AT91_SDRAMC_MODE_NORMAL 0 -#define AT91_SDRAMC_MODE_NOP 1 -#define AT91_SDRAMC_MODE_PRECHARGE 2 -#define AT91_SDRAMC_MODE_LMR 3 -#define AT91_SDRAMC_MODE_REFRESH 4 -#define AT91_SDRAMC_MODE_EXT_LMR 5 -#define AT91_SDRAMC_MODE_DEEP 6 - -#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ -#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ - -#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ -#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_SDRAMC_NC_8 (0 << 0) -#define AT91_SDRAMC_NC_9 (1 << 0) -#define AT91_SDRAMC_NC_10 (2 << 0) -#define AT91_SDRAMC_NC_11 (3 << 0) -#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_SDRAMC_NR_11 (0 << 2) -#define AT91_SDRAMC_NR_12 (1 << 2) -#define AT91_SDRAMC_NR_13 (2 << 2) -#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ -#define AT91_SDRAMC_NB_2 (0 << 4) -#define AT91_SDRAMC_NB_4 (1 << 4) -#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91_SDRAMC_CAS_1 (1 << 5) -#define AT91_SDRAMC_CAS_2 (2 << 5) -#define AT91_SDRAMC_CAS_3 (3 << 5) -#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ -#define AT91_SDRAMC_DBW_32 (0 << 7) -#define AT91_SDRAMC_DBW_16 (1 << 7) -#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ -#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ -#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ -#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ -#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ -#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ - -#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ -#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ -#define AT91_SDRAMC_LPCB_DISABLE 0 -#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 -#define AT91_SDRAMC_LPCB_POWER_DOWN 2 -#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 -#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ -#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ -#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ -#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) -#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) - -#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ -#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ - -#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ -#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ -#define AT91_SDRAMC_MD_SDRAM 0 -#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 - - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h deleted file mode 100644 index d180c8a..0000000 --- a/include/asm-arm/arch-at91/at91sam9_smc.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Static Memory Controllers (SMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9_SMC_H -#define AT91SAM9_SMC_H - -#ifdef __ASSEMBLY__ - -#ifndef AT91_SMC_BASE -#define AT91_SMC_BASE AT91_SMC0_BASE -#endif - -#define AT91_ASM_SMC_SETUP0 AT91_SMC_BASE -#define AT91_ASM_SMC_PULSE0 (AT91_SMC_BASE + 0x04) -#define AT91_ASM_SMC_CYCLE0 (AT91_SMC_BASE + 0x08) -#define AT91_ASM_SMC_MODE0 (AT91_SMC_BASE + 0x0C) - -#else - -typedef struct at91_cs { - u32 setup; /* 0x00 SMC Setup Register */ - u32 pulse; /* 0x04 SMC Pulse Register */ - u32 cycle; /* 0x08 SMC Cycle Register */ - u32 mode; /* 0x0C SMC Mode Register */ -} at91_cs_t; - -typedef struct at91_smc { - at91_cs_t cs[8]; -} at91_smc_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_SMC_SETUP_NWE(x) (x & 0x3f) -#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) -#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) -#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) - -#define AT91_SMC_PULSE_NWE(x) (x & 0x7f) -#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) -#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) -#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) - -#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) -#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) - -#define AT91_SMC_MODE_RM_NCS 0x00000000 -#define AT91_SMC_MODE_RM_NRD 0x00000001 -#define AT91_SMC_MODE_WM_NCS 0x00000000 -#define AT91_SMC_MODE_WM_NWE 0x00000002 - -#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 -#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 -#define AT91_SMC_MODE_EXNW_READY 0x00000030 - -#define AT91_SMC_MODE_BAT 0x00000100 -#define AT91_SMC_MODE_DBW_8 0x00000000 -#define AT91_SMC_MODE_DBW_16 0x00001000 -#define AT91_SMC_MODE_DBW_32 0x00002000 -#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) -#define AT91_SMC_MODE_TDF 0x00100000 -#define AT91_SMC_MODE_PMEN 0x01000000 -#define AT91_SMC_MODE_PS_4 0x00000000 -#define AT91_SMC_MODE_PS_8 0x10000000 -#define AT91_SMC_MODE_PS_16 0x20000000 -#define AT91_SMC_MODE_PS_32 0x30000000 - -#ifdef CONFIG_AT91_LEGACY - -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ -#define AT91_SMC_NWESETUP_(x) ((x) << 0) -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ -#define AT91_SMC_NRDSETUP_(x) ((x) << 16) -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) - -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ -#define AT91_SMC_NWEPULSE_(x) ((x) << 0) -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ -#define AT91_SMC_NRDPULSE_(x) ((x) << 16) -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) - -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ -#define AT91_SMC_NWECYCLE_(x) ((x) << 0) -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) - -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) -#define AT91_SMC_EXNWMODE_READY (3 << 4) -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ -#define AT91_SMC_BAT_SELECT (0 << 8) -#define AT91_SMC_BAT_WRITE (1 << 8) -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ -#define AT91_SMC_DBW_8 (0 << 12) -#define AT91_SMC_DBW_16 (1 << 12) -#define AT91_SMC_DBW_32 (2 << 12) -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ -#define AT91_SMC_TDF_(x) ((x) << 16) -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ -#define AT91_SMC_PS (3 << 28) /* Page Size */ -#define AT91_SMC_PS_4 (0 << 28) -#define AT91_SMC_PS_8 (1 << 28) -#define AT91_SMC_PS_16 (2 << 28) -#define AT91_SMC_PS_32 (3 << 28) - -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#endif - -#endif -#endif diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/include/asm-arm/arch-at91/at91sam9g45.h deleted file mode 100644 index 445f4b2..0000000 --- a/include/asm-arm/arch-at91/at91sam9g45.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Chip-specific header file for the AT91SAM9M1x family - * - * Copyright (C) 2008 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9G45 preliminary datasheet. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9G45_H -#define AT91SAM9G45_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Controller Interrupt */ -#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ -#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ -#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ -#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ -#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ -#define AT91SAM9G45_ID_US0 7 /* USART 0 */ -#define AT91SAM9G45_ID_US1 8 /* USART 1 */ -#define AT91SAM9G45_ID_US2 9 /* USART 2 */ -#define AT91SAM9G45_ID_US3 10 /* USART 3 */ -#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ -#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ -#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ -#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ -#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ -#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ -#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ -#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ -#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ -#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ -#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -#define AT91_EMAC_BASE 0xfffbc000 -#define AT91_SMC_BASE 0xffffe800 -#define AT91_MATRIX_BASE 0xffffea00 -#define AT91_PIO_BASE 0xfffff200 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9G45_BASE_UDPHS 0xfff78000 -#define AT91SAM9G45_BASE_TC0 0xfff7c000 -#define AT91SAM9G45_BASE_TC1 0xfff7c040 -#define AT91SAM9G45_BASE_TC2 0xfff7c080 -#define AT91SAM9G45_BASE_MCI0 0xfff80000 -#define AT91SAM9G45_BASE_TWI0 0xfff84000 -#define AT91SAM9G45_BASE_TWI1 0xfff88000 -#define AT91SAM9G45_BASE_US0 0xfff8c000 -#define AT91SAM9G45_BASE_US1 0xfff90000 -#define AT91SAM9G45_BASE_US2 0xfff94000 -#define AT91SAM9G45_BASE_US3 0xfff98000 -#define AT91SAM9G45_BASE_SSC0 0xfff9c000 -#define AT91SAM9G45_BASE_SSC1 0xfffa0000 -#define AT91SAM9G45_BASE_SPI0 0xfffa4000 -#define AT91SAM9G45_BASE_SPI1 0xfffa8000 -#define AT91SAM9G45_BASE_AC97C 0xfffac000 -#define AT91SAM9G45_BASE_TSC 0xfffb0000 -#define AT91SAM9G45_BASE_ISI 0xfffb4000 -#define AT91SAM9G45_BASE_PWMC 0xfffb8000 -#define AT91SAM9G45_BASE_EMAC 0xfffbc000 -#define AT91SAM9G45_BASE_AES 0xfffc0000 -#define AT91SAM9G45_BASE_TDES 0xfffc4000 -#define AT91SAM9G45_BASE_SHA 0xfffc8000 -#define AT91SAM9G45_BASE_TRNG 0xfffcc000 -#define AT91SAM9G45_BASE_MCI1 0xfffd0000 -#define AT91SAM9G45_BASE_TC3 0xfffd4000 -#define AT91SAM9G45_BASE_TC4 0xfffd4040 -#define AT91SAM9G45_BASE_TC5 0xfffd4080 -#define AT91_BASE_SYS 0xffffe200 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) -#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) -#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9G45_BASE_US0 -#define AT91_USART1 AT91SAM9G45_BASE_US1 -#define AT91_USART2 AT91SAM9G45_BASE_US2 -#define AT91_USART3 AT91SAM9G45_BASE_US3 - -#endif - -/* - * Internal Memory. - */ -#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ - -#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ - -#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ -#define AT91SAM9G45_HCI_BASE 0x00700000 /* USB Host controller (OHCI) */ -#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ -#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ - -#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 - -/* - * Cpu Name - */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9g45_matrix.h b/include/asm-arm/arch-at91/at91sam9g45_matrix.h deleted file mode 100644 index 1620e1b..0000000 --- a/include/asm-arm/arch-at91/at91sam9g45_matrix.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Matrix-centric header file for the AT91SAM9M1x family - * - * Copyright (C) 2008 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9G45 preliminary datasheet. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9G45_MATRIX_H -#define AT91SAM9G45_MATRIX_H - -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ -#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ -#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ -#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91_MATRIX_ULBT_128 (7 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) -#define AT91_MATRIX_RCB11 (1 << 11) - -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) -#define AT91_MATRIX_DTCM_64 (7 << 4) -#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ -#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) -#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) - -#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ -#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ -#define AT91C_VDEC_SEL_OFF (0 << 0) -#define AT91C_VDEC_SEL_ON (1 << 0) - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) -#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) -#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) - -#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ -#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ - -#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ -#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91_MATRIX_WPSR_WPV (1 << 0) -#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h deleted file mode 100644 index 8eb0d4f..0000000 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h] - * - * Copyright (C) 2007 Atmel Corporation - * - * Common definitions. - * Based on AT91SAM9RL datasheet revision A. (Preliminary) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef AT91SAM9RL_H -#define AT91SAM9RL_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Controller */ -#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91SAM9RL_ID_US0 6 /* USART 0 */ -#define AT91SAM9RL_ID_US1 7 /* USART 1 */ -#define AT91SAM9RL_ID_US2 8 /* USART 2 */ -#define AT91SAM9RL_ID_US3 9 /* USART 3 */ -#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ -#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ -#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ -#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ -#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ -#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ -#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ -#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ - -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9RL_BASE_TCB0 0xfffa0000 -#define AT91SAM9RL_BASE_TC0 0xfffa0000 -#define AT91SAM9RL_BASE_TC1 0xfffa0040 -#define AT91SAM9RL_BASE_TC2 0xfffa0080 -#define AT91SAM9RL_BASE_MCI 0xfffa4000 -#define AT91SAM9RL_BASE_TWI0 0xfffa8000 -#define AT91SAM9RL_BASE_TWI1 0xfffac000 -#define AT91SAM9RL_BASE_US0 0xfffb0000 -#define AT91SAM9RL_BASE_US1 0xfffb4000 -#define AT91SAM9RL_BASE_US2 0xfffb8000 -#define AT91SAM9RL_BASE_US3 0xfffbc000 -#define AT91SAM9RL_BASE_SSC0 0xfffc0000 -#define AT91SAM9RL_BASE_SSC1 0xfffc4000 -#define AT91SAM9RL_BASE_PWMC 0xfffc8000 -#define AT91SAM9RL_BASE_SPI 0xfffcc000 -#define AT91SAM9RL_BASE_TSC 0xfffd0000 -#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 -#define AT91SAM9RL_BASE_AC97C 0xfffd8000 -#define AT91_BASE_SYS 0xffffc000 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9RL_BASE_US0 -#define AT91_USART1 AT91SAM9RL_BASE_US1 -#define AT91_USART2 AT91SAM9RL_BASE_US2 -#define AT91_USART3 AT91SAM9RL_BASE_US3 - -#endif /* CONFIG_AT91_LEGACY */ - -/* - * Internal Memory. - */ -#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ - -#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ - -#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ - -/* - * Cpu Name - */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9RL" - -#endif diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h deleted file mode 100644 index af8d914..0000000 --- a/include/asm-arm/arch-at91/at91sam9rl_matrix.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h] - * - * Copyright (C) 2007 Atmel Corporation - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9RL datasheet revision A. (Preliminary) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef AT91SAM9RL_MATRIX_H -#define AT91SAM9RL_MATRIX_H - -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) - -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - - -#endif diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h deleted file mode 100644 index f642dd9..0000000 --- a/include/asm-arm/arch-at91/clk.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2007 - * Stelian Pop - * Lead Tech Design - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_CLK_H__ -#define __ASM_ARM_ARCH_CLK_H__ - -#include - -unsigned long get_cpu_clk_rate(void); -unsigned long get_main_clk_rate(void); -unsigned long get_mck_clk_rate(void); -unsigned long get_plla_clk_rate(void); -unsigned long get_pllb_clk_rate(void); -unsigned int get_pllb_init(void); - -static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) -{ - return get_mck_clk_rate(); -} - -static inline unsigned long get_usart_clk_rate(unsigned int dev_id) -{ - return get_mck_clk_rate(); -} - -static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) -{ - return get_mck_clk_rate(); -} - -static inline unsigned long get_spi_clk_rate(unsigned int dev_id) -{ - return get_mck_clk_rate(); -} - -static inline unsigned long get_twi_clk_rate(unsigned int dev_id) -{ - return get_mck_clk_rate(); -} - -int at91_clock_init(unsigned long main_clock); -#endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h deleted file mode 100644 index 716f81f..0000000 --- a/include/asm-arm/arch-at91/gpio.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h] - * - * Copyright (C) 2005 HP Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_AT91_GPIO_H -#define __ASM_ARCH_AT91_GPIO_H - -#include -#include -#include -#include - -#ifdef CONFIG_AT91_LEGACY - -#define PIN_BASE 32 - -#define MAX_GPIO_BANKS 5 - -/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ - -#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) - -#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) - -#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) - -#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) -#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) -#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) -#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) -#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) -#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) -#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) -#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) -#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) -#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) -#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) -#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) -#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) -#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) -#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) -#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) -#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) -#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) -#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) -#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) -#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) -#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) -#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) -#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) -#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) -#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) -#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) -#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) -#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) -#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) -#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) -#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) - -#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) -#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) -#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) -#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) -#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) -#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) -#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) -#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) -#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) -#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) -#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) -#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) -#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) -#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) -#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) -#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) -#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) -#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) -#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) -#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) -#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) -#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) -#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) -#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) -#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) -#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) -#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) -#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) -#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) -#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) -#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) -#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) - -static unsigned long at91_pios[] = { - AT91_PIOA, - AT91_PIOB, - AT91_PIOC, -#ifdef AT91_PIOD - AT91_PIOD, -#ifdef AT91_PIOE - AT91_PIOE -#endif -#endif -}; - -static inline void *pin_to_controller(unsigned pin) -{ - pin -= PIN_BASE; - pin /= 32; - return (void *)(AT91_BASE_SYS + at91_pios[pin]); -} - -static inline unsigned pin_to_mask(unsigned pin) -{ - pin -= PIN_BASE; - return 1 << (pin % 32); -} - -/* The following macros are need for backward compatibility */ -#define at91_set_GPIO_periph(x, y) \ - at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_A_periph(x, y) \ - at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_B_periph(x, y) \ - at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_gpio_output(x, y) \ - at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_gpio_input(x, y) \ - at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_gpio_value(x, y) \ - at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y) -#define at91_get_gpio_value(x) \ - at91_get_pio_value((x - PIN_BASE) / 32,(x % 32)) -#else -#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y) -#define at91_get_gpio_value(x) at91_get_pio_value(x) -#endif -#endif diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h deleted file mode 100644 index 4ddb315..0000000 --- a/include/asm-arm/arch-at91/hardware.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/hardware.h] - * - * Copyright (C) 2003 SAN People - * Copyright (C) 2003 ATMEL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include - -#if defined(CONFIG_AT91RM9200) -#include -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#include -#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 -#define AT91_ID_UHP AT91SAM9260_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP -#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) -#include -#define AT91_BASE_SPI AT91SAM9261_BASE_SPI0 -#define AT91_ID_UHP AT91SAM9261_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP -#elif defined(CONFIG_AT91SAM9263) -#include -#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0 -#define AT91_ID_UHP AT91SAM9263_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP -#elif defined(CONFIG_AT91SAM9RL) -#include -#define AT91_BASE_SPI AT91SAM9RL_BASE_SPI -#define AT91_ID_UHP AT91SAM9RL_ID_UHP -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) -#include -#define AT91_BASE_EMAC AT91SAM9G45_BASE_EMAC -#define AT91_BASE_SPI AT91SAM9G45_BASE_SPI0 -#define AT91_ID_UHP AT91SAM9G45_ID_UHPHS -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP -#elif defined(CONFIG_AT91CAP9) -#include -#define AT91_BASE_SPI AT91CAP9_BASE_SPI0 -#define AT91_ID_UHP AT91CAP9_ID_UHP -#define AT91_PMC_UHP AT91CAP9_PMC_UHP -#elif defined(CONFIG_AT91X40) -#include -#else -#error "Unsupported AT91 processor" -#endif - -/* External Memory Map */ -#define AT91_CHIPSELECT_0 0x10000000 -#define AT91_CHIPSELECT_1 0x20000000 -#define AT91_CHIPSELECT_2 0x30000000 -#define AT91_CHIPSELECT_3 0x40000000 -#define AT91_CHIPSELECT_4 0x50000000 -#define AT91_CHIPSELECT_5 0x60000000 -#define AT91_CHIPSELECT_6 0x70000000 -#define AT91_CHIPSELECT_7 0x80000000 - -/* SDRAM */ -#ifdef CONFIG_DRAM_BASE -#define AT91_SDRAM_BASE CONFIG_DRAM_BASE -#else -#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 -#endif - -/* Clocks */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#endif diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h deleted file mode 100644 index 38d185e..0000000 --- a/include/asm-arm/arch-at91/io.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/io.h] - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include - -#ifdef CONFIG_AT91_LEGACY - -static inline unsigned int at91_sys_read(unsigned int reg_offset) -{ - void *addr = (void *)AT91_BASE_SYS; - - return __raw_readl(addr + reg_offset); -} - -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -{ - void *addr = (void *)AT91_BASE_SYS; - - __raw_writel(value, addr + reg_offset); -} -#endif - -#endif diff --git a/include/asm-arm/arch-at91/memory-map.h b/include/asm-arm/arch-at91/memory-map.h deleted file mode 100644 index f605f37..0000000 --- a/include/asm-arm/arch-at91/memory-map.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_MEMORYMAP_H__ -#define __ASM_ARM_ARCH_MEMORYMAP_H__ - -#include - -#define USART0_BASE AT91_USART0 -#define USART1_BASE AT91_USART1 -#define USART2_BASE AT91_USART2 -#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU) -#define SPI0_BASE AT91_BASE_SPI - -#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */ diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h deleted file mode 100644 index 00bae1c..0000000 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ /dev/null @@ -1,812 +0,0 @@ -/* - * (C) Copyright 2003 - * AT91RM9200 definitions - * Author : ATMEL AT91 application group - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef AT91RM9200_H -#define AT91RM9200_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG; /* Hardware register definition */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ -/*****************************************************************************/ -typedef struct _AT91S_TC -{ - AT91_REG TC_CCR; /* Channel Control Register */ - AT91_REG TC_CMR; /* Channel Mode Register */ - AT91_REG Reserved0[2]; /* */ - AT91_REG TC_CV; /* Counter Value */ - AT91_REG TC_RA; /* Register A */ - AT91_REG TC_RB; /* Register B */ - AT91_REG TC_RC; /* Register C */ - AT91_REG TC_SR; /* Status Register */ - AT91_REG TC_IER; /* Interrupt Enable Register */ - AT91_REG TC_IDR; /* Interrupt Disable Register */ - AT91_REG TC_IMR; /* Interrupt Mask Register */ -} AT91S_TC, *AT91PS_TC; - -#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ -#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ -#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ -#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ -#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK*/ -#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ -#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ -#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Usart */ -/*****************************************************************************/ -typedef struct _AT91S_USART -{ - AT91_REG US_CR; /* Control Register */ - AT91_REG US_MR; /* Mode Register */ - AT91_REG US_IER; /* Interrupt Enable Register */ - AT91_REG US_IDR; /* Interrupt Disable Register */ - AT91_REG US_IMR; /* Interrupt Mask Register */ - AT91_REG US_CSR; /* Channel Status Register */ - AT91_REG US_RHR; /* Receiver Holding Register */ - AT91_REG US_THR; /* Transmitter Holding Register */ - AT91_REG US_BRGR; /* Baud Rate Generator Register */ - AT91_REG US_RTOR; /* Receiver Time-out Register */ - AT91_REG US_TTGR; /* Transmitter Time-guard Register */ - AT91_REG Reserved0[5]; /* */ - AT91_REG US_FIDI; /* FI_DI_Ratio Register */ - AT91_REG US_NER; /* Nb Errors Register */ - AT91_REG US_XXR; /* XON_XOFF Register */ - AT91_REG US_IF; /* IRDA_FILTER Register */ - AT91_REG Reserved1[44]; /* */ - AT91_REG US_RPR; /* Receive Pointer Register */ - AT91_REG US_RCR; /* Receive Counter Register */ - AT91_REG US_TPR; /* Transmit Pointer Register */ - AT91_REG US_TCR; /* Transmit Counter Register */ - AT91_REG US_RNPR; /* Receive Next Pointer Register */ - AT91_REG US_RNCR; /* Receive Next Counter Register */ - AT91_REG US_TNPR; /* Transmit Next Pointer Register */ - AT91_REG US_TNCR; /* Transmit Next Counter Register */ - AT91_REG US_PTCR; /* PDC Transfer Control Register */ - AT91_REG US_PTSR; /* PDC Transfer Status Register */ -} AT91S_USART, *AT91PS_USART; - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ -/*****************************************************************************/ -typedef struct _AT91S_CKGR -{ - AT91_REG CKGR_MOR; /* Main Oscillator Register */ - AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ - AT91_REG CKGR_PLLAR; /* PLL A Register */ - AT91_REG CKGR_PLLBR; /* PLL B Register */ -} AT91S_CKGR, *AT91PS_CKGR; - -/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */ -#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */ -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */ - -/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */ -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */ - -/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */ -#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ -#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ -#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ -#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */ -#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */ -#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */ -#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */ - -/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */ -#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ -#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ -#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ -#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */ -#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */ -#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */ -#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ -#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ -/*****************************************************************************/ -typedef struct _AT91S_PIO -{ - AT91_REG PIO_PER; /* PIO Enable Register */ - AT91_REG PIO_PDR; /* PIO Disable Register */ - AT91_REG PIO_PSR; /* PIO Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PIO_OER; /* Output Enable Register */ - AT91_REG PIO_ODR; /* Output Disable Registerr */ - AT91_REG PIO_OSR; /* Output Status Register */ - AT91_REG Reserved1[1]; /* */ - AT91_REG PIO_IFER; /* Input Filter Enable Register */ - AT91_REG PIO_IFDR; /* Input Filter Disable Register */ - AT91_REG PIO_IFSR; /* Input Filter Status Register */ - AT91_REG Reserved2[1]; /* */ - AT91_REG PIO_SODR; /* Set Output Data Register */ - AT91_REG PIO_CODR; /* Clear Output Data Register */ - AT91_REG PIO_ODSR; /* Output Data Status Register */ - AT91_REG PIO_PDSR; /* Pin Data Status Register */ - AT91_REG PIO_IER; /* Interrupt Enable Register */ - AT91_REG PIO_IDR; /* Interrupt Disable Register */ - AT91_REG PIO_IMR; /* Interrupt Mask Register */ - AT91_REG PIO_ISR; /* Interrupt Status Register */ - AT91_REG PIO_MDER; /* Multi-driver Enable Register */ - AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ - AT91_REG PIO_MDSR; /* Multi-driver Status Register */ - AT91_REG Reserved3[1]; /* */ - AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ - AT91_REG PIO_PPUER; /* Pull-up Enable Register */ - AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ - AT91_REG Reserved4[1]; /* */ - AT91_REG PIO_ASR; /* Select A Register */ - AT91_REG PIO_BSR; /* Select B Register */ - AT91_REG PIO_ABSR; /* AB Select Status Register */ - AT91_REG Reserved5[9]; /* */ - AT91_REG PIO_OWER; /* Output Write Enable Register */ - AT91_REG PIO_OWDR; /* Output Write Disable Register */ - AT91_REG PIO_OWSR; /* Output Write Status Register */ -} AT91S_PIO, *AT91PS_PIO; - - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Debug Unit */ -/*****************************************************************************/ -typedef struct _AT91S_DBGU -{ - AT91_REG DBGU_CR; /* Control Register */ - AT91_REG DBGU_MR; /* Mode Register */ - AT91_REG DBGU_IER; /* Interrupt Enable Register */ - AT91_REG DBGU_IDR; /* Interrupt Disable Register */ - AT91_REG DBGU_IMR; /* Interrupt Mask Register */ - AT91_REG DBGU_CSR; /* Channel Status Register */ - AT91_REG DBGU_RHR; /* Receiver Holding Register */ - AT91_REG DBGU_THR; /* Transmitter Holding Register */ - AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ - AT91_REG Reserved0[7]; /* */ - AT91_REG DBGU_C1R; /* Chip ID1 Register */ - AT91_REG DBGU_C2R; /* Chip ID2 Register */ - AT91_REG DBGU_FNTR; /* Force NTRST Register */ - AT91_REG Reserved1[45]; /* */ - AT91_REG DBGU_RPR; /* Receive Pointer Register */ - AT91_REG DBGU_RCR; /* Receive Counter Register */ - AT91_REG DBGU_TPR; /* Transmit Pointer Register */ - AT91_REG DBGU_TCR; /* Transmit Counter Register */ - AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ - AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ - AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ - AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ - AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ - AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ -} AT91S_DBGU, *AT91PS_DBGU; - -/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */ -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */ -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */ -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */ -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */ -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */ -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */ -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */ -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */ -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */ -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */ -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */ - -/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */ -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */ -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */ -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */ -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */ -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */ - -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */ -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */ -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ -/*****************************************************************************/ -typedef struct _AT91S_SMC2 -{ - AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ -} AT91S_SMC2, *AT91PS_SMC2; - -/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ -#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */ -#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ -#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ -#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ -#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ -#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ -#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ -#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */ -#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */ -#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ -#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */ -#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */ -#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */ -#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ -#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Power Management Controler */ -/*****************************************************************************/ -typedef struct _AT91S_PMC -{ - AT91_REG PMC_SCER; /* System Clock Enable Register */ - AT91_REG PMC_SCDR; /* System Clock Disable Register */ - AT91_REG PMC_SCSR; /* System Clock Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ - AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ - AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ - AT91_REG Reserved1[5]; /* */ - AT91_REG PMC_MCKR; /* Master Clock Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ - AT91_REG PMC_IER; /* Interrupt Enable Register */ - AT91_REG PMC_IDR; /* Interrupt Disable Register */ - AT91_REG PMC_SR; /* Status Register */ - AT91_REG PMC_IMR; /* Interrupt Mask Register */ -} AT91S_PMC, *AT91PS_PMC; - -/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */ -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */ -#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */ -#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */ -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */ -/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/ -/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/ -/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/ -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */ -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */ -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */ -#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */ -#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */ -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */ -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */ -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */ -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */ -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */ -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */ -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */ -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */ -#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */ -#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */ -#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */ -#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */ -#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */ -/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/ -/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/ -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */ -#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */ -#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */ -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */ -/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/ -/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ -/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Ethernet MAC */ -/*****************************************************************************/ -typedef struct _AT91S_EMAC -{ - AT91_REG EMAC_CTL; /* Network Control Register */ - AT91_REG EMAC_CFG; /* Network Configuration Register */ - AT91_REG EMAC_SR; /* Network Status Register */ - AT91_REG EMAC_TAR; /* Transmit Address Register */ - AT91_REG EMAC_TCR; /* Transmit Control Register */ - AT91_REG EMAC_TSR; /* Transmit Status Register */ - AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ - AT91_REG Reserved0[1]; /* */ - AT91_REG EMAC_RSR; /* Receive Status Register */ - AT91_REG EMAC_ISR; /* Interrupt Status Register */ - AT91_REG EMAC_IER; /* Interrupt Enable Register */ - AT91_REG EMAC_IDR; /* Interrupt Disable Register */ - AT91_REG EMAC_IMR; /* Interrupt Mask Register */ - AT91_REG EMAC_MAN; /* PHY Maintenance Register */ - AT91_REG Reserved1[2]; /* */ - AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ - AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ - AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ - AT91_REG EMAC_OK; /* Frames Received OK Register */ - AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ - AT91_REG EMAC_ALE; /* Alignment Error Register */ - AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ - AT91_REG EMAC_LCOL; /* Late Collision Register */ - AT91_REG EMAC_ECOL; /* Excessive Collision Register */ - AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ - AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ - AT91_REG EMAC_CDE; /* Code Error Register */ - AT91_REG EMAC_ELR; /* Excessive Length Error Register */ - AT91_REG EMAC_RJB; /* Receive Jabber Register */ - AT91_REG EMAC_USF; /* Undersize Frame Register */ - AT91_REG EMAC_SQEE; /* SQE Test Error Register */ - AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ - AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ - AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ - AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ - AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ - AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ - AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ - AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ - AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ - AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ -} AT91S_EMAC, *AT91PS_EMAC; - -/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */ -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ -#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */ -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */ -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */ -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */ -#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */ -#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */ -#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */ -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */ - -/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */ -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */ -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ -#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */ -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */ -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */ -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */ -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */ -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */ -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */ -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */ -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */ -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */ -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */ -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */ -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */ - -/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */ -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ - -/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */ -#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ -#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ - -/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */ -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ -#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */ -#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */ -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */ -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */ - -/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ - -/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */ -#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ -#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */ -#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */ -#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */ -#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */ -#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */ -#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */ -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */ -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ - -/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */ -/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */ -/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ -/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */ -#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */ -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */ -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */ -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */ -#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */ -#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */ -#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ -#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ -/*****************************************************************************/ -typedef struct _AT91S_SPI -{ - AT91_REG SPI_CR; /* Control Register */ - AT91_REG SPI_MR; /* Mode Register */ - AT91_REG SPI_RDR; /* Receive Data Register */ - AT91_REG SPI_TDR; /* Transmit Data Register */ - AT91_REG SPI_SR; /* Status Register */ - AT91_REG SPI_IER; /* Interrupt Enable Register */ - AT91_REG SPI_IDR; /* Interrupt Disable Register */ - AT91_REG SPI_IMR; /* Interrupt Mask Register */ - AT91_REG Reserved0[4]; /* */ - AT91_REG SPI_CSR[4]; /* Chip Select Register */ - AT91_REG Reserved1[48]; /* */ - AT91_REG SPI_RPR; /* Receive Pointer Register */ - AT91_REG SPI_RCR; /* Receive Counter Register */ - AT91_REG SPI_TPR; /* Transmit Pointer Register */ - AT91_REG SPI_TCR; /* Transmit Counter Register */ - AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ - AT91_REG SPI_RNCR; /* Receive Next Counter Register */ - AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ - AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ - AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ - AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ -} AT91S_SPI, *AT91PS_SPI; - -/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */ -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */ -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */ - -/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */ -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */ -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */ -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */ -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */ -#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */ -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */ -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */ -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */ -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */ - -/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */ -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ - -/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */ -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ - -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */ -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */ -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */ -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */ -#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */ -#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */ -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */ -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */ -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ - -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */ -/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ -/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */ -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */ -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */ -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */ -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */ -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */ -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */ -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */ -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */ -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */ -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */ -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */ -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ -/*****************************************************************************/ -typedef struct _AT91S_PDC -{ - AT91_REG PDC_RPR; /* Receive Pointer Register */ - AT91_REG PDC_RCR; /* Receive Counter Register */ - AT91_REG PDC_TPR; /* Transmit Pointer Register */ - AT91_REG PDC_TCR; /* Transmit Counter Register */ - AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ - AT91_REG PDC_RNCR; /* Receive Next Counter Register */ - AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ - AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ - AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ - AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ -} AT91S_PDC, *AT91PS_PDC; - -/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */ -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */ -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */ -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */ -/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ - -/* ========== Register definition ==================================== */ -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */ -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */ -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */ -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */ -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */ -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */ -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */ -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */ -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */ -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */ -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */ -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */ -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */ -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */ -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */ -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */ -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */ -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */ -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */ -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */ -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */ -#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */ -#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */ -#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */ -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */ -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */ -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */ -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */ -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */ -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */ -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ - -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */ -#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */ -#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */ -#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */ -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */ -#define AT91C_PA25_TWD ((unsigned int) 1 << 25) -#define AT91C_PA26_TWCK ((unsigned int) 1 << 26) -#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */ -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */ -#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */ -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */ -#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */ -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */ -#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */ -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */ -#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */ - -#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ -#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ -#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ -#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */ -#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */ -#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */ -#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */ -#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */ -#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */ -#define AT91C_ID_UHP ((unsigned int) 23) /* OHCI USB Host Port */ -#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */ - -#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */ -#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */ -#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */ -#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */ -#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */ -#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */ -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */ - -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */ -#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */ - -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */ -#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */ -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */ -#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */ -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */ -#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */ -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */ -#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */ -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */ -#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */ -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */ -#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */ -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */ -#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */ - -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */ -#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */ -#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */ -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */ -#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */ -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */ -#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */ -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */ -#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */ -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */ -#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */ -#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */ -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */ -#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */ -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */ -#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */ -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ -#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ - -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */ -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ -#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ -#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */ -#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */ -#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */ -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */ -#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */ -#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */ -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */ -#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */ -#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */ -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */ -#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */ -#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */ -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */ -#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */ -#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */ -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */ -#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */ -#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */ -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */ -#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */ -#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */ -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */ -#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ -#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ - -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ - -#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */ -#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ -#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ -#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ -#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ -#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ -#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ -#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ - -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */ -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ -#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ -#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */ -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ -#if 0 -#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */ -#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */ -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */ -#endif - -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */ -#if 0 -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */ -#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */ -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */ -#endif -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ -#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */ -#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */ -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ - -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ -#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ -#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ -#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ -#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ -#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ -#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ -#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ - -#else -/* flash */ -#define AT91C_MC_PUIA 0xFFFFFF10 -#define AT91C_MC_PUP 0xFFFFFF50 -#define AT91C_MC_PUER 0xFFFFFF54 -#define AT91C_MC_ASR 0xFFFFFF04 -#define AT91C_MC_AASR 0xFFFFFF08 -#define AT91C_EBI_CFGR 0xFFFFFF64 -#define AT91C_SMC_CSR0 0xFFFFFF70 - -/* clocks */ -#define AT91C_PLLAR 0xFFFFFC28 -#define AT91C_PLLBR 0xFFFFFC2C -#define AT91C_MCKR 0xFFFFFC30 - -#define AT91C_BASE_CKGR 0xFFFFFC20 -#define AT91C_CKGR_MOR 0 - -/* sdram */ -#define AT91C_PIOC_ASR 0xFFFFF870 -#define AT91C_PIOC_BSR 0xFFFFF874 -#define AT91C_PIOC_PDR 0xFFFFF804 -#define AT91C_EBI_CSA 0xFFFFFF60 -#define AT91C_SDRC_CR 0xFFFFFF98 -#define AT91C_SDRC_MR 0xFFFFFF90 -#define AT91C_SDRC_TR 0xFFFFFF94 - -#endif /* __ASSEMBLY__ */ -#endif /* AT91RM9200_H */ diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h deleted file mode 100644 index b868e38..0000000 --- a/include/asm-arm/arch-at91rm9200/hardware.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * linux/include/asm-arm/arch-at91/hardware.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include - -#ifndef __ASSEMBLY__ -#include "AT91RM9200.h" -#endif - -/* Virtual and Physical base address for system peripherals */ -#define AT91_SYS_BASE 0xFFFFF000 /*4K */ - -/* Virtual and Physical base addresses of user peripherals */ -#define AT91_SPI_BASE 0xFFFE0000 /*16K */ -#define AT91_SSC2_BASE 0xFFFD8000 /*16K */ -#define AT91_SSC1_BASE 0xFFFD4000 /*16K */ -#define AT91_SSC0_BASE 0xFFFD0000 /*16K */ -#define AT91_USART3_BASE 0xFFFCC000 /*16K */ -#define AT91_USART2_BASE 0xFFFC8000 /*16K */ -#define AT91_USART1_BASE 0xFFFC4000 /*16K */ -#define AT91_USART0_BASE 0xFFFC0000 /*16K */ -#define AT91_EMAC_BASE 0xFFFBC000 /*16K */ -#define AT91_TWI_BASE 0xFFFB8000 /*16K */ -#define AT91_MCI_BASE 0xFFFB4000 /*16K */ -#define AT91_UDP_BASE 0xFFFB0000 /*16K */ -#define AT91_TCB1_BASE 0xFFFA4000 /*16K */ -#define AT91_TCB0_BASE 0xFFFA0000 /*16K */ - -#define AT91_USB_HOST_BASE 0x00300000 - -/* - * Where in virtual memory the IO devices (timers, system controllers - * and so on) - */ -#define AT91_IO_BASE 0xF0000000 /* Virt/Phys Address of IO */ - -/* FLASH */ -#define AT91_FLASH_BASE 0x10000000 /* NCS0 */ - -/* SDRAM */ -#define AT91_SDRAM_BASE 0x20000000 /* NCS1 */ - -/* SmartMedia */ -#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3 */ - -/* Definition of interrupt priority levels */ -#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST -#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1) -#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2) -#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3) -#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4) -#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5) -#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6) -#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST - -#endif diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h deleted file mode 100644 index b0ec8f5..0000000 --- a/include/asm-arm/arch-davinci/emac_defs.h +++ /dev/null @@ -1,393 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Based on: - * - * ---------------------------------------------------------------------------- - * - * dm644x_emac.h - * - * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM - * - * Copyright (C) 2005 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * ---------------------------------------------------------------------------- - - * Modifications: - * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. - * - */ - -#ifndef _DM644X_EMAC_H_ -#define _DM644X_EMAC_H_ - -#include - -#ifdef CONFIG_SOC_DM365 -#define EMAC_BASE_ADDR (0x01d07000) -#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) -#define EMAC_WRAPPER_RAM_ADDR (0x01d08000) -#define EMAC_MDIO_BASE_ADDR (0x01d0b000) -#define DAVINCI_EMAC_VERSION2 -#elif defined(CONFIG_SOC_DA8XX) -#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE -#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE -#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE -#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE -#define DAVINCI_EMAC_VERSION2 -#else -#define EMAC_BASE_ADDR (0x01c80000) -#define EMAC_WRAPPER_BASE_ADDR (0x01c81000) -#define EMAC_WRAPPER_RAM_ADDR (0x01c82000) -#define EMAC_MDIO_BASE_ADDR (0x01c84000) -#endif - -#ifdef CONFIG_SOC_DM646X -#define DAVINCI_EMAC_VERSION2 -#define DAVINCI_EMAC_GIG_ENABLE -#endif - -#ifdef CONFIG_SOC_DM646X -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 76500000 -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ -#elif defined(CONFIG_SOC_DM365) -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 121500000 -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ -#elif defined(CONFIG_SOC_DA8XX) -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID) -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ -#else -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ -#endif - -/* PHY mask - set only those phy number bits where phy is/can be connected */ -#define EMAC_MDIO_PHY_NUM 1 -#define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM) - -/* Ethernet Min/Max packet size */ -#define EMAC_MIN_ETHERNET_PKT_SIZE 60 -#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 -#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ - -/* Number of RX packet buffers - * NOTE: Only 1 buffer supported as of now - */ -#define EMAC_MAX_RX_BUFFERS 10 - - -/*********************************************** - ******** Internally used macros *************** - ***********************************************/ - -#define EMAC_CH_TX 1 -#define EMAC_CH_RX 0 - -/* Each descriptor occupies 4 words, lets start RX desc's at 0 and - * reserve space for 64 descriptors max - */ -#define EMAC_RX_DESC_BASE 0x0 -#define EMAC_TX_DESC_BASE 0x1000 - -/* EMAC Teardown value */ -#define EMAC_TEARDOWN_VALUE 0xfffffffc - -/* MII Status Register */ -#define MII_STATUS_REG 1 - -/* Number of statistics registers */ -#define EMAC_NUM_STATS 36 - - -/* EMAC Descriptor */ -typedef volatile struct _emac_desc -{ - u_int32_t next; /* Pointer to next descriptor in chain */ - u_int8_t *buffer; /* Pointer to data buffer */ - u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ - u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ -} emac_desc; - -/* CPPI bit positions */ -#define EMAC_CPPI_SOP_BIT (0x80000000) -#define EMAC_CPPI_EOP_BIT (0x40000000) -#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) -#define EMAC_CPPI_EOQ_BIT (0x10000000) -#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) -#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) - -#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) - -#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) -#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) -#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) -#define EMAC_MACCONTROL_GIGFORCE (1 << 17) -#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) - -#define EMAC_MAC_ADDR_MATCH (1 << 19) -#define EMAC_MAC_ADDR_IS_VALID (1 << 20) - -#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) -#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) - - -#define MDIO_CONTROL_IDLE (0x80000000) -#define MDIO_CONTROL_ENABLE (0x40000000) -#define MDIO_CONTROL_FAULT_ENABLE (0x40000) -#define MDIO_CONTROL_FAULT (0x80000) -#define MDIO_USERACCESS0_GO (0x80000000) -#define MDIO_USERACCESS0_WRITE_READ (0x0) -#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) -#define MDIO_USERACCESS0_ACK (0x20000000) - -/* Ethernet MAC Registers Structure */ -typedef struct { - dv_reg TXIDVER; - dv_reg TXCONTROL; - dv_reg TXTEARDOWN; - u_int8_t RSVD0[4]; - dv_reg RXIDVER; - dv_reg RXCONTROL; - dv_reg RXTEARDOWN; - u_int8_t RSVD1[100]; - dv_reg TXINTSTATRAW; - dv_reg TXINTSTATMASKED; - dv_reg TXINTMASKSET; - dv_reg TXINTMASKCLEAR; - dv_reg MACINVECTOR; - u_int8_t RSVD2[12]; - dv_reg RXINTSTATRAW; - dv_reg RXINTSTATMASKED; - dv_reg RXINTMASKSET; - dv_reg RXINTMASKCLEAR; - dv_reg MACINTSTATRAW; - dv_reg MACINTSTATMASKED; - dv_reg MACINTMASKSET; - dv_reg MACINTMASKCLEAR; - u_int8_t RSVD3[64]; - dv_reg RXMBPENABLE; - dv_reg RXUNICASTSET; - dv_reg RXUNICASTCLEAR; - dv_reg RXMAXLEN; - dv_reg RXBUFFEROFFSET; - dv_reg RXFILTERLOWTHRESH; - u_int8_t RSVD4[8]; - dv_reg RX0FLOWTHRESH; - dv_reg RX1FLOWTHRESH; - dv_reg RX2FLOWTHRESH; - dv_reg RX3FLOWTHRESH; - dv_reg RX4FLOWTHRESH; - dv_reg RX5FLOWTHRESH; - dv_reg RX6FLOWTHRESH; - dv_reg RX7FLOWTHRESH; - dv_reg RX0FREEBUFFER; - dv_reg RX1FREEBUFFER; - dv_reg RX2FREEBUFFER; - dv_reg RX3FREEBUFFER; - dv_reg RX4FREEBUFFER; - dv_reg RX5FREEBUFFER; - dv_reg RX6FREEBUFFER; - dv_reg RX7FREEBUFFER; - dv_reg MACCONTROL; - dv_reg MACSTATUS; - dv_reg EMCONTROL; - dv_reg FIFOCONTROL; - dv_reg MACCONFIG; - dv_reg SOFTRESET; - u_int8_t RSVD5[88]; - dv_reg MACSRCADDRLO; - dv_reg MACSRCADDRHI; - dv_reg MACHASH1; - dv_reg MACHASH2; - dv_reg BOFFTEST; - dv_reg TPACETEST; - dv_reg RXPAUSE; - dv_reg TXPAUSE; - u_int8_t RSVD6[16]; - dv_reg RXGOODFRAMES; - dv_reg RXBCASTFRAMES; - dv_reg RXMCASTFRAMES; - dv_reg RXPAUSEFRAMES; - dv_reg RXCRCERRORS; - dv_reg RXALIGNCODEERRORS; - dv_reg RXOVERSIZED; - dv_reg RXJABBER; - dv_reg RXUNDERSIZED; - dv_reg RXFRAGMENTS; - dv_reg RXFILTERED; - dv_reg RXQOSFILTERED; - dv_reg RXOCTETS; - dv_reg TXGOODFRAMES; - dv_reg TXBCASTFRAMES; - dv_reg TXMCASTFRAMES; - dv_reg TXPAUSEFRAMES; - dv_reg TXDEFERRED; - dv_reg TXCOLLISION; - dv_reg TXSINGLECOLL; - dv_reg TXMULTICOLL; - dv_reg TXEXCESSIVECOLL; - dv_reg TXLATECOLL; - dv_reg TXUNDERRUN; - dv_reg TXCARRIERSENSE; - dv_reg TXOCTETS; - dv_reg FRAME64; - dv_reg FRAME65T127; - dv_reg FRAME128T255; - dv_reg FRAME256T511; - dv_reg FRAME512T1023; - dv_reg FRAME1024TUP; - dv_reg NETOCTETS; - dv_reg RXSOFOVERRUNS; - dv_reg RXMOFOVERRUNS; - dv_reg RXDMAOVERRUNS; - u_int8_t RSVD7[624]; - dv_reg MACADDRLO; - dv_reg MACADDRHI; - dv_reg MACINDEX; - u_int8_t RSVD8[244]; - dv_reg TX0HDP; - dv_reg TX1HDP; - dv_reg TX2HDP; - dv_reg TX3HDP; - dv_reg TX4HDP; - dv_reg TX5HDP; - dv_reg TX6HDP; - dv_reg TX7HDP; - dv_reg RX0HDP; - dv_reg RX1HDP; - dv_reg RX2HDP; - dv_reg RX3HDP; - dv_reg RX4HDP; - dv_reg RX5HDP; - dv_reg RX6HDP; - dv_reg RX7HDP; - dv_reg TX0CP; - dv_reg TX1CP; - dv_reg TX2CP; - dv_reg TX3CP; - dv_reg TX4CP; - dv_reg TX5CP; - dv_reg TX6CP; - dv_reg TX7CP; - dv_reg RX0CP; - dv_reg RX1CP; - dv_reg RX2CP; - dv_reg RX3CP; - dv_reg RX4CP; - dv_reg RX5CP; - dv_reg RX6CP; - dv_reg RX7CP; -} emac_regs; - -/* EMAC Wrapper Registers Structure */ -typedef struct { -#ifdef DAVINCI_EMAC_VERSION2 - dv_reg idver; - dv_reg softrst; - dv_reg emctrl; - dv_reg c0rxthreshen; - dv_reg c0rxen; - dv_reg c0txen; - dv_reg c0miscen; - dv_reg c1rxthreshen; - dv_reg c1rxen; - dv_reg c1txen; - dv_reg c1miscen; - dv_reg c2rxthreshen; - dv_reg c2rxen; - dv_reg c2txen; - dv_reg c2miscen; - dv_reg c0rxthreshstat; - dv_reg c0rxstat; - dv_reg c0txstat; - dv_reg c0miscstat; - dv_reg c1rxthreshstat; - dv_reg c1rxstat; - dv_reg c1txstat; - dv_reg c1miscstat; - dv_reg c2rxthreshstat; - dv_reg c2rxstat; - dv_reg c2txstat; - dv_reg c2miscstat; - dv_reg c0rximax; - dv_reg c0tximax; - dv_reg c1rximax; - dv_reg c1tximax; - dv_reg c2rximax; - dv_reg c2tximax; -#else - u_int8_t RSVD0[4100]; - dv_reg EWCTL; - dv_reg EWINTTCNT; -#endif -} ewrap_regs; - -/* EMAC MDIO Registers Structure */ -typedef struct { - dv_reg VERSION; - dv_reg CONTROL; - dv_reg ALIVE; - dv_reg LINK; - dv_reg LINKINTRAW; - dv_reg LINKINTMASKED; - u_int8_t RSVD0[8]; - dv_reg USERINTRAW; - dv_reg USERINTMASKED; - dv_reg USERINTMASKSET; - dv_reg USERINTMASKCLEAR; - u_int8_t RSVD1[80]; - dv_reg USERACCESS0; - dv_reg USERPHYSEL0; - dv_reg USERACCESS1; - dv_reg USERPHYSEL1; -} mdio_regs; - -int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); -int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); -void davinci_eth_set_mac_addr(const u_int8_t *addr); - -typedef struct -{ - char name[64]; - int (*init)(int phy_addr); - int (*is_phy_connected)(int phy_addr); - int (*get_link_speed)(int phy_addr); - int (*auto_negotiate)(int phy_addr); -} phy_t; - -#define PHY_LXT972 (0x001378e2) -int lxt972_is_phy_connected(int phy_addr); -int lxt972_get_link_speed(int phy_addr); -int lxt972_init_phy(int phy_addr); -int lxt972_auto_negotiate(int phy_addr); - -#define PHY_DP83848 (0x20005c90) -int dp83848_is_phy_connected(int phy_addr); -int dp83848_get_link_speed(int phy_addr); -int dp83848_init_phy(int phy_addr); -int dp83848_auto_negotiate(int phy_addr); - -#endif /* _DM644X_EMAC_H_ */ diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h deleted file mode 100644 index b48ec17..0000000 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ - -#include - -struct davinci_emif_regs { - u_int32_t ercsr; - u_int32_t awccr; - u_int32_t sdbcr; - u_int32_t sdrcr; - u_int32_t ab1cr; - u_int32_t ab2cr; - u_int32_t ab3cr; - u_int32_t ab4cr; - u_int32_t sdtimr; - u_int32_t ddrsr; - u_int32_t ddrphycr; - u_int32_t ddrphysr; - u_int32_t totar; - u_int32_t totactr; - u_int32_t ddrphyid_rev; - u_int32_t sdsretr; - u_int32_t eirr; - u_int32_t eimr; - u_int32_t eimsr; - u_int32_t eimcr; - u_int32_t ioctrlr; - u_int32_t iostatr; - u_int8_t rsvd0[8]; - u_int32_t nandfcr; - u_int32_t nandfsr; - u_int8_t rsvd1[8]; - u_int32_t nandfecc[4]; - u_int8_t rsvd2[60]; - u_int32_t nand4biteccload; - u_int32_t nand4bitecc[4]; - u_int32_t nanderradd1; - u_int32_t nanderradd2; - u_int32_t nanderrval1; - u_int32_t nanderrval2; -}; - -#define davinci_emif_regs \ - ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) - -#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) -#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) - -/* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) (n << 26) -#define DAVINCI_ABCR_WSTROBE(n) (n << 20) -#define DAVINCI_ABCR_WHOLD(n) (n << 17) -#define DAVINCI_ABCR_RSETUP(n) (n << 13) -#define DAVINCI_ABCR_RSTROBE(n) (n << 7) -#define DAVINCI_ABCR_RHOLD(n) (n << 4) -#define DAVINCI_ABCR_TA(n) (n << 2) -#define DAVINCI_ABCR_ASIZE_16BIT 1 -#define DAVINCI_ABCR_ASIZE_8BIT 0 - -#endif diff --git a/include/asm-arm/arch-davinci/gpio_defs.h b/include/asm-arm/arch-davinci/gpio_defs.h deleted file mode 100644 index 1be2ac2..0000000 --- a/include/asm-arm/arch-davinci/gpio_defs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _GPIO_DEFS_H_ -#define _GPIO_DEFS_H_ - -#ifndef CONFIG_SOC_DA8XX -#define DAVINCI_GPIO_BINTEN 0x01C67008 -#define DAVINCI_GPIO_BANK01 0x01C67010 -#define DAVINCI_GPIO_BANK23 0x01C67038 -#define DAVINCI_GPIO_BANK45 0x01C67060 -#define DAVINCI_GPIO_BANK67 0x01C67088 - -#else /* CONFIG_SOC_DA8XX */ -#define DAVINCI_GPIO_BINTEN 0x01E26008 -#define DAVINCI_GPIO_BANK01 0x01E26010 -#define DAVINCI_GPIO_BANK23 0x01E26038 -#define DAVINCI_GPIO_BANK45 0x01E26060 -#define DAVINCI_GPIO_BANK67 0x01E26088 -#endif /* CONFIG_SOC_DA8XX */ - -struct davinci_gpio { - unsigned int dir; - unsigned int out_data; - unsigned int set_data; - unsigned int clr_data; - unsigned int in_data; - unsigned int set_rising; - unsigned int clr_rising; - unsigned int set_falling; - unsigned int clr_falling; - unsigned int intstat; -}; - -struct davinci_gpio_bank { - int num_gpio; - unsigned int irq_num; - unsigned int irq_mask; - unsigned long *in_use; - unsigned long base; -}; - -#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01) -#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23) -#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45) -#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67) - -#endif diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h deleted file mode 100644 index 81cc8ab..0000000 --- a/include/asm-arm/arch-davinci/hardware.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Based on: - * - * ------------------------------------------------------------------------- - * - * linux/include/asm-arm/arch-davinci/hardware.h - * - * Copyright (C) 2006 Texas Instruments. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include -#include - -#define REG(addr) (*(volatile unsigned int *)(addr)) -#define REG_P(addr) ((volatile unsigned int *)(addr)) - -typedef volatile unsigned int dv_reg; -typedef volatile unsigned int * dv_reg_p; - -/* - * Base register addresses - * - * NOTE: some of these DM6446-specific addresses DO NOT WORK - * on other DaVinci chips. Double check them before you try - * using the addresses ... or PSC module identifiers, etc. - */ -#ifndef CONFIG_SOC_DA8XX - -#define DAVINCI_DMA_3PCC_BASE (0x01c00000) -#define DAVINCI_DMA_3PTC0_BASE (0x01c10000) -#define DAVINCI_DMA_3PTC1_BASE (0x01c10400) -#define DAVINCI_UART0_BASE (0x01c20000) -#define DAVINCI_UART1_BASE (0x01c20400) -#define DAVINCI_I2C_BASE (0x01c21000) -#define DAVINCI_TIMER0_BASE (0x01c21400) -#define DAVINCI_TIMER1_BASE (0x01c21800) -#define DAVINCI_WDOG_BASE (0x01c21c00) -#define DAVINCI_PWM0_BASE (0x01c22000) -#define DAVINCI_PWM1_BASE (0x01c22400) -#define DAVINCI_PWM2_BASE (0x01c22800) -#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) -#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) -#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000) -#define DAVINCI_ARM_INTC_BASE (0x01c48000) -#define DAVINCI_USB_OTG_BASE (0x01c64000) -#define DAVINCI_CFC_ATA_BASE (0x01c66000) -#define DAVINCI_SPI_BASE (0x01c66800) -#define DAVINCI_GPIO_BASE (0x01c67000) -#define DAVINCI_VPSS_REGS_BASE (0x01c70000) -#if !defined(CONFIG_SOC_DM646X) -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) -#endif -#define DAVINCI_DDR_BASE (0x80000000) - -#ifdef CONFIG_SOC_DM644X -#define DAVINCI_UART2_BASE 0x01c20800 -#define DAVINCI_UHPI_BASE 0x01c67800 -#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000 -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000 -#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000 -#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000 -#define DAVINCI_IMCOP_BASE 0x01cc0000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000 -#define DAVINCI_VLYNQ_BASE 0x01e01000 -#define DAVINCI_ASP_BASE 0x01e02000 -#define DAVINCI_MMC_SD_BASE 0x01e10000 -#define DAVINCI_MS_BASE 0x01e20000 -#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000 - -#elif defined(CONFIG_SOC_DM355) -#define DAVINCI_MMC_SD1_BASE 0x01e00000 -#define DAVINCI_ASP0_BASE 0x01e02000 -#define DAVINCI_ASP1_BASE 0x01e04000 -#define DAVINCI_UART2_BASE 0x01e06000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000 -#define DAVINCI_MMC_SD0_BASE 0x01e11000 - -#elif defined(CONFIG_SOC_DM365) -#define DAVINCI_MMC_SD1_BASE 0x01d00000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 -#define DAVINCI_MMC_SD0_BASE 0x01d11000 - -#elif defined(CONFIG_SOC_DM646X) -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 - -#endif - -#else /* CONFIG_SOC_DA8XX */ - -#define DAVINCI_UART0_BASE 0x01c42000 -#define DAVINCI_UART1_BASE 0x01d0c000 -#define DAVINCI_UART2_BASE 0x01d0d000 -#define DAVINCI_I2C0_BASE 0x01c22000 -#define DAVINCI_I2C1_BASE 0x01e28000 -#define DAVINCI_TIMER0_BASE 0x01c20000 -#define DAVINCI_TIMER1_BASE 0x01c21000 -#define DAVINCI_WDOG_BASE 0x01c21000 -#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000 -#define DAVINCI_PSC0_BASE 0x01c10000 -#define DAVINCI_PSC1_BASE 0x01e27000 -#define DAVINCI_SPI0_BASE 0x01c41000 -#define DAVINCI_USB_OTG_BASE 0x01e00000 -#define DAVINCI_SPI1_BASE 0x01e12000 -#define DAVINCI_GPIO_BASE 0x01e26000 -#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000 -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 -#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000 -#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000 -#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000 -#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 -#define DAVINCI_INTC_BASE 0xfffee000 -#define DAVINCI_BOOTCFG_BASE 0x01c14000 - -#endif /* CONFIG_SOC_DA8XX */ - -/* Power and Sleep Controller (PSC) Domains */ -#define DAVINCI_GPSC_ARMDOMAIN 0 -#define DAVINCI_GPSC_DSPDOMAIN 1 - -#ifndef CONFIG_SOC_DA8XX - -#define DAVINCI_LPSC_VPSSMSTR 0 -#define DAVINCI_LPSC_VPSSSLV 1 -#define DAVINCI_LPSC_TPCC 2 -#define DAVINCI_LPSC_TPTC0 3 -#define DAVINCI_LPSC_TPTC1 4 -#define DAVINCI_LPSC_EMAC 5 -#define DAVINCI_LPSC_EMAC_WRAPPER 6 -#define DAVINCI_LPSC_MDIO 7 -#define DAVINCI_LPSC_IEEE1394 8 -#define DAVINCI_LPSC_USB 9 -#define DAVINCI_LPSC_ATA 10 -#define DAVINCI_LPSC_VLYNQ 11 -#define DAVINCI_LPSC_UHPI 12 -#define DAVINCI_LPSC_DDR_EMIF 13 -#define DAVINCI_LPSC_AEMIF 14 -#define DAVINCI_LPSC_MMC_SD 15 -#define DAVINCI_LPSC_MEMSTICK 16 -#define DAVINCI_LPSC_McBSP 17 -#define DAVINCI_LPSC_I2C 18 -#define DAVINCI_LPSC_UART0 19 -#define DAVINCI_LPSC_UART1 20 -#define DAVINCI_LPSC_UART2 21 -#define DAVINCI_LPSC_SPI 22 -#define DAVINCI_LPSC_PWM0 23 -#define DAVINCI_LPSC_PWM1 24 -#define DAVINCI_LPSC_PWM2 25 -#define DAVINCI_LPSC_GPIO 26 -#define DAVINCI_LPSC_TIMER0 27 -#define DAVINCI_LPSC_TIMER1 28 -#define DAVINCI_LPSC_TIMER2 29 -#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 -#define DAVINCI_LPSC_ARM 31 -#define DAVINCI_LPSC_SCR2 32 -#define DAVINCI_LPSC_SCR3 33 -#define DAVINCI_LPSC_SCR4 34 -#define DAVINCI_LPSC_CROSSBAR 35 -#define DAVINCI_LPSC_CFG27 36 -#define DAVINCI_LPSC_CFG3 37 -#define DAVINCI_LPSC_CFG5 38 -#define DAVINCI_LPSC_GEM 39 -#define DAVINCI_LPSC_IMCOP 40 - -#define DAVINCI_DM646X_LPSC_EMAC 14 -#define DAVINCI_DM646X_LPSC_UART0 26 -#define DAVINCI_DM646X_LPSC_I2C 31 - -#else /* CONFIG_SOC_DA8XX */ - -enum davinci_lpsc_ids { - DAVINCI_LPSC_TPCC = 0, - DAVINCI_LPSC_TPTC0, - DAVINCI_LPSC_TPTC1, - DAVINCI_LPSC_AEMIF, - DAVINCI_LPSC_SPI0, - DAVINCI_LPSC_MMC_SD, - DAVINCI_LPSC_AINTC, - DAVINCI_LPSC_ARM_RAM_ROM, - DAVINCI_LPSC_SECCTL_KEYMGR, - DAVINCI_LPSC_UART0, - DAVINCI_LPSC_SCR0, - DAVINCI_LPSC_SCR1, - DAVINCI_LPSC_SCR2, - DAVINCI_LPSC_DMAX, - DAVINCI_LPSC_ARM, - DAVINCI_LPSC_GEM, - /* for LPSCs in PSC1, offset from 32 for differentiation */ - DAVINCI_LPSC_PSC1_BASE = 32, - DAVINCI_LPSC_USB11, - DAVINCI_LPSC_USB20, - DAVINCI_LPSC_GPIO, - DAVINCI_LPSC_UHPI, - DAVINCI_LPSC_EMAC, - DAVINCI_LPSC_DDR_EMIF, - DAVINCI_LPSC_McASP0, - DAVINCI_LPSC_McASP1, - DAVINCI_LPSC_McASP2, - DAVINCI_LPSC_SPI1, - DAVINCI_LPSC_I2C1, - DAVINCI_LPSC_UART1, - DAVINCI_LPSC_UART2, - DAVINCI_LPSC_LCDC, - DAVINCI_LPSC_ePWM, - DAVINCI_LPSC_eCAP, - DAVINCI_LPSC_eQEP, - DAVINCI_LPSC_SCR_P0, - DAVINCI_LPSC_SCR_P1, - DAVINCI_LPSC_CR_P3, - DAVINCI_LPSC_L3_CBA_RAM -}; - -#endif /* CONFIG_SOC_DA8XX */ - -void lpsc_on(unsigned int id); -void dsp_on(void); - -void davinci_enable_uart0(void); -void davinci_enable_emac(void); -void davinci_enable_i2c(void); -void davinci_errata_workarounds(void); - -#ifndef CONFIG_SOC_DA8XX - -/* Some PSC defines */ -#define PSC_CHP_SHRTSW (0x01c40038) -#define PSC_GBLCTL (0x01c41010) -#define PSC_EPCPR (0x01c41070) -#define PSC_EPCCR (0x01c41078) -#define PSC_PTCMD (0x01c41120) -#define PSC_PTSTAT (0x01c41128) -#define PSC_PDSTAT (0x01c41200) -#define PSC_PDSTAT1 (0x01c41204) -#define PSC_PDCTL (0x01c41300) -#define PSC_PDCTL1 (0x01c41304) - -#define PSC_MDCTL_BASE (0x01c41a00) -#define PSC_MDSTAT_BASE (0x01c41800) - -#define VDD3P3V_PWDN (0x01c40048) -#define UART0_PWREMU_MGMT (0x01c20030) - -#define PSC_SILVER_BULLET (0x01c41a20) - -#else /* CONFIG_SOC_DA8XX */ - -#define PSC_PSC0_MODULE_ID_CNT 16 -#define PSC_PSC1_MODULE_ID_CNT 32 - -struct davinci_psc_regs { - dv_reg revid; - dv_reg rsvd0[71]; - dv_reg ptcmd; - dv_reg rsvd1; - dv_reg ptstat; - dv_reg rsvd2[437]; - union { - struct { - dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT]; - dv_reg rsvd3[112]; - dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT]; - } psc0; - struct { - dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT]; - dv_reg rsvd3[96]; - dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT]; - } psc1; - }; -}; - -#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE) -#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE) - -#endif /* CONFIG_SOC_DA8XX */ - -#ifndef CONFIG_SOC_DA8XX - -/* Miscellania... */ -#define VBPR (0x20000020) - -/* NOTE: system control modules are *highly* chip-specific, both - * as to register content (e.g. for muxing) and which registers exist. - */ -#define PINMUX0 0x01c40000 -#define PINMUX1 0x01c40004 -#define PINMUX2 0x01c40008 -#define PINMUX3 0x01c4000c -#define PINMUX4 0x01c40010 - -#else /* CONFIG_SOC_DA8XX */ - -struct davinci_pllc_regs { - dv_reg revid; - dv_reg rsvd1[56]; - dv_reg rstype; - dv_reg rsvd2[6]; - dv_reg pllctl; - dv_reg ocsel; - dv_reg rsvd3[2]; - dv_reg pllm; - dv_reg prediv; - dv_reg plldiv1; - dv_reg plldiv2; - dv_reg plldiv3; - dv_reg oscdiv; - dv_reg postdiv; - dv_reg rsvd4[3]; - dv_reg pllcmd; - dv_reg pllstat; - dv_reg alnctl; - dv_reg dchange; - dv_reg cken; - dv_reg ckstat; - dv_reg systat; - dv_reg rsvd5[3]; - dv_reg plldiv4; - dv_reg plldiv5; - dv_reg plldiv6; - dv_reg plldiv7; - dv_reg rsvd6[32]; - dv_reg emucnt0; - dv_reg emucnt1; -}; - -#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) -#define DAVINCI_PLLC_DIV_MASK 0x1f - -/* Clock IDs */ -enum davinci_clk_ids { - DAVINCI_SPI0_CLKID = 2, - DAVINCI_UART2_CLKID = 2, - DAVINCI_MDIO_CLKID = 4, - DAVINCI_ARM_CLKID = 6, - DAVINCI_PLLM_CLKID = 0xff, - DAVINCI_PLLC_CLKID = 0x100, - DAVINCI_AUXCLK_CLKID = 0x101 -}; - -int clk_get(enum davinci_clk_ids id); - -/* Boot config */ -struct davinci_syscfg_regs { - dv_reg revid; - dv_reg rsvd[71]; - dv_reg pinmux[20]; - dv_reg suspsrc; - dv_reg chipsig; - dv_reg chipsig_clr; - dv_reg cfgchip0; - dv_reg cfgchip1; - dv_reg cfgchip2; - dv_reg cfgchip3; - dv_reg cfgchip4; -}; - -#define davinci_syscfg_regs \ - ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE) - -/* Emulation suspend bits */ -#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5) -#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16) -#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) -#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) -#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) - -/* Interrupt controller */ -struct davinci_aintc_regs { - dv_reg revid; - dv_reg cr; - dv_reg dummy0[2]; - dv_reg ger; - dv_reg dummy1[219]; - dv_reg ecr1; - dv_reg ecr2; - dv_reg ecr3; - dv_reg dummy2[1117]; - dv_reg hier; -}; - -#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE) - -struct davinci_uart_ctrl_regs { - dv_reg revid1; - dv_reg revid2; - dv_reg pwremu_mgmt; - dv_reg mdr; -}; - -#define DAVINCI_UART_CTRL_BASE 0x28 -#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE) -#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE) -#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE) - -#define davinci_uart0_ctrl_regs \ - ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR) -#define davinci_uart1_ctrl_regs \ - ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR) -#define davinci_uart2_ctrl_regs \ - ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR) - -/* UART PWREMU_MGMT definitions */ -#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) -#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) -#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) - -#endif /* CONFIG_SOC_DA8XX */ - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/i2c_defs.h b/include/asm-arm/arch-davinci/i2c_defs.h deleted file mode 100644 index 24cd268..0000000 --- a/include/asm-arm/arch-davinci/i2c_defs.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * - * Some changes copyright (C) 2007 Sergey Kubushyn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _DAVINCI_I2C_H_ -#define _DAVINCI_I2C_H_ - -#define I2C_WRITE 0 -#define I2C_READ 1 - -#ifndef CONFIG_SOC_DA8XX -#define I2C_BASE 0x01c21000 -#else -#define I2C_BASE 0x01c22000 -#endif - -#define I2C_OA (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_SCLL (I2C_BASE + 0x0c) -#define I2C_SCLH (I2C_BASE + 0x10) -#define I2C_CNT (I2C_BASE + 0x14) -#define I2C_DRR (I2C_BASE + 0x18) -#define I2C_SA (I2C_BASE + 0x1c) -#define I2C_DXR (I2C_BASE + 0x20) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_IV (I2C_BASE + 0x28) -#define I2C_PSC (I2C_BASE + 0x30) - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ -#define I2C_INTCODE_SCD 6 /* Stop condition detect */ - - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 5) /* I2C module enable */ -#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ -#define I2C_CON_FREE (1 << 14) /* Free run on emulation */ - -#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ - -#endif diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h deleted file mode 100644 index 10f3a39..0000000 --- a/include/asm-arm/arch-davinci/nand_defs.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Parts shamelesly stolen from Linux Kernel source tree. - * - * ------------------------------------------------------------ - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include - -#ifdef CONFIG_SOC_DM646X -#define MASK_CLE 0x80000 -#define MASK_ALE 0x40000 -#else -#define MASK_CLE 0x10 -#define MASK_ALE 0x08 -#endif - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/include/asm-arm/arch-ep93xx/ep93xx.h b/include/asm-arm/arch-ep93xx/ep93xx.h deleted file mode 100644 index 806557a..0000000 --- a/include/asm-arm/arch-ep93xx/ep93xx.h +++ /dev/null @@ -1,596 +0,0 @@ -/* - * Cirrus Logic EP93xx register definitions. - * - * Copyright (C) 2009 - * Matthias Kaehlcke - * - * Copyright (C) 2006 - * Dominic Rath - * - * Copyright (C) 2004, 2005 - * Cory T. Tusar, Videon Central, Inc., - * - * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is - * - * Copyright (C) 2004 Ray Lehtiniemi - * Copyright (C) 2003 Cirrus Logic, Inc - * Copyright (C) 1999 ARM Limited. - * - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#define EP93XX_AHB_BASE 0x80000000 -#define EP93XX_APB_BASE 0x80800000 - -/* - * 0x80000000 - 0x8000FFFF: DMA - */ -#define DMA_OFFSET 0x000000 -#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET) - -#ifndef __ASSEMBLY__ -struct dma_channel { - uint32_t control; - uint32_t interrupt; - uint32_t ppalloc; - uint32_t status; - uint32_t reserved0; - uint32_t remain; - uint32_t reserved1[2]; - uint32_t maxcnt0; - uint32_t base0; - uint32_t current0; - uint32_t reserved2; - uint32_t maxcnt1; - uint32_t base1; - uint32_t current1; - uint32_t reserved3; -}; - -struct dma_regs { - struct dma_channel m2p_channel_0; - struct dma_channel m2p_channel_1; - struct dma_channel m2p_channel_2; - struct dma_channel m2p_channel_3; - struct dma_channel m2m_channel_0; - struct dma_channel m2m_channel_1; - struct dma_channel reserved0[2]; - struct dma_channel m2p_channel_5; - struct dma_channel m2p_channel_4; - struct dma_channel m2p_channel_7; - struct dma_channel m2p_channel_6; - struct dma_channel m2p_channel_9; - struct dma_channel m2p_channel_8; - uint32_t channel_arbitration; - uint32_t reserved[15]; - uint32_t global_interrupt; -}; -#endif - -/* - * 0x80010000 - 0x8001FFFF: Ethernet MAC - */ -#define MAC_OFFSET 0x010000 -#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET) - -#ifndef __ASSEMBLY__ -struct mac_queue { - uint32_t badd; - union { /* deal with half-word aligned registers */ - uint32_t blen; - union { - uint16_t filler; - uint16_t curlen; - }; - }; - uint32_t curadd; -}; - -struct mac_regs { - uint32_t rxctl; - uint32_t txctl; - uint32_t testctl; - uint32_t reserved0; - uint32_t miicmd; - uint32_t miidata; - uint32_t miists; - uint32_t reserved1; - uint32_t selfctl; - uint32_t inten; - uint32_t intstsp; - uint32_t intstsc; - uint32_t reserved2[2]; - uint32_t diagad; - uint32_t diagdata; - uint32_t gt; - uint32_t fct; - uint32_t fcf; - uint32_t afp; - union { - struct { - uint32_t indad; - uint32_t indad_upper; - }; - uint32_t hashtbl; - }; - uint32_t reserved3[2]; - uint32_t giintsts; - uint32_t giintmsk; - uint32_t giintrosts; - uint32_t giintfrc; - uint32_t txcollcnt; - uint32_t rxmissnct; - uint32_t rxruntcnt; - uint32_t reserved4; - uint32_t bmctl; - uint32_t bmsts; - uint32_t rxbca; - uint32_t reserved5; - struct mac_queue rxdq; - uint32_t rxdqenq; - struct mac_queue rxstsq; - uint32_t rxstsqenq; - struct mac_queue txdq; - uint32_t txdqenq; - struct mac_queue txstsq; - uint32_t reserved6; - uint32_t rxbufthrshld; - uint32_t txbufthrshld; - uint32_t rxststhrshld; - uint32_t txststhrshld; - uint32_t rxdthrshld; - uint32_t txdthrshld; - uint32_t maxfrmlen; - uint32_t maxhdrlen; -}; -#endif - -#define SELFCTL_RWP (1 << 7) -#define SELFCTL_GPO0 (1 << 5) -#define SELFCTL_PUWE (1 << 4) -#define SELFCTL_PDWE (1 << 3) -#define SELFCTL_MIIL (1 << 2) -#define SELFCTL_RESET (1 << 0) - -#define INTSTS_RWI (1 << 30) -#define INTSTS_RXMI (1 << 29) -#define INTSTS_RXBI (1 << 28) -#define INTSTS_RXSQI (1 << 27) -#define INTSTS_TXLEI (1 << 26) -#define INTSTS_ECIE (1 << 25) -#define INTSTS_TXUHI (1 << 24) -#define INTSTS_MOI (1 << 18) -#define INTSTS_TXCOI (1 << 17) -#define INTSTS_RXROI (1 << 16) -#define INTSTS_MIII (1 << 12) -#define INTSTS_PHYI (1 << 11) -#define INTSTS_TI (1 << 10) -#define INTSTS_AHBE (1 << 8) -#define INTSTS_OTHER (1 << 4) -#define INTSTS_TXSQ (1 << 3) -#define INTSTS_RXSQ (1 << 2) - -#define BMCTL_MT (1 << 13) -#define BMCTL_TT (1 << 12) -#define BMCTL_UNH (1 << 11) -#define BMCTL_TXCHR (1 << 10) -#define BMCTL_TXDIS (1 << 9) -#define BMCTL_TXEN (1 << 8) -#define BMCTL_EH2 (1 << 6) -#define BMCTL_EH1 (1 << 5) -#define BMCTL_EEOB (1 << 4) -#define BMCTL_RXCHR (1 << 2) -#define BMCTL_RXDIS (1 << 1) -#define BMCTL_RXEN (1 << 0) - -#define BMSTS_TXACT (1 << 7) -#define BMSTS_TP (1 << 4) -#define BMSTS_RXACT (1 << 3) -#define BMSTS_QID_MASK 0x07 -#define BMSTS_QID_RXDATA 0x00 -#define BMSTS_QID_TXDATA 0x01 -#define BMSTS_QID_RXSTS 0x02 -#define BMSTS_QID_TXSTS 0x03 -#define BMSTS_QID_RXDESC 0x04 -#define BMSTS_QID_TXDESC 0x05 - -#define AFP_MASK 0x07 -#define AFP_IAPRIMARY 0x00 -#define AFP_IASECONDARY1 0x01 -#define AFP_IASECONDARY2 0x02 -#define AFP_IASECONDARY3 0x03 -#define AFP_TX 0x06 -#define AFP_HASH 0x07 - -#define RXCTL_PAUSEA (1 << 20) -#define RXCTL_RXFCE1 (1 << 19) -#define RXCTL_RXFCE0 (1 << 18) -#define RXCTL_BCRC (1 << 17) -#define RXCTL_SRXON (1 << 16) -#define RXCTL_RCRCA (1 << 13) -#define RXCTL_RA (1 << 12) -#define RXCTL_PA (1 << 11) -#define RXCTL_BA (1 << 10) -#define RXCTL_MA (1 << 9) -#define RXCTL_IAHA (1 << 8) -#define RXCTL_IA3 (1 << 3) -#define RXCTL_IA2 (1 << 2) -#define RXCTL_IA1 (1 << 1) -#define RXCTL_IA0 (1 << 0) - -#define TXCTL_DEFDIS (1 << 7) -#define TXCTL_MBE (1 << 6) -#define TXCTL_ICRC (1 << 5) -#define TXCTL_TPD (1 << 4) -#define TXCTL_OCOLL (1 << 3) -#define TXCTL_SP (1 << 2) -#define TXCTL_PB (1 << 1) -#define TXCTL_STXON (1 << 0) - -#define MIICMD_REGAD_MASK (0x001F) -#define MIICMD_PHYAD_MASK (0x03E0) -#define MIICMD_OPCODE_MASK (0xC000) -#define MIICMD_PHYAD_8950 (0x0000) -#define MIICMD_OPCODE_READ (0x8000) -#define MIICMD_OPCODE_WRITE (0x4000) - -#define MIISTS_BUSY (1 << 0) - -/* - * 0x80020000 - 0x8002FFFF: USB OHCI - */ -#define USB_OFFSET 0x020000 -#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET) - -/* - * 0x80030000 - 0x8003FFFF: Raster engine - */ -#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315)) -#define RASTER_OFFSET 0x030000 -#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET) -#endif - -/* - * 0x80040000 - 0x8004FFFF: Graphics accelerator - */ -#if defined(CONFIG_EP9315) -#define GFX_OFFSET 0x040000 -#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET) -#endif - -/* - * 0x80050000 - 0x8005FFFF: Reserved - */ - -/* - * 0x80060000 - 0x8006FFFF: SDRAM controller - */ -#define SDRAM_OFFSET 0x060000 -#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET) - -#ifndef __ASSEMBLY__ -struct sdram_regs { - uint32_t reserved; - uint32_t glconfig; - uint32_t refrshtimr; - uint32_t bootsts; - uint32_t devcfg0; - uint32_t devcfg1; - uint32_t devcfg2; - uint32_t devcfg3; -}; -#endif - -#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2) -#define SDRAM_DEVCFG_BANKCOUNT (1 << 3) -#define SDRAM_DEVCFG_SROMLL (1 << 5) -#define SDRAM_DEVCFG_CASLAT_2 0x00010000 -#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 - -#define GLCONFIG_INIT (1 << 0) -#define GLCONFIG_MRS (1 << 1) -#define GLCONFIG_SMEMBUSY (1 << 5) -#define GLCONFIG_LCR (1 << 6) -#define GLCONFIG_REARBEN (1 << 7) -#define GLCONFIG_CLKSHUTDOWN (1 << 30) -#define GLCONFIG_CKE (1 << 31) - -/* - * 0x80070000 - 0x8007FFFF: Reserved - */ - -/* - * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA - */ -#define SMC_OFFSET 0x080000 -#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET) - -#ifndef __ASSEMBLY__ -struct smc_regs { - uint32_t bcr0; - uint32_t bcr1; - uint32_t bcr2; - uint32_t bcr3; - uint32_t reserved0[2]; - uint32_t bcr6; - uint32_t bcr7; -#if defined(CONFIG_EP9315) - uint32_t pcattribute; - uint32_t pccommon; - uint32_t pcio; - uint32_t reserved1[5]; - uint32_t pcmciactrl; -#endif -}; -#endif - -#define SMC_BCR_IDCY_SHIFT 0 -#define SMC_BCR_WST1_SHIFT 5 -#define SMC_BCR_BLE (1 << 10) -#define SMC_BCR_WST2_SHIFT 11 -#define SMC_BCR_MW_SHIFT 28 - -/* - * 0x80090000 - 0x8009FFFF: Boot ROM - */ - -/* - * 0x800A0000 - 0x800AFFFF: IDE interface - */ - -/* - * 0x800B0000 - 0x800BFFFF: VIC1 - */ - -/* - * 0x800C0000 - 0x800CFFFF: VIC2 - */ - -/* - * 0x800D0000 - 0x800FFFFF: Reserved - */ - -/* - * 0x80800000 - 0x8080FFFF: Reserved - */ - -/* - * 0x80810000 - 0x8081FFFF: Timers - */ -#define TIMER_OFFSET 0x010000 -#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET) - -#ifndef __ASSEMBLY__ -struct timer { - uint32_t load; - uint32_t value; - uint32_t control; - uint32_t clear; -}; - -struct timer4 { - uint32_t value_low; - uint32_t value_high; -}; - -struct timer_regs { - struct timer timer1; - uint32_t reserved0[4]; - struct timer timer2; - uint32_t reserved1[12]; - struct timer4 timer4; - uint32_t reserved2[6]; - struct timer timer3; -}; -#endif - -/* - * 0x80820000 - 0x8082FFFF: I2S - */ -#define I2S_OFFSET 0x020000 -#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET) - -/* - * 0x80830000 - 0x8083FFFF: Security - */ -#define SECURITY_OFFSET 0x030000 -#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET) - -#define EXTENSIONID (SECURITY_BASE + 0x2714) - -/* - * 0x80840000 - 0x8084FFFF: GPIO - */ -#define GPIO_OFFSET 0x040000 -#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET) - -#ifndef __ASSEMBLY__ -struct gpio_int { - uint32_t inttype1; - uint32_t inttype2; - uint32_t eoi; - uint32_t inten; - uint32_t intsts; - uint32_t rawintsts; - uint32_t db; -}; - -struct gpio_regs { - uint32_t padr; - uint32_t pbdr; - uint32_t pcdr; - uint32_t pddr; - uint32_t paddr; - uint32_t pbddr; - uint32_t pcddr; - uint32_t pdddr; - uint32_t pedr; - uint32_t peddr; - uint32_t reserved0[2]; - uint32_t pfdr; - uint32_t pfddr; - uint32_t pgdr; - uint32_t pgddr; - uint32_t phdr; - uint32_t phddr; - uint32_t reserved1; - uint32_t finttype1; - uint32_t finttype2; - uint32_t reserved2; - struct gpio_int pfint; - uint32_t reserved3[10]; - struct gpio_int paint; - struct gpio_int pbint; - uint32_t eedrive; -}; -#endif - -/* - * 0x80850000 - 0x8087FFFF: Reserved - */ - -/* - * 0x80880000 - 0x8088FFFF: AAC - */ -#define AAC_OFFSET 0x080000 -#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET) - -/* - * 0x80890000 - 0x8089FFFF: Reserved - */ - -/* - * 0x808A0000 - 0x808AFFFF: SPI - */ -#define SPI_OFFSET 0x0A0000 -#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET) - -/* - * 0x808B0000 - 0x808BFFFF: IrDA - */ -#define IRDA_OFFSET 0x0B0000 -#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET) - -/* - * 0x808C0000 - 0x808CFFFF: UART1 - */ -#define UART1_OFFSET 0x0C0000 -#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET) - -/* - * 0x808D0000 - 0x808DFFFF: UART2 - */ -#define UART2_OFFSET 0x0D0000 -#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET) - -/* - * 0x808E0000 - 0x808EFFFF: UART3 - */ -#define UART3_OFFSET 0x0E0000 -#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET) - -/* - * 0x808F0000 - 0x808FFFFF: Key Matrix - */ -#define KEY_OFFSET 0x0F0000 -#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET) - -/* - * 0x80900000 - 0x8090FFFF: Touchscreen - */ -#define TOUCH_OFFSET 0x900000 -#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET) - -/* - * 0x80910000 - 0x8091FFFF: Pulse Width Modulation - */ -#define PWM_OFFSET 0x910000 -#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET) - -/* - * 0x80920000 - 0x8092FFFF: Real time clock - */ -#define RTC_OFFSET 0x920000 -#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET) - -/* - * 0x80930000 - 0x8093FFFF: Syscon - */ -#define SYSCON_OFFSET 0x930000 -#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) - -#ifndef __ASSEMBLY__ -struct syscon_regs { - uint32_t pwrsts; - uint32_t pwrcnt; - uint32_t halt; - uint32_t stby; - uint32_t reserved0[2]; - uint32_t teoi; - uint32_t stfclr; - uint32_t clkset1; - uint32_t clkset2; - uint32_t reserved1[6]; - uint32_t scratch0; - uint32_t scratch1; - uint32_t reserved2[2]; - uint32_t apbwait; - uint32_t bustmstrarb; - uint32_t bootmodeclr; - uint32_t reserved3[9]; - uint32_t devicecfg; - uint32_t vidclkdiv; - uint32_t mirclkdiv; - uint32_t i2sclkdiv; - uint32_t keytchclkdiv; - uint32_t chipid; - uint32_t reserved4; - uint32_t syscfg; - uint32_t reserved5[8]; - uint32_t sysswlock; -}; -#else -#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040) -#endif - -#define SYSCON_PWRCNT_UART_BAUD (1 << 29) - -#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 -#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 -#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11 -#define SYSCON_CLKSET_PLL_PS_SHIFT 16 -#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18 -#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20 -#define SYSCON_CLKSET1_NBYP1 (1 << 23) -#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25 - -#define SYSCON_CLKSET2_PLL2_EN (1 << 18) -#define SYSCON_CLKSET2_NBYP2 (1 << 19) -#define SYSCON_CLKSET2_USB_DIV_SHIFT 28 - -#define SYSCON_CHIPID_REV_MASK 0xF0000000 -#define SYSCON_DEVICECFG_SWRST (1 << 31) - -/* - * 0x80930000 - 0x8093FFFF: Watchdog Timer - */ -#define WATCHDOG_OFFSET 0x940000 -#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET) - -/* - * 0x80950000 - 0x9000FFFF: Reserved - */ diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h deleted file mode 100644 index ec94ba9..0000000 --- a/include/asm-arm/arch-imx/imx-regs.h +++ /dev/null @@ -1,634 +0,0 @@ -#ifndef _IMX_REGS_H -#define _IMX_REGS_H -/* ------------------------------------------------------------------------ - * Motorola IMX system registers - * ------------------------------------------------------------------------ - * - */ - -#define IO_ADDRESS(x) ((x) | IMX_IO_BASE) - -# ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# define __REG2(x,y) ((x)+(y)) -#endif - -#define IMX_IO_BASE 0x00200000 - -/* - * Register BASEs, based on OFFSETs - * - */ -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) -#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) -#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) -#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) -#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) -#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) -#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) -#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) -#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) -#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) -#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) -#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) -#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) -#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) -#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) -#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) -#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) -#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) -#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) -#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) -#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) - -/* Watchdog Registers*/ - -#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ -#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */ -#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */ - -/* SYSCTRL Registers */ -#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */ -#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */ -#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */ - -/* Chip Select Registers */ -#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */ -#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */ -#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */ -#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */ -#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ -#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ -#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ -#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */ -#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ -#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ -#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ -#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */ -#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ - -/* SDRAM controller registers */ - -#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */ -#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */ -#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */ -#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */ - -/* PLL registers */ -#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ -#define CSCR_SPLL_RESTART (1<<22) -#define CSCR_MPLL_RESTART (1<<21) -#define CSCR_SYSTEM_SEL (1<<16) -#define CSCR_BCLK_DIV (0xf<<10) -#define CSCR_MPU_PRESC (1<<15) -#define CSCR_SPEN (1<<1) -#define CSCR_MPEN (1<<0) - -#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ -#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ -#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ - -/* - * GPIO Module and I/O Multiplexer - * x = 0..3 for reg_A, reg_B, reg_C, reg_D - */ -#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) -#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) -#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) -#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) -#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) -#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) -#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) -#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) -#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) -#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) -#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) -#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) -#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) -#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) -#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) -#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) -#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) - -#define GPIO_PORT_MAX 3 - -#define GPIO_PIN_MASK 0x1f -#define GPIO_PORT_MASK (0x3 << 5) - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORTA (0<<5) -#define GPIO_PORTB (1<<5) -#define GPIO_PORTC (2<<5) -#define GPIO_PORTD (3<<5) - -#define GPIO_OUT (1<<7) -#define GPIO_IN (0<<7) -#define GPIO_PUEN (1<<8) - -#define GPIO_PF (0<<9) -#define GPIO_AF (1<<9) - -#define GPIO_OCR_SHIFT 10 -#define GPIO_OCR_MASK (3<<10) -#define GPIO_AIN (0<<10) -#define GPIO_BIN (1<<10) -#define GPIO_CIN (2<<10) -#define GPIO_DR (3<<10) - -#define GPIO_AOUT_SHIFT 12 -#define GPIO_AOUT_MASK (3<<12) -#define GPIO_AOUT (0<<12) -#define GPIO_AOUT_ISR (1<<12) -#define GPIO_AOUT_0 (2<<12) -#define GPIO_AOUT_1 (3<<12) - -#define GPIO_BOUT_SHIFT 14 -#define GPIO_BOUT_MASK (3<<14) -#define GPIO_BOUT (0<<14) -#define GPIO_BOUT_ISR (1<<14) -#define GPIO_BOUT_0 (2<<14) -#define GPIO_BOUT_1 (3<<14) - -#define GPIO_GIUS (1<<16) - -/* assignements for GPIO alternate/primary functions */ - -/* FIXME: This list is not completed. The correct directions are - * missing on some (many) pins - */ -#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) -#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) -#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) -#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) -#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) -#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) -#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) -#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) -#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) -#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) -#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) -#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) -#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) -#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) -#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) -#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) -#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) -#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) -#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) -#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) -#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) -#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) -#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) -#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) -#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) -#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) -#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) -#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) -#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) -#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) -#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) -#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) -#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) -#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) -#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) -#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) -#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) -#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) -#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) -#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) -#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) -#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) -#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) -#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) -#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) -#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) -#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) -#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) -#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) -#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) -#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) -#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) -#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) -#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) -#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) -#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) -#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) -#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) -#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) -#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) -#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) -#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) -#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) -#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) -#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) -#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) -#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) -#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) -#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) -#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) -#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) -#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) -#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) -#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) -#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) -#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) -#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) -#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) -#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) -#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) -#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) -#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) -#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) -#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) -#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) -#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) -#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) -#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) -#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) -#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) -#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) -#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) -#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) -#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) -#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) -#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) -#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) -#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) -#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) -#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) -#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) -#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) -#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) -#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) -#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) -#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) -#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) -#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) -#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) -#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) -#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) -#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) -#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) -#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) -#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) -#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) -#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) -#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) -#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) -#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) -#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) -#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) -#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) -#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) -#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) -#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) -#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) -#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) -#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) -#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) -#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) - -/* - * PWM controller - */ -#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ -#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ -#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ -#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ - -#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ -#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ -#define PWMC_SWR (0x01<<16) /* Software Reset */ -#define PWMC_CLKSRC (0x01<<15) /* Clock Source */ -#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ -#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ -#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ -#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ -#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ -#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ -#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ - -#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ -#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ -#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ - -/* - * DMA Controller - */ -#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ -#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ -#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ -#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ -#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ -#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ -#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ -#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ -#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ -#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ -#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ -#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ -#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ -#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ -#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ -#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ -#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ -#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ -#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ -#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ -#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ -#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ - -/* TODO: define DMA_REQ lines */ - -#define DCR_DRST (1<<1) -#define DCR_DEN (1<<0) -#define DBTOCR_EN (1<<15) -#define DBTOCR_CNT(x) ((x) & 0x7fff ) -#define CNTR_CNT(x) ((x) & 0xffffff ) -#define CCR_DMOD_LINEAR ( 0x0 << 12 ) -#define CCR_DMOD_2D ( 0x1 << 12 ) -#define CCR_DMOD_FIFO ( 0x2 << 12 ) -#define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) -#define CCR_SMOD_LINEAR ( 0x0 << 10 ) -#define CCR_SMOD_2D ( 0x1 << 10 ) -#define CCR_SMOD_FIFO ( 0x2 << 10 ) -#define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) -#define CCR_MDIR_DEC (1<<9) -#define CCR_MSEL_B (1<<8) -#define CCR_DSIZ_32 ( 0x0 << 6 ) -#define CCR_DSIZ_8 ( 0x1 << 6 ) -#define CCR_DSIZ_16 ( 0x2 << 6 ) -#define CCR_SSIZ_32 ( 0x0 << 4 ) -#define CCR_SSIZ_8 ( 0x1 << 4 ) -#define CCR_SSIZ_16 ( 0x2 << 4 ) -#define CCR_REN (1<<3) -#define CCR_RPT (1<<2) -#define CCR_FRC (1<<1) -#define CCR_CEN (1<<0) -#define RTOR_EN (1<<15) -#define RTOR_CLK (1<<14) -#define RTOR_PSC (1<<13) - -/* - * LCD Controller - */ - -#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) - -#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) -#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) -#define SIZE_YMAX(y) ( (y) & 0x1ff ) - -#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) -#define VPW_VPW(x) ( (x) & 0x3ff ) - -#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) -#define CPOS_CC1 (1<<31) -#define CPOS_CC0 (1<<30) -#define CPOS_OP (1<<28) -#define CPOS_CXP(x) (((x) & 3ff) << 16) -#define CPOS_CYP(y) ((y) & 0x1ff) - -#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) -#define LCWHB_BK_EN (1<<31) -#define LCWHB_CW(w) (((w) & 0x1f) << 24) -#define LCWHB_CH(h) (((h) & 0x1f) << 16) -#define LCWHB_BD(x) ((x) & 0xff) - -#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) -#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) -#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) -#define LCHCC_CUR_COL_B(b) ((b) & 0x1f) - -#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) -#define PCR_TFT (1<<31) -#define PCR_COLOR (1<<30) -#define PCR_PBSIZ_1 (0<<28) -#define PCR_PBSIZ_2 (1<<28) -#define PCR_PBSIZ_4 (2<<28) -#define PCR_PBSIZ_8 (3<<28) -#define PCR_BPIX_1 (0<<25) -#define PCR_BPIX_2 (1<<25) -#define PCR_BPIX_4 (2<<25) -#define PCR_BPIX_8 (3<<25) -#define PCR_BPIX_12 (4<<25) -#define PCR_BPIX_16 (4<<25) -#define PCR_PIXPOL (1<<24) -#define PCR_FLMPOL (1<<23) -#define PCR_LPPOL (1<<22) -#define PCR_CLKPOL (1<<21) -#define PCR_OEPOL (1<<20) -#define PCR_SCLKIDLE (1<<19) -#define PCR_END_SEL (1<<18) -#define PCR_END_BYTE_SWAP (1<<17) -#define PCR_REV_VS (1<<16) -#define PCR_ACD_SEL (1<<15) -#define PCR_ACD(x) (((x) & 0x7f) << 8) -#define PCR_SCLK_SEL (1<<7) -#define PCR_SHARP (1<<6) -#define PCR_PCD(x) ((x) & 0x3f) - -#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) -#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) -#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) -#define HCR_H_WAIT_2(x) ((x) & 0xff) - -#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) -#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) -#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) -#define VCR_V_WAIT_2(x) ((x) & 0xff) - -#define LCDC_POS __REG(IMX_LCDC_BASE+0x24) -#define POS_POS(x) ((x) & 1f) - -#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) -#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) -#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) -#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) -#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) -#define LSCR1_GRAY1(x) (((x) & 0xf)) - -#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) -#define PWMR_CLS(x) (((x) & 0x1ff) << 16) -#define PWMR_LDMSK (1<<15) -#define PWMR_SCR1 (1<<10) -#define PWMR_SCR0 (1<<9) -#define PWMR_CC_EN (1<<8) -#define PWMR_PW(x) ((x) & 0xff) - -#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) -#define DMACR_BURST (1<<31) -#define DMACR_HM(x) (((x) & 0xf) << 16) -#define DMACR_TM(x) ((x) &0xf) - -#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) -#define RMCR_LCDC_EN (1<<1) -#define RMCR_SELF_REF (1<<0) - -#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) -#define LCDICR_INT_SYN (1<<2) -#define LCDICR_INT_CON (1) - -#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) -#define LCDISR_UDR_ERR (1<<3) -#define LCDISR_ERR_RES (1<<2) -#define LCDISR_EOF (1<<1) -#define LCDISR_BOF (1<<0) -/* - * UART Module - */ -#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12) /* Receiver Register */ -#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12) /* Transmitter Register */ -#define UCR1(x) __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12) /* Control Register 1 */ -#define UCR2(x) __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12) /* Control Register 2 */ -#define UCR3(x) __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12) /* Control Register 3 */ -#define UCR4(x) __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12) /* Control Register 4 */ -#define UFCR(x) __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12) /* FIFO Control Register */ -#define USR1(x) __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12) /* Status Register 1 */ -#define USR2(x) __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12) /* Status Register 2 */ -#define UESC(x) __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12) /* Escape Character Register */ -#define UTIM(x) __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12) /* Escape Timer Register */ -#define UBIR(x) __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12) /* BRM Incremental Register */ -#define UBMR(x) __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12) /* BRM Modulator Register */ -#define UBRC(x) __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12) /* Baud Rate Count Register */ -#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12) /* Incremental Preset Register 1 */ -#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12) /* Incremental Preset Register 2 */ -#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12) /* Incremental Preset Register 3 */ -#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12) /* Incremental Preset Register 4 */ -#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12) /* BRM Modulator Register 1 */ -#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12) /* BRM Modulator Register 2 */ -#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12) /* BRM Modulator Register 3 */ -#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12) /* BRM Modulator Register 4 */ -#define UTS(x) __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12) /* UART Test Register */ - -/* UART Control Register Bit Fields.*/ -#define URXD_CHARRDY (1<<15) -#define URXD_ERR (1<<14) -#define URXD_OVRRUN (1<<13) -#define URXD_FRMERR (1<<12) -#define URXD_BRK (1<<11) -#define URXD_PRERR (1<<10) -#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ -#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ -#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ -#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ -#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ -#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ -#define UCR1_IREN (1<<7) /* Infrared interface enable */ -#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ -#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ -#define UCR1_SNDBRK (1<<4) /* Send break */ -#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ -#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ -#define UCR1_DOZE (1<<1) /* Doze */ -#define UCR1_UARTEN (1<<0) /* UART enabled */ -#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ -#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ -#define UCR2_CTSC (1<<13) /* CTS pin control */ -#define UCR2_CTS (1<<12) /* Clear to send */ -#define UCR2_ESCEN (1<<11) /* Escape enable */ -#define UCR2_PREN (1<<8) /* Parity enable */ -#define UCR2_PROE (1<<7) /* Parity odd/even */ -#define UCR2_STPB (1<<6) /* Stop */ -#define UCR2_WS (1<<5) /* Word size */ -#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ -#define UCR2_TXEN (1<<2) /* Transmitter enabled */ -#define UCR2_RXEN (1<<1) /* Receiver enabled */ -#define UCR2_SRST (1<<0) /* SW reset */ -#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ -#define UCR3_PARERREN (1<<12) /* Parity enable */ -#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ -#define UCR3_DSR (1<<10) /* Data set ready */ -#define UCR3_DCD (1<<9) /* Data carrier detect */ -#define UCR3_RI (1<<8) /* Ring indicator */ -#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ -#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ -#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ -#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ -#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ -#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ -#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ -#define UCR3_BPEN (1<<0) /* Preset registers enable */ -#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ -#define UCR4_INVR (1<<9) /* Inverted infrared reception */ -#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ -#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ -#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ -#define UCR4_IRSC (1<<5) /* IR special case */ -#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ -#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ -#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ -#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ -#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ -#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ -#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ -#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ -#define USR1_RTSS (1<<14) /* RTS pin status */ -#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ -#define USR1_RTSD (1<<12) /* RTS delta */ -#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ -#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ -#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ -#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ -#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ -#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ -#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ -#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ -#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ -#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ -#define USR2_IDLE (1<<12) /* Idle condition */ -#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ -#define USR2_WAKE (1<<7) /* Wake */ -#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ -#define USR2_TXDC (1<<3) /* Transmitter complete */ -#define USR2_BRCD (1<<2) /* Break condition */ -#define USR2_ORE (1<<1) /* Overrun error */ -#define USR2_RDR (1<<0) /* Recv data ready */ -#define UTS_FRCPERR (1<<13) /* Force parity error */ -#define UTS_LOOP (1<<12) /* Loop tx and rx */ -#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ -#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ -#define UTS_TXFULL (1<<4) /* TxFIFO full */ -#define UTS_RXFULL (1<<3) /* RxFIFO full */ -#define UTS_SOFTRST (1<<0) /* Software reset */ - -/* General purpose timers registers */ -#define TCTL1 __REG(IMX_TIM1_BASE) -#define TPRER1 __REG(IMX_TIM1_BASE + 0x4) -#define TCMP1 __REG(IMX_TIM1_BASE + 0x8) -#define TCR1 __REG(IMX_TIM1_BASE + 0xc) -#define TCN1 __REG(IMX_TIM1_BASE + 0x10) -#define TSTAT1 __REG(IMX_TIM1_BASE + 0x14) -#define TCTL2 __REG(IMX_TIM2_BASE) -#define TPRER2 __REG(IMX_TIM2_BASE + 0x4) -#define TCMP2 __REG(IMX_TIM2_BASE + 0x8) -#define TCR2 __REG(IMX_TIM2_BASE + 0xc) -#define TCN2 __REG(IMX_TIM2_BASE + 0x10) -#define TSTAT2 __REG(IMX_TIM2_BASE + 0x14) - -/* General purpose timers bitfields */ -#define TCTL_SWR (1<<15) /* Software reset */ -#define TCTL_FRR (1<<8) /* Freerun / restart */ -#define TCTL_CAP (3<<6) /* Capture Edge */ -#define TCTL_OM (1<<5) /* output mode */ -#define TCTL_IRQEN (1<<4) /* interrupt enable */ -#define TCTL_CLKSOURCE (7<<1) /* Clock source */ -#define TCTL_TEN (1) /* Timer enable */ -#define TPRER_PRES (0xff) /* Prescale */ -#define TSTAT_CAPT (1<<1) /* Capture event */ -#define TSTAT_COMP (1) /* Compare event */ - -#endif /* _IMX_REGS_H */ diff --git a/include/asm-arm/arch-ixp/ixp425.h b/include/asm-arm/arch-ixp/ixp425.h deleted file mode 100644 index 2114437..0000000 --- a/include/asm-arm/arch-ixp/ixp425.h +++ /dev/null @@ -1,543 +0,0 @@ -/* - * include/asm-arm/arch-ixp425/ixp425.h - * - * Register definitions for IXP425 - * - * Copyright (C) 2002 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef _ASM_ARM_IXP425_H_ -#define _ASM_ARM_IXP425_H_ - -#define BIT(x) (1<<(x)) - -/* FIXME: Only this does work for u-boot... find out why... [RS] */ -#define UBOOT_REG_FIX 1 -#ifdef UBOOT_REG_FIX -# undef io_p2v -# undef __REG -# ifndef __ASSEMBLY__ -# define io_p2v(PhAdd) (PhAdd) -# define __REG(x) (*((volatile u32 *)io_p2v(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# endif -#endif /* UBOOT_REG_FIX */ - -/* - * - * IXP425 Memory map: - * - * Phy Phy Size Map Size Virt Description - * ========================================================================= - * - * 0x00000000 0x10000000 SDRAM 1 - * - * 0x10000000 0x10000000 SDRAM 2 - * - * 0x20000000 0x10000000 SDRAM 3 - * - * 0x30000000 0x10000000 SDRAM 4 - * - * The above four are aliases to the same memory location (0x00000000) - * - * 0x48000000 0x4000000 PCI Memory - * - * 0x50000000 0x10000000 Not Mapped EXP BUS - * - * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr - * - * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG - * - * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG - * - * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL - * - * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG - */ - -/* - * SDRAM - */ -#define IXP425_SDRAM_BASE (0x00000000) -#define IXP425_SDRAM_BASE_ALT (0x10000000) - - -/* - * PCI Configuration space - */ -#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000) -#define IXP425_PCI_CFG_REGION_SIZE (0x00001000) - -/* - * Expansion BUS Configuration registers - */ -#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000) -#define IXP425_EXP_CFG_REGION_SIZE (0x00001000) - -/* - * Peripheral space - */ -#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000) -#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000) - -/* - * SDRAM configuration registers - */ -#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000) - -/* - * Q Manager space .. not static mapped - */ -#define IXP425_QMGR_BASE_PHYS (0x60000000) -#define IXP425_QMGR_REGION_SIZE (0x00004000) - -/* - * Expansion BUS - * - * Expansion Bus 'lives' at either base1 or base 2 depending on the value of - * Exp Bus config registers: - * - * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero, - * and The expansion bus to IXP425_EXP_BUS_BASE2 - */ -#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000) -#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000) - -#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS - -#define IXP425_EXP_BUS_REGION_SIZE (0x08000000) -#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000) - -#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000) -#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000) -#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000) -#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000) -#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000) -#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000) -#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000) -#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000) - -#define IXP425_FLASH_WRITABLE (0x2) -#define IXP425_FLASH_DEFAULT (0xbcd23c40) -#define IXP425_FLASH_WRITE (0xbcd23c42) - -#define IXP425_EXP_CS0_OFFSET 0x00 -#define IXP425_EXP_CS1_OFFSET 0x04 -#define IXP425_EXP_CS2_OFFSET 0x08 -#define IXP425_EXP_CS3_OFFSET 0x0C -#define IXP425_EXP_CS4_OFFSET 0x10 -#define IXP425_EXP_CS5_OFFSET 0x14 -#define IXP425_EXP_CS6_OFFSET 0x18 -#define IXP425_EXP_CS7_OFFSET 0x1C -#define IXP425_EXP_CFG0_OFFSET 0x20 -#define IXP425_EXP_CFG1_OFFSET 0x24 -#define IXP425_EXP_CFG2_OFFSET 0x28 -#define IXP425_EXP_CFG3_OFFSET 0x2C - -/* - * Expansion Bus Controller registers. - */ -#ifndef __ASSEMBLY__ -#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x))) -#else -#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x)) -#endif - -#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET) -#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET) -#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET) -#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET) -#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET) -#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET) -#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET) -#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET) - -#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET) -#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET) -#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET) -#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET) - -/* - * SDRAM Controller registers. - */ -#define IXP425_SDR_CONFIG_OFFSET 0x00 -#define IXP425_SDR_REFRESH_OFFSET 0x04 -#define IXP425_SDR_IR_OFFSET 0x08 - -#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) - -#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET) -#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) -#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) - -/* - * UART registers - */ -#define IXP425_UART1 0 -#define IXP425_UART2 0x1000 - -#define IXP425_UART_RBR_OFFSET 0x00 -#define IXP425_UART_THR_OFFSET 0x00 -#define IXP425_UART_DLL_OFFSET 0x00 -#define IXP425_UART_IER_OFFSET 0x04 -#define IXP425_UART_DLH_OFFSET 0x04 -#define IXP425_UART_IIR_OFFSET 0x08 -#define IXP425_UART_FCR_OFFSET 0x00 -#define IXP425_UART_LCR_OFFSET 0x0c -#define IXP425_UART_MCR_OFFSET 0x10 -#define IXP425_UART_LSR_OFFSET 0x14 -#define IXP425_UART_MSR_OFFSET 0x18 -#define IXP425_UART_SPR_OFFSET 0x1c -#define IXP425_UART_ISR_OFFSET 0x20 - -#define IXP425_UART_CFG_BASE_PHYS (0xc8000000) - -#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET) -#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET) -#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET) -#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET) -#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET) -#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET) -#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET) -#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET) -#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET) -#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET) -#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET) -#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET) -#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET) - -#define IER_DMAE (1 << 7) /* DMA Requests Enable */ -#define IER_UUE (1 << 6) /* UART Unit Enable */ -#define IER_NRZE (1 << 5) /* NRZ coding Enable */ -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ - -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ -#define IIR_TOD (1 << 3) /* Time Out Detected */ -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ - -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ -#define FCR_ITL_1 (0) -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ -#define LCR_SB (1 << 6) /* Set Break */ -#define LCR_STKYP (1 << 5) /* Sticky Parity */ -#define LCR_EPS (1 << 4) /* Even Parity Select */ -#define LCR_PEN (1 << 3) /* Parity Enable */ -#define LCR_STB (1 << 2) /* Stop Bit */ -#define LCR_WLS1 (1 << 1) /* Word Length Select */ -#define LCR_WLS0 (1 << 0) /* Word Length Select */ - -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ -#define LSR_TEMT (1 << 6) /* Transmitter Empty */ -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ -#define LSR_BI (1 << 4) /* Break Interrupt */ -#define LSR_FE (1 << 3) /* Framing Error */ -#define LSR_PE (1 << 2) /* Parity Error */ -#define LSR_OE (1 << 1) /* Overrun Error */ -#define LSR_DR (1 << 0) /* Data Ready */ - -#define MCR_LOOP (1 << 4) */ -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ - -#define MSR_DCD (1 << 7) /* Data Carrier Detect */ -#define MSR_RI (1 << 6) /* Ring Indicator */ -#define MSR_DSR (1 << 5) /* Data Set Ready */ -#define MSR_CTS (1 << 4) /* Clear To Send */ -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ - -#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS -/* - * Peripheral Space Registers - */ -#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000) -#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000) -#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000) -#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000) -#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000) -#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000) -#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000) -#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000) -#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000) -#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000) -#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000) -#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000) - -/* - * UART Register Definitions , Offsets only as there are 2 UARTS. - * IXP425_UART1_BASE , IXP425_UART2_BASE. - */ - -#undef UART_NO_RX_INTERRUPT - -#define IXP425_UART_XTAL 14745600 - -/* - * Constants to make it easy to access Interrupt Controller registers - */ -#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */ -#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */ -#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ -#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */ -#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */ -#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */ -#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ -#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ - -#define N_IRQS 32 -#define IXP425_TIMER_2_IRQ 11 - -/* - * Interrupt Controller Register Definitions. - */ -#ifndef __ASSEMBLY__ -#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x))) -#else -#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x)) -#endif - -#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET) -#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET) -#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET) -#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET) -#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET) -#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET) -#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET) -#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET) - -/* - * Constants to make it easy to access GPIO registers - */ -#define IXP425_GPIO_GPOUTR_OFFSET 0x00 -#define IXP425_GPIO_GPOER_OFFSET 0x04 -#define IXP425_GPIO_GPINR_OFFSET 0x08 -#define IXP425_GPIO_GPISR_OFFSET 0x0C -#define IXP425_GPIO_GPIT1R_OFFSET 0x10 -#define IXP425_GPIO_GPIT2R_OFFSET 0x14 -#define IXP425_GPIO_GPCLKR_OFFSET 0x18 -#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C - -/* - * GPIO Register Definitions. - * [Only perform 32bit reads/writes] - */ -#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x))) - -#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET) -#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET) -#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET) -#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET) -#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET) -#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET) -#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET) -#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET) - -/* - * Macros to make it easy to access the GPIO registers - */ -#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line)) -#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line)) -#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line)) -#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line)) -#define GPIO_INT_ACT_LOW_SET(line) *IXP425_GPIO_GPIT1R = \ - (*IXP425_GPIO_GPIT1R & ~(0x7 << (line * 3))) | (0x1 << (line * 3)) - -/* - * Constants to make it easy to access Timer Control/Status registers - */ -#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */ -#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ -#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ -#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ -#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ -#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */ -#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */ -#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */ -#define IXP425_OSST_OFFSET 0x20 /* Timer Status */ - -/* - * Operating System Timer Register Definitions. - */ - -#ifndef __ASSEMBLY__ -#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x))) -#else -#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x)) -#endif - -#if 0 /* test-only: also defined in npe/include/... */ -#define IXP425_OSTS IXP425_TIMER_REG(IXP425_OSTS_OFFSET) -#endif -#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET) -#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET) -#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET) -#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET) -#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET) -#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET) -#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET) -#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET) - -/* - * Timer register values and bit definitions - */ -#define IXP425_OST_ENABLE BIT(0) -#define IXP425_OST_ONE_SHOT BIT(1) -/* Low order bits of reload value ignored */ -#define IXP425_OST_RELOAD_MASK (0x3) -#define IXP425_OST_DISABLED (0x0) -#define IXP425_OSST_TIMER_1_PEND BIT(0) -#define IXP425_OSST_TIMER_2_PEND BIT(1) -#define IXP425_OSST_TIMER_TS_PEND BIT(2) -#define IXP425_OSST_TIMER_WDOG_PEND BIT(3) -#define IXP425_OSST_TIMER_WARM_RESET BIT(4) - -/* - * Constants to make it easy to access PCI Control/Status registers - */ -#define PCI_NP_AD_OFFSET 0x00 -#define PCI_NP_CBE_OFFSET 0x04 -#define PCI_NP_WDATA_OFFSET 0x08 -#define PCI_NP_RDATA_OFFSET 0x0c -#define PCI_CRP_AD_CBE_OFFSET 0x10 -#define PCI_CRP_WDATA_OFFSET 0x14 -#define PCI_CRP_RDATA_OFFSET 0x18 -#define PCI_CSR_OFFSET 0x1c -#define PCI_ISR_OFFSET 0x20 -#define PCI_INTEN_OFFSET 0x24 -#define PCI_DMACTRL_OFFSET 0x28 -#define PCI_AHBMEMBASE_OFFSET 0x2c -#define PCI_AHBIOBASE_OFFSET 0x30 -#define PCI_PCIMEMBASE_OFFSET 0x34 -#define PCI_AHBDOORBELL_OFFSET 0x38 -#define PCI_PCIDOORBELL_OFFSET 0x3C -#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 -#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 -#define PCI_ATPDMA0_LENADDR_OFFSET 0x48 -#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C -#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 -#define PCI_ATPDMA1_LENADDR_OFFSET 0x54 - -/* - * PCI Control/Status Registers - */ -#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x))) - -#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET) -#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET) -#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET) -#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET) -#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) -#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET) -#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET) -#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET) -#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET) -#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET) -#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET) -#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET) -#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET) -#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET) -#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET) -#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET) -#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) -#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) -#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) -#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) -#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) -#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) - -/* - * PCI register values and bit definitions - */ - -/* CSR bit definitions */ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) - -/* ISR (Interrupt status) Register bit definitions */ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) - -/* INTEN (Interrupt Enable) Register bit definitions */ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) - -/* - * Shift value for byte enable on NP cmd/byte enable register - */ -#define IXP425_PCI_NP_CBE_BESL 4 - -/* - * PCI commands supported by NP access unit - */ -#define NP_CMD_IOREAD 0x2 -#define NP_CMD_IOWRITE 0x3 -#define NP_CMD_CONFIGREAD 0xa -#define NP_CMD_CONFIGWRITE 0xb -#define NP_CMD_MEMREAD 0x6 -#define NP_CMD_MEMWRITE 0x7 - -#if 0 -#ifndef __ASSEMBLY__ -extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data); -extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data); -extern void ixp425_pci_init(void *); -#endif -#endif - -/* - * Constants for CRP access into local config space - */ -#define CRP_AD_CBE_BESL 20 -#define CRP_AD_CBE_WRITE BIT(16) - -/* - * Clock Speed Definitions. - */ -#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ - - -#endif diff --git a/include/asm-arm/arch-ixp/ixp425pci.h b/include/asm-arm/arch-ixp/ixp425pci.h deleted file mode 100644 index 9ea3319..0000000 --- a/include/asm-arm/arch-ixp/ixp425pci.h +++ /dev/null @@ -1,312 +0,0 @@ -/* - * IXP PCI Init - * (C) Copyright 2004 eslab.whut.edu.cn - * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _IXP425PCI_H_ -#define _IXP425PCI_H_ - -#define TRUE 1 -#define FALSE 0 -#define OK 0 -#define ERROR -1 -#define BOOL int - -#define IXP425_PCI_MAX_BAR_PER_FUNC 6 -#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \ - IXP425_PCI_MAX_FUNC_ON_BUS) - -enum PciBarId -{ - CSR_BAR=0, - IO_BAR, - SD_BAR, - NO_BAR -}; - -/*Base address register descriptor*/ -typedef struct -{ - unsigned int size; - unsigned int address; -} PciBar; - -typedef struct -{ - unsigned int bus; - unsigned int device; - unsigned int func; - unsigned int irq; - BOOL error; - unsigned short vendor_id; - unsigned short device_id; - /*We need an extra entry in this array for dummy placeholder*/ - PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1]; -} PciDevice; - -/* Mask definitions*/ -#define IXP425_PCI_TOP_WORD_OF_LONG_MASK 0xffff0000 -#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK 0xff000000 -#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK 0x0000ffff -#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff -#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f -#define IXP425_PCI_MAX_UINT32 0xffffffff - - -#define IXP425_PCI_BAR_QUERY 0xffffffff - -#define IXP425_PCI_BAR_MEM_BASE 0x100000 -#define IXP425_PCI_BAR_IO_BASE 0x000000 - -/*define the maximum number of bus segments - we support a single segment*/ -#define IXP425_PCI_MAX_BUS 1 -/*define the maximum number of cards per bus segment*/ -#define IXP425_PCI_MAX_DEV 4 -/*define the maximum number of functions per device*/ -#define IXP425_PCI_MAX_FUNC 8 -/* define the maximum number of separate functions that we can - potentially have on the bus*/ -#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC * \ - IXP425_PCI_MAX_DEV * \ - IXP425_PCI_MAX_BUS) -/*define the maximum number of BARs per function*/ -#define IXP425_PCI_MAX_BAR_PER_FUNC 6 -#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \ - IXP425_PCI_MAX_FUNC_ON_BUS) - -#define PCI_NP_CBE_BESL (4) -#define PCI_NP_AD_FUNCSL (8) - -#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v)) -#define REG_READ(b,o,v) ((v)=(*(volatile unsigned int*)((b+o)))) - -#define PCI_DELAY 500 -#define USEC_LOOP_COUNT 533 -#define PCI_SETTLE_USEC 200 -#define PCI_MIN_RESET_ASSERT_USEC 2000 - -/*Register addressing definitions for PCI controller configuration - and status registers*/ - -#define PCI_CSR_BASE (0xC0000000) -/* -#define PCI_NP_AD_OFFSET (0x00) -#define PCI_NP_CBE_OFFSET (0x04) -#define PCI_NP_WDATA_OFFSET (0x08) -#define PCI_NP_RDATA_OFFSET (0x0C) -#define PCI_CRP_OFFSET (0x10) -#define PCI_CRP_WDATA_OFFSET (0x14) -#define PCI_CRP_RDATA_OFFSET (0x18) -#define PCI_CSR_OFFSET (0x1C) -#define PCI_ISR_OFFSET (0x20) -#define PCI_INTEN_OFFSET (0x24) -#define PCI_DMACTRL_OFFSET (0x28) -#define PCI_AHBMEMBASE_OFFSET (0x2C) -#define PCI_AHBIOBASE_OFFSET (0x30) -#define PCI_PCIMEMBASE_OFFSET (0x34) -#define PCI_AHBDOORBELL_OFFSET (0x38) -#define PCI_PCIDOORBELL_OFFSET (0x3C) -#define PCI_ATPDMA0_AHBADDR (0x40) -#define PCI_ATPDMA0_PCIADDR (0x44) -#define PCI_ATPDMA0_LENADDR (0x48) -#define PCI_ATPDMA1_AHBADDR (0x4C) -#define PCI_ATPDMA1_PCIADDR (0x50) -#define PCI_ATPDMA1_LENADDR (0x54) -#define PCI_PTADMA0_AHBADDR (0x58) -#define PCI_PTADMA0_PCIADDR (0x5C) -#define PCI_PTADMA0_LENADDR (0x60) -#define PCI_PTADMA1_AHBADDR (0x64) -#define PCI_PTADMA1_PCIADDR (0x68) -#define PCI_PTADMA1_LENADDR (0x6C) -*/ -/*Non prefetch registers bit definitions*/ -/* -#define NP_CMD_INTACK (0x0) -#define NP_CMD_SPECIAL (0x1) -#define NP_CMD_IOREAD (0x2) -#define NP_CMD_IOWRITE (0x3) -#define NP_CMD_MEMREAD (0x6) -#define NP_CMD_MEMWRITE (0x7) -#define NP_CMD_CONFIGREAD (0xa) -#define NP_CMD_CONFIGWRITE (0xb) -*/ - -/*define the default setting of the AHB memory base reg*/ -#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203 -#define IXP425_PCI_AHBIOBASE_DEFAULT 0x0 -#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0 - -/*define the default settings for the controller's BARs*/ -#ifdef IXP425_PCI_SIMPLE_MAPPING -#define IXP425_PCI_BAR_0_DEFAULT 0x00000000 -#define IXP425_PCI_BAR_1_DEFAULT 0x01000000 -#define IXP425_PCI_BAR_2_DEFAULT 0x02000000 -#define IXP425_PCI_BAR_3_DEFAULT 0x03000000 -#define IXP425_PCI_BAR_4_DEFAULT 0x00000000 -#define IXP425_PCI_BAR_5_DEFAULT 0x00000000 -#else -#define IXP425_PCI_BAR_0_DEFAULT 0x40000000 -#define IXP425_PCI_BAR_1_DEFAULT 0x41000000 -#define IXP425_PCI_BAR_2_DEFAULT 0x42000000 -#define IXP425_PCI_BAR_3_DEFAULT 0x43000000 -#define IXP425_PCI_BAR_4_DEFAULT 0x00000000 -#define IXP425_PCI_BAR_5_DEFAULT 0x00000000 -#endif - -/*Configuration Port register bit definitions*/ -#define PCI_CRP_WRITE BIT(16) - -/*ISR (Interrupt status) Register bit definitions*/ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) - -/*INTEN (Interrupt Enable) Register bit definitions*/ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) - -/*PCI configuration regs.*/ - -#define PCI_CFG_VENDOR_ID 0x00 -#define PCI_CFG_DEVICE_ID 0x02 -#define PCI_CFG_COMMAND 0x04 -#define PCI_CFG_STATUS 0x06 -#define PCI_CFG_REVISION 0x08 -#define PCI_CFG_PROGRAMMING_IF 0x09 -#define PCI_CFG_SUBCLASS 0x0a -#define PCI_CFG_CLASS 0x0b -#define PCI_CFG_CACHE_LINE_SIZE 0x0c -#define PCI_CFG_LATENCY_TIMER 0x0d -#define PCI_CFG_HEADER_TYPE 0x0e -#define PCI_CFG_BIST 0x0f -#define PCI_CFG_BASE_ADDRESS_0 0x10 -#define PCI_CFG_BASE_ADDRESS_1 0x14 -#define PCI_CFG_BASE_ADDRESS_2 0x18 -#define PCI_CFG_BASE_ADDRESS_3 0x1c -#define PCI_CFG_BASE_ADDRESS_4 0x20 -#define PCI_CFG_BASE_ADDRESS_5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SUB_VENDOR_ID 0x2c -#define PCI_CFG_SUB_SYSTEM_ID 0x2e -#define PCI_CFG_EXPANSION_ROM 0x30 -#define PCI_CFG_RESERVED_0 0x34 -#define PCI_CFG_RESERVED_1 0x38 -#define PCI_CFG_DEV_INT_LINE 0x3c -#define PCI_CFG_DEV_INT_PIN 0x3d -#define PCI_CFG_MIN_GRANT 0x3e -#define PCI_CFG_MAX_LATENCY 0x3f -#define PCI_CFG_SPECIAL_USE 0x41 -#define PCI_CFG_MODE 0x43 - -/*Specify the initial command we send to PCI devices*/ -#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE \ - | PCI_CMD_MEM_ENABLE \ - | PCI_CMD_MASTER_ENABLE \ - | PCI_CMD_WI_ENABLE) - -/*define the sub vendor and subsystem to be used */ -#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000 - -#define PCI_IRQ_LINES 4 - -#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ -#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ -#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ -#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */ -#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */ -#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */ -#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */ -#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */ -#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */ -#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */ - - -/*CSR Register bit definitions*/ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) - -/*Configuration command bit definitions*/ -#define PCI_CFG_CMD_IOAE BIT(0) -#define PCI_CFG_CMD_MAE BIT(1) -#define PCI_CFG_CMD_BME BIT(2) -#define PCI_CFG_CMD_MWIE BIT(4) -#define PCI_CFG_CMD_SER BIT(8) -#define PCI_CFG_CMD_FBBE BIT(9) -#define PCI_CFG_CMD_MDPE BIT(24) -#define PCI_CFG_CMD_STA BIT(27) -#define PCI_CFG_CMD_RTA BIT(28) -#define PCI_CFG_CMD_RMA BIT(29) -#define PCI_CFG_CMD_SSE BIT(30) -#define PCI_CFG_CMD_DPE BIT(31) - -/*DMACTRL DMA Control and status Register*/ -#define PCI_DMACTRL_APDCEN BIT(0) -#define PCI_DMACTRL_APDC0 BIT(4) -#define PCI_DMACTRL_APDE0 BIT(5) -#define PCI_DMACTRL_APDC1 BIT(6) -#define PCI_DMACTRL_APDE1 BIT(7) -#define PCI_DMACTRL_PADCEN BIT(8) -#define PCI_DMACTRL_PADC0 BIT(12) -#define PCI_DMACTRL_PADE0 BIT(13) -#define PCI_DMACTRL_PADC1 BIT(14) -#define PCI_DMACTRL_PADE1 BIT(15) - -/* GPIO related register */ -#undef IXP425_GPIO_GPOUTR -#undef IXP425_GPIO_GPOER -#undef IXP425_GPIO_GPINR -#undef IXP425_GPIO_GPISR -#undef IXP425_GPIO_GPIT1R -#undef IXP425_GPIO_GPIT2R -#undef IXP425_GPIO_GPCLKR - -#define IXP425_GPIO_GPOUTR 0xC8004000 -#define IXP425_GPIO_GPOER 0xC8004004 -#define IXP425_GPIO_GPINR 0xC8004008 -#define IXP425_GPIO_GPISR 0xC800400C -#define IXP425_GPIO_GPIT1R 0xC8004010 -#define IXP425_GPIO_GPIT2R 0xC8004014 -#define IXP425_GPIO_GPCLKR 0xC8004018 - -#define READ_GPIO_REG(addr,val) \ - (val) = *((volatile int *)(addr)); -#define WRITE_GPIO_REG(addr,val) \ - *((volatile int *)(addr)) = (val); - -#endif diff --git a/include/asm-arm/arch-kirkwood/cpu.h b/include/asm-arm/arch-kirkwood/cpu.h deleted file mode 100644 index b3022a3..0000000 --- a/include/asm-arm/arch-kirkwood/cpu.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _KWCPU_H -#define _KWCPU_H - -#include - -#ifndef __ASSEMBLY__ - -#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ - | (attr << 8) | (kw_winctrl_calcsize(size) << 16)) - -#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ - ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) - -#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) -#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50) -#define SYSRST_CNT_1SEC_VAL (25*1000000) -#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0) - -enum memory_bank { - BANK0, - BANK1, - BANK2, - BANK3 -}; - -enum kwcpu_winen { - KWCPU_WIN_DISABLE, - KWCPU_WIN_ENABLE -}; - -enum kwcpu_target { - KWCPU_TARGET_RESERVED, - KWCPU_TARGET_MEMORY, - KWCPU_TARGET_1RESERVED, - KWCPU_TARGET_SASRAM, - KWCPU_TARGET_PCIE -}; - -enum kwcpu_attrib { - KWCPU_ATTR_SASRAM = 0x01, - KWCPU_ATTR_DRAM_CS0 = 0x0e, - KWCPU_ATTR_DRAM_CS1 = 0x0d, - KWCPU_ATTR_DRAM_CS2 = 0x0b, - KWCPU_ATTR_DRAM_CS3 = 0x07, - KWCPU_ATTR_NANDFLASH = 0x2f, - KWCPU_ATTR_SPIFLASH = 0x1e, - KWCPU_ATTR_BOOTROM = 0x1d, - KWCPU_ATTR_PCIE_IO = 0xe0, - KWCPU_ATTR_PCIE_MEM = 0xe8 -}; - -/* - * Default Device Address MAP BAR values - */ -#define KW_DEFADR_PCI_MEM 0x90000000 -#define KW_DEFADR_PCI_IO 0xC0000000 -#define KW_DEFADR_PCI_IO_REMAP 0xC0000000 -#define KW_DEFADR_SASRAM 0xC8010000 -#define KW_DEFADR_NANDF 0xD8000000 -#define KW_DEFADR_SPIF 0xE8000000 -#define KW_DEFADR_BOOTROM 0xF8000000 - -/* - * read feroceon/sheeva core extra feature register - * using co-proc instruction - */ -static inline unsigned int readfr_extra_feature_reg(void) -{ - unsigned int val; - asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" - (val)::"cc"); - return val; -} - -/* - * write feroceon/sheeva core extra feature register - * using co-proc instruction - */ -static inline void writefr_extra_feature_reg(unsigned int val) -{ - asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" - (val):"cc"); - isb(); -} - -/* - * MBus-L to Mbus Bridge Registers - * Ref: Datasheet sec:A.3 - */ -struct kwwin_registers { - u32 ctrl; - u32 base; - u32 remap_lo; - u32 remap_hi; -}; - -/* - * CPU control and status Registers - * Ref: Datasheet sec:A.3.2 - */ -struct kwcpu_registers { - u32 config; /*0x20100 */ - u32 ctrl_stat; /*0x20104 */ - u32 rstoutn_mask; /* 0x20108 */ - u32 sys_soft_rst; /* 0x2010C */ - u32 ahb_mbus_cause_irq; /* 0x20110 */ - u32 ahb_mbus_mask_irq; /* 0x20114 */ - u32 pad1[2]; - u32 ftdll_config; /* 0x20120 */ - u32 pad2; - u32 l2_cfg; /* 0x20128 */ -}; - -/* - * GPIO Registers - * Ref: Datasheet sec:A.19 - */ -struct kwgpio_registers { - u32 dout; - u32 oe; - u32 blink_en; - u32 din_pol; - u32 din; - u32 irq_cause; - u32 irq_mask; - u32 irq_level; -}; - -/* - * functions - */ -void reset_cpu(unsigned long ignored); -unsigned char get_random_hex(void); -unsigned int kw_sdram_bar(enum memory_bank bank); -unsigned int kw_sdram_bs(enum memory_bank bank); -int kw_config_adr_windows(void); -void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, - unsigned int gpp0_oe, unsigned int gpp1_oe); -int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, - unsigned int mpp16_23, unsigned int mpp24_31, - unsigned int mpp32_39, unsigned int mpp40_47, - unsigned int mpp48_55); -unsigned int kw_winctrl_calcsize(unsigned int sizeval); -#endif /* __ASSEMBLY__ */ -#endif /* _KWCPU_H */ diff --git a/include/asm-arm/arch-kirkwood/gpio.h b/include/asm-arm/arch-kirkwood/gpio.h deleted file mode 100644 index cd1bc00..0000000 --- a/include/asm-arm/arch-kirkwood/gpio.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * arch/asm-arm/mach-kirkwood/include/mach/gpio.h - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* - * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver. - * Removed kernel level irq handling. Took some macros from kernel to - * allow build. - * - * Dieter Kiermaier dk-arm-linux@gmx.de - */ - -#ifndef __KIRKWOOD_GPIO_H -#define __KIRKWOOD_GPIO_H - -/* got from kernel include/linux/bitops.h */ -#define BITS_PER_BYTE 8 -#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) - -#define GPIO_MAX 50 -#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) -#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00) -#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04) -#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08) -#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) -#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10) -#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14) -#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18) -#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) - -/* - * Kirkwood-specific GPIO API - */ - -void kw_gpio_set_valid(unsigned pin, int mode); -int kw_gpio_is_valid(unsigned pin, int mode); -int kw_gpio_direction_input(unsigned pin); -int kw_gpio_direction_output(unsigned pin, int value); -int kw_gpio_get_value(unsigned pin); -void kw_gpio_set_value(unsigned pin, int value); -void kw_gpio_set_blink(unsigned pin, int blink); -void kw_gpio_set_unused(unsigned pin); - -#define GPIO_INPUT_OK (1 << 0) -#define GPIO_OUTPUT_OK (1 << 1) - -#endif diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h deleted file mode 100644 index 2470efb..0000000 --- a/include/asm-arm/arch-kirkwood/kirkwood.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * Header file for the Marvell's Feroceon CPU core. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _ASM_ARCH_KIRKWOOD_H -#define _ASM_ARCH_KIRKWOOD_H - -#ifndef __ASSEMBLY__ -#include -#include -#endif /* __ASSEMBLY__ */ - -#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) -#include - -/* SOC specific definations */ -#define INTREG_BASE 0xd0000000 -#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x) -#define KW_OFFSET_REG (INTREG_BASE + 0x20080) - -/* undocumented registers */ -#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) -#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) - -#define KW_TWSI_BASE (KW_REGISTER(0x11000)) -#define KW_UART0_BASE (KW_REGISTER(0x12000)) -#define KW_UART1_BASE (KW_REGISTER(0x12100)) -#define KW_MPP_BASE (KW_REGISTER(0x10000)) -#define KW_GPIO0_BASE (KW_REGISTER(0x10100)) -#define KW_GPIO1_BASE (KW_REGISTER(0x10140)) -#define KW_NANDF_BASE (KW_REGISTER(0x10418)) -#define KW_SPI_BASE (KW_REGISTER(0x10600)) -#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) -#define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) -#define KW_TIMER_BASE (KW_REGISTER(0x20300)) -#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) -#define KW_USB20_BASE (KW_REGISTER(0x50000)) -#define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) -#define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) - -#if defined (CONFIG_KW88F6281) -#include -#elif defined (CONFIG_KW88F6192) -#include -#else -#error "SOC Name not defined" -#endif /* CONFIG_KW88F6281 */ -#endif /* CONFIG_FEROCEON_88FR131 */ -#endif /* _ASM_ARCH_KIRKWOOD_H */ diff --git a/include/asm-arm/arch-kirkwood/kw88f6192.h b/include/asm-arm/arch-kirkwood/kw88f6192.h deleted file mode 100644 index bbb7cee..0000000 --- a/include/asm-arm/arch-kirkwood/kw88f6192.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _CONFIG_KW88F6192_H -#define _CONFIG_KW88F6192_H - -/* SOC specific definations */ -#define KW88F6192_REGS_PHYS_BASE 0xf1000000 -#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE - -/* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - -#endif /* _CONFIG_KW88F6192_H */ diff --git a/include/asm-arm/arch-kirkwood/kw88f6281.h b/include/asm-arm/arch-kirkwood/kw88f6281.h deleted file mode 100644 index 80723ea..0000000 --- a/include/asm-arm/arch-kirkwood/kw88f6281.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _ASM_ARCH_KW88F6281_H -#define _ASM_ARCH_KW88F6281_H - -/* SOC specific definations */ -#define KW88F6281_REGS_PHYS_BASE 0xf1000000 -#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE - -/* TCLK Core Clock defination*/ -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ - -#endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/include/asm-arm/arch-kirkwood/mpp.h b/include/asm-arm/arch-kirkwood/mpp.h deleted file mode 100644 index b3c090e..0000000 --- a/include/asm-arm/arch-kirkwood/mpp.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins - * - * Copyright 2009: Marvell Technology Group Ltd. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __KIRKWOOD_MPP_H -#define __KIRKWOOD_MPP_H - -#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ - /* MPP number */ ((_num) & 0xff) | \ - /* MPP select value */ (((_sel) & 0xf) << 8) | \ - /* may be input signal */ ((!!(_in)) << 12) | \ - /* may be output signal */ ((!!(_out)) << 13) | \ - /* available on F6180 */ ((!!(_F6180)) << 14) | \ - /* available on F6190 */ ((!!(_F6190)) << 15) | \ - /* available on F6192 */ ((!!(_F6192)) << 16) | \ - /* available on F6281 */ ((!!(_F6281)) << 17)) - -#define MPP_NUM(x) ((x) & 0xff) -#define MPP_SEL(x) (((x) >> 8) & 0xf) - - /* num sel i o 6180 6190 6192 6281 */ - -#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) -#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) - -#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) -#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) -#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) -#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) - -#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) - -#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) -#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) -#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) -#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) -#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) -#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) -#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) -#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) - -#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) -#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) -#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) -#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) - -#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) - -#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) - -#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) - -#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) - -#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) -#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) - -#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) - -#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) - -#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) -#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) - -#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) -#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) -#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) -#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) -#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) - -#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) -#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) -#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) -#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) - -#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) - -#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) - -#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) - -#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) - -#define MPP_MAX 49 - -void kirkwood_mpp_conf(unsigned int *mpp_list); - -#endif diff --git a/include/asm-arm/arch-kirkwood/spi.h b/include/asm-arm/arch-kirkwood/spi.h deleted file mode 100644 index 1d5043f..0000000 --- a/include/asm-arm/arch-kirkwood/spi.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * Derived from drivers/spi/mpc8xxx_spi.c - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __KW_SPI_H__ -#define __KW_SPI_H__ - -/* SPI Registers on kirkwood SOC */ -struct kwspi_registers { - u32 ctrl; /* 0x10600 */ - u32 cfg; /* 0x10604 */ - u32 dout; /* 0x10608 */ - u32 din; /* 0x1060c */ - u32 irq_cause; /* 0x10610 */ - u32 irq_mask; /* 0x10614 */ -}; - -#define KWSPI_CLKPRESCL_MASK 0x1f -#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ -#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ -#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ -#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ -#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ -#define KWSPI_XFERLEN_1BYTE 0 -#define KWSPI_XFERLEN_2BYTE (1 << 5) -#define KWSPI_XFERLEN_MASK (1 << 5) -#define KWSPI_ADRLEN_1BYTE 0 -#define KWSPI_ADRLEN_2BYTE 1 << 8 -#define KWSPI_ADRLEN_3BYTE 2 << 8 -#define KWSPI_ADRLEN_4BYTE 3 << 8 -#define KWSPI_ADRLEN_MASK 3 << 8 -#define KWSPI_TIMEOUT 10000 - -#endif /* __KW_SPI_H__ */ diff --git a/include/asm-arm/arch-ks8695/platform.h b/include/asm-arm/arch-ks8695/platform.h deleted file mode 100644 index de20015..0000000 --- a/include/asm-arm/arch-ks8695/platform.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __address_h -#define __address_h 1 - -#define KS8695_SDRAM_START 0x00000000 -#define KS8695_SDRAM_SIZE 0x01000000 -#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE -#define KS8695_MEM_START KS8695_SDRAM_START - -#define KS8695_PCMCIA_IO_BASE 0x03800000 -#define KS8695_PCMCIA_IO_SIZE 0x00040000 - -#define KS8695_IO_BASE 0x03FF0000 -#define KS8695_IO_SIZE 0x00010000 - -#define KS8695_SYSTEN_CONFIG 0x00 -#define KS8695_SYSTEN_BUS_CLOCK 0x04 - -#define KS8695_FLASH_START 0x02800000 -#define KS8695_FLASH_SIZE 0x00400000 - -/*i/o control registers offset difinitions*/ -#define KS8695_IO_CTRL0 0x4000 -#define KS8695_IO_CTRL1 0x4004 -#define KS8695_IO_CTRL2 0x4008 -#define KS8695_IO_CTRL3 0x400C - -/*memory control registers offset difinitions*/ -#define KS8695_MEM_CTRL0 0x4010 -#define KS8695_MEM_CTRL1 0x4014 -#define KS8695_MEM_CTRL2 0x4018 -#define KS8695_MEM_CTRL3 0x401C -#define KS8695_MEM_GENERAL 0x4020 -#define KS8695_SDRAM_CTRL0 0x4030 -#define KS8695_SDRAM_CTRL1 0x4034 -#define KS8695_SDRAM_GENERAL 0x4038 -#define KS8695_SDRAM_BUFFER 0x403C -#define KS8695_SDRAM_REFRESH 0x4040 - -/*WAN control registers offset difinitions*/ -#define KS8695_WAN_DMA_TX 0x6000 -#define KS8695_WAN_DMA_RX 0x6004 -#define KS8695_WAN_DMA_TX_START 0x6008 -#define KS8695_WAN_DMA_RX_START 0x600C -#define KS8695_WAN_TX_LIST 0x6010 -#define KS8695_WAN_RX_LIST 0x6014 -#define KS8695_WAN_MAC_LOW 0x6018 -#define KS8695_WAN_MAC_HIGH 0x601C -#define KS8695_WAN_MAC_ELOW 0x6080 -#define KS8695_WAN_MAC_EHIGH 0x6084 - -/*LAN control registers offset difinitions*/ -#define KS8695_LAN_DMA_TX 0x8000 -#define KS8695_LAN_DMA_RX 0x8004 -#define KS8695_LAN_DMA_TX_START 0x8008 -#define KS8695_LAN_DMA_RX_START 0x800C -#define KS8695_LAN_TX_LIST 0x8010 -#define KS8695_LAN_RX_LIST 0x8014 -#define KS8695_LAN_MAC_LOW 0x8018 -#define KS8695_LAN_MAC_HIGH 0x801C -#define KS8695_LAN_MAC_ELOW 0X8080 -#define KS8695_LAN_MAC_EHIGH 0X8084 - -/*HPNA control registers offset difinitions*/ -#define KS8695_HPNA_DMA_TX 0xA000 -#define KS8695_HPNA_DMA_RX 0xA004 -#define KS8695_HPNA_DMA_TX_START 0xA008 -#define KS8695_HPNA_DMA_RX_START 0xA00C -#define KS8695_HPNA_TX_LIST 0xA010 -#define KS8695_HPNA_RX_LIST 0xA014 -#define KS8695_HPNA_MAC_LOW 0xA018 -#define KS8695_HPNA_MAC_HIGH 0xA01C -#define KS8695_HPNA_MAC_ELOW 0xA080 -#define KS8695_HPNA_MAC_EHIGH 0xA084 - -/*UART control registers offset difinitions*/ -#define KS8695_UART_RX_BUFFER 0xE000 -#define KS8695_UART_TX_HOLDING 0xE004 - -#define KS8695_UART_FIFO_CTRL 0xE008 -#define KS8695_UART_FIFO_TRIG01 0x00 -#define KS8695_UART_FIFO_TRIG04 0x80 -#define KS8695_UART_FIFO_TXRST 0x03 -#define KS8695_UART_FIFO_RXRST 0x02 -#define KS8695_UART_FIFO_FEN 0x01 - -#define KS8695_UART_LINE_CTRL 0xE00C -#define KS8695_UART_LINEC_BRK 0x40 -#define KS8695_UART_LINEC_EPS 0x10 -#define KS8695_UART_LINEC_PEN 0x08 -#define KS8695_UART_LINEC_STP2 0x04 -#define KS8695_UART_LINEC_WLEN8 0x03 -#define KS8695_UART_LINEC_WLEN7 0x02 -#define KS8695_UART_LINEC_WLEN6 0x01 -#define KS8695_UART_LINEC_WLEN5 0x00 - -#define KS8695_UART_MODEM_CTRL 0xE010 -#define KS8695_UART_MODEMC_RTS 0x02 -#define KS8695_UART_MODEMC_DTR 0x01 - -#define KS8695_UART_LINE_STATUS 0xE014 -#define KS8695_UART_LINES_TXFE 0x20 -#define KS8695_UART_LINES_BE 0x10 -#define KS8695_UART_LINES_FE 0x08 -#define KS8695_UART_LINES_PE 0x04 -#define KS8695_UART_LINES_OE 0x02 -#define KS8695_UART_LINES_RXFE 0x01 -#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE) - -#define KS8695_UART_MODEM_STATUS 0xE018 -#define KS8695_UART_MODEM_DCD 0x80 -#define KS8695_UART_MODEM_DSR 0x20 -#define KS8695_UART_MODEM_CTS 0x10 -#define KS8695_UART_MODEM_DDCD 0x08 -#define KS8695_UART_MODEM_DDSR 0x02 -#define KS8695_UART_MODEM_DCTS 0x01 -#define UART8695_MODEM_ANY 0xFF - -#define KS8695_UART_DIVISOR 0xE01C -#define KS8695_UART_STATUS 0xE020 - -/*Interrupt controlller registers offset difinitions*/ -#define KS8695_INT_CONTL 0xE200 -#define KS8695_INT_ENABLE 0xE204 -#define KS8695_INT_ENABLE_MODEM 0x0800 -#define KS8695_INT_ENABLE_ERR 0x0400 -#define KS8695_INT_ENABLE_RX 0x0200 -#define KS8695_INT_ENABLE_TX 0x0100 - -#define KS8695_INT_STATUS 0xE208 -#define KS8695_INT_WAN_PRIORITY 0xE20C -#define KS8695_INT_HPNA_PRIORITY 0xE210 -#define KS8695_INT_LAN_PRIORITY 0xE214 -#define KS8695_INT_TIMER_PRIORITY 0xE218 -#define KS8695_INT_UART_PRIORITY 0xE21C -#define KS8695_INT_EXT_PRIORITY 0xE220 -#define KS8695_INT_CHAN_PRIORITY 0xE224 -#define KS8695_INT_BUSERROR_PRO 0xE228 -#define KS8695_INT_MASK_STATUS 0xE22C -#define KS8695_FIQ_PEND_PRIORITY 0xE230 -#define KS8695_IRQ_PEND_PRIORITY 0xE234 - -/*timer registers offset difinitions*/ -#define KS8695_TIMER_CTRL 0xE400 -#define KS8695_TIMER1 0xE404 -#define KS8695_TIMER0 0xE408 -#define KS8695_TIMER1_PCOUNT 0xE40C -#define KS8695_TIMER0_PCOUNT 0xE410 - -/*GPIO registers offset difinitions*/ -#define KS8695_GPIO_MODE 0xE600 -#define KS8695_GPIO_CTRL 0xE604 -#define KS8695_GPIO_DATA 0xE608 - -/*SWITCH registers offset difinitions*/ -#define KS8695_SWITCH_CTRL0 0xE800 -#define KS8695_SWITCH_CTRL1 0xE804 -#define KS8695_SWITCH_PORT1 0xE808 -#define KS8695_SWITCH_PORT2 0xE80C -#define KS8695_SWITCH_PORT3 0xE810 -#define KS8695_SWITCH_PORT4 0xE814 -#define KS8695_SWITCH_PORT5 0xE818 -#define KS8695_SWITCH_AUTO0 0xE81C -#define KS8695_SWITCH_AUTO1 0xE820 -#define KS8695_SWITCH_LUE_CTRL 0xE824 -#define KS8695_SWITCH_LUE_HIGH 0xE828 -#define KS8695_SWITCH_LUE_LOW 0xE82C -#define KS8695_SWITCH_ADVANCED 0xE830 - -#define KS8695_SWITCH_LPPM12 0xE874 -#define KS8695_SWITCH_LPPM34 0xE878 - -/*host communication registers difinitions*/ -#define KS8695_DSCP_HIGH 0xE834 -#define KS8695_DSCP_LOW 0xE838 -#define KS8695_SWITCH_MAC_HIGH 0xE83C -#define KS8695_SWITCH_MAC_LOW 0xE840 - -/*miscellaneours registers difinitions*/ -#define KS8695_MANAGE_COUNTER 0xE844 -#define KS8695_MANAGE_DATA 0xE848 -#define KS8695_LAN12_POWERMAGR 0xE84C -#define KS8695_LAN34_POWERMAGR 0xE850 - -#define KS8695_DEVICE_ID 0xEA00 -#define KS8695_REVISION_ID 0xEA04 - -#define KS8695_MISC_CONTROL 0xEA08 -#define KS8695_WAN_CONTROL 0xEA0C -#define KS8695_WAN_POWERMAGR 0xEA10 -#define KS8695_WAN_PHY_CONTROL 0xEA14 -#define KS8695_WAN_PHY_STATUS 0xEA18 - -/* bus clock definitions*/ -#define KS8695_BUS_CLOCK_125MHZ 0x0 -#define KS8695_BUS_CLOCK_100MHZ 0x1 -#define KS8695_BUS_CLOCK_62MHZ 0x2 -#define KS8695_BUS_CLOCK_50MHZ 0x3 -#define KS8695_BUS_CLOCK_41MHZ 0x4 -#define KS8695_BUS_CLOCK_33MHZ 0x5 -#define KS8695_BUS_CLOCK_31MHZ 0x6 -#define KS8695_BUS_CLOCK_25MHZ 0x7 - -/* ------------------------------------------------------------------------------- - * definations for IRQ - * -------------------------------------------------------------------------------*/ - -#define KS8695_INT_EXT_INT0 2 -#define KS8695_INT_EXT_INT1 3 -#define KS8695_INT_EXT_INT2 4 -#define KS8695_INT_EXT_INT3 5 -#define KS8695_INT_TIMERINT0 6 -#define KS8695_INT_TIMERINT1 7 -#define KS8695_INT_UART_TX 8 -#define KS8695_INT_UART_RX 9 -#define KS8695_INT_UART_LINE_ERR 10 -#define KS8695_INT_UART_MODEMS 11 -#define KS8695_INT_LAN_STOP_RX 12 -#define KS8695_INT_LAN_STOP_TX 13 -#define KS8695_INT_LAN_BUF_RX_STATUS 14 -#define KS8695_INT_LAN_BUF_TX_STATUS 15 -#define KS8695_INT_LAN_RX_STATUS 16 -#define KS8695_INT_LAN_TX_STATUS 17 -#define KS8695_INT_HPAN_STOP_RX 18 -#define KS8695_INT_HPNA_STOP_TX 19 -#define KS8695_INT_HPNA_BUF_RX_STATUS 20 -#define KS8695_INT_HPNA_BUF_TX_STATUS 21 -#define KS8695_INT_HPNA_RX_STATUS 22 -#define KS8695_INT_HPNA_TX_STATUS 23 -#define KS8695_INT_BUS_ERROR 24 -#define KS8695_INT_WAN_STOP_RX 25 -#define KS8695_INT_WAN_STOP_TX 26 -#define KS8695_INT_WAN_BUF_RX_STATUS 27 -#define KS8695_INT_WAN_BUF_TX_STATUS 28 -#define KS8695_INT_WAN_RX_STATUS 29 -#define KS8695_INT_WAN_TX_STATUS 30 - -#define KS8695_INT_UART KS8695_INT_UART_TX - -/* ------------------------------------------------------------------------------- - * Interrupt bit positions - * - * ------------------------------------------------------------------------------- - */ - -#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 ) -#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 ) -#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 ) -#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 ) -#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 ) -#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 ) -#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX ) -#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX ) -#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR ) -#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS ) -#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX ) -#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX ) -#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX ) -#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX ) -#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS ) -#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS -#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS ) -#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS ) -#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR ) -#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX ) -#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX ) -#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS ) -#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS ) - -#define KS8695_SC_VALID_INT 0xFFFFFFFF -#define MAXIRQNUM 31 - -/* - * Timer definitions - * - * Use timer 1 & 2 - * (both run at 25MHz). - * - */ -#define TICKS_PER_uSEC 25 -#define mSEC_1 1000 -#define mSEC_10 (mSEC_1 * 10) - -#endif - -/* END */ diff --git a/include/asm-arm/arch-lpc2292/hardware.h b/include/asm-arm/arch-lpc2292/hardware.h deleted file mode 100644 index 5e227e3..0000000 --- a/include/asm-arm/arch-lpc2292/hardware.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if defined(CONFIG_LPC2292) -#include -#else -#error No hardware file defined for this configuration -#endif - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-lpc2292/lpc2292_registers.h b/include/asm-arm/arch-lpc2292/lpc2292_registers.h deleted file mode 100644 index 5715f3e..0000000 --- a/include/asm-arm/arch-lpc2292/lpc2292_registers.h +++ /dev/null @@ -1,225 +0,0 @@ -#ifndef __LPC2292_REGISTERS_H -#define __LPC2292_REGISTERS_H - -#include - -/* Macros for reading/writing registers */ -#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) -#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) -#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) -#define GET8(reg) (*(volatile unsigned char*)(reg)) -#define GET16(reg) (*(volatile unsigned short*)(reg)) -#define GET32(reg) (*(volatile unsigned int*)(reg)) - -/* External Memory Controller */ - -#define BCFG0 0xFFE00000 /* 32-bits */ -#define BCFG1 0xFFE00004 /* 32-bits */ -#define BCFG2 0xFFE00008 /* 32-bits */ -#define BCFG3 0xFFE0000c /* 32-bits */ - -/* System Control Block */ - -#define EXTINT 0xE01FC140 -#define EXTWAKE 0xE01FC144 -#define EXTMODE 0xE01FC148 -#define EXTPOLAR 0xE01FC14C -#define MEMMAP 0xE01FC040 -#define PLLCON 0xE01FC080 -#define PLLCFG 0xE01FC084 -#define PLLSTAT 0xE01FC088 -#define PLLFEED 0xE01FC08C -#define PCON 0xE01FC0C0 -#define PCONP 0xE01FC0C4 -#define VPBDIV 0xE01FC100 - -/* Memory Acceleration Module */ - -#define MAMCR 0xE01FC000 -#define MAMTIM 0xE01FC004 - -/* Vectored Interrupt Controller */ - -#define VICIRQStatus 0xFFFFF000 -#define VICFIQStatus 0xFFFFF004 -#define VICRawIntr 0xFFFFF008 -#define VICIntSelect 0xFFFFF00C -#define VICIntEnable 0xFFFFF010 -#define VICIntEnClr 0xFFFFF014 -#define VICSoftInt 0xFFFFF018 -#define VICSoftIntClear 0xFFFFF01C -#define VICProtection 0xFFFFF020 -#define VICVectAddr 0xFFFFF030 -#define VICDefVectAddr 0xFFFFF034 -#define VICVectAddr0 0xFFFFF100 -#define VICVectAddr1 0xFFFFF104 -#define VICVectAddr2 0xFFFFF108 -#define VICVectAddr3 0xFFFFF10C -#define VICVectAddr4 0xFFFFF110 -#define VICVectAddr5 0xFFFFF114 -#define VICVectAddr6 0xFFFFF118 -#define VICVectAddr7 0xFFFFF11C -#define VICVectAddr8 0xFFFFF120 -#define VICVectAddr9 0xFFFFF124 -#define VICVectAddr10 0xFFFFF128 -#define VICVectAddr11 0xFFFFF12C -#define VICVectAddr12 0xFFFFF130 -#define VICVectAddr13 0xFFFFF134 -#define VICVectAddr14 0xFFFFF138 -#define VICVectAddr15 0xFFFFF13C -#define VICVectCntl0 0xFFFFF200 -#define VICVectCntl1 0xFFFFF204 -#define VICVectCntl2 0xFFFFF208 -#define VICVectCntl3 0xFFFFF20C -#define VICVectCntl4 0xFFFFF210 -#define VICVectCntl5 0xFFFFF214 -#define VICVectCntl6 0xFFFFF218 -#define VICVectCntl7 0xFFFFF21C -#define VICVectCntl8 0xFFFFF220 -#define VICVectCntl9 0xFFFFF224 -#define VICVectCntl10 0xFFFFF228 -#define VICVectCntl11 0xFFFFF22C -#define VICVectCntl12 0xFFFFF230 -#define VICVectCntl13 0xFFFFF234 -#define VICVectCntl14 0xFFFFF238 -#define VICVectCntl15 0xFFFFF23C - -/* Pin connect block */ - -#define PINSEL0 0xE002C000 /* 32 bits */ -#define PINSEL1 0xE002C004 /* 32 bits */ -#define PINSEL2 0xE002C014 /* 32 bits */ - -/* GPIO */ - -#define IO0PIN 0xE0028000 -#define IO0SET 0xE0028004 -#define IO0DIR 0xE0028008 -#define IO0CLR 0xE002800C -#define IO1PIN 0xE0028010 -#define IO1SET 0xE0028014 -#define IO1DIR 0xE0028018 -#define IO1CLR 0xE002801C -#define IO2PIN 0xE0028020 -#define IO2SET 0xE0028024 -#define IO2DIR 0xE0028028 -#define IO2CLR 0xE002802C -#define IO3PIN 0xE0028030 -#define IO3SET 0xE0028034 -#define IO3DIR 0xE0028038 -#define IO3CLR 0xE002803C - -/* Uarts */ - -#define U0RBR 0xE000C000 -#define U0THR 0xE000C000 -#define U0IER 0xE000C004 -#define U0IIR 0xE000C008 -#define U0FCR 0xE000C008 -#define U0LCR 0xE000C00C -#define U0LSR 0xE000C014 -#define U0SCR 0xE000C01C -#define U0DLL 0xE000C000 -#define U0DLM 0xE000C004 - -#define U1RBR 0xE0010000 -#define U1THR 0xE0010000 -#define U1IER 0xE0010004 -#define U1IIR 0xE0010008 -#define U1FCR 0xE0010008 -#define U1LCR 0xE001000C -#define U1MCR 0xE0010010 -#define U1LSR 0xE0010014 -#define U1MSR 0xE0010018 -#define U1SCR 0xE001001C -#define U1DLL 0xE0010000 -#define U1DLM 0xE0010004 - -/* I2C */ - -#define I2CONSET 0xE001C000 -#define I2STAT 0xE001C004 -#define I2DAT 0xE001C008 -#define I2ADR 0xE001C00C -#define I2SCLH 0xE001C010 -#define I2SCLL 0xE001C014 -#define I2CONCLR 0xE001C018 - -/* SPI */ - -#define S0SPCR 0xE0020000 -#define S0SPSR 0xE0020004 -#define S0SPDR 0xE0020008 -#define S0SPCCR 0xE002000C -#define S0SPINT 0xE002001C - -#define S1SPCR 0xE0030000 -#define S1SPSR 0xE0030004 -#define S1SPDR 0xE0030008 -#define S1SPCCR 0xE003000C -#define S1SPINT 0xE003001C - -/* CAN controller */ - -/* skip for now */ - -/* Timers */ - -#define T0IR 0xE0004000 -#define T0TCR 0xE0004004 -#define T0TC 0xE0004008 -#define T0PR 0xE000400C -#define T0PC 0xE0004010 -#define T0MCR 0xE0004014 -#define T0MR0 0xE0004018 -#define T0MR1 0xE000401C -#define T0MR2 0xE0004020 -#define T0MR3 0xE0004024 -#define T0CCR 0xE0004028 -#define T0CR0 0xE000402C -#define T0CR1 0xE0004030 -#define T0CR2 0xE0004034 -#define T0CR3 0xE0004038 -#define T0EMR 0xE000403C - -#define T1IR 0xE0008000 -#define T1TCR 0xE0008004 -#define T1TC 0xE0008008 -#define T1PR 0xE000800C -#define T1PC 0xE0008010 -#define T1MCR 0xE0008014 -#define T1MR0 0xE0008018 -#define T1MR1 0xE000801C -#define T1MR2 0xE0008020 -#define T1MR3 0xE0008024 -#define T1CCR 0xE0008028 -#define T1CR0 0xE000802C -#define T1CR1 0xE0008030 -#define T1CR2 0xE0008034 -#define T1CR3 0xE0008038 -#define T1EMR 0xE000803C - -/* PWM */ - -/* skip for now */ - -/* A/D converter */ - -/* skip for now */ - -/* Real Time Clock */ - -/* skip for now */ - -/* Watchdog */ - -#define WDMOD 0xE0000000 -#define WDTC 0xE0000004 -#define WDFEED 0xE0000008 -#define WDTV 0xE000000C - -/* EmbeddedICE LOGIC */ - -/* skip for now */ - -#endif diff --git a/include/asm-arm/arch-lpc2292/spi.h b/include/asm-arm/arch-lpc2292/spi.h deleted file mode 100644 index 6ae66e8..0000000 --- a/include/asm-arm/arch-lpc2292/spi.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - This file defines the interface to the lpc22xx SPI module. - Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) - - This file may be included in software not adhering to the GPL. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#ifndef SPI_H -#define SPI_H - -#include -#include -#include -#include - -#define SPIF 0x80 - -#define spi_lock() disable_interrupts(); -#define spi_unlock() enable_interrupts(); - -extern unsigned long spi_flags; -extern unsigned char spi_idle; - -int spi_init(void); - -static inline unsigned char spi_read(void) -{ - unsigned char b; - - PUT8(S0SPDR, spi_idle); - while (!(GET8(S0SPSR) & SPIF)); - b = GET8(S0SPDR); - - return b; -} - -static inline void spi_write(unsigned char b) -{ - PUT8(S0SPDR, b); - while (!(GET8(S0SPSR) & SPIF)); - GET8(S0SPDR); /* this will clear the SPIF bit */ -} - -static inline void spi_set_clock(unsigned char clk_value) -{ - PUT8(S0SPCCR, clk_value); -} - -static inline void spi_set_cfg(unsigned char phase, - unsigned char polarity, - unsigned char lsbf) -{ - unsigned char v = 0x20; /* master bit set */ - - if (phase) - v |= 0x08; /* set phase bit */ - if (polarity) { - v |= 0x10; /* set polarity bit */ - spi_idle = 0xFF; - } else { - spi_idle = 0x00; - } - if (lsbf) - v |= 0x40; /* set lsbf bit */ - - PUT8(S0SPCR, v); -} -#endif /* SPI_H */ diff --git a/include/asm-arm/arch-mx25/clock.h b/include/asm-arm/arch-mx25/clock.h deleted file mode 100644 index c59f588..0000000 --- a/include/asm-arm/arch-mx25/clock.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * - * (c) 2009 Ilya Yanok, Emcraft Systems - * - * Modified for mx25 by John Rigby - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -ulong imx_get_perclk(int clk); -ulong imx_get_ahbclk(void); - -#define imx_get_uartclk() imx_get_perclk(15) -#define imx_get_fecclk() (imx_get_ahbclk()/2) - - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/include/asm-arm/arch-mx25/imx-regs.h b/include/asm-arm/arch-mx25/imx-regs.h deleted file mode 100644 index f709bd8..0000000 --- a/include/asm-arm/arch-mx25/imx-regs.h +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (C) 2009, DENX Software Engineering - * Author: John Rigby - * and arch-mx27/imx-regs.h - * Copyright (C) 2007 Pengutronix, - * Sascha Hauer - * Copyright (C) 2009 Ilya Yanok, - * Emcraft Systems - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -#ifndef __ASSEMBLY__ -#ifdef CONFIG_FEC_MXC -extern void mx25_fec_init_pins(void); -#endif - -/* Clock Control Module (CCM) registers */ -struct ccm_regs { - u32 mpctl; /* Core PLL Control */ - u32 upctl; /* USB PLL Control */ - u32 cctl; /* Clock Control */ - u32 cgr0; /* Clock Gating Control 0 */ - u32 cgr1; /* Clock Gating Control 1 */ - u32 cgr2; /* Clock Gating Control 2 */ - u32 pcdr[4]; /* PER Clock Dividers */ - u32 rcsr; /* CCM Status */ - u32 crdr; /* CCM Reset and Debug */ - u32 dcvr0; /* DPTC Comparator Value 0 */ - u32 dcvr1; /* DPTC Comparator Value 1 */ - u32 dcvr2; /* DPTC Comparator Value 2 */ - u32 dcvr3; /* DPTC Comparator Value 3 */ - u32 ltr0; /* Load Tracking 0 */ - u32 ltr1; /* Load Tracking 1 */ - u32 ltr2; /* Load Tracking 2 */ - u32 ltr3; /* Load Tracking 3 */ - u32 ltbr0; /* Load Tracking Buffer 0 */ - u32 ltbr1; /* Load Tracking Buffer 1 */ - u32 pcmr0; /* Power Management Control 0 */ - u32 pcmr1; /* Power Management Control 1 */ - u32 pcmr2; /* Power Management Control 2 */ - u32 mcr; /* Miscellaneous Control */ - u32 lpimr0; /* Low Power Interrupt Mask 0 */ - u32 lpimr1; /* Low Power Interrupt Mask 1 */ -}; - -/* Enhanced SDRAM Controller (ESDRAMC) registers */ -struct esdramc_regs { - u32 ctl0; /* control 0 */ - u32 cfg0; /* configuration 0 */ - u32 ctl1; /* control 1 */ - u32 cfg1; /* configuration 1 */ - u32 misc; /* miscellaneous */ - u32 pad[3]; - u32 cdly1; /* Delay Line 1 configuration debug */ - u32 cdly2; /* delay line 2 configuration debug */ - u32 cdly3; /* delay line 3 configuration debug */ - u32 cdly4; /* delay line 4 configuration debug */ - u32 cdly5; /* delay line 5 configuration debug */ - u32 cdlyl; /* delay line cycle length debug */ -}; - -/* GPIO registers */ -struct gpio_regs { - u32 dr; /* data */ - u32 dir; /* direction */ - u32 psr; /* pad satus */ - u32 icr1; /* interrupt config 1 */ - u32 icr2; /* interrupt config 2 */ - u32 imr; /* interrupt mask */ - u32 isr; /* interrupt status */ - u32 edge_sel; /* edge select */ -}; - -/* General Purpose Timer (GPT) registers */ -struct gpt_regs { - u32 ctrl; /* control */ - u32 pre; /* prescaler */ - u32 stat; /* status */ - u32 intr; /* interrupt */ - u32 cmp[3]; /* output compare 1-3 */ - u32 capt[2]; /* input capture 1-2 */ - u32 counter; /* counter */ -}; - -/* Watchdog Timer (WDOG) registers */ -struct wdog_regs { - u32 wcr; /* Control */ - u32 wsr; /* Service */ - u32 wrsr; /* Reset Status */ - u32 wicr; /* Interrupt Control */ - u32 wmcr; /* Misc Control */ -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prog_p; - u32 res1[0x1f5]; - u32 iim_bank_area0[0x20]; - u32 res2[0xe0]; - u32 iim_bank_area1[0x20]; - u32 res3[0xe0]; - u32 iim_bank_area2[0x20]; -}; -#endif - -/* AIPS 1 */ -#define IMX_AIPS1_BASE (0x43F00000) -#define IMX_MAX_BASE (0x43F04000) -#define IMX_CLKCTL_BASE (0x43F08000) -#define IMX_ETB_SLOT4_BASE (0x43F0C000) -#define IMX_ETB_SLOT5_BASE (0x43F10000) -#define IMX_ECT_CTIO_BASE (0x43F18000) -#define IMX_I2C_BASE (0x43F80000) -#define IMX_I2C3_BASE (0x43F84000) -#define IMX_CAN1_BASE (0x43F88000) -#define IMX_CAN2_BASE (0x43F8C000) -#define IMX_UART1_BASE (0x43F90000) -#define IMX_UART2_BASE (0x43F94000) -#define IMX_I2C2_BASE (0x43F98000) -#define IMX_OWIRE_BASE (0x43F9C000) -#define IMX_CSPI1_BASE (0x43FA4000) -#define IMX_KPP_BASE (0x43FA8000) -#define IMX_IOPADMUX_BASE (0x43FAC000) -#define IMX_IOPADCTL_BASE (0x43FAC22C) -#define IMX_IOPADGRPCTL_BASE (0x43FAC418) -#define IMX_IOPADINPUTSEL_BASE (0x43FAC460) -#define IMX_AUDMUX_BASE (0x43FB0000) -#define IMX_ECT_IP1_BASE (0x43FB8000) -#define IMX_ECT_IP2_BASE (0x43FBC000) - -/* SPBA */ -#define IMX_SPBA_BASE (0x50000000) -#define IMX_CSPI3_BASE (0x50004000) -#define IMX_UART4_BASE (0x50008000) -#define IMX_UART3_BASE (0x5000C000) -#define IMX_CSPI2_BASE (0x50010000) -#define IMX_SSI2_BASE (0x50014000) -#define IMX_ESAI_BASE (0x50018000) -#define IMX_ATA_DMA_BASE (0x50020000) -#define IMX_SIM1_BASE (0x50024000) -#define IMX_SIM2_BASE (0x50028000) -#define IMX_UART5_BASE (0x5002C000) -#define IMX_TSC_BASE (0x50030000) -#define IMX_SSI1_BASE (0x50034000) -#define IMX_FEC_BASE (0x50038000) -#define IMX_SPBA_CTRL_BASE (0x5003C000) - -/* AIPS 2 */ -#define IMX_AIPS2_BASE (0x53F00000) -#define IMX_CCM_BASE (0x53F80000) -#define IMX_GPT4_BASE (0x53F84000) -#define IMX_GPT3_BASE (0x53F88000) -#define IMX_GPT2_BASE (0x53F8C000) -#define IMX_GPT1_BASE (0x53F90000) -#define IMX_EPIT1_BASE (0x53F94000) -#define IMX_EPIT2_BASE (0x53F98000) -#define IMX_GPIO4_BASE (0x53F9C000) -#define IMX_PWM2_BASE (0x53FA0000) -#define IMX_GPIO3_BASE (0x53FA4000) -#define IMX_PWM3_BASE (0x53FA8000) -#define IMX_SCC_BASE (0x53FAC000) -#define IMX_SCM_BASE (0x53FAE000) -#define IMX_SMN_BASE (0x53FAF000) -#define IMX_RNGD_BASE (0x53FB0000) -#define IMX_MMC_SDHC1_BASE (0x53FB4000) -#define IMX_MMC_SDHC2_BASE (0x53FB8000) -#define IMX_LCDC_BASE (0x53FBC000) -#define IMX_SLCDC_BASE (0x53FC0000) -#define IMX_PWM4_BASE (0x53FC8000) -#define IMX_GPIO1_BASE (0x53FCC000) -#define IMX_GPIO2_BASE (0x53FD0000) -#define IMX_SDMA_BASE (0x53FD4000) -#define IMX_WDT_BASE (0x53FDC000) -#define IMX_PWM1_BASE (0x53FE0000) -#define IMX_RTIC_BASE (0x53FEC000) -#define IMX_IIM_BASE (0x53FF0000) -#define IMX_USB_BASE (0x53FF4000) -#define IMX_CSI_BASE (0x53FF8000) -#define IMX_DRYICE_BASE (0x53FFC000) - -#define IMX_ARM926_ROMPATCH (0x60000000) -#define IMX_ARM926_ASIC (0x68000000) - -/* 128K Internal Static RAM */ -#define IMX_RAM_BASE (0x78000000) - -/* SDRAM BANKS */ -#define IMX_SDRAM_BANK0_BASE (0x80000000) -#define IMX_SDRAM_BANK1_BASE (0x90000000) - -#define IMX_WEIM_CS0 (0xA0000000) -#define IMX_WEIM_CS1 (0xA8000000) -#define IMX_WEIM_CS2 (0xB0000000) -#define IMX_WEIM_CS3 (0xB2000000) -#define IMX_WEIM_CS4 (0xB4000000) -#define IMX_ESDRAMC_BASE (0xB8001000) -#define IMX_WEIM_CTRL_BASE (0xB8002000) -#define IMX_M3IF_CTRL_BASE (0xB8003000) -#define IMX_EMI_CTRL_BASE (0xB8004000) - -/* NAND Flash Controller */ -#define IMX_NFC_BASE (0xBB000000) -#define NFC_BASE_ADDR IMX_NFC_BASE - -/* CCM bitfields */ -#define CCM_PLL_MFI_SHIFT 10 -#define CCM_PLL_MFI_MASK 0xf -#define CCM_PLL_MFN_SHIFT 0 -#define CCM_PLL_MFN_MASK 0x3ff -#define CCM_PLL_MFD_SHIFT 16 -#define CCM_PLL_MFD_MASK 0x3ff -#define CCM_PLL_PD_SHIFT 26 -#define CCM_PLL_PD_MASK 0xf -#define CCM_CCTL_ARM_DIV_SHIFT 30 -#define CCM_CCTL_ARM_DIV_MASK 3 -#define CCM_CCTL_AHB_DIV_SHIFT 28 -#define CCM_CCTL_AHB_DIV_MASK 3 -#define CCM_CCTL_ARM_SRC (1 << 14) -#define CCM_CGR1_GPT1 (1 << 19) -#define CCM_PERCLK_REG(clk) (clk / 4) -#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) -#define CCM_PERCLK_MASK 0x3f -#define CCM_RCSR_NF_16BIT_SEL (1 << 14) -#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) - -/* ESDRAM Controller register bitfields */ -#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) -#define ESDCTL_DSIZ_32 (2 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) - -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) - -/* GPT bits */ -#define GPT_CTRL_SWR (1 << 15) /* Software reset */ -#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ -#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ -#define GPT_CTRL_TEN 1 /* Timer enable */ - -/* WDOG enable */ -#define WCR_WDE 0x04 - -/* FUSE bank offsets */ -#define IIM0_MAC 0x1a - -#endif /* _IMX_REGS_H */ diff --git a/include/asm-arm/arch-mx25/imx25-pinmux.h b/include/asm-arm/arch-mx25/imx25-pinmux.h deleted file mode 100644 index a4c658b..0000000 --- a/include/asm-arm/arch-mx25/imx25-pinmux.h +++ /dev/null @@ -1,421 +0,0 @@ -/* - * iopin settings are controlled by four different sets of registers - * iopad mux control - * individual iopad setup (voltage select, pull/keep, drive strength ...) - * group iopad setup (same as above but for groups of signals) - * input select when multiple inputs are possible - */ - -/* - * software pad mux control - */ -/* SW Input On (Loopback) */ -#define MX25_PIN_MUX_SION (1 << 4) -/* MUX Mode (0-7) */ -#define MX25_PIN_MUX_MODE(mode) ((mode & 0x7) << 0) -struct iomuxc_mux_ctl { - u32 gpr1; - u32 observe_int_mux; - u32 pad_a10; - u32 pad_a13; - u32 pad_a14; - u32 pad_a15; - u32 pad_a16; - u32 pad_a17; - u32 pad_a18; - u32 pad_a19; - u32 pad_a20; - u32 pad_a21; - u32 pad_a22; - u32 pad_a23; - u32 pad_a24; - u32 pad_a25; - u32 pad_eb0; - u32 pad_eb1; - u32 pad_oe; - u32 pad_cs0; - u32 pad_cs1; - u32 pad_cs4; - u32 pad_cs5; - u32 pad_nf_ce0; - u32 pad_ecb; - u32 pad_lba; - u32 pad_bclk; - u32 pad_rw; - u32 pad_nfwe_b; - u32 pad_nfre_b; - u32 pad_nfale; - u32 pad_nfcle; - u32 pad_nfwp_b; - u32 pad_nfrb; - u32 pad_d15; - u32 pad_d14; - u32 pad_d13; - u32 pad_d12; - u32 pad_d11; - u32 pad_d10; - u32 pad_d9; - u32 pad_d8; - u32 pad_d7; - u32 pad_d6; - u32 pad_d5; - u32 pad_d4; - u32 pad_d3; - u32 pad_d2; - u32 pad_d1; - u32 pad_d0; - u32 pad_ld0; - u32 pad_ld1; - u32 pad_ld2; - u32 pad_ld3; - u32 pad_ld4; - u32 pad_ld5; - u32 pad_ld6; - u32 pad_ld7; - u32 pad_ld8; - u32 pad_ld9; - u32 pad_ld10; - u32 pad_ld11; - u32 pad_ld12; - u32 pad_ld13; - u32 pad_ld14; - u32 pad_ld15; - u32 pad_hsync; - u32 pad_vsync; - u32 pad_lsclk; - u32 pad_oe_acd; - u32 pad_contrast; - u32 pad_pwm; - u32 pad_csi_d2; - u32 pad_csi_d3; - u32 pad_csi_d4; - u32 pad_csi_d5; - u32 pad_csi_d6; - u32 pad_csi_d7; - u32 pad_csi_d8; - u32 pad_csi_d9; - u32 pad_csi_mclk; - u32 pad_csi_vsync; - u32 pad_csi_hsync; - u32 pad_csi_pixclk; - u32 pad_i2c1_clk; - u32 pad_i2c1_dat; - u32 pad_cspi1_mosi; - u32 pad_cspi1_miso; - u32 pad_cspi1_ss0; - u32 pad_cspi1_ss1; - u32 pad_cspi1_sclk; - u32 pad_cspi1_rdy; - u32 pad_uart1_rxd; - u32 pad_uart1_txd; - u32 pad_uart1_rts; - u32 pad_uart1_cts; - u32 pad_uart2_rxd; - u32 pad_uart2_txd; - u32 pad_uart2_rts; - u32 pad_uart2_cts; - u32 pad_sd1_cmd; - u32 pad_sd1_clk; - u32 pad_sd1_data0; - u32 pad_sd1_data1; - u32 pad_sd1_data2; - u32 pad_sd1_data3; - u32 pad_kpp_row0; - u32 pad_kpp_row1; - u32 pad_kpp_row2; - u32 pad_kpp_row3; - u32 pad_kpp_col0; - u32 pad_kpp_col1; - u32 pad_kpp_col2; - u32 pad_kpp_col3; - u32 pad_fec_mdc; - u32 pad_fec_mdio; - u32 pad_fec_tdata0; - u32 pad_fec_tdata1; - u32 pad_fec_tx_en; - u32 pad_fec_rdata0; - u32 pad_fec_rdata1; - u32 pad_fec_rx_dv; - u32 pad_fec_tx_clk; - u32 pad_rtck; - u32 pad_de_b; - u32 pad_gpio_a; - u32 pad_gpio_b; - u32 pad_gpio_c; - u32 pad_gpio_d; - u32 pad_gpio_e; - u32 pad_gpio_f; - u32 pad_ext_armclk; - u32 pad_upll_bypclk; - u32 pad_vstby_req; - u32 pad_vstby_ack; - u32 pad_power_fail; - u32 pad_clko; - u32 pad_boot_mode0; - u32 pad_boot_mode1; -}; - -/* - * software pad control - */ -/* Select 3.3 or 1.8 volts */ -#define MX25_PIN_PAD_CTL_DVS_33 (0 << 13) -#define MX25_PIN_PAD_CTL_DVS_18 (1 << 13) -/* Enable hysteresis */ -#define MX25_PIN_PAD_CTL_HYS (1 << 8) -/* Enable pull/keeper */ -#define MX25_PIN_PAD_CTL_PKE (1 << 7) -/* 0 - keeper / 1 - pull */ -#define MX25_PIN_PAD_CTL_PUE (1 << 6) -/* pull up/down strength */ -#define MX25_PIN_PAD_CTL_100K_PD (0 << 4) -#define MX25_PIN_PAD_CTL_47K_PU (1 << 4) -#define MX25_PIN_PAD_CTL_100K_PU (2 << 4) -#define MX25_PIN_PAD_CTL_22K_PU (3 << 4) -/* open drain control */ -#define MX25_PIN_PAD_CTL_OD (1 << 3) -/* drive strength */ -#define MX25_PIN_PAD_CTL_DS_NOM (0 << 1) -#define MX25_PIN_PAD_CTL_DS_HIGH (1 << 1) -#define MX25_PIN_PAD_CTL_DS_MAX (2 << 1) -#define MX25_PIN_PAD_CTL_DS_MAX11 (3 << 1) -/* slew rate */ -#define MX25_PIN_PAD_CTL_SRE_SLOW (0 << 0) -#define MX25_PIN_PAD_CTL_SRE_FAST (1 << 0) -struct iomuxc_pad_ctl { - u32 pad_a13; - u32 pad_a14; - u32 pad_a15; - u32 pad_a17; - u32 pad_a18; - u32 pad_a19; - u32 pad_a20; - u32 pad_a21; - u32 pad_a23; - u32 pad_a24; - u32 pad_a25; - u32 pad_eb0; - u32 pad_eb1; - u32 pad_oe; - u32 pad_cs4; - u32 pad_cs5; - u32 pad_nf_ce0; - u32 pad_ecb; - u32 pad_lba; - u32 pad_rw; - u32 pad_nfrb; - u32 pad_d15; - u32 pad_d14; - u32 pad_d13; - u32 pad_d12; - u32 pad_d11; - u32 pad_d10; - u32 pad_d9; - u32 pad_d8; - u32 pad_d7; - u32 pad_d6; - u32 pad_d5; - u32 pad_d4; - u32 pad_d3; - u32 pad_d2; - u32 pad_d1; - u32 pad_d0; - u32 pad_ld0; - u32 pad_ld1; - u32 pad_ld2; - u32 pad_ld3; - u32 pad_ld4; - u32 pad_ld5; - u32 pad_ld6; - u32 pad_ld7; - u32 pad_ld8; - u32 pad_ld9; - u32 pad_ld10; - u32 pad_ld11; - u32 pad_ld12; - u32 pad_ld13; - u32 pad_ld14; - u32 pad_ld15; - u32 pad_hsync; - u32 pad_vsync; - u32 pad_lsclk; - u32 pad_oe_acd; - u32 pad_contrast; - u32 pad_pwm; - u32 pad_csi_d2; - u32 pad_csi_d3; - u32 pad_csi_d4; - u32 pad_csi_d5; - u32 pad_csi_d6; - u32 pad_csi_d7; - u32 pad_csi_d8; - u32 pad_csi_d9; - u32 pad_csi_mclk; - u32 pad_csi_vsync; - u32 pad_csi_hsync; - u32 pad_csi_pixclk; - u32 pad_i2c1_clk; - u32 pad_i2c1_dat; - u32 pad_cspi1_mosi; - u32 pad_cspi1_miso; - u32 pad_cspi1_ss0; - u32 pad_cspi1_ss1; - u32 pad_cspi1_sclk; - u32 pad_cspi1_rdy; - u32 pad_uart1_rxd; - u32 pad_uart1_txd; - u32 pad_uart1_rts; - u32 pad_uart1_cts; - u32 pad_uart2_rxd; - u32 pad_uart2_txd; - u32 pad_uart2_rts; - u32 pad_uart2_cts; - u32 pad_sd1_cmd; - u32 pad_sd1_clk; - u32 pad_sd1_data0; - u32 pad_sd1_data1; - u32 pad_sd1_data2; - u32 pad_sd1_data3; - u32 pad_kpp_row0; - u32 pad_kpp_row1; - u32 pad_kpp_row2; - u32 pad_kpp_row3; - u32 pad_kpp_col0; - u32 pad_kpp_col1; - u32 pad_kpp_col2; - u32 pad_kpp_col3; - u32 pad_fec_mdc; - u32 pad_fec_mdio; - u32 pad_fec_tdata0; - u32 pad_fec_tdata1; - u32 pad_fec_tx_en; - u32 pad_fec_rdata0; - u32 pad_fec_rdata1; - u32 pad_fec_rx_dv; - u32 pad_fec_tx_clk; - u32 pad_rtck; - u32 pad_tdo; - u32 pad_de_b; - u32 pad_gpio_a; - u32 pad_gpio_b; - u32 pad_gpio_c; - u32 pad_gpio_d; - u32 pad_gpio_e; - u32 pad_gpio_f; - u32 pad_vstby_req; - u32 pad_vstby_ack; - u32 pad_power_fail; - u32 pad_clko; -}; - - -/* - * Pad group drive strength and voltage select - * Same fields as iomuxc_pad_ctl plus ddr type - */ -/* Select DDR type */ -#define MX25_PIN_PAD_CTL_DDR_18 (0 << 11) -#define MX25_PIN_PAD_CTL_DDR_33 (1 << 11) -#define MX25_PIN_PAD_CTL_DDR_MAX (2 << 11) -struct iomuxc_pad_grp_ctl { - u32 grp_dvs_misc; - u32 grp_dse_fec; - u32 grp_dvs_jtag; - u32 grp_dse_nfc; - u32 grp_dse_csi; - u32 grp_dse_weim; - u32 grp_dse_ddr; - u32 grp_dvs_crm; - u32 grp_dse_kpp; - u32 grp_dse_sdhc1; - u32 grp_dse_lcd; - u32 grp_dse_uart; - u32 grp_dvs_nfc; - u32 grp_dvs_csi; - u32 grp_dse_cspi1; - u32 grp_ddrtype; - u32 grp_dvs_sdhc1; - u32 grp_dvs_lcd; -}; - -/* - * Pad input select control - * Select which pad to connect to an input port - * where multiple pads can function as given input - */ -#define MX25_PAD_INPUT_SELECT_DAISY(in) ((in & 0x7) << 0) -struct iomuxc_pad_input_select { - u32 audmux_p4_input_da_amx; - u32 audmux_p4_input_db_amx; - u32 audmux_p4_input_rxclk_amx; - u32 audmux_p4_input_rxfs_amx; - u32 audmux_p4_input_txclk_amx; - u32 audmux_p4_input_txfs_amx; - u32 audmux_p7_input_da_amx; - u32 audmux_p7_input_txfs_amx; - u32 can1_ipp_ind_canrx; - u32 can2_ipp_ind_canrx; - u32 csi_ipp_csi_d_0; - u32 csi_ipp_csi_d_1; - u32 cspi1_ipp_ind_ss3_b; - u32 cspi2_ipp_cspi_clk_in; - u32 cspi2_ipp_ind_dataready_b; - u32 cspi2_ipp_ind_miso; - u32 cspi2_ipp_ind_mosi; - u32 cspi2_ipp_ind_ss0_b; - u32 cspi2_ipp_ind_ss1_b; - u32 cspi3_ipp_cspi_clk_in; - u32 cspi3_ipp_ind_dataready_b; - u32 cspi3_ipp_ind_miso; - u32 cspi3_ipp_ind_mosi; - u32 cspi3_ipp_ind_ss0_b; - u32 cspi3_ipp_ind_ss1_b; - u32 cspi3_ipp_ind_ss2_b; - u32 cspi3_ipp_ind_ss3_b; - u32 esdhc1_ipp_dat4_in; - u32 esdhc1_ipp_dat5_in; - u32 esdhc1_ipp_dat6_in; - u32 esdhc1_ipp_dat7_in; - u32 esdhc2_ipp_card_clk_in; - u32 esdhc2_ipp_cmd_in; - u32 esdhc2_ipp_dat0_in; - u32 esdhc2_ipp_dat1_in; - u32 esdhc2_ipp_dat2_in; - u32 esdhc2_ipp_dat3_in; - u32 esdhc2_ipp_dat4_in; - u32 esdhc2_ipp_dat5_in; - u32 esdhc2_ipp_dat6_in; - u32 esdhc2_ipp_dat7_in; - u32 fec_fec_col; - u32 fec_fec_crs; - u32 fec_fec_rdata_2; - u32 fec_fec_rdata_3; - u32 fec_fec_rx_clk; - u32 fec_fec_rx_er; - u32 i2c2_ipp_scl_in; - u32 i2c2_ipp_sda_in; - u32 i2c3_ipp_scl_in; - u32 i2c3_ipp_sda_in; - u32 kpp_ipp_ind_col_4; - u32 kpp_ipp_ind_col_5; - u32 kpp_ipp_ind_col_6; - u32 kpp_ipp_ind_col_7; - u32 kpp_ipp_ind_row_4; - u32 kpp_ipp_ind_row_5; - u32 kpp_ipp_ind_row_6; - u32 kpp_ipp_ind_row_7; - u32 sim1_pin_sim_rcvd1_in; - u32 sim1_pin_sim_simpd1; - u32 sim1_sim_rcvd1_io; - u32 sim2_pin_sim_rcvd1_in; - u32 sim2_pin_sim_simpd1; - u32 sim2_sim_rcvd1_io; - u32 uart3_ipp_uart_rts_b; - u32 uart3_ipp_uart_rxd_mux; - u32 uart4_ipp_uart_rts_b; - u32 uart4_ipp_uart_rxd_mux; - u32 uart5_ipp_uart_rts_b; - u32 uart5_ipp_uart_rxd_mux; - u32 usb_top_ipp_ind_otg_usb_oc; - u32 usb_top_ipp_ind_uh2_usb_oc; -}; diff --git a/include/asm-arm/arch-mx27/asm-offsets.h b/include/asm-arm/arch-mx27/asm-offsets.h deleted file mode 100644 index 497afe5..0000000 --- a/include/asm-arm/arch-mx27/asm-offsets.h +++ /dev/null @@ -1,16 +0,0 @@ -#define AIPI1_PSR0 0x10000000 -#define AIPI1_PSR1 0x10000004 -#define AIPI2_PSR0 0x10020000 -#define AIPI2_PSR1 0x10020004 -#define CSCR 0x10027000 -#define MPCTL0 0x10027004 -#define SPCTL0 0x1002700c -#define PCDR0 0x10027018 -#define PCDR1 0x1002701c -#define PCCR0 0x10027020 -#define PCCR1 0x10027024 -#define ESDCTL0_ROF 0x00 -#define ESDCFG0_ROF 0x04 -#define ESDCTL1_ROF 0x08 -#define ESDCFG1_ROF 0x0C -#define ESDMISC_ROF 0x10 diff --git a/include/asm-arm/arch-mx27/clock.h b/include/asm-arm/arch-mx27/clock.h deleted file mode 100644 index 7e9c7aa..0000000 --- a/include/asm-arm/arch-mx27/clock.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * - * (c) 2009 Ilya Yanok, Emcraft Systems - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H -unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); - -ulong imx_get_mpllclk(void); -ulong imx_get_armclk(void); -ulong imx_get_spllclk(void); -ulong imx_get_fclk(void); -ulong imx_get_hclk(void); -ulong imx_get_bclk(void); -ulong imx_get_perclk1(void); -ulong imx_get_perclk2(void); -ulong imx_get_perclk3(void); -ulong imx_get_ahbclk(void); - -#define imx_get_uartclk imx_get_perclk1 -#define imx_get_fecclk imx_get_ahbclk - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/include/asm-arm/arch-mx27/imx-regs.h b/include/asm-arm/arch-mx27/imx-regs.h deleted file mode 100644 index d36a6da..0000000 --- a/include/asm-arm/arch-mx27/imx-regs.h +++ /dev/null @@ -1,519 +0,0 @@ -/* - * (c) 2007 Pengutronix, Sascha Hauer - * (c) 2009 Ilya Yanok, Emcraft Systems - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -#ifndef __ASSEMBLY__ - -extern void imx_gpio_mode (int gpio_mode); - -#ifdef CONFIG_MXC_UART -extern void mx27_uart_init_pins(void); -#endif /* CONFIG_MXC_UART */ - -#ifdef CONFIG_FEC_MXC -extern void mx27_fec_init_pins(void); -#endif /* CONFIG_FEC_MXC */ - -#ifdef CONFIG_MXC_MMC -extern void mx27_sd2_init_pins(void); -#endif /* CONFIG_MXC_MMC */ - -/* AIPI */ -struct aipi_regs { - u32 psr0; - u32 psr1; -}; - -/* System Control */ -struct system_control_regs { - u32 res[5]; - u32 fmcr; - u32 gpcr; - u32 wbcr; - u32 dscr1; - u32 dscr2; - u32 dscr3; - u32 dscr4; - u32 dscr5; - u32 dscr6; - u32 dscr7; - u32 dscr8; - u32 dscr9; - u32 dscr10; - u32 dscr11; - u32 dscr12; - u32 dscr13; - u32 pscr; - u32 pmcr; - u32 res1; - u32 dcvr0; - u32 dcvr1; - u32 dcvr2; - u32 dcvr3; -}; - -/* Chip Select Registers */ -struct weim_regs { - u32 cs0u; /* Chip Select 0 Upper Register */ - u32 cs0l; /* Chip Select 0 Lower Register */ - u32 cs0a; /* Chip Select 0 Addition Register */ - u32 pad0; - u32 cs1u; /* Chip Select 1 Upper Register */ - u32 cs1l; /* Chip Select 1 Lower Register */ - u32 cs1a; /* Chip Select 1 Addition Register */ - u32 pad1; - u32 cs2u; /* Chip Select 2 Upper Register */ - u32 cs2l; /* Chip Select 2 Lower Register */ - u32 cs2a; /* Chip Select 2 Addition Register */ - u32 pad2; - u32 cs3u; /* Chip Select 3 Upper Register */ - u32 cs3l; /* Chip Select 3 Lower Register */ - u32 cs3a; /* Chip Select 3 Addition Register */ - u32 pad3; - u32 cs4u; /* Chip Select 4 Upper Register */ - u32 cs4l; /* Chip Select 4 Lower Register */ - u32 cs4a; /* Chip Select 4 Addition Register */ - u32 pad4; - u32 cs5u; /* Chip Select 5 Upper Register */ - u32 cs5l; /* Chip Select 5 Lower Register */ - u32 cs5a; /* Chip Select 5 Addition Register */ - u32 pad5; - u32 eim; /* WEIM Configuration Register */ -}; - -/* SDRAM Controller registers */ -struct esdramc_regs { -/* Enhanced SDRAM Control Register 0 */ - u32 esdctl0; -/* Enhanced SDRAM Configuration Register 0 */ - u32 esdcfg0; -/* Enhanced SDRAM Control Register 1 */ - u32 esdctl1; -/* Enhanced SDRAM Configuration Register 1 */ - u32 esdcfg1; -/* Enhanced SDRAM Miscellanious Register */ - u32 esdmisc; -}; - -/* Watchdog Registers*/ -struct wdog_regs { - u32 wcr; - u32 wsr; - u32 wstr; -}; - -/* PLL registers */ -struct pll_regs { - u32 cscr; /* Clock Source Control Register */ - u32 mpctl0; /* MCU PLL Control Register 0 */ - u32 mpctl1; /* MCU PLL Control Register 1 */ - u32 spctl0; /* System PLL Control Register 0 */ - u32 spctl1; /* System PLL Control Register 1 */ - u32 osc26mctl; /* Oscillator 26M Register */ - u32 pcdr0; /* Peripheral Clock Divider Register 0 */ - u32 pcdr1; /* Peripheral Clock Divider Register 1 */ - u32 pccr0; /* Peripheral Clock Control Register 0 */ - u32 pccr1; /* Peripheral Clock Control Register 1 */ - u32 ccsr; /* Clock Control Status Register */ -}; - -/* - * Definitions for the clocksource registers - */ -struct gpt_regs { - u32 gpt_tctl; - u32 gpt_tprer; - u32 gpt_tcmp; - u32 gpt_tcr; - u32 gpt_tcn; - u32 gpt_tstat; -}; - -/* - * GPIO Module and I/O Multiplexer - */ -#define PORTA 0 -#define PORTB 1 -#define PORTC 2 -#define PORTD 3 -#define PORTE 4 -#define PORTF 5 - -struct gpio_regs { - struct { - u32 ddir; - u32 ocr1; - u32 ocr2; - u32 iconfa1; - u32 iconfa2; - u32 iconfb1; - u32 iconfb2; - u32 dr; - u32 gius; - u32 ssr; - u32 icr1; - u32 icr2; - u32 imr; - u32 isr; - u32 gpr; - u32 swr; - u32 puen; - u32 res[0x2f]; - } port[6]; -}; - -/* IIM Control Registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prog_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res[0x1F0]; - u32 iim_bank_area0[0x100]; -}; -#endif - -#define IMX_IO_BASE 0x10000000 - -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) -#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) -#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) -#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) -#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) -#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) -#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) -#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) -#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) -#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE) -#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) -#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) -#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) -#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) - -#define IMX_ESD_BASE (0xD8001000) -#define IMX_WEIM_BASE (0xD8002000) - -/* FMCR System Control bit definition*/ -#define UART4_RXD_CTL (1 << 25) -#define UART4_RTS_CTL (1 << 24) -#define KP_COL6_CTL (1 << 18) -#define KP_ROW7_CTL (1 << 17) -#define KP_ROW6_CTL (1 << 16) -#define PC_WAIT_B_CTL (1 << 14) -#define PC_READY_CTL (1 << 13) -#define PC_VS1_CTL (1 << 12) -#define PC_VS2_CTL (1 << 11) -#define PC_BVD1_CTL (1 << 10) -#define PC_BVD2_CTL (1 << 9) -#define IOS16_CTL (1 << 8) -#define NF_FMS (1 << 5) -#define NF_16BIT_SEL (1 << 4) -#define SLCDC_SEL (1 << 2) -#define SDCS1_SEL (1 << 1) -#define SDCS0_SEL (1 << 0) - - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x04 - -#define CSCR_MPEN (1 << 0) -#define CSCR_SPEN (1 << 1) -#define CSCR_FPM_EN (1 << 2) -#define CSCR_OSC26M_DIS (1 << 3) -#define CSCR_OSC26M_DIV1P5 (1 << 4) -#define CSCR_AHB_DIV -#define CSCR_ARM_DIV -#define CSCR_ARM_SRC_MPLL (1 << 15) -#define CSCR_MCU_SEL (1 << 16) -#define CSCR_SP_SEL (1 << 17) -#define CSCR_MPLL_RESTART (1 << 18) -#define CSCR_SPLL_RESTART (1 << 19) -#define CSCR_MSHC_SEL (1 << 20) -#define CSCR_H264_SEL (1 << 21) -#define CSCR_SSI1_SEL (1 << 22) -#define CSCR_SSI2_SEL (1 << 23) -#define CSCR_SD_CNT -#define CSCR_USB_DIV -#define CSCR_UPDATE_DIS (1 << 31) - -#define MPCTL1_BRMO (1 << 6) -#define MPCTL1_LF (1 << 15) - -#define PCCR0_SSI2_EN (1 << 0) -#define PCCR0_SSI1_EN (1 << 1) -#define PCCR0_SLCDC_EN (1 << 2) -#define PCCR0_SDHC3_EN (1 << 3) -#define PCCR0_SDHC2_EN (1 << 4) -#define PCCR0_SDHC1_EN (1 << 5) -#define PCCR0_SDC_EN (1 << 6) -#define PCCR0_SAHARA_EN (1 << 7) -#define PCCR0_RTIC_EN (1 << 8) -#define PCCR0_RTC_EN (1 << 9) -#define PCCR0_PWM_EN (1 << 11) -#define PCCR0_OWIRE_EN (1 << 12) -#define PCCR0_MSHC_EN (1 << 13) -#define PCCR0_LCDC_EN (1 << 14) -#define PCCR0_KPP_EN (1 << 15) -#define PCCR0_IIM_EN (1 << 16) -#define PCCR0_I2C2_EN (1 << 17) -#define PCCR0_I2C1_EN (1 << 18) -#define PCCR0_GPT6_EN (1 << 19) -#define PCCR0_GPT5_EN (1 << 20) -#define PCCR0_GPT4_EN (1 << 21) -#define PCCR0_GPT3_EN (1 << 22) -#define PCCR0_GPT2_EN (1 << 23) -#define PCCR0_GPT1_EN (1 << 24) -#define PCCR0_GPIO_EN (1 << 25) -#define PCCR0_FEC_EN (1 << 26) -#define PCCR0_EMMA_EN (1 << 27) -#define PCCR0_DMA_EN (1 << 28) -#define PCCR0_CSPI3_EN (1 << 29) -#define PCCR0_CSPI2_EN (1 << 30) -#define PCCR0_CSPI1_EN (1 << 31) - -#define PCCR1_MSHC_BAUDEN (1 << 2) -#define PCCR1_NFC_BAUDEN (1 << 3) -#define PCCR1_SSI2_BAUDEN (1 << 4) -#define PCCR1_SSI1_BAUDEN (1 << 5) -#define PCCR1_H264_BAUDEN (1 << 6) -#define PCCR1_PERCLK4_EN (1 << 7) -#define PCCR1_PERCLK3_EN (1 << 8) -#define PCCR1_PERCLK2_EN (1 << 9) -#define PCCR1_PERCLK1_EN (1 << 10) -#define PCCR1_HCLK_USB (1 << 11) -#define PCCR1_HCLK_SLCDC (1 << 12) -#define PCCR1_HCLK_SAHARA (1 << 13) -#define PCCR1_HCLK_RTIC (1 << 14) -#define PCCR1_HCLK_LCDC (1 << 15) -#define PCCR1_HCLK_H264 (1 << 16) -#define PCCR1_HCLK_FEC (1 << 17) -#define PCCR1_HCLK_EMMA (1 << 18) -#define PCCR1_HCLK_EMI (1 << 19) -#define PCCR1_HCLK_DMA (1 << 20) -#define PCCR1_HCLK_CSI (1 << 21) -#define PCCR1_HCLK_BROM (1 << 22) -#define PCCR1_HCLK_ATA (1 << 23) -#define PCCR1_WDT_EN (1 << 24) -#define PCCR1_USB_EN (1 << 25) -#define PCCR1_UART6_EN (1 << 26) -#define PCCR1_UART5_EN (1 << 27) -#define PCCR1_UART4_EN (1 << 28) -#define PCCR1_UART3_EN (1 << 29) -#define PCCR1_UART2_EN (1 << 30) -#define PCCR1_UART1_EN (1 << 31) - -/* SDRAM Controller registers bitfields */ -#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) -#define ESDCTL_DSIZ_32 (2 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) - -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) - -#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) -#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) -#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) -#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) -#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) -#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) -#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) -#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) -#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) - -#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) -#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) -#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) -#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) -#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) -#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) -#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) -#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) -#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) -#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) -#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) -#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) -#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) -#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) -#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) -#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) -#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) -#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) - -#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) -#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) -#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) -#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) -#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) -#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) -#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) -#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) -#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) -#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) -#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) -#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) -#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) -#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) -#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) -#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) -#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) -#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) -#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) -#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) -#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) -#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) -#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) -#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) -#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) -#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) -#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) - -/* Clocksource Bitfields */ -#define TCTL_SWR (1 << 15) /* Software reset */ -#define TCTL_FRR (1 << 8) /* Freerun / restart */ -#define TCTL_CAP (3 << 6) /* Capture Edge */ -#define TCTL_OM (1 << 5) /* output mode */ -#define TCTL_IRQEN (1 << 4) /* interrupt enable */ -#define TCTL_CLKSOURCE 1 /* Clock source bit position */ -#define TCTL_TEN 1 /* Timer enable */ -#define TPRER_PRES 0xff /* Prescale */ -#define TSTAT_CAPT (1 << 1) /* Capture event */ -#define TSTAT_COMP 1 /* Compare event */ - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT) -#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT) -#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT) -#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT) -#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) -#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) - -#define IIM_STAT_BUSY (1 << 7) -#define IIM_STAT_PRGD (1 << 1) -#define IIM_STAT_SNSD (1 << 0) -#define IIM_ERR_PRGE (1 << 7) -#define IIM_ERR_WPE (1 << 6) -#define IIM_ERR_OPE (1 << 5) -#define IIM_ERR_RPE (1 << 4) -#define IIM_ERR_WLRE (1 << 3) -#define IIM_ERR_SNSE (1 << 2) -#define IIM_ERR_PARITYE (1 << 1) - -/* Definitions for i.MX27 TO2 */ -#define IIM0_MAC 5 -#define IIM0_SCC_KEY 11 -#define IIM1_SUID 1 - -#endif /* _IMX_REGS_H */ diff --git a/include/asm-arm/arch-mx27/mxcmmc.h b/include/asm-arm/arch-mx27/mxcmmc.h deleted file mode 100644 index 4c83cc7..0000000 --- a/include/asm-arm/arch-mx27/mxcmmc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2009 Ilya Yanok - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef ASM_ARCH_MXCMMC_H -#define ASM_ARCH_MXCMMC_H - -int mxc_mmc_init(bd_t *bis); - -#endif diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h deleted file mode 100644 index 6f6e9a4..0000000 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MX31_REGS_H -#define __ASM_ARCH_MX31_REGS_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include - -/* Clock control module registers */ -struct clock_control_regs { - u32 ccmr; - u32 pdr0; - u32 pdr1; - u32 rcsr; - u32 mpctl; - u32 upctl; - u32 spctl; - u32 cosr; - u32 cgr0; - u32 cgr1; - u32 cgr2; - u32 wimr0; - u32 ldc; - u32 dcvr0; - u32 dcvr1; - u32 dcvr2; - u32 dcvr3; - u32 ltr0; - u32 ltr1; - u32 ltr2; - u32 ltr3; - u32 ltbr0; - u32 ltbr1; - u32 pmcr0; - u32 pmcr1; - u32 pdr2; -}; - -/* Bit definitions for RCSR register in CCM */ -#define CCM_RCSR_NF16B (1 << 31) -#define CCM_RCSR_NFMS (1 << 30) - -#endif - -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) - -#define CCM_BASE 0x53f80000 -#define CCM_CCMR (CCM_BASE + 0x00) -#define CCM_PDR0 (CCM_BASE + 0x04) -#define CCM_PDR1 (CCM_BASE + 0x08) -#define CCM_RCSR (CCM_BASE + 0x0c) -#define CCM_MPCTL (CCM_BASE + 0x10) -#define CCM_UPCTL (CCM_BASE + 0x14) -#define CCM_SPCTL (CCM_BASE + 0x18) -#define CCM_COSR (CCM_BASE + 0x1C) -#define CCM_CGR0 (CCM_BASE + 0x20) -#define CCM_CGR1 (CCM_BASE + 0x24) -#define CCM_CGR2 (CCM_BASE + 0x28) - -#define CCMR_MDS (1 << 7) -#define CCMR_SBYCS (1 << 4) -#define CCMR_MPE (1 << 3) -#define CCMR_PRCS_MASK (3 << 1) -#define CCMR_FPM (1 << 1) -#define CCMR_CKIH (2 << 1) - -#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) -#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) -#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) -#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) -#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) -#define PDR0_MCU_PODF(x) ((x) & 0x7) - -#define PLL_PD(x) (((x) & 0xf) << 26) -#define PLL_MFD(x) (((x) & 0x3ff) << 16) -#define PLL_MFI(x) (((x) & 0xf) << 10) -#define PLL_MFN(x) (((x) & 0x3ff) << 0) - -#define WEIM_ESDCTL0 0xB8001000 -#define WEIM_ESDCFG0 0xB8001004 -#define WEIM_ESDCTL1 0xB8001008 -#define WEIM_ESDCFG1 0xB800100C -#define WEIM_ESDMISC 0xB8001010 - -#define ESDCTL_SDE (1 << 31) -#define ESDCTL_CMD_RW (0 << 28) -#define ESDCTL_CMD_PRECHARGE (1 << 28) -#define ESDCTL_CMD_AUTOREFRESH (2 << 28) -#define ESDCTL_CMD_LOADMODEREG (3 << 28) -#define ESDCTL_CMD_MANUALREFRESH (4 << 28) -#define ESDCTL_ROW_13 (2 << 24) -#define ESDCTL_ROW(x) ((x) << 24) -#define ESDCTL_COL_9 (1 << 20) -#define ESDCTL_COL(x) ((x) << 20) -#define ESDCTL_DSIZ(x) ((x) << 16) -#define ESDCTL_SREFR(x) ((x) << 13) -#define ESDCTL_PWDT(x) ((x) << 10) -#define ESDCTL_FP(x) ((x) << 8) -#define ESDCTL_BL(x) ((x) << 7) -#define ESDCTL_PRCT(x) ((x) << 0) - -#define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) - -#define IOMUXC_BASE 0x43FAC000 -#define IOMUXC_GPR (IOMUXC_BASE + 0x8) -#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) -#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) - -#define IPU_BASE 0x53fc0000 -#define IPU_CONF IPU_BASE - -#define IPU_CONF_PXL_ENDIAN (1<<8) -#define IPU_CONF_DU_EN (1<<7) -#define IPU_CONF_DI_EN (1<<6) -#define IPU_CONF_ADC_EN (1<<5) -#define IPU_CONF_SDC_EN (1<<4) -#define IPU_CONF_PF_EN (1<<3) -#define IPU_CONF_ROT_EN (1<<2) -#define IPU_CONF_IC_EN (1<<1) -#define IPU_CONF_SCI_EN (1<<0) - -#define ARM_PPMRR 0x40000015 - -#define WDOG_BASE 0x53FDC000 - -/* - * GPIO - */ -#define GPIO1_BASE 0x53FCC000 -#define GPIO2_BASE 0x53FD0000 -#define GPIO3_BASE 0x53FA4000 -#define GPIO_DR 0x00000000 /* data register */ -#define GPIO_GDIR 0x00000004 /* direction register */ -#define GPIO_PSR 0x00000008 /* pad status register */ - -/* - * Signal Multiplexing (IOMUX) - */ - -/* bits in the SW_MUX_CTL registers */ -#define MUX_CTL_OUT_GPIO_DR (0 << 4) -#define MUX_CTL_OUT_FUNC (1 << 4) -#define MUX_CTL_OUT_ALT1 (2 << 4) -#define MUX_CTL_OUT_ALT2 (3 << 4) -#define MUX_CTL_OUT_ALT3 (4 << 4) -#define MUX_CTL_OUT_ALT4 (5 << 4) -#define MUX_CTL_OUT_ALT5 (6 << 4) -#define MUX_CTL_OUT_ALT6 (7 << 4) -#define MUX_CTL_IN_NONE (0 << 0) -#define MUX_CTL_IN_GPIO (1 << 0) -#define MUX_CTL_IN_FUNC (2 << 0) -#define MUX_CTL_IN_ALT1 (4 << 0) -#define MUX_CTL_IN_ALT2 (8 << 0) - -#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) -#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) -#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) -#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) - -/* Register offsets based on IOMUXC_BASE */ -/* 0x00 .. 0x7b */ -#define MUX_CTL_RTS1 0x7c -#define MUX_CTL_CTS1 0x7d -#define MUX_CTL_DTR_DCE1 0x7e -#define MUX_CTL_DSR_DCE1 0x7f -#define MUX_CTL_CSPI2_SCLK 0x80 -#define MUX_CTL_CSPI2_SPI_RDY 0x81 -#define MUX_CTL_RXD1 0x82 -#define MUX_CTL_TXD1 0x83 -#define MUX_CTL_CSPI2_MISO 0x84 -#define MUX_CTL_CSPI2_SS0 0x85 -#define MUX_CTL_CSPI2_SS1 0x86 -#define MUX_CTL_CSPI2_SS2 0x87 -#define MUX_CTL_CSPI1_SS2 0x88 -#define MUX_CTL_CSPI1_SCLK 0x89 -#define MUX_CTL_CSPI1_SPI_RDY 0x8a -#define MUX_CTL_CSPI2_MOSI 0x8b -#define MUX_CTL_CSPI1_MOSI 0x8c -#define MUX_CTL_CSPI1_MISO 0x8d -#define MUX_CTL_CSPI1_SS0 0x8e -#define MUX_CTL_CSPI1_SS1 0x8f - -/* - * Helper macros for the MUX_[contact name]__[pin function] macros - */ -#define IOMUX_MODE_POS 9 -#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact)) - -/* - * These macros can be used in mx31_gpio_mux() and have the form - * MUX_[contact name]__[pin function] - */ -#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC) -#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC) -#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) -#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) - -#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) -#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) -#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) -#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC) -#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC) -#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \ - IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) -#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) - -#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC) -#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC) -#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC) -#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC) -#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC) -#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \ - IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC) -#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC) - -#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) -#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) - -/* PAD control registers for SDR/DDR */ -#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C) -#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270) -#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274) -#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278) -#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C) -#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280) -#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284) -#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288) -#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C) -#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290) -#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294) -#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298) -#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C) -#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0) -#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4) -#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8) -#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC) -#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0) -#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4) -#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8) -#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC) -#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0) -#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4) -#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8) -#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC) -#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0) -#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4) -#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8) -#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC) - -/* - * Memory regions and CS - */ -#define IPU_MEM_BASE 0x70000000 -#define CSD0_BASE 0x80000000 -#define CSD1_BASE 0x90000000 -#define CS0_BASE 0xA0000000 -#define CS1_BASE 0xA8000000 -#define CS2_BASE 0xB0000000 -#define CS3_BASE 0xB2000000 -#define CS4_BASE 0xB4000000 -#define CS4_PSRAM_BASE 0xB5000000 -#define CS5_BASE 0xB6000000 -#define PCMCIA_MEM_BASE 0xC0000000 - -/* - * NAND controller - */ -#define NFC_BASE_ADDR 0xB8000000 - -#endif /* __ASM_ARCH_MX31_REGS_H */ diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h deleted file mode 100644 index 3cc4b35..0000000 --- a/include/asm-arm/arch-mx31/mx31.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MX31_H -#define __ASM_ARCH_MX31_H - -extern u32 mx31_get_ipg_clk(void); -#define imx_get_uartclk mx31_get_ipg_clk -extern void mx31_gpio_mux(unsigned long mode); - -enum mx31_gpio_direction { - MX31_GPIO_DIRECTION_IN, - MX31_GPIO_DIRECTION_OUT, -}; - -#ifdef CONFIG_MX31_GPIO -extern int mx31_gpio_direction(unsigned int gpio, - enum mx31_gpio_direction direction); -extern void mx31_gpio_set(unsigned int gpio, unsigned int value); -#else -static inline int mx31_gpio_direction(unsigned int gpio, - enum mx31_gpio_direction direction) -{ - return 1; -} -static inline void mx31_gpio_set(unsigned int gpio, unsigned int value) -{ -} -#endif - -void mx31_uart1_hw_init(void); -void mx31_spi2_hw_init(void); - -#endif /* __ASM_ARCH_MX31_H */ diff --git a/include/asm-arm/arch-mx51/asm-offsets.h b/include/asm-arm/arch-mx51/asm-offsets.h deleted file mode 100644 index 3a83fa0..0000000 --- a/include/asm-arm/arch-mx51/asm-offsets.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * needed for cpu/arm_cortexa8/mx51/lowlevel_init.S - * - * These should be auto-generated - */ -/* CCM */ -#define CLKCTL_CCR 0x00 -#define CLKCTL_CCDR 0x04 -#define CLKCTL_CSR 0x08 -#define CLKCTL_CCSR 0x0C -#define CLKCTL_CACRR 0x10 -#define CLKCTL_CBCDR 0x14 -#define CLKCTL_CBCMR 0x18 -#define CLKCTL_CSCMR1 0x1C -#define CLKCTL_CSCMR2 0x20 -#define CLKCTL_CSCDR1 0x24 -#define CLKCTL_CS1CDR 0x28 -#define CLKCTL_CS2CDR 0x2C -#define CLKCTL_CDCDR 0x30 -#define CLKCTL_CHSCCDR 0x34 -#define CLKCTL_CSCDR2 0x38 -#define CLKCTL_CSCDR3 0x3C -#define CLKCTL_CSCDR4 0x40 -#define CLKCTL_CWDR 0x44 -#define CLKCTL_CDHIPR 0x48 -#define CLKCTL_CDCR 0x4C -#define CLKCTL_CTOR 0x50 -#define CLKCTL_CLPCR 0x54 -#define CLKCTL_CISR 0x58 -#define CLKCTL_CIMR 0x5C -#define CLKCTL_CCOSR 0x60 -#define CLKCTL_CGPR 0x64 -#define CLKCTL_CCGR0 0x68 -#define CLKCTL_CCGR1 0x6C -#define CLKCTL_CCGR2 0x70 -#define CLKCTL_CCGR3 0x74 -#define CLKCTL_CCGR4 0x78 -#define CLKCTL_CCGR5 0x7C -#define CLKCTL_CCGR6 0x80 -#define CLKCTL_CMEOR 0x84 - -/* DPLL */ -#define PLL_DP_CTL 0x00 -#define PLL_DP_CONFIG 0x04 -#define PLL_DP_OP 0x08 -#define PLL_DP_MFD 0x0C -#define PLL_DP_MFN 0x10 -#define PLL_DP_HFS_OP 0x1C -#define PLL_DP_HFS_MFD 0x20 -#define PLL_DP_HFS_MFN 0x24 diff --git a/include/asm-arm/arch-mx51/clock.h b/include/asm-arm/arch-mx51/clock.h deleted file mode 100644 index 1f8a537..0000000 --- a/include/asm-arm/arch-mx51/clock.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_FEC_CLK, -}; - -unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); - -u32 imx_get_uartclk(void); -u32 imx_get_fecclk(void); -unsigned int mxc_get_clock(enum mxc_clock clk); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/include/asm-arm/arch-mx51/crm_regs.h b/include/asm-arm/arch-mx51/crm_regs.h deleted file mode 100644 index 14aa231..0000000 --- a/include/asm-arm/arch-mx51/crm_regs.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ - -#define MXC_CCM_BASE CCM_BASE_ADDR - -/* DPLL register mapping structure */ -struct mxc_pll_reg { - u32 ctrl; - u32 config; - u32 op; - u32 mfd; - u32 mfn; - u32 mfn_minus; - u32 mfn_plus; - u32 hfs_op; - u32 hfs_mfd; - u32 hfs_mfn; - u32 mfn_togc; - u32 destat; -}; - -/* Register maping of CCM*/ -struct mxc_ccm_reg { - u32 ccr; /* 0x0000 */ - u32 ccdr; - u32 csr; - u32 ccsr; - u32 cacrr; /* 0x0010*/ - u32 cbcdr; - u32 cbcmr; - u32 cscmr1; - u32 cscmr2; /* 0x0020 */ - u32 cscdr1; - u32 cs1cdr; - u32 cs2cdr; - u32 cdcdr; /* 0x0030 */ - u32 chscdr; - u32 cscdr2; - u32 cscdr3; - u32 cscdr4; /* 0x0040 */ - u32 cwdr; - u32 cdhipr; - u32 cdcr; - u32 ctor; /* 0x0050 */ - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; /* 0x0060 */ - u32 cgpr; - u32 CCGR0; - u32 CCGR1; - u32 CCGR2; /* 0x0070 */ - u32 CCGR3; - u32 CCGR4; - u32 CCGR5; - u32 CCGR6; /* 0x0080 */ - u32 cmeor; -}; - -/* Define the bits in register CACRR */ -#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 -#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 - -/* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) -#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 -#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) -#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 -#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) -#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 -#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) -#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 -#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) -#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) -#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 -#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) -#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 -#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) -#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 -#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 - -/* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26 -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 -#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) -#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) -#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) -#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) -#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 - -/* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 -#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0 -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F - -/* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 -#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 -#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) - -/* Define the bits in register CSCDR1 */ -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 -#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 - -#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/include/asm-arm/arch-mx51/imx-regs.h b/include/asm-arm/arch-mx51/imx-regs.h deleted file mode 100644 index 3887d3c..0000000 --- a/include/asm-arm/arch-mx51/imx-regs.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_MX51_H__ -#define __ASM_ARCH_MXC_MX51_H__ - -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) -/* - * IRAM - */ -#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ -/* - * Graphics Memory of GPU - */ -#define GPU_BASE_ADDR 0x20000000 -#define GPU_CTRL_BASE_ADDR 0x30000000 -#define IPU_CTRL_BASE_ADDR 0x40000000 -/* - * Debug - */ -#define DEBUG_BASE_ADDR 0x60000000 -#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) -#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) -#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) -#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) -#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) -#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) -#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) -#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) - -/* - * SPBA global module enabled #0 - */ -#define SPBA0_BASE_ADDR 0x70000000 - -#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) -#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) -#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) -#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) -#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) -#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) -#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) -#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) -#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) -#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) -#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) -#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) - -/* - * AIPS 1 - */ -#define AIPS1_BASE_ADDR 0x73F00000 - -#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) -#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) -#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) -#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) -#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) -#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) -#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) -#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) -#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) -#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) -#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) -#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) -#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) -#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) -#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) -#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) -#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) -#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) -#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) -#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) - -/* - * AIPS 2 - */ -#define AIPS2_BASE_ADDR 0x83F00000 - -#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) -#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) -#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) -#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) -#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) -#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) -#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) -#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) -#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) -#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) -#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) -#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) -#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) -#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) -#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) -#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) -#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) -#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) -#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) -#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) -#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) -#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) -#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) -#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) -#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) -#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) -#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) -#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) -#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) -#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) -#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) -#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) - -#define TZIC_BASE_ADDR 0x8FFFC000 - -/* - * Memory regions and CS - */ -#define CSD0_BASE_ADDR 0x90000000 -#define CSD1_BASE_ADDR 0xA0000000 -#define CS0_BASE_ADDR 0xB0000000 -#define CS1_BASE_ADDR 0xB8000000 -#define CS2_BASE_ADDR 0xC0000000 -#define CS3_BASE_ADDR 0xC8000000 -#define CS4_BASE_ADDR 0xCC000000 -#define CS5_BASE_ADDR 0xCE000000 - -/* - * NFC - */ -#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ - -/*! - * Number of GPIO port as defined in the IC Spec - */ -#define GPIO_PORT_NUM 4 -/*! - * Number of GPIO pins per port - */ -#define GPIO_NUM_PIN 32 - -#define IIM_SREV 0x24 -#define ROM_SI_REV 0x48 - -#define NFC_BUF_SIZE 0x1000 - -/* M4IF */ -#define M4IF_FBPM0 0x40 -#define M4IF_FIDBP 0x48 - -/* Assuming 24MHz input clock with doubler ON */ -/* MFI PDF */ -#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) -#define DP_MFD_850 (48 - 1) -#define DP_MFN_850 41 - -#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) -#define DP_MFD_800 (3 - 1) -#define DP_MFN_800 1 - -#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) -#define DP_MFD_700 (24 - 1) -#define DP_MFN_700 7 - -#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) -#define DP_MFD_665 (96 - 1) -#define DP_MFN_665 89 - -#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) -#define DP_MFD_532 (24 - 1) -#define DP_MFN_532 13 - -#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) -#define DP_MFD_400 (3 - 1) -#define DP_MFN_400 1 - -#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) -#define DP_MFD_216 (4 - 1) -#define DP_MFN_216 3 - -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_1_1 0x11 -#define CHIP_REV_2_0 0x20 -#define CHIP_REV_2_5 0x25 -#define CHIP_REV_3_0 0x30 - -#define BOARD_REV_1_0 0x0 -#define BOARD_REV_2_0 0x1 - -#ifndef __ASSEMBLY__ - -struct clkctl { - u32 ccr; - u32 ccdr; - u32 csr; - u32 ccsr; - u32 cacrr; - u32 cbcdr; - u32 cbcmr; - u32 cscmr1; - u32 cscmr2; - u32 cscdr1; - u32 cs1cdr; - u32 cs2cdr; - u32 cdcdr; - u32 chsccdr; - u32 cscdr2; - u32 cscdr3; - u32 cscdr4; - u32 cwdr; - u32 cdhipr; - u32 cdcr; - u32 ctor; - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; - u32 cgpr; - u32 ccgr0; - u32 ccgr1; - u32 ccgr2; - u32 ccgr3; - u32 ccgr4; - u32 ccgr5; - u32 ccgr6; - u32 cmeor; -}; - -/* WEIM registers */ -struct weim { - u32 csgcr1; - u32 csgcr2; - u32 csrcr1; - u32 csrcr2; - u32 cswcr1; - u32 cswcr2; -}; - -#endif /* __ASSEMBLER__*/ - -#endif /* __ASM_ARCH_MXC_MX51_H__ */ diff --git a/include/asm-arm/arch-mx51/iomux.h b/include/asm-arm/arch-mx51/iomux.h deleted file mode 100644 index a41c387..0000000 --- a/include/asm-arm/arch-mx51/iomux.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MACH_MX51_IOMUX_H__ -#define __MACH_MX51_IOMUX_H__ - -#include -#include -#include -#include - -typedef unsigned int iomux_pin_name_t; - -/* various IOMUX output functions */ -typedef enum iomux_config { - IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ - IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ - IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ - IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ - IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ - IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ - IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ - IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ - IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ - IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ -} iomux_pin_cfg_t; - -/* various IOMUX pad functions */ -typedef enum iomux_pad_config { - PAD_CTL_SRE_SLOW = 0x0 << 0, /* Slow slew rate */ - PAD_CTL_SRE_FAST = 0x1 << 0, /* Fast slew rate */ - PAD_CTL_DRV_LOW = 0x0 << 1, /* Low drive strength */ - PAD_CTL_DRV_MEDIUM = 0x1 << 1, /* Medium drive strength */ - PAD_CTL_DRV_HIGH = 0x2 << 1, /* High drive strength */ - PAD_CTL_DRV_MAX = 0x3 << 1, /* Max drive strength */ - PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, /* Opendrain disable */ - PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */ - PAD_CTL_100K_PD = 0x0 << 4, /* 100Kohm pulldown */ - PAD_CTL_47K_PU = 0x1 << 4, /* 47Kohm pullup */ - PAD_CTL_100K_PU = 0x2 << 4, /* 100Kohm pullup */ - PAD_CTL_22K_PU = 0x3 << 4, /* 22Kohm pullup */ - PAD_CTL_PUE_KEEPER = 0x0 << 6, /* enable pulldown */ - PAD_CTL_PUE_PULL = 0x1 << 6, /* enable pullup */ - PAD_CTL_PKE_NONE = 0x0 << 7, /* Disable pullup/pulldown */ - PAD_CTL_PKE_ENABLE = 0x1 << 7, /* Enable pullup/pulldown */ - PAD_CTL_HYS_NONE = 0x0 << 8, /* Hysteresis disabled */ - PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */ - PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */ - PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */ - PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */ - PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */ -} iomux_pad_config_t; - -/* various IOMUX input select register index */ -typedef enum iomux_input_select { - MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, - MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, - MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, - MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, - /* TO2 */ - MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, - MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, - MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, - MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, - MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, - /* TO2 */ - MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, - MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, - MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, - MUX_IN_FEC_FEC_COL_SELECT_INPUT, - MUX_IN_FEC_FEC_CRS_SELECT_INPUT, - MUX_IN_FEC_FEC_MDI_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, - MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, - /* TO2 */ - MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, - /* TO2 */ - MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, - /* TO2 */ - MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, - MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, - MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, - MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, - MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, - - MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, - - MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, - - MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, - MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, - MUX_INPUT_NUM_MUX, -} iomux_input_select_t; - -/* various IOMUX input functions */ -typedef enum iomux_input_config { - INPUT_CTL_PATH0 = 0x0, - INPUT_CTL_PATH1, - INPUT_CTL_PATH2, - INPUT_CTL_PATH3, - INPUT_CTL_PATH4, - INPUT_CTL_PATH5, - INPUT_CTL_PATH6, - INPUT_CTL_PATH7, -} iomux_input_config_t; - -void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); -void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); -void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); -unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); -void mxc_iomux_set_input(iomux_input_select_t input, u32 config); - -#endif /* __MACH_MX51_IOMUX_H__ */ diff --git a/include/asm-arm/arch-mx51/mx51_pins.h b/include/asm-arm/arch-mx51/mx51_pins.h deleted file mode 100644 index ca26f41..0000000 --- a/include/asm-arm/arch-mx51/mx51_pins.h +++ /dev/null @@ -1,374 +0,0 @@ -/* - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_MX51_PINS_H__ -#define __ASM_ARCH_MXC_MX51_PINS_H__ - -#ifndef __ASSEMBLY__ - -/* - * In order to identify pins more effectively, each mux-controlled pin's - * enumerated value is constructed in the following way: - * - * ------------------------------------------------------------------- - * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 - * ------------------------------------------------------------------- - * IO_P | IO_I | GPIO_I | PAD_I | MUX_I - * ------------------------------------------------------------------- - * - * Bit 0 to 9 contains MUX_I used to identify the register - * offset (0-based. base is IOMUX_module_base) defined in the Section - * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The - * similar field definitions are used for the pad control register. - * The IOMUX controller can be split in two parts. At the begeinning, - * there is the register definitions for the multiplexing each pin. - * Then there is a set of registers (PAD_I) to configure each pin - * (pullup, pulldown, etc). - * PAD_I defines the offset of the pad register for each pin. - * GPIO_I defines, if available, the number of gpio that can be - * connected to that pad - * IO_I defines the multiplexer mode required to set the pad in gpio mode - * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs - * - * For example, the MX51_PIN_ETM_D0 is defined in the enumeration: - * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I) - * It means the mux control register is at register offset 0x28. The pad control - * register offset is: 0x250 and also occupy the least significant bits - * within the register. - */ - -/*! - * Starting bit position within each entry of \b iomux_pins to represent the - * MUX control register offset - */ -#define MUX_I 0 -/*! - * Starting bit position within each entry of \b iomux_pins to represent the - * PAD control register offset - */ -#define PAD_I 10 -/*! - * Starting bit position within each entry of \b iomux_pins to represent which - * mux mode is for GPIO (0-based) - */ -#define GPIO_I 21 - -#define MUX_IO_P 29 -#define MUX_IO_I 24 -#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ - GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ - ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) -#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) -#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) -#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) - -#define NON_GPIO_PORT 0x7 -#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) -#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) -#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) - -#define NON_MUX_I PIN_TO_MUX_MASK -#define MUX_I_START 0x001C -#define PAD_I_START 0x3F0 -#define INPUT_CTL_START 0x8C4 -#define INPUT_CTL_START_TO1 0x928 -#define MUX_I_END (PAD_I_START - 4) - -#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ - (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ - ((mi) << MUX_I) | \ - ((pi - PAD_I_START) << PAD_I) | \ - ((ga) << GPIO_I)) - -#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ - _MXC_BUILD_PIN(gp, gi, ga, mi, pi) - -#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ - _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) - -#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) -#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) -#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) -#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) - -/* - * This enumeration is constructed based on the Section - * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated - * value is constructed based on the rules described above. - */ -enum iomux_pins { - MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8), - MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8), - MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8), - MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8), - MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC), - MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC), - MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC), - MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC), - MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0), - MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0), - MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0), - MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0), - MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC), - MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC), - MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC), - MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC), - MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0), - MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4), - MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8), - MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC), - MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400), - MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404), - MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408), - MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C), - MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410), - MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414), - MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418), - MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C), - MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420), - MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424), - MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428), - MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C), - MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430), - MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434), - MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438), - MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C), - MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440), - MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444), - MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448), - MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C), - MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450), - MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454), - MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458), - MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C), - MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460), - MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464), - MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468), - MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C), - MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470), - MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474), - MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478), - MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C), - MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480), - MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484), - MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488), - MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C), - MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494), - MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0), - MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0), - MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4), - MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8), - MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC), - MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0), - MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4), - MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8), - MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC), - MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500), - MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504), - MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514), - MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND, - MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8), - MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC), - MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0), - MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518), - MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C), - MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520), - MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524), - MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528), - MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C), - MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530), - MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534), - MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538), - MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C), - MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540), - MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544), - MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548), - MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C), - MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550), - MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554), - MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558), - MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C), - MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560), - MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564), - MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568), - MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C), - MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570), - MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574), - MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578), - MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C), - MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580), - MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584), - MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588), - MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C), - MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590), - MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594), - MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598), - MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C), - MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0), - MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4), - MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8), - MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC), - MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0), - MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4), - MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8), - MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860), - MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC), - MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0), - MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4), - MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8), - MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC), - MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0), - MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4), - MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8), - MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC), - MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0), - MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4), - MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C), - MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8), - MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC), - MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0), - MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4), - MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8), - MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC), - MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600), - MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604), - MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608), - MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C), - MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610), - MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614), - MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618), - MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C), - MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620), - MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624), - MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628), - MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C), - MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630), - MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634), - MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638), - MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C), - MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640), - MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644), - MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648), - MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C), - MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650), - MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654), - MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658), - MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C), - MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660), - MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678), - MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C), - MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680), - MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684), - MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688), - MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C), - MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690), - MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694), - MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698), - MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C), - MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0), - MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4), - MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8), - MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC), - MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0), - MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4), - MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8), - MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC), - MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0), - MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4), - MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8), - MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC), - MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0), - MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4), - MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8), - MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC), - MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0), - MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4), - MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8), - MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC), - MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0), - MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4), - MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8), - MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC), - MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700), - MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704), - MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708), - MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C), - MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710), - MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714), - MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718), - MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C), - MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720), - MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724), - MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728), - MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C), - MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734), - MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C), - MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740), - MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744), - MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748), - MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C), - MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750), - MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754), - MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758), - MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C), - MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760), - MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764), - MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768), - MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C), - MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770), - MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774), - MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778), - MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C), - MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780), - MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784), - MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788), - MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C), - MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790), - MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794), - MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798), - MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C), - MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0), - MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4), - MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8), - MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC), - MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0), - MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4), - MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8), - MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC), - MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0), - MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4), - MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8), - MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC), - MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0), - MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4), - MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8), - MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC), - MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804), - MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808), - MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C), - MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), - MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), - MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), -}; - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */ diff --git a/include/asm-arm/arch-mx51/sys_proto.h b/include/asm-arm/arch-mx51/sys_proto.h deleted file mode 100644 index bf500a8..0000000 --- a/include/asm-arm/arch-mx51/sys_proto.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -u32 get_cpu_rev(void); -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) - -#endif diff --git a/include/asm-arm/arch-nomadik/gpio.h b/include/asm-arm/arch-nomadik/gpio.h deleted file mode 100644 index 1d3c9ce..0000000 --- a/include/asm-arm/arch-nomadik/gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __NMK_GPIO_H__ -#define __NMK_GPIO_H__ - -/* - * These functions are called from the soft-i2c driver, but - * are also used by board files to set output bits. - */ - -enum nmk_af { /* alternate function settings */ - GPIO_GPIO = 0, - GPIO_ALT_A, - GPIO_ALT_B, - GPIO_ALT_C -}; - -extern void nmk_gpio_af(int gpio, int alternate_function); -extern void nmk_gpio_dir(int gpio, int dir); -extern void nmk_gpio_set(int gpio, int val); -extern int nmk_gpio_get(int gpio); - -#endif /* __NMK_GPIO_H__ */ diff --git a/include/asm-arm/arch-nomadik/mtu.h b/include/asm-arm/arch-nomadik/mtu.h deleted file mode 100644 index a87be9e..0000000 --- a/include/asm-arm/arch-nomadik/mtu.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MTU_H -#define __ASM_ARCH_MTU_H - -/* - * The MTU device hosts four different counters, with 4 set of - * registers. These are register names. - */ - -#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ -#define MTU_RIS 0x04 /* Raw interrupt status */ -#define MTU_MIS 0x08 /* Masked interrupt status */ -#define MTU_ICR 0x0C /* Interrupt clear register */ - -/* per-timer registers take 0..3 as argument */ -#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ -#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ -#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ -#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ - -/* bits for the control register */ -#define MTU_CRn_ENA 0x80 -#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ -#define MTU_CRn_PRESCALE_MASK 0x0c -#define MTU_CRn_PRESCALE_1 0x00 -#define MTU_CRn_PRESCALE_16 0x04 -#define MTU_CRn_PRESCALE_256 0x08 -#define MTU_CRn_32BITS 0x02 -#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ - -/* Other registers are usual amba/primecell registers, currently not used */ -#define MTU_ITCR 0xff0 -#define MTU_ITOP 0xff4 - -#define MTU_PERIPH_ID0 0xfe0 -#define MTU_PERIPH_ID1 0xfe4 -#define MTU_PERIPH_ID2 0xfe8 -#define MTU_PERIPH_ID3 0xfeC - -#define MTU_PCELL0 0xff0 -#define MTU_PCELL1 0xff4 -#define MTU_PCELL2 0xff8 -#define MTU_PCELL3 0xffC - -#endif /* __ASM_ARCH_MTU_H */ diff --git a/include/asm-arm/arch-omap/sizes.h b/include/asm-arm/arch-omap/sizes.h deleted file mode 100644 index f8d92ca..0000000 --- a/include/asm-arm/arch-omap/sizes.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ diff --git a/include/asm-arm/arch-omap24xx/bits.h b/include/asm-arm/arch-omap24xx/bits.h deleted file mode 100644 index 8522335..0000000 --- a/include/asm-arm/arch-omap24xx/bits.h +++ /dev/null @@ -1,48 +0,0 @@ -/* bits.h - * Copyright (c) 2004 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif diff --git a/include/asm-arm/arch-omap24xx/clocks.h b/include/asm-arm/arch-omap24xx/clocks.h deleted file mode 100644 index 2e92569..0000000 --- a/include/asm-arm/arch-omap24xx/clocks.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_CLOCKS_H_ -#define _OMAP24XX_CLOCKS_H_ - -#define COMMIT_DIVIDERS 0x1 - -#define MODE_BYPASS_FAST 0x2 -#define APLL_LOCK 0xc -#ifdef CONFIG_APTIX -#define DPLL_LOCK 0x1 /* stay in bypass mode */ -#else -#define DPLL_LOCK 0x3 /* DPLL lock */ -#endif - -/****************************************************************************; -; PRCM Scheme II -; -; Enable clocks and DPLL for: -; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 -; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] -; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] -; DSPI=100 6 CM_CLKSEL_DSP[6:5] -; DSP_S bypass CM_CLKSEL_DSP[7] -; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] -; IVAF=100 auto -; IVAI auto -; IVA_MPU auto -; IVA_S bypass CM_CLKSEL_DSP[13] -; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] -; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=100 auto -; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] -; L4=100Mhz 6 -; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define II_DPLL_OUT_X2 0x2 /* x2 core out */ -#define II_MPU_DIV 0x2 /* mpu = core/2 */ -#define II_DSP_DIV 0x343 /* dsp & iva divider */ -#define II_GFX_DIV 0x2 -#define II_BUS_DIV 0x04601026 -#define II_DPLL_300 0x01832100 - -/****************************************************************************; -; PRCM Scheme III -; -; Enable clocks and DPLL for: -; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 -; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] -; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] -; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] -; DSP_S ACTIVATED CM_CLKSEL_DSP[7] -; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] -; IVAF=88.67 auto -; IVAI auto -; IVA_MPU auto -; IVA_S ACTIVATED CM_CLKSEL_DSP[13] -; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: -; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=88.67 auto -; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] -; L4=66.5Mhz /8 -; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define III_DPLL_OUT_X2 0x2 /* x2 core out */ -#define III_MPU_DIV 0x2 /* mpu = core/2 */ -#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ -#define III_GFX_DIV 0x2 -#define III_BUS_DIV 0x08301044 -#define III_DPLL_266 0x01885500 - -/* set defaults for boot up */ -#ifdef PRCM_CONFIG_II -# define DPLL_OUT II_DPLL_OUT_X2 -# define MPU_DIV II_MPU_DIV -# define DSP_DIV II_DSP_DIV -# define GFX_DIV II_GFX_DIV -# define BUS_DIV II_BUS_DIV -# define DPLL_VAL II_DPLL_300 -#elif PRCM_CONFIG_III -# define DPLL_OUT III_DPLL_OUT_X2 -# define MPU_DIV III_MPU_DIV -# define DSP_DIV III_DSP_DIV -# define GFX_DIV III_GFX_DIV -# define BUS_DIV III_BUS_DIV -# define DPLL_VAL III_DPLL_266 -#endif - -/* lock delay time out */ -#define LDELAY 12000000 - -#endif diff --git a/include/asm-arm/arch-omap24xx/i2c.h b/include/asm-arm/arch-omap24xx/i2c.h deleted file mode 100644 index 19046aa..0000000 --- a/include/asm-arm/arch-omap24xx/i2c.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_I2C_H_ -#define _OMAP24XX_I2C_H_ - -#define I2C_BASE1 0x48070000 -#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */ - -#define I2C_DEFAULT_BASE I2C_BASE1 - -struct i2c { - unsigned short rev; /* 0x00 */ - unsigned short res1; - unsigned short ie; /* 0x04 */ - unsigned short res2; - unsigned short stat; /* 0x08 */ - unsigned short res3; - unsigned short iv; /* 0x0C */ - unsigned short res4[3]; - unsigned short buf; /* 0x14 */ - unsigned short res5; - unsigned short cnt; /* 0x18 */ - unsigned short res6; - unsigned short data; /* 0x1C */ - unsigned short res7; - unsigned short sysc; /* 0x20 */ - unsigned short res8; - unsigned short con; /* 0x24 */ - unsigned short res9; - unsigned short oa; /* 0x28 */ - unsigned short res10; - unsigned short sa; /* 0x2C */ - unsigned short res11; - unsigned short psc; /* 0x30 */ - unsigned short res12; - unsigned short scll; /* 0x34 */ - unsigned short res13; - unsigned short sclh; /* 0x38 */ - unsigned short res14; - unsigned short systest; /* 0x3c */ - unsigned short res15; -}; - -#define I2C_BUS_MAX 2 - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */ -#define OMAP_I2C_STANDARD 100000 -#define OMAP_I2C_FAST_MODE 400000 -#define OMAP_I2C_HIGH_SPEED 3400000 - -#define SYSTEM_CLOCK_12 12000000 -#define SYSTEM_CLOCK_13 13000000 -#define SYSTEM_CLOCK_192 19200000 -#define SYSTEM_CLOCK_96 96000000 - -#ifndef I2C_IP_CLK -#define I2C_IP_CLK SYSTEM_CLOCK_96 -#endif - -#ifndef I2C_INTERNAL_SAMPLING_CLK -#define I2C_INTERNAL_SAMPLING_CLK 19200000 -#endif - -/* These are the trim values for standard and fast speed */ -#ifndef I2C_FASTSPEED_SCLL_TRIM -#define I2C_FASTSPEED_SCLL_TRIM 6 -#endif -#ifndef I2C_FASTSPEED_SCLH_TRIM -#define I2C_FASTSPEED_SCLH_TRIM 6 -#endif - -/* These are the trim values for high speed */ -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif - -#define I2C_PSC_MAX 0x0f -#define I2C_PSC_MIN 0x00 - - -#endif diff --git a/include/asm-arm/arch-omap24xx/mem.h b/include/asm-arm/arch-omap24xx/mem.h deleted file mode 100644 index 42e8ab2..0000000 --- a/include/asm-arm/arch-omap24xx/mem.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_MEM_H_ -#define _OMAP24XX_MEM_H_ - -#define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ - -#ifndef __ASSEMBLY__ -/* struct's for holding data tables for current boards, they are getting used - early in init when NO global access are there */ -struct sdrc_data_s { - u32 sdrc_sharing; - u32 sdrc_mdcfg_0_ddr; - u32 sdrc_mdcfg_0_sdr; - u32 sdrc_actim_ctrla_0; - u32 sdrc_actim_ctrlb_0; - u32 sdrc_rfr_ctrl; - u32 sdrc_mr_0_ddr; - u32 sdrc_mr_0_sdr; - u32 sdrc_dllab_ctrl; -} /*__attribute__ ((packed))*/; -typedef struct sdrc_data_s sdrc_data_t; - -typedef enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -} mem_t; - -#endif - -/* Slower full frequency range default timings for x32 operation*/ -#define H4_2420_SDRC_SHARING 0x00000100 -#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ -#define H4_2420_SDRC_MR_0_SDR 0x00000031 -#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ -#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ -#define H4_2420_SDRC_MR_0_DDR 0x00000032 - -#define H4_2422_SDRC_SHARING 0x00004b00 -#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */ -#define H4_2422_SDRC_MR_0_DDR 0x00000032 - -/* ES1 work around timings */ -#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ -#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 -#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ - -/* optimized timings good for current shipping parts */ -#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 -#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e -#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ -#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ -#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 -#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 -#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/ -#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */ - -#ifdef PRCM_CONFIG_II -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz -#elif PRCM_CONFIG_III -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz -# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz -#endif - - -/* GPMC settings */ -#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ -# ifdef CONFIG_SYS_NAND_BOOT -# define H4_24XX_GPMC_CONFIG1_0 0x0 -# define H4_24XX_GPMC_CONFIG2_0 0x00141400 -# define H4_24XX_GPMC_CONFIG3_0 0x00141400 -# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 -# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 -# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 -# else /* else NOR */ -# define H4_24XX_GPMC_CONFIG1_0 0x3 -# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01 -# define H4_24XX_GPMC_CONFIG3_0 0x00050502 -# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06 -# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F -# endif /* endif CONFIG_SYS_NAND_BOOT */ -# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) -# define H4_24XX_GPMC_CONFIG1_1 0x00011000 -# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00 -# define H4_24XX_GPMC_CONFIG3_1 0x00080802 -# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 -# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F -# define H4_24XX_GPMC_CONFIG6_1 0x000003C2 -# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) -#endif /* endif PRCM_CONFIG_II */ - -#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ -# ifdef CONFIG_SYS_NAND_BOOT -# define H4_24XX_GPMC_CONFIG1_0 0x0 -# define H4_24XX_GPMC_CONFIG2_0 0x00141400 -# define H4_24XX_GPMC_CONFIG3_0 0x00141400 -# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 -# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 -# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 -# else /* NOR boot */ -# define H4_24XX_GPMC_CONFIG1_0 0x3 -# define H4_24XX_GPMC_CONFIG2_0 0x00151501 -# define H4_24XX_GPMC_CONFIG3_0 0x00060602 -# define H4_24XX_GPMC_CONFIG4_0 0x10081008 -# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F -# define H4_24XX_GPMC_CONFIG6_0 0x000004c4 -# endif /* endif CONFIG_SYS_NAND_BOOT */ -# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) -# define H4_24XX_GPMC_CONFIG1_1 0x00011000 -# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01 -# define H4_24XX_GPMC_CONFIG3_1 0x00080803 -# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 -# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F -# define H4_24XX_GPMC_CONFIG6_1 0x000004C4 -# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) -#endif /* endif CONFIG_SYS_PRCM_III */ - -#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/include/asm-arm/arch-omap24xx/mux.h b/include/asm-arm/arch-omap24xx/mux.h deleted file mode 100644 index 4fdb9c6..0000000 --- a/include/asm-arm/arch-omap24xx/mux.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP2420_MUX_H_ -#define _OMAP2420_MUX_H_ - -#ifndef __ASSEMBLY__ -typedef unsigned char uint8; -typedef unsigned int uint32; - -void muxSetupSDRC(void); -void muxSetupGPMC(void); -void muxSetupUsb0(void); -void muxSetupUsbHost(void); -void muxSetupUart3(void); -void muxSetupI2C1(void); -void muxSetupUART1(void); -void muxSetupLCD(void); -void muxSetupCamera(void); -void muxSetupMMCSD(void) ; -void muxSetupTouchScreen(void) ; -void muxSetupHDQ(void); -#endif - -#define USB_OTG_CTRL ((volatile uint32 *)0x4805E30C) - -/* Pin Muxing registers used for HDQ (Smart battery) */ -#define CONTROL_PADCONF_HDQ_SIO ((volatile unsigned char *)0x48000115) - -/* Pin Muxing registers used for GPMC */ -#define CONTROL_PADCONF_GPMC_D2_BYTE0 ((volatile unsigned char *)0x48000088) -#define CONTROL_PADCONF_GPMC_D2_BYTE1 ((volatile unsigned char *)0x48000089) -#define CONTROL_PADCONF_GPMC_D2_BYTE2 ((volatile unsigned char *)0x4800008A) -#define CONTROL_PADCONF_GPMC_D2_BYTE3 ((volatile unsigned char *)0x4800008B) - -#define CONTROL_PADCONF_GPMC_NCS0_BYTE0 ((volatile unsigned char *)0x4800008C) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE1 ((volatile unsigned char *)0x4800008D) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE2 ((volatile unsigned char *)0x4800008E) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE3 ((volatile unsigned char *)0x4800008F) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE4 (0x48000090) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE5 (0x48000091) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE6 (0x48000092) -#define CONTROL_PADCONF_GPMC_NCS0_BYTE7 (0x48000093) - -/* Pin Muxing registers used for SDRC */ -#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0) -#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1) -#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2) -#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3) - -#define CONTROL_PADCONF_SDRC_A14_BYTE0 ((volatile unsigned char *)0x48000030) -#define CONTROL_PADCONF_SDRC_A14_BYTE1 ((volatile unsigned char *)0x48000031) -#define CONTROL_PADCONF_SDRC_A14_BYTE2 ((volatile unsigned char *)0x48000032) -#define CONTROL_PADCONF_SDRC_A14_BYTE3 ((volatile unsigned char *)0x48000033) - -/* Pin Muxing registers used for Touch Screen (SPI) */ -#define CONTROL_PADCONF_SPI1_CLK ((volatile unsigned char *)0x480000FF) -#define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100) -#define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101) -#define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102) -#define CONTROL_PADCONF_SPI1_NCS1 (0x48000103) - -#define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B) - -/* Pin Muxing registers used for MMCSD */ -#define CONTROL_PADCONF_MMC_CLKI ((volatile unsigned char *)0x480000FE) -#define CONTROL_PADCONF_MMC_CLKO ((volatile unsigned char *)0x480000F3) -#define CONTROL_PADCONF_MMC_CMD ((volatile unsigned char *)0x480000F4) -#define CONTROL_PADCONF_MMC_DAT0 ((volatile unsigned char *)0x480000F5) -#define CONTROL_PADCONF_MMC_DAT1 ((volatile unsigned char *)0x480000F6) -#define CONTROL_PADCONF_MMC_DAT2 ((volatile unsigned char *)0x480000F7) -#define CONTROL_PADCONF_MMC_DAT3 ((volatile unsigned char *)0x480000F8) -#define CONTROL_PADCONF_MMC_DAT_DIR0 ((volatile unsigned char *)0x480000F9) -#define CONTROL_PADCONF_MMC_DAT_DIR1 ((volatile unsigned char *)0x480000FA) -#define CONTROL_PADCONF_MMC_DAT_DIR2 ((volatile unsigned char *)0x480000FB) -#define CONTROL_PADCONF_MMC_DAT_DIR3 ((volatile unsigned char *)0x480000FC) -#define CONTROL_PADCONF_MMC_CMD_DIR ((volatile unsigned char *)0x480000FD) - -#define CONTROL_PADCONF_SDRC_A14 ((volatile unsigned char *)0x48000030) -#define CONTROL_PADCONF_SDRC_A13 ((volatile unsigned char *)0x48000031) - -/* Pin Muxing registers used for CAMERA */ -#define CONTROL_PADCONF_SYS_NRESWARM ((volatile unsigned char *)0x4800012B) - -#define CONTROL_PADCONF_CAM_XCLK ((volatile unsigned char *)0x480000DC) -#define CONTROL_PADCONF_CAM_LCLK ((volatile unsigned char *)0x480000DB) -#define CONTROL_PADCONF_CAM_VS ((volatile unsigned char *)0x480000DA) -#define CONTROL_PADCONF_CAM_HS ((volatile unsigned char *)0x480000D9) -#define CONTROL_PADCONF_CAM_D0 ((volatile unsigned char *)0x480000D8) -#define CONTROL_PADCONF_CAM_D1 ((volatile unsigned char *)0x480000D7) -#define CONTROL_PADCONF_CAM_D2 ((volatile unsigned char *)0x480000D6) -#define CONTROL_PADCONF_CAM_D3 ((volatile unsigned char *)0x480000D5) -#define CONTROL_PADCONF_CAM_D4 ((volatile unsigned char *)0x480000D4) -#define CONTROL_PADCONF_CAM_D5 ((volatile unsigned char *)0x480000D3) -#define CONTROL_PADCONF_CAM_D6 ((volatile unsigned char *)0x480000D2) -#define CONTROL_PADCONF_CAM_D7 ((volatile unsigned char *)0x480000D1) -#define CONTROL_PADCONF_CAM_D8 ((volatile unsigned char *)0x480000D0) -#define CONTROL_PADCONF_CAM_D9 ((volatile unsigned char *)0x480000CF) - -/* Pin Muxing registers used for LCD */ -#define CONTROL_PADCONF_DSS_D0 ((volatile unsigned char *)0x480000B3) -#define CONTROL_PADCONF_DSS_D1 ((volatile unsigned char *)0x480000B4) -#define CONTROL_PADCONF_DSS_D2 ((volatile unsigned char *)0x480000B5) -#define CONTROL_PADCONF_DSS_D3 ((volatile unsigned char *)0x480000B6) -#define CONTROL_PADCONF_DSS_D4 ((volatile unsigned char *)0x480000B7) -#define CONTROL_PADCONF_DSS_D5 ((volatile unsigned char *)0x480000B8) -#define CONTROL_PADCONF_DSS_D6 ((volatile unsigned char *)0x480000B9) -#define CONTROL_PADCONF_DSS_D7 ((volatile unsigned char *)0x480000BA) -#define CONTROL_PADCONF_DSS_D8 ((volatile unsigned char *)0x480000BB) -#define CONTROL_PADCONF_DSS_D9 ((volatile unsigned char *)0x480000BC) -#define CONTROL_PADCONF_DSS_D10 ((volatile unsigned char *)0x480000BD) -#define CONTROL_PADCONF_DSS_D11 ((volatile unsigned char *)0x480000BE) -#define CONTROL_PADCONF_DSS_D12 ((volatile unsigned char *)0x480000BF) -#define CONTROL_PADCONF_DSS_D13 ((volatile unsigned char *)0x480000C0) -#define CONTROL_PADCONF_DSS_D14 ((volatile unsigned char *)0x480000C1) -#define CONTROL_PADCONF_DSS_D15 ((volatile unsigned char *)0x480000C2) -#define CONTROL_PADCONF_DSS_D16 ((volatile unsigned char *)0x480000C3) -#define CONTROL_PADCONF_DSS_D17 ((volatile unsigned char *)0x480000C4) -#define CONTROL_PADCONF_DSS_PCLK ((volatile unsigned char *)0x480000CB) -#define CONTROL_PADCONF_DSS_VSYNC ((volatile unsigned char *)0x480000CC) -#define CONTROL_PADCONF_DSS_HSYNC ((volatile unsigned char *)0x480000CD) -#define CONTROL_PADCONF_DSS_ACBIAS ((volatile unsigned char *)0x480000CE) - -/* Pin Muxing registers used for UART1 */ -#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5) -#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6) -#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7) -#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8) - -/* Pin Muxing registers used for I2C1 */ -#define CONTROL_PADCONF_I2C1_SCL ((volatile unsigned char *)0x48000111) -#define CONTROL_PADCONF_I2C1_SDA ((volatile unsigned char *)0x48000112) - -/* Pin Muxing registres used for USB0. */ -#define CONTROL_PADCONF_USB0_PUEN ((volatile uint8 *)0x4800011D) -#define CONTROL_PADCONF_USB0_VP ((volatile uint8 *)0x4800011E) -#define CONTROL_PADCONF_USB0_VM ((volatile uint8 *)0x4800011F) -#define CONTROL_PADCONF_USB0_RCV ((volatile uint8 *)0x48000120) -#define CONTROL_PADCONF_USB0_TXEN ((volatile uint8 *)0x48000121) -#define CONTROL_PADCONF_USB0_SE0 ((volatile uint8 *)0x48000122) -#define CONTROL_PADCONF_USB0_DAT ((volatile uint8 *)0x48000123) - -/* Pin Muxing registres used for USB1. */ -#define CONTROL_PADCONF_USB1_RCV (0x480000EB) -#define CONTROL_PADCONF_USB1_TXEN (0x480000EC) - -/* Pin Muxing registers used for UART3/IRDA */ -#define CONTROL_PADCONF_UART3_TX_IRTX ((volatile uint8 *)0x48000118) -#define CONTROL_PADCONF_UART3_RX_IRRX ((volatile uint8 *)0x48000119) - -/* Pin Muxing registers used for GPIO */ -#define CONTROL_PADCONF_GPIO69 (0x480000ED) -#define CONTROL_PADCONF_GPIO70 (0x480000EE) -#define CONTROL_PADCONF_GPIO102 (0x48000116) -#define CONTROL_PADCONF_GPIO103 (0x48000117) -#define CONTROL_PADCONF_GPIO104 (0x48000118) -#define CONTROL_PADCONF_GPIO105 (0x48000119) - -#endif diff --git a/include/asm-arm/arch-omap24xx/omap2420.h b/include/asm-arm/arch-omap24xx/omap2420.h deleted file mode 100644 index 0c11bec..0000000 --- a/include/asm-arm/arch-omap24xx/omap2420.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP2420_SYS_H_ -#define _OMAP2420_SYS_H_ - -#include - -/* - * 2420 specific Section - */ - -/* L3 Firewall */ -#define A_REQINFOPERM0 0x68005048 -#define A_READPERM0 0x68005050 -#define A_WRITEPERM0 0x68005058 -/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */ - -/* L3 Firewall */ -#define A_REQINFOPERM0 0x68005048 -#define A_READPERM0 0x68005050 -#define A_WRITEPERM0 0x68005058 - -/* CONTROL */ -#define OMAP2420_CTRL_BASE (0x48000000) -#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) - -/* device type */ -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* TAP information */ -#define OMAP2420_TAP_BASE (0x48014000) -#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) -#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) - -/* GPMC */ -#define OMAP2420_GPMC_BASE (0x6800A000) -#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) -#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) -#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) -#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) -#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) -#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) -#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) -#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) -#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) -#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) -#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) -#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) -#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) -#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) -#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) -#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) - -/* SMS */ -#define OMAP2420_SMS_BASE 0x68008000 -#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) -#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0) -# define BURSTCOMPLETE_GROUP7 BIT31 - -/* SDRC */ -#define OMAP2420_SDRC_BASE 0x68009000 -#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) -#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) -#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) -#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) -#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) -#define OMAP2420_SDRC_CS0 0x80000000 -#define OMAP2420_SDRC_CS1 0xA0000000 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - - -/* UART */ -#define OMAP2420_UART1 0x4806A000 -#define OMAP2420_UART2 0x4806C000 -#define OMAP2420_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP2420_GPT1 0x48028000 -#define OMAP2420_GPT2 0x4802A000 -#define OMAP2420_GPT3 0x48078000 -#define OMAP2420_GPT4 0x4807A000 -#define OMAP2420_GPT5 0x4807C000 -#define OMAP2420_GPT6 0x4807E000 -#define OMAP2420_GPT7 0x48080000 -#define OMAP2420_GPT8 0x48082000 -#define OMAP2420_GPT9 0x48084000 -#define OMAP2420_GPT10 0x48086000 -#define OMAP2420_GPT11 0x48088000 -#define OMAP2420_GPT12 0x4808A000 - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x48020000 -#define WD2_BASE 0x48022000 -#define WD3_BASE 0x48024000 -#define WD4_BASE 0x48026000 -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define OMAP2420_CM_BASE 0x48008000 -#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) -#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) -#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) -#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) - -/* - * H4 specific Section - */ - -/* - * The 2420's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - */ -#if defined(CONFIG_OMAP2420H4) -/* GPMC */ -#ifdef CONFIG_VIRTIO_A /* Pre version B */ -# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x04000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#else -# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x08000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#endif - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -/* FPGA on Debug board.*/ -#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) -#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) -#endif /* endif CONFIG_2420H4 */ - -#if defined(CONFIG_APOLLON) -#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */ -#define APOLLON_CS1_BASE 0x08000000 /* ethernet */ -#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */ -#define APOLLON_CS3_BASE 0x18000000 /* NOR */ - -#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b) -#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c) -#endif /* endif CONFIG_APOLLON */ - -/* Common */ -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - -#endif diff --git a/include/asm-arm/arch-omap24xx/sizes.h b/include/asm-arm/arch-omap24xx/sizes.h deleted file mode 100644 index aaba18f..0000000 --- a/include/asm-arm/arch-omap24xx/sizes.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/include/asm-arm/arch-omap24xx/sys_info.h b/include/asm-arm/arch-omap24xx/sys_info.h deleted file mode 100644 index 53c231a..0000000 --- a/include/asm-arm/arch-omap24xx/sys_info.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_SYS_INFO_H_ -#define _OMAP24XX_SYS_INFO_H_ - -typedef struct h4_system_data { - /* base board info */ - u32 base_b_rev; /* rev from base board i2c */ - /* cpu board info */ - u32 cpu_b_rev; /* rev from cpu board i2c */ - u32 cpu_b_mux; /* mux type on daughter board */ - u32 cpu_b_ddr_type; /* mem type */ - u32 cpu_b_ddr_speed; /* ddr speed rating */ - u32 cpu_b_switches; /* boot ctrl switch settings */ - /* cpu info */ - u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ - u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ -} h4_sys_data; - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_2420 0x2420 -#define CPU_2422 0x2422 /* 2420 + 64M stacked */ -#define CPU_2423 0x2423 /* 2420 + 96M stacked */ - -#define CPU_2422_ES1 1 -#define CPU_2422_ES2 2 -#define CPU_2420_ES1 1 -#define CPU_2420_ES2 2 -#define CPU_2420_2422_ES1 1 - -#define CPU_2420_CHIPID 0x0B5D9000 -#define CPU_24XX_ID_MASK 0x0FFFF000 -#define CPU_242X_REV_MASK 0xF0000000 -#define CPU_242X_PID_MASK 0x000F0000 - -#define BOARD_H4_MENELAUS 1 -#define BOARD_H4_SDP 2 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ - -#endif diff --git a/include/asm-arm/arch-omap24xx/sys_proto.h b/include/asm-arm/arch-omap24xx/sys_proto.h deleted file mode 100644 index 9d8e5b2..0000000 --- a/include/asm-arm/arch-omap24xx/sys_proto.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_SYS_PROTO_H_ -#define _OMAP24XX_SYS_PROTO_H_ - -void prcm_init(void); -void memif_init(void); -void sdrc_init(void); -void do_sdrc_init(u32,u32); -void gpmc_init(void); - -void ether_init(void); -void watchdog_init(void); -void set_muxconf_regs(void); -void peripheral_enable(void); - -u32 get_cpu_type(void); -u32 get_cpu_rev(void); -u32 get_mem_type(void); -u32 get_sysboot_value(void); -u32 get_gpmc0_base(void); -u32 is_gpmc_muxed(void); -u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); -u32 get_board_type(void); -void display_board_info(u32); -void update_mux(u32,u32); -u32 get_sdr_cs_size(u32 offset); - -u32 running_in_sdram(void); -u32 running_in_sram(void); -u32 running_in_flash(void); -u32 running_from_internal_boot(void); -u32 get_device_type(void); -#endif diff --git a/include/asm-arm/arch-omap3/clocks.h b/include/asm-arm/arch-omap3/clocks.h deleted file mode 100644 index 71a0cb6..0000000 --- a/include/asm-arm/arch-omap3/clocks.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _CLOCKS_H_ -#define _CLOCKS_H_ - -#define LDELAY 12000000 - -#define S12M 12000000 -#define S13M 13000000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S38_4M 38400000 - -#define FCK_IVA2_ON 0x00000001 -#define FCK_CORE1_ON 0x03fffe29 -#define ICK_CORE1_ON 0x3ffffffb -#define ICK_CORE2_ON 0x0000001f -#define FCK_WKUP_ON 0x000000e9 -#define ICK_WKUP_ON 0x0000003f -#define FCK_DSS_ON 0x00000005 -#define ICK_DSS_ON 0x00000001 -#define FCK_CAM_ON 0x00000001 -#define ICK_CAM_ON 0x00000001 -#define FCK_PER_ON 0x0003ffff -#define ICK_PER_ON 0x0003ffff - -/* Used to index into DPLL parameter tables */ -typedef struct { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -} dpll_param; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param *get_mpu_dpll_param(void); -extern dpll_param *get_iva_dpll_param(void); -extern dpll_param *get_core_dpll_param(void); -extern dpll_param *get_per_dpll_param(void); - -extern void *_end_vect, *_start; - -#endif diff --git a/include/asm-arm/arch-omap3/clocks_omap3.h b/include/asm-arm/arch-omap3/clocks_omap3.h deleted file mode 100644 index 661407b..0000000 --- a/include/asm-arm/arch-omap3/clocks_omap3.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _CLOCKS_OMAP3_H_ -#define _CLOCKS_OMAP3_H_ - -#define PLL_STOP 1 /* PER & IVA */ -#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ -#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ - -/* - * The following configurations are OPP and SysClk value independant - * and hence are defined here. All the other DPLL related values are - * tabulated in lowlevel_init.S. - */ - -/* CORE DPLL */ -#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ -#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ -#define CORE_FUSB_DIV 2 /* 41.5MHz: */ -#define CORE_L4_DIV 2 /* 83MHz : L4 */ -#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ -#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ - -/* PER DPLL */ -#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ -#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ -#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ - -#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) - -/* MPU DPLL */ - -#define MPU_M_12_ES1 0x0FE -#define MPU_N_12_ES1 0x07 -#define MPU_FSEL_12_ES1 0x05 -#define MPU_M2_12_ES1 0x01 - -#define MPU_M_12_ES2 0x0FA -#define MPU_N_12_ES2 0x05 -#define MPU_FSEL_12_ES2 0x07 -#define MPU_M2_ES2 0x01 - -#define MPU_M_12 0x085 -#define MPU_N_12 0x05 -#define MPU_FSEL_12 0x07 -#define MPU_M2_12 0x01 - -#define MPU_M_13_ES1 0x17D -#define MPU_N_13_ES1 0x0C -#define MPU_FSEL_13_ES1 0x03 -#define MPU_M2_13_ES1 0x01 - -#define MPU_M_13_ES2 0x1F4 -#define MPU_N_13_ES2 0x0C -#define MPU_FSEL_13_ES2 0x03 -#define MPU_M2_13_ES2 0x01 - -#define MPU_M_13 0x10A -#define MPU_N_13 0x0C -#define MPU_FSEL_13 0x03 -#define MPU_M2_13 0x01 - -#define MPU_M_19P2_ES1 0x179 -#define MPU_N_19P2_ES1 0x12 -#define MPU_FSEL_19P2_ES1 0x04 -#define MPU_M2_19P2_ES1 0x01 - -#define MPU_M_19P2_ES2 0x271 -#define MPU_N_19P2_ES2 0x17 -#define MPU_FSEL_19P2_ES2 0x03 -#define MPU_M2_19P2_ES2 0x01 - -#define MPU_M_19P2 0x14C -#define MPU_N_19P2 0x17 -#define MPU_FSEL_19P2 0x03 -#define MPU_M2_19P2 0x01 - -#define MPU_M_26_ES1 0x17D -#define MPU_N_26_ES1 0x19 -#define MPU_FSEL_26_ES1 0x03 -#define MPU_M2_26_ES1 0x01 - -#define MPU_M_26_ES2 0x0FA -#define MPU_N_26_ES2 0x0C -#define MPU_FSEL_26_ES2 0x07 -#define MPU_M2_26_ES2 0x01 - -#define MPU_M_26 0x085 -#define MPU_N_26 0x0C -#define MPU_FSEL_26 0x07 -#define MPU_M2_26 0x01 - -#define MPU_M_38P4_ES1 0x1FA -#define MPU_N_38P4_ES1 0x32 -#define MPU_FSEL_38P4_ES1 0x03 -#define MPU_M2_38P4_ES1 0x01 - -#define MPU_M_38P4_ES2 0x271 -#define MPU_N_38P4_ES2 0x2F -#define MPU_FSEL_38P4_ES2 0x03 -#define MPU_M2_38P4_ES2 0x01 - -#define MPU_M_38P4 0x14C -#define MPU_N_38P4 0x2F -#define MPU_FSEL_38P4 0x03 -#define MPU_M2_38P4 0x01 - -/* IVA DPLL */ - -#define IVA_M_12_ES1 0x07D -#define IVA_N_12_ES1 0x05 -#define IVA_FSEL_12_ES1 0x07 -#define IVA_M2_12_ES1 0x01 - -#define IVA_M_12_ES2 0x0B4 -#define IVA_N_12_ES2 0x05 -#define IVA_FSEL_12_ES2 0x07 -#define IVA_M2_12_ES2 0x01 - -#define IVA_M_12 0x085 -#define IVA_N_12 0x05 -#define IVA_FSEL_12 0x07 -#define IVA_M2_12 0x01 - -#define IVA_M_13_ES1 0x0FA -#define IVA_N_13_ES1 0x0C -#define IVA_FSEL_13_ES1 0x03 -#define IVA_M2_13_ES1 0x01 - -#define IVA_M_13_ES2 0x168 -#define IVA_N_13_ES2 0x0C -#define IVA_FSEL_13_ES2 0x03 -#define IVA_M2_13_ES2 0x01 - -#define IVA_M_13 0x10A -#define IVA_N_13 0x0C -#define IVA_FSEL_13 0x03 -#define IVA_M2_13 0x01 - -#define IVA_M_19P2_ES1 0x082 -#define IVA_N_19P2_ES1 0x09 -#define IVA_FSEL_19P2_ES1 0x07 -#define IVA_M2_19P2_ES1 0x01 - -#define IVA_M_19P2_ES2 0x0E1 -#define IVA_N_19P2_ES2 0x0B -#define IVA_FSEL_19P2_ES2 0x06 -#define IVA_M2_19P2_ES2 0x01 - -#define IVA_M_19P2 0x14C -#define IVA_N_19P2 0x17 -#define IVA_FSEL_19P2 0x03 -#define IVA_M2_19P2 0x01 - -#define IVA_M_26_ES1 0x07D -#define IVA_N_26_ES1 0x0C -#define IVA_FSEL_26_ES1 0x07 -#define IVA_M2_26_ES1 0x01 - -#define IVA_M_26_ES2 0x0B4 -#define IVA_N_26_ES2 0x0C -#define IVA_FSEL_26_ES2 0x07 -#define IVA_M2_26_ES2 0x01 - -#define IVA_M_26 0x085 -#define IVA_N_26 0x0C -#define IVA_FSEL_26 0x07 -#define IVA_M2_26 0x01 - -#define IVA_M_38P4_ES1 0x13F -#define IVA_N_38P4_ES1 0x30 -#define IVA_FSEL_38P4_ES1 0x03 -#define IVA_M2_38P4_ES1 0x01 - -#define IVA_M_38P4_ES2 0x0E1 -#define IVA_N_38P4_ES2 0x17 -#define IVA_FSEL_38P4_ES2 0x06 -#define IVA_M2_38P4_ES2 0x01 - -#define IVA_M_38P4 0x14C -#define IVA_N_38P4 0x2F -#define IVA_FSEL_38P4 0x03 -#define IVA_M2_38P4 0x01 - -/* CORE DPLL */ - -#define CORE_M_12 0xA6 -#define CORE_N_12 0x05 -#define CORE_FSEL_12 0x07 -#define CORE_M2_12 0x01 /* M3 of 2 */ - -#define CORE_M_12_ES1 0x19F -#define CORE_N_12_ES1 0x0E -#define CORE_FSL_12_ES1 0x03 -#define CORE_M2_12_ES1 0x1 /* M3 of 2 */ - -#define CORE_M_13 0x14C -#define CORE_N_13 0x0C -#define CORE_FSEL_13 0x03 -#define CORE_M2_13 0x01 /* M3 of 2 */ - -#define CORE_M_13_ES1 0x1B2 -#define CORE_N_13_ES1 0x10 -#define CORE_FSL_13_ES1 0x03 -#define CORE_M2_13_ES1 0x01 /* M3 of 2 */ - -#define CORE_M_19P2 0x19F -#define CORE_N_19P2 0x17 -#define CORE_FSEL_19P2 0x03 -#define CORE_M2_19P2 0x01 /* M3 of 2 */ - -#define CORE_M_19P2_ES1 0x19F -#define CORE_N_19P2_ES1 0x17 -#define CORE_FSL_19P2_ES1 0x03 -#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ - -#define CORE_M_26 0xA6 -#define CORE_N_26 0x0C -#define CORE_FSEL_26 0x07 -#define CORE_M2_26 0x01 /* M3 of 2 */ - -#define CORE_M_26_ES1 0x1B2 -#define CORE_N_26_ES1 0x21 -#define CORE_FSL_26_ES1 0x03 -#define CORE_M2_26_ES1 0x01 /* M3 of 2 */ - -#define CORE_M_38P4 0x19F -#define CORE_N_38P4 0x2F -#define CORE_FSEL_38P4 0x03 -#define CORE_M2_38P4 0x01 /* M3 of 2 */ - -#define CORE_M_38P4_ES1 0x19F -#define CORE_N_38P4_ES1 0x2F -#define CORE_FSL_38P4_ES1 0x03 -#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ - -/* PER DPLL */ - -#define PER_M_12 0xD8 -#define PER_N_12 0x05 -#define PER_FSEL_12 0x07 -#define PER_M2_12 0x09 - -#define PER_M_13 0x1B0 -#define PER_N_13 0x0C -#define PER_FSEL_13 0x03 -#define PER_M2_13 0x09 - -#define PER_M_19P2 0xE1 -#define PER_N_19P2 0x09 -#define PER_FSEL_19P2 0x07 -#define PER_M2_19P2 0x09 - -#define PER_M_26 0xD8 -#define PER_N_26 0x0C -#define PER_FSEL_26 0x07 -#define PER_M2_26 0x09 - -#define PER_M_38P4 0xE1 -#define PER_N_38P4 0x13 -#define PER_FSEL_38P4 0x07 -#define PER_M2_38P4 0x09 - -#endif /* endif _CLOCKS_OMAP3_H_ */ diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h deleted file mode 100644 index aa8de32..0000000 --- a/include/asm-arm/arch-omap3/cpu.h +++ /dev/null @@ -1,461 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _CPU_H -#define _CPU_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -/* Register offsets of common modules */ -/* Control */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct ctrl { - u8 res1[0xC0]; - u16 gpmc_nadv_ale; /* 0xC0 */ - u16 gpmc_noe; /* 0xC2 */ - u16 gpmc_nwe; /* 0xC4 */ - u8 res2[0x22A]; - u32 status; /* 0x2F0 */ - u32 gpstatus; /* 0x2F4 */ - u8 res3[0x08]; - u32 rpubkey_0; /* 0x300 */ - u32 rpubkey_1; /* 0x304 */ - u32 rpubkey_2; /* 0x308 */ - u32 rpubkey_3; /* 0x30C */ - u32 rpubkey_4; /* 0x310 */ - u8 res4[0x04]; - u32 randkey_0; /* 0x318 */ - u32 randkey_1; /* 0x31C */ - u32 randkey_2; /* 0x320 */ - u32 randkey_3; /* 0x324 */ - u8 res5[0x124]; - u32 ctrl_omap_stat; /* 0x44C */ -}; -#else /* __ASSEMBLY__ */ -#define CONTROL_STATUS 0x2F0 -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* cpu type */ -#define OMAP3503 0x5c00 -#define OMAP3515 0x1c00 -#define OMAP3525 0x4c00 -#define OMAP3530 0x0c00 - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct ctrl_id { - u8 res1[0x4]; - u32 idcode; /* 0x04 */ - u32 prod_id; /* 0x08 */ - u8 res2[0x0C]; - u32 die_id_0; /* 0x18 */ - u32 die_id_1; /* 0x1C */ - u32 die_id_2; /* 0x20 */ - u32 die_id_3; /* 0x24 */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* device type */ -#define DEVICE_MASK (0x7 << 8) -#define SYSBOOT_MASK 0x1F -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -#define GPMC_BASE (OMAP34XX_GPMC_BASE) -#define GPMC_CONFIG_CS0 0x60 -#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - -#else /* __ASSEMBLY__ */ -#define GPMC_CONFIG1 0x00 -#define GPMC_CONFIG2 0x04 -#define GPMC_CONFIG3 0x08 -#define GPMC_CONFIG4 0x0C -#define GPMC_CONFIG5 0x10 -#define GPMC_CONFIG6 0x14 -#define GPMC_CONFIG7 0x18 -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* GPMC Mapping */ -#define FLASH_BASE 0x10000000 /* NOR flash, */ - /* aligned to 256 Meg */ -#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ - /* aligned to 64 Meg */ -#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ - /* aligned to 256 Meg */ -#define DEBUG_BASE 0x08000000 /* debug board */ -#define NAND_BASE 0x30000000 /* NAND addr */ - /* (actual size small port) */ -#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ -#define ONENAND_MAP 0x20000000 /* OneNand addr */ - /* (actual size small port) */ -/* SMS */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct sms { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x34]; - u32 rg_att0; /* 0x48 */ - u8 res3[0x84]; - u32 class_arb0; /* 0xD0 */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define BURSTCOMPLETE_GROUP7 (0x1 << 31) - -/* SDRC */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct sdrc_cs { - u32 mcfg; /* 0x80 || 0xB0 */ - u32 mr; /* 0x84 || 0xB4 */ - u8 res1[0x4]; - u32 emr2; /* 0x8C || 0xBC */ - u8 res2[0x14]; - u32 rfr_ctrl; /* 0x84 || 0xD4 */ - u32 manual; /* 0xA8 || 0xD8 */ - u8 res3[0x4]; -}; - -struct sdrc_actim { - u32 ctrla; /* 0x9C || 0xC4 */ - u32 ctrlb; /* 0xA0 || 0xC8 */ -}; - -struct sdrc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u32 status; /* 0x14 */ - u8 res2[0x28]; - u32 cs_cfg; /* 0x40 */ - u32 sharing; /* 0x44 */ - u8 res3[0x18]; - u32 dlla_ctrl; /* 0x60 */ - u32 dlla_status; /* 0x64 */ - u32 dllb_ctrl; /* 0x68 */ - u32 dllb_status; /* 0x6C */ - u32 power; /* 0x70 */ - u8 res4[0xC]; - struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define DLLPHASE_90 (0x1 << 1) -#define LOADDLL (0x1 << 2) -#define ENADLL (0x1 << 3) -#define DLL_DELAY_MASK 0xFF00 -#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) - -#define PAGEPOLICY_HIGH (0x1 << 0) -#define SRFRONRESET (0x1 << 7) -#define PWDNEN (0x1 << 2) -#define WAKEUPPROC (0x1 << 26) - -#define DDR_SDRAM (0x1 << 0) -#define DEEPPD (0x1 << 3) -#define B32NOT16 (0x1 << 4) -#define BANKALLOCATION (0x2 << 6) -#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ -#define ADDRMUXLEGACY (0x1 << 19) -#define CASWIDTH_10BITS (0x5 << 20) -#define RASWIDTH_13BITS (0x2 << 24) -#define BURSTLENGTH4 (0x2 << 0) -#define CASL3 (0x3 << 4) -#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) -#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) -#define ARE_ARCV_1 (0x1 << 0) -#define ARCV (0x4e2 << 8) /* Autorefresh count */ -#define OMAP34XX_SDRC_CS0 0x80000000 -#define OMAP34XX_SDRC_CS1 0xA0000000 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET (0x1 << 1) -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - -/* timer regs offsets (32 bit regs) */ - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gptimer { - u32 tidr; /* 0x00 r */ - u8 res[0xc]; - u32 tiocp_cfg; /* 0x10 rw */ - u32 tistat; /* 0x14 r */ - u32 tisr; /* 0x18 rw */ - u32 tier; /* 0x1c rw */ - u32 twer; /* 0x20 rw */ - u32 tclr; /* 0x24 rw */ - u32 tcrr; /* 0x28 rw */ - u32 tldr; /* 0x2c rw */ - u32 ttgr; /* 0x30 rw */ - u32 twpc; /* 0x34 r*/ - u32 tmar; /* 0x38 rw*/ - u32 tcar1; /* 0x3c r */ - u32 tcicr; /* 0x40 rw */ - u32 tcar2; /* 0x44 r */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) - -/* Watchdog */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct watchdog { - u8 res1[0x34]; - u32 wwps; /* 0x34 r */ - u8 res2[0x10]; - u32 wspr; /* 0x48 rw */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define PRCM_BASE 0x48004000 - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct prcm { - u32 fclken_iva2; /* 0x00 */ - u32 clken_pll_iva2; /* 0x04 */ - u8 res1[0x1c]; - u32 idlest_pll_iva2; /* 0x24 */ - u8 res2[0x18]; - u32 clksel1_pll_iva2 ; /* 0x40 */ - u32 clksel2_pll_iva2; /* 0x44 */ - u8 res3[0x8bc]; - u32 clken_pll_mpu; /* 0x904 */ - u8 res4[0x1c]; - u32 idlest_pll_mpu; /* 0x924 */ - u8 res5[0x18]; - u32 clksel1_pll_mpu; /* 0x940 */ - u32 clksel2_pll_mpu; /* 0x944 */ - u8 res6[0xb8]; - u32 fclken1_core; /* 0xa00 */ - u8 res7[0xc]; - u32 iclken1_core; /* 0xa10 */ - u32 iclken2_core; /* 0xa14 */ - u8 res8[0x28]; - u32 clksel_core; /* 0xa40 */ - u8 res9[0xbc]; - u32 fclken_gfx; /* 0xb00 */ - u8 res10[0xc]; - u32 iclken_gfx; /* 0xb10 */ - u8 res11[0x2c]; - u32 clksel_gfx; /* 0xb40 */ - u8 res12[0xbc]; - u32 fclken_wkup; /* 0xc00 */ - u8 res13[0xc]; - u32 iclken_wkup; /* 0xc10 */ - u8 res14[0xc]; - u32 idlest_wkup; /* 0xc20 */ - u8 res15[0x1c]; - u32 clksel_wkup; /* 0xc40 */ - u8 res16[0xbc]; - u32 clken_pll; /* 0xd00 */ - u8 res17[0x1c]; - u32 idlest_ckgen; /* 0xd20 */ - u8 res18[0x1c]; - u32 clksel1_pll; /* 0xd40 */ - u32 clksel2_pll; /* 0xd44 */ - u32 clksel3_pll; /* 0xd48 */ - u8 res19[0xb4]; - u32 fclken_dss; /* 0xe00 */ - u8 res20[0xc]; - u32 iclken_dss; /* 0xe10 */ - u8 res21[0x2c]; - u32 clksel_dss; /* 0xe40 */ - u8 res22[0xbc]; - u32 fclken_cam; /* 0xf00 */ - u8 res23[0xc]; - u32 iclken_cam; /* 0xf10 */ - u8 res24[0x2c]; - u32 clksel_cam; /* 0xf40 */ - u8 res25[0xbc]; - u32 fclken_per; /* 0x1000 */ - u8 res26[0xc]; - u32 iclken_per; /* 0x1010 */ - u8 res27[0x2c]; - u32 clksel_per; /* 0x1040 */ - u8 res28[0xfc]; - u32 clksel1_emu; /* 0x1140 */ -}; -#else /* __ASSEMBLY__ */ -#define CM_CLKSEL_CORE 0x48004a40 -#define CM_CLKSEL_GFX 0x48004b40 -#define CM_CLKSEL_WKUP 0x48004c40 -#define CM_CLKEN_PLL 0x48004d00 -#define CM_CLKSEL1_PLL 0x48004d40 -#define CM_CLKSEL1_EMU 0x48005140 -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define PRM_BASE 0x48306000 - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct prm { - u8 res1[0xd40]; - u32 clksel; /* 0xd40 */ - u8 res2[0x50c]; - u32 rstctrl; /* 0x1250 */ - u8 res3[0x1c]; - u32 clksrc_ctrl; /* 0x1270 */ -}; -#else /* __ASSEMBLY__ */ -#define PRM_RSTCTRL 0x48307250 -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define SYSCLKDIV_1 (0x1 << 6) -#define SYSCLKDIV_2 (0x1 << 7) - -#define CLKSEL_GPT1 (0x1 << 0) - -#define EN_GPT1 (0x1 << 0) -#define EN_32KSYNC (0x1 << 2) - -#define ST_WDT2 (0x1 << 5) - -#define ST_MPU_CLK (0x1 << 0) - -#define ST_CORE_CLK (0x1 << 0) - -#define ST_PERIPH_CLK (0x1 << 1) - -#define ST_IVA2_CLK (0x1 << 0) - -#define RESETDONE (0x1 << 0) - -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* SMX-APE */ -#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct pm { - u8 res1[0x48]; - u32 req_info_permission_0; /* 0x48 */ - u8 res2[0x4]; - u32 read_permission_0; /* 0x50 */ - u8 res3[0x4]; - u32 wirte_permission_0; /* 0x58 */ - u8 res4[0x4]; - u32 addr_match_1; /* 0x58 */ - u8 res5[0x4]; - u32 req_info_permission_1; /* 0x68 */ - u8 res6[0x14]; - u32 addr_match_2; /* 0x80 */ -}; -#endif /*__ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - -#define NOT_EARLY 0 - -/* I2C base */ -#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) -#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) -#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) - -#endif /* _CPU_H */ diff --git a/include/asm-arm/arch-omap3/gpio.h b/include/asm-arm/arch-omap3/gpio.h deleted file mode 100644 index 30f633c..0000000 --- a/include/asm-arm/arch-omap3/gpio.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef _GPIO_H -#define _GPIO_H - -#define OMAP24XX_GPIO_REVISION 0x0000 -#define OMAP24XX_GPIO_SYSCONFIG 0x0010 -#define OMAP24XX_GPIO_SYSSTATUS 0x0014 -#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 -#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 -#define OMAP24XX_GPIO_IRQENABLE2 0x002c -#define OMAP24XX_GPIO_IRQENABLE1 0x001c -#define OMAP24XX_GPIO_WAKE_EN 0x0020 -#define OMAP24XX_GPIO_CTRL 0x0030 -#define OMAP24XX_GPIO_OE 0x0034 -#define OMAP24XX_GPIO_DATAIN 0x0038 -#define OMAP24XX_GPIO_DATAOUT 0x003c -#define OMAP24XX_GPIO_LEVELDETECT0 0x0040 -#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 -#define OMAP24XX_GPIO_RISINGDETECT 0x0048 -#define OMAP24XX_GPIO_FALLINGDETECT 0x004c -#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 -#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 -#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 -#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 -#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 -#define OMAP24XX_GPIO_SETWKUENA 0x0084 -#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 -#define OMAP24XX_GPIO_SETDATAOUT 0x0094 - -struct gpio_bank { - void *base; - int method; -}; - -#define METHOD_GPIO_24XX 4 - -/* This is the interface */ - -/* Request a gpio before using it */ -int omap_request_gpio(int gpio); -/* Reset and free a gpio after using it */ -void omap_free_gpio(int gpio); -/* Sets the gpio as input or output */ -void omap_set_gpio_direction(int gpio, int is_input); -/* Set or clear a gpio output */ -void omap_set_gpio_dataout(int gpio, int enable); -/* Get the value of a gpio input */ -int omap_get_gpio_datain(int gpio); - -#endif /* _GPIO_H_ */ diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h deleted file mode 100644 index 490e03b..0000000 --- a/include/asm-arm/arch-omap3/i2c.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2004-2008 - * Texas Instruments, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _I2C_H_ -#define _I2C_H_ - -#define I2C_DEFAULT_BASE I2C_BASE1 - -struct i2c { - unsigned short rev; /* 0x00 */ - unsigned short res1; - unsigned short ie; /* 0x04 */ - unsigned short res2; - unsigned short stat; /* 0x08 */ - unsigned short res3; - unsigned short iv; /* 0x0C */ - unsigned short res4[3]; - unsigned short buf; /* 0x14 */ - unsigned short res5; - unsigned short cnt; /* 0x18 */ - unsigned short res6; - unsigned short data; /* 0x1C */ - unsigned short res7; - unsigned short sysc; /* 0x20 */ - unsigned short res8; - unsigned short con; /* 0x24 */ - unsigned short res9; - unsigned short oa; /* 0x28 */ - unsigned short res10; - unsigned short sa; /* 0x2C */ - unsigned short res11; - unsigned short psc; /* 0x30 */ - unsigned short res12; - unsigned short scll; /* 0x34 */ - unsigned short res13; - unsigned short sclh; /* 0x38 */ - unsigned short res14; - unsigned short systest; /* 0x3c */ - unsigned short res15; -}; - -#define I2C_BUS_MAX 3 - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ - /* (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -#define I2C_SCLL_SCLL 0 -#define I2C_SCLL_SCLL_M 0xFF -#define I2C_SCLL_HSSCLL 8 -#define I2C_SCLH_HSSCLL_M 0xFF -#define I2C_SCLH_SCLH 0 -#define I2C_SCLH_SCLH_M 0xFF -#define I2C_SCLH_HSSCLH 8 -#define I2C_SCLH_HSSCLH_M 0xFF - -#define OMAP_I2C_STANDARD 100000 -#define OMAP_I2C_FAST_MODE 400000 -#define OMAP_I2C_HIGH_SPEED 3400000 - -#define SYSTEM_CLOCK_12 12000000 -#define SYSTEM_CLOCK_13 13000000 -#define SYSTEM_CLOCK_192 19200000 -#define SYSTEM_CLOCK_96 96000000 - -/* Use the reference value of 96MHz if not explicitly set by the board */ -#ifndef I2C_IP_CLK -#define I2C_IP_CLK SYSTEM_CLOCK_96 -#endif - -/* - * The reference minimum clock for high speed is 19.2MHz. - * The linux 2.6.30 kernel uses this value. - * The reference minimum clock for fast mode is 9.6MHz - * The reference minimum clock for standard mode is 4MHz - * In TRM, the value of 12MHz is used. - */ -#ifndef I2C_INTERNAL_SAMPLING_CLK -#define I2C_INTERNAL_SAMPLING_CLK 19200000 -#endif - -/* - * The equation for the low and high time is - * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed - * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed - * - * If the duty cycle is 50% - * - * tlow = scll + scll_trim = sampling clock / (2 * speed) - * thigh = sclh + sclh_trim = sampling clock / (2 * speed) - * - * In TRM - * scll_trim = 7 - * sclh_trim = 5 - * - * The linux 2.6.30 kernel uses - * scll_trim = 6 - * sclh_trim = 6 - * - * These are the trim values for standard and fast speed - */ -#ifndef I2C_FASTSPEED_SCLL_TRIM -#define I2C_FASTSPEED_SCLL_TRIM 6 -#endif -#ifndef I2C_FASTSPEED_SCLH_TRIM -#define I2C_FASTSPEED_SCLH_TRIM 6 -#endif - -/* These are the trim values for high speed */ -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif - -#define I2C_PSC_MAX 0x0f -#define I2C_PSC_MIN 0x00 - -#endif /* _I2C_H_ */ diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h deleted file mode 100644 index 9439758..0000000 --- a/include/asm-arm/arch-omap3/mem.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _MEM_H_ -#define _MEM_H_ - -#define CS0 0x0 -#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ - -#ifndef __ASSEMBLY__ -enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -}; -#endif /* __ASSEMBLY__ */ - -#define EARLY_INIT 1 - -/* Slower full frequency range default timings for x32 operation*/ -#define SDRC_SHARING 0x00000100 -#define SDRC_MR_0_SDR 0x00000031 - -#define DLL_OFFSET 0 -#define DLL_WRITEDDRCLKX2DIS 1 -#define DLL_ENADLL 1 -#define DLL_LOCKDLL 0 -#define DLL_DLLPHASE_72 0 -#define DLL_DLLPHASE_90 1 - -/* rkw - need to find of 90/72 degree recommendation for speed like before */ -#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ - (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) - -/* Infineon part of 3430SDP (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 72/6 = 12 - * ACTIMB - * TCKE = 2 - * XSR = 120/6 = 20 - */ -#define INFINEON_TDAL_165 6 -#define INFINEON_TDPL_165 3 -#define INFINEON_TRRD_165 2 -#define INFINEON_TRCD_165 3 -#define INFINEON_TRP_165 3 -#define INFINEON_TRAS_165 7 -#define INFINEON_TRC_165 10 -#define INFINEON_TRFC_165 12 -#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \ - (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \ - (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \ - (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \ - (INFINEON_TDAL_165)) - -#define INFINEON_TWTR_165 1 -#define INFINEON_TCKE_165 2 -#define INFINEON_TXP_165 2 -#define INFINEON_XSR_165 20 -#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \ - (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \ - (INFINEON_TWTR_165 << 16)) - -/* Micron part of 3430 EVM (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 125/6 = 21 - * ACTIMB - * TWTR = 1 - * TCKE = 1 - * TXSR = 138/6 = 23 - * TXP = 25/6 = 4.1 ~5 - */ -#define MICRON_TDAL_165 6 -#define MICRON_TDPL_165 3 -#define MICRON_TRRD_165 2 -#define MICRON_TRCD_165 3 -#define MICRON_TRP_165 3 -#define MICRON_TRAS_165 7 -#define MICRON_TRC_165 10 -#define MICRON_TRFC_165 21 -#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \ - (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \ - (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \ - (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \ - (MICRON_TDAL_165)) - -#define MICRON_TWTR_165 1 -#define MICRON_TCKE_165 1 -#define MICRON_XSR_165 23 -#define MICRON_TXP_165 5 -#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \ - (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \ - (MICRON_TWTR_165 << 16)) - -#ifdef CONFIG_OMAP3_INFINEON_DDR -#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 -#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 -#endif -#ifdef CONFIG_OMAP3_MICRON_DDR -#define V_ACTIMA_165 MICRON_V_ACTIMA_165 -#define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#endif - -#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) -#error "Please choose the right DDR type in config header" -#endif - -/* - * GPMC settings - - * Definitions is as per the following format - * #define _GPMC_CONFIG - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * STNOR - Intel Strata Flash - * SMNAND - Samsung NAND - * MPDB - H4 MPDB board - * SBNOR - Sibley NOR - * MNAND - Micron Large page x16 NAND - * ONNAND - Samsung One NAND - * - * include/configs/file.h contains the defn - for all CS we are interested - * #define OMAP34XX_GPMC_CSx PART - * #define OMAP34XX_GPMC_CSx_SIZE Size - * #define OMAP34XX_GPMC_CSx_MAP Map - * Where: - * x - CS number - * PART - Part Name as defined above - * SIZE - how big is the mapping to be - * GPMC_SIZE_128M - 0x8 - * GPMC_SIZE_64M - 0xC - * GPMC_SIZE_32M - 0xE - * GPMC_SIZE_16M - 0xF - * MAP - Map this CS to which address(GPMC address space)- Absolute address - * >>24 before being used. - */ -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#define SMNAND_GPMC_CONFIG1 0x00000800 -#define SMNAND_GPMC_CONFIG2 0x00141400 -#define SMNAND_GPMC_CONFIG3 0x00141400 -#define SMNAND_GPMC_CONFIG4 0x0F010F01 -#define SMNAND_GPMC_CONFIG5 0x010C1414 -#define SMNAND_GPMC_CONFIG6 0x1F0F0A80 -#define SMNAND_GPMC_CONFIG7 0x00000C44 - -#define M_NAND_GPMC_CONFIG1 0x00001800 -#define M_NAND_GPMC_CONFIG2 0x00141400 -#define M_NAND_GPMC_CONFIG3 0x00141400 -#define M_NAND_GPMC_CONFIG4 0x0F010F01 -#define M_NAND_GPMC_CONFIG5 0x010C1414 -#define M_NAND_GPMC_CONFIG6 0x1f0f0A80 -#define M_NAND_GPMC_CONFIG7 0x00000C44 - -#define STNOR_GPMC_CONFIG1 0x3 -#define STNOR_GPMC_CONFIG2 0x00151501 -#define STNOR_GPMC_CONFIG3 0x00060602 -#define STNOR_GPMC_CONFIG4 0x11091109 -#define STNOR_GPMC_CONFIG5 0x01141F1F -#define STNOR_GPMC_CONFIG6 0x000004c4 - -#define SIBNOR_GPMC_CONFIG1 0x1200 -#define SIBNOR_GPMC_CONFIG2 0x001f1f00 -#define SIBNOR_GPMC_CONFIG3 0x00080802 -#define SIBNOR_GPMC_CONFIG4 0x1C091C09 -#define SIBNOR_GPMC_CONFIG5 0x01131F1F -#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 - -#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 -#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 -#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 -#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 -#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F -#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 - -#define MPDB_GPMC_CONFIG1 0x00011000 -#define MPDB_GPMC_CONFIG2 0x001f1f01 -#define MPDB_GPMC_CONFIG3 0x00080803 -#define MPDB_GPMC_CONFIG4 0x1c0b1c0a -#define MPDB_GPMC_CONFIG5 0x041f1F1F -#define MPDB_GPMC_CONFIG6 0x1F0F04C4 - -#define P2_GPMC_CONFIG1 0x0 -#define P2_GPMC_CONFIG2 0x0 -#define P2_GPMC_CONFIG3 0x0 -#define P2_GPMC_CONFIG4 0x0 -#define P2_GPMC_CONFIG5 0x0 -#define P2_GPMC_CONFIG6 0x0 - -#define ONENAND_GPMC_CONFIG1 0x00001200 -#define ONENAND_GPMC_CONFIG2 0x000F0F01 -#define ONENAND_GPMC_CONFIG3 0x00030301 -#define ONENAND_GPMC_CONFIG4 0x0F040F04 -#define ONENAND_GPMC_CONFIG5 0x010F1010 -#define ONENAND_GPMC_CONFIG6 0x1F060000 - -#define NET_GPMC_CONFIG1 0x00001000 -#define NET_GPMC_CONFIG2 0x001e1e01 -#define NET_GPMC_CONFIG3 0x00080300 -#define NET_GPMC_CONFIG4 0x1c091c09 -#define NET_GPMC_CONFIG5 0x04181f1f -#define NET_GPMC_CONFIG6 0x00000FCF -#define NET_GPMC_CONFIG7 0x00000f6c - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 -#define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE NAND_BASE -#define PISMO2_CS0_BASE PISMO2_MAP1 -#define PISMO1_ONEN_BASE ONENAND_MAP -#define DBG_MPDB_BASE DEBUG_BASE - -#endif /* endif _MEM_H_ */ diff --git a/include/asm-arm/arch-omap3/mmc.h b/include/asm-arm/arch-omap3/mmc.h deleted file mode 100644 index 196ffdc..0000000 --- a/include/asm-arm/arch-omap3/mmc.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_H -#define MMC_H - -#include "mmc_host_def.h" - -/* Responses */ -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) -#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) - -/* All supported commands */ -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_DESELECT (INDEX(7)| RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) -#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) - -#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) -#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) -#define MMC_DSR_DEFAULT 0x0404 -#define SD_CMD8_CHECK_PATTERN 0xAA -#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) - -/* Clock Configurations and Macros */ - -#define MMC_CLOCK_REFERENCE 96 -#define MMC_RELATIVE_CARD_ADDRESS 0x1234 -#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) -#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) -#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1) -#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) - -#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) -#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) -#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) - -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) - -#define MMC_SD2_CSD_C_SIZE_LSB_MASK 0xFFFF -#define MMC_SD2_CSD_C_SIZE_MSB_MASK 0x003F -#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET 16 -#define MMC_CSD_C_SIZE_LSB_MASK 0x0003 -#define MMC_CSD_C_SIZE_MSB_MASK 0x03FF -#define MMC_CSD_C_SIZE_MSB_OFFSET 2 - -#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) -#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) -#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) - -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned ecc:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned content_prot_app:1; - unsigned reserved_1:4; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned default_ecc:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:5; - unsigned erase_grp_mult:5; - unsigned erase_grp_size:5; - unsigned c_size_mult:3; - unsigned vdd_w_curr_max:3; - unsigned vdd_w_curr_min:3; - unsigned vdd_r_curr_max:3; - unsigned vdd_r_curr_min:3; - unsigned c_size_lsb:2; - unsigned c_size_msb:10; - unsigned reserved_2:2; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_3:2; - unsigned spec_vers:4; - unsigned csd_structure:2; -} mmc_csd_reg_t; - -/* csd for sd2.0 */ -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned reserved_1:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned reserved_2:5; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned reserved_3:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:7; - unsigned sector_size:7; - unsigned erase_blk_len:1; - unsigned reserved_4:1; - unsigned c_size_lsb:16; - unsigned c_size_msb:6; - unsigned reserved_5:6; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_6:6; - unsigned csd_structure:2; -} mmc_sd2_csd_reg_t; - -/* extended csd - 512 bytes long */ -typedef struct { - unsigned char reserved_1[181]; - unsigned char erasedmemorycontent; - unsigned char reserved_2; - unsigned char buswidthmode; - unsigned char reserved_3; - unsigned char highspeedinterfacetiming; - unsigned char reserved_4; - unsigned char powerclass; - unsigned char reserved_5; - unsigned char commandsetrevision; - unsigned char reserved_6; - unsigned char commandset; - unsigned char extendedcsdrevision; - unsigned char reserved_7; - unsigned char csdstructureversion; - unsigned char reserved_8; - unsigned char cardtype; - unsigned char reserved_9[3]; - unsigned char powerclass_52mhz_1_95v; - unsigned char powerclass_26mhz_1_95v; - unsigned char powerclass_52mhz_3_6v; - unsigned char powerclass_26mhz_3_6v; - unsigned char reserved_10; - unsigned char minreadperf_4b_26mhz; - unsigned char minwriteperf_4b_26mhz; - unsigned char minreadperf_8b_26mhz_4b_52mhz; - unsigned char minwriteperf_8b_26mhz_4b_52mhz; - unsigned char minreadperf_8b_52mhz; - unsigned char minwriteperf_8b_52mhz; - unsigned char reserved_11; - unsigned int sectorcount; - unsigned char reserved_12[288]; - unsigned char supportedcommandsets; - unsigned char reserved_13[7]; -} mmc_extended_csd_reg_t; - -/* mmc sd responce */ -typedef struct { - unsigned int ocr; -} mmc_resp_r3; - -typedef struct { - unsigned short cardstatus; - unsigned short newpublishedrca; -} mmc_resp_r6; - -typedef union { - unsigned int resp[4]; - mmc_resp_r3 r3; - mmc_resp_r6 r6; - mmc_csd_reg_t Card_CSD; -} mmc_resp_t; - -extern mmc_card_data mmc_dev; - -unsigned char mmc_lowlevel_init(void); -unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, - unsigned int *response); -unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); -unsigned char mmc_set_opendrain(unsigned char state); -unsigned char mmc_read_data(unsigned int *output_buf); - -#endif /* MMC_H */ diff --git a/include/asm-arm/arch-omap3/mmc_host_def.h b/include/asm-arm/arch-omap3/mmc_host_def.h deleted file mode 100644 index aa751c9..0000000 --- a/include/asm-arm/arch-omap3/mmc_host_def.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -/* T2 Register definitions */ -#define T2_BASE 0x48002000 - -typedef struct t2 { - unsigned char res1[0x274]; - unsigned int devconf0; /* 0x274 */ - unsigned char res2[0x2A8]; - unsigned int pbias_lite; /* 0x520 */ -} t2_t; - -#define MMCSDIO1ADPCLKISEL (1 << 24) - -#define PBIASLITEPWRDNZ0 (1 << 1) -#define PBIASSPEEDCTRL0 (1 << 2) -#define PBIASLITEPWRDNZ1 (1 << 9) - -/* - * OMAP HSMMC register definitions - */ -#define OMAP_HSMMC_BASE 0x4809C000 - -typedef struct hsmmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ -} hsmmc_t; - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define DATI_CMDDIS (0x1 << 1) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -typedef struct { - unsigned int card_type; - unsigned int version; - unsigned int mode; - unsigned int size; - unsigned int RCA; -} mmc_card_data; - -#define mmc_reg_out(addr, mask, val)\ - writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) - -#endif /* MMC_HOST_DEF_H */ diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-arm/arch-omap3/mux.h deleted file mode 100644 index 0c01c73..0000000 --- a/include/asm-arm/arch-omap3/mux.h +++ /dev/null @@ -1,412 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _MUX_H_ -#define _MUX_H_ - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - */ - -#define IEN (1 << 8) - -#define IDIS (0 << 8) -#define PTU (1 << 4) -#define PTD (0 << 4) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -/* - * To get the actual address the offset has to added - * with OMAP34XX_CTRL_BASE to get the actual address - */ - -/*SDRC*/ -#define CONTROL_PADCONF_SDRC_D0 0x0030 -#define CONTROL_PADCONF_SDRC_D1 0x0032 -#define CONTROL_PADCONF_SDRC_D2 0x0034 -#define CONTROL_PADCONF_SDRC_D3 0x0036 -#define CONTROL_PADCONF_SDRC_D4 0x0038 -#define CONTROL_PADCONF_SDRC_D5 0x003A -#define CONTROL_PADCONF_SDRC_D6 0x003C -#define CONTROL_PADCONF_SDRC_D7 0x003E -#define CONTROL_PADCONF_SDRC_D8 0x0040 -#define CONTROL_PADCONF_SDRC_D9 0x0042 -#define CONTROL_PADCONF_SDRC_D10 0x0044 -#define CONTROL_PADCONF_SDRC_D11 0x0046 -#define CONTROL_PADCONF_SDRC_D12 0x0048 -#define CONTROL_PADCONF_SDRC_D13 0x004A -#define CONTROL_PADCONF_SDRC_D14 0x004C -#define CONTROL_PADCONF_SDRC_D15 0x004E -#define CONTROL_PADCONF_SDRC_D16 0x0050 -#define CONTROL_PADCONF_SDRC_D17 0x0052 -#define CONTROL_PADCONF_SDRC_D18 0x0054 -#define CONTROL_PADCONF_SDRC_D19 0x0056 -#define CONTROL_PADCONF_SDRC_D20 0x0058 -#define CONTROL_PADCONF_SDRC_D21 0x005A -#define CONTROL_PADCONF_SDRC_D22 0x005C -#define CONTROL_PADCONF_SDRC_D23 0x005E -#define CONTROL_PADCONF_SDRC_D24 0x0060 -#define CONTROL_PADCONF_SDRC_D25 0x0062 -#define CONTROL_PADCONF_SDRC_D26 0x0064 -#define CONTROL_PADCONF_SDRC_D27 0x0066 -#define CONTROL_PADCONF_SDRC_D28 0x0068 -#define CONTROL_PADCONF_SDRC_D29 0x006A -#define CONTROL_PADCONF_SDRC_D30 0x006C -#define CONTROL_PADCONF_SDRC_D31 0x006E -#define CONTROL_PADCONF_SDRC_CLK 0x0070 -#define CONTROL_PADCONF_SDRC_DQS0 0x0072 -#define CONTROL_PADCONF_SDRC_DQS1 0x0074 -#define CONTROL_PADCONF_SDRC_DQS2 0x0076 -#define CONTROL_PADCONF_SDRC_DQS3 0x0078 -/*GPMC*/ -#define CONTROL_PADCONF_GPMC_A1 0x007A -#define CONTROL_PADCONF_GPMC_A2 0x007C -#define CONTROL_PADCONF_GPMC_A3 0x007E -#define CONTROL_PADCONF_GPMC_A4 0x0080 -#define CONTROL_PADCONF_GPMC_A5 0x0082 -#define CONTROL_PADCONF_GPMC_A6 0x0084 -#define CONTROL_PADCONF_GPMC_A7 0x0086 -#define CONTROL_PADCONF_GPMC_A8 0x0088 -#define CONTROL_PADCONF_GPMC_A9 0x008A -#define CONTROL_PADCONF_GPMC_A10 0x008C -#define CONTROL_PADCONF_GPMC_D0 0x008E -#define CONTROL_PADCONF_GPMC_D1 0x0090 -#define CONTROL_PADCONF_GPMC_D2 0x0092 -#define CONTROL_PADCONF_GPMC_D3 0x0094 -#define CONTROL_PADCONF_GPMC_D4 0x0096 -#define CONTROL_PADCONF_GPMC_D5 0x0098 -#define CONTROL_PADCONF_GPMC_D6 0x009A -#define CONTROL_PADCONF_GPMC_D7 0x009C -#define CONTROL_PADCONF_GPMC_D8 0x009E -#define CONTROL_PADCONF_GPMC_D9 0x00A0 -#define CONTROL_PADCONF_GPMC_D10 0x00A2 -#define CONTROL_PADCONF_GPMC_D11 0x00A4 -#define CONTROL_PADCONF_GPMC_D12 0x00A6 -#define CONTROL_PADCONF_GPMC_D13 0x00A8 -#define CONTROL_PADCONF_GPMC_D14 0x00AA -#define CONTROL_PADCONF_GPMC_D15 0x00AC -#define CONTROL_PADCONF_GPMC_NCS0 0x00AE -#define CONTROL_PADCONF_GPMC_NCS1 0x00B0 -#define CONTROL_PADCONF_GPMC_NCS2 0x00B2 -#define CONTROL_PADCONF_GPMC_NCS3 0x00B4 -#define CONTROL_PADCONF_GPMC_NCS4 0x00B6 -#define CONTROL_PADCONF_GPMC_NCS5 0x00B8 -#define CONTROL_PADCONF_GPMC_NCS6 0x00BA -#define CONTROL_PADCONF_GPMC_NCS7 0x00BC -#define CONTROL_PADCONF_GPMC_CLK 0x00BE -#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 -#define CONTROL_PADCONF_GPMC_NOE 0x00C2 -#define CONTROL_PADCONF_GPMC_NWE 0x00C4 -#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 -#define CONTROL_PADCONF_GPMC_NBE1 0x00C8 -#define CONTROL_PADCONF_GPMC_NWP 0x00CA -#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC -#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE -#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 -#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 -/*DSS*/ -#define CONTROL_PADCONF_DSS_PCLK 0x00D4 -#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 -#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 -#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA -#define CONTROL_PADCONF_DSS_DATA0 0x00DC -#define CONTROL_PADCONF_DSS_DATA1 0x00DE -#define CONTROL_PADCONF_DSS_DATA2 0x00E0 -#define CONTROL_PADCONF_DSS_DATA3 0x00E2 -#define CONTROL_PADCONF_DSS_DATA4 0x00E4 -#define CONTROL_PADCONF_DSS_DATA5 0x00E6 -#define CONTROL_PADCONF_DSS_DATA6 0x00E8 -#define CONTROL_PADCONF_DSS_DATA7 0x00EA -#define CONTROL_PADCONF_DSS_DATA8 0x00EC -#define CONTROL_PADCONF_DSS_DATA9 0x00EE -#define CONTROL_PADCONF_DSS_DATA10 0x00F0 -#define CONTROL_PADCONF_DSS_DATA11 0x00F2 -#define CONTROL_PADCONF_DSS_DATA12 0x00F4 -#define CONTROL_PADCONF_DSS_DATA13 0x00F6 -#define CONTROL_PADCONF_DSS_DATA14 0x00F8 -#define CONTROL_PADCONF_DSS_DATA15 0x00FA -#define CONTROL_PADCONF_DSS_DATA16 0x00FC -#define CONTROL_PADCONF_DSS_DATA17 0x00FE -#define CONTROL_PADCONF_DSS_DATA18 0x0100 -#define CONTROL_PADCONF_DSS_DATA19 0x0102 -#define CONTROL_PADCONF_DSS_DATA20 0x0104 -#define CONTROL_PADCONF_DSS_DATA21 0x0106 -#define CONTROL_PADCONF_DSS_DATA22 0x0108 -#define CONTROL_PADCONF_DSS_DATA23 0x010A -/*CAMERA*/ -#define CONTROL_PADCONF_CAM_HS 0x010C -#define CONTROL_PADCONF_CAM_VS 0x010E -#define CONTROL_PADCONF_CAM_XCLKA 0x0110 -#define CONTROL_PADCONF_CAM_PCLK 0x0112 -#define CONTROL_PADCONF_CAM_FLD 0x0114 -#define CONTROL_PADCONF_CAM_D0 0x0116 -#define CONTROL_PADCONF_CAM_D1 0x0118 -#define CONTROL_PADCONF_CAM_D2 0x011A -#define CONTROL_PADCONF_CAM_D3 0x011C -#define CONTROL_PADCONF_CAM_D4 0x011E -#define CONTROL_PADCONF_CAM_D5 0x0120 -#define CONTROL_PADCONF_CAM_D6 0x0122 -#define CONTROL_PADCONF_CAM_D7 0x0124 -#define CONTROL_PADCONF_CAM_D8 0x0126 -#define CONTROL_PADCONF_CAM_D9 0x0128 -#define CONTROL_PADCONF_CAM_D10 0x012A -#define CONTROL_PADCONF_CAM_D11 0x012C -#define CONTROL_PADCONF_CAM_XCLKB 0x012E -#define CONTROL_PADCONF_CAM_WEN 0x0130 -#define CONTROL_PADCONF_CAM_STROBE 0x0132 -#define CONTROL_PADCONF_CSI2_DX0 0x0134 -#define CONTROL_PADCONF_CSI2_DY0 0x0136 -#define CONTROL_PADCONF_CSI2_DX1 0x0138 -#define CONTROL_PADCONF_CSI2_DY1 0x013A -/*Audio Interface */ -#define CONTROL_PADCONF_MCBSP2_FSX 0x013C -#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E -#define CONTROL_PADCONF_MCBSP2_DR 0x0140 -#define CONTROL_PADCONF_MCBSP2_DX 0x0142 -#define CONTROL_PADCONF_MMC1_CLK 0x0144 -#define CONTROL_PADCONF_MMC1_CMD 0x0146 -#define CONTROL_PADCONF_MMC1_DAT0 0x0148 -#define CONTROL_PADCONF_MMC1_DAT1 0x014A -#define CONTROL_PADCONF_MMC1_DAT2 0x014C -#define CONTROL_PADCONF_MMC1_DAT3 0x014E -#define CONTROL_PADCONF_MMC1_DAT4 0x0150 -#define CONTROL_PADCONF_MMC1_DAT5 0x0152 -#define CONTROL_PADCONF_MMC1_DAT6 0x0154 -#define CONTROL_PADCONF_MMC1_DAT7 0x0156 -/*Wireless LAN */ -#define CONTROL_PADCONF_MMC2_CLK 0x0158 -#define CONTROL_PADCONF_MMC2_CMD 0x015A -#define CONTROL_PADCONF_MMC2_DAT0 0x015C -#define CONTROL_PADCONF_MMC2_DAT1 0x015E -#define CONTROL_PADCONF_MMC2_DAT2 0x0160 -#define CONTROL_PADCONF_MMC2_DAT3 0x0162 -#define CONTROL_PADCONF_MMC2_DAT4 0x0164 -#define CONTROL_PADCONF_MMC2_DAT5 0x0166 -#define CONTROL_PADCONF_MMC2_DAT6 0x0168 -#define CONTROL_PADCONF_MMC2_DAT7 0x016A -/*Bluetooth*/ -#define CONTROL_PADCONF_MCBSP3_DX 0x016C -#define CONTROL_PADCONF_MCBSP3_DR 0x016E -#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 -#define CONTROL_PADCONF_MCBSP3_FSX 0x0172 -#define CONTROL_PADCONF_UART2_CTS 0x0174 -#define CONTROL_PADCONF_UART2_RTS 0x0176 -#define CONTROL_PADCONF_UART2_TX 0x0178 -#define CONTROL_PADCONF_UART2_RX 0x017A -/*Modem Interface */ -#define CONTROL_PADCONF_UART1_TX 0x017C -#define CONTROL_PADCONF_UART1_RTS 0x017E -#define CONTROL_PADCONF_UART1_CTS 0x0180 -#define CONTROL_PADCONF_UART1_RX 0x0182 -#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 -#define CONTROL_PADCONF_MCBSP4_DR 0x0186 -#define CONTROL_PADCONF_MCBSP4_DX 0x0188 -#define CONTROL_PADCONF_MCBSP4_FSX 0x018A -#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C -#define CONTROL_PADCONF_MCBSP1_FSR 0x018E -#define CONTROL_PADCONF_MCBSP1_DX 0x0190 -#define CONTROL_PADCONF_MCBSP1_DR 0x0192 -#define CONTROL_PADCONF_MCBSP_CLKS 0x0194 -#define CONTROL_PADCONF_MCBSP1_FSX 0x0196 -#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 -/*Serial Interface*/ -#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A -#define CONTROL_PADCONF_UART3_RTS_SD 0x019C -#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E -#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 -#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 -#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 -#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 -#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 -#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA -#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC -#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE -#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 -#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 -#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 -#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 -#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 -#define CONTROL_PADCONF_I2C1_SCL 0x01BA -#define CONTROL_PADCONF_I2C1_SDA 0x01BC -#define CONTROL_PADCONF_I2C2_SCL 0x01BE -#define CONTROL_PADCONF_I2C2_SDA 0x01C0 -#define CONTROL_PADCONF_I2C3_SCL 0x01C2 -#define CONTROL_PADCONF_I2C3_SDA 0x01C4 -#define CONTROL_PADCONF_I2C4_SCL 0x0A00 -#define CONTROL_PADCONF_I2C4_SDA 0x0A02 -#define CONTROL_PADCONF_HDQ_SIO 0x01C6 -#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 -#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA -#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC -#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE -#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 -#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 -#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 -#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 -#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 -#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA -#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC -#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE -/*Control and debug */ -#define CONTROL_PADCONF_SYS_32K 0x0A04 -#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 -#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 -#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A -#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C -#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E -#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 -#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 -#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 -#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 -#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 -#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A -#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 -#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C -#define CONTROL_PADCONF_JTAG_TCK 0x0A1E -#define CONTROL_PADCONF_JTAG_TMS 0x0A20 -#define CONTROL_PADCONF_JTAG_TDI 0x0A22 -#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 -#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 -#define CONTROL_PADCONF_ETK_CLK 0x0A28 -#define CONTROL_PADCONF_ETK_CTL 0x0A2A -#define CONTROL_PADCONF_ETK_D0 0x0A2C -#define CONTROL_PADCONF_ETK_D1 0x0A2E -#define CONTROL_PADCONF_ETK_D2 0x0A30 -#define CONTROL_PADCONF_ETK_D3 0x0A32 -#define CONTROL_PADCONF_ETK_D4 0x0A34 -#define CONTROL_PADCONF_ETK_D5 0x0A36 -#define CONTROL_PADCONF_ETK_D6 0x0A38 -#define CONTROL_PADCONF_ETK_D7 0x0A3A -#define CONTROL_PADCONF_ETK_D8 0x0A3C -#define CONTROL_PADCONF_ETK_D9 0x0A3E -#define CONTROL_PADCONF_ETK_D10 0x0A40 -#define CONTROL_PADCONF_ETK_D11 0x0A42 -#define CONTROL_PADCONF_ETK_D12 0x0A44 -#define CONTROL_PADCONF_ETK_D13 0x0A46 -#define CONTROL_PADCONF_ETK_D14 0x0A48 -#define CONTROL_PADCONF_ETK_D15 0x0A4A -#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 -#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA -#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC -#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE -#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 -#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 -#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 -#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 -#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 -#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA -#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC -#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE -#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 -#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 -#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 -#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 -#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 -#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA -/*Die to Die */ -#define CONTROL_PADCONF_D2D_MCAD0 0x01E4 -#define CONTROL_PADCONF_D2D_MCAD1 0x01E6 -#define CONTROL_PADCONF_D2D_MCAD2 0x01E8 -#define CONTROL_PADCONF_D2D_MCAD3 0x01EA -#define CONTROL_PADCONF_D2D_MCAD4 0x01EC -#define CONTROL_PADCONF_D2D_MCAD5 0x01EE -#define CONTROL_PADCONF_D2D_MCAD6 0x01F0 -#define CONTROL_PADCONF_D2D_MCAD7 0x01F2 -#define CONTROL_PADCONF_D2D_MCAD8 0x01F4 -#define CONTROL_PADCONF_D2D_MCAD9 0x01F6 -#define CONTROL_PADCONF_D2D_MCAD10 0x01F8 -#define CONTROL_PADCONF_D2D_MCAD11 0x01FA -#define CONTROL_PADCONF_D2D_MCAD12 0x01FC -#define CONTROL_PADCONF_D2D_MCAD13 0x01FE -#define CONTROL_PADCONF_D2D_MCAD14 0x0200 -#define CONTROL_PADCONF_D2D_MCAD15 0x0202 -#define CONTROL_PADCONF_D2D_MCAD16 0x0204 -#define CONTROL_PADCONF_D2D_MCAD17 0x0206 -#define CONTROL_PADCONF_D2D_MCAD18 0x0208 -#define CONTROL_PADCONF_D2D_MCAD19 0x020A -#define CONTROL_PADCONF_D2D_MCAD20 0x020C -#define CONTROL_PADCONF_D2D_MCAD21 0x020E -#define CONTROL_PADCONF_D2D_MCAD22 0x0210 -#define CONTROL_PADCONF_D2D_MCAD23 0x0212 -#define CONTROL_PADCONF_D2D_MCAD24 0x0214 -#define CONTROL_PADCONF_D2D_MCAD25 0x0216 -#define CONTROL_PADCONF_D2D_MCAD26 0x0218 -#define CONTROL_PADCONF_D2D_MCAD27 0x021A -#define CONTROL_PADCONF_D2D_MCAD28 0x021C -#define CONTROL_PADCONF_D2D_MCAD29 0x021E -#define CONTROL_PADCONF_D2D_MCAD30 0x0220 -#define CONTROL_PADCONF_D2D_MCAD31 0x0222 -#define CONTROL_PADCONF_D2D_MCAD32 0x0224 -#define CONTROL_PADCONF_D2D_MCAD33 0x0226 -#define CONTROL_PADCONF_D2D_MCAD34 0x0228 -#define CONTROL_PADCONF_D2D_MCAD35 0x022A -#define CONTROL_PADCONF_D2D_MCAD36 0x022C -#define CONTROL_PADCONF_D2D_CLK26MI 0x022E -#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 -#define CONTROL_PADCONF_D2D_NRESWARM 0x0232 -#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 -#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 -#define CONTROL_PADCONF_D2D_SPINT 0x0238 -#define CONTROL_PADCONF_D2D_FRINT 0x023A -#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C -#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E -#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 -#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 -#define CONTROL_PADCONF_D2D_N3GTRST 0x0244 -#define CONTROL_PADCONF_D2D_N3GTDI 0x0246 -#define CONTROL_PADCONF_D2D_N3GTDO 0x0248 -#define CONTROL_PADCONF_D2D_N3GTMS 0x024A -#define CONTROL_PADCONF_D2D_N3GTCK 0x024C -#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E -#define CONTROL_PADCONF_D2D_MSTDBY 0x0250 -#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C -#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 -#define CONTROL_PADCONF_D2D_IDLEACK 0x0254 -#define CONTROL_PADCONF_D2D_MWRITE 0x0256 -#define CONTROL_PADCONF_D2D_SWRITE 0x0258 -#define CONTROL_PADCONF_D2D_MREAD 0x025A -#define CONTROL_PADCONF_D2D_SREAD 0x025C -#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E -#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 -#define CONTROL_PADCONF_SDRC_CKE0 0x0262 -#define CONTROL_PADCONF_SDRC_CKE1 0x0264 - -#define MUX_VAL(OFFSET,VALUE)\ - writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) - -#endif diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h deleted file mode 100644 index 12815f6..0000000 --- a/include/asm-arm/arch-omap3/omap3.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, - * Richard Woodruff - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP3_H_ -#define _OMAP3_H_ - -/* Stuff on L3 Interconnect */ -#define SMX_APE_BASE 0x68000000 - -/* GPMC */ -#define OMAP34XX_GPMC_BASE 0x6E000000 - -/* SMS */ -#define OMAP34XX_SMS_BASE 0x6C000000 - -/* SDRC */ -#define OMAP34XX_SDRC_BASE 0x6D000000 - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 -#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 -#define OMAP34XX_ID_L4_IO_BASE 0x4830A200 -#define OMAP34XX_L4_PER 0x49000000 -#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE - -/* CONTROL */ -#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000) - -/* UART */ -#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) -#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) -#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) - -/* General Purpose Timers */ -#define OMAP34XX_GPT1 0x48318000 -#define OMAP34XX_GPT2 0x49032000 -#define OMAP34XX_GPT3 0x49034000 -#define OMAP34XX_GPT4 0x49036000 -#define OMAP34XX_GPT5 0x49038000 -#define OMAP34XX_GPT6 0x4903A000 -#define OMAP34XX_GPT7 0x4903C000 -#define OMAP34XX_GPT8 0x4903E000 -#define OMAP34XX_GPT9 0x49040000 -#define OMAP34XX_GPT10 0x48086000 -#define OMAP34XX_GPT11 0x48088000 -#define OMAP34XX_GPT12 0x48304000 - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x4830C000 -#define WD2_BASE 0x48314000 -#define WD3_BASE 0x49030000 - -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE 0x48320000 - -#ifndef __ASSEMBLY__ - -struct s32ktimer { - unsigned char res[0x10]; - unsigned int s32k_cr; /* 0x10 */ -}; - -#endif /* __ASSEMBLY__ */ - -/* OMAP3 GPIO registers */ -#define OMAP34XX_GPIO1_BASE 0x48310000 -#define OMAP34XX_GPIO2_BASE 0x49050000 -#define OMAP34XX_GPIO3_BASE 0x49052000 -#define OMAP34XX_GPIO4_BASE 0x49054000 -#define OMAP34XX_GPIO5_BASE 0x49056000 -#define OMAP34XX_GPIO6_BASE 0x49058000 - -#ifndef __ASSEMBLY__ -struct gpio { - unsigned char res1[0x34]; - unsigned int oe; /* 0x34 */ - unsigned int datain; /* 0x38 */ - unsigned char res2[0x54]; - unsigned int cleardataout; /* 0x90 */ - unsigned int setdataout; /* 0x94 */ -}; -#endif /* __ASSEMBLY__ */ - -#define GPIO0 (0x1 << 0) -#define GPIO1 (0x1 << 1) -#define GPIO2 (0x1 << 2) -#define GPIO3 (0x1 << 3) -#define GPIO4 (0x1 << 4) -#define GPIO5 (0x1 << 5) -#define GPIO6 (0x1 << 6) -#define GPIO7 (0x1 << 7) -#define GPIO8 (0x1 << 8) -#define GPIO9 (0x1 << 9) -#define GPIO10 (0x1 << 10) -#define GPIO11 (0x1 << 11) -#define GPIO12 (0x1 << 12) -#define GPIO13 (0x1 << 13) -#define GPIO14 (0x1 << 14) -#define GPIO15 (0x1 << 15) -#define GPIO16 (0x1 << 16) -#define GPIO17 (0x1 << 17) -#define GPIO18 (0x1 << 18) -#define GPIO19 (0x1 << 19) -#define GPIO20 (0x1 << 20) -#define GPIO21 (0x1 << 21) -#define GPIO22 (0x1 << 22) -#define GPIO23 (0x1 << 23) -#define GPIO24 (0x1 << 24) -#define GPIO25 (0x1 << 25) -#define GPIO26 (0x1 << 26) -#define GPIO27 (0x1 << 27) -#define GPIO28 (0x1 << 28) -#define GPIO29 (0x1 << 29) -#define GPIO30 (0x1 << 30) -#define GPIO31 (0x1 << 31) - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ - SRAM_OFFSET2) - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define DEBUG_LED1 149 /* gpio */ -#define DEBUG_LED2 150 /* gpio */ - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module */ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_3430 0x3430 - -/* - * 343x real hardware: - * ES1 = rev 0 - * - * ES2 onwards, the value maps to contents of IDCODE register [31:28]. - * - * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing. - */ -#define CPU_3XX_ES10 0 -#define CPU_3XX_ES20 1 -#define CPU_3XX_ES21 2 -#define CPU_3XX_ES30 3 -#define CPU_3XX_ES31 4 -#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1) - -#define CPU_3XX_ID_SHIFT 28 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#endif diff --git a/include/asm-arm/arch-omap3/omap_gpmc.h b/include/asm-arm/arch-omap3/omap_gpmc.h deleted file mode 100644 index bd22bce..0000000 --- a/include/asm-arm/arch-omap3/omap_gpmc.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2004-2008 Texas Instruments, - * Rohit Choraria - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_OMAP_GPMC_H -#define __ASM_ARCH_OMAP_GPMC_H - -#define GPMC_BUF_EMPTY 0 -#define GPMC_BUF_FULL 1 - -#define ECCCLEAR (0x1 << 8) -#define ECCRESULTREG1 (0x1 << 0) -#define ECCSIZE512BYTE 0xFF -#define ECCSIZE1 (ECCSIZE512BYTE << 22) -#define ECCSIZE0 (ECCSIZE512BYTE << 12) -#define ECCSIZE0SEL (0x000 << 0) - -/* Generic ECC Layouts */ -/* Large Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ - 9, 10, 11, 12},\ - .oobfree = {\ - {.offset = 13,\ - .length = 51 } } \ -} -#endif - -/* Large Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13},\ - .oobfree = {\ - {.offset = 14,\ - .length = 50 } } \ -} -#endif - -/* Small Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {1, 2, 3},\ - .oobfree = {\ - {.offset = 4,\ - .length = 12 } } \ -} -#endif - -/* Small Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {2, 3, 4},\ - .oobfree = {\ - {.offset = 5,\ - .length = 11 } } \ -} -#endif - -#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h deleted file mode 100644 index 34bd515..0000000 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2004-2008 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -typedef struct { - u32 mtype; - char *board_string; - char *nand_string; -} omap3_sysinfo; - -void prcm_init(void); -void per_clocks_enable(void); - -void memif_init(void); -void sdrc_init(void); -void do_sdrc_init(u32, u32); -void gpmc_init(void); -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size); - -void watchdog_init(void); -void set_muxconf_regs(void); - -u32 get_cpu_rev(void); -u32 get_mem_type(void); -u32 get_sysboot_value(void); -u32 is_gpmc_muxed(void); -u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); -u32 get_sdr_cs_size(u32); -u32 get_sdr_cs_offset(u32); -u32 is_running_in_sdram(void); -u32 is_running_in_sram(void); -u32 is_running_in_flash(void); -u32 get_device_type(void); -void l2cache_enable(void); -void secureworld_exit(void); -void setup_auxcr(void); -void try_unlock_memory(void); -u32 get_boot_type(void); -void invalidate_dcache(u32); -void sr32(void *, u32, u32, u32); -u32 wait_on_value(u32, u32, void *, u32); -void sdelay(unsigned long); -void make_cs1_contiguous(void); -void omap_nand_switch_ecc(int); -void power_init_r(void); -void dieid_num_r(void); - -#endif diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h deleted file mode 100644 index 104a21c..0000000 --- a/include/asm-arm/arch-pxa/bitfield.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FILE bitfield.h - * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) - * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. - */ - - -#ifndef __BITFIELD_H -#define __BITFIELD_H - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) -#else -#define UData(Data) (Data) -#endif - - -/* - * MACRO: Fld - * - * Purpose - * The macro "Fld" encodes a bit field, given its size and its shift value - * with respect to bit 0. - * - * Note - * A more intuitive way to encode bit fields would have been to use their - * mask. However, extracting size and shift value information from a bit - * field's mask is cumbersome and might break the assembler (255-character - * line-size limit). - * - * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. - * - * Output - * Fld Encoded bit field. - */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - - -/* - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit - * - * Purpose - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return - * the size, shift value, mask, aligned mask, and first bit of a - * bit field. - * - * Input - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. - */ - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h deleted file mode 100644 index c8c479a..0000000 --- a/include/asm-arm/arch-pxa/hardware.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/hardware.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: This file was taken from linux-2.4.19-rmk4-pxa1 - * - * - 2003/01/20 implementation specifics activated - * Robert Schwebel - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include -#include - - -/* - * These are statically mapped PCMCIA IO space for designs using it as a - * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. - * The actual PCMCIA code is mapping required IO region at run time. - */ -#define PCMCIA_IO_0_BASE 0xf6000000 -#define PCMCIA_IO_1_BASE 0xf7000000 - - -/* - * We requires absolute addresses. - */ -#define PCIO_BASE 0 - -/* - * Workarounds for at least 2 errata so far require this. - * The mapping is set in mach-pxa/generic.c. - */ -#define UNCACHED_PHYS_0 0xff000000 -#define UNCACHED_ADDR UNCACHED_PHYS_0 - -/* - * Intel PXA internal I/O mappings: - * - * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff - * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff - * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff - */ - -/* FIXME: Only this does work for u-boot... find out why... [RS] */ -#define UBOOT_REG_FIX 1 - -#ifndef UBOOT_REG_FIX -#ifndef __ASSEMBLY__ - -#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) ) -#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) ) - -/* - * This __REG() version gives the same results as the one above, except - * that we are fooling gcc somehow so it generates far better and smaller - * assembly code for access to contigous registers. It's a shame that gcc - * doesn't guess this by itself. - */ -#include -typedef struct { volatile u32 offset[4096]; } __regbase; -# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] -# define __REG(x) __REGP(io_p2v(x)) -#endif - -/* Let's kick gcc's ass again... */ -# define __REG2(x,y) \ - ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ - : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) - -# define __PREG(x) (io_v2p((u32)&(x))) - -#else - -# define __REG(x) io_p2v(x) -# define __PREG(x) io_v2p(x) - -# undef io_p2v -# undef __REG -# ifndef __ASSEMBLY__ -# define io_p2v(PhAdd) (PhAdd) -# define __REG(x) (*((volatile u32 *)io_p2v(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */ -# define __REG_2(x) (x) -# define __REG_3(x) (x) -# endif -# endif -#endif /* UBOOT_REG_FIX */ - -#include "pxa-regs.h" - -#ifndef __ASSEMBLY__ - -/* - * GPIO edge detection for IRQs: - * IRQs are generated on Falling-Edge, Rising-Edge, or both. - * This must be called *before* the corresponding IRQ is registered. - * Use this instead of directly setting GRER/GFER. - */ -#define GPIO_FALLING_EDGE 1 -#define GPIO_RISING_EDGE 2 -#define GPIO_BOTH_EDGES 3 -extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask ); - -/* - * Handy routine to set GPIO alternate functions - */ -extern void set_GPIO_mode( int gpio_mode ); - -/* - * return current lclk frequency in units of 10kHz - */ -extern unsigned int get_lclk_frequency_10khz(void); - -#endif - - -/* - * Implementation specifics - */ - -#ifdef CONFIG_ARCH_LUBBOCK -#include "lubbock.h" -#endif - -#ifdef CONFIG_ARCH_PXA_IDP -#include "idp.h" -#endif - -#ifdef CONFIG_ARCH_PXA_CERF -#include "cerf.h" -#endif - -#ifdef CONFIG_ARCH_CSB226 -#include "csb226.h" -#endif - -#ifdef CONFIG_ARCH_INNOKOM -#include "innokom.h" -#endif - -#ifdef CONFIG_ARCH_PLEB -#include "pleb.h" -#endif - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h deleted file mode 100644 index a25d4c5..0000000 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ /dev/null @@ -1,2613 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/pxa-regs.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * - 2003/01/20: Robert Schwebel */ -#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ -#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ - -#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ -#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ -#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ - -#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ -#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ -#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ - -#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ -#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ -#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ - -#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ -#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ -#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ - -#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ -#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ - -#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ -#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ -#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ - -#ifdef CONFIG_CPU_MONAHANS -#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ -#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ -#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ -#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ -#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ -#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ -#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ - -#define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */ -#define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */ -#define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */ -#define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */ - -#define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */ -#define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */ -#define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */ -#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */ - -#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */ -#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */ -#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */ -#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */ - -#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */ -#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */ -#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */ -#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */ - -#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */ -#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */ -#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */ -#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */ - -#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */ -#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */ -#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */ -#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */ - -#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3) -#define GCDR(x) __REG2(0x40E00420, ((x) & 0x60) >> 3) - -/* Multi-funktion Pin Registers, uncomplete, only: - * - GPIO - * - Data Flash DF_* pins defined. - */ -#define GPIO0 __REG(0x40e10124) -#define GPIO1 __REG(0x40e10128) -#define GPIO2 __REG(0x40e1012c) -#define GPIO3 __REG(0x40e10130) -#define GPIO4 __REG(0x40e10134) -#define nXCVREN __REG(0x40e10138) - -#define DF_CLE_NOE __REG(0x40e10204) -#define DF_ALE_WE1 __REG(0x40e10208) - -#define DF_SCLK_E __REG(0x40e10210) -#define nBE0 __REG(0x40e10214) -#define nBE1 __REG(0x40e10218) -#define DF_ALE_WE2 __REG(0x40e1021c) -#define DF_INT_RnB __REG(0x40e10220) -#define DF_nCS0 __REG(0x40e10224) -#define DF_nCS1 __REG(0x40e10228) -#define DF_nWE __REG(0x40e1022c) -#define DF_nRE __REG(0x40e10230) -#define nLUA __REG(0x40e10234) -#define nLLA __REG(0x40e10238) -#define DF_ADDR0 __REG(0x40e1023c) -#define DF_ADDR1 __REG(0x40e10240) -#define DF_ADDR2 __REG(0x40e10244) -#define DF_ADDR3 __REG(0x40e10248) -#define DF_IO0 __REG(0x40e1024c) -#define DF_IO8 __REG(0x40e10250) -#define DF_IO1 __REG(0x40e10254) -#define DF_IO9 __REG(0x40e10258) -#define DF_IO2 __REG(0x40e1025c) -#define DF_IO10 __REG(0x40e10260) -#define DF_IO3 __REG(0x40e10264) -#define DF_IO11 __REG(0x40e10268) -#define DF_IO4 __REG(0x40e1026c) -#define DF_IO12 __REG(0x40e10270) -#define DF_IO5 __REG(0x40e10274) -#define DF_IO13 __REG(0x40e10278) -#define DF_IO6 __REG(0x40e1027c) -#define DF_IO14 __REG(0x40e10280) -#define DF_IO7 __REG(0x40e10284) -#define DF_IO15 __REG(0x40e10288) - -#define GPIO5 __REG(0x40e1028c) -#define GPIO6 __REG(0x40e10290) -#define GPIO7 __REG(0x40e10294) -#define GPIO8 __REG(0x40e10298) -#define GPIO9 __REG(0x40e1029c) - -#define GPIO11 __REG(0x40e102a0) -#define GPIO12 __REG(0x40e102a4) -#define GPIO13 __REG(0x40e102a8) -#define GPIO14 __REG(0x40e102ac) -#define GPIO15 __REG(0x40e102b0) -#define GPIO16 __REG(0x40e102b4) -#define GPIO17 __REG(0x40e102b8) -#define GPIO18 __REG(0x40e102bc) -#define GPIO19 __REG(0x40e102c0) -#define GPIO20 __REG(0x40e102c4) -#define GPIO21 __REG(0x40e102c8) -#define GPIO22 __REG(0x40e102cc) -#define GPIO23 __REG(0x40e102d0) -#define GPIO24 __REG(0x40e102d4) -#define GPIO25 __REG(0x40e102d8) -#define GPIO26 __REG(0x40e102dc) - -#define GPIO27 __REG(0x40e10400) -#define GPIO28 __REG(0x40e10404) -#define GPIO29 __REG(0x40e10408) -#define GPIO30 __REG(0x40e1040c) -#define GPIO31 __REG(0x40e10410) -#define GPIO32 __REG(0x40e10414) -#define GPIO33 __REG(0x40e10418) -#define GPIO34 __REG(0x40e1041c) -#define GPIO35 __REG(0x40e10420) -#define GPIO36 __REG(0x40e10424) -#define GPIO37 __REG(0x40e10428) -#define GPIO38 __REG(0x40e1042c) -#define GPIO39 __REG(0x40e10430) -#define GPIO40 __REG(0x40e10434) -#define GPIO41 __REG(0x40e10438) -#define GPIO42 __REG(0x40e1043c) -#define GPIO43 __REG(0x40e10440) -#define GPIO44 __REG(0x40e10444) -#define GPIO45 __REG(0x40e10448) -#define GPIO46 __REG(0x40e1044c) -#define GPIO47 __REG(0x40e10450) -#define GPIO48 __REG(0x40e10454) - -#define GPIO10 __REG(0x40e10458) - -#define GPIO49 __REG(0x40e1045c) -#define GPIO50 __REG(0x40e10460) -#define GPIO51 __REG(0x40e10464) -#define GPIO52 __REG(0x40e10468) -#define GPIO53 __REG(0x40e1046c) -#define GPIO54 __REG(0x40e10470) -#define GPIO55 __REG(0x40e10474) -#define GPIO56 __REG(0x40e10478) -#define GPIO57 __REG(0x40e1047c) -#define GPIO58 __REG(0x40e10480) -#define GPIO59 __REG(0x40e10484) -#define GPIO60 __REG(0x40e10488) -#define GPIO61 __REG(0x40e1048c) -#define GPIO62 __REG(0x40e10490) - -#define GPIO6_2 __REG(0x40e10494) -#define GPIO7_2 __REG(0x40e10498) -#define GPIO8_2 __REG(0x40e1049c) -#define GPIO9_2 __REG(0x40e104a0) -#define GPIO10_2 __REG(0x40e104a4) -#define GPIO11_2 __REG(0x40e104a8) -#define GPIO12_2 __REG(0x40e104ac) -#define GPIO13_2 __REG(0x40e104b0) - -#define GPIO63 __REG(0x40e104b4) -#define GPIO64 __REG(0x40e104b8) -#define GPIO65 __REG(0x40e104bc) -#define GPIO66 __REG(0x40e104c0) -#define GPIO67 __REG(0x40e104c4) -#define GPIO68 __REG(0x40e104c8) -#define GPIO69 __REG(0x40e104cc) -#define GPIO70 __REG(0x40e104d0) -#define GPIO71 __REG(0x40e104d4) -#define GPIO72 __REG(0x40e104d8) -#define GPIO73 __REG(0x40e104dc) - -#define GPIO14_2 __REG(0x40e104e0) -#define GPIO15_2 __REG(0x40e104e4) -#define GPIO16_2 __REG(0x40e104e8) -#define GPIO17_2 __REG(0x40e104ec) - -#define GPIO74 __REG(0x40e104f0) -#define GPIO75 __REG(0x40e104f4) -#define GPIO76 __REG(0x40e104f8) -#define GPIO77 __REG(0x40e104fc) -#define GPIO78 __REG(0x40e10500) -#define GPIO79 __REG(0x40e10504) -#define GPIO80 __REG(0x40e10508) -#define GPIO81 __REG(0x40e1050c) -#define GPIO82 __REG(0x40e10510) -#define GPIO83 __REG(0x40e10514) -#define GPIO84 __REG(0x40e10518) -#define GPIO85 __REG(0x40e1051c) -#define GPIO86 __REG(0x40e10520) -#define GPIO87 __REG(0x40e10524) -#define GPIO88 __REG(0x40e10528) -#define GPIO89 __REG(0x40e1052c) -#define GPIO90 __REG(0x40e10530) -#define GPIO91 __REG(0x40e10534) -#define GPIO92 __REG(0x40e10538) -#define GPIO93 __REG(0x40e1053c) -#define GPIO94 __REG(0x40e10540) -#define GPIO95 __REG(0x40e10544) -#define GPIO96 __REG(0x40e10548) -#define GPIO97 __REG(0x40e1054c) -#define GPIO98 __REG(0x40e10550) - -#define GPIO99 __REG(0x40e10600) -#define GPIO100 __REG(0x40e10604) -#define GPIO101 __REG(0x40e10608) -#define GPIO102 __REG(0x40e1060c) -#define GPIO103 __REG(0x40e10610) -#define GPIO104 __REG(0x40e10614) -#define GPIO105 __REG(0x40e10618) -#define GPIO106 __REG(0x40e1061c) -#define GPIO107 __REG(0x40e10620) -#define GPIO108 __REG(0x40e10624) -#define GPIO109 __REG(0x40e10628) -#define GPIO110 __REG(0x40e1062c) -#define GPIO111 __REG(0x40e10630) -#define GPIO112 __REG(0x40e10634) - -#define GPIO113 __REG(0x40e10638) -#define GPIO114 __REG(0x40e1063c) -#define GPIO115 __REG(0x40e10640) -#define GPIO116 __REG(0x40e10644) -#define GPIO117 __REG(0x40e10648) -#define GPIO118 __REG(0x40e1064c) -#define GPIO119 __REG(0x40e10650) -#define GPIO120 __REG(0x40e10654) -#define GPIO121 __REG(0x40e10658) -#define GPIO122 __REG(0x40e1065c) -#define GPIO123 __REG(0x40e10660) -#define GPIO124 __REG(0x40e10664) -#define GPIO125 __REG(0x40e10668) -#define GPIO126 __REG(0x40e1066c) -#define GPIO127 __REG(0x40e10670) - -#define GPIO0_2 __REG(0x40e10674) -#define GPIO1_2 __REG(0x40e10678) -#define GPIO2_2 __REG(0x40e1067c) -#define GPIO3_2 __REG(0x40e10680) -#define GPIO4_2 __REG(0x40e10684) -#define GPIO5_2 __REG(0x40e10688) - -/* MFPR Bit Definitions, see 4-10, Vol. 1 */ -#define PULL_SEL 0x8000 -#define PULLUP_EN 0x4000 -#define PULLDOWN_EN 0x2000 - -#define DRIVE_FAST_1mA 0x0 -#define DRIVE_FAST_2mA 0x400 -#define DRIVE_FAST_3mA 0x800 -#define DRIVE_FAST_4mA 0xC00 -#define DRIVE_SLOW_6mA 0x1000 -#define DRIVE_FAST_6mA 0x1400 -#define DRIVE_SLOW_10mA 0x1800 -#define DRIVE_FAST_10mA 0x1C00 - -#define SLEEP_SEL 0x200 -#define SLEEP_DATA 0x100 -#define SLEEP_OE_N 0x80 -#define EDGE_CLEAR 0x40 -#define EDGE_FALL_EN 0x20 -#define EDGE_RISE_EN 0x10 - -#define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */ -#define AF_SEL_1 0x1 /* Alternate function 1 */ -#define AF_SEL_2 0x2 /* Alternate function 2 */ -#define AF_SEL_3 0x3 /* Alternate function 3 */ -#define AF_SEL_4 0x4 /* Alternate function 4 */ -#define AF_SEL_5 0x5 /* Alternate function 5 */ -#define AF_SEL_6 0x6 /* Alternate function 6 */ -#define AF_SEL_7 0x7 /* Alternate function 7 */ - - -#else /* CONFIG_CPU_MONAHANS */ - -#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ -#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ -#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ -#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ -#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ -#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */ -#endif /* CONFIG_CPU_MONAHANS */ - -/* More handy macros. The argument is a literal GPIO number. */ - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) - -#ifdef CONFIG_PXA27X - -/* Interrupt Controller */ - -#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ -#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ -#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ - -#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) - -#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) -#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) -#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) -#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) -#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) -#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) -#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) -#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ - ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) -#else - -#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) - -#endif - -/* GPIO alternate function assignments */ - -#define GPIO1_RST 1 /* reset */ -#define GPIO6_MMCCLK 6 /* MMC Clock */ -#define GPIO8_48MHz 7 /* 48 MHz clock output */ -#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ -#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ -#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ -#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ -#define GPIO12_32KHz 12 /* 32 kHz out */ -#define GPIO13_MBGNT 13 /* memory controller grant */ -#define GPIO14_MBREQ 14 /* alternate bus master request */ -#define GPIO15_nCS_1 15 /* chip select 1 */ -#define GPIO16_PWM0 16 /* PWM0 output */ -#define GPIO17_PWM1 17 /* PWM1 output */ -#define GPIO18_RDY 18 /* Ext. Bus Ready */ -#define GPIO19_DREQ1 19 /* External DMA Request */ -#define GPIO20_DREQ0 20 /* External DMA Request */ -#define GPIO23_SCLK 23 /* SSP clock */ -#define GPIO24_SFRM 24 /* SSP Frame */ -#define GPIO25_STXD 25 /* SSP transmit */ -#define GPIO26_SRXD 26 /* SSP receive */ -#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ -#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ -#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ -#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ -#define GPIO31_SYNC 31 /* AC97/I2S sync */ -#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ -#define GPIO33_nCS_5 33 /* chip select 5 */ -#define GPIO34_FFRXD 34 /* FFUART receive */ -#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ -#define GPIO35_FFCTS 35 /* FFUART Clear to send */ -#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ -#define GPIO37_FFDSR 37 /* FFUART data set ready */ -#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ -#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ -#define GPIO39_FFTXD 39 /* FFUART transmit data */ -#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ -#define GPIO41_FFRTS 41 /* FFUART request to send */ -#define GPIO42_BTRXD 42 /* BTUART receive data */ -#define GPIO43_BTTXD 43 /* BTUART transmit data */ -#define GPIO44_BTCTS 44 /* BTUART clear to send */ -#define GPIO45_BTRTS 45 /* BTUART request to send */ -#define GPIO46_ICPRXD 46 /* ICP receive data */ -#define GPIO46_STRXD 46 /* STD_UART receive data */ -#define GPIO47_ICPTXD 47 /* ICP transmit data */ -#define GPIO47_STTXD 47 /* STD_UART transmit data */ -#define GPIO48_nPOE 48 /* Output Enable for Card Space */ -#define GPIO49_nPWE 49 /* Write Enable for Card Space */ -#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ -#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ -#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ -#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ -#define GPIO53_MMCCLK 53 /* MMC Clock */ -#define GPIO54_MMCCLK 54 /* MMC Clock */ -#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ -#define GPIO55_nPREG 55 /* Card Address bit 26 */ -#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ -#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ -#define GPIO58_LDD_0 58 /* LCD data pin 0 */ -#define GPIO59_LDD_1 59 /* LCD data pin 1 */ -#define GPIO60_LDD_2 60 /* LCD data pin 2 */ -#define GPIO61_LDD_3 61 /* LCD data pin 3 */ -#define GPIO62_LDD_4 62 /* LCD data pin 4 */ -#define GPIO63_LDD_5 63 /* LCD data pin 5 */ -#define GPIO64_LDD_6 64 /* LCD data pin 6 */ -#define GPIO65_LDD_7 65 /* LCD data pin 7 */ -#define GPIO66_LDD_8 66 /* LCD data pin 8 */ -#define GPIO66_MBREQ 66 /* alternate bus master req */ -#define GPIO67_LDD_9 67 /* LCD data pin 9 */ -#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ -#define GPIO68_LDD_10 68 /* LCD data pin 10 */ -#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ -#define GPIO69_LDD_11 69 /* LCD data pin 11 */ -#define GPIO69_MMCCLK 69 /* MMC_CLK */ -#define GPIO70_LDD_12 70 /* LCD data pin 12 */ -#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ -#define GPIO71_LDD_13 71 /* LCD data pin 13 */ -#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ -#define GPIO72_LDD_14 72 /* LCD data pin 14 */ -#define GPIO72_32kHz 72 /* 32 kHz clock */ -#define GPIO73_LDD_15 73 /* LCD data pin 15 */ -#define GPIO73_MBGNT 73 /* Memory controller grant */ -#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ -#define GPIO75_LCD_LCLK 75 /* LCD line clock */ -#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ -#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ -#define GPIO78_nCS_2 78 /* chip select 2 */ -#define GPIO79_nCS_3 79 /* chip select 3 */ -#define GPIO80_nCS_4 80 /* chip select 4 */ - -/* GPIO alternate function mode & direction */ - -#define GPIO_IN 0x000 -#define GPIO_OUT 0x080 -#define GPIO_ALT_FN_1_IN 0x100 -#define GPIO_ALT_FN_1_OUT 0x180 -#define GPIO_ALT_FN_2_IN 0x200 -#define GPIO_ALT_FN_2_OUT 0x280 -#define GPIO_ALT_FN_3_IN 0x300 -#define GPIO_ALT_FN_3_OUT 0x380 -#define GPIO_MD_MASK_NR 0x07f -#define GPIO_MD_MASK_DIR 0x080 -#define GPIO_MD_MASK_FN 0x300 - -#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) -#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) -#define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) -#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) -#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) -#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) -#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) -#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) -#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) -#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) -#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) -#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) -#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) -#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) -#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT) -#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) -#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) -#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) -#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN) -#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) -#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) -#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) -#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) -#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) -#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) -#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) -#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) -#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) -#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) -#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) -#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) -#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) -#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) -#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) -#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) -#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) -#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) -#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) -#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) -#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) -#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) -#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) -#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) -#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) -#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) -#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) -#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) -#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) -#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) -#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) -#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) -#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) -#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) -#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) -#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) -#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) -#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) -#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) -#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) -#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) -#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) -#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) -#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) -#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) -#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) -#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) -#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) -#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) -#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) -#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) -#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) -#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) -#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) -#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) -#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) -#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) -#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) -#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) -#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) -#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) -#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) -#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) -#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) -#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) -#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) -#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) -#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) -#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) - -#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT) -#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT) - -/* - * Power Manager - */ -#ifdef CONFIG_CPU_MONAHANS - -#define ASCR __REG(0x40F40000) /* Application Subsystem Power Status/Control Register */ -#define ARSR __REG(0x40F40004) /* Application Subsystem Reset Status Register */ -#define AD3ER __REG(0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */ -#define AD3SR __REG(0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */ -#define AD2D0ER __REG(0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */ -#define AD2D0SR __REG(0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */ -#define AD2D1ER __REG(0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */ -#define AD2D1SR __REG(0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */ -#define AD1D0ER __REG(0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */ -#define AD1D0SR __REG(0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */ -#define ASDCNT __REG(0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */ -#define AD3R __REG(0x40F40030) /* Application Subsystem D3 State Configuration Register */ -#define AD2R __REG(0x40F40034) /* Application Subsystem D2 State Configuration Register */ -#define AD1R __REG(0x40F40038) /* Application Subsystem D1 State Configuration Register */ - -#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ -#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ -#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ -#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ -#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ -#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ -#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ -#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ -#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ -#define PCMD(x) __REG(0x40F50110 + x*4) -#define PCMD0 __REG(0x40F50110 + 0 * 4) -#define PCMD1 __REG(0x40F50110 + 1 * 4) -#define PCMD2 __REG(0x40F50110 + 2 * 4) -#define PCMD3 __REG(0x40F50110 + 3 * 4) -#define PCMD4 __REG(0x40F50110 + 4 * 4) -#define PCMD5 __REG(0x40F50110 + 5 * 4) -#define PCMD6 __REG(0x40F50110 + 6 * 4) -#define PCMD7 __REG(0x40F50110 + 7 * 4) -#define PCMD8 __REG(0x40F50110 + 8 * 4) -#define PCMD9 __REG(0x40F50110 + 9 * 4) -#define PCMD10 __REG(0x40F50110 + 10 * 4) -#define PCMD11 __REG(0x40F50110 + 11 * 4) -#define PCMD12 __REG(0x40F50110 + 12 * 4) -#define PCMD13 __REG(0x40F50110 + 13 * 4) -#define PCMD14 __REG(0x40F50110 + 14 * 4) -#define PCMD15 __REG(0x40F50110 + 15 * 4) -#define PCMD16 __REG(0x40F50110 + 16 * 4) -#define PCMD17 __REG(0x40F50110 + 17 * 4) -#define PCMD18 __REG(0x40F50110 + 18 * 4) -#define PCMD19 __REG(0x40F50110 + 19 * 4) -#define PCMD20 __REG(0x40F50110 + 20 * 4) -#define PCMD21 __REG(0x40F50110 + 21 * 4) -#define PCMD22 __REG(0x40F50110 + 22 * 4) -#define PCMD23 __REG(0x40F50110 + 23 * 4) -#define PCMD24 __REG(0x40F50110 + 24 * 4) -#define PCMD25 __REG(0x40F50110 + 25 * 4) -#define PCMD26 __REG(0x40F50110 + 26 * 4) -#define PCMD27 __REG(0x40F50110 + 27 * 4) -#define PCMD28 __REG(0x40F50110 + 28 * 4) -#define PCMD29 __REG(0x40F50110 + 29 * 4) -#define PCMD30 __REG(0x40F50110 + 30 * 4) -#define PCMD31 __REG(0x40F50110 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -#define PCMD_SQC (3<<8) /* only 00 and 01 are valid */ - -#define PVCR_FVC (0x1 << 28) -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -#define PVCR_ReadPointer (0x01f00000) -#define PVCR_SlaveAddress (0x7f) - -#else /* ifdef CONFIG_CPU_MONAHANS */ - -#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ -#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ -#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ -#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ -#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ -#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ -#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ -#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ -#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ -#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ -#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ -#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ -#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ - -#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ -#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ -#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ -#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ -#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ -#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ -#define PCMD(x) __REG(0x40F00080 + x*4) -#define PCMD0 __REG(0x40F00080 + 0 * 4) -#define PCMD1 __REG(0x40F00080 + 1 * 4) -#define PCMD2 __REG(0x40F00080 + 2 * 4) -#define PCMD3 __REG(0x40F00080 + 3 * 4) -#define PCMD4 __REG(0x40F00080 + 4 * 4) -#define PCMD5 __REG(0x40F00080 + 5 * 4) -#define PCMD6 __REG(0x40F00080 + 6 * 4) -#define PCMD7 __REG(0x40F00080 + 7 * 4) -#define PCMD8 __REG(0x40F00080 + 8 * 4) -#define PCMD9 __REG(0x40F00080 + 9 * 4) -#define PCMD10 __REG(0x40F00080 + 10 * 4) -#define PCMD11 __REG(0x40F00080 + 11 * 4) -#define PCMD12 __REG(0x40F00080 + 12 * 4) -#define PCMD13 __REG(0x40F00080 + 13 * 4) -#define PCMD14 __REG(0x40F00080 + 14 * 4) -#define PCMD15 __REG(0x40F00080 + 15 * 4) -#define PCMD16 __REG(0x40F00080 + 16 * 4) -#define PCMD17 __REG(0x40F00080 + 17 * 4) -#define PCMD18 __REG(0x40F00080 + 18 * 4) -#define PCMD19 __REG(0x40F00080 + 19 * 4) -#define PCMD20 __REG(0x40F00080 + 20 * 4) -#define PCMD21 __REG(0x40F00080 + 21 * 4) -#define PCMD22 __REG(0x40F00080 + 22 * 4) -#define PCMD23 __REG(0x40F00080 + 23 * 4) -#define PCMD24 __REG(0x40F00080 + 24 * 4) -#define PCMD25 __REG(0x40F00080 + 25 * 4) -#define PCMD26 __REG(0x40F00080 + 26 * 4) -#define PCMD27 __REG(0x40F00080 + 27 * 4) -#define PCMD28 __REG(0x40F00080 + 28 * 4) -#define PCMD29 __REG(0x40F00080 + 29 * 4) -#define PCMD30 __REG(0x40F00080 + 30 * 4) -#define PCMD31 __REG(0x40F00080 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -/* FIXME: PCMD_SQC need be checked. */ -#define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */ - /* bit 9 should be 0 all day. */ -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -/* define MACRO for Power Manager General Configuration Register (PCFR) */ -#define PCFR_FVC (0x1 << 10) -#define PCFR_PI2C_EN (0x1 << 6) - -#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ -#define PSSR_RDH (1 << 5) /* Read Disable Hold */ -#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ -#define PSSR_VFS (1 << 2) /* VDD Fault Status */ -#define PSSR_BFS (1 << 1) /* Battery Fault Status */ -#define PSSR_SSS (1 << 0) /* Software Sleep Status */ - -#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ -#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ -#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ -#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ - -#define RCSR_GPR (1 << 3) /* GPIO Reset */ -#define RCSR_SMR (1 << 2) /* Sleep Mode */ -#define RCSR_WDR (1 << 1) /* Watchdog Reset */ -#define RCSR_HWR (1 << 0) /* Hardware Reset */ - -#endif /* CONFIG_CPU_MONAHANS */ - -/* - * SSP Serial Port Registers - */ -#define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */ -#define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */ -#define SSSR __REG(0x41000008) /* SSP Status Register */ -#define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */ -#define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ - -/* - * MultiMediaCard (MMC) controller - */ -#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ -#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ -#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ -#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ -#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ -#define MMC_RESTO __REG(0x41100014) /* Expected response time out */ -#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ -#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ -#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ -#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ -#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ -#define MMC_CMD __REG(0x41100030) /* Index of current command */ -#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ -#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ -#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ -#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ -#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ - -/* - * Core Clock - */ - -#if defined(CONFIG_CPU_MONAHANS) -#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ -#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ -#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ -#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ -#define CKENB __REG(0x41340010) /* B Clock Enable Register */ -#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ - -#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */ -#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */ -#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */ -#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */ -#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */ -#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */ -#define ACCR_XPDIS (1 << 31) -#define ACCR_SPDIS (1 << 30) -#define ACCR_13MEND1 (1 << 27) -#define ACCR_D0CS (1 << 26) -#define ACCR_13MEND2 (1 << 21) -#define ACCR_PCCE (1 << 11) - -#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ -#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ -#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ -#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ -#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ -#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ -#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ -#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ -#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ -#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ -#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ -#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ -#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ -#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ -#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ -#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ -#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ -#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ -#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ -#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ -#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ -#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ -#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ -#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ -#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ -#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ -#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ -#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ - -#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ -#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ -#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ -#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ -#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ -#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ - -#else /* if defined CONFIG_CPU_MONAHANS */ - -#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ -#define CKEN __REG(0x41300004) /* Clock Enable Register */ -#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ - -#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#if !defined(CONFIG_PXA27X) -#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ -#endif -#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ - -#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ -#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ -#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ -#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ -#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ -#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ -#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ -#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#if defined(CONFIG_PXA27X) -#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ -#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ -#endif -#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ -#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ -#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ -#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ -#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ -#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ -#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ -#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ - -#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ -#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ - -#if !defined(CONFIG_PXA27X) -#define CCCR_L09 (0x1F) -#define CCCR_L27 (0x1) -#define CCCR_L32 (0x2) -#define CCCR_L36 (0x3) -#define CCCR_L40 (0x4) -#define CCCR_L45 (0x5) - -#define CCCR_M1 (0x1 << 5) -#define CCCR_M2 (0x2 << 5) -#define CCCR_M4 (0x3 << 5) - -#define CCCR_N10 (0x2 << 7) -#define CCCR_N15 (0x3 << 7) -#define CCCR_N20 (0x4 << 7) -#define CCCR_N25 (0x5 << 7) -#define CCCR_N30 (0x6 << 7) -#endif - -#endif /* CONFIG_CPU_MONAHANS */ - -/* - * LCD - */ -#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */ -#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ -#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ -#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ -#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ -#define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */ -#define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */ -#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */ -#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */ -#define TMEDCR __REG(0x44000044) /* TMED Control Register */ - -#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ -#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ -#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */ -#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */ -#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */ -#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */ -#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */ -#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */ - -#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ -#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ -#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */ -#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ -#define LCCR0_SFM (1 << 4) /* Start of frame mask */ -#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ -#define LCCR0_EFM (1 << 6) /* End of Frame mask */ -#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */ -#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */ -#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ -#define LCCR0_DIS (1 << 10) /* LCD Disable */ -#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ -#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ -#define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ -#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#if defined(CONFIG_PXA27X) -#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ -#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ -#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ -#endif - -#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ - (((Pixel) - 1) << FShft (LCCR1_PPL)) - -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [1..64 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_HSW)) - -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) - -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) - - -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) - -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) - -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) - -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) - -#if 0 -#define LCCR3_PCD (0xff) /* Pixel clock divisor */ -#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */ -#define LCCR3_ACB_S 8 -#endif - -#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ -#define LCCR3_API_S 16 -#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ -#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ -#define LCCR3_PCP (1 << 22) /* pixel clock polarity */ -#define LCCR3_OEP (1 << 23) /* output enable polarity */ -#if 0 -#define LCCR3_BPP (7 << 24) /* bits per pixel */ -#define LCCR3_BPP_S 24 -#endif -#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ - -#define LCCR3_PDFOR_0 (0 << 30) -#define LCCR3_PDFOR_1 (1 << 30) -#define LCCR3_PDFOR_2 (2 << 30) -#define LCCR3_PDFOR_3 (3 << 30) - - -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ - (((Div) << FShft (LCCR3_PCD))) - - -#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ -#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ - ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26))) - -#define LCCR3_ACB Fld (8, 8) /* AC Bias */ -#define LCCR3_Acb(Acb) /* BAC Bias */ \ - (((Acb) << FShft (LCCR3_ACB))) - -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ - -#define LCSR0_LDD (1 << 0) /* LCD Disable Done */ -#define LCSR0_SOF (1 << 1) /* Start of frame */ -#define LCSR0_BER (1 << 2) /* Bus error */ -#define LCSR0_ABC (1 << 3) /* AC Bias count */ -#define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */ -#define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */ -#define LCSR0_OU (1 << 6) /* output FIFO underrun */ -#define LCSR0_QD (1 << 7) /* quick disable */ -#define LCSR0_EOF0 (1 << 8) /* end of frame */ -#define LCSR0_BS (1 << 9) /* branch status */ -#define LCSR0_SINT (1 << 10) /* subsequent interrupt */ - -#define LCSR1_SOF1 (1 << 0) -#define LCSR1_SOF2 (1 << 1) -#define LCSR1_SOF3 (1 << 2) -#define LCSR1_SOF4 (1 << 3) -#define LCSR1_SOF5 (1 << 4) -#define LCSR1_SOF6 (1 << 5) - -#define LCSR1_EOF1 (1 << 8) -#define LCSR1_EOF2 (1 << 9) -#define LCSR1_EOF3 (1 << 10) -#define LCSR1_EOF4 (1 << 11) -#define LCSR1_EOF5 (1 << 12) -#define LCSR1_EOF6 (1 << 13) - -#define LCSR1_BS1 (1 << 16) -#define LCSR1_BS2 (1 << 17) -#define LCSR1_BS3 (1 << 18) -#define LCSR1_BS4 (1 << 19) -#define LCSR1_BS5 (1 << 20) -#define LCSR1_BS6 (1 << 21) - -#define LCSR1_IU2 (1 << 25) -#define LCSR1_IU3 (1 << 26) -#define LCSR1_IU4 (1 << 27) -#define LCSR1_IU5 (1 << 28) -#define LCSR1_IU6 (1 << 29) - -#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -#if defined(CONFIG_PXA27X) -#define LDCMD_SOFINT (1 << 22) -#define LDCMD_EOFINT (1 << 21) -#endif - -/* - * Memory controller - */ - -#ifdef CONFIG_CPU_MONAHANS -/* Static Memory Controller Registers */ -#define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */ -#define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */ -#define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */ -#define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */ -#define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */ -#define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */ -#define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */ -#define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */ -#define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */ -#define CLK_RET_DEL __REG_2(0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */ -#define ADV_RET_DEL __REG_2(0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */ - -/* Dynamic Memory Controller Registers */ -#define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */ -#define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */ -#define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */ -#define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */ -#define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_WCAL __REG_2(0x48100068) /* DDR Write Strobe Calibration Register */ -#define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */ -#define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */ -#define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */ -#define EMPI __REG_2(0x48100090) /* EMPI Control Register */ -#define RCOMP __REG_2(0x48100100) -#define PAD_MA __REG_2(0x48100110) -#define PAD_MDMSB __REG_2(0x48100114) -#define PAD_MDLSB __REG_2(0x48100118) -#define PAD_DMEM __REG_2(0x4810011c) -#define PAD_SDCLK __REG_2(0x48100120) -#define PAD_SDCS __REG_2(0x48100124) -#define PAD_SMEM __REG_2(0x48100128) -#define PAD_SCLK __REG_2(0x4810012C) -#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */ - -/* Some frequently used bits */ -#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */ -#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */ -#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */ -#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */ - -#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */ -#define MDCNFG_DTC_1 0x100 -#define MDCNFG_DTC_2 0x200 -#define MDCNFG_DTC_3 0x300 - -#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */ -#define MDCNFG_DRAC_13 0x20 -#define MDCNFG_DRAC_14 0x40 - -#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */ -#define MDCNFG_DCAC_10 0x08 -#define MDCNFG_DCAC_11 0x10 - -#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */ -#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */ -#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */ - - -/* Data Flash Controller Registers */ - -#define NDCR __REG(0x43100000) /* Data Flash Control register */ -#define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ -/* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ -#define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ -/* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ -#define NDSR __REG(0x43100014) /* Data Controller Status Register */ -#define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */ -#define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */ -#define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */ -#define NDDB __REG(0x43100040) /* Data Controller Data Buffer */ -#define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */ -#define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */ -#define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */ - -#define NDCR_SPARE_EN (0x1<<31) -#define NDCR_ECC_EN (0x1<<30) -#define NDCR_DMA_EN (0x1<<29) -#define NDCR_ND_RUN (0x1<<28) -#define NDCR_DWIDTH_C (0x1<<27) -#define NDCR_DWIDTH_M (0x1<<26) -#define NDCR_PAGE_SZ (0x3<<24) -#define NDCR_NCSX (0x1<<23) -#define NDCR_ND_STOP (0x1<<22) -/* reserved: - * #define NDCR_ND_MODE (0x3<<21) - * #define NDCR_NAND_MODE 0x0 */ -#define NDCR_CLR_PG_CNT (0x1<<20) -#define NDCR_CLR_ECC (0x1<<19) -#define NDCR_RD_ID_CNT (0x7<<16) -#define NDCR_RA_START (0x1<<15) -#define NDCR_PG_PER_BLK (0x1<<14) -#define NDCR_ND_ARB_EN (0x1<<12) -#define NDCR_RDYM (0x1<<11) -#define NDCR_CS0_PAGEDM (0x1<<10) -#define NDCR_CS1_PAGEDM (0x1<<9) -#define NDCR_CS0_CMDDM (0x1<<8) -#define NDCR_CS1_CMDDM (0x1<<7) -#define NDCR_CS0_BBDM (0x1<<6) -#define NDCR_CS1_BBDM (0x1<<5) -#define NDCR_DBERRM (0x1<<4) -#define NDCR_SBERRM (0x1<<3) -#define NDCR_WRDREQM (0x1<<2) -#define NDCR_RDDREQM (0x1<<1) -#define NDCR_WRCMDREQM (0x1) - -#define NDSR_RDY (0x1<<11) -#define NDSR_CS0_PAGED (0x1<<10) -#define NDSR_CS1_PAGED (0x1<<9) -#define NDSR_CS0_CMDD (0x1<<8) -#define NDSR_CS1_CMDD (0x1<<7) -#define NDSR_CS0_BBD (0x1<<6) -#define NDSR_CS1_BBD (0x1<<5) -#define NDSR_DBERR (0x1<<4) -#define NDSR_SBERR (0x1<<3) -#define NDSR_WRDREQ (0x1<<2) -#define NDSR_RDDREQ (0x1<<1) -#define NDSR_WRCMDREQ (0x1) - -#define NDCB0_AUTO_RS (0x1<<25) -#define NDCB0_CSEL (0x1<<24) -#define NDCB0_CMD_TYPE (0x7<<21) -#define NDCB0_NC (0x1<<20) -#define NDCB0_DBC (0x1<<19) -#define NDCB0_ADDR_CYC (0x7<<16) -#define NDCB0_CMD2 (0xff<<8) -#define NDCB0_CMD1 (0xff) -#define MCMEM(s) MCMEM0 -#define MCATT(s) MCATT0 -#define MCIO(s) MCIO0 -#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */ - -/* Maximum values for NAND Interface Timing Registers in DFC clock - * periods */ -#define DFC_MAX_tCH 7 -#define DFC_MAX_tCS 7 -#define DFC_MAX_tWH 7 -#define DFC_MAX_tWP 7 -#define DFC_MAX_tRH 7 -#define DFC_MAX_tRP 15 -#define DFC_MAX_tR 65535 -#define DFC_MAX_tWHR 15 -#define DFC_MAX_tAR 15 - -#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */ -#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */ - -#else /* CONFIG_CPU_MONAHANS */ - -#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */ -#define MDCNFG_OFFSET 0x0 -#define MDREFR_OFFSET 0x4 -#define MSC0_OFFSET 0x8 -#define MSC1_OFFSET 0xC -#define MSC2_OFFSET 0x10 -#define MECR_OFFSET 0x14 -#define SXLCR_OFFSET 0x18 -#define SXCNFG_OFFSET 0x1C -#define FLYCNFG_OFFSET 0x20 -#define SXMRS_OFFSET 0x24 -#define MCMEM0_OFFSET 0x28 -#define MCMEM1_OFFSET 0x2C -#define MCATT0_OFFSET 0x30 -#define MCATT1_OFFSET 0x34 -#define MCIO0_OFFSET 0x38 -#define MCIO1_OFFSET 0x3C -#define MDMRS_OFFSET 0x40 - -#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ -#define MDCNFG_DE0 0x00000001 -#define MDCNFG_DE1 0x00000002 -#define MDCNFG_DE2 0x00010000 -#define MDCNFG_DE3 0x00020000 -#define MDCNFG_DWID0 0x00000004 - -#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ -#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ -#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ -#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ -#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ -#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ - -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - -#if defined(CONFIG_PXA27X) - -#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ - -#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ -#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ -#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ -#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ -#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ -#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ -#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ -#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ -#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ - -#endif /* CONFIG_CPU_MONAHANS */ - -/* Interrupt Controller */ - -#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ -#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ -#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ - -/* General Purpose I/O */ - -#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ -#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ -#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ -#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ -#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ -#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO <127:96> */ -#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ -#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ - -/* Core Clock */ - -#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ - -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controler */ -#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ -#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ -#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ -#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ - -/* Memory controller */ - -#define MDREFR_K0DB4 (1 << 29) /* SDCLK[0] divide by 4 */ - -/* LCD registers */ -#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */ -#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */ -#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ -#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ -#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */ -#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */ -#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */ -#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */ -#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */ -#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */ -#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */ -#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */ -#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */ -#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */ -#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */ -#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */ -#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */ -#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */ -#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */ -#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */ -#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */ -#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */ -#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */ - -#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */ -#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */ -#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */ -#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */ -#define CCR __REG(0x44000090) /* Cursor Control Register */ - -#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */ -#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */ - -#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */ -#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */ - -#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */ -#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */ -#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */ -#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */ -#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */ -#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */ - -#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */ -#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */ -#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */ -#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */ -#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */ -#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */ - -#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */ -#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */ -#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */ -#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */ -#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */ -#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */ - -#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */ -#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */ -#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */ - -#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */ -#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */ -#define CCR_CEN (1<<31) /* Enable bit for Cursor */ - -/* Keypad controller */ - -#define KPC __REG(0x41500000) /* Keypad Interface Control register */ -#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */ -#define KPREC __REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */ -#define KPMK __REG(0x41500018) /* Keypad Intefcace Matrix Key register */ -#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */ -#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ -#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ -#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ -#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ -#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */ - -#define KPC_AS (0x1 << 30) /* Automatic Scan bit */ -#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ -#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ -#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ -#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ -#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ -#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ -#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ -#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ -#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ -#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ -#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ -#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ -#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ -#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */ -#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ -#define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */ -#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ -#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ - -#define KPDK_DKP (0x1 << 31) -#define KPDK_DK7 (0x1 << 7) -#define KPDK_DK6 (0x1 << 6) -#define KPDK_DK5 (0x1 << 5) -#define KPDK_DK4 (0x1 << 4) -#define KPDK_DK3 (0x1 << 3) -#define KPDK_DK2 (0x1 << 2) -#define KPDK_DK1 (0x1 << 1) -#define KPDK_DK0 (0x1 << 0) - -#define KPREC_OF1 (0x1 << 31) -#define kPREC_UF1 (0x1 << 30) -#define KPREC_OF0 (0x1 << 15) -#define KPREC_UF0 (0x1 << 14) - -#define KPMK_MKP (0x1 << 31) -#define KPAS_SO (0x1 << 31) -#define KPASMKPx_SO (0x1 << 31) - -#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ -#define PSLR __REG(0x40F00034) -#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */ -#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */ -#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */ -#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */ -#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */ -#define OSMR4 __REG(0x40A00080) /* */ -#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ -#define OMCR4 __REG(0x40A000C0) /* */ - -#endif /* CONFIG_PXA27X */ - -#endif /* _PXA_REGS_H_ */ diff --git a/include/asm-arm/arch-s3c24x0/memory.h b/include/asm-arm/arch-s3c24x0/memory.h deleted file mode 100644 index 61d6270..0000000 --- a/include/asm-arm/arch-s3c24x0/memory.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * linux/include/asm-arm/arch-s3c2400/memory.h by garyj@denx.de - * based on - * linux/include/asm-arm/arch-sa1100/memory.h - * - * Copyright (c) 1999 Nicolas Pitre - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - - -/* - * Task size: 3GB - */ -#define TASK_SIZE (0xc0000000UL) -#define TASK_SIZE_26 (0x04000000UL) - -/* - * This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) - -/* - * Page offset: 3GB - */ -#define PAGE_OFFSET (0xc0000000UL) - -/* - * Physical DRAM offset is 0x0c000000 on the S3C2400 - */ -#define PHYS_OFFSET (0x0c000000UL) - -#include - - -/* Modified for S3C2400, by chc, 20010509 */ -#define RAM_IN_BANK_0 32*1024*1024 -#define RAM_IN_BANK_1 0 -#define RAM_IN_BANK_2 0 -#define RAM_IN_BANK_3 0 - -#define MEM_SIZE (RAM_IN_BANK_0+RAM_IN_BANK_1+RAM_IN_BANK_2+RAM_IN_BANK_3) - - -/* translation macros */ -#define __virt_to_phys__is_a_macro -#define __phys_to_virt__is_a_macro - -#if (RAM_IN_BANK_1 + RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) - -#define __virt_to_phys(x) ( (x) - PAGE_OFFSET + 0x0c000000 ) -#define __phys_to_virt(x) ( (x) - 0x0c000000 + PAGE_OFFSET ) - -#elif (RAM_IN_BANK_0 == RAM_IN_BANK_1) && \ - (RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) - -/* Two identical banks */ -#define __virt_to_phys(x) \ - ( ((x) < PAGE_OFFSET+RAM_IN_BANK_0) ? \ - ((x) - PAGE_OFFSET + _DRAMBnk0) : \ - ((x) - PAGE_OFFSET - RAM_IN_BANK_0 + _DRAMBnk1) ) -#define __phys_to_virt(x) \ - ( ((x)&0x07ffffff) + \ - (((x)&0x08000000) ? PAGE_OFFSET+RAM_IN_BANK_0 : PAGE_OFFSET) ) -#else - -/* It's more efficient for all other cases to use the function call */ -#undef __virt_to_phys__is_a_macro -#undef __phys_to_virt__is_a_macro -extern unsigned long __virt_to_phys(unsigned long vpage); -extern unsigned long __phys_to_virt(unsigned long ppage); - -#endif - -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - * - * On the SA1100, bus addresses are equivalent to physical addresses. - */ -#define __virt_to_bus__is_a_macro -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt__is_a_macro -#define __bus_to_virt(x) __phys_to_virt(x) - - -#ifdef CONFIG_DISCONTIGMEM -#error "CONFIG_DISCONTIGMEM will not work on S3C2400" -/* - * Because of the wide memory address space between physical RAM banks on the - * SA1100, it's much more convenient to use Linux's NUMA support to implement - * our memory map representation. Assuming all memory nodes have equal access - * characteristics, we then have generic discontiguous memory support. - * - * Of course, all this isn't mandatory for SA1100 implementations with only - * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. - * - * The nodes are matched with the physical memory bank addresses which are - * incidentally the same as virtual addresses. - * - * node 0: 0xc0000000 - 0xc7ffffff - * node 1: 0xc8000000 - 0xcfffffff - * node 2: 0xd0000000 - 0xd7ffffff - * node 3: 0xd8000000 - 0xdfffffff - */ - -#define NR_NODES 4 - -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define KVADDR_TO_NID(addr) \ - (((unsigned long)(addr) - 0xc0000000) >> 27) - -/* - * Given a physical address, convert it to a node id. - */ -#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr)) - -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and returns the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) \ - NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) - -/* - * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory - * and returns the index corresponding to the appropriate page in the - * node's mem_map. - */ -#define LOCAL_MAP_NR(kvaddr) \ - (((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT) - -/* - * Given a kaddr, virt_to_page returns a pointer to the corresponding - * mem_map entry. - */ -#define virt_to_page(kaddr) \ - (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) - -/* - * VALID_PAGE returns a non-zero value if given page pointer is valid. - * This assumes all node's mem_maps are stored within the node they refer to. - */ -#define VALID_PAGE(page) \ -({ unsigned int node = KVADDR_TO_NID(page); \ - ( (node < NR_NODES) && \ - ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \ -}) - -#else - -#define PHYS_TO_NID(addr) (0) - -#endif -#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/include/asm-arm/arch-s3c24x0/s3c2400.h b/include/asm-arm/arch-s3c24x0/s3c2400.h deleted file mode 100644 index 2678be1..0000000 --- a/include/asm-arm/arch-s3c24x0/s3c2400.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c2400.h - * Version : 31.3.2003 - * - * Based on S3C2400X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2400_H__ -#define __S3C2400_H__ - -#define S3C24X0_UART_CHANNELS 2 -#define S3C24X0_SPI_CHANNELS 1 -#define PALETTE (0x14A00400) /* SJS */ - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, -}; - -/*S3C2400 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x14000000 -#define S3C24X0_USB_HOST_BASE 0x14200000 -#define S3C24X0_INTERRUPT_BASE 0x14400000 -#define S3C24X0_DMA_BASE 0x14600000 -#define S3C24X0_CLOCK_POWER_BASE 0x14800000 -#define S3C24X0_LCD_BASE 0x14A00000 -#define S3C24X0_UART_BASE 0x15000000 -#define S3C24X0_TIMER_BASE 0x15100000 -#define S3C24X0_USB_DEVICE_BASE 0x15200140 -#define S3C24X0_WATCHDOG_BASE 0x15300000 -#define S3C24X0_I2C_BASE 0x15400000 -#define S3C24X0_I2S_BASE 0x15508000 -#define S3C24X0_GPIO_BASE 0x15600000 -#define S3C24X0_RTC_BASE 0x15700000 -#define S3C24X0_ADC_BASE 0x15800000 -#define S3C24X0_SPI_BASE 0x15900000 -#define S3C2400_MMC_BASE 0x15A00000 - -/* include common stuff */ -#include - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2400_adc *s3c2400_get_base_adc(void) -{ - return (struct s3c2400_adc *)S3C24X0_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) -{ - return (struct s3c2400_mmc *)S3C2400_MMC_BASE; -} - -#endif /*__S3C2400_H__*/ diff --git a/include/asm-arm/arch-s3c24x0/s3c2410.h b/include/asm-arm/arch-s3c24x0/s3c2410.h deleted file mode 100644 index 0543fe1..0000000 --- a/include/asm-arm/arch-s3c24x0/s3c2410.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c2410.h - * Version : 31.3.2003 - * - * Based on S3C2410X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2410_H__ -#define __S3C2410_H__ - -#define S3C24X0_UART_CHANNELS 3 -#define S3C24X0_SPI_CHANNELS 2 - -/* S3C2410 only supports 512 Byte HW ECC */ -#define S3C2410_ECCSIZE 512 -#define S3C2410_ECCBYTES 3 - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, - S3C24X0_UART2 -}; - -/* S3C2410 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x48000000 -#define S3C24X0_USB_HOST_BASE 0x49000000 -#define S3C24X0_INTERRUPT_BASE 0x4A000000 -#define S3C24X0_DMA_BASE 0x4B000000 -#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 -#define S3C24X0_LCD_BASE 0x4D000000 -#define S3C2410_NAND_BASE 0x4E000000 -#define S3C24X0_UART_BASE 0x50000000 -#define S3C24X0_TIMER_BASE 0x51000000 -#define S3C24X0_USB_DEVICE_BASE 0x52000140 -#define S3C24X0_WATCHDOG_BASE 0x53000000 -#define S3C24X0_I2C_BASE 0x54000000 -#define S3C24X0_I2S_BASE 0x55000000 -#define S3C24X0_GPIO_BASE 0x56000000 -#define S3C24X0_RTC_BASE 0x57000000 -#define S3C2410_ADC_BASE 0x58000000 -#define S3C24X0_SPI_BASE 0x59000000 -#define S3C2410_SDI_BASE 0x5A000000 - - -/* include common stuff */ -#include - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c2410_nand *s3c2410_get_base_nand(void) -{ - return (struct s3c2410_nand *)S3C2410_NAND_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2410_adc *s3c2410_get_base_adc(void) -{ - return (struct s3c2410_adc *)S3C2410_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) -{ - return (struct s3c2410_sdi *)S3C2410_SDI_BASE; -} - -#endif /*__S3C2410_H__*/ diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/include/asm-arm/arch-s3c24x0/s3c24x0.h deleted file mode 100644 index 15f53dd..0000000 --- a/include/asm-arm/arch-s3c24x0/s3c24x0.h +++ /dev/null @@ -1,652 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c24x0.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C24X0 SoC - ************************************************/ - -#ifndef __S3C24X0_H__ -#define __S3C24X0_H__ - -/* Memory controller (see manual chapter 5) */ -struct s3c24x0_memctl { - u32 BWSCON; - u32 BANKCON[8]; - u32 REFRESH; - u32 BANKSIZE; - u32 MRSRB6; - u32 MRSRB7; -}; - - -/* USB HOST (see manual chapter 12) */ -struct s3c24x0_usb_host { - u32 HcRevision; - u32 HcControl; - u32 HcCommonStatus; - u32 HcInterruptStatus; - u32 HcInterruptEnable; - u32 HcInterruptDisable; - u32 HcHCCA; - u32 HcPeriodCuttendED; - u32 HcControlHeadED; - u32 HcControlCurrentED; - u32 HcBulkHeadED; - u32 HcBuldCurrentED; - u32 HcDoneHead; - u32 HcRmInterval; - u32 HcFmRemaining; - u32 HcFmNumber; - u32 HcPeriodicStart; - u32 HcLSThreshold; - u32 HcRhDescriptorA; - u32 HcRhDescriptorB; - u32 HcRhStatus; - u32 HcRhPortStatus1; - u32 HcRhPortStatus2; -}; - - -/* INTERRUPT (see manual chapter 14) */ -struct s3c24x0_interrupt { - u32 SRCPND; - u32 INTMOD; - u32 INTMSK; - u32 PRIORITY; - u32 INTPND; - u32 INTOFFSET; -#ifdef CONFIG_S3C2410 - u32 SUBSRCPND; - u32 INTSUBMSK; -#endif -}; - - -/* DMAS (see manual chapter 8) */ -struct s3c24x0_dma { - u32 DISRC; -#ifdef CONFIG_S3C2410 - u32 DISRCC; -#endif - u32 DIDST; -#ifdef CONFIG_S3C2410 - u32 DIDSTC; -#endif - u32 DCON; - u32 DSTAT; - u32 DCSRC; - u32 DCDST; - u32 DMASKTRIG; -#ifdef CONFIG_S3C2400 - u32 res[1]; -#endif -#ifdef CONFIG_S3C2410 - u32 res[7]; -#endif -}; - -struct s3c24x0_dmas { - struct s3c24x0_dma dma[4]; -}; - - -/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ -/* (see S3C2410 manual chapter 7) */ -struct s3c24x0_clock_power { - u32 LOCKTIME; - u32 MPLLCON; - u32 UPLLCON; - u32 CLKCON; - u32 CLKSLOW; - u32 CLKDIVN; -}; - - -/* LCD CONTROLLER (see manual chapter 15) */ -struct s3c24x0_lcd { - u32 LCDCON1; - u32 LCDCON2; - u32 LCDCON3; - u32 LCDCON4; - u32 LCDCON5; - u32 LCDSADDR1; - u32 LCDSADDR2; - u32 LCDSADDR3; - u32 REDLUT; - u32 GREENLUT; - u32 BLUELUT; - u32 res[8]; - u32 DITHMODE; - u32 TPAL; -#ifdef CONFIG_S3C2410 - u32 LCDINTPND; - u32 LCDSRCPND; - u32 LCDINTMSK; - u32 LPCSEL; -#endif -}; - - -/* NAND FLASH (see S3C2410 manual chapter 6) */ -struct s3c2410_nand { - u32 NFCONF; - u32 NFCMD; - u32 NFADDR; - u32 NFDATA; - u32 NFSTAT; - u32 NFECC; -}; - - -/* UART (see manual chapter 11) */ -struct s3c24x0_uart { - u32 ULCON; - u32 UCON; - u32 UFCON; - u32 UMCON; - u32 UTRSTAT; - u32 UERSTAT; - u32 UFSTAT; - u32 UMSTAT; -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 UTXH; - u8 res2[3]; - u8 URXH; -#else /* Little Endian */ - u8 UTXH; - u8 res1[3]; - u8 URXH; - u8 res2[3]; -#endif - u32 UBRDIV; -}; - - -/* PWM TIMER (see manual chapter 10) */ -struct s3c24x0_timer { - u32 TCNTB; - u32 TCMPB; - u32 TCNTO; -}; - -struct s3c24x0_timers { - u32 TCFG0; - u32 TCFG1; - u32 TCON; - struct s3c24x0_timer ch[4]; - u32 TCNTB4; - u32 TCNTO4; -}; - - -/* USB DEVICE (see manual chapter 13) */ -struct s3c24x0_usb_dev_fifos { -#ifdef __BIG_ENDIAN - u8 res[3]; - u8 EP_FIFO_REG; -#else /* little endian */ - u8 EP_FIFO_REG; - u8 res[3]; -#endif -}; - -struct s3c24x0_usb_dev_dmas { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 EP_DMA_CON; - u8 res2[3]; - u8 EP_DMA_UNIT; - u8 res3[3]; - u8 EP_DMA_FIFO; - u8 res4[3]; - u8 EP_DMA_TTC_L; - u8 res5[3]; - u8 EP_DMA_TTC_M; - u8 res6[3]; - u8 EP_DMA_TTC_H; -#else /* little endian */ - u8 EP_DMA_CON; - u8 res1[3]; - u8 EP_DMA_UNIT; - u8 res2[3]; - u8 EP_DMA_FIFO; - u8 res3[3]; - u8 EP_DMA_TTC_L; - u8 res4[3]; - u8 EP_DMA_TTC_M; - u8 res5[3]; - u8 EP_DMA_TTC_H; - u8 res6[3]; -#endif -}; - -struct s3c24x0_usb_device { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 FUNC_ADDR_REG; - u8 res2[3]; - u8 PWR_REG; - u8 res3[3]; - u8 EP_INT_REG; - u8 res4[15]; - u8 USB_INT_REG; - u8 res5[3]; - u8 EP_INT_EN_REG; - u8 res6[15]; - u8 USB_INT_EN_REG; - u8 res7[3]; - u8 FRAME_NUM1_REG; - u8 res8[3]; - u8 FRAME_NUM2_REG; - u8 res9[3]; - u8 INDEX_REG; - u8 res10[7]; - u8 MAXP_REG; - u8 res11[3]; - u8 EP0_CSR_IN_CSR1_REG; - u8 res12[3]; - u8 IN_CSR2_REG; - u8 res13[7]; - u8 OUT_CSR1_REG; - u8 res14[3]; - u8 OUT_CSR2_REG; - u8 res15[3]; - u8 OUT_FIFO_CNT1_REG; - u8 res16[3]; - u8 OUT_FIFO_CNT2_REG; -#else /* little endian */ - u8 FUNC_ADDR_REG; - u8 res1[3]; - u8 PWR_REG; - u8 res2[3]; - u8 EP_INT_REG; - u8 res3[15]; - u8 USB_INT_REG; - u8 res4[3]; - u8 EP_INT_EN_REG; - u8 res5[15]; - u8 USB_INT_EN_REG; - u8 res6[3]; - u8 FRAME_NUM1_REG; - u8 res7[3]; - u8 FRAME_NUM2_REG; - u8 res8[3]; - u8 INDEX_REG; - u8 res9[7]; - u8 MAXP_REG; - u8 res10[7]; - u8 EP0_CSR_IN_CSR1_REG; - u8 res11[3]; - u8 IN_CSR2_REG; - u8 res12[3]; - u8 OUT_CSR1_REG; - u8 res13[7]; - u8 OUT_CSR2_REG; - u8 res14[3]; - u8 OUT_FIFO_CNT1_REG; - u8 res15[3]; - u8 OUT_FIFO_CNT2_REG; - u8 res16[3]; -#endif /* __BIG_ENDIAN */ - struct s3c24x0_usb_dev_fifos fifo[5]; - struct s3c24x0_usb_dev_dmas dma[5]; -}; - - -/* WATCH DOG TIMER (see manual chapter 18) */ -struct s3c24x0_watchdog { - u32 WTCON; - u32 WTDAT; - u32 WTCNT; -}; - - -/* IIC (see manual chapter 20) */ -struct s3c24x0_i2c { - u32 IICCON; - u32 IICSTAT; - u32 IICADD; - u32 IICDS; -}; - - -/* IIS (see manual chapter 21) */ -struct s3c24x0_i2s { -#ifdef __BIG_ENDIAN - u16 res1; - u16 IISCON; - u16 res2; - u16 IISMOD; - u16 res3; - u16 IISPSR; - u16 res4; - u16 IISFCON; - u16 res5; - u16 IISFIFO; -#else /* little endian */ - u16 IISCON; - u16 res1; - u16 IISMOD; - u16 res2; - u16 IISPSR; - u16 res3; - u16 IISFCON; - u16 res4; - u16 IISFIFO; - u16 res5; -#endif -}; - - -/* I/O PORT (see manual chapter 9) */ -struct s3c24x0_gpio { -#ifdef CONFIG_S3C2400 - u32 PACON; - u32 PADAT; - - u32 PBCON; - u32 PBDAT; - u32 PBUP; - - u32 PCCON; - u32 PCDAT; - u32 PCUP; - - u32 PDCON; - u32 PDDAT; - u32 PDUP; - - u32 PECON; - u32 PEDAT; - u32 PEUP; - - u32 PFCON; - u32 PFDAT; - u32 PFUP; - - u32 PGCON; - u32 PGDAT; - u32 PGUP; - - u32 OPENCR; - - u32 MISCCR; - u32 EXTINT; -#endif -#ifdef CONFIG_S3C2410 - u32 GPACON; - u32 GPADAT; - u32 res1[2]; - u32 GPBCON; - u32 GPBDAT; - u32 GPBUP; - u32 res2; - u32 GPCCON; - u32 GPCDAT; - u32 GPCUP; - u32 res3; - u32 GPDCON; - u32 GPDDAT; - u32 GPDUP; - u32 res4; - u32 GPECON; - u32 GPEDAT; - u32 GPEUP; - u32 res5; - u32 GPFCON; - u32 GPFDAT; - u32 GPFUP; - u32 res6; - u32 GPGCON; - u32 GPGDAT; - u32 GPGUP; - u32 res7; - u32 GPHCON; - u32 GPHDAT; - u32 GPHUP; - u32 res8; - - u32 MISCCR; - u32 DCLKCON; - u32 EXTINT0; - u32 EXTINT1; - u32 EXTINT2; - u32 EINTFLT0; - u32 EINTFLT1; - u32 EINTFLT2; - u32 EINTFLT3; - u32 EINTMASK; - u32 EINTPEND; - u32 GSTATUS0; - u32 GSTATUS1; - u32 GSTATUS2; - u32 GSTATUS3; - u32 GSTATUS4; -#endif -}; - - -/* RTC (see manual chapter 17) */ -struct s3c24x0_rtc { -#ifdef __BIG_ENDIAN - u8 res1[67]; - u8 RTCCON; - u8 res2[3]; - u8 TICNT; - u8 res3[11]; - u8 RTCALM; - u8 res4[3]; - u8 ALMSEC; - u8 res5[3]; - u8 ALMMIN; - u8 res6[3]; - u8 ALMHOUR; - u8 res7[3]; - u8 ALMDATE; - u8 res8[3]; - u8 ALMMON; - u8 res9[3]; - u8 ALMYEAR; - u8 res10[3]; - u8 RTCRST; - u8 res11[3]; - u8 BCDSEC; - u8 res12[3]; - u8 BCDMIN; - u8 res13[3]; - u8 BCDHOUR; - u8 res14[3]; - u8 BCDDATE; - u8 res15[3]; - u8 BCDDAY; - u8 res16[3]; - u8 BCDMON; - u8 res17[3]; - u8 BCDYEAR; -#else /* little endian */ - u8 res0[64]; - u8 RTCCON; - u8 res1[3]; - u8 TICNT; - u8 res2[11]; - u8 RTCALM; - u8 res3[3]; - u8 ALMSEC; - u8 res4[3]; - u8 ALMMIN; - u8 res5[3]; - u8 ALMHOUR; - u8 res6[3]; - u8 ALMDATE; - u8 res7[3]; - u8 ALMMON; - u8 res8[3]; - u8 ALMYEAR; - u8 res9[3]; - u8 RTCRST; - u8 res10[3]; - u8 BCDSEC; - u8 res11[3]; - u8 BCDMIN; - u8 res12[3]; - u8 BCDHOUR; - u8 res13[3]; - u8 BCDDATE; - u8 res14[3]; - u8 BCDDAY; - u8 res15[3]; - u8 BCDMON; - u8 res16[3]; - u8 BCDYEAR; - u8 res17[3]; -#endif -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2400_adc { - u32 ADCCON; - u32 ADCDAT; -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2410_adc { - u32 ADCCON; - u32 ADCTSC; - u32 ADCDLY; - u32 ADCDAT0; - u32 ADCDAT1; -}; - - -/* SPI (see manual chapter 22) */ -struct s3c24x0_spi_channel { - u8 SPCON; - u8 res1[3]; - u8 SPSTA; - u8 res2[3]; - u8 SPPIN; - u8 res3[3]; - u8 SPPRE; - u8 res4[3]; - u8 SPTDAT; - u8 res5[3]; - u8 SPRDAT; - u8 res6[3]; - u8 res7[16]; -}; - -struct s3c24x0_spi { - struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; -}; - - -/* MMC INTERFACE (see S3C2400 manual chapter 19) */ -struct s3c2400_mmc { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 MMCON; - u8 res2[3]; - u8 MMCRR; - u8 res3[3]; - u8 MMFCON; - u8 res4[3]; - u8 MMSTA; - u16 res5; - u16 MMFSTA; - u8 res6[3]; - u8 MMPRE; - u16 res7; - u16 MMLEN; - u8 res8[3]; - u8 MMCR7; - u32 MMRSP[4]; - u8 res9[3]; - u8 MMCMD0; - u32 MMCMD1; - u16 res10; - u16 MMCR16; - u8 res11[3]; - u8 MMDAT; -#else - u8 MMCON; - u8 res1[3]; - u8 MMCRR; - u8 res2[3]; - u8 MMFCON; - u8 res3[3]; - u8 MMSTA; - u8 res4[3]; - u16 MMFSTA; - u16 res5; - u8 MMPRE; - u8 res6[3]; - u16 MMLEN; - u16 res7; - u8 MMCR7; - u8 res8[3]; - u32 MMRSP[4]; - u8 MMCMD0; - u8 res9[3]; - u32 MMCMD1; - u16 MMCR16; - u16 res10; - u8 MMDAT; - u8 res11[3]; -#endif -}; - - -/* SD INTERFACE (see S3C2410 manual chapter 19) */ -struct s3c2410_sdi { - u32 SDICON; - u32 SDIPRE; - u32 SDICARG; - u32 SDICCON; - u32 SDICSTA; - u32 SDIRSP0; - u32 SDIRSP1; - u32 SDIRSP2; - u32 SDIRSP3; - u32 SDIDTIMER; - u32 SDIBSIZE; - u32 SDIDCON; - u32 SDIDCNT; - u32 SDIDSTA; - u32 SDIFSTA; -#ifdef __BIG_ENDIAN - u8 res[3]; - u8 SDIDAT; -#else - u8 SDIDAT; - u8 res[3]; -#endif - u32 SDIIMSK; -}; - -#endif /*__S3C24X0_H__*/ diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h b/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h deleted file mode 100644 index c37d4a1..0000000 --- a/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2009 - * Kevin Morfitt, Fearnside Systems Ltd, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifdef CONFIG_S3C2400 - #include -#elif defined CONFIG_S3C2410 - #include -#else - #error Please define the s3c24x0 cpu type -#endif diff --git a/include/asm-arm/arch-s3c44b0/hardware.h b/include/asm-arm/arch-s3c44b0/hardware.h deleted file mode 100644 index 146e265..0000000 --- a/include/asm-arm/arch-s3c44b0/hardware.h +++ /dev/null @@ -1,281 +0,0 @@ -/********************************************************/ -/* */ -/* Samsung S3C44B0 */ -/* tpu */ -/* */ -/********************************************************/ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#define REGBASE 0x01c00000 -#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr)) -#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr)) -#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr)) - - -/*****************************/ -/* CPU Wrapper Registers */ -/*****************************/ - -#define SYSCFG REGL(0x000000) -#define NCACHBE0 REGL(0x000004) -#define NCACHBE1 REGL(0x000008) -#define SBUSCON REGL(0x040000) - -/************************************/ -/* Memory Controller Registers */ -/************************************/ - -#define BWSCON REGL(0x080000) -#define BANKCON0 REGL(0x080004) -#define BANKCON1 REGL(0x080008) -#define BANKCON2 REGL(0x08000c) -#define BANKCON3 REGL(0x080010) -#define BANKCON4 REGL(0x080014) -#define BANKCON5 REGL(0x080018) -#define BANKCON6 REGL(0x08001c) -#define BANKCON7 REGL(0x080020) -#define REFRESH REGL(0x080024) -#define BANKSIZE REGL(0x080028) -#define MRSRB6 REGL(0x08002c) -#define MRSRB7 REGL(0x080030) - -/*********************/ -/* UART Registers */ -/*********************/ - -#define ULCON0 REGL(0x100000) -#define ULCON1 REGL(0x104000) -#define UCON0 REGL(0x100004) -#define UCON1 REGL(0x104004) -#define UFCON0 REGL(0x100008) -#define UFCON1 REGL(0x104008) -#define UMCON0 REGL(0x10000c) -#define UMCON1 REGL(0x10400c) -#define UTRSTAT0 REGL(0x100010) -#define UTRSTAT1 REGL(0x104010) -#define UERSTAT0 REGL(0x100014) -#define UERSTAT1 REGL(0x104014) -#define UFSTAT0 REGL(0x100018) -#define UFSTAT1 REGL(0x104018) -#define UMSTAT0 REGL(0x10001c) -#define UMSTAT1 REGL(0x10401c) -#define UTXH0 REGB(0x100020) -#define UTXH1 REGB(0x104020) -#define URXH0 REGB(0x100024) -#define URXH1 REGB(0x104024) -#define UBRDIV0 REGL(0x100028) -#define UBRDIV1 REGL(0x104028) - -/*******************/ -/* SIO Registers */ -/*******************/ - -#define SIOCON REGL(0x114000) -#define SIODAT REGL(0x114004) -#define SBRDR REGL(0x114008) -#define ITVCNT REGL(0x11400c) -#define DCNTZ REGL(0x114010) - -/********************/ -/* IIS Registers */ -/********************/ - -#define IISCON REGL(0x118000) -#define IISMOD REGL(0x118004) -#define IISPSR REGL(0x118008) -#define IISFIFCON REGL(0x11800c) -#define IISFIF REGW(0x118010) - -/**************************/ -/* I/O Ports Registers */ -/**************************/ - -#define PCONA REGL(0x120000) -#define PDATA REGL(0x120004) -#define PCONB REGL(0x120008) -#define PDATB REGL(0x12000c) -#define PCONC REGL(0x120010) -#define PDATC REGL(0x120014) -#define PUPC REGL(0x120018) -#define PCOND REGL(0x12001c) -#define PDATD REGL(0x120020) -#define PUPD REGL(0x120024) -#define PCONE REGL(0x120028) -#define PDATE REGL(0x12002c) -#define PUPE REGL(0x120030) -#define PCONF REGL(0x120034) -#define PDATF REGL(0x120038) -#define PUPF REGL(0x12003c) -#define PCONG REGL(0x120040) -#define PDATG REGL(0x120044) -#define PUPG REGL(0x120048) -#define SPUCR REGL(0x12004c) -#define EXTINT REGL(0x120050) -#define EXTINTPND REGL(0x120054) - -/*********************************/ -/* WatchDog Timers Registers */ -/*********************************/ - -#define WTCON REGL(0x130000) -#define WTDAT REGL(0x130004) -#define WTCNT REGL(0x130008) - -/*********************************/ -/* A/D Converter Registers */ -/*********************************/ - -#define ADCCON REGL(0x140000) -#define ADCPSR REGL(0x140004) -#define ADCDAT REGL(0x140008) - -/***************************/ -/* PWM Timer Registers */ -/***************************/ - -#define TCFG0 REGL(0x150000) -#define TCFG1 REGL(0x150004) -#define TCON REGL(0x150008) -#define TCNTB0 REGL(0x15000c) -#define TCMPB0 REGL(0x150010) -#define TCNTO0 REGL(0x150014) -#define TCNTB1 REGL(0x150018) -#define TCMPB1 REGL(0x15001c) -#define TCNTO1 REGL(0x150020) -#define TCNTB2 REGL(0x150024) -#define TCMPB2 REGL(0x150028) -#define TCNTO2 REGL(0x15002c) -#define TCNTB3 REGL(0x150030) -#define TCMPB3 REGL(0x150034) -#define TCNTO3 REGL(0x150038) -#define TCNTB4 REGL(0x15003c) -#define TCMPB4 REGL(0x150040) -#define TCNTO4 REGL(0x150044) -#define TCNTB5 REGL(0x150048) -#define TCNTO5 REGL(0x15004c) - -/*********************/ -/* IIC Registers */ -/*********************/ - -#define IICCON REGL(0x160000) -#define IICSTAT REGL(0x160004) -#define IICADD REGL(0x160008) -#define IICDS REGL(0x16000c) - -/*********************/ -/* RTC Registers */ -/*********************/ - -#define RTCCON REGB(0x170040) -#define RTCALM REGB(0x170050) -#define ALMSEC REGB(0x170054) -#define ALMMIN REGB(0x170058) -#define ALMHOUR REGB(0x17005c) -#define ALMDAY REGB(0x170060) -#define ALMMON REGB(0x170064) -#define ALMYEAR REGB(0x170068) -#define RTCRST REGB(0x17006c) -#define BCDSEC REGB(0x170070) -#define BCDMIN REGB(0x170074) -#define BCDHOUR REGB(0x170078) -#define BCDDAY REGB(0x17007c) -#define BCDDATE REGB(0x170080) -#define BCDMON REGB(0x170084) -#define BCDYEAR REGB(0x170088) -#define TICINT REGB(0x17008c) - -/*********************************/ -/* Clock & Power Registers */ -/*********************************/ - -#define PLLCON REGL(0x180000) -#define CLKCON REGL(0x180004) -#define CLKSLOW REGL(0x180008) -#define LOCKTIME REGL(0x18000c) - -/**************************************/ -/* Interrupt Controller Registers */ -/**************************************/ - -#define INTCON REGL(0x200000) -#define INTPND REGL(0x200004) -#define INTMOD REGL(0x200008) -#define INTMSK REGL(0x20000c) -#define I_PSLV REGL(0x200010) -#define I_PMST REGL(0x200014) -#define I_CSLV REGL(0x200018) -#define I_CMST REGL(0x20001c) -#define I_ISPR REGL(0x200020) -#define I_ISPC REGL(0x200024) -#define F_ISPR REGL(0x200038) -#define F_ISPC REGL(0x20003c) - -/********************************/ -/* LCD Controller Registers */ -/********************************/ - -#define LCDCON1 REGL(0x300000) -#define LCDCON2 REGL(0x300004) -#define LCDSADDR1 REGL(0x300008) -#define LCDSADDR2 REGL(0x30000c) -#define LCDSADDR3 REGL(0x300010) -#define REDLUT REGL(0x300014) -#define GREENLUT REGL(0x300018) -#define BLUELUT REGL(0x30001c) -#define DP1_2 REGL(0x300020) -#define DP4_7 REGL(0x300024) -#define DP3_5 REGL(0x300028) -#define DP2_3 REGL(0x30002c) -#define DP5_7 REGL(0x300030) -#define DP3_4 REGL(0x300034) -#define DP4_5 REGL(0x300038) -#define DP6_7 REGL(0x30003c) -#define LCDCON3 REGL(0x300040) -#define DITHMODE REGL(0x300044) - -/*********************/ -/* DMA Registers */ -/*********************/ - -#define ZDCON0 REGL(0x280000) -#define ZDISRC0 REGL(0x280004) -#define ZDIDES0 REGL(0x280008) -#define ZDICNT0 REGL(0x28000c) -#define ZDCSRC0 REGL(0x280010) -#define ZDCDES0 REGL(0x280014) -#define ZDCCNT0 REGL(0x280018) - -#define ZDCON1 REGL(0x280020) -#define ZDISRC1 REGL(0x280024) -#define ZDIDES1 REGL(0x280028) -#define ZDICNT1 REGL(0x28002c) -#define ZDCSRC1 REGL(0x280030) -#define ZDCDES1 REGL(0x280034) -#define ZDCCNT1 REGL(0x280038) - -#define BDCON0 REGL(0x380000) -#define BDISRC0 REGL(0x380004) -#define BDIDES0 REGL(0x380008) -#define BDICNT0 REGL(0x38000c) -#define BDCSRC0 REGL(0x380010) -#define BDCDES0 REGL(0x380014) -#define BDCCNT0 REGL(0x380018) - -#define BDCON1 REGL(0x380020) -#define BDISRC1 REGL(0x380024) -#define BDIDES1 REGL(0x380028) -#define BDICNT1 REGL(0x38002c) -#define BDCSRC1 REGL(0x380030) -#define BDCDES1 REGL(0x380034) -#define BDCCNT1 REGL(0x380038) - - -#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n)) -#define INT_ENABLE(n) INTMSK &= ~(1<<(n)) -#define INT_DISABLE(n) INTMSK |= (1<<(n)) - -#define HARD_RESET_NOW() - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-s3c4510b/hardware.h b/include/asm-arm/arch-s3c4510b/hardware.h deleted file mode 100644 index 6b8c8ed..0000000 --- a/include/asm-arm/arch-s3c4510b/hardware.h +++ /dev/null @@ -1,272 +0,0 @@ -#ifndef __HW_S3C4510_H -#define __HW_S3C4510_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Description: Samsung S3C4510B register layout - */ - -/*------------------------------------------------------------------------ - * ASIC Address Definition - *----------------------------------------------------------------------*/ - -/* L1 8KB on chip SRAM base address */ -#define SRAM_BASE (0x03fe0000) - -/* Special Register Start Address After System Reset */ -#define REG_BASE (0x03ff0000) -#define SPSTR (REG_BASE) - -/* *********************** */ -/* System Manager Register */ -/* *********************** */ -#define REG_SYSCFG (REG_BASE+0x0000) - -#define REG_CLKCON (REG_BASE+0x3000) -#define REG_EXTACON0 (REG_BASE+0x3008) -#define REG_EXTACON1 (REG_BASE+0x300c) -#define REG_EXTDBWTH (REG_BASE+0x3010) -#define REG_ROMCON0 (REG_BASE+0x3014) -#define REG_ROMCON1 (REG_BASE+0x3018) -#define REG_ROMCON2 (REG_BASE+0x301c) -#define REG_ROMCON3 (REG_BASE+0x3020) -#define REG_ROMCON4 (REG_BASE+0x3024) -#define REG_ROMCON5 (REG_BASE+0x3028) -#define REG_DRAMCON0 (REG_BASE+0x302c) -#define REG_DRAMCON1 (REG_BASE+0x3030) -#define REG_DRAMCON2 (REG_BASE+0x3034) -#define REG_DRAMCON3 (REG_BASE+0x3038) -#define REG_REFEXTCON (REG_BASE+0x303c) - -/* *********************** */ -/* Ethernet BDMA Register */ -/* *********************** */ -#define REG_BDMATXCON (REG_BASE+0x9000) -#define REG_BDMARXCON (REG_BASE+0x9004) -#define REG_BDMATXPTR (REG_BASE+0x9008) -#define REG_BDMARXPTR (REG_BASE+0x900c) -#define REG_BDMARXLSZ (REG_BASE+0x9010) -#define REG_BDMASTAT (REG_BASE+0x9014) - -/* Content Address Memory */ -#define REG_CAM_BASE (REG_BASE+0x9100) - -#define REG_BDMATXBUF (REG_BASE+0x9200) -#define REG_BDMARXBUF (REG_BASE+0x9800) - -/* *********************** */ -/* Ethernet MAC Register */ -/* *********************** */ -#define REG_MACCON (REG_BASE+0xa000) -#define REG_CAMCON (REG_BASE+0xa004) -#define REG_MACTXCON (REG_BASE+0xa008) -#define REG_MACTXSTAT (REG_BASE+0xa00c) -#define REG_MACRXCON (REG_BASE+0xa010) -#define REG_MACRXSTAT (REG_BASE+0xa014) -#define REG_STADATA (REG_BASE+0xa018) -#define REG_STACON (REG_BASE+0xa01c) -#define REG_CAMEN (REG_BASE+0xa028) -#define REG_EMISSCNT (REG_BASE+0xa03c) -#define REG_EPZCNT (REG_BASE+0xa040) -#define REG_ERMPZCNT (REG_BASE+0xa044) -#define REG_ETXSTAT (REG_BASE+0x9040) -#define REG_MACRXDESTR (REG_BASE+0xa064) -#define REG_MACRXSTATEM (REG_BASE+0xa090) -#define REG_MACRXFIFO (REG_BASE+0xa200) - -/********************/ -/* I2C Bus Register */ -/********************/ -#define REG_I2C_CON (REG_BASE+0xf000) -#define REG_I2C_BUF (REG_BASE+0xf004) -#define REG_I2C_PS (REG_BASE+0xf008) -#define REG_I2C_COUNT (REG_BASE+0xf00c) - -/********************/ -/* GDMA 0 */ -/********************/ -#define REG_GDMACON0 (REG_BASE+0xb000) -#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020) -#define REG_GDMASRC0 (REG_BASE+0xb004) -#define REG_GDMADST0 (REG_BASE+0xb008) -#define REG_GDMACNT0 (REG_BASE+0xb00c) - -/********************/ -/* GDMA 1 */ -/********************/ -#define REG_GDMACON1 (REG_BASE+0xc000) -#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020) -#define REG_GDMASRC1 (REG_BASE+0xc004) -#define REG_GDMADST1 (REG_BASE+0xc008) -#define REG_GDMACNT1 (REG_BASE+0xc00c) - -/********************/ -/* UART 0 */ -/********************/ -#define UART0_BASE (REG_BASE+0xd000) -#define REG_UART0_LCON (REG_BASE+0xd000) -#define REG_UART0_CTRL (REG_BASE+0xd004) -#define REG_UART0_STAT (REG_BASE+0xd008) -#define REG_UART0_TXB (REG_BASE+0xd00c) -#define REG_UART0_RXB (REG_BASE+0xd010) -#define REG_UART0_BAUD_DIV (REG_BASE+0xd014) -#define REG_UART0_BAUD_CNT (REG_BASE+0xd018) -#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C) - -/********************/ -/* UART 1 */ -/********************/ -#define UART1_BASE (REG_BASE+0xe000) -#define REG_UART1_LCON (REG_BASE+0xe000) -#define REG_UART1_CTRL (REG_BASE+0xe004) -#define REG_UART1_STAT (REG_BASE+0xe008) -#define REG_UART1_TXB (REG_BASE+0xe00c) -#define REG_UART1_RXB (REG_BASE+0xe010) -#define REG_UART1_BAUD_DIV (REG_BASE+0xe014) -#define REG_UART1_BAUD_CNT (REG_BASE+0xe018) -#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C) - -/********************/ -/* Timer Register */ -/********************/ -#define REG_TMOD (REG_BASE+0x6000) -#define REG_TDATA0 (REG_BASE+0x6004) -#define REG_TDATA1 (REG_BASE+0x6008) -#define REG_TCNT0 (REG_BASE+0x600c) -#define REG_TCNT1 (REG_BASE+0x6010) - -/**********************/ -/* I/O Port Interface */ -/**********************/ -#define REG_IOPMODE (REG_BASE+0x5000) -#define REG_IOPCON (REG_BASE+0x5004) -#define REG_IOPDATA (REG_BASE+0x5008) - -/*********************************/ -/* Interrupt Controller Register */ -/*********************************/ -#define REG_INTMODE (REG_BASE+0x4000) -#define REG_INTPEND (REG_BASE+0x4004) -#define REG_INTMASK (REG_BASE+0x4008) - -#define REG_INTPRI0 (REG_BASE+0x400c) -#define REG_INTPRI1 (REG_BASE+0x4010) -#define REG_INTPRI2 (REG_BASE+0x4014) -#define REG_INTPRI3 (REG_BASE+0x4018) -#define REG_INTPRI4 (REG_BASE+0x401c) -#define REG_INTPRI5 (REG_BASE+0x4020) -#define REG_INTOFFSET (REG_BASE+0x4024) -#define REG_INTPNDPRI (REG_BASE+0x4028) -#define REG_INTPNDTST (REG_BASE+0x402C) - -/*********************************/ -/* CACHE CONTROL MASKS */ -/*********************************/ -#define CACHE_STALL (0x00000001) -#define CACHE_ENABLE (0x00000002) -#define CACHE_WRITE_BUFF (0x00000004) -#define CACHE_MODE (0x00000030) -#define CACHE_MODE_00 (0x00000000) -#define CACHE_MODE_01 (0x00000010) -#define CACHE_MODE_10 (0x00000020) - -/*********************************/ -/* CACHE RAM BASE ADDRESSES */ -/*********************************/ -#define CACHE_SET0_RAM (0x10000000) -#define CACHE_SET1_RAM (0x10800000) -#define CACHE_TAG_RAM (0x11000000) - -/*********************************/ -/* CACHE_DISABLE MASK */ -/*********************************/ -#define CACHE_DISABLE_MASK (0x04000000) - -#define GET_REG(reg) (*((volatile u32 *)(reg))) -#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val))) -#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask)) -#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask)) -#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val))) -#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF))) -#define GET__U8(reg) (*((volatile u8 *)(reg))) - -#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF)) -#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF) -#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); } -#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); } - -/***********************************/ -/* CLOCK CONSTANTS -- 50 MHz Clock */ -/***********************************/ - -#define CLK_FREQ_MHZ (50) -#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */ -#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */ - -/*********************************************************/ -/* TIMER MODE REGISTER */ -/*********************************************************/ -#define TM0_RUN 0x01 /* Timer 0 enable */ -#define TM0_TOGGLE 0x02 /* 0, interval mode */ -#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */ -#define TM1_RUN 0x08 /* Timer 1 enable */ -#define TM1_TOGGLE 0x10 /* 0, interval mode */ -#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */ - - -/*********************************/ -/* INTERRUPT SOURCES */ -/*********************************/ -#define INT_EXTINT0 0 -#define INT_EXTINT1 1 -#define INT_EXTINT2 2 -#define INT_EXTINT3 3 -#define INT_UARTTX0 4 -#define INT_UARTRX0 5 -#define INT_UARTTX1 6 -#define INT_UARTRX1 7 -#define INT_GDMA0 8 -#define INT_GDMA1 9 -#define INT_TIMER0 10 -#define INT_TIMER1 11 -#define INT_HDLCTXA 12 -#define INT_HDLCRXA 13 -#define INT_HDLCTXB 14 -#define INT_HDLCRXB 15 -#define INT_BDMATX 16 -#define INT_BDMARX 17 -#define INT_MACTX 18 -#define INT_MACRX 19 -#define INT_IIC 20 -#define INT_GLOBAL 21 -#define N_IRQS (21) - -#ifndef __ASSEMBLER__ -struct _irq_handler { - void *m_data; - void (*m_func)( void *data); -}; - -#endif - -#endif /* __S3C4510_h */ diff --git a/include/asm-arm/arch-s3c64xx/hardware.h b/include/asm-arm/arch-s3c64xx/hardware.h deleted file mode 100644 index 84d24c9..0000000 --- a/include/asm-arm/arch-s3c64xx/hardware.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ARCH_HARDWARE_H_ -#define _ARCH_HARDWARE_H_ - -#include - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) - -#define __REG(x) (*(vu_long *)(x)) -#define __REGl(x) (*(vu_long *)(x)) -#define __REGw(x) (*(vu_short *)(x)) -#define __REGb(x) (*(vu_char *)(x)) -#define __REG2(x, y) (*(vu_long *)((x) + (y))) -#else -#define UData(Data) (Data) - -#define __REG(x) (x) -#define __REGl(x) (x) -#define __REGw(x) (x) -#define __REGb(x) (x) -#define __REG2(x, y) ((x) + (y)) -#endif - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - -#define FClrBit(Data, Bit) (Data = (Data & ~(Bit))) -#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field))) - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - -#endif /* _ARCH_HARDWARE_H_ */ diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h b/include/asm-arm/arch-s3c64xx/s3c6400.h deleted file mode 100644 index 10b3324..0000000 --- a/include/asm-arm/arch-s3c64xx/s3c6400.h +++ /dev/null @@ -1,895 +0,0 @@ -/* - * (C) Copyright 2007 - * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. - * - only support for S3C6400 - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c6400.h - * - * Based on S3C6400 User's manual Rev 0.0 - ************************************************/ - -#ifndef __S3C6400_H__ -#define __S3C6400_H__ - -#define S3C64XX_UART_CHANNELS 3 -#define S3C64XX_SPI_CHANNELS 2 - -#include - -#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 - -/* Clock & Power Controller for mDirac3*/ -#define APLL_LOCK_OFFSET 0x00 -#define MPLL_LOCK_OFFSET 0x04 -#define EPLL_LOCK_OFFSET 0x08 -#define APLL_CON_OFFSET 0x0C -#define MPLL_CON_OFFSET 0x10 -#define EPLL_CON0_OFFSET 0x14 -#define EPLL_CON1_OFFSET 0x18 -#define CLK_SRC_OFFSET 0x1C -#define CLK_DIV0_OFFSET 0x20 -#define CLK_DIV1_OFFSET 0x24 -#define CLK_DIV2_OFFSET 0x28 -#define CLK_OUT_OFFSET 0x2C -#define HCLK_GATE_OFFSET 0x30 -#define PCLK_GATE_OFFSET 0x34 -#define SCLK_GATE_OFFSET 0x38 -#define AHB_CON0_OFFSET 0x100 -#define AHB_CON1_OFFSET 0x104 -#define AHB_CON2_OFFSET 0x108 -#define SELECT_DMA_OFFSET 0x110 -#define SW_RST_OFFSET 0x114 -#define SYS_ID_OFFSET 0x118 -#define MEM_SYS_CFG_OFFSET 0x120 -#define QOS_OVERRIDE0_OFFSET 0x124 -#define QOS_OVERRIDE1_OFFSET 0x128 -#define MEM_CFG_STAT_OFFSET 0x12C -#define PWR_CFG_OFFSET 0x804 -#define EINT_MASK_OFFSET 0x808 -#define NOR_CFG_OFFSET 0x810 -#define STOP_CFG_OFFSET 0x814 -#define SLEEP_CFG_OFFSET 0x818 -#define OSC_FREQ_OFFSET 0x820 -#define OSC_STABLE_OFFSET 0x824 -#define PWR_STABLE_OFFSET 0x828 -#define FPC_STABLE_OFFSET 0x82C -#define MTC_STABLE_OFFSET 0x830 -#define OTHERS_OFFSET 0x900 -#define RST_STAT_OFFSET 0x904 -#define WAKEUP_STAT_OFFSET 0x908 -#define BLK_PWR_STAT_OFFSET 0x90C -#define INF_REG0_OFFSET 0xA00 -#define INF_REG1_OFFSET 0xA04 -#define INF_REG2_OFFSET 0xA08 -#define INF_REG3_OFFSET 0xA0C -#define INF_REG4_OFFSET 0xA10 -#define INF_REG5_OFFSET 0xA14 -#define INF_REG6_OFFSET 0xA18 -#define INF_REG7_OFFSET 0xA1C - -#define OSC_CNT_VAL_OFFSET 0x824 -#define PWR_CNT_VAL_OFFSET 0x828 -#define FPC_CNT_VAL_OFFSET 0x82C -#define MTC_CNT_VAL_OFFSET 0x830 - -#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - SELECT_DMA_OFFSET) -#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_CFG_STAT_OFFSET) -#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MTC_CNT_VAL_OFFSET) -#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - BLK_PWR_STAT_OFFSET) -#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - -#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET) -#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET) -#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET) -#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET) -#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - - -/* - * GPIO - */ -#define ELFIN_GPIO_BASE 0x7f008000 - -#define GPACON_OFFSET 0x00 -#define GPADAT_OFFSET 0x04 -#define GPAPUD_OFFSET 0x08 -#define GPACONSLP_OFFSET 0x0C -#define GPAPUDSLP_OFFSET 0x10 -#define GPBCON_OFFSET 0x20 -#define GPBDAT_OFFSET 0x24 -#define GPBPUD_OFFSET 0x28 -#define GPBCONSLP_OFFSET 0x2C -#define GPBPUDSLP_OFFSET 0x30 -#define GPCCON_OFFSET 0x40 -#define GPCDAT_OFFSET 0x44 -#define GPCPUD_OFFSET 0x48 -#define GPCCONSLP_OFFSET 0x4C -#define GPCPUDSLP_OFFSET 0x50 -#define GPDCON_OFFSET 0x60 -#define GPDDAT_OFFSET 0x64 -#define GPDPUD_OFFSET 0x68 -#define GPDCONSLP_OFFSET 0x6C -#define GPDPUDSLP_OFFSET 0x70 -#define GPECON_OFFSET 0x80 -#define GPEDAT_OFFSET 0x84 -#define GPEPUD_OFFSET 0x88 -#define GPECONSLP_OFFSET 0x8C -#define GPEPUDSLP_OFFSET 0x90 -#define GPFCON_OFFSET 0xA0 -#define GPFDAT_OFFSET 0xA4 -#define GPFPUD_OFFSET 0xA8 -#define GPFCONSLP_OFFSET 0xAC -#define GPFPUDSLP_OFFSET 0xB0 -#define GPGCON_OFFSET 0xC0 -#define GPGDAT_OFFSET 0xC4 -#define GPGPUD_OFFSET 0xC8 -#define GPGCONSLP_OFFSET 0xCC -#define GPGPUDSLP_OFFSET 0xD0 -#define GPHCON0_OFFSET 0xE0 -#define GPHCON1_OFFSET 0xE4 -#define GPHDAT_OFFSET 0xE8 -#define GPHPUD_OFFSET 0xEC -#define GPHCONSLP_OFFSET 0xF0 -#define GPHPUDSLP_OFFSET 0xF4 -#define GPICON_OFFSET 0x100 -#define GPIDAT_OFFSET 0x104 -#define GPIPUD_OFFSET 0x108 -#define GPICONSLP_OFFSET 0x10C -#define GPIPUDSLP_OFFSET 0x110 -#define GPJCON_OFFSET 0x120 -#define GPJDAT_OFFSET 0x124 -#define GPJPUD_OFFSET 0x128 -#define GPJCONSLP_OFFSET 0x12C -#define GPJPUDSLP_OFFSET 0x130 -#define MEM0DRVCON_OFFSET 0x1D0 -#define MEM1DRVCON_OFFSET 0x1D4 -#define GPKCON0_OFFSET 0x800 -#define GPKCON1_OFFSET 0x804 -#define GPKDAT_OFFSET 0x808 -#define GPKPUD_OFFSET 0x80C -#define GPLCON0_OFFSET 0x810 -#define GPLCON1_OFFSET 0x814 -#define GPLDAT_OFFSET 0x818 -#define GPLPUD_OFFSET 0x81C -#define GPMCON_OFFSET 0x820 -#define GPMDAT_OFFSET 0x824 -#define GPMPUD_OFFSET 0x828 -#define GPNCON_OFFSET 0x830 -#define GPNDAT_OFFSET 0x834 -#define GPNPUD_OFFSET 0x838 -#define GPOCON_OFFSET 0x140 -#define GPODAT_OFFSET 0x144 -#define GPOPUD_OFFSET 0x148 -#define GPOCONSLP_OFFSET 0x14C -#define GPOPUDSLP_OFFSET 0x150 -#define GPPCON_OFFSET 0x160 -#define GPPDAT_OFFSET 0x164 -#define GPPPUD_OFFSET 0x168 -#define GPPCONSLP_OFFSET 0x16C -#define GPPPUDSLP_OFFSET 0x170 -#define GPQCON_OFFSET 0x180 -#define GPQDAT_OFFSET 0x184 -#define GPQPUD_OFFSET 0x188 -#define GPQCONSLP_OFFSET 0x18C -#define GPQPUDSLP_OFFSET 0x190 - -#define EINTPEND_OFFSET 0x924 - -#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET) -#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET) -#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET) -#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET) -#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) -#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET) -#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET) -#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET) -#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) -#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) -#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET) -#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET) -#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET) -#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) -#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) -#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET) -#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET) -#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET) -#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) -#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) -#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET) -#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET) -#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET) -#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET) -#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) -#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET) -#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET) -#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET) -#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) -#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) -#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET) -#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET) -#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET) -#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) -#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) -#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET) -#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET) -#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET) -#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET) -#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) -#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) -#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET) -#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET) -#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET) -#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET) -#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) -#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET) -#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET) -#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET) -#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) -#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) -#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET) -#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET) -#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET) -#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET) -#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET) -#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET) -#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET) -#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET) -#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET) -#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET) -#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET) -#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET) -#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET) -#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET) -#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET) -#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET) -#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET) -#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) -#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) -#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET) -#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET) -#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET) -#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) -#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) -#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET) -#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET) -#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET) -#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) -#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) - -/* - * Bus Matrix - */ -#define ELFIN_MEM_SYS_CFG 0x7e00f120 - -#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) - -#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 -#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT - -#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET) -#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET) -#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET) -#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET) -#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) -#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET) -#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET) -#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET) -#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) -#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) -#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET) -#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET) -#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET) -#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) -#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) -#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET) -#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET) -#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET) -#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) -#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) -#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET) -#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET) -#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET) -#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET) -#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) -#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET) -#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET) -#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET) -#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) -#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) -#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET) -#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET) -#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET) -#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) -#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) -#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET) -#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET) -#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET) -#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET) -#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) -#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) -#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET) -#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET) -#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET) -#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET) -#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) -#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET) -#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET) -#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET) -#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) -#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) -#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET) -#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET) -#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET) -#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET) -#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET) -#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET) -#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET) -#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET) -#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET) -#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET) -#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET) -#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET) -#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET) -#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET) -#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET) -#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET) -#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET) -#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) -#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) -#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET) -#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET) -#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET) -#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) -#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) -#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET) -#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET) -#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET) -#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) -#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) - -/* - * Memory controller - */ -#define ELFIN_SROM_BASE 0x70000000 - -#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0) -#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4) -#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8) -#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC) -#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10) -#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14) -#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18) - -/* - * SDRAM Controller - */ -#define ELFIN_DMC0_BASE 0x7e000000 -#define ELFIN_DMC1_BASE 0x7e001000 - -#define INDEX_DMC_MEMC_STATUS 0x00 -#define INDEX_DMC_MEMC_CMD 0x04 -#define INDEX_DMC_DIRECT_CMD 0x08 -#define INDEX_DMC_MEMORY_CFG 0x0C -#define INDEX_DMC_REFRESH_PRD 0x10 -#define INDEX_DMC_CAS_LATENCY 0x14 -#define INDEX_DMC_T_DQSS 0x18 -#define INDEX_DMC_T_MRD 0x1C -#define INDEX_DMC_T_RAS 0x20 -#define INDEX_DMC_T_RC 0x24 -#define INDEX_DMC_T_RCD 0x28 -#define INDEX_DMC_T_RFC 0x2C -#define INDEX_DMC_T_RP 0x30 -#define INDEX_DMC_T_RRD 0x34 -#define INDEX_DMC_T_WR 0x38 -#define INDEX_DMC_T_WTR 0x3C -#define INDEX_DMC_T_XP 0x40 -#define INDEX_DMC_T_XSR 0x44 -#define INDEX_DMC_T_ESR 0x48 -#define INDEX_DMC_MEMORY_CFG2 0x4C -#define INDEX_DMC_CHIP_0_CFG 0x200 -#define INDEX_DMC_CHIP_1_CFG 0x204 -#define INDEX_DMC_CHIP_2_CFG 0x208 -#define INDEX_DMC_CHIP_3_CFG 0x20C -#define INDEX_DMC_USER_STATUS 0x300 -#define INDEX_DMC_USER_CONFIG 0x304 - -/* - * Memory Chip direct command - */ -#define DMC_NOP0 0x0c0000 -#define DMC_NOP1 0x1c0000 -#define DMC_PA0 0x000000 /* Precharge all */ -#define DMC_PA1 0x100000 -#define DMC_AR0 0x040000 /* Autorefresh */ -#define DMC_AR1 0x140000 -#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ -#define DMC_SDR_MR1 0x180032 -#define DMC_DDR_MR0 0x080162 -#define DMC_DDR_MR1 0x180162 -#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ -#define DMC_mDDR_MR1 0x180032 -#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ -#define DMC_mSDR_EMR1 0x1a0000 -#define DMC_DDR_EMR0 0x090000 -#define DMC_DDR_EMR1 0x190000 -#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ -#define DMC_mDDR_EMR1 0x1a0000 - -/* - * Definitions for memory configuration - * Set memory configuration - * active_chips = 1'b0 (1 chip) - * qos_master_chip = 3'b000(ARID[3:0]) - * memory burst = 3'b010(burst 4) - * stop_mem_clock = 1'b0(disable dynamical stop) - * auto_power_down = 1'b0(disable auto power-down mode) - * power_down_prd = 6'b00_0000(0 cycle for auto power-down) - * ap_bit = 1'b0 (bit position of auto-precharge is 10) - * row_bits = 3'b010(# row address 13) - * column_bits = 3'b010(# column address 10 ) - * - * Set user configuration - * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR - * - * Set chip select for chip [n] - * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff - * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] - */ - -/* - * Nand flash controller - */ -#define ELFIN_NAND_BASE 0x70200000 - -#define NFCONF_OFFSET 0x00 -#define NFCONT_OFFSET 0x04 -#define NFCMMD_OFFSET 0x08 -#define NFADDR_OFFSET 0x0c -#define NFDATA_OFFSET 0x10 -#define NFMECCDATA0_OFFSET 0x14 -#define NFMECCDATA1_OFFSET 0x18 -#define NFSECCDATA0_OFFSET 0x1c -#define NFSBLK_OFFSET 0x20 -#define NFEBLK_OFFSET 0x24 -#define NFSTAT_OFFSET 0x28 -#define NFESTAT0_OFFSET 0x2c -#define NFESTAT1_OFFSET 0x30 -#define NFMECC0_OFFSET 0x34 -#define NFMECC1_OFFSET 0x38 -#define NFSECC_OFFSET 0x3c -#define NFMLCBITPT_OFFSET 0x40 - -#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_ECC_4BIT (1<<24) - -#define NFCONT_ECC_ENC (1<<18) -#define NFCONT_WP (1<<16) -#define NFCONT_MECCLOCK (1<<7) -#define NFCONT_SECCLOCK (1<<6) -#define NFCONT_INITMECC (1<<5) -#define NFCONT_INITSECC (1<<4) -#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) -#define NFCONT_CS_ALT (1<<2) -#define NFCONT_CS (1<<1) -#define NFCONT_ENABLE (1<<0) - -#define NFSTAT_ECCENCDONE (1<<7) -#define NFSTAT_ECCDECDONE (1<<6) -#define NFSTAT_RnB (1<<0) - -#define NFESTAT0_ECCBUSY (1<<31) - -/* - * Interrupt - */ -#define ELFIN_VIC0_BASE_ADDR 0x71200000 -#define ELFIN_VIC1_BASE_ADDR 0x71300000 -#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */ -#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */ -#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */ -#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */ -#define oVECTADDR 0xF00 /* VIC ADDRESS */ - -/* - * Watchdog timer - */ -#define ELFIN_WATCHDOG_BASE 0x7E004000 - -#define WTCON_REG __REG(0x7E004004) -#define WTDAT_REG __REG(0x7E004008) -#define WTCNT_REG __REG(0x7E00400C) - - -/* - * UART - */ -#define ELFIN_UART_BASE 0x7F005000 - -#define ELFIN_UART0_OFFSET 0x0000 -#define ELFIN_UART1_OFFSET 0x0400 -#define ELFIN_UART2_OFFSET 0x0800 - -#define ULCON_OFFSET 0x00 -#define UCON_OFFSET 0x04 -#define UFCON_OFFSET 0x08 -#define UMCON_OFFSET 0x0C -#define UTRSTAT_OFFSET 0x10 -#define UERSTAT_OFFSET 0x14 -#define UFSTAT_OFFSET 0x18 -#define UMSTAT_OFFSET 0x1C -#define UTXH_OFFSET 0x20 -#define URXH_OFFSET 0x24 -#define UBRDIV_OFFSET 0x28 -#define UDIVSLOT_OFFSET 0x2C -#define UINTP_OFFSET 0x30 -#define UINTSP_OFFSET 0x34 -#define UINTM_OFFSET 0x38 - -#define ULCON0_REG __REG(0x7F005000) -#define UCON0_REG __REG(0x7F005004) -#define UFCON0_REG __REG(0x7F005008) -#define UMCON0_REG __REG(0x7F00500C) -#define UTRSTAT0_REG __REG(0x7F005010) -#define UERSTAT0_REG __REG(0x7F005014) -#define UFSTAT0_REG __REG(0x7F005018) -#define UMSTAT0_REG __REG(0x7F00501c) -#define UTXH0_REG __REG(0x7F005020) -#define URXH0_REG __REG(0x7F005024) -#define UBRDIV0_REG __REG(0x7F005028) -#define UDIVSLOT0_REG __REG(0x7F00502c) -#define UINTP0_REG __REG(0x7F005030) -#define UINTSP0_REG __REG(0x7F005034) -#define UINTM0_REG __REG(0x7F005038) - -#define ULCON1_REG __REG(0x7F005400) -#define UCON1_REG __REG(0x7F005404) -#define UFCON1_REG __REG(0x7F005408) -#define UMCON1_REG __REG(0x7F00540C) -#define UTRSTAT1_REG __REG(0x7F005410) -#define UERSTAT1_REG __REG(0x7F005414) -#define UFSTAT1_REG __REG(0x7F005418) -#define UMSTAT1_REG __REG(0x7F00541c) -#define UTXH1_REG __REG(0x7F005420) -#define URXH1_REG __REG(0x7F005424) -#define UBRDIV1_REG __REG(0x7F005428) -#define UDIVSLOT1_REG __REG(0x7F00542c) -#define UINTP1_REG __REG(0x7F005430) -#define UINTSP1_REG __REG(0x7F005434) -#define UINTM1_REG __REG(0x7F005438) - -#define UTRSTAT_TX_EMPTY (1 << 2) -#define UTRSTAT_RX_READY (1 << 0) -#define UART_ERR_MASK 0xF - -/* - * PWM timer - */ -#define ELFIN_TIMER_BASE 0x7F006000 - -#define TCFG0_REG __REG(0x7F006000) -#define TCFG1_REG __REG(0x7F006004) -#define TCON_REG __REG(0x7F006008) -#define TCNTB0_REG __REG(0x7F00600c) -#define TCMPB0_REG __REG(0x7F006010) -#define TCNTO0_REG __REG(0x7F006014) -#define TCNTB1_REG __REG(0x7F006018) -#define TCMPB1_REG __REG(0x7F00601c) -#define TCNTO1_REG __REG(0x7F006020) -#define TCNTB2_REG __REG(0x7F006024) -#define TCMPB2_REG __REG(0x7F006028) -#define TCNTO2_REG __REG(0x7F00602c) -#define TCNTB3_REG __REG(0x7F006030) -#define TCMPB3_REG __REG(0x7F006034) -#define TCNTO3_REG __REG(0x7F006038) -#define TCNTB4_REG __REG(0x7F00603c) -#define TCNTO4_REG __REG(0x7F006040) - -/* Fields */ -#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */ -#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */ -#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */ -#define fTCFG1_MUX4 Fld(4, 16) -/* bits */ -#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) -#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) -#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) -#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ -#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ -#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ -#define COUNT_4_ON (TCON_4_ONOFF * 1) -#define COUNT_4_OFF (TCON_4_ONOFF * 0) -#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ -#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1) -#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) -#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ -#define TIMER3_IVT_ON (TCON_3_INVERT * 1) -#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) -#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ -#define TIMER3_MANUP (TCON_3_MAN*1) -#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) -#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ -#define TIMER3_ON (TCON_3_ONOFF * 1) -#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) - -#if defined(CONFIG_CLK_400_100_50) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 400 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_400_133_66) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_533_133_66) -#define STARTUP_AMDIV 533 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_667_133_66) -#define STARTUP_AMDIV 667 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#endif - -#define STARTUP_PCLKDIV 3 -#define STARTUP_HCLKX2DIV 1 -#define STARTUP_HCLKDIV 1 -#define STARTUP_MPLLDIV 1 -#define STARTUP_APLLDIV 0 - -#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ - (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) -#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) - -#if defined(CONFIG_SYNC_MODE) -#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#else -#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_AMDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#endif - - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ -#define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */ -#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ - -/* Memory Parameters */ -/* DDR Parameters */ -#define DDR_tREFRESH 7800 /* ns */ -#define DDR_tRAS 45 /* ns (min: 45ns)*/ -#define DDR_tRC 68 /* ns (min: 67.5ns)*/ -#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ -#define DDR_tRFC 80 /* ns (min: 80ns)*/ -#define DDR_tRP 23 /* ns (min: 22.5ns)*/ -#define DDR_tRRD 15 /* ns (min: 15ns)*/ -#define DDR_tWR 15 /* ns (min: 15ns)*/ -#define DDR_tXSR 120 /* ns (min: 120ns)*/ -#define DDR_CASL 3 /* CAS Latency 3 */ - -/* - * mDDR memory configuration - */ - -#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) - -#define DMC_DDR_BA_EMRS 2 -#define DMC_DDR_MEM_CASLAT 3 -/* 6 Set Cas Latency to 3 */ -#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) -/* Min 0.75 ~ 1.25 */ -#define DMC_DDR_t_DQSS 1 -/* Min 2 tck */ -#define DMC_DDR_t_MRD 2 -/* 7, Min 45ns */ -#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) -/* 10, Min 67.5ns */ -#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) -/* 4,5(TRM), Min 22.5ns */ -#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) -#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) -/* 11,18(TRM) Min 80ns */ -#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) -#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) -/* 4, 5(TRM) Min 22.5ns */ -#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) -#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) -/* 3, Min 15ns */ -#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) -/* Min 15ns */ -#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) -#define DMC_DDR_t_WTR 2 -/* 1tck + tIS(1.5ns) */ -#define DMC_DDR_t_XP 2 -/* 17, Min 120ns */ -#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) -#define DMC_DDR_t_ESR DMC_DDR_t_XSR -/* TRM 2656 */ -#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) -/* 2b01 : mDDR */ -#define DMC_DDR_USER_CONFIG 1 - -#ifndef __ASSEMBLY__ -enum s3c64xx_uarts_nr { - S3C64XX_UART0, - S3C64XX_UART1, - S3C64XX_UART2, -}; - -#include "s3c64x0.h" - -static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) -{ - return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); -} -#endif - -#endif /*__S3C6400_H__*/ diff --git a/include/asm-arm/arch-s3c64xx/s3c64x0.h b/include/asm-arm/arch-s3c64xx/s3c64x0.h deleted file mode 100644 index 0bbf1d0..0000000 --- a/include/asm-arm/arch-s3c64xx/s3c64x0.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) Copyright 2003 - * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : S3C64XX.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C64XX SoC - ************************************************/ - -#ifndef __S3C64XX_H__ -#define __S3C64XX_H__ - -#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) -#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! -#endif - -#include - -/* UART (see manual chapter 11) */ -typedef struct { - volatile u32 ULCON; - volatile u32 UCON; - volatile u32 UFCON; - volatile u32 UMCON; - volatile u32 UTRSTAT; - volatile u32 UERSTAT; - volatile u32 UFSTAT; - volatile u32 UMSTAT; -#ifdef __BIG_ENDIAN - volatile u8 res1[3]; - volatile u8 UTXH; - volatile u8 res2[3]; - volatile u8 URXH; -#else /* Little Endian */ - volatile u8 UTXH; - volatile u8 res1[3]; - volatile u8 URXH; - volatile u8 res2[3]; -#endif - volatile u32 UBRDIV; -#ifdef __BIG_ENDIAN - volatile u8 res3[2]; - volatile u16 UDIVSLOT; -#else - volatile u16 UDIVSLOT; - volatile u8 res3[2]; -#endif -} s3c64xx_uart; - -/* PWM TIMER (see manual chapter 10) */ -typedef struct { - volatile u32 TCNTB; - volatile u32 TCMPB; - volatile u32 TCNTO; -} s3c64xx_timer; - -typedef struct { - volatile u32 TCFG0; - volatile u32 TCFG1; - volatile u32 TCON; - s3c64xx_timer ch[4]; - volatile u32 TCNTB4; - volatile u32 TCNTO4; -} s3c64xx_timers; - -#endif /*__S3C64XX_H__*/ diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h deleted file mode 100644 index 3e59abe..0000000 --- a/include/asm-arm/arch-s5pc1xx/clk.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang - * Heungjun Kim - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARM_ARCH_CLK_H_ -#define __ASM_ARM_ARCH_CLK_H_ - -#define APLL 0 -#define MPLL 1 -#define EPLL 2 -#define HPLL 3 -#define VPLL 4 - -void s5pc1xx_clock_init(void); - -extern unsigned long (*get_pll_clk)(int pllreg); -extern unsigned long (*get_arm_clk)(void); -extern unsigned long (*get_pclk)(void); - -#endif diff --git a/include/asm-arm/arch-s5pc1xx/clock.h b/include/asm-arm/arch-s5pc1xx/clock.h deleted file mode 100644 index 7b4eb89..0000000 --- a/include/asm-arm/arch-s5pc1xx/clock.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang - * Heungjun Kim - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARM_ARCH_CLOCK_H_ -#define __ASM_ARM_ARCH_CLOCK_H_ - -#ifndef __ASSEMBLY__ -struct s5pc100_clock { - unsigned int apll_lock; - unsigned int mpll_lock; - unsigned int epll_lock; - unsigned int hpll_lock; - unsigned char res1[0xf0]; - unsigned int apll_con; - unsigned int mpll_con; - unsigned int epll_con; - unsigned int hpll_con; - unsigned char res2[0xf0]; - unsigned int src0; - unsigned int src1; - unsigned int src2; - unsigned int src3; - unsigned char res3[0xf0]; - unsigned int div0; - unsigned int div1; - unsigned int div2; - unsigned int div3; - unsigned int div4; - unsigned char res4[0x1ec]; - unsigned int gate_d00; - unsigned int gate_d01; - unsigned int gate_d02; - unsigned char res5[0x54]; - unsigned int gate_sclk0; - unsigned int gate_sclk1; -}; - -struct s5pc110_clock { - unsigned int apll_lock; - unsigned char res1[0x4]; - unsigned int mpll_lock; - unsigned char res2[0x4]; - unsigned int epll_lock; - unsigned char res3[0xc]; - unsigned int vpll_lock; - unsigned char res4[0xdc]; - unsigned int apll_con; - unsigned char res5[0x4]; - unsigned int mpll_con; - unsigned char res6[0x4]; - unsigned int epll_con; - unsigned char res7[0xc]; - unsigned int vpll_con; - unsigned char res8[0xdc]; - unsigned int src0; - unsigned int src1; - unsigned int src2; - unsigned int src3; - unsigned char res9[0xf0]; - unsigned int div0; - unsigned int div1; - unsigned int div2; - unsigned int div3; - unsigned int div4; - unsigned char res10[0x1ec]; - unsigned int gate_d00; - unsigned int gate_d01; - unsigned int gate_d02; - unsigned char res11[0x54]; - unsigned int gate_sclk0; - unsigned int gate_sclk1; -}; -#endif - -#endif diff --git a/include/asm-arm/arch-s5pc1xx/cpu.h b/include/asm-arm/arch-s5pc1xx/cpu.h deleted file mode 100644 index 90485aa..0000000 --- a/include/asm-arm/arch-s5pc1xx/cpu.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang - * Heungjun Kim - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _S5PC1XX_CPU_H -#define _S5PC1XX_CPU_H - -#define S5PC1XX_ADDR_BASE 0xE0000000 - -#define S5PC1XX_CLOCK_BASE 0xE0100000 - -/* S5PC100 */ -#define S5PC100_GPIO_BASE 0xE0300000 -#define S5PC100_VIC0_BASE 0xE4000000 -#define S5PC100_VIC1_BASE 0xE4100000 -#define S5PC100_VIC2_BASE 0xE4200000 -#define S5PC100_DMC_BASE 0xE6000000 -#define S5PC100_SROMC_BASE 0xE7000000 -#define S5PC100_ONENAND_BASE 0xE7100000 -#define S5PC100_PWMTIMER_BASE 0xEA000000 -#define S5PC100_WATCHDOG_BASE 0xEA200000 -#define S5PC100_UART_BASE 0xEC000000 - -/* S5PC110 */ -#define S5PC110_GPIO_BASE 0xE0200000 -#define S5PC110_PWMTIMER_BASE 0xE2500000 -#define S5PC110_WATCHDOG_BASE 0xE2700000 -#define S5PC110_UART_BASE 0xE2900000 -#define S5PC110_SROMC_BASE 0xE8000000 -#define S5PC110_DMC0_BASE 0xF0000000 -#define S5PC110_DMC1_BASE 0xF1400000 -#define S5PC110_VIC0_BASE 0xF2000000 -#define S5PC110_VIC1_BASE 0xF2100000 -#define S5PC110_VIC2_BASE 0xF2200000 -#define S5PC110_VIC3_BASE 0xF2300000 - -/* Chip ID */ -#define S5PC1XX_PRO_ID 0xE0000000 - -#ifndef __ASSEMBLY__ -/* CPU detection macros */ -extern unsigned int s5pc1xx_cpu_id; - -#define IS_SAMSUNG_TYPE(type, id) \ -static inline int cpu_is_##type(void) \ -{ \ - return s5pc1xx_cpu_id == id ? 1 : 0; \ -} - -IS_SAMSUNG_TYPE(s5pc100, 0xc100) -IS_SAMSUNG_TYPE(s5pc110, 0xc110) -#endif - -#endif /* _S5PC1XX_CPU_H */ diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h deleted file mode 100644 index 8e4bb86..0000000 --- a/include/asm-arm/arch-s5pc1xx/gpio.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#ifndef __ASSEMBLY__ -struct s5pc1xx_gpio_bank { - unsigned int con; - unsigned int dat; - unsigned int pull; - unsigned int drv; - unsigned int pdn_con; - unsigned int pdn_pull; - unsigned char res1[8]; -}; - -struct s5pc100_gpio { - struct s5pc1xx_gpio_bank gpio_a0; - struct s5pc1xx_gpio_bank gpio_a1; - struct s5pc1xx_gpio_bank gpio_b; - struct s5pc1xx_gpio_bank gpio_c; - struct s5pc1xx_gpio_bank gpio_d; - struct s5pc1xx_gpio_bank gpio_e0; - struct s5pc1xx_gpio_bank gpio_e1; - struct s5pc1xx_gpio_bank gpio_f0; - struct s5pc1xx_gpio_bank gpio_f1; - struct s5pc1xx_gpio_bank gpio_f2; - struct s5pc1xx_gpio_bank gpio_f3; - struct s5pc1xx_gpio_bank gpio_g0; - struct s5pc1xx_gpio_bank gpio_g1; - struct s5pc1xx_gpio_bank gpio_g2; - struct s5pc1xx_gpio_bank gpio_g3; - struct s5pc1xx_gpio_bank gpio_i; - struct s5pc1xx_gpio_bank gpio_j0; - struct s5pc1xx_gpio_bank gpio_j1; - struct s5pc1xx_gpio_bank gpio_j2; - struct s5pc1xx_gpio_bank gpio_j3; - struct s5pc1xx_gpio_bank gpio_j4; - struct s5pc1xx_gpio_bank gpio_k0; - struct s5pc1xx_gpio_bank gpio_k1; - struct s5pc1xx_gpio_bank gpio_k2; - struct s5pc1xx_gpio_bank gpio_k3; - struct s5pc1xx_gpio_bank gpio_l0; - struct s5pc1xx_gpio_bank gpio_l1; - struct s5pc1xx_gpio_bank gpio_l2; - struct s5pc1xx_gpio_bank gpio_l3; - struct s5pc1xx_gpio_bank gpio_l4; - struct s5pc1xx_gpio_bank gpio_h0; - struct s5pc1xx_gpio_bank gpio_h1; - struct s5pc1xx_gpio_bank gpio_h2; - struct s5pc1xx_gpio_bank gpio_h3; -}; - -struct s5pc110_gpio { - struct s5pc1xx_gpio_bank gpio_a0; - struct s5pc1xx_gpio_bank gpio_a1; - struct s5pc1xx_gpio_bank gpio_b; - struct s5pc1xx_gpio_bank gpio_c0; - struct s5pc1xx_gpio_bank gpio_c1; - struct s5pc1xx_gpio_bank gpio_d0; - struct s5pc1xx_gpio_bank gpio_d1; - struct s5pc1xx_gpio_bank gpio_e0; - struct s5pc1xx_gpio_bank gpio_e1; - struct s5pc1xx_gpio_bank gpio_f0; - struct s5pc1xx_gpio_bank gpio_f1; - struct s5pc1xx_gpio_bank gpio_f2; - struct s5pc1xx_gpio_bank gpio_f3; - struct s5pc1xx_gpio_bank gpio_g0; - struct s5pc1xx_gpio_bank gpio_g1; - struct s5pc1xx_gpio_bank gpio_g2; - struct s5pc1xx_gpio_bank gpio_g3; - struct s5pc1xx_gpio_bank gpio_i; - struct s5pc1xx_gpio_bank gpio_j0; - struct s5pc1xx_gpio_bank gpio_j1; - struct s5pc1xx_gpio_bank gpio_j2; - struct s5pc1xx_gpio_bank gpio_j3; - struct s5pc1xx_gpio_bank gpio_j4; - struct s5pc1xx_gpio_bank gpio_mp0_1; - struct s5pc1xx_gpio_bank gpio_mp0_2; - struct s5pc1xx_gpio_bank gpio_mp0_3; - struct s5pc1xx_gpio_bank gpio_mp0_4; - struct s5pc1xx_gpio_bank gpio_mp0_5; - struct s5pc1xx_gpio_bank gpio_mp0_6; - struct s5pc1xx_gpio_bank gpio_mp0_7; - struct s5pc1xx_gpio_bank gpio_mp1_0; - struct s5pc1xx_gpio_bank gpio_mp1_1; - struct s5pc1xx_gpio_bank gpio_mp1_2; - struct s5pc1xx_gpio_bank gpio_mp1_3; - struct s5pc1xx_gpio_bank gpio_mp1_4; - struct s5pc1xx_gpio_bank gpio_mp1_5; - struct s5pc1xx_gpio_bank gpio_mp1_6; - struct s5pc1xx_gpio_bank gpio_mp1_7; - struct s5pc1xx_gpio_bank gpio_mp1_8; - struct s5pc1xx_gpio_bank gpio_mp2_0; - struct s5pc1xx_gpio_bank gpio_mp2_1; - struct s5pc1xx_gpio_bank gpio_mp2_2; - struct s5pc1xx_gpio_bank gpio_mp2_3; - struct s5pc1xx_gpio_bank gpio_mp2_4; - struct s5pc1xx_gpio_bank gpio_mp2_5; - struct s5pc1xx_gpio_bank gpio_mp2_6; - struct s5pc1xx_gpio_bank gpio_mp2_7; - struct s5pc1xx_gpio_bank gpio_mp2_8; - struct s5pc1xx_gpio_bank res1[48]; - struct s5pc1xx_gpio_bank gpio_h0; - struct s5pc1xx_gpio_bank gpio_h1; - struct s5pc1xx_gpio_bank gpio_h2; - struct s5pc1xx_gpio_bank gpio_h3; -}; - -/* functions */ -void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg); -void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en); -void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio); -void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en); -unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio); -void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); -void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); -void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); -#endif - -/* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) - -/* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x2 - -/* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_2X 0x1 -#define GPIO_DRV_3X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 - -#endif diff --git a/include/asm-arm/arch-s5pc1xx/power.h b/include/asm-arm/arch-s5pc1xx/power.h deleted file mode 100644 index 57e2a2b..0000000 --- a/include/asm-arm/arch-s5pc1xx/power.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2009 Samsung Electronics - * Kyungmin Park - * Minkyu Kang - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARM_ARCH_POWER_H_ -#define __ASM_ARM_ARCH_POWER_H_ - -/* - * Power control - */ -#define S5PC100_OTHERS 0xE0108200 -#define S5PC100_RST_STAT 0xE0108300 -#define S5PC100_SLEEP_WAKEUP (1 << 3) -#define S5PC100_WAKEUP_STAT 0xE0108304 -#define S5PC100_INFORM0 0xE0108400 - -#define S5PC110_RST_STAT 0xE010A000 -#define S5PC110_SLEEP_WAKEUP (1 << 3) -#define S5PC110_WAKEUP_STAT 0xE010C200 -#define S5PC110_OTHERS 0xE010E000 -#define S5PC110_USB_PHY_CON 0xE010E80C -#define S5PC110_INFORM0 0xE010F000 - -#endif diff --git a/include/asm-arm/arch-s5pc1xx/pwm.h b/include/asm-arm/arch-s5pc1xx/pwm.h deleted file mode 100644 index e02a8d8..0000000 --- a/include/asm-arm/arch-s5pc1xx/pwm.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Kyungmin Park - * Minkyu Kang - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARM_ARCH_PWM_H_ -#define __ASM_ARM_ARCH_PWM_H_ - -/* PWM timer addressing */ -#define S5PC100_TIMER_BASE S5PC100_PWMTIMER_BASE -#define S5PC110_TIMER_BASE S5PC110_PWMTIMER_BASE - -/* Interval mode(Auto Reload) of PWM Timer 4 */ -#define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22) -/* Update TCNTB4 */ -#define S5PC1XX_TCON4_UPDATE (1 << 21) -/* start bit of PWM Timer 4 */ -#define S5PC1XX_TCON4_START (1 << 20) - -#ifndef __ASSEMBLY__ -struct s5pc1xx_timer { - unsigned int tcfg0; - unsigned int tcfg1; - unsigned int tcon; - unsigned int tcntb0; - unsigned int tcmpb0; - unsigned int tcnto0; - unsigned int tcntb1; - unsigned int tcmpb1; - unsigned int tcnto1; - unsigned int tcntb2; - unsigned int tcmpb2; - unsigned int tcnto2; - unsigned int tcntb3; - unsigned int res1; - unsigned int tcnto3; - unsigned int tcntb4; - unsigned int tcnto4; - unsigned int tintcstat; -}; -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/include/asm-arm/arch-s5pc1xx/smc.h deleted file mode 100644 index 88f4ffe..0000000 --- a/include/asm-arm/arch-s5pc1xx/smc.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2010 Samsung Electronics - * Naveen Krishna Ch - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Note: This file contains the register description for Memory subsystem - * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. - * - * Only SROMC is defined as of now - */ - -#ifndef __ASM_ARCH_SMC_H_ -#define __ASM_ARCH_SMC_H_ - -#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) -#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ - /* 1-> Byte base address*/ -#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) -#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) - -#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ -#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ -#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ -#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ -#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ -#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ -#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ - -#ifndef __ASSEMBLY__ -struct s5pc1xx_smc { - unsigned int bw; - unsigned int bc[6]; -}; -#endif /* __ASSEMBLY__ */ - -/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ -void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf); - -#endif /* __ASM_ARCH_SMC_H_ */ diff --git a/include/asm-arm/arch-s5pc1xx/sys_proto.h b/include/asm-arm/arch-s5pc1xx/sys_proto.h deleted file mode 100644 index 3078aaf..0000000 --- a/include/asm-arm/arch-s5pc1xx/sys_proto.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electrnoics - * Minkyu Kang - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -u32 get_device_type(void); -void invalidate_dcache(u32); -void l2_cache_disable(void); -void l2_cache_enable(void); - -#endif diff --git a/include/asm-arm/arch-s5pc1xx/uart.h b/include/asm-arm/arch-s5pc1xx/uart.h deleted file mode 100644 index 140dbdc..0000000 --- a/include/asm-arm/arch-s5pc1xx/uart.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang - * Heungjun Kim - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_UART_H_ -#define __ASM_ARCH_UART_H_ - -#ifndef __ASSEMBLY__ -struct s5pc1xx_uart { - unsigned int ulcon; - unsigned int ucon; - unsigned int ufcon; - unsigned int umcon; - unsigned int utrstat; - unsigned int uerstat; - unsigned int ufstat; - unsigned int umstat; - unsigned char utxh; - unsigned char res1[3]; - unsigned char urxh; - unsigned char res2[3]; - unsigned int ubrdiv; - unsigned short udivslot; - unsigned char res3[2]; - unsigned char res4[0x3d0]; -}; -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h deleted file mode 100644 index 104a21c..0000000 --- a/include/asm-arm/arch-sa1100/bitfield.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FILE bitfield.h - * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) - * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. - */ - - -#ifndef __BITFIELD_H -#define __BITFIELD_H - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) -#else -#define UData(Data) (Data) -#endif - - -/* - * MACRO: Fld - * - * Purpose - * The macro "Fld" encodes a bit field, given its size and its shift value - * with respect to bit 0. - * - * Note - * A more intuitive way to encode bit fields would have been to use their - * mask. However, extracting size and shift value information from a bit - * field's mask is cumbersome and might break the assembler (255-character - * line-size limit). - * - * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. - * - * Output - * Fld Encoded bit field. - */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - - -/* - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit - * - * Purpose - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return - * the size, shift value, mask, aligned mask, and first bit of a - * bit field. - * - * Input - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. - */ - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/include/asm-arm/arch-spear/hardware.h b/include/asm-arm/arch-spear/hardware.h deleted file mode 100644 index 818f36c..0000000 --- a/include/asm-arm/arch-spear/hardware.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, STMicroelectronics, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -#define CONFIG_SYS_USBD_BASE (0xE1100000) -#define CONFIG_SYS_PLUG_BASE (0xE1200000) -#define CONFIG_SYS_FIFO_BASE (0xE1000800) -#define CONFIG_SYS_SMI_BASE (0xFC000000) -#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) -#define CONFIG_SPEAR_TIMERBASE (0xFC800000) -#define CONFIG_SPEAR_MISCBASE (0xFCA80000) - -#define CONFIG_SYS_NAND_CLE (1 << 16) -#define CONFIG_SYS_NAND_ALE (1 << 17) - -#if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_I2C_BASE (0xD0200000) -#define CONFIG_SPEAR_FSMCBASE (0xD1800000) - -#elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x94000000) - -#elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x44000000) - -#undef CONFIG_SYS_NAND_CLE -#undef CONFIG_SYS_NAND_ALE -#define CONFIG_SYS_NAND_CLE (1 << 17) -#define CONFIG_SYS_NAND_ALE (1 << 16) - -#define CONFIG_SPEAR_EMIBASE (0x4F000000) -#define CONFIG_SPEAR_RASBASE (0xB4000000) - -#elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x4C000000) - -#define CONFIG_SPEAR_EMIBASE (0x40000000) -#define CONFIG_SPEAR_RASBASE (0xB3000000) - -#endif -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-spear/spr_defs.h b/include/asm-arm/arch-spear/spr_defs.h deleted file mode 100644 index fa8412c..0000000 --- a/include/asm-arm/arch-spear/spr_defs.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPR_DEFS_H__ -#define __SPR_DEFS_H__ - -extern int spear_board_init(ulong); -extern void setfreq(unsigned int, unsigned int); -extern unsigned int setfreq_sz; - -struct chip_data { - int cpufreq; - int dramfreq; - int dramtype; - uchar version[32]; -}; - -/* HW mac id in i2c memory definitions */ -#define MAGIC_OFF 0x0 -#define MAGIC_LEN 0x2 -#define MAGIC_BYTE0 0x55 -#define MAGIC_BYTE1 0xAA -#define MAC_OFF 0x2 -#define MAC_LEN 0x6 - -#endif diff --git a/include/asm-arm/arch-spear/spr_emi.h b/include/asm-arm/arch-spear/spr_emi.h deleted file mode 100644 index c1f1c2a..0000000 --- a/include/asm-arm/arch-spear/spr_emi.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2009 - * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPEAR_EMI_H__ -#define __SPEAR_EMI_H__ - -#ifdef CONFIG_SPEAR_EMI - -struct emi_bank_regs { - u32 tap; - u32 tsdp; - u32 tdpw; - u32 tdpr; - u32 tdcs; - u32 control; -}; - -struct emi_regs { - struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS]; - u32 tout; - u32 ack; - u32 irq; -}; - -#define EMI_ACKMSK 0x40 - -/* control register definitions */ -#define EMI_CNTL_ENBBYTEW (1 << 2) -#define EMI_CNTL_ENBBYTER (1 << 3) -#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW) - -#endif - -#endif diff --git a/include/asm-arm/arch-spear/spr_gpt.h b/include/asm-arm/arch-spear/spr_gpt.h deleted file mode 100644 index 965b5ab..0000000 --- a/include/asm-arm/arch-spear/spr_gpt.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SPR_GPT_H -#define _SPR_GPT_H - -struct gpt_regs { - u8 reserved[0x80]; - u32 control; - u32 status; - u32 compare; - u32 count; - u32 capture_re; - u32 capture_fe; -}; - -/* - * TIMER_CONTROL register settings - */ - -#define GPT_PRESCALER_MASK 0x000F -#define GPT_PRESCALER_1 0x0000 -#define GPT_PRESCALER_2 0x0001 -#define GPT_PRESCALER_4 0x0002 -#define GPT_PRESCALER_8 0x0003 -#define GPT_PRESCALER_16 0x0004 -#define GPT_PRESCALER_32 0x0005 -#define GPT_PRESCALER_64 0x0006 -#define GPT_PRESCALER_128 0x0007 -#define GPT_PRESCALER_256 0x0008 - -#define GPT_MODE_SINGLE_SHOT 0x0010 -#define GPT_MODE_AUTO_RELOAD 0x0000 - -#define GPT_ENABLE 0x0020 - -#define GPT_CAPT_MODE_MASK 0x00C0 -#define GPT_CAPT_MODE_NONE 0x0000 -#define GPT_CAPT_MODE_RE 0x0040 -#define GPT_CAPT_MODE_FE 0x0080 -#define GPT_CAPT_MODE_BOTH 0x00C0 - -#define GPT_INT_MATCH 0x0100 -#define GPT_INT_FE 0x0200 -#define GPT_INT_RE 0x0400 - -/* - * TIMER_STATUS register settings - */ - -#define GPT_STS_MATCH 0x0001 -#define GPT_STS_FE 0x0002 -#define GPT_STS_RE 0x0004 - -/* - * TIMER_COMPARE register settings - */ - -#define GPT_FREE_RUNNING 0xFFFF - -/* Timer, HZ specific defines */ -#define CONFIG_SPEAR_HZ (1000) -#define CONFIG_SPEAR_HZ_CLOCK (8300000) - -#endif diff --git a/include/asm-arm/arch-spear/spr_i2c.h b/include/asm-arm/arch-spear/spr_i2c.h deleted file mode 100644 index 7521ebc..0000000 --- a/include/asm-arm/arch-spear/spr_i2c.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPR_I2C_H_ -#define __SPR_I2C_H_ - -struct i2c_regs { - u32 ic_con; - u32 ic_tar; - u32 ic_sar; - u32 ic_hs_maddr; - u32 ic_cmd_data; - u32 ic_ss_scl_hcnt; - u32 ic_ss_scl_lcnt; - u32 ic_fs_scl_hcnt; - u32 ic_fs_scl_lcnt; - u32 ic_hs_scl_hcnt; - u32 ic_hs_scl_lcnt; - u32 ic_intr_stat; - u32 ic_intr_mask; - u32 ic_raw_intr_stat; - u32 ic_rx_tl; - u32 ic_tx_tl; - u32 ic_clr_intr; - u32 ic_clr_rx_under; - u32 ic_clr_rx_over; - u32 ic_clr_tx_over; - u32 ic_clr_rd_req; - u32 ic_clr_tx_abrt; - u32 ic_clr_rx_done; - u32 ic_clr_activity; - u32 ic_clr_stop_det; - u32 ic_clr_start_det; - u32 ic_clr_gen_call; - u32 ic_enable; - u32 ic_status; - u32 ic_txflr; - u32 ix_rxflr; - u32 reserved_1; - u32 ic_tx_abrt_source; -}; - -#define IC_CLK 166 -#define NANO_TO_MICRO 1000 - -/* High and low times in different speed modes (in ns) */ -#define MIN_SS_SCL_HIGHTIME 4000 -#define MIN_SS_SCL_LOWTIME 5000 -#define MIN_FS_SCL_HIGHTIME 800 -#define MIN_FS_SCL_LOWTIME 1700 -#define MIN_HS_SCL_HIGHTIME 60 -#define MIN_HS_SCL_LOWTIME 160 - -/* Worst case timeout for 1 byte is kept as 2ms */ -#define I2C_BYTE_TO (CONFIG_SYS_HZ/500) -#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500) -#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16) - -/* i2c control register definitions */ -#define IC_CON_SD 0x0040 -#define IC_CON_RE 0x0020 -#define IC_CON_10BITADDRMASTER 0x0010 -#define IC_CON_10BITADDR_SLAVE 0x0008 -#define IC_CON_SPD_MSK 0x0006 -#define IC_CON_SPD_SS 0x0002 -#define IC_CON_SPD_FS 0x0004 -#define IC_CON_SPD_HS 0x0006 -#define IC_CON_MM 0x0001 - -/* i2c target address register definitions */ -#define TAR_ADDR 0x0050 - -/* i2c slave address register definitions */ -#define IC_SLAVE_ADDR 0x0002 - -/* i2c data buffer and command register definitions */ -#define IC_CMD 0x0100 - -/* i2c interrupt status register definitions */ -#define IC_GEN_CALL 0x0800 -#define IC_START_DET 0x0400 -#define IC_STOP_DET 0x0200 -#define IC_ACTIVITY 0x0100 -#define IC_RX_DONE 0x0080 -#define IC_TX_ABRT 0x0040 -#define IC_RD_REQ 0x0020 -#define IC_TX_EMPTY 0x0010 -#define IC_TX_OVER 0x0008 -#define IC_RX_FULL 0x0004 -#define IC_RX_OVER 0x0002 -#define IC_RX_UNDER 0x0001 - -/* fifo threshold register definitions */ -#define IC_TL0 0x00 -#define IC_TL1 0x01 -#define IC_TL2 0x02 -#define IC_TL3 0x03 -#define IC_TL4 0x04 -#define IC_TL5 0x05 -#define IC_TL6 0x06 -#define IC_TL7 0x07 -#define IC_RX_TL IC_TL0 -#define IC_TX_TL IC_TL0 - -/* i2c enable register definitions */ -#define IC_ENABLE_0B 0x0001 - -/* i2c status register definitions */ -#define IC_STATUS_SA 0x0040 -#define IC_STATUS_MA 0x0020 -#define IC_STATUS_RFF 0x0010 -#define IC_STATUS_RFNE 0x0008 -#define IC_STATUS_TFE 0x0004 -#define IC_STATUS_TFNF 0x0002 -#define IC_STATUS_ACT 0x0001 - -/* Speed Selection */ -#define IC_SPEED_MODE_STANDARD 1 -#define IC_SPEED_MODE_FAST 2 -#define IC_SPEED_MODE_MAX 3 - -#define I2C_MAX_SPEED 3400000 -#define I2C_FAST_SPEED 400000 -#define I2C_STANDARD_SPEED 100000 - -#endif /* __SPR_I2C_H_ */ diff --git a/include/asm-arm/arch-spear/spr_misc.h b/include/asm-arm/arch-spear/spr_misc.h deleted file mode 100644 index 8b96d9b..0000000 --- a/include/asm-arm/arch-spear/spr_misc.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SPR_MISC_H -#define _SPR_MISC_H - -struct misc_regs { - u32 auto_cfg_reg; /* 0x0 */ - u32 armdbg_ctr_reg; /* 0x4 */ - u32 pll1_cntl; /* 0x8 */ - u32 pll1_frq; /* 0xc */ - u32 pll1_mod; /* 0x10 */ - u32 pll2_cntl; /* 0x14 */ - u32 pll2_frq; /* 0x18 */ - u32 pll2_mod; /* 0x1C */ - u32 pll_ctr_reg; /* 0x20 */ - u32 amba_clk_cfg; /* 0x24 */ - u32 periph_clk_cfg; /* 0x28 */ - u32 periph1_clken; /* 0x2C */ - u32 periph2_clken; /* 0x30 */ - u32 ras_clken; /* 0x34 */ - u32 periph1_rst; /* 0x38 */ - u32 periph2_rst; /* 0x3C */ - u32 ras_rst; /* 0x40 */ - u32 prsc1_clk_cfg; /* 0x44 */ - u32 prsc2_clk_cfg; /* 0x48 */ - u32 prsc3_clk_cfg; /* 0x4C */ - u32 amem_cfg_ctrl; /* 0x50 */ - u32 port_cfg_ctrl; /* 0x54 */ - u32 reserved_1; /* 0x58 */ - u32 clcd_synth_clk; /* 0x5C */ - u32 irda_synth_clk; /* 0x60 */ - u32 uart_synth_clk; /* 0x64 */ - u32 gmac_synth_clk; /* 0x68 */ - u32 ras_synth1_clk; /* 0x6C */ - u32 ras_synth2_clk; /* 0x70 */ - u32 ras_synth3_clk; /* 0x74 */ - u32 ras_synth4_clk; /* 0x78 */ - u32 arb_icm_ml1; /* 0x7C */ - u32 arb_icm_ml2; /* 0x80 */ - u32 arb_icm_ml3; /* 0x84 */ - u32 arb_icm_ml4; /* 0x88 */ - u32 arb_icm_ml5; /* 0x8C */ - u32 arb_icm_ml6; /* 0x90 */ - u32 arb_icm_ml7; /* 0x94 */ - u32 arb_icm_ml8; /* 0x98 */ - u32 arb_icm_ml9; /* 0x9C */ - u32 dma_src_sel; /* 0xA0 */ - u32 uphy_ctr_reg; /* 0xA4 */ - u32 gmac_ctr_reg; /* 0xA8 */ - u32 port_bridge_ctrl; /* 0xAC */ - u32 reserved_2[4]; /* 0xB0--0xBC */ - u32 prc1_ilck_ctrl_reg; /* 0xC0 */ - u32 prc2_ilck_ctrl_reg; /* 0xC4 */ - u32 prc3_ilck_ctrl_reg; /* 0xC8 */ - u32 prc4_ilck_ctrl_reg; /* 0xCC */ - u32 prc1_intr_ctrl_reg; /* 0xD0 */ - u32 prc2_intr_ctrl_reg; /* 0xD4 */ - u32 prc3_intr_ctrl_reg; /* 0xD8 */ - u32 prc4_intr_ctrl_reg; /* 0xDC */ - u32 powerdown_cfg_reg; /* 0xE0 */ - u32 ddr_1v8_compensation; /* 0xE4 */ - u32 ddr_2v5_compensation; /* 0xE8 */ - u32 core_3v3_compensation; /* 0xEC */ - u32 ddr_pad; /* 0xF0 */ - u32 bist1_ctr_reg; /* 0xF4 */ - u32 bist2_ctr_reg; /* 0xF8 */ - u32 bist3_ctr_reg; /* 0xFC */ - u32 bist4_ctr_reg; /* 0x100 */ - u32 bist5_ctr_reg; /* 0x104 */ - u32 bist1_rslt_reg; /* 0x108 */ - u32 bist2_rslt_reg; /* 0x10C */ - u32 bist3_rslt_reg; /* 0x110 */ - u32 bist4_rslt_reg; /* 0x114 */ - u32 bist5_rslt_reg; /* 0x118 */ - u32 syst_error_reg; /* 0x11C */ - u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */ - u32 ras_gpp1_in; /* 0x8000 */ - u32 ras_gpp2_in; /* 0x8004 */ - u32 ras_gpp1_out; /* 0x8008 */ - u32 ras_gpp2_out; /* 0x800C */ -}; - -/* AUTO_CFG_REG value */ -#define MISC_SOCCFGMSK 0x0000003F -#define MISC_SOCCFG30 0x0000000C -#define MISC_SOCCFG31 0x0000000D -#define MISC_NANDDIS 0x00020000 - -/* PERIPH_CLK_CFG value */ -#define MISC_GPT3SYNTH 0x00000400 -#define MISC_GPT4SYNTH 0x00000800 - -/* PRSC_CLK_CFG value */ -/* - * Fout = Fin / (2^(N+1) * (M + 1)) - */ -#define MISC_PRSC_N_1 0x00001000 -#define MISC_PRSC_M_9 0x00000009 -#define MISC_PRSC_N_4 0x00004000 -#define MISC_PRSC_M_399 0x0000018F -#define MISC_PRSC_N_6 0x00006000 -#define MISC_PRSC_M_2593 0x00000A21 -#define MISC_PRSC_M_124 0x0000007C -#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9) - -/* PERIPH1_CLKEN, PERIPH1_RST value */ -#define MISC_USBDENB 0x01000000 - -#endif diff --git a/include/asm-arm/arch-spear/spr_nand.h b/include/asm-arm/arch-spear/spr_nand.h deleted file mode 100644 index 2b63dc7..0000000 --- a/include/asm-arm/arch-spear/spr_nand.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPR_NAND_H__ -#define __SPR_NAND_H__ - -struct fsmc_regs { - u32 reserved_1[0x10]; - u32 genmemctrl_pc; - u32 reserved_2; - u32 genmemctrl_comm; - u32 genmemctrl_attrib; - u32 reserved_3; - u32 genmemctrl_ecc; -}; - -/* genmemctrl_pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) - -/* genmemctrl_comm register definitions */ -#define FSMC_TSET_0 (0 << 0) -#define FSMC_TWAIT_6 (6 << 8) -#define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) - -extern int spear_nand_init(struct nand_chip *nand); -#endif diff --git a/include/asm-arm/arch-spear/spr_smi.h b/include/asm-arm/arch-spear/spr_smi.h deleted file mode 100644 index 06df745..0000000 --- a/include/asm-arm/arch-spear/spr_smi.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef SPR_SMI_H -#define SPR_SMI_H - -/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ -/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ - -#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE -#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE - -#define SMIBANK0_BASE (FLASH_START_ADDRESS) -#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) -#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) -#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) - -#define BANK0 0 -#define BANK1 1 -#define BANK2 2 -#define BANK3 3 - -struct smi_regs { - u32 smi_cr1; - u32 smi_cr2; - u32 smi_sr; - u32 smi_tr; - u32 smi_rr; -}; - -/* CONTROL REG 1 */ -#define BANK_EN 0x0000000F /* enables all banks */ -#define DSEL_TIME 0x00000060 /* Deselect time */ -#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ -#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ -#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ -#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ -#define SW_MODE 0x10000000 /* enables SW Mode */ -#define WB_MODE 0x20000000 /* Write Burst Mode */ -#define FAST_MODE 0x00008000 /* Fast Mode */ -#define HOLD1 0x00010000 - -/* CONTROL REG 2 */ -#define RD_STATUS_REG 0x00000400 /* reads status reg */ -#define WE 0x00000800 /* Write Enable */ -#define BANK0_SEL 0x00000000 /* Select Banck0 */ -#define BANK1_SEL 0x00001000 /* Select Banck1 */ -#define BANK2_SEL 0x00002000 /* Select Banck2 */ -#define BANK3_SEL 0x00003000 /* Select Banck3 */ -#define BANKSEL_SHIFT 12 -#define SEND 0x00000080 /* Send data */ -#define TX_LEN_1 0x00000001 /* data length = 1 byte */ -#define TX_LEN_2 0x00000002 /* data length = 2 byte */ -#define TX_LEN_3 0x00000003 /* data length = 3 byte */ -#define TX_LEN_4 0x00000004 /* data length = 4 byte */ -#define RX_LEN_1 0x00000010 /* data length = 1 byte */ -#define RX_LEN_2 0x00000020 /* data length = 2 byte */ -#define RX_LEN_3 0x00000030 /* data length = 3 byte */ -#define RX_LEN_4 0x00000040 /* data length = 4 byte */ -#define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ -#define WCIE 0x00000200 /* WCF Interrupt Enable */ - -/* STATUS_REG */ -#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ -#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ -#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ -#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ -#define RSR 0x00000005 /* Read Status regiser */ -#define TFF 0x00000100 /* Transfer Finished FLag */ -#define WCF 0x00000200 /* Transfer Finished FLag */ -#define ERF1 0x00000400 /* Error Flag 1 */ -#define ERF2 0x00000800 /* Error Flag 2 */ -#define WM0 0x00001000 /* WM Bank 0 */ -#define WM1 0x00002000 /* WM Bank 1 */ -#define WM2 0x00004000 /* WM Bank 2 */ -#define WM3 0x00008000 /* WM Bank 3 */ -#define WM_SHIFT 12 - -/* TR REG */ -#define READ_ID 0x0000009F /* Read Identification */ -#define BULK_ERASE 0x000000C7 /* BULK erase */ -#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ -#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ - -struct flash_dev { - u32 density; - ulong size; - ushort sector_count; -}; - -#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ -#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ -#define WMODE_TOUT 2 /* write enable timeout */ - -#endif diff --git a/include/asm-arm/arch-spear/spr_syscntl.h b/include/asm-arm/arch-spear/spr_syscntl.h deleted file mode 100644 index 3c92f09..0000000 --- a/include/asm-arm/arch-spear/spr_syscntl.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2009 - * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -struct syscntl_regs { - u32 scctrl; - u32 scsysstat; - u32 scimctrl; - u32 scimsysstat; - u32 scxtalctrl; - u32 scpllctrl; - u32 scpllfctrl; - u32 scperctrl0; - u32 scperctrl1; - u32 scperen; - u32 scperdis; - const u32 scperclken; - const u32 scperstat; -}; diff --git a/include/asm-arm/arch-spear/spr_xloader_table.h b/include/asm-arm/arch-spear/spr_xloader_table.h deleted file mode 100644 index 7e3da18..0000000 --- a/include/asm-arm/arch-spear/spr_xloader_table.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SPR_XLOADER_TABLE_H -#define _SPR_XLOADER_TABLE_H - -#define XLOADER_TABLE_VERSION_1_1 2 -#define XLOADER_TABLE_VERSION_1_2 3 - -#define XLOADER_TABLE_ADDRESS 0xD2801FF0 - -#define DDRMOBILE 1 -#define DDR2 2 - -#define REV_BA 1 -#define REV_AA 2 -#define REV_AB 3 - -struct xloader_table_1_1 { - unsigned short ddrfreq; - unsigned char ddrsize; - unsigned char ddrtype; - - unsigned char soc_rev; -} __attribute__ ((packed)); - -struct xloader_table_1_2 { - unsigned const char *version; - - unsigned short ddrfreq; - unsigned char ddrsize; - unsigned char ddrtype; - - unsigned char soc_rev; -} __attribute__ ((packed)); - -union table_contents { - struct xloader_table_1_1 table_1_1; - struct xloader_table_1_2 table_1_2; -}; - -struct xloader_table { - unsigned char table_version; - union table_contents table; -} __attribute__ ((packed)); - -#endif diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h deleted file mode 100644 index ba9e4b7..0000000 --- a/include/asm-arm/atomic.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * linux/include/asm-arm/atomic.h - * - * Copyright (c) 1996 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - * 13-04-1997 RMK Made functions atomic! - * 07-12-1997 RMK Upgraded for v2.1. - * 26-08-1998 PJB Added #ifdef __KERNEL__ - */ -#ifndef __ASM_ARM_ATOMIC_H -#define __ASM_ARM_ATOMIC_H - -#include - -#ifdef CONFIG_SMP -#error SMP not supported -#endif - -typedef struct { volatile int counter; } atomic_t; - -#define ATOMIC_INIT(i) { (i) } - -#ifdef __KERNEL__ -#include - -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) - -static inline void atomic_add(int i, volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter += i; - local_irq_restore(flags); -} - -static inline void atomic_sub(int i, volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter -= i; - local_irq_restore(flags); -} - -static inline void atomic_inc(volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter += 1; - local_irq_restore(flags); -} - -static inline void atomic_dec(volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter -= 1; - local_irq_restore(flags); -} - -static inline int atomic_dec_and_test(volatile atomic_t *v) -{ - unsigned long flags; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val -= 1; - local_irq_restore(flags); - - return val == 0; -} - -static inline int atomic_add_negative(int i, volatile atomic_t *v) -{ - unsigned long flags; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val += i; - local_irq_restore(flags); - - return val < 0; -} - -static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) -{ - unsigned long flags; - - local_irq_save(flags); - *addr &= ~mask; - local_irq_restore(flags); -} - -/* Atomic operations are already serializing on ARM */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#endif -#endif diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h deleted file mode 100644 index 270f163..0000000 --- a/include/asm-arm/bitops.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 1995, Russell King. - * Various bits and pieces copyrights include: - * Linus Torvalds (test_bit). - * - * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). - * - * Please note that the code in this file should never be included - * from user space. Many of these are not implemented in assembler - * since they would be too costly. Also, they require priviledged - * instructions (which are not available from user mode) to ensure - * that they are atomic. - */ - -#ifndef __ASM_ARM_BITOPS_H -#define __ASM_ARM_BITOPS_H - -#ifdef __KERNEL__ - -#include - -#define smp_mb__before_clear_bit() do { } while (0) -#define smp_mb__after_clear_bit() do { } while (0) - -/* - * Function prototypes to keep gcc -Wall happy. - */ -extern void set_bit(int nr, volatile void * addr); - -extern void clear_bit(int nr, volatile void * addr); - -extern void change_bit(int nr, volatile void * addr); - -static inline void __change_bit(int nr, volatile void *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - - *p ^= mask; -} - -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old = *p; - - *p = old | mask; - return (old & mask) != 0; -} - -static inline int test_and_set_bit(int nr, volatile void * addr) -{ - unsigned long flags; - int out; - - local_irq_save(flags); - out = __test_and_set_bit(nr, addr); - local_irq_restore(flags); - - return out; -} - -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old = *p; - - *p = old & ~mask; - return (old & mask) != 0; -} - -static inline int test_and_clear_bit(int nr, volatile void * addr) -{ - unsigned long flags; - int out; - - local_irq_save(flags); - out = __test_and_clear_bit(nr, addr); - local_irq_restore(flags); - - return out; -} - -extern int test_and_change_bit(int nr, volatile void * addr); - -static inline int __test_and_change_bit(int nr, volatile void *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old = *p; - - *p = old ^ mask; - return (old & mask) != 0; -} - -extern int find_first_zero_bit(void * addr, unsigned size); -extern int find_next_zero_bit(void * addr, int size, int offset); - -/* - * This routine doesn't need to be atomic. - */ -static inline int test_bit(int nr, const void * addr) -{ - return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); -} - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) -{ - int k; - - word = ~word; - k = 31; - if (word & 0x0000ffff) { k -= 16; word <<= 16; } - if (word & 0x00ff0000) { k -= 8; word <<= 8; } - if (word & 0x0f000000) { k -= 4; word <<= 4; } - if (word & 0x30000000) { k -= 2; word <<= 2; } - if (word & 0x40000000) { k -= 1; } - return k; -} - -/* - * hweightN: returns the hamming weight (i.e. the number - * of bits set) of a N-bit word - */ - -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) - -#define ext2_set_bit test_and_set_bit -#define ext2_clear_bit test_and_clear_bit -#define ext2_test_bit test_bit -#define ext2_find_first_zero_bit find_first_zero_bit -#define ext2_find_next_zero_bit find_next_zero_bit - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -#endif /* __KERNEL__ */ - -#endif /* _ARM_BITOPS_H */ diff --git a/include/asm-arm/byteorder.h b/include/asm-arm/byteorder.h deleted file mode 100644 index c3489f1..0000000 --- a/include/asm-arm/byteorder.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * linux/include/asm-arm/byteorder.h - * - * ARM Endian-ness. In little endian mode, the data bus is connected such - * that byte accesses appear as: - * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 - * and word accesses (data or instruction) appear as: - * d0...d31 - * - * When in big endian mode, byte accesses appear as: - * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 - * and word accesses (data or instruction) appear as: - * d0...d31 - */ -#ifndef __ASM_ARM_BYTEORDER_H -#define __ASM_ARM_BYTEORDER_H - - -#include - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#ifdef __ARMEB__ -#include -#else -#include -#endif - -#endif diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h deleted file mode 100644 index d0518be..0000000 --- a/include/asm-arm/cache.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -#include - -/* - * Invalidate L2 Cache using co-proc instruction - */ -static inline void invalidate_l2_cache(void) -{ - unsigned int val=0; - - asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" - : : "r" (val) : "cc"); - isb(); -} - -void l2_cache_enable(void); -void l2_cache_disable(void); - -#endif /* _ASM_CACHE_H */ diff --git a/include/asm-arm/config.h b/include/asm-arm/config.h deleted file mode 100644 index b76fd8e..0000000 --- a/include/asm-arm/config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -/* Relocation to SDRAM works on all ARM boards */ -#define CONFIG_RELOC_FIXUP_WORKS - -#endif diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h deleted file mode 100644 index 501ce0e..0000000 --- a/include/asm-arm/dma-mapping.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2007 - * Stelian Pop - * Lead Tech Design - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARM_DMA_MAPPING_H -#define __ASM_ARM_DMA_MAPPING_H - -enum dma_data_direction { - DMA_BIDIRECTIONAL = 0, - DMA_TO_DEVICE = 1, - DMA_FROM_DEVICE = 2, -}; - -static void *dma_alloc_coherent(size_t len, unsigned long *handle) -{ - *handle = (unsigned long)malloc(len); - return (void *)*handle; -} - -static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, - enum dma_data_direction dir) -{ - return (unsigned long)vaddr; -} - -static inline void dma_unmap_single(volatile void *vaddr, size_t len, - unsigned long paddr) -{ -} - -#endif /* __ASM_ARM_DMA_MAPPING_H */ diff --git a/include/asm-arm/errno.h b/include/asm-arm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/include/asm-arm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h deleted file mode 100644 index 02cfe45..0000000 --- a/include/asm-arm/global_data.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long have_console; /* serial_init() was called */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long fb_base; /* base address of frame buffer */ -#ifdef CONFIG_VFD - unsigned char vfd_type; /* display type */ -#endif -#ifdef CONFIG_FSL_ESDHC - unsigned long sdhc_clk; -#endif -#if 0 - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long bus_clk; - phys_size_t ram_size; /* RAM size */ - unsigned long reset_status; /* reset status register at boot */ -#endif - void **jt; /* jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") - -#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-arm/hardware.h b/include/asm-arm/hardware.h deleted file mode 100644 index 1fd1a5b..0000000 --- a/include/asm-arm/hardware.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * linux/include/asm-arm/hardware.h - * - * Copyright (C) 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Common hardware definitions - */ - -#ifndef __ASM_HARDWARE_H -#define __ASM_HARDWARE_H - -#include - -#endif diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h deleted file mode 100644 index 0a4b5be..0000000 --- a/include/asm-arm/io.h +++ /dev/null @@ -1,395 +0,0 @@ -/* - * linux/include/asm-arm/io.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions - */ -#ifndef __ASM_ARM_IO_H -#define __ASM_ARM_IO_H - -#ifdef __KERNEL__ - -#include -#include -#include -#if 0 /* XXX###XXX */ -#include -#endif /* XXX###XXX */ - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -#define writeb(v,a) __arch_putb(v,a) -#define writew(v,a) __arch_putw(v,a) -#define writel(v,a) __arch_putl(v,a) - -#define readb(a) __arch_getb(a) -#define readw(a) __arch_getw(a) -#define readl(a) __arch_getl(a) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) - -/* - * Clear and set bits in one shot. These macros can be used to clear and - * set multiple bits in a register using a single call. These macros can - * also be used to set a multiple-bit bit pattern using a mask, by - * specifying the mask in the 'clear' parameter and the new bit pattern - * in the 'set' parameter. - */ - -#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) -#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) - -#define out_le32(a,v) out_arch(l,le32,a,v) -#define out_le16(a,v) out_arch(w,le16,a,v) - -#define in_le32(a) in_arch(l,le32,a) -#define in_le16(a) in_arch(w,le16,a) - -#define out_be32(a,v) out_arch(l,be32,a,v) -#define out_be16(a,v) out_arch(w,be16,a,v) - -#define in_be32(a) in_arch(l,be32,a) -#define in_be16(a) in_arch(w,be16,a) - -#define out_8(a,v) __raw_writeb(v,a) -#define in_8(a) __raw_readb(a) - -#define clrbits(type, addr, clear) \ - out_##type((addr), in_##type(addr) & ~(clear)) - -#define setbits(type, addr, set) \ - out_##type((addr), in_##type(addr) | (set)) - -#define clrsetbits(type, addr, clear, set) \ - out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) - -#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) -#define setbits_be32(addr, set) setbits(be32, addr, set) -#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) - -#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) -#define setbits_le32(addr, set) setbits(le32, addr, set) -#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) - -#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) -#define setbits_be16(addr, set) setbits(be16, addr, set) -#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) - -#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) -#define setbits_le16(addr, set) setbits(le16, addr, set) -#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) - -#define clrbits_8(addr, clear) clrbits(8, addr, clear) -#define setbits_8(addr, set) setbits(8, addr, set) -#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) - -/* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include -#endif /* XXX###XXX */ - -/* - * IO port access primitives - * ------------------------- - * - * The ARM doesn't have special IO access instructions; all IO is memory - * mapped. Note that these are defined to perform little endian accesses - * only. Their primary purpose is to access PCI and ISA peripherals. - * - * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerous - * ARM documents: - * - * PCI: D0-D7 D8-D15 D16-D23 D24-D31 - * ARM: D24-D31 D16-D23 D8-D15 D0-D7 - * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * - * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. - * - * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. - */ -#ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) -#endif - -#define outb_p(val,port) outb((val),(port)) -#define outw_p(val,port) outw((val),(port)) -#define outl_p(val,port) outl((val),(port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port,from,len) outsb(port,from,len) -#define outsw_p(port,from,len) outsw(port,from,len) -#define outsl_p(port,from,len) outsl(port,from,len) -#define insb_p(port,to,len) insb(port,to,len) -#define insw_p(port,to,len) insw(port,to,len) -#define insl_p(port,to,len) insl(port,to,len) - -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off,sz) __arch_ioremap((off),(sz),0) -#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); - -/* - * String version of IO memory access ops: - */ -extern void _memcpy_fromio(void *, unsigned long, size_t); -extern void _memcpy_toio(unsigned long, const void *, size_t); -extern void _memset_io(unsigned long, int, size_t); - -extern void __readwrite_bug(const char *fn); - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) - -#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) -#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) -#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) - -#define eth_io_copy_and_sum(s,c,l,b) \ - eth_copy_and_sum((s),__mem_pci(c),(l),(b)) - -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - -#endif /* __mem_pci */ - -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) -#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) -#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_isa(b),(c),(d)) - -static inline int -isa_check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) -#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") -#define isa_writew(val,addr) __readwrite_bug("isa_writew") -#define isa_writel(val,addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io,sig,len) (0) - -#endif /* __mem_isa */ -#endif /* __KERNEL__ */ -#endif /* __ASM_ARM_IO_H */ diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h deleted file mode 100644 index 4622557..0000000 --- a/include/asm-arm/mach-types.h +++ /dev/null @@ -1,34955 +0,0 @@ -/* - * This was automagically generated from arch/arm/tools/mach-types! - * Do NOT edit - */ - -#ifndef __ASM_ARM_MACH_TYPE_H -#define __ASM_ARM_MACH_TYPE_H - -#ifndef __ASSEMBLY__ -/* The type of machine we're running on */ -extern unsigned int __machine_arch_type; -#endif - -/* see arch/arm/kernel/arch.c for a description of these */ -#define MACH_TYPE_EBSA110 0 -#define MACH_TYPE_RISCPC 1 -#define MACH_TYPE_NEXUSPCI 3 -#define MACH_TYPE_EBSA285 4 -#define MACH_TYPE_NETWINDER 5 -#define MACH_TYPE_CATS 6 -#define MACH_TYPE_TBOX 7 -#define MACH_TYPE_CO285 8 -#define MACH_TYPE_CLPS7110 9 -#define MACH_TYPE_ARCHIMEDES 10 -#define MACH_TYPE_A5K 11 -#define MACH_TYPE_ETOILE 12 -#define MACH_TYPE_LACIE_NAS 13 -#define MACH_TYPE_CLPS7500 14 -#define MACH_TYPE_SHARK 15 -#define MACH_TYPE_BRUTUS 16 -#define MACH_TYPE_PERSONAL_SERVER 17 -#define MACH_TYPE_ITSY 18 -#define MACH_TYPE_L7200 19 -#define MACH_TYPE_PLEB 20 -#define MACH_TYPE_INTEGRATOR 21 -#define MACH_TYPE_H3600 22 -#define MACH_TYPE_IXP1200 23 -#define MACH_TYPE_P720T 24 -#define MACH_TYPE_ASSABET 25 -#define MACH_TYPE_VICTOR 26 -#define MACH_TYPE_LART 27 -#define MACH_TYPE_RANGER 28 -#define MACH_TYPE_GRAPHICSCLIENT 29 -#define MACH_TYPE_XP860 30 -#define MACH_TYPE_CERF 31 -#define MACH_TYPE_NANOENGINE 32 -#define MACH_TYPE_FPIC 33 -#define MACH_TYPE_EXTENEX1 34 -#define MACH_TYPE_SHERMAN 35 -#define MACH_TYPE_ACCELENT_SA 36 -#define MACH_TYPE_ACCELENT_L7200 37 -#define MACH_TYPE_NETPORT 38 -#define MACH_TYPE_PANGOLIN 39 -#define MACH_TYPE_YOPY 40 -#define MACH_TYPE_COOLIDGE 41 -#define MACH_TYPE_HUW_WEBPANEL 42 -#define MACH_TYPE_SPOTME 43 -#define MACH_TYPE_FREEBIRD 44 -#define MACH_TYPE_TI925 45 -#define MACH_TYPE_RISCSTATION 46 -#define MACH_TYPE_CAVY 47 -#define MACH_TYPE_JORNADA720 48 -#define MACH_TYPE_OMNIMETER 49 -#define MACH_TYPE_EDB7211 50 -#define MACH_TYPE_CITYGO 51 -#define MACH_TYPE_PFS168 52 -#define MACH_TYPE_SPOT 53 -#define MACH_TYPE_FLEXANET 54 -#define MACH_TYPE_WEBPAL 55 -#define MACH_TYPE_LINPDA 56 -#define MACH_TYPE_ANAKIN 57 -#define MACH_TYPE_MVI 58 -#define MACH_TYPE_JUPITER 59 -#define MACH_TYPE_PSIONW 60 -#define MACH_TYPE_ALN 61 -#define MACH_TYPE_CAMELOT 62 -#define MACH_TYPE_GDS2200 63 -#define MACH_TYPE_PSION_SERIES7 64 -#define MACH_TYPE_XFILE 65 -#define MACH_TYPE_ACCELENT_EP9312 66 -#define MACH_TYPE_IC200 67 -#define MACH_TYPE_CREDITLART 68 -#define MACH_TYPE_HTM 69 -#define MACH_TYPE_IQ80310 70 -#define MACH_TYPE_FREEBOT 71 -#define MACH_TYPE_ENTEL 72 -#define MACH_TYPE_ENP3510 73 -#define MACH_TYPE_TRIZEPS 74 -#define MACH_TYPE_NESA 75 -#define MACH_TYPE_VENUS 76 -#define MACH_TYPE_TARDIS 77 -#define MACH_TYPE_MERCURY 78 -#define MACH_TYPE_EMPEG 79 -#define MACH_TYPE_I80200FCC 80 -#define MACH_TYPE_ITT_CPB 81 -#define MACH_TYPE_SVC 82 -#define MACH_TYPE_ALPHA2 84 -#define MACH_TYPE_ALPHA1 85 -#define MACH_TYPE_NETARM 86 -#define MACH_TYPE_SIMPAD 87 -#define MACH_TYPE_PDA1 88 -#define MACH_TYPE_LUBBOCK 89 -#define MACH_TYPE_ANIKO 90 -#define MACH_TYPE_CLEP7212 91 -#define MACH_TYPE_CS89712 92 -#define MACH_TYPE_WEARARM 93 -#define MACH_TYPE_POSSIO_PX 94 -#define MACH_TYPE_SIDEARM 95 -#define MACH_TYPE_STORK 96 -#define MACH_TYPE_SHANNON 97 -#define MACH_TYPE_ACE 98 -#define MACH_TYPE_BALLYARM 99 -#define MACH_TYPE_SIMPUTER 100 -#define MACH_TYPE_NEXTERM 101 -#define MACH_TYPE_SA1100_ELF 102 -#define MACH_TYPE_GATOR 103 -#define MACH_TYPE_GRANITE 104 -#define MACH_TYPE_CONSUS 105 -#define MACH_TYPE_AAED2000 106 -#define MACH_TYPE_CDB89712 107 -#define MACH_TYPE_GRAPHICSMASTER 108 -#define MACH_TYPE_ADSBITSY 109 -#define MACH_TYPE_PXA_IDP 110 -#define MACH_TYPE_PLCE 111 -#define MACH_TYPE_PT_SYSTEM3 112 -#define MACH_TYPE_MEDALB 113 -#define MACH_TYPE_EAGLE 114 -#define MACH_TYPE_DSC21 115 -#define MACH_TYPE_DSC24 116 -#define MACH_TYPE_TI5472 117 -#define MACH_TYPE_AUTCPU12 118 -#define MACH_TYPE_UENGINE 119 -#define MACH_TYPE_BLUESTEM 120 -#define MACH_TYPE_XINGU8 121 -#define MACH_TYPE_BUSHSTB 122 -#define MACH_TYPE_EPSILON1 123 -#define MACH_TYPE_BALLOON 124 -#define MACH_TYPE_PUPPY 125 -#define MACH_TYPE_ELROY 126 -#define MACH_TYPE_GMS720 127 -#define MACH_TYPE_S24X 128 -#define MACH_TYPE_JTEL_CLEP7312 129 -#define MACH_TYPE_CX821XX 130 -#define MACH_TYPE_EDB7312 131 -#define MACH_TYPE_BSA1110 132 -#define MACH_TYPE_POWERPIN 133 -#define MACH_TYPE_OPENARM 134 -#define MACH_TYPE_WHITECHAPEL 135 -#define MACH_TYPE_H3100 136 -#define MACH_TYPE_H3800 137 -#define MACH_TYPE_BLUE_V1 138 -#define MACH_TYPE_PXA_CERF 139 -#define MACH_TYPE_ARM7TEVB 140 -#define MACH_TYPE_D7400 141 -#define MACH_TYPE_PIRANHA 142 -#define MACH_TYPE_SBCAMELOT 143 -#define MACH_TYPE_KINGS 144 -#define MACH_TYPE_SMDK2400 145 -#define MACH_TYPE_COLLIE 146 -#define MACH_TYPE_IDR 147 -#define MACH_TYPE_BADGE4 148 -#define MACH_TYPE_WEBNET 149 -#define MACH_TYPE_D7300 150 -#define MACH_TYPE_CEP 151 -#define MACH_TYPE_FORTUNET 152 -#define MACH_TYPE_VC547X 153 -#define MACH_TYPE_FILEWALKER 154 -#define MACH_TYPE_NETGATEWAY 155 -#define MACH_TYPE_SYMBOL2800 156 -#define MACH_TYPE_SUNS 157 -#define MACH_TYPE_FRODO 158 -#define MACH_TYPE_MACH_TYTE_MS301 159 -#define MACH_TYPE_MX1ADS 160 -#define MACH_TYPE_H7201 161 -#define MACH_TYPE_H7202 162 -#define MACH_TYPE_AMICO 163 -#define MACH_TYPE_IAM 164 -#define MACH_TYPE_TT530 165 -#define MACH_TYPE_SAM2400 166 -#define MACH_TYPE_JORNADA56X 167 -#define MACH_TYPE_ACTIVE 168 -#define MACH_TYPE_IQ80321 169 -#define MACH_TYPE_WID 170 -#define MACH_TYPE_SABINAL 171 -#define MACH_TYPE_IXP425_MATACUMBE 172 -#define MACH_TYPE_MINIPRINT 173 -#define MACH_TYPE_ADM510X 174 -#define MACH_TYPE_SVS200 175 -#define MACH_TYPE_ATG_TCU 176 -#define MACH_TYPE_JORNADA820 177 -#define MACH_TYPE_S3C44B0 178 -#define MACH_TYPE_MARGIS2 179 -#define MACH_TYPE_KS8695 180 -#define MACH_TYPE_BRH 181 -#define MACH_TYPE_S3C2410 182 -#define MACH_TYPE_POSSIO_PX30 183 -#define MACH_TYPE_S3C2800 184 -#define MACH_TYPE_FLEETWOOD 185 -#define MACH_TYPE_OMAHA 186 -#define MACH_TYPE_TA7 187 -#define MACH_TYPE_NOVA 188 -#define MACH_TYPE_HMK 189 -#define MACH_TYPE_KARO 190 -#define MACH_TYPE_FESTER 191 -#define MACH_TYPE_GPI 192 -#define MACH_TYPE_SMDK2410 193 -#define MACH_TYPE_I519 194 -#define MACH_TYPE_NEXIO 195 -#define MACH_TYPE_BITBOX 196 -#define MACH_TYPE_G200 197 -#define MACH_TYPE_GILL 198 -#define MACH_TYPE_PXA_MERCURY 199 -#define MACH_TYPE_CEIVA 200 -#define MACH_TYPE_FRET 201 -#define MACH_TYPE_EMAILPHONE 202 -#define MACH_TYPE_H3900 203 -#define MACH_TYPE_PXA1 204 -#define MACH_TYPE_KOAN369 205 -#define MACH_TYPE_COGENT 206 -#define MACH_TYPE_ESL_SIMPUTER 207 -#define MACH_TYPE_ESL_SIMPUTER_CLR 208 -#define MACH_TYPE_ESL_SIMPUTER_BW 209 -#define MACH_TYPE_HHP_CRADLE 210 -#define MACH_TYPE_HE500 211 -#define MACH_TYPE_INHANDELF2 212 -#define MACH_TYPE_INHANDFTIP 213 -#define MACH_TYPE_DNP1110 214 -#define MACH_TYPE_PNP1110 215 -#define MACH_TYPE_CSB226 216 -#define MACH_TYPE_ARNOLD 217 -#define MACH_TYPE_VOICEBLUE 218 -#define MACH_TYPE_JZ8028 219 -#define MACH_TYPE_H5400 220 -#define MACH_TYPE_FORTE 221 -#define MACH_TYPE_ACAM 222 -#define MACH_TYPE_ABOX 223 -#define MACH_TYPE_ATMEL 224 -#define MACH_TYPE_SITSANG 225 -#define MACH_TYPE_CPU1110LCDNET 226 -#define MACH_TYPE_MPL_VCMA9 227 -#define MACH_TYPE_OPUS_A1 228 -#define MACH_TYPE_DAYTONA 229 -#define MACH_TYPE_KILLBEAR 230 -#define MACH_TYPE_YOHO 231 -#define MACH_TYPE_JASPER 232 -#define MACH_TYPE_DSC25 233 -#define MACH_TYPE_OMAP_INNOVATOR 234 -#define MACH_TYPE_RAMSES 235 -#define MACH_TYPE_S28X 236 -#define MACH_TYPE_MPORT3 237 -#define MACH_TYPE_PXA_EAGLE250 238 -#define MACH_TYPE_PDB 239 -#define MACH_TYPE_BLUE_2G 240 -#define MACH_TYPE_BLUEARCH 241 -#define MACH_TYPE_IXDP2400 242 -#define MACH_TYPE_IXDP2800 243 -#define MACH_TYPE_EXPLORER 244 -#define MACH_TYPE_IXDP425 245 -#define MACH_TYPE_CHIMP 246 -#define MACH_TYPE_STORK_NEST 247 -#define MACH_TYPE_STORK_EGG 248 -#define MACH_TYPE_WISMO 249 -#define MACH_TYPE_EZLINX 250 -#define MACH_TYPE_AT91RM9200 251 -#define MACH_TYPE_ADTECH_ORION 252 -#define MACH_TYPE_NEPTUNE 253 -#define MACH_TYPE_HACKKIT 254 -#define MACH_TYPE_PXA_WINS30 255 -#define MACH_TYPE_LAVINNA 256 -#define MACH_TYPE_PXA_UENGINE 257 -#define MACH_TYPE_INNOKOM 258 -#define MACH_TYPE_BMS 259 -#define MACH_TYPE_IXCDP1100 260 -#define MACH_TYPE_PRPMC1100 261 -#define MACH_TYPE_AT91RM9200DK 262 -#define MACH_TYPE_ARMSTICK 263 -#define MACH_TYPE_ARMONIE 264 -#define MACH_TYPE_MPORT1 265 -#define MACH_TYPE_S3C5410 266 -#define MACH_TYPE_ZCP320A 267 -#define MACH_TYPE_I_BOX 268 -#define MACH_TYPE_STLC1502 269 -#define MACH_TYPE_SIREN 270 -#define MACH_TYPE_GREENLAKE 271 -#define MACH_TYPE_ARGUS 272 -#define MACH_TYPE_COMBADGE 273 -#define MACH_TYPE_ROKEPXA 274 -#define MACH_TYPE_CINTEGRATOR 275 -#define MACH_TYPE_GUIDEA07 276 -#define MACH_TYPE_TAT257 277 -#define MACH_TYPE_IGP2425 278 -#define MACH_TYPE_BLUEGRAMMA 279 -#define MACH_TYPE_IPOD 280 -#define MACH_TYPE_ADSBITSYX 281 -#define MACH_TYPE_TRIZEPS2 282 -#define MACH_TYPE_VIPER 283 -#define MACH_TYPE_ADSBITSYPLUS 284 -#define MACH_TYPE_ADSAGC 285 -#define MACH_TYPE_STP7312 286 -#define MACH_TYPE_NX_PHNX 287 -#define MACH_TYPE_WEP_EP250 288 -#define MACH_TYPE_INHANDELF3 289 -#define MACH_TYPE_ADI_COYOTE 290 -#define MACH_TYPE_IYONIX 291 -#define MACH_TYPE_DAMICAM_SA1110 292 -#define MACH_TYPE_MEG03 293 -#define MACH_TYPE_PXA_WHITECHAPEL 294 -#define MACH_TYPE_NWSC 295 -#define MACH_TYPE_NWLARM 296 -#define MACH_TYPE_IXP425_MGUARD 297 -#define MACH_TYPE_PXA_NETDCU4 298 -#define MACH_TYPE_IXDP2401 299 -#define MACH_TYPE_IXDP2801 300 -#define MACH_TYPE_ZODIAC 301 -#define MACH_TYPE_ARMMODUL 302 -#define MACH_TYPE_KETOP 303 -#define MACH_TYPE_AV7200 304 -#define MACH_TYPE_ARCH_TI925 305 -#define MACH_TYPE_ACQ200 306 -#define MACH_TYPE_PT_DAFIT 307 -#define MACH_TYPE_IHBA 308 -#define MACH_TYPE_QUINQUE 309 -#define MACH_TYPE_NIMBRAONE 310 -#define MACH_TYPE_NIMBRA29X 311 -#define MACH_TYPE_NIMBRA210 312 -#define MACH_TYPE_HHP_D95XX 313 -#define MACH_TYPE_LABARM 314 -#define MACH_TYPE_M825XX 315 -#define MACH_TYPE_M7100 316 -#define MACH_TYPE_NIPC2 317 -#define MACH_TYPE_FU7202 318 -#define MACH_TYPE_ADSAGX 319 -#define MACH_TYPE_PXA_POOH 320 -#define MACH_TYPE_BANDON 321 -#define MACH_TYPE_PCM7210 322 -#define MACH_TYPE_NMS9200 323 -#define MACH_TYPE_LOGODL 324 -#define MACH_TYPE_M7140 325 -#define MACH_TYPE_KOREBOT 326 -#define MACH_TYPE_IQ31244 327 -#define MACH_TYPE_KOAN393 328 -#define MACH_TYPE_INHANDFTIP3 329 -#define MACH_TYPE_GONZO 330 -#define MACH_TYPE_BAST 331 -#define MACH_TYPE_SCANPASS 332 -#define MACH_TYPE_EP7312_POOH 333 -#define MACH_TYPE_TA7S 334 -#define MACH_TYPE_TA7V 335 -#define MACH_TYPE_ICARUS 336 -#define MACH_TYPE_H1900 337 -#define MACH_TYPE_GEMINI 338 -#define MACH_TYPE_AXIM 339 -#define MACH_TYPE_AUDIOTRON 340 -#define MACH_TYPE_H2200 341 -#define MACH_TYPE_LOOX600 342 -#define MACH_TYPE_NIOP 343 -#define MACH_TYPE_DM310 344 -#define MACH_TYPE_SEEDPXA_C2 345 -#define MACH_TYPE_IXP4XX_MGUARD_PCI 346 -#define MACH_TYPE_H1940 347 -#define MACH_TYPE_SCORPIO 348 -#define MACH_TYPE_VIVA 349 -#define MACH_TYPE_PXA_XCARD 350 -#define MACH_TYPE_CSB335 351 -#define MACH_TYPE_IXRD425 352 -#define MACH_TYPE_IQ80315 353 -#define MACH_TYPE_NMP7312 354 -#define MACH_TYPE_CX861XX 355 -#define MACH_TYPE_ENP2611 356 -#define MACH_TYPE_XDA 357 -#define MACH_TYPE_CSIR_IMS 358 -#define MACH_TYPE_IXP421_DNAEETH 359 -#define MACH_TYPE_POCKETSERV9200 360 -#define MACH_TYPE_TOTO 361 -#define MACH_TYPE_S3C2440 362 -#define MACH_TYPE_KS8695P 363 -#define MACH_TYPE_SE4000 364 -#define MACH_TYPE_QUADRICEPS 365 -#define MACH_TYPE_BRONCO 366 -#define MACH_TYPE_ESL_WIRELESS_TAB 367 -#define MACH_TYPE_ESL_SOFCOMP 368 -#define MACH_TYPE_S5C7375 369 -#define MACH_TYPE_SPEARHEAD 370 -#define MACH_TYPE_PANTERA 371 -#define MACH_TYPE_PRAYOGLITE 372 -#define MACH_TYPE_GUMSTIX 373 -#define MACH_TYPE_RCUBE 374 -#define MACH_TYPE_REA_OLV 375 -#define MACH_TYPE_PXA_IPHONE 376 -#define MACH_TYPE_S3C3410 377 -#define MACH_TYPE_ESPD_4510B 378 -#define MACH_TYPE_MP1X 379 -#define MACH_TYPE_AT91RM9200TB 380 -#define MACH_TYPE_ADSVGX 381 -#define MACH_TYPE_OMAP_H2 382 -#define MACH_TYPE_PELEE 383 -#define MACH_TYPE_E740 384 -#define MACH_TYPE_IQ80331 385 -#define MACH_TYPE_VERSATILE_PB 387 -#define MACH_TYPE_KEV7A400 388 -#define MACH_TYPE_LPD7A400 389 -#define MACH_TYPE_LPD7A404 390 -#define MACH_TYPE_FUJITSU_CAMELOT 391 -#define MACH_TYPE_JANUS2M 392 -#define MACH_TYPE_EMBTF 393 -#define MACH_TYPE_HPM 394 -#define MACH_TYPE_SMDK2410TK 395 -#define MACH_TYPE_SMDK2410AJ 396 -#define MACH_TYPE_STREETRACER 397 -#define MACH_TYPE_EFRAME 398 -#define MACH_TYPE_CSB337 399 -#define MACH_TYPE_PXA_LARK 400 -#define MACH_TYPE_PNP2110 401 -#define MACH_TYPE_TCC72X 402 -#define MACH_TYPE_ALTAIR 403 -#define MACH_TYPE_KC3 404 -#define MACH_TYPE_SINTEFTD 405 -#define MACH_TYPE_MAINSTONE 406 -#define MACH_TYPE_ADAY4X 407 -#define MACH_TYPE_LITE300 408 -#define MACH_TYPE_S5C7376 409 -#define MACH_TYPE_MT02 410 -#define MACH_TYPE_MPORT3S 411 -#define MACH_TYPE_RA_ALPHA 412 -#define MACH_TYPE_XCEP 413 -#define MACH_TYPE_ARCOM_VULCAN 414 -#define MACH_TYPE_STARGATE 415 -#define MACH_TYPE_ARMADILLOJ 416 -#define MACH_TYPE_ELROY_JACK 417 -#define MACH_TYPE_BACKEND 418 -#define MACH_TYPE_S5LINBOX 419 -#define MACH_TYPE_NOMADIK 420 -#define MACH_TYPE_IA_CPU_9200 421 -#define MACH_TYPE_AT91_BJA1 422 -#define MACH_TYPE_CORGI 423 -#define MACH_TYPE_POODLE 424 -#define MACH_TYPE_TEN 425 -#define MACH_TYPE_ROVERP5P 426 -#define MACH_TYPE_SC2700 427 -#define MACH_TYPE_EX_EAGLE 428 -#define MACH_TYPE_NX_PXA12 429 -#define MACH_TYPE_NX_PXA5 430 -#define MACH_TYPE_BLACKBOARD2 431 -#define MACH_TYPE_I819 432 -#define MACH_TYPE_IXMB995E 433 -#define MACH_TYPE_SKYRIDER 434 -#define MACH_TYPE_SKYHAWK 435 -#define MACH_TYPE_ENTERPRISE 436 -#define MACH_TYPE_DEP2410 437 -#define MACH_TYPE_ARMCORE 438 -#define MACH_TYPE_HOBBIT 439 -#define MACH_TYPE_H7210 440 -#define MACH_TYPE_PXA_NETDCU5 441 -#define MACH_TYPE_ACC 442 -#define MACH_TYPE_ESL_SARVA 443 -#define MACH_TYPE_XM250 444 -#define MACH_TYPE_T6TC1XB 445 -#define MACH_TYPE_ESS710 446 -#define MACH_TYPE_MX31ADS 447 -#define MACH_TYPE_HIMALAYA 448 -#define MACH_TYPE_BOLFENK 449 -#define MACH_TYPE_AT91RM9200KR 450 -#define MACH_TYPE_EDB9312 451 -#define MACH_TYPE_OMAP_GENERIC 452 -#define MACH_TYPE_AXIMX3 453 -#define MACH_TYPE_EB67XDIP 454 -#define MACH_TYPE_WEBTXS 455 -#define MACH_TYPE_HAWK 456 -#define MACH_TYPE_CCAT91SBC001 457 -#define MACH_TYPE_EXPRESSO 458 -#define MACH_TYPE_H4000 459 -#define MACH_TYPE_DINO 460 -#define MACH_TYPE_ML675K 461 -#define MACH_TYPE_EDB9301 462 -#define MACH_TYPE_EDB9315 463 -#define MACH_TYPE_RECIVA_TT 464 -#define MACH_TYPE_CSTCB01 465 -#define MACH_TYPE_CSTCB1 466 -#define MACH_TYPE_SHADWELL 467 -#define MACH_TYPE_GOEPEL263 468 -#define MACH_TYPE_ACQ100 469 -#define MACH_TYPE_MX1FS2 470 -#define MACH_TYPE_HIPTOP_G1 471 -#define MACH_TYPE_SPARKY 472 -#define MACH_TYPE_NS9750 473 -#define MACH_TYPE_PHOENIX 474 -#define MACH_TYPE_VR1000 475 -#define MACH_TYPE_DEISTERPXA 476 -#define MACH_TYPE_BCM1160 477 -#define MACH_TYPE_PCM022 478 -#define MACH_TYPE_ADSGCX 479 -#define MACH_TYPE_DREADNAUGHT 480 -#define MACH_TYPE_DM320 481 -#define MACH_TYPE_MARKOV 482 -#define MACH_TYPE_COS7A400 483 -#define MACH_TYPE_MILANO 484 -#define MACH_TYPE_UE9328 485 -#define MACH_TYPE_UEX255 486 -#define MACH_TYPE_UE2410 487 -#define MACH_TYPE_A620 488 -#define MACH_TYPE_OCELOT 489 -#define MACH_TYPE_CHEETAH 490 -#define MACH_TYPE_OMAP_PERSEUS2 491 -#define MACH_TYPE_ZVUE 492 -#define MACH_TYPE_ROVERP1 493 -#define MACH_TYPE_ASIDIAL2 494 -#define MACH_TYPE_S3C24A0 495 -#define MACH_TYPE_E800 496 -#define MACH_TYPE_E750 497 -#define MACH_TYPE_S3C5500 498 -#define MACH_TYPE_SMDK5500 499 -#define MACH_TYPE_SIGNALSYNC 500 -#define MACH_TYPE_NBC 501 -#define MACH_TYPE_KODIAK 502 -#define MACH_TYPE_NETBOOKPRO 503 -#define MACH_TYPE_HW90200 504 -#define MACH_TYPE_CONDOR 505 -#define MACH_TYPE_CUP 506 -#define MACH_TYPE_KITE 507 -#define MACH_TYPE_SCB9328 508 -#define MACH_TYPE_OMAP_H3 509 -#define MACH_TYPE_OMAP_H4 510 -#define MACH_TYPE_N10 511 -#define MACH_TYPE_MONTAJADE 512 -#define MACH_TYPE_SG560 513 -#define MACH_TYPE_DP1000 514 -#define MACH_TYPE_OMAP_OSK 515 -#define MACH_TYPE_RG100V3 516 -#define MACH_TYPE_MX2ADS 517 -#define MACH_TYPE_PXA_KILO 518 -#define MACH_TYPE_IXP4XX_EAGLE 519 -#define MACH_TYPE_TOSA 520 -#define MACH_TYPE_MB2520F 521 -#define MACH_TYPE_EMC1000 522 -#define MACH_TYPE_TIDSC25 523 -#define MACH_TYPE_AKCPMXL 524 -#define MACH_TYPE_AV3XX 525 -#define MACH_TYPE_AVILA 526 -#define MACH_TYPE_PXA_MPM10 527 -#define MACH_TYPE_PXA_KYANITE 528 -#define MACH_TYPE_SGOLD 529 -#define MACH_TYPE_OSCAR 530 -#define MACH_TYPE_EPXA4USB2 531 -#define MACH_TYPE_XSENGINE 532 -#define MACH_TYPE_IP600 533 -#define MACH_TYPE_MCAN2 534 -#define MACH_TYPE_DDI_BLUERIDGE 535 -#define MACH_TYPE_SKYMINDER 536 -#define MACH_TYPE_LPD79520 537 -#define MACH_TYPE_EDB9302 538 -#define MACH_TYPE_HW90340 539 -#define MACH_TYPE_CIP_BOX 540 -#define MACH_TYPE_IVPN 541 -#define MACH_TYPE_RSOC2 542 -#define MACH_TYPE_HUSKY 543 -#define MACH_TYPE_BOXER 544 -#define MACH_TYPE_SHEPHERD 545 -#define MACH_TYPE_AML42800AA 546 -#define MACH_TYPE_LPC2294 548 -#define MACH_TYPE_SWITCHGRASS 549 -#define MACH_TYPE_ENS_CMU 550 -#define MACH_TYPE_MM6_SDB 551 -#define MACH_TYPE_SATURN 552 -#define MACH_TYPE_I30030EVB 553 -#define MACH_TYPE_MXC27530EVB 554 -#define MACH_TYPE_SMDK2800 555 -#define MACH_TYPE_MTWILSON 556 -#define MACH_TYPE_ZITI 557 -#define MACH_TYPE_GRANDFATHER 558 -#define MACH_TYPE_TENGINE 559 -#define MACH_TYPE_S3C2460 560 -#define MACH_TYPE_PDM 561 -#define MACH_TYPE_H4700 562 -#define MACH_TYPE_H6300 563 -#define MACH_TYPE_RZ1700 564 -#define MACH_TYPE_A716 565 -#define MACH_TYPE_ESTK2440A 566 -#define MACH_TYPE_ATWIXP425 567 -#define MACH_TYPE_CSB336 568 -#define MACH_TYPE_RIRM2 569 -#define MACH_TYPE_CX23518 570 -#define MACH_TYPE_CX2351X 571 -#define MACH_TYPE_COMPUTIME 572 -#define MACH_TYPE_IZARUS 573 -#define MACH_TYPE_RTS 574 -#define MACH_TYPE_SE5100 575 -#define MACH_TYPE_S3C2510 576 -#define MACH_TYPE_CSB437TL 577 -#define MACH_TYPE_SLAUSON 578 -#define MACH_TYPE_PEARLRIVER 579 -#define MACH_TYPE_TDC_P210 580 -#define MACH_TYPE_SG580 581 -#define MACH_TYPE_WRSBCARM7 582 -#define MACH_TYPE_IPD 583 -#define MACH_TYPE_PXA_DNP2110 584 -#define MACH_TYPE_XAENIAX 585 -#define MACH_TYPE_SOMN4250 586 -#define MACH_TYPE_PLEB2 587 -#define MACH_TYPE_CORNWALLIS 588 -#define MACH_TYPE_GURNEY_DRV 589 -#define MACH_TYPE_CHAFFEE 590 -#define MACH_TYPE_RMS101 591 -#define MACH_TYPE_RX3715 592 -#define MACH_TYPE_SWIFT 593 -#define MACH_TYPE_ROVERP7 594 -#define MACH_TYPE_PR818S 595 -#define MACH_TYPE_TRXPRO 596 -#define MACH_TYPE_NSLU2 597 -#define MACH_TYPE_E400 598 -#define MACH_TYPE_TRAB 599 -#define MACH_TYPE_CMC_PU2 600 -#define MACH_TYPE_FULCRUM 601 -#define MACH_TYPE_NETGATE42X 602 -#define MACH_TYPE_STR710 603 -#define MACH_TYPE_IXDPG425 604 -#define MACH_TYPE_TOMTOMGO 605 -#define MACH_TYPE_VERSATILE_AB 606 -#define MACH_TYPE_EDB9307 607 -#define MACH_TYPE_SG565 608 -#define MACH_TYPE_LPD79524 609 -#define MACH_TYPE_LPD79525 610 -#define MACH_TYPE_RMS100 611 -#define MACH_TYPE_KB9200 612 -#define MACH_TYPE_SX1 613 -#define MACH_TYPE_HMS39C7092 614 -#define MACH_TYPE_ARMADILLO 615 -#define MACH_TYPE_IPCU 616 -#define MACH_TYPE_LOOX720 617 -#define MACH_TYPE_IXDP465 618 -#define MACH_TYPE_IXDP2351 619 -#define MACH_TYPE_ADSVIX 620 -#define MACH_TYPE_DM270 621 -#define MACH_TYPE_SOCLTPLUS 622 -#define MACH_TYPE_ECIA 623 -#define MACH_TYPE_CM4008 624 -#define MACH_TYPE_P2001 625 -#define MACH_TYPE_TWISTER 626 -#define MACH_TYPE_MUDSHARK 627 -#define MACH_TYPE_HB2 628 -#define MACH_TYPE_IQ80332 629 -#define MACH_TYPE_SENDT 630 -#define MACH_TYPE_MX2JAZZ 631 -#define MACH_TYPE_MULTIIO 632 -#define MACH_TYPE_HRDISPLAY 633 -#define MACH_TYPE_MXC27530ADS 634 -#define MACH_TYPE_TRIZEPS3 635 -#define MACH_TYPE_ZEFEERDZA 636 -#define MACH_TYPE_ZEFEERDZB 637 -#define MACH_TYPE_ZEFEERDZG 638 -#define MACH_TYPE_ZEFEERDZN 639 -#define MACH_TYPE_ZEFEERDZQ 640 -#define MACH_TYPE_GTWX5715 641 -#define MACH_TYPE_ASTRO_JACK 643 -#define MACH_TYPE_TIP03 644 -#define MACH_TYPE_A9200EC 645 -#define MACH_TYPE_PNX0105 646 -#define MACH_TYPE_ADCPOECPU 647 -#define MACH_TYPE_CSB637 648 -#define MACH_TYPE_MB9200 650 -#define MACH_TYPE_KULUN 651 -#define MACH_TYPE_SNAPPER 652 -#define MACH_TYPE_OPTIMA 653 -#define MACH_TYPE_DLHSBC 654 -#define MACH_TYPE_X30 655 -#define MACH_TYPE_N30 656 -#define MACH_TYPE_MANGA_KS8695 657 -#define MACH_TYPE_AJAX 658 -#define MACH_TYPE_NEC_MP900 659 -#define MACH_TYPE_VVTK1000 661 -#define MACH_TYPE_KAFA 662 -#define MACH_TYPE_VVTK3000 663 -#define MACH_TYPE_PIMX1 664 -#define MACH_TYPE_OLLIE 665 -#define MACH_TYPE_SKYMAX 666 -#define MACH_TYPE_JAZZ 667 -#define MACH_TYPE_TEL_T3 668 -#define MACH_TYPE_AISINO_FCR255 669 -#define MACH_TYPE_BTWEB 670 -#define MACH_TYPE_DBG_LH79520 671 -#define MACH_TYPE_CM41XX 672 -#define MACH_TYPE_TS72XX 673 -#define MACH_TYPE_NGGPXA 674 -#define MACH_TYPE_CSB535 675 -#define MACH_TYPE_CSB536 676 -#define MACH_TYPE_PXA_TRAKPOD 677 -#define MACH_TYPE_PRAXIS 678 -#define MACH_TYPE_LH75411 679 -#define MACH_TYPE_OTOM 680 -#define MACH_TYPE_NEXCODER_2440 681 -#define MACH_TYPE_LOOX410 682 -#define MACH_TYPE_WESTLAKE 683 -#define MACH_TYPE_NSB 684 -#define MACH_TYPE_ESL_SARVA_STN 685 -#define MACH_TYPE_ESL_SARVA_TFT 686 -#define MACH_TYPE_ESL_SARVA_IAD 687 -#define MACH_TYPE_ESL_SARVA_ACC 688 -#define MACH_TYPE_TYPHOON 689 -#define MACH_TYPE_CNAV 690 -#define MACH_TYPE_A730 691 -#define MACH_TYPE_NETSTAR 692 -#define MACH_TYPE_PHASEFALE_SUPERCON 693 -#define MACH_TYPE_SHIVA1100 694 -#define MACH_TYPE_ETEXSC 695 -#define MACH_TYPE_IXDPG465 696 -#define MACH_TYPE_A9M2410 697 -#define MACH_TYPE_A9M2440 698 -#define MACH_TYPE_A9M9750 699 -#define MACH_TYPE_A9M9360 700 -#define MACH_TYPE_UNC90 701 -#define MACH_TYPE_ECO920 702 -#define MACH_TYPE_SATVIEW 703 -#define MACH_TYPE_ROADRUNNER 704 -#define MACH_TYPE_AT91RM9200EK 705 -#define MACH_TYPE_GP32 706 -#define MACH_TYPE_GEM 707 -#define MACH_TYPE_I858 708 -#define MACH_TYPE_HX2750 709 -#define MACH_TYPE_MXC91131EVB 710 -#define MACH_TYPE_P700 711 -#define MACH_TYPE_CPE 712 -#define MACH_TYPE_SPITZ 713 -#define MACH_TYPE_NIMBRA340 714 -#define MACH_TYPE_LPC22XX 715 -#define MACH_TYPE_COMET3 716 -#define MACH_TYPE_COMET4 717 -#define MACH_TYPE_CSB625 718 -#define MACH_TYPE_FORTUNET2 719 -#define MACH_TYPE_S5H2200 720 -#define MACH_TYPE_OPTORM920 721 -#define MACH_TYPE_ADSBITSYXB 722 -#define MACH_TYPE_ADSSPHERE 723 -#define MACH_TYPE_ADSPORTAL 724 -#define MACH_TYPE_LN2410SBC 725 -#define MACH_TYPE_CB3RUFC 726 -#define MACH_TYPE_MP2USB 727 -#define MACH_TYPE_NTNP425C 728 -#define MACH_TYPE_COLIBRI 729 -#define MACH_TYPE_PCM7220 730 -#define MACH_TYPE_GATEWAY7001 731 -#define MACH_TYPE_PCM027 732 -#define MACH_TYPE_CMPXA 733 -#define MACH_TYPE_ANUBIS 734 -#define MACH_TYPE_ITE8152 735 -#define MACH_TYPE_LPC3XXX 736 -#define MACH_TYPE_PUPPETEER 737 -#define MACH_TYPE_E570 739 -#define MACH_TYPE_X50 740 -#define MACH_TYPE_RECON 741 -#define MACH_TYPE_XBOARDGP8 742 -#define MACH_TYPE_FPIC2 743 -#define MACH_TYPE_AKITA 744 -#define MACH_TYPE_A81 745 -#define MACH_TYPE_SVM_SC25X 746 -#define MACH_TYPE_VADATECH020 747 -#define MACH_TYPE_TLI 748 -#define MACH_TYPE_EDB9315LC 749 -#define MACH_TYPE_PASSEC 750 -#define MACH_TYPE_DS_TIGER 751 -#define MACH_TYPE_E310 752 -#define MACH_TYPE_E330 753 -#define MACH_TYPE_RT3000 754 -#define MACH_TYPE_NOKIA770 755 -#define MACH_TYPE_PNX0106 756 -#define MACH_TYPE_HX21XX 757 -#define MACH_TYPE_FARADAY 758 -#define MACH_TYPE_SBC9312 759 -#define MACH_TYPE_BATMAN 760 -#define MACH_TYPE_JPD201 761 -#define MACH_TYPE_MIPSA 762 -#define MACH_TYPE_KACOM 763 -#define MACH_TYPE_SWARCOCPU 764 -#define MACH_TYPE_SWARCODSL 765 -#define MACH_TYPE_BLUEANGEL 766 -#define MACH_TYPE_HAIRYGRAMA 767 -#define MACH_TYPE_BANFF 768 -#define MACH_TYPE_CARMEVA 769 -#define MACH_TYPE_SAM255 770 -#define MACH_TYPE_PPM10 771 -#define MACH_TYPE_EDB9315A 772 -#define MACH_TYPE_SUNSET 773 -#define MACH_TYPE_STARGATE2 774 -#define MACH_TYPE_INTELMOTE2 775 -#define MACH_TYPE_TRIZEPS4 776 -#define MACH_TYPE_MAINSTONE2 777 -#define MACH_TYPE_EZ_IXP42X 778 -#define MACH_TYPE_TAPWAVE_ZODIAC 779 -#define MACH_TYPE_UNIVERSALMETER 780 -#define MACH_TYPE_HICOARM9 781 -#define MACH_TYPE_PNX4008 782 -#define MACH_TYPE_KWS6000 783 -#define MACH_TYPE_PORTUX920T 784 -#define MACH_TYPE_EZ_X5 785 -#define MACH_TYPE_OMAP_RUDOLPH 786 -#define MACH_TYPE_CPUAT91 787 -#define MACH_TYPE_REA9200 788 -#define MACH_TYPE_ACTS_PUNE_SA1110 789 -#define MACH_TYPE_IXP425 790 -#define MACH_TYPE_I30030ADS 791 -#define MACH_TYPE_PERCH 792 -#define MACH_TYPE_EIS05R1 793 -#define MACH_TYPE_PEPPERPAD 794 -#define MACH_TYPE_SB3010 795 -#define MACH_TYPE_RM9200 796 -#define MACH_TYPE_DMA03 797 -#define MACH_TYPE_ROAD_S101 798 -#define MACH_TYPE_IQ81340SC 799 -#define MACH_TYPE_IQ_NEXTGEN_B 800 -#define MACH_TYPE_IQ81340MC 801 -#define MACH_TYPE_IQ_NEXTGEN_D 802 -#define MACH_TYPE_IQ_NEXTGEN_E 803 -#define MACH_TYPE_MALLOW_AT91 804 -#define MACH_TYPE_CYBERTRACKER_I 805 -#define MACH_TYPE_GESBC931X 806 -#define MACH_TYPE_CENTIPAD 807 -#define MACH_TYPE_ARMSOC 808 -#define MACH_TYPE_SE4200 809 -#define MACH_TYPE_EMS197A 810 -#define MACH_TYPE_MICRO9 811 -#define MACH_TYPE_MICRO9L 812 -#define MACH_TYPE_UC5471DSP 813 -#define MACH_TYPE_SJ5471ENG 814 -#define MACH_TYPE_CMPXA26X 815 -#define MACH_TYPE_NC 816 -#define MACH_TYPE_OMAP_PALMTE 817 -#define MACH_TYPE_AJAX52X 818 -#define MACH_TYPE_SIRIUSTAR 819 -#define MACH_TYPE_IODATA_HDLG 820 -#define MACH_TYPE_AT91RM9200UTL 821 -#define MACH_TYPE_BIOSAFE 822 -#define MACH_TYPE_MP1000 823 -#define MACH_TYPE_PARSY 824 -#define MACH_TYPE_CCXP 825 -#define MACH_TYPE_OMAP_GSAMPLE 826 -#define MACH_TYPE_REALVIEW_EB 827 -#define MACH_TYPE_SAMOA 828 -#define MACH_TYPE_PALMT3 829 -#define MACH_TYPE_I878 830 -#define MACH_TYPE_BORZOI 831 -#define MACH_TYPE_GECKO 832 -#define MACH_TYPE_DS101 833 -#define MACH_TYPE_OMAP_PALMTT2 834 -#define MACH_TYPE_PALMLD 835 -#define MACH_TYPE_CC9C 836 -#define MACH_TYPE_SBC1670 837 -#define MACH_TYPE_IXDP28X5 838 -#define MACH_TYPE_OMAP_PALMTT 839 -#define MACH_TYPE_ML696K 840 -#define MACH_TYPE_ARCOM_ZEUS 841 -#define MACH_TYPE_OSIRIS 842 -#define MACH_TYPE_MAESTRO 843 -#define MACH_TYPE_PALMTE2 844 -#define MACH_TYPE_IXBBM 845 -#define MACH_TYPE_MX27ADS 846 -#define MACH_TYPE_AX8004 847 -#define MACH_TYPE_AT91SAM9261EK 848 -#define MACH_TYPE_LOFT 849 -#define MACH_TYPE_MAGPIE 850 -#define MACH_TYPE_MX21ADS 851 -#define MACH_TYPE_MB87M3400 852 -#define MACH_TYPE_MGUARD_DELTA 853 -#define MACH_TYPE_DAVINCI_DVDP 854 -#define MACH_TYPE_HTCUNIVERSAL 855 -#define MACH_TYPE_TPAD 856 -#define MACH_TYPE_ROVERP3 857 -#define MACH_TYPE_JORNADA928 858 -#define MACH_TYPE_MV88FXX81 859 -#define MACH_TYPE_STMP36XX 860 -#define MACH_TYPE_SXNI79524 861 -#define MACH_TYPE_AMS_DELTA 862 -#define MACH_TYPE_URANIUM 863 -#define MACH_TYPE_UCON 864 -#define MACH_TYPE_NAS100D 865 -#define MACH_TYPE_L083_1000 866 -#define MACH_TYPE_EZX 867 -#define MACH_TYPE_PNX5220 868 -#define MACH_TYPE_BUTTE 869 -#define MACH_TYPE_SRM2 870 -#define MACH_TYPE_DSBR 871 -#define MACH_TYPE_CRYSTALBALL 872 -#define MACH_TYPE_TINYPXA27X 873 -#define MACH_TYPE_HERBIE 874 -#define MACH_TYPE_MAGICIAN 875 -#define MACH_TYPE_CM4002 876 -#define MACH_TYPE_B4 877 -#define MACH_TYPE_MAUI 878 -#define MACH_TYPE_CYBERTRACKER_G 879 -#define MACH_TYPE_NXDKN 880 -#define MACH_TYPE_MIO8390 881 -#define MACH_TYPE_OMI_BOARD 882 -#define MACH_TYPE_MX21CIV 883 -#define MACH_TYPE_MAHI_CDAC 884 -#define MACH_TYPE_PALMTX 885 -#define MACH_TYPE_S3C2413 887 -#define MACH_TYPE_SAMSYS_EP0 888 -#define MACH_TYPE_WG302V1 889 -#define MACH_TYPE_WG302V2 890 -#define MACH_TYPE_EB42X 891 -#define MACH_TYPE_IQ331ES 892 -#define MACH_TYPE_COSYDSP 893 -#define MACH_TYPE_UPLAT7D 894 -#define MACH_TYPE_PTDAVINCI 895 -#define MACH_TYPE_MBUS 896 -#define MACH_TYPE_NADIA2VB 897 -#define MACH_TYPE_R1000 898 -#define MACH_TYPE_HW90250 899 -#define MACH_TYPE_OMAP_2430SDP 900 -#define MACH_TYPE_DAVINCI_EVM 901 -#define MACH_TYPE_OMAP_TORNADO 902 -#define MACH_TYPE_OLOCREEK 903 -#define MACH_TYPE_PALMZ72 904 -#define MACH_TYPE_NXDB500 905 -#define MACH_TYPE_APF9328 906 -#define MACH_TYPE_OMAP_WIPOQ 907 -#define MACH_TYPE_OMAP_TWIP 908 -#define MACH_TYPE_TREO650 909 -#define MACH_TYPE_ACUMEN 910 -#define MACH_TYPE_XP100 911 -#define MACH_TYPE_FS2410 912 -#define MACH_TYPE_PXA270_CERF 913 -#define MACH_TYPE_SQ2FTLPALM 914 -#define MACH_TYPE_BSEMSERVER 915 -#define MACH_TYPE_NETCLIENT 916 -#define MACH_TYPE_PALMT5 917 -#define MACH_TYPE_PALMTC 918 -#define MACH_TYPE_OMAP_APOLLON 919 -#define MACH_TYPE_MXC30030EVB 920 -#define MACH_TYPE_REA_2D 921 -#define MACH_TYPE_TI3E524 922 -#define MACH_TYPE_ATEB9200 923 -#define MACH_TYPE_AUCKLAND 924 -#define MACH_TYPE_AK3320M 925 -#define MACH_TYPE_DURAMAX 926 -#define MACH_TYPE_N35 927 -#define MACH_TYPE_PRONGHORN 928 -#define MACH_TYPE_FUNDY 929 -#define MACH_TYPE_LOGICPD_PXA270 930 -#define MACH_TYPE_CPU777 931 -#define MACH_TYPE_SIMICON9201 932 -#define MACH_TYPE_LEAP2_HPM 933 -#define MACH_TYPE_CM922TXA10 934 -#define MACH_TYPE_PXA 935 -#define MACH_TYPE_SANDGATE2 936 -#define MACH_TYPE_SANDGATE2G 937 -#define MACH_TYPE_SANDGATE2P 938 -#define MACH_TYPE_FRED_JACK 939 -#define MACH_TYPE_TTG_COLOR1 940 -#define MACH_TYPE_NXEB500HMI 941 -#define MACH_TYPE_NETDCU8 942 -#define MACH_TYPE_NG_FVX538 944 -#define MACH_TYPE_NG_FVS338 945 -#define MACH_TYPE_PNX4103 946 -#define MACH_TYPE_HESDB 947 -#define MACH_TYPE_XSILO 948 -#define MACH_TYPE_ESPRESSO 949 -#define MACH_TYPE_EMLC 950 -#define MACH_TYPE_SISTERON 951 -#define MACH_TYPE_RX1950 952 -#define MACH_TYPE_TSC_VENUS 953 -#define MACH_TYPE_DS101J 954 -#define MACH_TYPE_MXC30030ADS 955 -#define MACH_TYPE_FUJITSU_WIMAXSOC 956 -#define MACH_TYPE_DUALPCMODEM 957 -#define MACH_TYPE_GESBC9312 958 -#define MACH_TYPE_HTCAPACHE 959 -#define MACH_TYPE_IXDP435 960 -#define MACH_TYPE_CATPROVT100 961 -#define MACH_TYPE_PICOTUX1XX 962 -#define MACH_TYPE_PICOTUX2XX 963 -#define MACH_TYPE_DSMG600 964 -#define MACH_TYPE_EMPC2 965 -#define MACH_TYPE_VENTURA 966 -#define MACH_TYPE_PHIDGET_SBC 967 -#define MACH_TYPE_IJ3K 968 -#define MACH_TYPE_PISGAH 969 -#define MACH_TYPE_OMAP_FSAMPLE 970 -#define MACH_TYPE_SG720 971 -#define MACH_TYPE_REDFOX 972 -#define MACH_TYPE_MYSH_EP9315_1 973 -#define MACH_TYPE_TPF106 974 -#define MACH_TYPE_AT91RM9200KG 975 -#define MACH_TYPE_SLEDB 976 -#define MACH_TYPE_ONTRACK 977 -#define MACH_TYPE_PM1200 978 -#define MACH_TYPE_ESS24XXX 979 -#define MACH_TYPE_COREMP7 980 -#define MACH_TYPE_NEXCODER_6446 981 -#define MACH_TYPE_STVC8380 982 -#define MACH_TYPE_TEKLYNX 983 -#define MACH_TYPE_CARBONADO 984 -#define MACH_TYPE_SYSMOS_MP730 985 -#define MACH_TYPE_SNAPPER_CL15 986 -#define MACH_TYPE_PGIGIM 987 -#define MACH_TYPE_PTX9160P2 988 -#define MACH_TYPE_DCORE1 989 -#define MACH_TYPE_VICTORPXA 990 -#define MACH_TYPE_MX2DTB 991 -#define MACH_TYPE_PXA_IREX_ER0100 992 -#define MACH_TYPE_OMAP_PALMZ71 993 -#define MACH_TYPE_BARTEC_DEG 994 -#define MACH_TYPE_HW50251 995 -#define MACH_TYPE_IBOX 996 -#define MACH_TYPE_ATLASLH7A404 997 -#define MACH_TYPE_PT2026 998 -#define MACH_TYPE_HTCALPINE 999 -#define MACH_TYPE_BARTEC_VTU 1000 -#define MACH_TYPE_VCOREII 1001 -#define MACH_TYPE_PDNB3 1002 -#define MACH_TYPE_HTCBEETLES 1003 -#define MACH_TYPE_S3C6400 1004 -#define MACH_TYPE_S3C2443 1005 -#define MACH_TYPE_OMAP_LDK 1006 -#define MACH_TYPE_SMDK2460 1007 -#define MACH_TYPE_SMDK2440 1008 -#define MACH_TYPE_SMDK2412 1009 -#define MACH_TYPE_WEBBOX 1010 -#define MACH_TYPE_CWWNDP 1011 -#define MACH_TYPE_DRAGON 1012 -#define MACH_TYPE_OPENDO_CPU_BOARD 1013 -#define MACH_TYPE_CCM2200 1014 -#define MACH_TYPE_ETWARM 1015 -#define MACH_TYPE_M93030 1016 -#define MACH_TYPE_CC7U 1017 -#define MACH_TYPE_MTT_RANGER 1018 -#define MACH_TYPE_NEXUS 1019 -#define MACH_TYPE_DESMAN 1020 -#define MACH_TYPE_BKDE303 1021 -#define MACH_TYPE_SMDK2413 1022 -#define MACH_TYPE_AML_M7200 1023 -#define MACH_TYPE_AML_M5900 1024 -#define MACH_TYPE_SG640 1025 -#define MACH_TYPE_EDG79524 1026 -#define MACH_TYPE_AI2410 1027 -#define MACH_TYPE_IXP465 1028 -#define MACH_TYPE_BALLOON3 1029 -#define MACH_TYPE_HEINS 1030 -#define MACH_TYPE_MPLUSEVA 1031 -#define MACH_TYPE_RT042 1032 -#define MACH_TYPE_CWIEM 1033 -#define MACH_TYPE_CM_X270 1034 -#define MACH_TYPE_CM_X255 1035 -#define MACH_TYPE_ESH_AT91 1036 -#define MACH_TYPE_SANDGATE3 1037 -#define MACH_TYPE_PRIMO 1038 -#define MACH_TYPE_GEMSTONE 1039 -#define MACH_TYPE_PRONGHORNMETRO 1040 -#define MACH_TYPE_SIDEWINDER 1041 -#define MACH_TYPE_PICOMOD1 1042 -#define MACH_TYPE_SG590 1043 -#define MACH_TYPE_AKAI9307 1044 -#define MACH_TYPE_FONTAINE 1045 -#define MACH_TYPE_WOMBAT 1046 -#define MACH_TYPE_ACQ300 1047 -#define MACH_TYPE_MOD_270 1048 -#define MACH_TYPE_VC0820 1049 -#define MACH_TYPE_ANI_AIM 1050 -#define MACH_TYPE_JELLYFISH 1051 -#define MACH_TYPE_AMANITA 1052 -#define MACH_TYPE_VLINK 1053 -#define MACH_TYPE_DEXFLEX 1054 -#define MACH_TYPE_EIGEN_TTQ 1055 -#define MACH_TYPE_ARCOM_TITAN 1056 -#define MACH_TYPE_TABLA 1057 -#define MACH_TYPE_MDIRAC3 1058 -#define MACH_TYPE_MRHFBP2 1059 -#define MACH_TYPE_AT91RM9200RB 1060 -#define MACH_TYPE_ANI_APM 1061 -#define MACH_TYPE_ELLA1 1062 -#define MACH_TYPE_INHAND_PXA27X 1063 -#define MACH_TYPE_INHAND_PXA25X 1064 -#define MACH_TYPE_EMPOS_XM 1065 -#define MACH_TYPE_EMPOS 1066 -#define MACH_TYPE_EMPOS_TINY 1067 -#define MACH_TYPE_EMPOS_SM 1068 -#define MACH_TYPE_EGRET 1069 -#define MACH_TYPE_OSTRICH 1070 -#define MACH_TYPE_N50 1071 -#define MACH_TYPE_ECBAT91 1072 -#define MACH_TYPE_STAREAST 1073 -#define MACH_TYPE_DSPG_DW 1074 -#define MACH_TYPE_ONEARM 1075 -#define MACH_TYPE_MRG110_6 1076 -#define MACH_TYPE_WRT300NV2 1077 -#define MACH_TYPE_XM_BULVERDE 1078 -#define MACH_TYPE_MSM6100 1079 -#define MACH_TYPE_ETI_B1 1080 -#define MACH_TYPE_ZILOG_ZA9L 1081 -#define MACH_TYPE_BIT2440 1082 -#define MACH_TYPE_NBI 1083 -#define MACH_TYPE_SMDK2443 1084 -#define MACH_TYPE_VDAVINCI 1085 -#define MACH_TYPE_ATC6 1086 -#define MACH_TYPE_MULTMDW 1087 -#define MACH_TYPE_MBA2440 1088 -#define MACH_TYPE_ECSD 1089 -#define MACH_TYPE_PALMZ31 1090 -#define MACH_TYPE_FSG 1091 -#define MACH_TYPE_RAZOR101 1092 -#define MACH_TYPE_OPERA_TDM 1093 -#define MACH_TYPE_COMCERTO 1094 -#define MACH_TYPE_TB0319 1095 -#define MACH_TYPE_KWS8000 1096 -#define MACH_TYPE_B2 1097 -#define MACH_TYPE_LCL54 1098 -#define MACH_TYPE_AT91SAM9260EK 1099 -#define MACH_TYPE_GLANTANK 1100 -#define MACH_TYPE_N2100 1101 -#define MACH_TYPE_N4100 1102 -#define MACH_TYPE_VERTICAL_RSC4 1103 -#define MACH_TYPE_SG8100 1104 -#define MACH_TYPE_IM42XX 1105 -#define MACH_TYPE_FTXX 1106 -#define MACH_TYPE_LWFUSION 1107 -#define MACH_TYPE_QT2410 1108 -#define MACH_TYPE_KIXRP435 1109 -#define MACH_TYPE_CCW9C 1110 -#define MACH_TYPE_DABHS 1111 -#define MACH_TYPE_GZMX 1112 -#define MACH_TYPE_IPNW100AP 1113 -#define MACH_TYPE_CC9P9360DEV 1114 -#define MACH_TYPE_CC9P9750DEV 1115 -#define MACH_TYPE_CC9P9360VAL 1116 -#define MACH_TYPE_CC9P9750VAL 1117 -#define MACH_TYPE_NX70V 1118 -#define MACH_TYPE_AT91RM9200DF 1119 -#define MACH_TYPE_SE_PILOT2 1120 -#define MACH_TYPE_MTCN_T800 1121 -#define MACH_TYPE_VCMX212 1122 -#define MACH_TYPE_LYNX 1123 -#define MACH_TYPE_AT91SAM9260ID 1124 -#define MACH_TYPE_HW86052 1125 -#define MACH_TYPE_PILZ_PMI3 1126 -#define MACH_TYPE_EDB9302A 1127 -#define MACH_TYPE_EDB9307A 1128 -#define MACH_TYPE_CT_DFS 1129 -#define MACH_TYPE_PILZ_PMI4 1130 -#define MACH_TYPE_XCEEDNP_IXP 1131 -#define MACH_TYPE_SMDK2442B 1132 -#define MACH_TYPE_XNODE 1133 -#define MACH_TYPE_AIDX270 1134 -#define MACH_TYPE_REMA 1135 -#define MACH_TYPE_BPS1000 1136 -#define MACH_TYPE_HW90350 1137 -#define MACH_TYPE_OMAP_3430SDP 1138 -#define MACH_TYPE_BLUETOUCH 1139 -#define MACH_TYPE_VSTMS 1140 -#define MACH_TYPE_XSBASE270 1141 -#define MACH_TYPE_AT91SAM9260EK_CN 1142 -#define MACH_TYPE_ADSTURBOXB 1143 -#define MACH_TYPE_OTI4110 1144 -#define MACH_TYPE_HME_PXA 1145 -#define MACH_TYPE_DEISTERDCA 1146 -#define MACH_TYPE_CES_SSEM2 1147 -#define MACH_TYPE_CES_MTR 1148 -#define MACH_TYPE_TDS_AVNG_SBC 1149 -#define MACH_TYPE_EVEREST 1150 -#define MACH_TYPE_PNX4010 1151 -#define MACH_TYPE_OXNAS 1152 -#define MACH_TYPE_FIORI 1153 -#define MACH_TYPE_ML1200 1154 -#define MACH_TYPE_PECOS 1155 -#define MACH_TYPE_NB2XXX 1156 -#define MACH_TYPE_HW6900 1157 -#define MACH_TYPE_CDCS_QUOLL 1158 -#define MACH_TYPE_QUICKSILVER 1159 -#define MACH_TYPE_UPLAT926 1160 -#define MACH_TYPE_DEP2410_THOMAS 1161 -#define MACH_TYPE_DTK2410 1162 -#define MACH_TYPE_CHILI 1163 -#define MACH_TYPE_DEMETER 1164 -#define MACH_TYPE_DIONYSUS 1165 -#define MACH_TYPE_AS352X 1166 -#define MACH_TYPE_SERVICE 1167 -#define MACH_TYPE_CS_E9301 1168 -#define MACH_TYPE_MICRO9M 1169 -#define MACH_TYPE_IA_MOSPCK 1170 -#define MACH_TYPE_QL201B 1171 -#define MACH_TYPE_BBM 1174 -#define MACH_TYPE_EXXX 1175 -#define MACH_TYPE_WMA11B 1176 -#define MACH_TYPE_PELCO_ATLAS 1177 -#define MACH_TYPE_G500 1178 -#define MACH_TYPE_BUG 1179 -#define MACH_TYPE_MX33ADS 1180 -#define MACH_TYPE_CHUB 1181 -#define MACH_TYPE_NEO1973_GTA01 1182 -#define MACH_TYPE_W90N740 1183 -#define MACH_TYPE_MEDALLION_SA2410 1184 -#define MACH_TYPE_IA_CPU_9200_2 1185 -#define MACH_TYPE_DIMMRM9200 1186 -#define MACH_TYPE_PM9261 1187 -#define MACH_TYPE_ML7304 1189 -#define MACH_TYPE_UCP250 1190 -#define MACH_TYPE_INTBOARD 1191 -#define MACH_TYPE_GULFSTREAM 1192 -#define MACH_TYPE_LABQUEST 1193 -#define MACH_TYPE_VCMX313 1194 -#define MACH_TYPE_URG200 1195 -#define MACH_TYPE_CPUX255LCDNET 1196 -#define MACH_TYPE_NETDCU9 1197 -#define MACH_TYPE_NETDCU10 1198 -#define MACH_TYPE_DSPG_DGA 1199 -#define MACH_TYPE_DSPG_DVW 1200 -#define MACH_TYPE_SOLOS 1201 -#define MACH_TYPE_AT91SAM9263EK 1202 -#define MACH_TYPE_OSSTBOX 1203 -#define MACH_TYPE_KBAT9261 1204 -#define MACH_TYPE_CT1100 1205 -#define MACH_TYPE_AKCPPXA 1206 -#define MACH_TYPE_OCHAYA1020 1207 -#define MACH_TYPE_HITRACK 1208 -#define MACH_TYPE_SYME1 1209 -#define MACH_TYPE_SYHL1 1210 -#define MACH_TYPE_EMPCA400 1211 -#define MACH_TYPE_EM7210 1212 -#define MACH_TYPE_HTCHERMES 1213 -#define MACH_TYPE_ETI_C1 1214 -#define MACH_TYPE_AC100 1216 -#define MACH_TYPE_SNEETCH 1217 -#define MACH_TYPE_STUDENTMATE 1218 -#define MACH_TYPE_ZIR2410 1219 -#define MACH_TYPE_ZIR2413 1220 -#define MACH_TYPE_DLONIP3 1221 -#define MACH_TYPE_INSTREAM 1222 -#define MACH_TYPE_AMBARELLA 1223 -#define MACH_TYPE_NEVIS 1224 -#define MACH_TYPE_HTC_TRINITY 1225 -#define MACH_TYPE_QL202B 1226 -#define MACH_TYPE_VPAC270 1227 -#define MACH_TYPE_RD129 1228 -#define MACH_TYPE_HTCWIZARD 1229 -#define MACH_TYPE_TREO680 1230 -#define MACH_TYPE_TECON_TMEZON 1231 -#define MACH_TYPE_ZYLONITE 1233 -#define MACH_TYPE_GENE1270 1234 -#define MACH_TYPE_ZIR2412 1235 -#define MACH_TYPE_MX31LITE 1236 -#define MACH_TYPE_T700WX 1237 -#define MACH_TYPE_VF100 1238 -#define MACH_TYPE_NSB2 1239 -#define MACH_TYPE_NXHMI_BB 1240 -#define MACH_TYPE_NXHMI_RE 1241 -#define MACH_TYPE_N4100PRO 1242 -#define MACH_TYPE_SAM9260 1243 -#define MACH_TYPE_OMAP_TREO600 1244 -#define MACH_TYPE_INDY2410 1245 -#define MACH_TYPE_NELT_A 1246 -#define MACH_TYPE_N311 1248 -#define MACH_TYPE_AT91SAM9260VGK 1249 -#define MACH_TYPE_AT91LEPPE 1250 -#define MACH_TYPE_AT91LEPCCN 1251 -#define MACH_TYPE_APC7100 1252 -#define MACH_TYPE_STARGAZER 1253 -#define MACH_TYPE_SONATA 1254 -#define MACH_TYPE_SCHMOOGIE 1255 -#define MACH_TYPE_AZTOOL 1256 -#define MACH_TYPE_MIOA701 1257 -#define MACH_TYPE_SXNI9260 1258 -#define MACH_TYPE_MXC27520EVB 1259 -#define MACH_TYPE_ARMADILLO5X0 1260 -#define MACH_TYPE_MB9260 1261 -#define MACH_TYPE_MB9263 1262 -#define MACH_TYPE_IPAC9302 1263 -#define MACH_TYPE_CC9P9360JS 1264 -#define MACH_TYPE_GALLIUM 1265 -#define MACH_TYPE_MSC2410 1266 -#define MACH_TYPE_GHI270 1267 -#define MACH_TYPE_DAVINCI_LEONARDO 1268 -#define MACH_TYPE_OIAB 1269 -#define MACH_TYPE_SMDK6400 1270 -#define MACH_TYPE_NOKIA_N800 1271 -#define MACH_TYPE_GREENPHONE 1272 -#define MACH_TYPE_COMPEXWP18 1273 -#define MACH_TYPE_XMATE 1274 -#define MACH_TYPE_ENERGIZER 1275 -#define MACH_TYPE_IME1 1276 -#define MACH_TYPE_SWEDATMS 1277 -#define MACH_TYPE_NTNP435C 1278 -#define MACH_TYPE_SPECTRO2 1279 -#define MACH_TYPE_H6039 1280 -#define MACH_TYPE_EP80219 1281 -#define MACH_TYPE_SAMOA_II 1282 -#define MACH_TYPE_CWMXL 1283 -#define MACH_TYPE_AS9200 1284 -#define MACH_TYPE_SFX1149 1285 -#define MACH_TYPE_NAVI010 1286 -#define MACH_TYPE_MULTMDP 1287 -#define MACH_TYPE_SCB9520 1288 -#define MACH_TYPE_HTCATHENA 1289 -#define MACH_TYPE_XP179 1290 -#define MACH_TYPE_H4300 1291 -#define MACH_TYPE_GORAMO_MLR 1292 -#define MACH_TYPE_MXC30020EVB 1293 -#define MACH_TYPE_ADSBITSYG5 1294 -#define MACH_TYPE_ADSPORTALPLUS 1295 -#define MACH_TYPE_MMSP2PLUS 1296 -#define MACH_TYPE_EM_X270 1297 -#define MACH_TYPE_TPP302 1298 -#define MACH_TYPE_TPM104 1299 -#define MACH_TYPE_TPM102 1300 -#define MACH_TYPE_TPM109 1301 -#define MACH_TYPE_FBXO1 1302 -#define MACH_TYPE_HXD8 1303 -#define MACH_TYPE_NEO1973_GTA02 1304 -#define MACH_TYPE_EMTEST 1305 -#define MACH_TYPE_AD6900 1306 -#define MACH_TYPE_EUROPA 1307 -#define MACH_TYPE_METROCONNECT 1308 -#define MACH_TYPE_EZ_S2410 1309 -#define MACH_TYPE_EZ_S2440 1310 -#define MACH_TYPE_EZ_EP9312 1311 -#define MACH_TYPE_EZ_EP9315 1312 -#define MACH_TYPE_EZ_X7 1313 -#define MACH_TYPE_GODOTDB 1314 -#define MACH_TYPE_MISTRAL 1315 -#define MACH_TYPE_MSM 1316 -#define MACH_TYPE_CT5910 1317 -#define MACH_TYPE_CT5912 1318 -#define MACH_TYPE_HYNET_INE 1319 -#define MACH_TYPE_HYNET_APP 1320 -#define MACH_TYPE_MSM7200 1321 -#define MACH_TYPE_MSM7600 1322 -#define MACH_TYPE_CEB255 1323 -#define MACH_TYPE_CIEL 1324 -#define MACH_TYPE_SLM5650 1325 -#define MACH_TYPE_AT91SAM9RLEK 1326 -#define MACH_TYPE_COMTECH_ROUTER 1327 -#define MACH_TYPE_SBC2410X 1328 -#define MACH_TYPE_AT4X0BD 1329 -#define MACH_TYPE_CBIFR 1330 -#define MACH_TYPE_ARCOM_QUANTUM 1331 -#define MACH_TYPE_MATRIX520 1332 -#define MACH_TYPE_MATRIX510 1333 -#define MACH_TYPE_MATRIX500 1334 -#define MACH_TYPE_M501 1335 -#define MACH_TYPE_AAEON1270 1336 -#define MACH_TYPE_MATRIX500EV 1337 -#define MACH_TYPE_PAC500 1338 -#define MACH_TYPE_PNX8181 1339 -#define MACH_TYPE_COLIBRI320 1340 -#define MACH_TYPE_AZTOOLBB 1341 -#define MACH_TYPE_AZTOOLG2 1342 -#define MACH_TYPE_DVLHOST 1343 -#define MACH_TYPE_ZIR9200 1344 -#define MACH_TYPE_ZIR9260 1345 -#define MACH_TYPE_COCOPAH 1346 -#define MACH_TYPE_NDS 1347 -#define MACH_TYPE_ROSENCRANTZ 1348 -#define MACH_TYPE_FTTX_ODSC 1349 -#define MACH_TYPE_CLASSE_R6904 1350 -#define MACH_TYPE_CAM60 1351 -#define MACH_TYPE_MXC30031ADS 1352 -#define MACH_TYPE_DATACALL 1353 -#define MACH_TYPE_AT91EB01 1354 -#define MACH_TYPE_RTY 1355 -#define MACH_TYPE_DWL2100 1356 -#define MACH_TYPE_VINSI 1357 -#define MACH_TYPE_DB88F5281 1358 -#define MACH_TYPE_CSB726 1359 -#define MACH_TYPE_TIK27 1360 -#define MACH_TYPE_MX_UC7420 1361 -#define MACH_TYPE_RIRM3 1362 -#define MACH_TYPE_PELCO_ODYSSEY 1363 -#define MACH_TYPE_ADX_ABOX 1365 -#define MACH_TYPE_ADX_TPID 1366 -#define MACH_TYPE_MINICHECK 1367 -#define MACH_TYPE_IDAM 1368 -#define MACH_TYPE_MARIO_MX 1369 -#define MACH_TYPE_VI1888 1370 -#define MACH_TYPE_ZR4230 1371 -#define MACH_TYPE_T1_IX_BLUE 1372 -#define MACH_TYPE_SYHQ2 1373 -#define MACH_TYPE_COMPUTIME_R3 1374 -#define MACH_TYPE_ORATIS 1375 -#define MACH_TYPE_MIKKO 1376 -#define MACH_TYPE_HOLON 1377 -#define MACH_TYPE_OLIP8 1378 -#define MACH_TYPE_GHI270HG 1379 -#define MACH_TYPE_DAVINCI_DM6467_EVM 1380 -#define MACH_TYPE_DAVINCI_DM355_EVM 1381 -#define MACH_TYPE_BLACKRIVER 1383 -#define MACH_TYPE_SANDGATEWP 1384 -#define MACH_TYPE_CDOTBWSG 1385 -#define MACH_TYPE_QUARK963 1386 -#define MACH_TYPE_CSB735 1387 -#define MACH_TYPE_LITTLETON 1388 -#define MACH_TYPE_MIO_P550 1389 -#define MACH_TYPE_MOTION2440 1390 -#define MACH_TYPE_IMM500 1391 -#define MACH_TYPE_HOMEMATIC 1392 -#define MACH_TYPE_ERMINE 1393 -#define MACH_TYPE_KB9202B 1394 -#define MACH_TYPE_HS1XX 1395 -#define MACH_TYPE_STUDENTMATE2440 1396 -#define MACH_TYPE_ARVOO_L1_Z1 1397 -#define MACH_TYPE_DEP2410K 1398 -#define MACH_TYPE_XXSVIDEO 1399 -#define MACH_TYPE_IM4004 1400 -#define MACH_TYPE_OCHAYA1050 1401 -#define MACH_TYPE_LEP9261 1402 -#define MACH_TYPE_SVENMEB 1403 -#define MACH_TYPE_FORTUNET2NE 1404 -#define MACH_TYPE_NXHX 1406 -#define MACH_TYPE_REALVIEW_PB11MP 1407 -#define MACH_TYPE_IDS500 1408 -#define MACH_TYPE_ORS_N725 1409 -#define MACH_TYPE_HSDARM 1410 -#define MACH_TYPE_SHA_PON003 1411 -#define MACH_TYPE_SHA_PON004 1412 -#define MACH_TYPE_SHA_PON007 1413 -#define MACH_TYPE_SHA_PON011 1414 -#define MACH_TYPE_H6042 1415 -#define MACH_TYPE_H6043 1416 -#define MACH_TYPE_LOOXC550 1417 -#define MACH_TYPE_CNTY_TITAN 1418 -#define MACH_TYPE_APP3XX 1419 -#define MACH_TYPE_SIDEOATSGRAMA 1420 -#define MACH_TYPE_TREO700P 1421 -#define MACH_TYPE_TREO700W 1422 -#define MACH_TYPE_TREO750 1423 -#define MACH_TYPE_TREO755P 1424 -#define MACH_TYPE_EZREGANUT9200 1425 -#define MACH_TYPE_SARGE 1426 -#define MACH_TYPE_A696 1427 -#define MACH_TYPE_TURTLE 1428 -#define MACH_TYPE_MX27_3DS 1430 -#define MACH_TYPE_BISHOP 1431 -#define MACH_TYPE_PXX 1432 -#define MACH_TYPE_REDWOOD 1433 -#define MACH_TYPE_OMAP_2430DLP 1436 -#define MACH_TYPE_OMAP_2430OSK 1437 -#define MACH_TYPE_SARDINE 1438 -#define MACH_TYPE_HALIBUT 1439 -#define MACH_TYPE_TROUT 1440 -#define MACH_TYPE_GOLDFISH 1441 -#define MACH_TYPE_GESBC2440 1442 -#define MACH_TYPE_NOMAD 1443 -#define MACH_TYPE_ROSALIND 1444 -#define MACH_TYPE_CC9P9215 1445 -#define MACH_TYPE_CC9P9210 1446 -#define MACH_TYPE_CC9P9215JS 1447 -#define MACH_TYPE_CC9P9210JS 1448 -#define MACH_TYPE_NASFFE 1449 -#define MACH_TYPE_TN2X0BD 1450 -#define MACH_TYPE_GWMPXA 1451 -#define MACH_TYPE_EXYPLUS 1452 -#define MACH_TYPE_JADOO21 1453 -#define MACH_TYPE_LOOXN560 1454 -#define MACH_TYPE_BONSAI 1455 -#define MACH_TYPE_ADSMILGATO 1456 -#define MACH_TYPE_GBA 1457 -#define MACH_TYPE_H6044 1458 -#define MACH_TYPE_APP 1459 -#define MACH_TYPE_TCT_HAMMER 1460 -#define MACH_TYPE_HERALD 1461 -#define MACH_TYPE_ARTEMIS 1462 -#define MACH_TYPE_HTCTITAN 1463 -#define MACH_TYPE_QRANIUM 1464 -#define MACH_TYPE_ADX_WSC2 1465 -#define MACH_TYPE_ADX_MEDCOM 1466 -#define MACH_TYPE_BBOARD 1467 -#define MACH_TYPE_CAMBRIA 1468 -#define MACH_TYPE_MT7XXX 1469 -#define MACH_TYPE_MATRIX512 1470 -#define MACH_TYPE_MATRIX522 1471 -#define MACH_TYPE_IPAC5010 1472 -#define MACH_TYPE_SAKURA 1473 -#define MACH_TYPE_GROCX 1474 -#define MACH_TYPE_PM9263 1475 -#define MACH_TYPE_SIM_ONE 1476 -#define MACH_TYPE_ACQ132 1477 -#define MACH_TYPE_DATR 1478 -#define MACH_TYPE_ACTUX1 1479 -#define MACH_TYPE_ACTUX2 1480 -#define MACH_TYPE_ACTUX3 1481 -#define MACH_TYPE_FLEXIT 1482 -#define MACH_TYPE_BH2X0BD 1483 -#define MACH_TYPE_ATB2002 1484 -#define MACH_TYPE_XENON 1485 -#define MACH_TYPE_FM607 1486 -#define MACH_TYPE_MATRIX514 1487 -#define MACH_TYPE_MATRIX524 1488 -#define MACH_TYPE_INPOD 1489 -#define MACH_TYPE_JIVE 1490 -#define MACH_TYPE_TLL_MX21 1491 -#define MACH_TYPE_SBC2800 1492 -#define MACH_TYPE_CC7UCAMRY 1493 -#define MACH_TYPE_UBISYS_P9_SC15 1494 -#define MACH_TYPE_UBISYS_P9_SSC2D10 1495 -#define MACH_TYPE_UBISYS_P9_RCU3 1496 -#define MACH_TYPE_AML_M8000 1497 -#define MACH_TYPE_SNAPPER_270 1498 -#define MACH_TYPE_OMAP_BBX 1499 -#define MACH_TYPE_UCN2410 1500 -#define MACH_TYPE_SAM9_L9260 1501 -#define MACH_TYPE_ETI_C2 1502 -#define MACH_TYPE_AVALANCHE 1503 -#define MACH_TYPE_REALVIEW_PB1176 1504 -#define MACH_TYPE_DP1500 1505 -#define MACH_TYPE_APPLE_IPHONE 1506 -#define MACH_TYPE_YL9200 1507 -#define MACH_TYPE_RD88F5182 1508 -#define MACH_TYPE_KUROBOX_PRO 1509 -#define MACH_TYPE_SE_POET 1510 -#define MACH_TYPE_MX31_3DS 1511 -#define MACH_TYPE_R270 1512 -#define MACH_TYPE_ARMOUR21 1513 -#define MACH_TYPE_DT2 1514 -#define MACH_TYPE_VT4 1515 -#define MACH_TYPE_TYCO320 1516 -#define MACH_TYPE_ADMA 1517 -#define MACH_TYPE_WP188 1518 -#define MACH_TYPE_CORSICA 1519 -#define MACH_TYPE_BIGEYE 1520 -#define MACH_TYPE_TLL5000 1522 -#define MACH_TYPE_BEBOT 1523 -#define MACH_TYPE_QONG 1524 -#define MACH_TYPE_TCOMPACT 1525 -#define MACH_TYPE_PUMA5 1526 -#define MACH_TYPE_ELARA 1527 -#define MACH_TYPE_ELLINGTON 1528 -#define MACH_TYPE_XDA_ATOM 1529 -#define MACH_TYPE_ENERGIZER2 1530 -#define MACH_TYPE_ODIN 1531 -#define MACH_TYPE_ACTUX4 1532 -#define MACH_TYPE_ESL_OMAP 1533 -#define MACH_TYPE_OMAP2EVM 1534 -#define MACH_TYPE_OMAP3EVM 1535 -#define MACH_TYPE_ADX_PCU57 1536 -#define MACH_TYPE_MONACO 1537 -#define MACH_TYPE_LEVANTE 1538 -#define MACH_TYPE_TMXIPX425 1539 -#define MACH_TYPE_LEEP 1540 -#define MACH_TYPE_RAAD 1541 -#define MACH_TYPE_DNS323 1542 -#define MACH_TYPE_AP1000 1543 -#define MACH_TYPE_A9SAM6432 1544 -#define MACH_TYPE_SHINY 1545 -#define MACH_TYPE_OMAP3_BEAGLE 1546 -#define MACH_TYPE_CSR_BDB2 1547 -#define MACH_TYPE_NOKIA_N810 1548 -#define MACH_TYPE_C270 1549 -#define MACH_TYPE_SENTRY 1550 -#define MACH_TYPE_PCM038 1551 -#define MACH_TYPE_ANC300 1552 -#define MACH_TYPE_HTCKAISER 1553 -#define MACH_TYPE_SBAT100 1554 -#define MACH_TYPE_MODUNORM 1555 -#define MACH_TYPE_PELOS_TWARM 1556 -#define MACH_TYPE_FLANK 1557 -#define MACH_TYPE_SIRLOIN 1558 -#define MACH_TYPE_BRISKET 1559 -#define MACH_TYPE_CHUCK 1560 -#define MACH_TYPE_OTTER 1561 -#define MACH_TYPE_DAVINCI_LDK 1562 -#define MACH_TYPE_PHREEDOM 1563 -#define MACH_TYPE_SG310 1564 -#define MACH_TYPE_TS209 1565 -#define MACH_TYPE_AT91CAP9ADK 1566 -#define MACH_TYPE_TION9315 1567 -#define MACH_TYPE_MAST 1568 -#define MACH_TYPE_PFW 1569 -#define MACH_TYPE_YL_P2440 1570 -#define MACH_TYPE_ZSBC32 1571 -#define MACH_TYPE_OMAP_PACE2 1572 -#define MACH_TYPE_IMX_PACE2 1573 -#define MACH_TYPE_MX31MOBOARD 1574 -#define MACH_TYPE_MX37_3DS 1575 -#define MACH_TYPE_RCC 1576 -#define MACH_TYPE_ARM9 1577 -#define MACH_TYPE_VISION_EP9307 1578 -#define MACH_TYPE_SCLY1000 1579 -#define MACH_TYPE_FONTEL_EP 1580 -#define MACH_TYPE_VOICEBLUE3G 1581 -#define MACH_TYPE_TT9200 1582 -#define MACH_TYPE_DIGI2410 1583 -#define MACH_TYPE_TERASTATION_PRO2 1584 -#define MACH_TYPE_LINKSTATION_PRO 1585 -#define MACH_TYPE_MOTOROLA_A780 1587 -#define MACH_TYPE_MOTOROLA_E6 1588 -#define MACH_TYPE_MOTOROLA_E2 1589 -#define MACH_TYPE_MOTOROLA_E680 1590 -#define MACH_TYPE_UR2410 1591 -#define MACH_TYPE_TAS9261 1592 -#define MACH_TYPE_HERMES_HD 1593 -#define MACH_TYPE_PERSEO_HD 1594 -#define MACH_TYPE_STARGAZER2 1595 -#define MACH_TYPE_E350 1596 -#define MACH_TYPE_WPCM450 1597 -#define MACH_TYPE_CARTESIO 1598 -#define MACH_TYPE_TOYBOX 1599 -#define MACH_TYPE_TX27 1600 -#define MACH_TYPE_TS409 1601 -#define MACH_TYPE_P300 1602 -#define MACH_TYPE_XDACOMET 1603 -#define MACH_TYPE_DEXFLEX2 1604 -#define MACH_TYPE_OW 1605 -#define MACH_TYPE_ARMEBS3 1606 -#define MACH_TYPE_U3 1607 -#define MACH_TYPE_SMDK2450 1608 -#define MACH_TYPE_RSI_EWS 1609 -#define MACH_TYPE_TNB 1610 -#define MACH_TYPE_TOEPATH 1611 -#define MACH_TYPE_KB9263 1612 -#define MACH_TYPE_MT7108 1613 -#define MACH_TYPE_SMTR2440 1614 -#define MACH_TYPE_MANAO 1615 -#define MACH_TYPE_CM_X300 1616 -#define MACH_TYPE_GULFSTREAM_KP 1617 -#define MACH_TYPE_LANREADYFN522 1618 -#define MACH_TYPE_ARMA37 1619 -#define MACH_TYPE_MENDEL 1620 -#define MACH_TYPE_PELCO_ILIAD 1621 -#define MACH_TYPE_UNIT2P 1622 -#define MACH_TYPE_INC20OTTER 1623 -#define MACH_TYPE_AT91SAM9G20EK 1624 -#define MACH_TYPE_STORCENTER 1625 -#define MACH_TYPE_SMDK6410 1626 -#define MACH_TYPE_U300 1627 -#define MACH_TYPE_U500 1628 -#define MACH_TYPE_DS9260 1629 -#define MACH_TYPE_RIVERROCK 1630 -#define MACH_TYPE_SCIBATH 1631 -#define MACH_TYPE_AT91SAM7SE512EK 1632 -#define MACH_TYPE_WRT350N_V2 1633 -#define MACH_TYPE_MULTIMEDIA 1634 -#define MACH_TYPE_MARVIN 1635 -#define MACH_TYPE_X500 1636 -#define MACH_TYPE_AWLUG4LCU 1637 -#define MACH_TYPE_PALERMOC 1638 -#define MACH_TYPE_OMAP_LDP 1639 -#define MACH_TYPE_IP500 1640 -#define MACH_TYPE_ASE2 1642 -#define MACH_TYPE_MX35EVB 1643 -#define MACH_TYPE_AML_M8050 1644 -#define MACH_TYPE_MX35_3DS 1645 -#define MACH_TYPE_MARS 1646 -#define MACH_TYPE_NEUROS_OSD2 1647 -#define MACH_TYPE_BADGER 1648 -#define MACH_TYPE_TRIZEPS4WL 1649 -#define MACH_TYPE_TRIZEPS5 1650 -#define MACH_TYPE_MARLIN 1651 -#define MACH_TYPE_TS78XX 1652 -#define MACH_TYPE_HPIPAQ214 1653 -#define MACH_TYPE_AT572D940DCM 1654 -#define MACH_TYPE_NE1BOARD 1655 -#define MACH_TYPE_ZANTE 1656 -#define MACH_TYPE_SFFSDR 1657 -#define MACH_TYPE_TW2662 1658 -#define MACH_TYPE_VF10XX 1659 -#define MACH_TYPE_ZORAN43XX 1660 -#define MACH_TYPE_SONIX926 1661 -#define MACH_TYPE_CELESTIALSEMI 1662 -#define MACH_TYPE_CC9M2443JS 1663 -#define MACH_TYPE_TW5334 1664 -#define MACH_TYPE_HTCARTEMIS 1665 -#define MACH_TYPE_NAL_HLITE 1666 -#define MACH_TYPE_HTCVOGUE 1667 -#define MACH_TYPE_SMARTWEB 1668 -#define MACH_TYPE_MV86XX 1669 -#define MACH_TYPE_MV87XX 1670 -#define MACH_TYPE_SONGYOUNGHO 1671 -#define MACH_TYPE_YOUNGHOTEMA 1672 -#define MACH_TYPE_PCM037 1673 -#define MACH_TYPE_MMVP 1674 -#define MACH_TYPE_MMAP 1675 -#define MACH_TYPE_PTID2410 1676 -#define MACH_TYPE_JAMES_926 1677 -#define MACH_TYPE_FM6000 1678 -#define MACH_TYPE_DB88F6281_BP 1680 -#define MACH_TYPE_RD88F6192_NAS 1681 -#define MACH_TYPE_RD88F6281 1682 -#define MACH_TYPE_DB78X00_BP 1683 -#define MACH_TYPE_SMDK2416 1685 -#define MACH_TYPE_OCE_SPIDER_SI 1686 -#define MACH_TYPE_OCE_SPIDER_SK 1687 -#define MACH_TYPE_ROVERN6 1688 -#define MACH_TYPE_PELCO_EVOLUTION 1689 -#define MACH_TYPE_WBD111 1690 -#define MACH_TYPE_ELARACPE 1691 -#define MACH_TYPE_MABV3 1692 -#define MACH_TYPE_MV2120 1693 -#define MACH_TYPE_CSB737 1695 -#define MACH_TYPE_MX51_3DS 1696 -#define MACH_TYPE_G900 1697 -#define MACH_TYPE_APF27 1698 -#define MACH_TYPE_GGUS2000 1699 -#define MACH_TYPE_OMAP_2430_MIMIC 1700 -#define MACH_TYPE_IMX27LITE 1701 -#define MACH_TYPE_ALMEX 1702 -#define MACH_TYPE_CONTROL 1703 -#define MACH_TYPE_MBA2410 1704 -#define MACH_TYPE_VOLCANO 1705 -#define MACH_TYPE_ZENITH 1706 -#define MACH_TYPE_MUCHIP 1707 -#define MACH_TYPE_MAGELLAN 1708 -#define MACH_TYPE_USB_A9260 1709 -#define MACH_TYPE_USB_A9263 1710 -#define MACH_TYPE_QIL_A9260 1711 -#define MACH_TYPE_CME9210 1712 -#define MACH_TYPE_HCZH4 1713 -#define MACH_TYPE_SPEARBASIC 1714 -#define MACH_TYPE_DEP2440 1715 -#define MACH_TYPE_HDL_GXR 1716 -#define MACH_TYPE_HDL_GT 1717 -#define MACH_TYPE_HDL_4G 1718 -#define MACH_TYPE_S3C6000 1719 -#define MACH_TYPE_MMSP2_MDK 1720 -#define MACH_TYPE_MPX220 1721 -#define MACH_TYPE_KZM_ARM11_01 1722 -#define MACH_TYPE_HTC_POLARIS 1723 -#define MACH_TYPE_HTC_KAISER 1724 -#define MACH_TYPE_LG_KS20 1725 -#define MACH_TYPE_HHGPS 1726 -#define MACH_TYPE_NOKIA_N810_WIMAX 1727 -#define MACH_TYPE_INSIGHT 1728 -#define MACH_TYPE_SAPPHIRE 1729 -#define MACH_TYPE_CSB637XO 1730 -#define MACH_TYPE_EVISIONG 1731 -#define MACH_TYPE_STMP37XX 1732 -#define MACH_TYPE_STMP378X 1733 -#define MACH_TYPE_TNT 1734 -#define MACH_TYPE_TBXT 1735 -#define MACH_TYPE_PLAYMATE 1736 -#define MACH_TYPE_PNS10 1737 -#define MACH_TYPE_EZNAVI 1738 -#define MACH_TYPE_PS4000 1739 -#define MACH_TYPE_EZX_A780 1740 -#define MACH_TYPE_EZX_E680 1741 -#define MACH_TYPE_EZX_A1200 1742 -#define MACH_TYPE_EZX_E6 1743 -#define MACH_TYPE_EZX_E2 1744 -#define MACH_TYPE_EZX_A910 1745 -#define MACH_TYPE_CWMX31 1746 -#define MACH_TYPE_SL2312 1747 -#define MACH_TYPE_BLENNY 1748 -#define MACH_TYPE_DS107 1749 -#define MACH_TYPE_DSX07 1750 -#define MACH_TYPE_PICOCOM1 1751 -#define MACH_TYPE_LYNX_WOLVERINE 1752 -#define MACH_TYPE_UBISYS_P9_SC19 1753 -#define MACH_TYPE_KRATOS_LOW 1754 -#define MACH_TYPE_M700 1755 -#define MACH_TYPE_EDMINI_V2 1756 -#define MACH_TYPE_ZIPIT2 1757 -#define MACH_TYPE_HSLFEMTOCELL 1758 -#define MACH_TYPE_DAINTREE_AT91 1759 -#define MACH_TYPE_SG560USB 1760 -#define MACH_TYPE_OMAP3_PANDORA 1761 -#define MACH_TYPE_USR8200 1762 -#define MACH_TYPE_S1S65K 1763 -#define MACH_TYPE_S2S65A 1764 -#define MACH_TYPE_ICORE 1765 -#define MACH_TYPE_MSS2 1766 -#define MACH_TYPE_BELMONT 1767 -#define MACH_TYPE_ASUSP525 1768 -#define MACH_TYPE_LB88RC8480 1769 -#define MACH_TYPE_HIPXA 1770 -#define MACH_TYPE_MX25_3DS 1771 -#define MACH_TYPE_M800 1772 -#define MACH_TYPE_OMAP3530_LV_SOM 1773 -#define MACH_TYPE_PRIMA_EVB 1774 -#define MACH_TYPE_MX31BT1 1775 -#define MACH_TYPE_ATLAS4_EVB 1776 -#define MACH_TYPE_MX31CICADA 1777 -#define MACH_TYPE_MI424WR 1778 -#define MACH_TYPE_AXS_ULTRAX 1779 -#define MACH_TYPE_AT572D940DEB 1780 -#define MACH_TYPE_DAVINCI_DA830_EVM 1781 -#define MACH_TYPE_EP9302 1782 -#define MACH_TYPE_AT572D940HFEB 1783 -#define MACH_TYPE_CYBOOK3 1784 -#define MACH_TYPE_WDG002 1785 -#define MACH_TYPE_SG560ADSL 1786 -#define MACH_TYPE_NEXTIO_N2800_ICA 1787 -#define MACH_TYPE_DOVE_DB 1788 -#define MACH_TYPE_MARVELL_NEWDB 1789 -#define MACH_TYPE_VANDIHUD 1790 -#define MACH_TYPE_MAGX_E8 1791 -#define MACH_TYPE_MAGX_Z6 1792 -#define MACH_TYPE_MAGX_V8 1793 -#define MACH_TYPE_MAGX_U9 1794 -#define MACH_TYPE_TOUGHCF08 1795 -#define MACH_TYPE_ZW4400 1796 -#define MACH_TYPE_MARAT91 1797 -#define MACH_TYPE_OVERO 1798 -#define MACH_TYPE_AT2440EVB 1799 -#define MACH_TYPE_NEOCORE926 1800 -#define MACH_TYPE_WNR854T 1801 -#define MACH_TYPE_IMX27 1802 -#define MACH_TYPE_MOOSE_DB 1803 -#define MACH_TYPE_FAB4 1804 -#define MACH_TYPE_HTCDIAMOND 1805 -#define MACH_TYPE_FIONA 1806 -#define MACH_TYPE_MXC30030_X 1807 -#define MACH_TYPE_BMP1000 1808 -#define MACH_TYPE_LOGI9200 1809 -#define MACH_TYPE_TQMA31 1810 -#define MACH_TYPE_CCW9P9215JS 1811 -#define MACH_TYPE_RD88F5181L_GE 1812 -#define MACH_TYPE_SIFMAIN 1813 -#define MACH_TYPE_SAM9_L9261 1814 -#define MACH_TYPE_CC9M2443 1815 -#define MACH_TYPE_XARIA300 1816 -#define MACH_TYPE_IT9200 1817 -#define MACH_TYPE_RD88F5181L_FXO 1818 -#define MACH_TYPE_KRISS_SENSOR 1819 -#define MACH_TYPE_PILZ_PMI5 1820 -#define MACH_TYPE_JADE 1821 -#define MACH_TYPE_KS8695_SOFTPLC 1822 -#define MACH_TYPE_GPRISC3 1823 -#define MACH_TYPE_STAMP9G20 1824 -#define MACH_TYPE_SMDK6430 1825 -#define MACH_TYPE_SMDKC100 1826 -#define MACH_TYPE_TAVOREVB 1827 -#define MACH_TYPE_SAAR 1828 -#define MACH_TYPE_DEISTER_EYECAM 1829 -#define MACH_TYPE_AT91SAM9M10G45EK 1830 -#define MACH_TYPE_LINKSTATION_PRODUO 1831 -#define MACH_TYPE_HIT_B0 1832 -#define MACH_TYPE_ADX_RMU 1833 -#define MACH_TYPE_XG_CPE_MAIN 1834 -#define MACH_TYPE_EDB9407A 1835 -#define MACH_TYPE_DTB9608 1836 -#define MACH_TYPE_EM104V1 1837 -#define MACH_TYPE_DEMO 1838 -#define MACH_TYPE_LOGI9260 1839 -#define MACH_TYPE_MX31_EXM32 1840 -#define MACH_TYPE_USB_A9G20 1841 -#define MACH_TYPE_PICPROJE2008 1842 -#define MACH_TYPE_CS_E9315 1843 -#define MACH_TYPE_QIL_A9G20 1844 -#define MACH_TYPE_SHA_PON020 1845 -#define MACH_TYPE_NAD 1846 -#define MACH_TYPE_SBC35_A9260 1847 -#define MACH_TYPE_SBC35_A9G20 1848 -#define MACH_TYPE_DAVINCI_BEGINNING 1849 -#define MACH_TYPE_UWC 1850 -#define MACH_TYPE_MXLADS 1851 -#define MACH_TYPE_HTCNIKE 1852 -#define MACH_TYPE_DEISTER_PXA270 1853 -#define MACH_TYPE_CME9210JS 1854 -#define MACH_TYPE_CC9P9360 1855 -#define MACH_TYPE_MOCHA 1856 -#define MACH_TYPE_WAPD170AG 1857 -#define MACH_TYPE_LINKSTATION_MINI 1858 -#define MACH_TYPE_AFEB9260 1859 -#define MACH_TYPE_W90X900 1860 -#define MACH_TYPE_W90X700 1861 -#define MACH_TYPE_KT300IP 1862 -#define MACH_TYPE_KT300IP_G20 1863 -#define MACH_TYPE_SRCM 1864 -#define MACH_TYPE_WLNX_9260 1865 -#define MACH_TYPE_OPENMOKO_GTA03 1866 -#define MACH_TYPE_OSPREY2 1867 -#define MACH_TYPE_KBIO9260 1868 -#define MACH_TYPE_GINZA 1869 -#define MACH_TYPE_A636N 1870 -#define MACH_TYPE_IMX27IPCAM 1871 -#define MACH_TYPE_NEMOC 1872 -#define MACH_TYPE_GENEVA 1873 -#define MACH_TYPE_HTCPHAROS 1874 -#define MACH_TYPE_NEONC 1875 -#define MACH_TYPE_NAS7100 1876 -#define MACH_TYPE_TEUPHONE 1877 -#define MACH_TYPE_ANNAX_ETH2 1878 -#define MACH_TYPE_CSB733 1879 -#define MACH_TYPE_BK3 1880 -#define MACH_TYPE_OMAP_EM32 1881 -#define MACH_TYPE_ET9261CP 1882 -#define MACH_TYPE_JASPERC 1883 -#define MACH_TYPE_ISSI_ARM9 1884 -#define MACH_TYPE_UED 1885 -#define MACH_TYPE_ESIBLADE 1886 -#define MACH_TYPE_EYE02 1887 -#define MACH_TYPE_IMX27KBD 1888 -#define MACH_TYPE_SST61VC010_FPGA 1889 -#define MACH_TYPE_KIXVP435 1890 -#define MACH_TYPE_KIXNP435 1891 -#define MACH_TYPE_AFRICA 1892 -#define MACH_TYPE_NH233 1893 -#define MACH_TYPE_RD88F6183AP_GE 1894 -#define MACH_TYPE_BCM4760 1895 -#define MACH_TYPE_EDDY_V2 1896 -#define MACH_TYPE_REALVIEW_PBA8 1897 -#define MACH_TYPE_HID_A7 1898 -#define MACH_TYPE_HERO 1899 -#define MACH_TYPE_OMAP_POSEIDON 1900 -#define MACH_TYPE_REALVIEW_PBX 1901 -#define MACH_TYPE_MICRO9S 1902 -#define MACH_TYPE_MAKO 1903 -#define MACH_TYPE_XDAFLAME 1904 -#define MACH_TYPE_PHIDGET_SBC2 1905 -#define MACH_TYPE_LIMESTONE 1906 -#define MACH_TYPE_IPROBE_C32 1907 -#define MACH_TYPE_RUT100 1908 -#define MACH_TYPE_ASUSP535 1909 -#define MACH_TYPE_HTCRAPHAEL 1910 -#define MACH_TYPE_SYGDG1 1911 -#define MACH_TYPE_SYGDG2 1912 -#define MACH_TYPE_SEOUL 1913 -#define MACH_TYPE_SALERNO 1914 -#define MACH_TYPE_UCN_S3C64XX 1915 -#define MACH_TYPE_MSM7201A 1916 -#define MACH_TYPE_LPR1 1917 -#define MACH_TYPE_ARMADILLO500FX 1918 -#define MACH_TYPE_G3EVM 1919 -#define MACH_TYPE_Z3_DM355 1920 -#define MACH_TYPE_W90P910EVB 1921 -#define MACH_TYPE_W90P920EVB 1922 -#define MACH_TYPE_W90P950EVB 1923 -#define MACH_TYPE_W90N960EVB 1924 -#define MACH_TYPE_CAMHD 1925 -#define MACH_TYPE_MVC100 1926 -#define MACH_TYPE_ELECTRUM_200 1927 -#define MACH_TYPE_HTCJADE 1928 -#define MACH_TYPE_MEMPHIS 1929 -#define MACH_TYPE_IMX27SBC 1930 -#define MACH_TYPE_LEXTAR 1931 -#define MACH_TYPE_MV88F6281GTW_GE 1932 -#define MACH_TYPE_NCP 1933 -#define MACH_TYPE_Z32AN 1934 -#define MACH_TYPE_TMQ_CAPD 1935 -#define MACH_TYPE_OMAP3_WL 1936 -#define MACH_TYPE_CHUMBY 1937 -#define MACH_TYPE_ATSARM9 1938 -#define MACH_TYPE_DAVINCI_DM365_EVM 1939 -#define MACH_TYPE_BAHAMAS 1940 -#define MACH_TYPE_DAS 1941 -#define MACH_TYPE_MINIDAS 1942 -#define MACH_TYPE_VK1000 1943 -#define MACH_TYPE_CENTRO 1944 -#define MACH_TYPE_CTERA_2BAY 1945 -#define MACH_TYPE_EDGECONNECT 1946 -#define MACH_TYPE_ND27000 1947 -#define MACH_TYPE_GEMALTO_COBRA 1948 -#define MACH_TYPE_INGELABS_COMET 1949 -#define MACH_TYPE_POLLUX_WIZ 1950 -#define MACH_TYPE_BLACKSTONE 1951 -#define MACH_TYPE_TOPAZ 1952 -#define MACH_TYPE_AIXLE 1953 -#define MACH_TYPE_MW998 1954 -#define MACH_TYPE_NOKIA_RX51 1955 -#define MACH_TYPE_VSC5605EV 1956 -#define MACH_TYPE_NT98700DK 1957 -#define MACH_TYPE_ICONTACT 1958 -#define MACH_TYPE_SWARCO_FRCPU 1959 -#define MACH_TYPE_SWARCO_SCPU 1960 -#define MACH_TYPE_BBOX_P16 1961 -#define MACH_TYPE_BSTD 1962 -#define MACH_TYPE_SBC2440II 1963 -#define MACH_TYPE_PCM034 1964 -#define MACH_TYPE_NESO 1965 -#define MACH_TYPE_WLNX_9G20 1966 -#define MACH_TYPE_OMAP_ZOOM2 1967 -#define MACH_TYPE_TOTEMNOVA 1968 -#define MACH_TYPE_C5000 1969 -#define MACH_TYPE_UNIPO_AT91SAM9263 1970 -#define MACH_TYPE_ETHERNUT5 1971 -#define MACH_TYPE_ARM11 1972 -#define MACH_TYPE_CPUAT9260 1973 -#define MACH_TYPE_CPUPXA255 1974 -#define MACH_TYPE_CPUIMX27 1975 -#define MACH_TYPE_CHEFLUX 1976 -#define MACH_TYPE_EB_CPUX9K2 1977 -#define MACH_TYPE_OPCOTEC 1978 -#define MACH_TYPE_YT 1979 -#define MACH_TYPE_MOTOQ 1980 -#define MACH_TYPE_BSB1 1981 -#define MACH_TYPE_ACS5K 1982 -#define MACH_TYPE_MILAN 1983 -#define MACH_TYPE_QUARTZV2 1984 -#define MACH_TYPE_RSVP 1985 -#define MACH_TYPE_RMP200 1986 -#define MACH_TYPE_SNAPPER_9260 1987 -#define MACH_TYPE_DSM320 1988 -#define MACH_TYPE_ADSGCM 1989 -#define MACH_TYPE_ASE2_400 1990 -#define MACH_TYPE_PIZZA 1991 -#define MACH_TYPE_SPOT_NGPL 1992 -#define MACH_TYPE_ARMATA 1993 -#define MACH_TYPE_EXEDA 1994 -#define MACH_TYPE_MX31SF005 1995 -#define MACH_TYPE_F5D8231_4_V2 1996 -#define MACH_TYPE_Q2440 1997 -#define MACH_TYPE_QQ2440 1998 -#define MACH_TYPE_MINI2440 1999 -#define MACH_TYPE_COLIBRI300 2000 -#define MACH_TYPE_JADES 2001 -#define MACH_TYPE_SPARK 2002 -#define MACH_TYPE_BENZINA 2003 -#define MACH_TYPE_BLAZE 2004 -#define MACH_TYPE_LINKSTATION_LS_HGL 2005 -#define MACH_TYPE_HTCVENUS 2006 -#define MACH_TYPE_SONY_PRS505 2007 -#define MACH_TYPE_HANLIN_V3 2008 -#define MACH_TYPE_SAPPHIRA 2009 -#define MACH_TYPE_DACK_SDA_01 2010 -#define MACH_TYPE_ARMBOX 2011 -#define MACH_TYPE_HARRIS_RVP 2012 -#define MACH_TYPE_RIBALDO 2013 -#define MACH_TYPE_AGORA 2014 -#define MACH_TYPE_OMAP3_MINI 2015 -#define MACH_TYPE_A9SAM6432_B 2016 -#define MACH_TYPE_USG2410 2017 -#define MACH_TYPE_PC72052_I10_REVB 2018 -#define MACH_TYPE_MX35_EXM32 2019 -#define MACH_TYPE_TOPAS910 2020 -#define MACH_TYPE_HYENA 2021 -#define MACH_TYPE_POSPAX 2022 -#define MACH_TYPE_HDL_GX 2023 -#define MACH_TYPE_CTERA_4BAY 2024 -#define MACH_TYPE_CTERA_PLUG_C 2025 -#define MACH_TYPE_CRWEA_PLUG_I 2026 -#define MACH_TYPE_EGAUGE2 2027 -#define MACH_TYPE_DIDJ 2028 -#define MACH_TYPE_MEISTER 2029 -#define MACH_TYPE_HTCBLACKSTONE 2030 -#define MACH_TYPE_CPUAT9G20 2031 -#define MACH_TYPE_SMDK6440 2032 -#define MACH_TYPE_OMAP_35XX_MVP 2033 -#define MACH_TYPE_CTERA_PLUG_I 2034 -#define MACH_TYPE_PVG610 2035 -#define MACH_TYPE_HPRW6815 2036 -#define MACH_TYPE_OMAP3_OSWALD 2037 -#define MACH_TYPE_NAS4220B 2038 -#define MACH_TYPE_HTCRAPHAEL_CDMA 2039 -#define MACH_TYPE_HTCDIAMOND_CDMA 2040 -#define MACH_TYPE_SCALER 2041 -#define MACH_TYPE_ZYLONITE2 2042 -#define MACH_TYPE_ASPENITE 2043 -#define MACH_TYPE_TETON 2044 -#define MACH_TYPE_TTC_DKB 2045 -#define MACH_TYPE_BISHOP2 2046 -#define MACH_TYPE_IPPV5 2047 -#define MACH_TYPE_FARM926 2048 -#define MACH_TYPE_MMCCPU 2049 -#define MACH_TYPE_SGMSFL 2050 -#define MACH_TYPE_TT8000 2051 -#define MACH_TYPE_ZRN4300LP 2052 -#define MACH_TYPE_MPTC 2053 -#define MACH_TYPE_H6051 2054 -#define MACH_TYPE_PVG610_101 2055 -#define MACH_TYPE_STAMP9261_PC_EVB 2056 -#define MACH_TYPE_PELCO_ODYSSEUS 2057 -#define MACH_TYPE_TNY_A9260 2058 -#define MACH_TYPE_TNY_A9G20 2059 -#define MACH_TYPE_AESOP_MP2530F 2060 -#define MACH_TYPE_DX900 2061 -#define MACH_TYPE_CPODC2 2062 -#define MACH_TYPE_TILT_8925 2063 -#define MACH_TYPE_DAVINCI_DM357_EVM 2064 -#define MACH_TYPE_SWORDFISH 2065 -#define MACH_TYPE_CORVUS 2066 -#define MACH_TYPE_TAURUS 2067 -#define MACH_TYPE_AXM 2068 -#define MACH_TYPE_AXC 2069 -#define MACH_TYPE_BABY 2070 -#define MACH_TYPE_MP200 2071 -#define MACH_TYPE_PCM043 2072 -#define MACH_TYPE_HANLIN_V3C 2073 -#define MACH_TYPE_KBK9G20 2074 -#define MACH_TYPE_ADSTURBOG5 2075 -#define MACH_TYPE_AVENGER_LITE1 2076 -#define MACH_TYPE_SUC 2077 -#define MACH_TYPE_AT91SAM7S256 2078 -#define MACH_TYPE_MENDOZA 2079 -#define MACH_TYPE_KIRA 2080 -#define MACH_TYPE_MX1HBM 2081 -#define MACH_TYPE_QUATRO43XX 2082 -#define MACH_TYPE_QUATRO4230 2083 -#define MACH_TYPE_NSB400 2084 -#define MACH_TYPE_DRP255 2085 -#define MACH_TYPE_THOTH 2086 -#define MACH_TYPE_FIRESTONE 2087 -#define MACH_TYPE_ASUSP750 2088 -#define MACH_TYPE_CTERA_DL 2089 -#define MACH_TYPE_SOCR 2090 -#define MACH_TYPE_HTCOXYGEN 2091 -#define MACH_TYPE_HEROC 2092 -#define MACH_TYPE_ZENO6800 2093 -#define MACH_TYPE_SC2MCS 2094 -#define MACH_TYPE_GENE100 2095 -#define MACH_TYPE_AS353X 2096 -#define MACH_TYPE_SHEEVAPLUG 2097 -#define MACH_TYPE_AT91SAM9G20 2098 -#define MACH_TYPE_MV88F6192GTW_FE 2099 -#define MACH_TYPE_CC9200 2100 -#define MACH_TYPE_SM9200 2101 -#define MACH_TYPE_TP9200 2102 -#define MACH_TYPE_SNAPPERDV 2103 -#define MACH_TYPE_AVENGERS_LITE 2104 -#define MACH_TYPE_AVENGERS_LITE1 2105 -#define MACH_TYPE_OMAP3AXON 2106 -#define MACH_TYPE_MA8XX 2107 -#define MACH_TYPE_MP201EK 2108 -#define MACH_TYPE_DAVINCI_TUX 2109 -#define MACH_TYPE_MPA1600 2110 -#define MACH_TYPE_PELCO_TROY 2111 -#define MACH_TYPE_NSB667 2112 -#define MACH_TYPE_ROVERS5_4MPIX 2113 -#define MACH_TYPE_TWOCOM 2114 -#define MACH_TYPE_UBISYS_P9_RCU3R2 2115 -#define MACH_TYPE_HERO_ESPRESSO 2116 -#define MACH_TYPE_AFEUSB 2117 -#define MACH_TYPE_T830 2118 -#define MACH_TYPE_SPD8020_CC 2119 -#define MACH_TYPE_OM_3D7K 2120 -#define MACH_TYPE_PICOCOM2 2121 -#define MACH_TYPE_UWG4MX27 2122 -#define MACH_TYPE_UWG4MX31 2123 -#define MACH_TYPE_CHERRY 2124 -#define MACH_TYPE_MX51_BABBAGE 2125 -#define MACH_TYPE_S3C2440TURKIYE 2126 -#define MACH_TYPE_TX37 2127 -#define MACH_TYPE_SBC2800_9G20 2128 -#define MACH_TYPE_BENZGLB 2129 -#define MACH_TYPE_BENZTD 2130 -#define MACH_TYPE_CARTESIO_PLUS 2131 -#define MACH_TYPE_SOLRAD_G20 2132 -#define MACH_TYPE_MX27WALLACE 2133 -#define MACH_TYPE_FMZWEBMODUL 2134 -#define MACH_TYPE_RD78X00_MASA 2135 -#define MACH_TYPE_SMALLOGGER 2136 -#define MACH_TYPE_CCW9P9215 2137 -#define MACH_TYPE_DM355_LEOPARD 2138 -#define MACH_TYPE_TS219 2139 -#define MACH_TYPE_TNY_A9263 2140 -#define MACH_TYPE_APOLLO 2141 -#define MACH_TYPE_AT91CAP9STK 2142 -#define MACH_TYPE_SPC300 2143 -#define MACH_TYPE_EKO 2144 -#define MACH_TYPE_CCW9M2443 2145 -#define MACH_TYPE_CCW9M2443JS 2146 -#define MACH_TYPE_M2M_ROUTER_DEVICE 2147 -#define MACH_TYPE_STAR9104NAS 2148 -#define MACH_TYPE_PCA100 2149 -#define MACH_TYPE_Z3_DM365_MOD_01 2150 -#define MACH_TYPE_HIPOX 2151 -#define MACH_TYPE_OMAP3_PITEDS 2152 -#define MACH_TYPE_BM150R 2153 -#define MACH_TYPE_TBONE 2154 -#define MACH_TYPE_MERLIN 2155 -#define MACH_TYPE_FALCON 2156 -#define MACH_TYPE_DAVINCI_DA850_EVM 2157 -#define MACH_TYPE_S5P6440 2158 -#define MACH_TYPE_AT91SAM9G10EK 2159 -#define MACH_TYPE_OMAP_4430SDP 2160 -#define MACH_TYPE_LPC313X 2161 -#define MACH_TYPE_MAGX_ZN5 2162 -#define MACH_TYPE_MAGX_EM30 2163 -#define MACH_TYPE_MAGX_VE66 2164 -#define MACH_TYPE_MEESC 2165 -#define MACH_TYPE_OTC570 2166 -#define MACH_TYPE_BCU2412 2167 -#define MACH_TYPE_BEACON 2168 -#define MACH_TYPE_ACTIA_TGW 2169 -#define MACH_TYPE_E4430 2170 -#define MACH_TYPE_QL300 2171 -#define MACH_TYPE_BTMAVB101 2172 -#define MACH_TYPE_BTMAWB101 2173 -#define MACH_TYPE_SQ201 2174 -#define MACH_TYPE_QUATRO45XX 2175 -#define MACH_TYPE_OPENPAD 2176 -#define MACH_TYPE_TX25 2177 -#define MACH_TYPE_OMAP3_TORPEDO 2178 -#define MACH_TYPE_HTCRAPHAEL_K 2179 -#define MACH_TYPE_LAL43 2181 -#define MACH_TYPE_HTCRAPHAEL_CDMA500 2182 -#define MACH_TYPE_ANW6410 2183 -#define MACH_TYPE_HTCPROPHET 2185 -#define MACH_TYPE_CFA_10022 2186 -#define MACH_TYPE_IMX27_VISSTRIM_M10 2187 -#define MACH_TYPE_PX2IMX27 2188 -#define MACH_TYPE_STM3210E_EVAL 2189 -#define MACH_TYPE_DVS10 2190 -#define MACH_TYPE_PORTUXG20 2191 -#define MACH_TYPE_ARM_SPV 2192 -#define MACH_TYPE_SMDKC110 2193 -#define MACH_TYPE_CABESPRESSO 2194 -#define MACH_TYPE_HMC800 2195 -#define MACH_TYPE_SHOLES 2196 -#define MACH_TYPE_BTMXC31 2197 -#define MACH_TYPE_DT501 2198 -#define MACH_TYPE_KTX 2199 -#define MACH_TYPE_OMAP3517EVM 2200 -#define MACH_TYPE_NETSPACE_V2 2201 -#define MACH_TYPE_NETSPACE_MAX_V2 2202 -#define MACH_TYPE_D2NET_V2 2203 -#define MACH_TYPE_NET2BIG_V2 2204 -#define MACH_TYPE_NET4BIG_V2 2205 -#define MACH_TYPE_NET5BIG_V2 2206 -#define MACH_TYPE_ENDB2443 2207 -#define MACH_TYPE_INETSPACE_V2 2208 -#define MACH_TYPE_TROS 2209 -#define MACH_TYPE_PELCO_HOMER 2210 -#define MACH_TYPE_OFSP8 2211 -#define MACH_TYPE_AT91SAM9G45EKES 2212 -#define MACH_TYPE_GUF_CUPID 2213 -#define MACH_TYPE_EAB1R 2214 -#define MACH_TYPE_DESIREC 2215 -#define MACH_TYPE_CORDOBA 2216 -#define MACH_TYPE_IRVINE 2217 -#define MACH_TYPE_SFF772 2218 -#define MACH_TYPE_PELCO_MILANO 2219 -#define MACH_TYPE_PC7302 2220 -#define MACH_TYPE_BIP6000 2221 -#define MACH_TYPE_SILVERMOON 2222 -#define MACH_TYPE_VC0830 2223 -#define MACH_TYPE_DT430 2224 -#define MACH_TYPE_JI42PF 2225 -#define MACH_TYPE_GNET_KSM 2226 -#define MACH_TYPE_GNET_SGM 2227 -#define MACH_TYPE_GNET_SGR 2228 -#define MACH_TYPE_OMAP3_ICETEKEVM 2229 -#define MACH_TYPE_PNP 2230 -#define MACH_TYPE_CTERA_2BAY_K 2231 -#define MACH_TYPE_CTERA_2BAY_U 2232 -#define MACH_TYPE_SAS_C 2233 -#define MACH_TYPE_VMA2315 2234 -#define MACH_TYPE_VCS 2235 -#define MACH_TYPE_SPEAR600 2236 -#define MACH_TYPE_SPEAR300 2237 -#define MACH_TYPE_SPEAR1300 2238 -#define MACH_TYPE_LILLY1131 2239 -#define MACH_TYPE_ARVOO_AX301 2240 -#define MACH_TYPE_MAPPHONE 2241 -#define MACH_TYPE_LEGEND 2242 -#define MACH_TYPE_SALSA 2243 -#define MACH_TYPE_LOUNGE 2244 -#define MACH_TYPE_VISION 2245 -#define MACH_TYPE_VMB20 2246 -#define MACH_TYPE_HY2410 2247 -#define MACH_TYPE_HY9315 2248 -#define MACH_TYPE_BULLWINKLE 2249 -#define MACH_TYPE_ARM_ULTIMATOR2 2250 -#define MACH_TYPE_VS_V210 2252 -#define MACH_TYPE_VS_V212 2253 -#define MACH_TYPE_HMT 2254 -#define MACH_TYPE_SUEN3 2255 -#define MACH_TYPE_VESPER 2256 -#define MACH_TYPE_STR9 2257 -#define MACH_TYPE_OMAP3_WL_FF 2258 -#define MACH_TYPE_SIMCOM 2259 -#define MACH_TYPE_MCWEBIO 2260 -#define MACH_TYPE_OMAP3_PHRAZER 2261 -#define MACH_TYPE_DARWIN 2262 -#define MACH_TYPE_ORATISCOMU 2263 -#define MACH_TYPE_RTSBC20 2264 -#define MACH_TYPE_I780 2265 -#define MACH_TYPE_GEMINI324 2266 -#define MACH_TYPE_ORATISLAN 2267 -#define MACH_TYPE_ORATISALOG 2268 -#define MACH_TYPE_ORATISMADI 2269 -#define MACH_TYPE_ORATISOT16 2270 -#define MACH_TYPE_ORATISDESK 2271 -#define MACH_TYPE_VEXPRESS 2272 -#define MACH_TYPE_SINTEXO 2273 -#define MACH_TYPE_CM3389 2274 -#define MACH_TYPE_OMAP3_CIO 2275 -#define MACH_TYPE_SGH_I900 2276 -#define MACH_TYPE_BST100 2277 -#define MACH_TYPE_PASSION 2278 -#define MACH_TYPE_INDESIGN_AT91SAM 2279 -#define MACH_TYPE_C4_BADGER 2280 -#define MACH_TYPE_C4_VIPER 2281 -#define MACH_TYPE_D2NET 2282 -#define MACH_TYPE_BIGDISK 2283 -#define MACH_TYPE_NOTALVISION 2284 -#define MACH_TYPE_OMAP3_KBOC 2285 -#define MACH_TYPE_CYCLONE 2286 -#define MACH_TYPE_NINJA 2287 -#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288 -#define MACH_TYPE_BCMRING 2289 -#define MACH_TYPE_RESOL_DL2 2290 -#define MACH_TYPE_IFOSW 2291 -#define MACH_TYPE_HTCRHODIUM 2292 -#define MACH_TYPE_HTCTOPAZ 2293 -#define MACH_TYPE_MATRIX504 2294 -#define MACH_TYPE_MRFSA 2295 -#define MACH_TYPE_SC_P270 2296 -#define MACH_TYPE_ATLAS5_EVB 2297 -#define MACH_TYPE_PELCO_LOBOX 2298 -#define MACH_TYPE_DILAX_PCU200 2299 -#define MACH_TYPE_LEONARDO 2300 -#define MACH_TYPE_ZORAN_APPROACH7 2301 -#define MACH_TYPE_DP6XX 2302 -#define MACH_TYPE_BCM2153_VESPER 2303 -#define MACH_TYPE_MAHIMAHI 2304 -#define MACH_TYPE_CLICKC 2305 -#define MACH_TYPE_ZB_GATEWAY 2306 -#define MACH_TYPE_TAZCARD 2307 -#define MACH_TYPE_TAZDEV 2308 -#define MACH_TYPE_ANNAX_CB_ARM 2309 -#define MACH_TYPE_ANNAX_DM3 2310 -#define MACH_TYPE_CEREBRIC 2311 -#define MACH_TYPE_ORCA 2312 -#define MACH_TYPE_PC9260 2313 -#define MACH_TYPE_EMS285A 2314 -#define MACH_TYPE_GEC2410 2315 -#define MACH_TYPE_GEC2440 2316 -#define MACH_TYPE_ARCH_MW903 2317 -#define MACH_TYPE_MW2440 2318 -#define MACH_TYPE_ECAC2378 2319 -#define MACH_TYPE_TAZKIOSK 2320 -#define MACH_TYPE_WHITERABBIT_MCH 2321 -#define MACH_TYPE_SBOX9263 2322 -#define MACH_TYPE_OREO 2323 -#define MACH_TYPE_SMDK6442 2324 -#define MACH_TYPE_OPENRD_BASE 2325 -#define MACH_TYPE_INCREDIBLE 2326 -#define MACH_TYPE_INCREDIBLEC 2327 -#define MACH_TYPE_HEROCT 2328 -#define MACH_TYPE_MMNET1000 2329 -#define MACH_TYPE_DEVKIT8000 2330 -#define MACH_TYPE_DEVKIT9000 2331 -#define MACH_TYPE_MX31TXTR 2332 -#define MACH_TYPE_U380 2333 -#define MACH_TYPE_HUALU_BOARD 2334 -#define MACH_TYPE_NPCMX50 2335 -#define MACH_TYPE_MX51_LANGE51 2336 -#define MACH_TYPE_MX51_LANGE52 2337 -#define MACH_TYPE_RIOM 2338 -#define MACH_TYPE_COMCAS 2339 -#define MACH_TYPE_WSI_MX27 2340 -#define MACH_TYPE_CM_T35 2341 -#define MACH_TYPE_NET2BIG 2342 -#define MACH_TYPE_MOTOROLA_A1600 2343 -#define MACH_TYPE_IGEP0020 2344 -#define MACH_TYPE_IGEP0010 2345 -#define MACH_TYPE_MV6281GTWGE2 2346 -#define MACH_TYPE_SCAT100 2347 -#define MACH_TYPE_SANMINA 2348 -#define MACH_TYPE_MOMENTO 2349 -#define MACH_TYPE_NUC9XX 2350 -#define MACH_TYPE_NUC910EVB 2351 -#define MACH_TYPE_NUC920EVB 2352 -#define MACH_TYPE_NUC950EVB 2353 -#define MACH_TYPE_NUC945EVB 2354 -#define MACH_TYPE_NUC960EVB 2355 -#define MACH_TYPE_NUC932EVB 2356 -#define MACH_TYPE_NUC900 2357 -#define MACH_TYPE_SD1SOC 2358 -#define MACH_TYPE_LN2440BC 2359 -#define MACH_TYPE_RSBC 2360 -#define MACH_TYPE_OPENRD_CLIENT 2361 -#define MACH_TYPE_HPIPAQ11X 2362 -#define MACH_TYPE_WAYLAND 2363 -#define MACH_TYPE_ACNBSX102 2364 -#define MACH_TYPE_HWAT91 2365 -#define MACH_TYPE_AT91SAM9263CS 2366 -#define MACH_TYPE_CSB732 2367 -#define MACH_TYPE_U8500 2368 -#define MACH_TYPE_HUQIU 2369 -#define MACH_TYPE_MX51_KUNLUN 2370 -#define MACH_TYPE_PMT1G 2371 -#define MACH_TYPE_HTCELF 2372 -#define MACH_TYPE_ARMADILLO420 2373 -#define MACH_TYPE_ARMADILLO440 2374 -#define MACH_TYPE_U_CHIP_DUAL_ARM 2375 -#define MACH_TYPE_CSR_BDB3 2376 -#define MACH_TYPE_DOLBY_CAT1018 2377 -#define MACH_TYPE_HY9307 2378 -#define MACH_TYPE_A_ES 2379 -#define MACH_TYPE_DAVINCI_IRIF 2380 -#define MACH_TYPE_AGAMA9263 2381 -#define MACH_TYPE_MARVELL_JASPER 2382 -#define MACH_TYPE_FLINT 2383 -#define MACH_TYPE_TAVOREVB3 2384 -#define MACH_TYPE_SCH_M490 2386 -#define MACH_TYPE_RBL01 2387 -#define MACH_TYPE_OMNIFI 2388 -#define MACH_TYPE_OTAVALO 2389 -#define MACH_TYPE_SIENNA 2390 -#define MACH_TYPE_HTC_EXCALIBUR_S620 2391 -#define MACH_TYPE_HTC_OPAL 2392 -#define MACH_TYPE_TOUCHBOOK 2393 -#define MACH_TYPE_LATTE 2394 -#define MACH_TYPE_XA200 2395 -#define MACH_TYPE_NIMROD 2396 -#define MACH_TYPE_CC9P9215_3G 2397 -#define MACH_TYPE_CC9P9215_3GJS 2398 -#define MACH_TYPE_TK71 2399 -#define MACH_TYPE_COMHAM3525 2400 -#define MACH_TYPE_MX31EREBUS 2401 -#define MACH_TYPE_MCARDMX27 2402 -#define MACH_TYPE_PARADISE 2403 -#define MACH_TYPE_TIDE 2404 -#define MACH_TYPE_WZL2440 2405 -#define MACH_TYPE_SDRDEMO 2406 -#define MACH_TYPE_ETHERCAN2 2407 -#define MACH_TYPE_ECMIMG20 2408 -#define MACH_TYPE_OMAP_DRAGON 2409 -#define MACH_TYPE_HALO 2410 -#define MACH_TYPE_HUANGSHAN 2411 -#define MACH_TYPE_VL_MA2SC 2412 -#define MACH_TYPE_RAUMFELD_RC 2413 -#define MACH_TYPE_RAUMFELD_CONNECTOR 2414 -#define MACH_TYPE_RAUMFELD_SPEAKER 2415 -#define MACH_TYPE_MULTIBUS_MASTER 2416 -#define MACH_TYPE_MULTIBUS_PBK 2417 -#define MACH_TYPE_TNETV107X 2418 -#define MACH_TYPE_SNAKE 2419 -#define MACH_TYPE_CWMX27 2420 -#define MACH_TYPE_SCH_M480 2421 -#define MACH_TYPE_PLATYPUS 2422 -#define MACH_TYPE_PSS2 2423 -#define MACH_TYPE_DAVINCI_APM150 2424 -#define MACH_TYPE_STR9100 2425 -#define MACH_TYPE_NET5BIG 2426 -#define MACH_TYPE_SEABED9263 2427 -#define MACH_TYPE_MX51_M2ID 2428 -#define MACH_TYPE_OCTVOCPLUS_EB 2429 -#define MACH_TYPE_KLK_FIREFOX 2430 -#define MACH_TYPE_KLK_WIRMA_MODULE 2431 -#define MACH_TYPE_KLK_WIRMA_MMI 2432 -#define MACH_TYPE_SUPERSONIC 2433 -#define MACH_TYPE_LIBERTY 2434 -#define MACH_TYPE_MH355 2435 -#define MACH_TYPE_PC7802 2436 -#define MACH_TYPE_GNET_SGC 2437 -#define MACH_TYPE_EINSTEIN15 2438 -#define MACH_TYPE_CMPD 2439 -#define MACH_TYPE_DAVINCI_HASE1 2440 -#define MACH_TYPE_LGEINCITEPHONE 2441 -#define MACH_TYPE_EA313X 2442 -#define MACH_TYPE_FWBD_39064 2443 -#define MACH_TYPE_FWBD_390128 2444 -#define MACH_TYPE_PELCO_MOE 2445 -#define MACH_TYPE_MINIMIX27 2446 -#define MACH_TYPE_OMAP3_THUNDER 2447 -#define MACH_TYPE_PASSIONC 2448 -#define MACH_TYPE_MX27AMATA 2449 -#define MACH_TYPE_BGAT1 2450 -#define MACH_TYPE_BUZZ 2451 -#define MACH_TYPE_MB9G20 2452 -#define MACH_TYPE_YUSHAN 2453 -#define MACH_TYPE_LIZARD 2454 -#define MACH_TYPE_OMAP3POLYCOM 2455 -#define MACH_TYPE_SMDKV210 2456 -#define MACH_TYPE_BRAVO 2457 -#define MACH_TYPE_SIOGENTOO1 2458 -#define MACH_TYPE_SIOGENTOO2 2459 -#define MACH_TYPE_SM3K 2460 -#define MACH_TYPE_ACER_TEMPO_F900 2461 -#define MACH_TYPE_SST61VC010_DEV 2462 -#define MACH_TYPE_GLITTERTIND 2463 -#define MACH_TYPE_OMAP_ZOOM3 2464 -#define MACH_TYPE_OMAP_3630SDP 2465 -#define MACH_TYPE_CYBOOK2440 2466 -#define MACH_TYPE_TORINO_S 2467 -#define MACH_TYPE_HAVANA 2468 -#define MACH_TYPE_BEAUMONT_11 2469 -#define MACH_TYPE_VANGUARD 2470 -#define MACH_TYPE_S5PC110_DRACO 2471 -#define MACH_TYPE_CARTESIO_TWO 2472 -#define MACH_TYPE_ASTER 2473 -#define MACH_TYPE_VOGUESV210 2474 -#define MACH_TYPE_ACM500X 2475 -#define MACH_TYPE_KM9260 2476 -#define MACH_TYPE_NIDEFLEXG1 2477 -#define MACH_TYPE_CTERA_PLUG_IO 2478 -#define MACH_TYPE_SMARTQ7 2479 -#define MACH_TYPE_AT91SAM9G10EK2 2480 -#define MACH_TYPE_ASUSP527 2481 -#define MACH_TYPE_AT91SAM9G20MPM2 2482 -#define MACH_TYPE_TOPASA900 2483 -#define MACH_TYPE_ELECTRUM_100 2484 -#define MACH_TYPE_MX51GRB 2485 -#define MACH_TYPE_XEA300 2486 -#define MACH_TYPE_HTCSTARTREK 2487 -#define MACH_TYPE_LIMA 2488 -#define MACH_TYPE_CSB740 2489 -#define MACH_TYPE_USB_S8815 2490 -#define MACH_TYPE_WATSON_EFM_PLUGIN 2491 -#define MACH_TYPE_MILKYWAY 2492 -#define MACH_TYPE_G4EVM 2493 -#define MACH_TYPE_PICOMOD6 2494 -#define MACH_TYPE_OMAPL138_HAWKBOARD 2495 -#define MACH_TYPE_IP6000 2496 -#define MACH_TYPE_IP6010 2497 -#define MACH_TYPE_UTM400 2498 -#define MACH_TYPE_OMAP3_ZYBEX 2499 -#define MACH_TYPE_WIRELESS_SPACE 2500 -#define MACH_TYPE_SX560 2501 -#define MACH_TYPE_TS41X 2502 -#define MACH_TYPE_ELPHEL10373 2503 -#define MACH_TYPE_RHOBOT 2504 -#define MACH_TYPE_MX51_REFRESH 2505 -#define MACH_TYPE_LS9260 2506 -#define MACH_TYPE_SHANK 2507 -#define MACH_TYPE_QSD8X50_ST1 2508 -#define MACH_TYPE_AT91SAM9M10EKES 2509 -#define MACH_TYPE_HIRAM 2510 -#define MACH_TYPE_PHY3250 2511 -#define MACH_TYPE_EA3250 2512 -#define MACH_TYPE_FDI3250 2513 -#define MACH_TYPE_WHITESTONE 2514 -#define MACH_TYPE_AT91SAM9263NIT 2515 -#define MACH_TYPE_CCMX51 2516 -#define MACH_TYPE_CCMX51JS 2517 -#define MACH_TYPE_CCWMX51 2518 -#define MACH_TYPE_CCWMX51JS 2519 -#define MACH_TYPE_MINI6410 2520 -#define MACH_TYPE_TINY6410 2521 -#define MACH_TYPE_NANO6410 2522 -#define MACH_TYPE_AT572D940HFNLDB 2523 -#define MACH_TYPE_HTCLEO 2524 -#define MACH_TYPE_AVP13 2525 -#define MACH_TYPE_XXSVIDEOD 2526 -#define MACH_TYPE_VPNEXT 2527 -#define MACH_TYPE_SWARCO_ITC3 2528 -#define MACH_TYPE_TX51 2529 -#define MACH_TYPE_DOLBY_CAT1021 2530 -#define MACH_TYPE_MX28EVK 2531 -#define MACH_TYPE_PHOENIX260 2532 -#define MACH_TYPE_UVACA_STORK 2533 -#define MACH_TYPE_SMARTQ5 2534 -#define MACH_TYPE_ALL3078 2535 -#define MACH_TYPE_CTERA_2BAY_DS 2536 -#define MACH_TYPE_SIOGENTOO3 2537 -#define MACH_TYPE_EPB5000 2538 -#define MACH_TYPE_HY9263 2539 -#define MACH_TYPE_ACER_TEMPO_M900 2540 -#define MACH_TYPE_ACER_TEMPO_DX900 2541 -#define MACH_TYPE_ACER_TEMPO_X960 2542 -#define MACH_TYPE_ACER_ETEN_V900 2543 -#define MACH_TYPE_ACER_ETEN_X900 2544 -#define MACH_TYPE_BONNELL 2545 -#define MACH_TYPE_OHT_MX27 2546 -#define MACH_TYPE_HTCQUARTZ 2547 -#define MACH_TYPE_DAVINCI_DM6467TEVM 2548 -#define MACH_TYPE_C3AX03 2549 -#define MACH_TYPE_MXT_TD60 2550 -#define MACH_TYPE_ESYX 2551 -#define MACH_TYPE_DOVE_DB2 2552 -#define MACH_TYPE_BULLDOG 2553 -#define MACH_TYPE_DERELL_ME2000 2554 -#define MACH_TYPE_BCMRING_BASE 2555 -#define MACH_TYPE_BCMRING_EVM 2556 -#define MACH_TYPE_BCMRING_EVM_JAZZ 2557 -#define MACH_TYPE_BCMRING_SP 2558 -#define MACH_TYPE_BCMRING_SV 2559 -#define MACH_TYPE_BCMRING_SV_JAZZ 2560 -#define MACH_TYPE_BCMRING_TABLET 2561 -#define MACH_TYPE_BCMRING_VP 2562 -#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563 -#define MACH_TYPE_BCMRING_SP_WQVGA 2564 -#define MACH_TYPE_BCMRING_CUSTOM 2565 -#define MACH_TYPE_ACER_S200 2566 -#define MACH_TYPE_BT270 2567 -#define MACH_TYPE_ISEO 2568 -#define MACH_TYPE_CEZANNE 2569 -#define MACH_TYPE_LUCCA 2570 -#define MACH_TYPE_SUPERSMART 2571 -#define MACH_TYPE_CS_MISANO 2572 -#define MACH_TYPE_MAGNOLIA2 2573 -#define MACH_TYPE_EMXX 2574 -#define MACH_TYPE_OUTLAW 2575 -#define MACH_TYPE_RIOT_BEI2 2576 -#define MACH_TYPE_RIOT_VOX 2577 -#define MACH_TYPE_RIOT_X37 2578 -#define MACH_TYPE_MEGA25MX 2579 -#define MACH_TYPE_BENZINA2 2580 -#define MACH_TYPE_IGNITE 2581 -#define MACH_TYPE_FOGGIA 2582 -#define MACH_TYPE_AREZZO 2583 -#define MACH_TYPE_LEICA_SKYWALKER 2584 -#define MACH_TYPE_JACINTO2_JAMR 2585 -#define MACH_TYPE_GTS_NOVA 2586 -#define MACH_TYPE_P3600 2587 -#define MACH_TYPE_DLT2 2588 -#define MACH_TYPE_DF3120 2589 -#define MACH_TYPE_ECUCORE_9G20 2590 -#define MACH_TYPE_NAUTEL_LPC3240 2591 -#define MACH_TYPE_GLACIER 2592 -#define MACH_TYPE_PHRAZER_BULLDOG 2593 -#define MACH_TYPE_OMAP3_BULLDOG 2594 -#define MACH_TYPE_PCA101 2595 -#define MACH_TYPE_BUZZC 2596 -#define MACH_TYPE_SASIE2 2597 -#define MACH_TYPE_DAVINCI_CIO 2598 -#define MACH_TYPE_SMARTMETER_DL 2599 -#define MACH_TYPE_WZL6410 2600 -#define MACH_TYPE_WZL6410M 2601 -#define MACH_TYPE_WZL6410F 2602 -#define MACH_TYPE_WZL6410I 2603 -#define MACH_TYPE_SPACECOM1 2604 -#define MACH_TYPE_PINGU920 2605 -#define MACH_TYPE_BRAVOC 2606 -#define MACH_TYPE_CYBO2440 2607 -#define MACH_TYPE_VDSSW 2608 -#define MACH_TYPE_ROMULUS 2609 -#define MACH_TYPE_OMAP_MAGIC 2610 -#define MACH_TYPE_ELTD100 2611 -#define MACH_TYPE_CAPC7117 2612 -#define MACH_TYPE_SWAN 2613 -#define MACH_TYPE_VEU 2614 -#define MACH_TYPE_RM2 2615 -#define MACH_TYPE_TT2100 2616 -#define MACH_TYPE_VENICE 2617 -#define MACH_TYPE_PC7323 2618 -#define MACH_TYPE_MASP 2619 -#define MACH_TYPE_FUJITSU_TVSTBSOC 2620 -#define MACH_TYPE_FUJITSU_TVSTBSOC1 2621 -#define MACH_TYPE_LEXIKON 2622 -#define MACH_TYPE_MINI2440V2 2623 -#define MACH_TYPE_ICONTROL 2624 -#define MACH_TYPE_SHEEVAD 2625 -#define MACH_TYPE_QSD8X50A_ST1_1 2626 -#define MACH_TYPE_QSD8X50A_ST1_5 2627 -#define MACH_TYPE_BEE 2628 -#define MACH_TYPE_MX23EVK 2629 -#define MACH_TYPE_AP4EVB 2630 -#define MACH_TYPE_STOCKHOLM 2631 -#define MACH_TYPE_LPC_H3131 2632 -#define MACH_TYPE_STINGRAY 2633 -#define MACH_TYPE_KRAKEN 2634 -#define MACH_TYPE_GW2388 2635 -#define MACH_TYPE_JADECPU 2636 -#define MACH_TYPE_CARLISLE 2637 -#define MACH_TYPE_LUX_SFT9 2638 -#define MACH_TYPE_NEMID_TB 2639 -#define MACH_TYPE_TERRIER 2640 -#define MACH_TYPE_TURBOT 2641 -#define MACH_TYPE_SANDDAB 2642 -#define MACH_TYPE_MX35_CICADA 2643 -#define MACH_TYPE_GHI2703D 2644 -#define MACH_TYPE_LUX_SFX9 2645 -#define MACH_TYPE_LUX_SF9G 2646 -#define MACH_TYPE_LUX_EDK9 2647 -#define MACH_TYPE_HW90240 2648 -#define MACH_TYPE_DM365_LEOPARD 2649 -#define MACH_TYPE_MITYOMAPL138 2650 -#define MACH_TYPE_SCAT110 2651 -#define MACH_TYPE_ACER_A1 2652 -#define MACH_TYPE_CMCONTROL 2653 -#define MACH_TYPE_PELCO_LAMAR 2654 -#define MACH_TYPE_RFP43 2655 -#define MACH_TYPE_SK86R0301 2656 -#define MACH_TYPE_CTPXA 2657 -#define MACH_TYPE_EPB_ARM9_A 2658 -#define MACH_TYPE_GURUPLUG 2659 -#define MACH_TYPE_SPEAR310 2660 -#define MACH_TYPE_SPEAR320 2661 -#define MACH_TYPE_ROBOTX 2662 -#define MACH_TYPE_LSXHL 2663 -#define MACH_TYPE_SMARTLITE 2664 -#define MACH_TYPE_CWS2 2665 -#define MACH_TYPE_M619 2666 -#define MACH_TYPE_SMARTVIEW 2667 -#define MACH_TYPE_LSA_SALSA 2668 -#define MACH_TYPE_KIZBOX 2669 -#define MACH_TYPE_HTCCHARMER 2670 -#define MACH_TYPE_GUF_NESO_LT 2671 -#define MACH_TYPE_PM9G45 2672 -#define MACH_TYPE_HTCPANTHER 2673 -#define MACH_TYPE_HTCPANTHER_CDMA 2674 -#define MACH_TYPE_REB01 2675 -#define MACH_TYPE_AQUILA 2676 -#define MACH_TYPE_SPARK_SLS_HW2 2677 -#define MACH_TYPE_ESATA_SHEEVAPLUG 2678 -#define MACH_TYPE_SURF7X30 2679 -#define MACH_TYPE_MICRO2440 2680 -#define MACH_TYPE_AM2440 2681 -#define MACH_TYPE_TQ2440 2682 -#define MACH_TYPE_LPC2478OEM 2683 -#define MACH_TYPE_AK880X 2684 -#define MACH_TYPE_COBRA3530 2685 -#define MACH_TYPE_PMPPB 2686 -#define MACH_TYPE_U6715 2687 -#define MACH_TYPE_AXAR1500_SENDER 2688 -#define MACH_TYPE_G30_DVB 2689 -#define MACH_TYPE_VC088X 2690 -#define MACH_TYPE_MIOA702 2691 -#define MACH_TYPE_HPMIN 2692 -#define MACH_TYPE_AK880XAK 2693 -#define MACH_TYPE_ARM926TOMAP850 2694 -#define MACH_TYPE_LKEVM 2695 -#define MACH_TYPE_MW6410 2696 -#define MACH_TYPE_TERASTATION_WXL 2697 -#define MACH_TYPE_CPU8000E 2698 -#define MACH_TYPE_CATANIA 2699 -#define MACH_TYPE_TOKYO 2700 -#define MACH_TYPE_MSM7201A_SURF 2701 -#define MACH_TYPE_MSM7201A_FFA 2702 -#define MACH_TYPE_MSM7X25_SURF 2703 -#define MACH_TYPE_MSM7X25_FFA 2704 -#define MACH_TYPE_MSM7X27_SURF 2705 -#define MACH_TYPE_MSM7X27_FFA 2706 -#define MACH_TYPE_MSM7X30_FFA 2707 -#define MACH_TYPE_QSD8X50_SURF 2708 -#define MACH_TYPE_QSD8X50_COMET 2709 -#define MACH_TYPE_QSD8X50_FFA 2710 -#define MACH_TYPE_QSD8X50A_SURF 2711 -#define MACH_TYPE_QSD8X50A_FFA 2712 -#define MACH_TYPE_XGCP10 2713 -#define MACH_TYPE_MCGWUMTS2A 2714 -#define MACH_TYPE_MOBIKT 2715 -#define MACH_TYPE_MX53_EVK 2716 -#define MACH_TYPE_IGEP0030 2717 -#define MACH_TYPE_AXELL_H40_H50_CTRL 2718 - -#ifdef CONFIG_ARCH_EBSA110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EBSA110 -# endif -# define machine_is_ebsa110() (machine_arch_type == MACH_TYPE_EBSA110) -#else -# define machine_is_ebsa110() (0) -#endif - -#ifdef CONFIG_ARCH_RPC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RISCPC -# endif -# define machine_is_riscpc() (machine_arch_type == MACH_TYPE_RISCPC) -#else -# define machine_is_riscpc() (0) -#endif - -#ifdef CONFIG_ARCH_NEXUSPCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXUSPCI -# endif -# define machine_is_nexuspci() (machine_arch_type == MACH_TYPE_NEXUSPCI) -#else -# define machine_is_nexuspci() (0) -#endif - -#ifdef CONFIG_ARCH_EBSA285 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EBSA285 -# endif -# define machine_is_ebsa285() (machine_arch_type == MACH_TYPE_EBSA285) -#else -# define machine_is_ebsa285() (0) -#endif - -#ifdef CONFIG_ARCH_NETWINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETWINDER -# endif -# define machine_is_netwinder() (machine_arch_type == MACH_TYPE_NETWINDER) -#else -# define machine_is_netwinder() (0) -#endif - -#ifdef CONFIG_ARCH_CATS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CATS -# endif -# define machine_is_cats() (machine_arch_type == MACH_TYPE_CATS) -#else -# define machine_is_cats() (0) -#endif - -#ifdef CONFIG_ARCH_TBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TBOX -# endif -# define machine_is_tbox() (machine_arch_type == MACH_TYPE_TBOX) -#else -# define machine_is_tbox() (0) -#endif - -#ifdef CONFIG_ARCH_CO285 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CO285 -# endif -# define machine_is_co285() (machine_arch_type == MACH_TYPE_CO285) -#else -# define machine_is_co285() (0) -#endif - -#ifdef CONFIG_ARCH_CLPS7110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLPS7110 -# endif -# define machine_is_clps7110() (machine_arch_type == MACH_TYPE_CLPS7110) -#else -# define machine_is_clps7110() (0) -#endif - -#ifdef CONFIG_ARCH_ARC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCHIMEDES -# endif -# define machine_is_archimedes() (machine_arch_type == MACH_TYPE_ARCHIMEDES) -#else -# define machine_is_archimedes() (0) -#endif - -#ifdef CONFIG_ARCH_A5K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A5K -# endif -# define machine_is_a5k() (machine_arch_type == MACH_TYPE_A5K) -#else -# define machine_is_a5k() (0) -#endif - -#ifdef CONFIG_ARCH_ETOILE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETOILE -# endif -# define machine_is_etoile() (machine_arch_type == MACH_TYPE_ETOILE) -#else -# define machine_is_etoile() (0) -#endif - -#ifdef CONFIG_ARCH_LACIE_NAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LACIE_NAS -# endif -# define machine_is_lacie_nas() (machine_arch_type == MACH_TYPE_LACIE_NAS) -#else -# define machine_is_lacie_nas() (0) -#endif - -#ifdef CONFIG_ARCH_CLPS7500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLPS7500 -# endif -# define machine_is_clps7500() (machine_arch_type == MACH_TYPE_CLPS7500) -#else -# define machine_is_clps7500() (0) -#endif - -#ifdef CONFIG_ARCH_SHARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHARK -# endif -# define machine_is_shark() (machine_arch_type == MACH_TYPE_SHARK) -#else -# define machine_is_shark() (0) -#endif - -#ifdef CONFIG_SA1100_BRUTUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRUTUS -# endif -# define machine_is_brutus() (machine_arch_type == MACH_TYPE_BRUTUS) -#else -# define machine_is_brutus() (0) -#endif - -#ifdef CONFIG_ARCH_PERSONAL_SERVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERSONAL_SERVER -# endif -# define machine_is_personal_server() (machine_arch_type == MACH_TYPE_PERSONAL_SERVER) -#else -# define machine_is_personal_server() (0) -#endif - -#ifdef CONFIG_SA1100_ITSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITSY -# endif -# define machine_is_itsy() (machine_arch_type == MACH_TYPE_ITSY) -#else -# define machine_is_itsy() (0) -#endif - -#ifdef CONFIG_ARCH_L7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_L7200 -# endif -# define machine_is_l7200() (machine_arch_type == MACH_TYPE_L7200) -#else -# define machine_is_l7200() (0) -#endif - -#ifdef CONFIG_SA1100_PLEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLEB -# endif -# define machine_is_pleb() (machine_arch_type == MACH_TYPE_PLEB) -#else -# define machine_is_pleb() (0) -#endif - -#ifdef CONFIG_ARCH_INTEGRATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTEGRATOR -# endif -# define machine_is_integrator() (machine_arch_type == MACH_TYPE_INTEGRATOR) -#else -# define machine_is_integrator() (0) -#endif - -#ifdef CONFIG_SA1100_H3600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3600 -# endif -# define machine_is_h3600() (machine_arch_type == MACH_TYPE_H3600) -#else -# define machine_is_h3600() (0) -#endif - -#ifdef CONFIG_ARCH_IXP1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP1200 -# endif -# define machine_is_ixp1200() (machine_arch_type == MACH_TYPE_IXP1200) -#else -# define machine_is_ixp1200() (0) -#endif - -#ifdef CONFIG_ARCH_P720T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P720T -# endif -# define machine_is_p720t() (machine_arch_type == MACH_TYPE_P720T) -#else -# define machine_is_p720t() (0) -#endif - -#ifdef CONFIG_SA1100_ASSABET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASSABET -# endif -# define machine_is_assabet() (machine_arch_type == MACH_TYPE_ASSABET) -#else -# define machine_is_assabet() (0) -#endif - -#ifdef CONFIG_SA1100_VICTOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VICTOR -# endif -# define machine_is_victor() (machine_arch_type == MACH_TYPE_VICTOR) -#else -# define machine_is_victor() (0) -#endif - -#ifdef CONFIG_SA1100_LART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LART -# endif -# define machine_is_lart() (machine_arch_type == MACH_TYPE_LART) -#else -# define machine_is_lart() (0) -#endif - -#ifdef CONFIG_SA1100_RANGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RANGER -# endif -# define machine_is_ranger() (machine_arch_type == MACH_TYPE_RANGER) -#else -# define machine_is_ranger() (0) -#endif - -#ifdef CONFIG_SA1100_GRAPHICSCLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRAPHICSCLIENT -# endif -# define machine_is_graphicsclient() (machine_arch_type == MACH_TYPE_GRAPHICSCLIENT) -#else -# define machine_is_graphicsclient() (0) -#endif - -#ifdef CONFIG_SA1100_XP860 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP860 -# endif -# define machine_is_xp860() (machine_arch_type == MACH_TYPE_XP860) -#else -# define machine_is_xp860() (0) -#endif - -#ifdef CONFIG_SA1100_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CERF -# endif -# define machine_is_cerf() (machine_arch_type == MACH_TYPE_CERF) -#else -# define machine_is_cerf() (0) -#endif - -#ifdef CONFIG_SA1100_NANOENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NANOENGINE -# endif -# define machine_is_nanoengine() (machine_arch_type == MACH_TYPE_NANOENGINE) -#else -# define machine_is_nanoengine() (0) -#endif - -#ifdef CONFIG_SA1100_FPIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FPIC -# endif -# define machine_is_fpic() (machine_arch_type == MACH_TYPE_FPIC) -#else -# define machine_is_fpic() (0) -#endif - -#ifdef CONFIG_SA1100_EXTENEX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXTENEX1 -# endif -# define machine_is_extenex1() (machine_arch_type == MACH_TYPE_EXTENEX1) -#else -# define machine_is_extenex1() (0) -#endif - -#ifdef CONFIG_SA1100_SHERMAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHERMAN -# endif -# define machine_is_sherman() (machine_arch_type == MACH_TYPE_SHERMAN) -#else -# define machine_is_sherman() (0) -#endif - -#ifdef CONFIG_SA1100_ACCELENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_SA -# endif -# define machine_is_accelent_sa() (machine_arch_type == MACH_TYPE_ACCELENT_SA) -#else -# define machine_is_accelent_sa() (0) -#endif - -#ifdef CONFIG_ARCH_L7200_ACCELENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_L7200 -# endif -# define machine_is_accelent_l7200() (machine_arch_type == MACH_TYPE_ACCELENT_L7200) -#else -# define machine_is_accelent_l7200() (0) -#endif - -#ifdef CONFIG_SA1100_NETPORT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETPORT -# endif -# define machine_is_netport() (machine_arch_type == MACH_TYPE_NETPORT) -#else -# define machine_is_netport() (0) -#endif - -#ifdef CONFIG_SA1100_PANGOLIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PANGOLIN -# endif -# define machine_is_pangolin() (machine_arch_type == MACH_TYPE_PANGOLIN) -#else -# define machine_is_pangolin() (0) -#endif - -#ifdef CONFIG_SA1100_YOPY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YOPY -# endif -# define machine_is_yopy() (machine_arch_type == MACH_TYPE_YOPY) -#else -# define machine_is_yopy() (0) -#endif - -#ifdef CONFIG_SA1100_COOLIDGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COOLIDGE -# endif -# define machine_is_coolidge() (machine_arch_type == MACH_TYPE_COOLIDGE) -#else -# define machine_is_coolidge() (0) -#endif - -#ifdef CONFIG_SA1100_HUW_WEBPANEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUW_WEBPANEL -# endif -# define machine_is_huw_webpanel() (machine_arch_type == MACH_TYPE_HUW_WEBPANEL) -#else -# define machine_is_huw_webpanel() (0) -#endif - -#ifdef CONFIG_ARCH_SPOTME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOTME -# endif -# define machine_is_spotme() (machine_arch_type == MACH_TYPE_SPOTME) -#else -# define machine_is_spotme() (0) -#endif - -#ifdef CONFIG_ARCH_FREEBIRD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FREEBIRD -# endif -# define machine_is_freebird() (machine_arch_type == MACH_TYPE_FREEBIRD) -#else -# define machine_is_freebird() (0) -#endif - -#ifdef CONFIG_ARCH_TI925 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI925 -# endif -# define machine_is_ti925() (machine_arch_type == MACH_TYPE_TI925) -#else -# define machine_is_ti925() (0) -#endif - -#ifdef CONFIG_ARCH_RISCSTATION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RISCSTATION -# endif -# define machine_is_riscstation() (machine_arch_type == MACH_TYPE_RISCSTATION) -#else -# define machine_is_riscstation() (0) -#endif - -#ifdef CONFIG_SA1100_CAVY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAVY -# endif -# define machine_is_cavy() (machine_arch_type == MACH_TYPE_CAVY) -#else -# define machine_is_cavy() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA720 -# endif -# define machine_is_jornada720() (machine_arch_type == MACH_TYPE_JORNADA720) -#else -# define machine_is_jornada720() (0) -#endif - -#ifdef CONFIG_SA1100_OMNIMETER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMNIMETER -# endif -# define machine_is_omnimeter() (machine_arch_type == MACH_TYPE_OMNIMETER) -#else -# define machine_is_omnimeter() (0) -#endif - -#ifdef CONFIG_ARCH_EDB7211 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB7211 -# endif -# define machine_is_edb7211() (machine_arch_type == MACH_TYPE_EDB7211) -#else -# define machine_is_edb7211() (0) -#endif - -#ifdef CONFIG_SA1100_CITYGO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CITYGO -# endif -# define machine_is_citygo() (machine_arch_type == MACH_TYPE_CITYGO) -#else -# define machine_is_citygo() (0) -#endif - -#ifdef CONFIG_SA1100_PFS168 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PFS168 -# endif -# define machine_is_pfs168() (machine_arch_type == MACH_TYPE_PFS168) -#else -# define machine_is_pfs168() (0) -#endif - -#ifdef CONFIG_SA1100_SPOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOT -# endif -# define machine_is_spot() (machine_arch_type == MACH_TYPE_SPOT) -#else -# define machine_is_spot() (0) -#endif - -#ifdef CONFIG_SA1100_FLEXANET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEXANET -# endif -# define machine_is_flexanet() (machine_arch_type == MACH_TYPE_FLEXANET) -#else -# define machine_is_flexanet() (0) -#endif - -#ifdef CONFIG_ARCH_WEBPAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBPAL -# endif -# define machine_is_webpal() (machine_arch_type == MACH_TYPE_WEBPAL) -#else -# define machine_is_webpal() (0) -#endif - -#ifdef CONFIG_SA1100_LINPDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINPDA -# endif -# define machine_is_linpda() (machine_arch_type == MACH_TYPE_LINPDA) -#else -# define machine_is_linpda() (0) -#endif - -#ifdef CONFIG_ARCH_ANAKIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANAKIN -# endif -# define machine_is_anakin() (machine_arch_type == MACH_TYPE_ANAKIN) -#else -# define machine_is_anakin() (0) -#endif - -#ifdef CONFIG_SA1100_MVI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MVI -# endif -# define machine_is_mvi() (machine_arch_type == MACH_TYPE_MVI) -#else -# define machine_is_mvi() (0) -#endif - -#ifdef CONFIG_SA1100_JUPITER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JUPITER -# endif -# define machine_is_jupiter() (machine_arch_type == MACH_TYPE_JUPITER) -#else -# define machine_is_jupiter() (0) -#endif - -#ifdef CONFIG_ARCH_PSIONW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PSIONW -# endif -# define machine_is_psionw() (machine_arch_type == MACH_TYPE_PSIONW) -#else -# define machine_is_psionw() (0) -#endif - -#ifdef CONFIG_SA1100_ALN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALN -# endif -# define machine_is_aln() (machine_arch_type == MACH_TYPE_ALN) -#else -# define machine_is_aln() (0) -#endif - -#ifdef CONFIG_ARCH_CAMELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAMELOT -# endif -# define machine_is_epxa() (machine_arch_type == MACH_TYPE_CAMELOT) -#else -# define machine_is_epxa() (0) -#endif - -#ifdef CONFIG_SA1100_GDS2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GDS2200 -# endif -# define machine_is_gds2200() (machine_arch_type == MACH_TYPE_GDS2200) -#else -# define machine_is_gds2200() (0) -#endif - -#ifdef CONFIG_SA1100_PSION_SERIES7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PSION_SERIES7 -# endif -# define machine_is_netbook() (machine_arch_type == MACH_TYPE_PSION_SERIES7) -#else -# define machine_is_netbook() (0) -#endif - -#ifdef CONFIG_SA1100_XFILE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XFILE -# endif -# define machine_is_xfile() (machine_arch_type == MACH_TYPE_XFILE) -#else -# define machine_is_xfile() (0) -#endif - -#ifdef CONFIG_ARCH_ACCELENT_EP9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACCELENT_EP9312 -# endif -# define machine_is_accelent_ep9312() (machine_arch_type == MACH_TYPE_ACCELENT_EP9312) -#else -# define machine_is_accelent_ep9312() (0) -#endif - -#ifdef CONFIG_ARCH_IC200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IC200 -# endif -# define machine_is_ic200() (machine_arch_type == MACH_TYPE_IC200) -#else -# define machine_is_ic200() (0) -#endif - -#ifdef CONFIG_SA1100_CREDITLART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CREDITLART -# endif -# define machine_is_creditlart() (machine_arch_type == MACH_TYPE_CREDITLART) -#else -# define machine_is_creditlart() (0) -#endif - -#ifdef CONFIG_SA1100_HTM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTM -# endif -# define machine_is_htm() (machine_arch_type == MACH_TYPE_HTM) -#else -# define machine_is_htm() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80310 -# endif -# define machine_is_iq80310() (machine_arch_type == MACH_TYPE_IQ80310) -#else -# define machine_is_iq80310() (0) -#endif - -#ifdef CONFIG_SA1100_FREEBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FREEBOT -# endif -# define machine_is_freebot() (machine_arch_type == MACH_TYPE_FREEBOT) -#else -# define machine_is_freebot() (0) -#endif - -#ifdef CONFIG_ARCH_ENTEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENTEL -# endif -# define machine_is_entel() (machine_arch_type == MACH_TYPE_ENTEL) -#else -# define machine_is_entel() (0) -#endif - -#ifdef CONFIG_ARCH_ENP3510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENP3510 -# endif -# define machine_is_enp3510() (machine_arch_type == MACH_TYPE_ENP3510) -#else -# define machine_is_enp3510() (0) -#endif - -#ifdef CONFIG_SA1100_TRIZEPS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS -# endif -# define machine_is_trizeps() (machine_arch_type == MACH_TYPE_TRIZEPS) -#else -# define machine_is_trizeps() (0) -#endif - -#ifdef CONFIG_SA1100_NESA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NESA -# endif -# define machine_is_nesa() (machine_arch_type == MACH_TYPE_NESA) -#else -# define machine_is_nesa() (0) -#endif - -#ifdef CONFIG_ARCH_VENUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VENUS -# endif -# define machine_is_venus() (machine_arch_type == MACH_TYPE_VENUS) -#else -# define machine_is_venus() (0) -#endif - -#ifdef CONFIG_ARCH_TARDIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TARDIS -# endif -# define machine_is_tardis() (machine_arch_type == MACH_TYPE_TARDIS) -#else -# define machine_is_tardis() (0) -#endif - -#ifdef CONFIG_ARCH_MERCURY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MERCURY -# endif -# define machine_is_mercury() (machine_arch_type == MACH_TYPE_MERCURY) -#else -# define machine_is_mercury() (0) -#endif - -#ifdef CONFIG_SA1100_EMPEG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPEG -# endif -# define machine_is_empeg() (machine_arch_type == MACH_TYPE_EMPEG) -#else -# define machine_is_empeg() (0) -#endif - -#ifdef CONFIG_ARCH_I80200FCC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I80200FCC -# endif -# define machine_is_adi_evb() (machine_arch_type == MACH_TYPE_I80200FCC) -#else -# define machine_is_adi_evb() (0) -#endif - -#ifdef CONFIG_SA1100_ITT_CPB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITT_CPB -# endif -# define machine_is_itt_cpb() (machine_arch_type == MACH_TYPE_ITT_CPB) -#else -# define machine_is_itt_cpb() (0) -#endif - -#ifdef CONFIG_SA1100_SVC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVC -# endif -# define machine_is_svc() (machine_arch_type == MACH_TYPE_SVC) -#else -# define machine_is_svc() (0) -#endif - -#ifdef CONFIG_SA1100_ALPHA2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALPHA2 -# endif -# define machine_is_alpha2() (machine_arch_type == MACH_TYPE_ALPHA2) -#else -# define machine_is_alpha2() (0) -#endif - -#ifdef CONFIG_SA1100_ALPHA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALPHA1 -# endif -# define machine_is_alpha1() (machine_arch_type == MACH_TYPE_ALPHA1) -#else -# define machine_is_alpha1() (0) -#endif - -#ifdef CONFIG_ARCH_NETARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETARM -# endif -# define machine_is_netarm() (machine_arch_type == MACH_TYPE_NETARM) -#else -# define machine_is_netarm() (0) -#endif - -#ifdef CONFIG_SA1100_SIMPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMPAD -# endif -# define machine_is_simpad() (machine_arch_type == MACH_TYPE_SIMPAD) -#else -# define machine_is_simpad() (0) -#endif - -#ifdef CONFIG_ARCH_PDA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDA1 -# endif -# define machine_is_pda1() (machine_arch_type == MACH_TYPE_PDA1) -#else -# define machine_is_pda1() (0) -#endif - -#ifdef CONFIG_ARCH_LUBBOCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUBBOCK -# endif -# define machine_is_lubbock() (machine_arch_type == MACH_TYPE_LUBBOCK) -#else -# define machine_is_lubbock() (0) -#endif - -#ifdef CONFIG_ARCH_ANIKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANIKO -# endif -# define machine_is_aniko() (machine_arch_type == MACH_TYPE_ANIKO) -#else -# define machine_is_aniko() (0) -#endif - -#ifdef CONFIG_ARCH_CLEP7212 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLEP7212 -# endif -# define machine_is_clep7212() (machine_arch_type == MACH_TYPE_CLEP7212) -#else -# define machine_is_clep7212() (0) -#endif - -#ifdef CONFIG_ARCH_CS89712 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS89712 -# endif -# define machine_is_cs89712() (machine_arch_type == MACH_TYPE_CS89712) -#else -# define machine_is_cs89712() (0) -#endif - -#ifdef CONFIG_SA1100_WEARARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEARARM -# endif -# define machine_is_weararm() (machine_arch_type == MACH_TYPE_WEARARM) -#else -# define machine_is_weararm() (0) -#endif - -#ifdef CONFIG_SA1100_POSSIO_PX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POSSIO_PX -# endif -# define machine_is_possio_px() (machine_arch_type == MACH_TYPE_POSSIO_PX) -#else -# define machine_is_possio_px() (0) -#endif - -#ifdef CONFIG_SA1100_SIDEARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIDEARM -# endif -# define machine_is_sidearm() (machine_arch_type == MACH_TYPE_SIDEARM) -#else -# define machine_is_sidearm() (0) -#endif - -#ifdef CONFIG_SA1100_STORK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORK -# endif -# define machine_is_stork() (machine_arch_type == MACH_TYPE_STORK) -#else -# define machine_is_stork() (0) -#endif - -#ifdef CONFIG_SA1100_SHANNON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHANNON -# endif -# define machine_is_shannon() (machine_arch_type == MACH_TYPE_SHANNON) -#else -# define machine_is_shannon() (0) -#endif - -#ifdef CONFIG_ARCH_ACE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACE -# endif -# define machine_is_ace() (machine_arch_type == MACH_TYPE_ACE) -#else -# define machine_is_ace() (0) -#endif - -#ifdef CONFIG_SA1100_BALLYARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLYARM -# endif -# define machine_is_ballyarm() (machine_arch_type == MACH_TYPE_BALLYARM) -#else -# define machine_is_ballyarm() (0) -#endif - -#ifdef CONFIG_SA1100_SIMPUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMPUTER -# endif -# define machine_is_simputer() (machine_arch_type == MACH_TYPE_SIMPUTER) -#else -# define machine_is_simputer() (0) -#endif - -#ifdef CONFIG_SA1100_NEXTERM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXTERM -# endif -# define machine_is_nexterm() (machine_arch_type == MACH_TYPE_NEXTERM) -#else -# define machine_is_nexterm() (0) -#endif - -#ifdef CONFIG_SA1100_SA1100_ELF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SA1100_ELF -# endif -# define machine_is_sa1100_elf() (machine_arch_type == MACH_TYPE_SA1100_ELF) -#else -# define machine_is_sa1100_elf() (0) -#endif - -#ifdef CONFIG_SA1100_GATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GATOR -# endif -# define machine_is_gator() (machine_arch_type == MACH_TYPE_GATOR) -#else -# define machine_is_gator() (0) -#endif - -#ifdef CONFIG_ARCH_GRANITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRANITE -# endif -# define machine_is_granite() (machine_arch_type == MACH_TYPE_GRANITE) -#else -# define machine_is_granite() (0) -#endif - -#ifdef CONFIG_SA1100_CONSUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONSUS -# endif -# define machine_is_consus() (machine_arch_type == MACH_TYPE_CONSUS) -#else -# define machine_is_consus() (0) -#endif - -#ifdef CONFIG_ARCH_AAED2000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AAED2000 -# endif -# define machine_is_aaed2000() (machine_arch_type == MACH_TYPE_AAED2000) -#else -# define machine_is_aaed2000() (0) -#endif - -#ifdef CONFIG_ARCH_CDB89712 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CDB89712 -# endif -# define machine_is_cdb89712() (machine_arch_type == MACH_TYPE_CDB89712) -#else -# define machine_is_cdb89712() (0) -#endif - -#ifdef CONFIG_SA1100_GRAPHICSMASTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRAPHICSMASTER -# endif -# define machine_is_graphicsmaster() (machine_arch_type == MACH_TYPE_GRAPHICSMASTER) -#else -# define machine_is_graphicsmaster() (0) -#endif - -#ifdef CONFIG_SA1100_ADSBITSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSY -# endif -# define machine_is_adsbitsy() (machine_arch_type == MACH_TYPE_ADSBITSY) -#else -# define machine_is_adsbitsy() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_IDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_IDP -# endif -# define machine_is_pxa_idp() (machine_arch_type == MACH_TYPE_PXA_IDP) -#else -# define machine_is_pxa_idp() (0) -#endif - -#ifdef CONFIG_ARCH_PLCE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLCE -# endif -# define machine_is_plce() (machine_arch_type == MACH_TYPE_PLCE) -#else -# define machine_is_plce() (0) -#endif - -#ifdef CONFIG_SA1100_PT_SYSTEM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PT_SYSTEM3 -# endif -# define machine_is_pt_system3() (machine_arch_type == MACH_TYPE_PT_SYSTEM3) -#else -# define machine_is_pt_system3() (0) -#endif - -#ifdef CONFIG_ARCH_MEDALB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEDALB -# endif -# define machine_is_murphy() (machine_arch_type == MACH_TYPE_MEDALB) -#else -# define machine_is_murphy() (0) -#endif - -#ifdef CONFIG_ARCH_EAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EAGLE -# endif -# define machine_is_eagle() (machine_arch_type == MACH_TYPE_EAGLE) -#else -# define machine_is_eagle() (0) -#endif - -#ifdef CONFIG_ARCH_DSC21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSC21 -# endif -# define machine_is_dsc21() (machine_arch_type == MACH_TYPE_DSC21) -#else -# define machine_is_dsc21() (0) -#endif - -#ifdef CONFIG_ARCH_DSC24 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSC24 -# endif -# define machine_is_dsc24() (machine_arch_type == MACH_TYPE_DSC24) -#else -# define machine_is_dsc24() (0) -#endif - -#ifdef CONFIG_ARCH_TI5472 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI5472 -# endif -# define machine_is_ti5472() (machine_arch_type == MACH_TYPE_TI5472) -#else -# define machine_is_ti5472() (0) -#endif - -#ifdef CONFIG_ARCH_AUTCPU12 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUTCPU12 -# endif -# define machine_is_autcpu12() (machine_arch_type == MACH_TYPE_AUTCPU12) -#else -# define machine_is_autcpu12() (0) -#endif - -#ifdef CONFIG_ARCH_UENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UENGINE -# endif -# define machine_is_uengine() (machine_arch_type == MACH_TYPE_UENGINE) -#else -# define machine_is_uengine() (0) -#endif - -#ifdef CONFIG_SA1100_BLUESTEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUESTEM -# endif -# define machine_is_bluestem() (machine_arch_type == MACH_TYPE_BLUESTEM) -#else -# define machine_is_bluestem() (0) -#endif - -#ifdef CONFIG_ARCH_XINGU8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XINGU8 -# endif -# define machine_is_xingu8() (machine_arch_type == MACH_TYPE_XINGU8) -#else -# define machine_is_xingu8() (0) -#endif - -#ifdef CONFIG_ARCH_BUSHSTB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUSHSTB -# endif -# define machine_is_bushstb() (machine_arch_type == MACH_TYPE_BUSHSTB) -#else -# define machine_is_bushstb() (0) -#endif - -#ifdef CONFIG_SA1100_EPSILON1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPSILON1 -# endif -# define machine_is_epsilon1() (machine_arch_type == MACH_TYPE_EPSILON1) -#else -# define machine_is_epsilon1() (0) -#endif - -#ifdef CONFIG_SA1100_BALLOON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLOON -# endif -# define machine_is_balloon() (machine_arch_type == MACH_TYPE_BALLOON) -#else -# define machine_is_balloon() (0) -#endif - -#ifdef CONFIG_ARCH_PUPPY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUPPY -# endif -# define machine_is_puppy() (machine_arch_type == MACH_TYPE_PUPPY) -#else -# define machine_is_puppy() (0) -#endif - -#ifdef CONFIG_SA1100_ELROY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELROY -# endif -# define machine_is_elroy() (machine_arch_type == MACH_TYPE_ELROY) -#else -# define machine_is_elroy() (0) -#endif - -#ifdef CONFIG_ARCH_GMS720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GMS720 -# endif -# define machine_is_gms720() (machine_arch_type == MACH_TYPE_GMS720) -#else -# define machine_is_gms720() (0) -#endif - -#ifdef CONFIG_ARCH_S24X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S24X -# endif -# define machine_is_s24x() (machine_arch_type == MACH_TYPE_S24X) -#else -# define machine_is_s24x() (0) -#endif - -#ifdef CONFIG_ARCH_JTEL_CLEP7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JTEL_CLEP7312 -# endif -# define machine_is_jtel_clep7312() (machine_arch_type == MACH_TYPE_JTEL_CLEP7312) -#else -# define machine_is_jtel_clep7312() (0) -#endif - -#ifdef CONFIG_ARCH_CX821XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX821XX -# endif -# define machine_is_cx821xx() (machine_arch_type == MACH_TYPE_CX821XX) -#else -# define machine_is_cx821xx() (0) -#endif - -#ifdef CONFIG_ARCH_EDB7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB7312 -# endif -# define machine_is_edb7312() (machine_arch_type == MACH_TYPE_EDB7312) -#else -# define machine_is_edb7312() (0) -#endif - -#ifdef CONFIG_SA1100_BSA1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSA1110 -# endif -# define machine_is_bsa1110() (machine_arch_type == MACH_TYPE_BSA1110) -#else -# define machine_is_bsa1110() (0) -#endif - -#ifdef CONFIG_ARCH_POWERPIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POWERPIN -# endif -# define machine_is_powerpin() (machine_arch_type == MACH_TYPE_POWERPIN) -#else -# define machine_is_powerpin() (0) -#endif - -#ifdef CONFIG_ARCH_OPENARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENARM -# endif -# define machine_is_openarm() (machine_arch_type == MACH_TYPE_OPENARM) -#else -# define machine_is_openarm() (0) -#endif - -#ifdef CONFIG_SA1100_WHITECHAPEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WHITECHAPEL -# endif -# define machine_is_whitechapel() (machine_arch_type == MACH_TYPE_WHITECHAPEL) -#else -# define machine_is_whitechapel() (0) -#endif - -#ifdef CONFIG_SA1100_H3100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3100 -# endif -# define machine_is_h3100() (machine_arch_type == MACH_TYPE_H3100) -#else -# define machine_is_h3100() (0) -#endif - -#ifdef CONFIG_SA1100_H3800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3800 -# endif -# define machine_is_h3800() (machine_arch_type == MACH_TYPE_H3800) -#else -# define machine_is_h3800() (0) -#endif - -#ifdef CONFIG_ARCH_BLUE_V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUE_V1 -# endif -# define machine_is_blue_v1() (machine_arch_type == MACH_TYPE_BLUE_V1) -#else -# define machine_is_blue_v1() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_CERF -# endif -# define machine_is_pxa_cerf() (machine_arch_type == MACH_TYPE_PXA_CERF) -#else -# define machine_is_pxa_cerf() (0) -#endif - -#ifdef CONFIG_ARCH_ARM7TEVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM7TEVB -# endif -# define machine_is_arm7tevb() (machine_arch_type == MACH_TYPE_ARM7TEVB) -#else -# define machine_is_arm7tevb() (0) -#endif - -#ifdef CONFIG_SA1100_D7400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D7400 -# endif -# define machine_is_d7400() (machine_arch_type == MACH_TYPE_D7400) -#else -# define machine_is_d7400() (0) -#endif - -#ifdef CONFIG_ARCH_PIRANHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PIRANHA -# endif -# define machine_is_piranha() (machine_arch_type == MACH_TYPE_PIRANHA) -#else -# define machine_is_piranha() (0) -#endif - -#ifdef CONFIG_SA1100_SBCAMELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBCAMELOT -# endif -# define machine_is_sbcamelot() (machine_arch_type == MACH_TYPE_SBCAMELOT) -#else -# define machine_is_sbcamelot() (0) -#endif - -#ifdef CONFIG_SA1100_KINGS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KINGS -# endif -# define machine_is_kings() (machine_arch_type == MACH_TYPE_KINGS) -#else -# define machine_is_kings() (0) -#endif - -#ifdef CONFIG_ARCH_SMDK2400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2400 -# endif -# define machine_is_smdk2400() (machine_arch_type == MACH_TYPE_SMDK2400) -#else -# define machine_is_smdk2400() (0) -#endif - -#ifdef CONFIG_SA1100_COLLIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLLIE -# endif -# define machine_is_collie() (machine_arch_type == MACH_TYPE_COLLIE) -#else -# define machine_is_collie() (0) -#endif - -#ifdef CONFIG_ARCH_IDR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IDR -# endif -# define machine_is_idr() (machine_arch_type == MACH_TYPE_IDR) -#else -# define machine_is_idr() (0) -#endif - -#ifdef CONFIG_SA1100_BADGE4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BADGE4 -# endif -# define machine_is_badge4() (machine_arch_type == MACH_TYPE_BADGE4) -#else -# define machine_is_badge4() (0) -#endif - -#ifdef CONFIG_ARCH_WEBNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBNET -# endif -# define machine_is_webnet() (machine_arch_type == MACH_TYPE_WEBNET) -#else -# define machine_is_webnet() (0) -#endif - -#ifdef CONFIG_SA1100_D7300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D7300 -# endif -# define machine_is_d7300() (machine_arch_type == MACH_TYPE_D7300) -#else -# define machine_is_d7300() (0) -#endif - -#ifdef CONFIG_SA1100_CEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEP -# endif -# define machine_is_cep() (machine_arch_type == MACH_TYPE_CEP) -#else -# define machine_is_cep() (0) -#endif - -#ifdef CONFIG_ARCH_FORTUNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTUNET -# endif -# define machine_is_fortunet() (machine_arch_type == MACH_TYPE_FORTUNET) -#else -# define machine_is_fortunet() (0) -#endif - -#ifdef CONFIG_ARCH_VC547X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC547X -# endif -# define machine_is_vc547x() (machine_arch_type == MACH_TYPE_VC547X) -#else -# define machine_is_vc547x() (0) -#endif - -#ifdef CONFIG_SA1100_FILEWALKER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FILEWALKER -# endif -# define machine_is_filewalker() (machine_arch_type == MACH_TYPE_FILEWALKER) -#else -# define machine_is_filewalker() (0) -#endif - -#ifdef CONFIG_SA1100_NETGATEWAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETGATEWAY -# endif -# define machine_is_netgateway() (machine_arch_type == MACH_TYPE_NETGATEWAY) -#else -# define machine_is_netgateway() (0) -#endif - -#ifdef CONFIG_SA1100_SYMBOL2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYMBOL2800 -# endif -# define machine_is_symbol2800() (machine_arch_type == MACH_TYPE_SYMBOL2800) -#else -# define machine_is_symbol2800() (0) -#endif - -#ifdef CONFIG_SA1100_SUNS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUNS -# endif -# define machine_is_suns() (machine_arch_type == MACH_TYPE_SUNS) -#else -# define machine_is_suns() (0) -#endif - -#ifdef CONFIG_SA1100_FRODO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRODO -# endif -# define machine_is_frodo() (machine_arch_type == MACH_TYPE_FRODO) -#else -# define machine_is_frodo() (0) -#endif - -#ifdef CONFIG_SA1100_MACH_TYTE_MS301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MACH_TYTE_MS301 -# endif -# define machine_is_ms301() (machine_arch_type == MACH_TYPE_MACH_TYTE_MS301) -#else -# define machine_is_ms301() (0) -#endif - -#ifdef CONFIG_ARCH_MX1ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX1ADS -# endif -# define machine_is_mx1ads() (machine_arch_type == MACH_TYPE_MX1ADS) -#else -# define machine_is_mx1ads() (0) -#endif - -#ifdef CONFIG_ARCH_H7201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7201 -# endif -# define machine_is_h7201() (machine_arch_type == MACH_TYPE_H7201) -#else -# define machine_is_h7201() (0) -#endif - -#ifdef CONFIG_ARCH_H7202 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7202 -# endif -# define machine_is_h7202() (machine_arch_type == MACH_TYPE_H7202) -#else -# define machine_is_h7202() (0) -#endif - -#ifdef CONFIG_ARCH_AMICO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMICO -# endif -# define machine_is_amico() (machine_arch_type == MACH_TYPE_AMICO) -#else -# define machine_is_amico() (0) -#endif - -#ifdef CONFIG_SA1100_IAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IAM -# endif -# define machine_is_iam() (machine_arch_type == MACH_TYPE_IAM) -#else -# define machine_is_iam() (0) -#endif - -#ifdef CONFIG_SA1100_TT530 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT530 -# endif -# define machine_is_tt530() (machine_arch_type == MACH_TYPE_TT530) -#else -# define machine_is_tt530() (0) -#endif - -#ifdef CONFIG_ARCH_SAM2400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM2400 -# endif -# define machine_is_sam2400() (machine_arch_type == MACH_TYPE_SAM2400) -#else -# define machine_is_sam2400() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA56X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA56X -# endif -# define machine_is_jornada56x() (machine_arch_type == MACH_TYPE_JORNADA56X) -#else -# define machine_is_jornada56x() (0) -#endif - -#ifdef CONFIG_SA1100_ACTIVE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTIVE -# endif -# define machine_is_active() (machine_arch_type == MACH_TYPE_ACTIVE) -#else -# define machine_is_active() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80321 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80321 -# endif -# define machine_is_iq80321() (machine_arch_type == MACH_TYPE_IQ80321) -#else -# define machine_is_iq80321() (0) -#endif - -#ifdef CONFIG_SA1100_WID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WID -# endif -# define machine_is_wid() (machine_arch_type == MACH_TYPE_WID) -#else -# define machine_is_wid() (0) -#endif - -#ifdef CONFIG_ARCH_SABINAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SABINAL -# endif -# define machine_is_sabinal() (machine_arch_type == MACH_TYPE_SABINAL) -#else -# define machine_is_sabinal() (0) -#endif - -#ifdef CONFIG_ARCH_IXP425_MATACUMBE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP425_MATACUMBE -# endif -# define machine_is_ixp425_matacumbe() (machine_arch_type == MACH_TYPE_IXP425_MATACUMBE) -#else -# define machine_is_ixp425_matacumbe() (0) -#endif - -#ifdef CONFIG_SA1100_MINIPRINT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINIPRINT -# endif -# define machine_is_miniprint() (machine_arch_type == MACH_TYPE_MINIPRINT) -#else -# define machine_is_miniprint() (0) -#endif - -#ifdef CONFIG_ARCH_ADM510X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADM510X -# endif -# define machine_is_adm510x() (machine_arch_type == MACH_TYPE_ADM510X) -#else -# define machine_is_adm510x() (0) -#endif - -#ifdef CONFIG_SA1100_SVS200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVS200 -# endif -# define machine_is_svs200() (machine_arch_type == MACH_TYPE_SVS200) -#else -# define machine_is_svs200() (0) -#endif - -#ifdef CONFIG_ARCH_ATG_TCU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATG_TCU -# endif -# define machine_is_atg_tcu() (machine_arch_type == MACH_TYPE_ATG_TCU) -#else -# define machine_is_atg_tcu() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA820 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA820 -# endif -# define machine_is_jornada820() (machine_arch_type == MACH_TYPE_JORNADA820) -#else -# define machine_is_jornada820() (0) -#endif - -#ifdef CONFIG_ARCH_S3C44B0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C44B0 -# endif -# define machine_is_s3c44b0() (machine_arch_type == MACH_TYPE_S3C44B0) -#else -# define machine_is_s3c44b0() (0) -#endif - -#ifdef CONFIG_ARCH_MARGIS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARGIS2 -# endif -# define machine_is_margis2() (machine_arch_type == MACH_TYPE_MARGIS2) -#else -# define machine_is_margis2() (0) -#endif - -#ifdef CONFIG_ARCH_KS8695 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KS8695 -# endif -# define machine_is_ks8695() (machine_arch_type == MACH_TYPE_KS8695) -#else -# define machine_is_ks8695() (0) -#endif - -#ifdef CONFIG_ARCH_BRH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRH -# endif -# define machine_is_brh() (machine_arch_type == MACH_TYPE_BRH) -#else -# define machine_is_brh() (0) -#endif - -#ifdef CONFIG_ARCH_S3C2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2410 -# endif -# define machine_is_s3c2410() (machine_arch_type == MACH_TYPE_S3C2410) -#else -# define machine_is_s3c2410() (0) -#endif - -#ifdef CONFIG_ARCH_POSSIO_PX30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POSSIO_PX30 -# endif -# define machine_is_possio_px30() (machine_arch_type == MACH_TYPE_POSSIO_PX30) -#else -# define machine_is_possio_px30() (0) -#endif - -#ifdef CONFIG_ARCH_S3C2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2800 -# endif -# define machine_is_s3c2800() (machine_arch_type == MACH_TYPE_S3C2800) -#else -# define machine_is_s3c2800() (0) -#endif - -#ifdef CONFIG_SA1100_FLEETWOOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEETWOOD -# endif -# define machine_is_fleetwood() (machine_arch_type == MACH_TYPE_FLEETWOOD) -#else -# define machine_is_fleetwood() (0) -#endif - -#ifdef CONFIG_ARCH_OMAHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAHA -# endif -# define machine_is_omaha() (machine_arch_type == MACH_TYPE_OMAHA) -#else -# define machine_is_omaha() (0) -#endif - -#ifdef CONFIG_ARCH_TA7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TA7 -# endif -# define machine_is_ta7() (machine_arch_type == MACH_TYPE_TA7) -#else -# define machine_is_ta7() (0) -#endif - -#ifdef CONFIG_SA1100_NOVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOVA -# endif -# define machine_is_nova() (machine_arch_type == MACH_TYPE_NOVA) -#else -# define machine_is_nova() (0) -#endif - -#ifdef CONFIG_ARCH_HMK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMK -# endif -# define machine_is_hmk() (machine_arch_type == MACH_TYPE_HMK) -#else -# define machine_is_hmk() (0) -#endif - -#ifdef CONFIG_ARCH_KARO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KARO -# endif -# define machine_is_karo() (machine_arch_type == MACH_TYPE_KARO) -#else -# define machine_is_karo() (0) -#endif - -#ifdef CONFIG_SA1100_FESTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FESTER -# endif -# define machine_is_fester() (machine_arch_type == MACH_TYPE_FESTER) -#else -# define machine_is_fester() (0) -#endif - -#ifdef CONFIG_ARCH_GPI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GPI -# endif -# define machine_is_gpi() (machine_arch_type == MACH_TYPE_GPI) -#else -# define machine_is_gpi() (0) -#endif - -#ifdef CONFIG_ARCH_SMDK2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2410 -# endif -# define machine_is_smdk2410() (machine_arch_type == MACH_TYPE_SMDK2410) -#else -# define machine_is_smdk2410() (0) -#endif - -#ifdef CONFIG_ARCH_I519 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I519 -# endif -# define machine_is_i519() (machine_arch_type == MACH_TYPE_I519) -#else -# define machine_is_i519() (0) -#endif - -#ifdef CONFIG_SA1100_NEXIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXIO -# endif -# define machine_is_nexio() (machine_arch_type == MACH_TYPE_NEXIO) -#else -# define machine_is_nexio() (0) -#endif - -#ifdef CONFIG_SA1100_BITBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BITBOX -# endif -# define machine_is_bitbox() (machine_arch_type == MACH_TYPE_BITBOX) -#else -# define machine_is_bitbox() (0) -#endif - -#ifdef CONFIG_SA1100_G200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G200 -# endif -# define machine_is_g200() (machine_arch_type == MACH_TYPE_G200) -#else -# define machine_is_g200() (0) -#endif - -#ifdef CONFIG_SA1100_GILL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GILL -# endif -# define machine_is_gill() (machine_arch_type == MACH_TYPE_GILL) -#else -# define machine_is_gill() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_MERCURY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_MERCURY -# endif -# define machine_is_pxa_mercury() (machine_arch_type == MACH_TYPE_PXA_MERCURY) -#else -# define machine_is_pxa_mercury() (0) -#endif - -#ifdef CONFIG_ARCH_CEIVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEIVA -# endif -# define machine_is_ceiva() (machine_arch_type == MACH_TYPE_CEIVA) -#else -# define machine_is_ceiva() (0) -#endif - -#ifdef CONFIG_SA1100_FRET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRET -# endif -# define machine_is_fret() (machine_arch_type == MACH_TYPE_FRET) -#else -# define machine_is_fret() (0) -#endif - -#ifdef CONFIG_SA1100_EMAILPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMAILPHONE -# endif -# define machine_is_emailphone() (machine_arch_type == MACH_TYPE_EMAILPHONE) -#else -# define machine_is_emailphone() (0) -#endif - -#ifdef CONFIG_ARCH_H3900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3900 -# endif -# define machine_is_h3900() (machine_arch_type == MACH_TYPE_H3900) -#else -# define machine_is_h3900() (0) -#endif - -#ifdef CONFIG_ARCH_PXA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA1 -# endif -# define machine_is_pxa1() (machine_arch_type == MACH_TYPE_PXA1) -#else -# define machine_is_pxa1() (0) -#endif - -#ifdef CONFIG_SA1100_KOAN369 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KOAN369 -# endif -# define machine_is_koan369() (machine_arch_type == MACH_TYPE_KOAN369) -#else -# define machine_is_koan369() (0) -#endif - -#ifdef CONFIG_ARCH_COGENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COGENT -# endif -# define machine_is_cogent() (machine_arch_type == MACH_TYPE_COGENT) -#else -# define machine_is_cogent() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SIMPUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SIMPUTER -# endif -# define machine_is_esl_simputer() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER) -#else -# define machine_is_esl_simputer() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SIMPUTER_CLR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SIMPUTER_CLR -# endif -# define machine_is_esl_simputer_clr() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER_CLR) -#else -# define machine_is_esl_simputer_clr() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SIMPUTER_BW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SIMPUTER_BW -# endif -# define machine_is_esl_simputer_bw() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER_BW) -#else -# define machine_is_esl_simputer_bw() (0) -#endif - -#ifdef CONFIG_ARCH_HHP_CRADLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HHP_CRADLE -# endif -# define machine_is_hhp_cradle() (machine_arch_type == MACH_TYPE_HHP_CRADLE) -#else -# define machine_is_hhp_cradle() (0) -#endif - -#ifdef CONFIG_ARCH_HE500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HE500 -# endif -# define machine_is_he500() (machine_arch_type == MACH_TYPE_HE500) -#else -# define machine_is_he500() (0) -#endif - -#ifdef CONFIG_SA1100_INHANDELF2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDELF2 -# endif -# define machine_is_inhandelf2() (machine_arch_type == MACH_TYPE_INHANDELF2) -#else -# define machine_is_inhandelf2() (0) -#endif - -#ifdef CONFIG_SA1100_INHANDFTIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDFTIP -# endif -# define machine_is_inhandftip() (machine_arch_type == MACH_TYPE_INHANDFTIP) -#else -# define machine_is_inhandftip() (0) -#endif - -#ifdef CONFIG_SA1100_DNP1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DNP1110 -# endif -# define machine_is_dnp1110() (machine_arch_type == MACH_TYPE_DNP1110) -#else -# define machine_is_dnp1110() (0) -#endif - -#ifdef CONFIG_SA1100_PNP1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNP1110 -# endif -# define machine_is_pnp1110() (machine_arch_type == MACH_TYPE_PNP1110) -#else -# define machine_is_pnp1110() (0) -#endif - -#ifdef CONFIG_ARCH_CSB226 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB226 -# endif -# define machine_is_csb226() (machine_arch_type == MACH_TYPE_CSB226) -#else -# define machine_is_csb226() (0) -#endif - -#ifdef CONFIG_SA1100_ARNOLD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARNOLD -# endif -# define machine_is_arnold() (machine_arch_type == MACH_TYPE_ARNOLD) -#else -# define machine_is_arnold() (0) -#endif - -#ifdef CONFIG_MACH_VOICEBLUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOICEBLUE -# endif -# define machine_is_voiceblue() (machine_arch_type == MACH_TYPE_VOICEBLUE) -#else -# define machine_is_voiceblue() (0) -#endif - -#ifdef CONFIG_ARCH_JZ8028 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JZ8028 -# endif -# define machine_is_jz8028() (machine_arch_type == MACH_TYPE_JZ8028) -#else -# define machine_is_jz8028() (0) -#endif - -#ifdef CONFIG_ARCH_H5400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H5400 -# endif -# define machine_is_h5400() (machine_arch_type == MACH_TYPE_H5400) -#else -# define machine_is_h5400() (0) -#endif - -#ifdef CONFIG_SA1100_FORTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTE -# endif -# define machine_is_forte() (machine_arch_type == MACH_TYPE_FORTE) -#else -# define machine_is_forte() (0) -#endif - -#ifdef CONFIG_SA1100_ACAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACAM -# endif -# define machine_is_acam() (machine_arch_type == MACH_TYPE_ACAM) -#else -# define machine_is_acam() (0) -#endif - -#ifdef CONFIG_SA1100_ABOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ABOX -# endif -# define machine_is_abox() (machine_arch_type == MACH_TYPE_ABOX) -#else -# define machine_is_abox() (0) -#endif - -#ifdef CONFIG_ARCH_ATMEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATMEL -# endif -# define machine_is_atmel() (machine_arch_type == MACH_TYPE_ATMEL) -#else -# define machine_is_atmel() (0) -#endif - -#ifdef CONFIG_ARCH_SITSANG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SITSANG -# endif -# define machine_is_sitsang() (machine_arch_type == MACH_TYPE_SITSANG) -#else -# define machine_is_sitsang() (0) -#endif - -#ifdef CONFIG_SA1100_CPU1110LCDNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPU1110LCDNET -# endif -# define machine_is_cpu1110lcdnet() (machine_arch_type == MACH_TYPE_CPU1110LCDNET) -#else -# define machine_is_cpu1110lcdnet() (0) -#endif - -#ifdef CONFIG_ARCH_MPL_VCMA9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPL_VCMA9 -# endif -# define machine_is_mpl_vcma9() (machine_arch_type == MACH_TYPE_MPL_VCMA9) -#else -# define machine_is_mpl_vcma9() (0) -#endif - -#ifdef CONFIG_ARCH_OPUS_A1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPUS_A1 -# endif -# define machine_is_opus_a1() (machine_arch_type == MACH_TYPE_OPUS_A1) -#else -# define machine_is_opus_a1() (0) -#endif - -#ifdef CONFIG_ARCH_DAYTONA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAYTONA -# endif -# define machine_is_daytona() (machine_arch_type == MACH_TYPE_DAYTONA) -#else -# define machine_is_daytona() (0) -#endif - -#ifdef CONFIG_SA1100_KILLBEAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KILLBEAR -# endif -# define machine_is_killbear() (machine_arch_type == MACH_TYPE_KILLBEAR) -#else -# define machine_is_killbear() (0) -#endif - -#ifdef CONFIG_ARCH_YOHO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YOHO -# endif -# define machine_is_yoho() (machine_arch_type == MACH_TYPE_YOHO) -#else -# define machine_is_yoho() (0) -#endif - -#ifdef CONFIG_ARCH_JASPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JASPER -# endif -# define machine_is_jasper() (machine_arch_type == MACH_TYPE_JASPER) -#else -# define machine_is_jasper() (0) -#endif - -#ifdef CONFIG_ARCH_DSC25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSC25 -# endif -# define machine_is_dsc25() (machine_arch_type == MACH_TYPE_DSC25) -#else -# define machine_is_dsc25() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_INNOVATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_INNOVATOR -# endif -# define machine_is_omap_innovator() (machine_arch_type == MACH_TYPE_OMAP_INNOVATOR) -#else -# define machine_is_omap_innovator() (0) -#endif - -#ifdef CONFIG_ARCH_RAMSES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAMSES -# endif -# define machine_is_mnci() (machine_arch_type == MACH_TYPE_RAMSES) -#else -# define machine_is_mnci() (0) -#endif - -#ifdef CONFIG_ARCH_S28X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S28X -# endif -# define machine_is_s28x() (machine_arch_type == MACH_TYPE_S28X) -#else -# define machine_is_s28x() (0) -#endif - -#ifdef CONFIG_ARCH_MPORT3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPORT3 -# endif -# define machine_is_mport3() (machine_arch_type == MACH_TYPE_MPORT3) -#else -# define machine_is_mport3() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_EAGLE250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_EAGLE250 -# endif -# define machine_is_pxa_eagle250() (machine_arch_type == MACH_TYPE_PXA_EAGLE250) -#else -# define machine_is_pxa_eagle250() (0) -#endif - -#ifdef CONFIG_ARCH_PDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDB -# endif -# define machine_is_pdb() (machine_arch_type == MACH_TYPE_PDB) -#else -# define machine_is_pdb() (0) -#endif - -#ifdef CONFIG_SA1100_BLUE_2G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUE_2G -# endif -# define machine_is_blue_2g() (machine_arch_type == MACH_TYPE_BLUE_2G) -#else -# define machine_is_blue_2g() (0) -#endif - -#ifdef CONFIG_SA1100_BLUEARCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUEARCH -# endif -# define machine_is_bluearch() (machine_arch_type == MACH_TYPE_BLUEARCH) -#else -# define machine_is_bluearch() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2400 -# endif -# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDP2400) -#else -# define machine_is_ixdp2400() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2800 -# endif -# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDP2800) -#else -# define machine_is_ixdp2800() (0) -#endif - -#ifdef CONFIG_SA1100_EXPLORER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXPLORER -# endif -# define machine_is_explorer() (machine_arch_type == MACH_TYPE_EXPLORER) -#else -# define machine_is_explorer() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP425 -# endif -# define machine_is_ixdp425() (machine_arch_type == MACH_TYPE_IXDP425) -#else -# define machine_is_ixdp425() (0) -#endif - -#ifdef CONFIG_ARCH_CHIMP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHIMP -# endif -# define machine_is_chimp() (machine_arch_type == MACH_TYPE_CHIMP) -#else -# define machine_is_chimp() (0) -#endif - -#ifdef CONFIG_ARCH_STORK_NEST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORK_NEST -# endif -# define machine_is_stork_nest() (machine_arch_type == MACH_TYPE_STORK_NEST) -#else -# define machine_is_stork_nest() (0) -#endif - -#ifdef CONFIG_ARCH_STORK_EGG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORK_EGG -# endif -# define machine_is_stork_egg() (machine_arch_type == MACH_TYPE_STORK_EGG) -#else -# define machine_is_stork_egg() (0) -#endif - -#ifdef CONFIG_SA1100_WISMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WISMO -# endif -# define machine_is_wismo() (machine_arch_type == MACH_TYPE_WISMO) -#else -# define machine_is_wismo() (0) -#endif - -#ifdef CONFIG_ARCH_EZLINX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZLINX -# endif -# define machine_is_ezlinx() (machine_arch_type == MACH_TYPE_EZLINX) -#else -# define machine_is_ezlinx() (0) -#endif - -#ifdef CONFIG_ARCH_AT91RM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200 -# endif -# define machine_is_at91rm9200() (machine_arch_type == MACH_TYPE_AT91RM9200) -#else -# define machine_is_at91rm9200() (0) -#endif - -#ifdef CONFIG_ARCH_ADTECH_ORION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADTECH_ORION -# endif -# define machine_is_adtech_orion() (machine_arch_type == MACH_TYPE_ADTECH_ORION) -#else -# define machine_is_adtech_orion() (0) -#endif - -#ifdef CONFIG_ARCH_NEPTUNE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEPTUNE -# endif -# define machine_is_neptune() (machine_arch_type == MACH_TYPE_NEPTUNE) -#else -# define machine_is_neptune() (0) -#endif - -#ifdef CONFIG_SA1100_HACKKIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HACKKIT -# endif -# define machine_is_hackkit() (machine_arch_type == MACH_TYPE_HACKKIT) -#else -# define machine_is_hackkit() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_WINS30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_WINS30 -# endif -# define machine_is_pxa_wins30() (machine_arch_type == MACH_TYPE_PXA_WINS30) -#else -# define machine_is_pxa_wins30() (0) -#endif - -#ifdef CONFIG_SA1100_LAVINNA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LAVINNA -# endif -# define machine_is_lavinna() (machine_arch_type == MACH_TYPE_LAVINNA) -#else -# define machine_is_lavinna() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_UENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_UENGINE -# endif -# define machine_is_pxa_uengine() (machine_arch_type == MACH_TYPE_PXA_UENGINE) -#else -# define machine_is_pxa_uengine() (0) -#endif - -#ifdef CONFIG_ARCH_INNOKOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INNOKOM -# endif -# define machine_is_innokom() (machine_arch_type == MACH_TYPE_INNOKOM) -#else -# define machine_is_innokom() (0) -#endif - -#ifdef CONFIG_ARCH_BMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BMS -# endif -# define machine_is_bms() (machine_arch_type == MACH_TYPE_BMS) -#else -# define machine_is_bms() (0) -#endif - -#ifdef CONFIG_ARCH_IXCDP1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXCDP1100 -# endif -# define machine_is_ixcdp1100() (machine_arch_type == MACH_TYPE_IXCDP1100) -#else -# define machine_is_ixcdp1100() (0) -#endif - -#ifdef CONFIG_ARCH_PRPMC1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRPMC1100 -# endif -# define machine_is_prpmc1100() (machine_arch_type == MACH_TYPE_PRPMC1100) -#else -# define machine_is_prpmc1100() (0) -#endif - -#ifdef CONFIG_ARCH_AT91RM9200DK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200DK -# endif -# define machine_is_at91rm9200dk() (machine_arch_type == MACH_TYPE_AT91RM9200DK) -#else -# define machine_is_at91rm9200dk() (0) -#endif - -#ifdef CONFIG_ARCH_ARMSTICK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMSTICK -# endif -# define machine_is_armstick() (machine_arch_type == MACH_TYPE_ARMSTICK) -#else -# define machine_is_armstick() (0) -#endif - -#ifdef CONFIG_ARCH_ARMONIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMONIE -# endif -# define machine_is_armonie() (machine_arch_type == MACH_TYPE_ARMONIE) -#else -# define machine_is_armonie() (0) -#endif - -#ifdef CONFIG_ARCH_MPORT1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPORT1 -# endif -# define machine_is_mport1() (machine_arch_type == MACH_TYPE_MPORT1) -#else -# define machine_is_mport1() (0) -#endif - -#ifdef CONFIG_ARCH_S3C5410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C5410 -# endif -# define machine_is_s3c5410() (machine_arch_type == MACH_TYPE_S3C5410) -#else -# define machine_is_s3c5410() (0) -#endif - -#ifdef CONFIG_ARCH_ZCP320A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZCP320A -# endif -# define machine_is_zcp320a() (machine_arch_type == MACH_TYPE_ZCP320A) -#else -# define machine_is_zcp320a() (0) -#endif - -#ifdef CONFIG_ARCH_I_BOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I_BOX -# endif -# define machine_is_i_box() (machine_arch_type == MACH_TYPE_I_BOX) -#else -# define machine_is_i_box() (0) -#endif - -#ifdef CONFIG_ARCH_STLC1502 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STLC1502 -# endif -# define machine_is_stlc1502() (machine_arch_type == MACH_TYPE_STLC1502) -#else -# define machine_is_stlc1502() (0) -#endif - -#ifdef CONFIG_ARCH_SIREN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIREN -# endif -# define machine_is_siren() (machine_arch_type == MACH_TYPE_SIREN) -#else -# define machine_is_siren() (0) -#endif - -#ifdef CONFIG_ARCH_GREENLAKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GREENLAKE -# endif -# define machine_is_greenlake() (machine_arch_type == MACH_TYPE_GREENLAKE) -#else -# define machine_is_greenlake() (0) -#endif - -#ifdef CONFIG_ARCH_ARGUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARGUS -# endif -# define machine_is_argus() (machine_arch_type == MACH_TYPE_ARGUS) -#else -# define machine_is_argus() (0) -#endif - -#ifdef CONFIG_SA1100_COMBADGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMBADGE -# endif -# define machine_is_combadge() (machine_arch_type == MACH_TYPE_COMBADGE) -#else -# define machine_is_combadge() (0) -#endif - -#ifdef CONFIG_ARCH_ROKEPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROKEPXA -# endif -# define machine_is_rokepxa() (machine_arch_type == MACH_TYPE_ROKEPXA) -#else -# define machine_is_rokepxa() (0) -#endif - -#ifdef CONFIG_ARCH_CINTEGRATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CINTEGRATOR -# endif -# define machine_is_cintegrator() (machine_arch_type == MACH_TYPE_CINTEGRATOR) -#else -# define machine_is_cintegrator() (0) -#endif - -#ifdef CONFIG_ARCH_GUIDEA07 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUIDEA07 -# endif -# define machine_is_guidea07() (machine_arch_type == MACH_TYPE_GUIDEA07) -#else -# define machine_is_guidea07() (0) -#endif - -#ifdef CONFIG_ARCH_TAT257 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAT257 -# endif -# define machine_is_tat257() (machine_arch_type == MACH_TYPE_TAT257) -#else -# define machine_is_tat257() (0) -#endif - -#ifdef CONFIG_ARCH_IGP2425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGP2425 -# endif -# define machine_is_igp2425() (machine_arch_type == MACH_TYPE_IGP2425) -#else -# define machine_is_igp2425() (0) -#endif - -#ifdef CONFIG_ARCH_BLUEGRAMMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUEGRAMMA -# endif -# define machine_is_bluegrama() (machine_arch_type == MACH_TYPE_BLUEGRAMMA) -#else -# define machine_is_bluegrama() (0) -#endif - -#ifdef CONFIG_ARCH_IPOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPOD -# endif -# define machine_is_ipod() (machine_arch_type == MACH_TYPE_IPOD) -#else -# define machine_is_ipod() (0) -#endif - -#ifdef CONFIG_ARCH_ADSBITSYX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYX -# endif -# define machine_is_adsbitsyx() (machine_arch_type == MACH_TYPE_ADSBITSYX) -#else -# define machine_is_adsbitsyx() (0) -#endif - -#ifdef CONFIG_ARCH_TRIZEPS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS2 -# endif -# define machine_is_trizeps2() (machine_arch_type == MACH_TYPE_TRIZEPS2) -#else -# define machine_is_trizeps2() (0) -#endif - -#ifdef CONFIG_ARCH_VIPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIPER -# endif -# define machine_is_viper() (machine_arch_type == MACH_TYPE_VIPER) -#else -# define machine_is_viper() (0) -#endif - -#ifdef CONFIG_SA1100_ADSBITSYPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYPLUS -# endif -# define machine_is_adsbitsyplus() (machine_arch_type == MACH_TYPE_ADSBITSYPLUS) -#else -# define machine_is_adsbitsyplus() (0) -#endif - -#ifdef CONFIG_SA1100_ADSAGC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSAGC -# endif -# define machine_is_adsagc() (machine_arch_type == MACH_TYPE_ADSAGC) -#else -# define machine_is_adsagc() (0) -#endif - -#ifdef CONFIG_ARCH_STP7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STP7312 -# endif -# define machine_is_stp7312() (machine_arch_type == MACH_TYPE_STP7312) -#else -# define machine_is_stp7312() (0) -#endif - -#ifdef CONFIG_MACH_NX_PHNX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX_PHNX -# endif -# define machine_is_nx_phnx() (machine_arch_type == MACH_TYPE_NX_PHNX) -#else -# define machine_is_nx_phnx() (0) -#endif - -#ifdef CONFIG_ARCH_WEP_EP250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEP_EP250 -# endif -# define machine_is_wep_ep250() (machine_arch_type == MACH_TYPE_WEP_EP250) -#else -# define machine_is_wep_ep250() (0) -#endif - -#ifdef CONFIG_ARCH_INHANDELF3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDELF3 -# endif -# define machine_is_inhandelf3() (machine_arch_type == MACH_TYPE_INHANDELF3) -#else -# define machine_is_inhandelf3() (0) -#endif - -#ifdef CONFIG_ARCH_ADI_COYOTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADI_COYOTE -# endif -# define machine_is_adi_coyote() (machine_arch_type == MACH_TYPE_ADI_COYOTE) -#else -# define machine_is_adi_coyote() (0) -#endif - -#ifdef CONFIG_ARCH_IYONIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IYONIX -# endif -# define machine_is_iyonix() (machine_arch_type == MACH_TYPE_IYONIX) -#else -# define machine_is_iyonix() (0) -#endif - -#ifdef CONFIG_ARCH_DAMICAM_SA1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAMICAM_SA1110 -# endif -# define machine_is_damicam1() (machine_arch_type == MACH_TYPE_DAMICAM_SA1110) -#else -# define machine_is_damicam1() (0) -#endif - -#ifdef CONFIG_ARCH_MEG03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEG03 -# endif -# define machine_is_meg03() (machine_arch_type == MACH_TYPE_MEG03) -#else -# define machine_is_meg03() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_WHITECHAPEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_WHITECHAPEL -# endif -# define machine_is_pxa_whitechapel() (machine_arch_type == MACH_TYPE_PXA_WHITECHAPEL) -#else -# define machine_is_pxa_whitechapel() (0) -#endif - -#ifdef CONFIG_ARCH_NWSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NWSC -# endif -# define machine_is_nwsc() (machine_arch_type == MACH_TYPE_NWSC) -#else -# define machine_is_nwsc() (0) -#endif - -#ifdef CONFIG_ARCH_NWLARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NWLARM -# endif -# define machine_is_nwlarm() (machine_arch_type == MACH_TYPE_NWLARM) -#else -# define machine_is_nwlarm() (0) -#endif - -#ifdef CONFIG_ARCH_IXP425_MGUARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP425_MGUARD -# endif -# define machine_is_ixp425_mguard() (machine_arch_type == MACH_TYPE_IXP425_MGUARD) -#else -# define machine_is_ixp425_mguard() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_NETDCU4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_NETDCU4 -# endif -# define machine_is_pxa_netdcu4() (machine_arch_type == MACH_TYPE_PXA_NETDCU4) -#else -# define machine_is_pxa_netdcu4() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2401 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2401 -# endif -# define machine_is_ixdp2401() (machine_arch_type == MACH_TYPE_IXDP2401) -#else -# define machine_is_ixdp2401() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2801 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2801 -# endif -# define machine_is_ixdp2801() (machine_arch_type == MACH_TYPE_IXDP2801) -#else -# define machine_is_ixdp2801() (0) -#endif - -#ifdef CONFIG_ARCH_ZODIAC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZODIAC -# endif -# define machine_is_zodiac() (machine_arch_type == MACH_TYPE_ZODIAC) -#else -# define machine_is_zodiac() (0) -#endif - -#ifdef CONFIG_ARCH_ARMMODUL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMMODUL -# endif -# define machine_is_armmodul() (machine_arch_type == MACH_TYPE_ARMMODUL) -#else -# define machine_is_armmodul() (0) -#endif - -#ifdef CONFIG_SA1100_KETOP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KETOP -# endif -# define machine_is_ketop() (machine_arch_type == MACH_TYPE_KETOP) -#else -# define machine_is_ketop() (0) -#endif - -#ifdef CONFIG_ARCH_AV7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AV7200 -# endif -# define machine_is_av7200() (machine_arch_type == MACH_TYPE_AV7200) -#else -# define machine_is_av7200() (0) -#endif - -#ifdef CONFIG_ARCH_ARCH_TI925 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCH_TI925 -# endif -# define machine_is_arch_ti925() (machine_arch_type == MACH_TYPE_ARCH_TI925) -#else -# define machine_is_arch_ti925() (0) -#endif - -#ifdef CONFIG_ARCH_ACQ200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ200 -# endif -# define machine_is_acq200() (machine_arch_type == MACH_TYPE_ACQ200) -#else -# define machine_is_acq200() (0) -#endif - -#ifdef CONFIG_SA1100_PT_DAFIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PT_DAFIT -# endif -# define machine_is_pt_dafit() (machine_arch_type == MACH_TYPE_PT_DAFIT) -#else -# define machine_is_pt_dafit() (0) -#endif - -#ifdef CONFIG_ARCH_IHBA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IHBA -# endif -# define machine_is_ihba() (machine_arch_type == MACH_TYPE_IHBA) -#else -# define machine_is_ihba() (0) -#endif - -#ifdef CONFIG_ARCH_QUINQUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUINQUE -# endif -# define machine_is_quinque() (machine_arch_type == MACH_TYPE_QUINQUE) -#else -# define machine_is_quinque() (0) -#endif - -#ifdef CONFIG_ARCH_NIMBRAONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRAONE -# endif -# define machine_is_nimbraone() (machine_arch_type == MACH_TYPE_NIMBRAONE) -#else -# define machine_is_nimbraone() (0) -#endif - -#ifdef CONFIG_ARCH_NIMBRA29X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRA29X -# endif -# define machine_is_nimbra29x() (machine_arch_type == MACH_TYPE_NIMBRA29X) -#else -# define machine_is_nimbra29x() (0) -#endif - -#ifdef CONFIG_ARCH_NIMBRA210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRA210 -# endif -# define machine_is_nimbra210() (machine_arch_type == MACH_TYPE_NIMBRA210) -#else -# define machine_is_nimbra210() (0) -#endif - -#ifdef CONFIG_ARCH_HHP_D95XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HHP_D95XX -# endif -# define machine_is_hhp_d95xx() (machine_arch_type == MACH_TYPE_HHP_D95XX) -#else -# define machine_is_hhp_d95xx() (0) -#endif - -#ifdef CONFIG_ARCH_LABARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LABARM -# endif -# define machine_is_labarm() (machine_arch_type == MACH_TYPE_LABARM) -#else -# define machine_is_labarm() (0) -#endif - -#ifdef CONFIG_ARCH_M825XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M825XX -# endif -# define machine_is_m825xx() (machine_arch_type == MACH_TYPE_M825XX) -#else -# define machine_is_m825xx() (0) -#endif - -#ifdef CONFIG_SA1100_M7100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M7100 -# endif -# define machine_is_m7100() (machine_arch_type == MACH_TYPE_M7100) -#else -# define machine_is_m7100() (0) -#endif - -#ifdef CONFIG_ARCH_NIPC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIPC2 -# endif -# define machine_is_nipc2() (machine_arch_type == MACH_TYPE_NIPC2) -#else -# define machine_is_nipc2() (0) -#endif - -#ifdef CONFIG_ARCH_FU7202 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FU7202 -# endif -# define machine_is_fu7202() (machine_arch_type == MACH_TYPE_FU7202) -#else -# define machine_is_fu7202() (0) -#endif - -#ifdef CONFIG_ARCH_ADSAGX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSAGX -# endif -# define machine_is_adsagx() (machine_arch_type == MACH_TYPE_ADSAGX) -#else -# define machine_is_adsagx() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_POOH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_POOH -# endif -# define machine_is_pxa_pooh() (machine_arch_type == MACH_TYPE_PXA_POOH) -#else -# define machine_is_pxa_pooh() (0) -#endif - -#ifdef CONFIG_ARCH_BANDON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BANDON -# endif -# define machine_is_bandon() (machine_arch_type == MACH_TYPE_BANDON) -#else -# define machine_is_bandon() (0) -#endif - -#ifdef CONFIG_ARCH_PCM7210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM7210 -# endif -# define machine_is_pcm7210() (machine_arch_type == MACH_TYPE_PCM7210) -#else -# define machine_is_pcm7210() (0) -#endif - -#ifdef CONFIG_ARCH_NMS9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NMS9200 -# endif -# define machine_is_nms9200() (machine_arch_type == MACH_TYPE_NMS9200) -#else -# define machine_is_nms9200() (0) -#endif - -#ifdef CONFIG_ARCH_LOGODL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGODL -# endif -# define machine_is_logodl() (machine_arch_type == MACH_TYPE_LOGODL) -#else -# define machine_is_logodl() (0) -#endif - -#ifdef CONFIG_SA1100_M7140 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M7140 -# endif -# define machine_is_m7140() (machine_arch_type == MACH_TYPE_M7140) -#else -# define machine_is_m7140() (0) -#endif - -#ifdef CONFIG_ARCH_KOREBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KOREBOT -# endif -# define machine_is_korebot() (machine_arch_type == MACH_TYPE_KOREBOT) -#else -# define machine_is_korebot() (0) -#endif - -#ifdef CONFIG_ARCH_IQ31244 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ31244 -# endif -# define machine_is_iq31244() (machine_arch_type == MACH_TYPE_IQ31244) -#else -# define machine_is_iq31244() (0) -#endif - -#ifdef CONFIG_SA1100_KOAN393 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KOAN393 -# endif -# define machine_is_koan393() (machine_arch_type == MACH_TYPE_KOAN393) -#else -# define machine_is_koan393() (0) -#endif - -#ifdef CONFIG_ARCH_INHANDFTIP3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHANDFTIP3 -# endif -# define machine_is_inhandftip3() (machine_arch_type == MACH_TYPE_INHANDFTIP3) -#else -# define machine_is_inhandftip3() (0) -#endif - -#ifdef CONFIG_ARCH_GONZO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GONZO -# endif -# define machine_is_gonzo() (machine_arch_type == MACH_TYPE_GONZO) -#else -# define machine_is_gonzo() (0) -#endif - -#ifdef CONFIG_ARCH_BAST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BAST -# endif -# define machine_is_bast() (machine_arch_type == MACH_TYPE_BAST) -#else -# define machine_is_bast() (0) -#endif - -#ifdef CONFIG_ARCH_SCANPASS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCANPASS -# endif -# define machine_is_scanpass() (machine_arch_type == MACH_TYPE_SCANPASS) -#else -# define machine_is_scanpass() (0) -#endif - -#ifdef CONFIG_ARCH_EP7312_POOH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EP7312_POOH -# endif -# define machine_is_ep7312_pooh() (machine_arch_type == MACH_TYPE_EP7312_POOH) -#else -# define machine_is_ep7312_pooh() (0) -#endif - -#ifdef CONFIG_ARCH_TA7S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TA7S -# endif -# define machine_is_ta7s() (machine_arch_type == MACH_TYPE_TA7S) -#else -# define machine_is_ta7s() (0) -#endif - -#ifdef CONFIG_ARCH_TA7V -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TA7V -# endif -# define machine_is_ta7v() (machine_arch_type == MACH_TYPE_TA7V) -#else -# define machine_is_ta7v() (0) -#endif - -#ifdef CONFIG_SA1100_ICARUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICARUS -# endif -# define machine_is_icarus() (machine_arch_type == MACH_TYPE_ICARUS) -#else -# define machine_is_icarus() (0) -#endif - -#ifdef CONFIG_ARCH_H1900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H1900 -# endif -# define machine_is_h1900() (machine_arch_type == MACH_TYPE_H1900) -#else -# define machine_is_h1900() (0) -#endif - -#ifdef CONFIG_SA1100_GEMINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMINI -# endif -# define machine_is_gemini() (machine_arch_type == MACH_TYPE_GEMINI) -#else -# define machine_is_gemini() (0) -#endif - -#ifdef CONFIG_ARCH_AXIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXIM -# endif -# define machine_is_axim() (machine_arch_type == MACH_TYPE_AXIM) -#else -# define machine_is_axim() (0) -#endif - -#ifdef CONFIG_ARCH_AUDIOTRON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUDIOTRON -# endif -# define machine_is_audiotron() (machine_arch_type == MACH_TYPE_AUDIOTRON) -#else -# define machine_is_audiotron() (0) -#endif - -#ifdef CONFIG_ARCH_H2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H2200 -# endif -# define machine_is_h2200() (machine_arch_type == MACH_TYPE_H2200) -#else -# define machine_is_h2200() (0) -#endif - -#ifdef CONFIG_ARCH_LOOX600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOX600 -# endif -# define machine_is_loox600() (machine_arch_type == MACH_TYPE_LOOX600) -#else -# define machine_is_loox600() (0) -#endif - -#ifdef CONFIG_ARCH_NIOP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIOP -# endif -# define machine_is_niop() (machine_arch_type == MACH_TYPE_NIOP) -#else -# define machine_is_niop() (0) -#endif - -#ifdef CONFIG_ARCH_DM310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM310 -# endif -# define machine_is_dm310() (machine_arch_type == MACH_TYPE_DM310) -#else -# define machine_is_dm310() (0) -#endif - -#ifdef CONFIG_ARCH_SEEDPXA_C2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SEEDPXA_C2 -# endif -# define machine_is_seedpxa_c2() (machine_arch_type == MACH_TYPE_SEEDPXA_C2) -#else -# define machine_is_seedpxa_c2() (0) -#endif - -#ifdef CONFIG_ARCH_IXP4XX_MGUARD_PCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP4XX_MGUARD_PCI -# endif -# define machine_is_ixp4xx_mguardpci() (machine_arch_type == MACH_TYPE_IXP4XX_MGUARD_PCI) -#else -# define machine_is_ixp4xx_mguardpci() (0) -#endif - -#ifdef CONFIG_ARCH_H1940 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H1940 -# endif -# define machine_is_h1940() (machine_arch_type == MACH_TYPE_H1940) -#else -# define machine_is_h1940() (0) -#endif - -#ifdef CONFIG_ARCH_SCORPIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCORPIO -# endif -# define machine_is_scorpio() (machine_arch_type == MACH_TYPE_SCORPIO) -#else -# define machine_is_scorpio() (0) -#endif - -#ifdef CONFIG_ARCH_VIVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIVA -# endif -# define machine_is_viva() (machine_arch_type == MACH_TYPE_VIVA) -#else -# define machine_is_viva() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_XCARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_XCARD -# endif -# define machine_is_pxa_xcard() (machine_arch_type == MACH_TYPE_PXA_XCARD) -#else -# define machine_is_pxa_xcard() (0) -#endif - -#ifdef CONFIG_ARCH_CSB335 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB335 -# endif -# define machine_is_csb335() (machine_arch_type == MACH_TYPE_CSB335) -#else -# define machine_is_csb335() (0) -#endif - -#ifdef CONFIG_ARCH_IXRD425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXRD425 -# endif -# define machine_is_ixrd425() (machine_arch_type == MACH_TYPE_IXRD425) -#else -# define machine_is_ixrd425() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80315 -# endif -# define machine_is_iq80315() (machine_arch_type == MACH_TYPE_IQ80315) -#else -# define machine_is_iq80315() (0) -#endif - -#ifdef CONFIG_ARCH_NMP7312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NMP7312 -# endif -# define machine_is_nmp7312() (machine_arch_type == MACH_TYPE_NMP7312) -#else -# define machine_is_nmp7312() (0) -#endif - -#ifdef CONFIG_ARCH_CX861XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX861XX -# endif -# define machine_is_cx861xx() (machine_arch_type == MACH_TYPE_CX861XX) -#else -# define machine_is_cx861xx() (0) -#endif - -#ifdef CONFIG_ARCH_ENP2611 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENP2611 -# endif -# define machine_is_enp2611() (machine_arch_type == MACH_TYPE_ENP2611) -#else -# define machine_is_enp2611() (0) -#endif - -#ifdef CONFIG_SA1100_XDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDA -# endif -# define machine_is_xda() (machine_arch_type == MACH_TYPE_XDA) -#else -# define machine_is_xda() (0) -#endif - -#ifdef CONFIG_ARCH_CSIR_IMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSIR_IMS -# endif -# define machine_is_csir_ims() (machine_arch_type == MACH_TYPE_CSIR_IMS) -#else -# define machine_is_csir_ims() (0) -#endif - -#ifdef CONFIG_ARCH_IXP421_DNAEETH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP421_DNAEETH -# endif -# define machine_is_ixp421_dnaeeth() (machine_arch_type == MACH_TYPE_IXP421_DNAEETH) -#else -# define machine_is_ixp421_dnaeeth() (0) -#endif - -#ifdef CONFIG_ARCH_POCKETSERV9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POCKETSERV9200 -# endif -# define machine_is_pocketserv9200() (machine_arch_type == MACH_TYPE_POCKETSERV9200) -#else -# define machine_is_pocketserv9200() (0) -#endif - -#ifdef CONFIG_ARCH_TOTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOTO -# endif -# define machine_is_toto() (machine_arch_type == MACH_TYPE_TOTO) -#else -# define machine_is_toto() (0) -#endif - -#ifdef CONFIG_ARCH_S3C2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2440 -# endif -# define machine_is_s3c2440() (machine_arch_type == MACH_TYPE_S3C2440) -#else -# define machine_is_s3c2440() (0) -#endif - -#ifdef CONFIG_ARCH_KS8695P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KS8695P -# endif -# define machine_is_ks8695p() (machine_arch_type == MACH_TYPE_KS8695P) -#else -# define machine_is_ks8695p() (0) -#endif - -#ifdef CONFIG_ARCH_SE4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE4000 -# endif -# define machine_is_se4000() (machine_arch_type == MACH_TYPE_SE4000) -#else -# define machine_is_se4000() (0) -#endif - -#ifdef CONFIG_ARCH_QUADRICEPS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUADRICEPS -# endif -# define machine_is_quadriceps() (machine_arch_type == MACH_TYPE_QUADRICEPS) -#else -# define machine_is_quadriceps() (0) -#endif - -#ifdef CONFIG_ARCH_BRONCO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRONCO -# endif -# define machine_is_bronco() (machine_arch_type == MACH_TYPE_BRONCO) -#else -# define machine_is_bronco() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_WIRELESS_TAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_WIRELESS_TAB -# endif -# define machine_is_esl_wireless_tab() (machine_arch_type == MACH_TYPE_ESL_WIRELESS_TAB) -#else -# define machine_is_esl_wireless_tab() (0) -#endif - -#ifdef CONFIG_ARCH_ESL_SOFCOMP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SOFCOMP -# endif -# define machine_is_esl_sofcomp() (machine_arch_type == MACH_TYPE_ESL_SOFCOMP) -#else -# define machine_is_esl_sofcomp() (0) -#endif - -#ifdef CONFIG_ARCH_S5C7375 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5C7375 -# endif -# define machine_is_s5c7375() (machine_arch_type == MACH_TYPE_S5C7375) -#else -# define machine_is_s5c7375() (0) -#endif - -#ifdef CONFIG_ARCH_SPEARHEAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEARHEAD -# endif -# define machine_is_spearhead() (machine_arch_type == MACH_TYPE_SPEARHEAD) -#else -# define machine_is_spearhead() (0) -#endif - -#ifdef CONFIG_ARCH_PANTERA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PANTERA -# endif -# define machine_is_pantera() (machine_arch_type == MACH_TYPE_PANTERA) -#else -# define machine_is_pantera() (0) -#endif - -#ifdef CONFIG_ARCH_PRAYOGLITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRAYOGLITE -# endif -# define machine_is_prayoglite() (machine_arch_type == MACH_TYPE_PRAYOGLITE) -#else -# define machine_is_prayoglite() (0) -#endif - -#ifdef CONFIG_ARCH_GUMSTIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUMSTIX -# endif -# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIX) -#else -# define machine_is_gumstix() (0) -#endif - -#ifdef CONFIG_ARCH_RCUBE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RCUBE -# endif -# define machine_is_rcube() (machine_arch_type == MACH_TYPE_RCUBE) -#else -# define machine_is_rcube() (0) -#endif - -#ifdef CONFIG_ARCH_REA_OLV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REA_OLV -# endif -# define machine_is_rea_olv() (machine_arch_type == MACH_TYPE_REA_OLV) -#else -# define machine_is_rea_olv() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_IPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_IPHONE -# endif -# define machine_is_pxa_iphone() (machine_arch_type == MACH_TYPE_PXA_IPHONE) -#else -# define machine_is_pxa_iphone() (0) -#endif - -#ifdef CONFIG_ARCH_S3C3410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C3410 -# endif -# define machine_is_s3c3410() (machine_arch_type == MACH_TYPE_S3C3410) -#else -# define machine_is_s3c3410() (0) -#endif - -#ifdef CONFIG_ARCH_ESPD_4510B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESPD_4510B -# endif -# define machine_is_espd_4510b() (machine_arch_type == MACH_TYPE_ESPD_4510B) -#else -# define machine_is_espd_4510b() (0) -#endif - -#ifdef CONFIG_ARCH_MP1X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP1X -# endif -# define machine_is_mp1x() (machine_arch_type == MACH_TYPE_MP1X) -#else -# define machine_is_mp1x() (0) -#endif - -#ifdef CONFIG_ARCH_AT91RM9200TB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200TB -# endif -# define machine_is_at91rm9200tb() (machine_arch_type == MACH_TYPE_AT91RM9200TB) -#else -# define machine_is_at91rm9200tb() (0) -#endif - -#ifdef CONFIG_ARCH_ADSVGX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSVGX -# endif -# define machine_is_adsvgx() (machine_arch_type == MACH_TYPE_ADSVGX) -#else -# define machine_is_adsvgx() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H2 -# endif -# define machine_is_omap_h2() (machine_arch_type == MACH_TYPE_OMAP_H2) -#else -# define machine_is_omap_h2() (0) -#endif - -#ifdef CONFIG_ARCH_PELEE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELEE -# endif -# define machine_is_pelee() (machine_arch_type == MACH_TYPE_PELEE) -#else -# define machine_is_pelee() (0) -#endif - -#ifdef CONFIG_MACH_E740 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E740 -# endif -# define machine_is_e740() (machine_arch_type == MACH_TYPE_E740) -#else -# define machine_is_e740() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80331 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80331 -# endif -# define machine_is_iq80331() (machine_arch_type == MACH_TYPE_IQ80331) -#else -# define machine_is_iq80331() (0) -#endif - -#ifdef CONFIG_ARCH_VERSATILE_PB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERSATILE_PB -# endif -# define machine_is_versatile_pb() (machine_arch_type == MACH_TYPE_VERSATILE_PB) -#else -# define machine_is_versatile_pb() (0) -#endif - -#ifdef CONFIG_MACH_KEV7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KEV7A400 -# endif -# define machine_is_kev7a400() (machine_arch_type == MACH_TYPE_KEV7A400) -#else -# define machine_is_kev7a400() (0) -#endif - -#ifdef CONFIG_MACH_LPD7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD7A400 -# endif -# define machine_is_lpd7a400() (machine_arch_type == MACH_TYPE_LPD7A400) -#else -# define machine_is_lpd7a400() (0) -#endif - -#ifdef CONFIG_MACH_LPD7A404 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD7A404 -# endif -# define machine_is_lpd7a404() (machine_arch_type == MACH_TYPE_LPD7A404) -#else -# define machine_is_lpd7a404() (0) -#endif - -#ifdef CONFIG_ARCH_FUJITSU_CAMELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJITSU_CAMELOT -# endif -# define machine_is_fujitsu_camelot() (machine_arch_type == MACH_TYPE_FUJITSU_CAMELOT) -#else -# define machine_is_fujitsu_camelot() (0) -#endif - -#ifdef CONFIG_ARCH_JANUS2M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JANUS2M -# endif -# define machine_is_janus2m() (machine_arch_type == MACH_TYPE_JANUS2M) -#else -# define machine_is_janus2m() (0) -#endif - -#ifdef CONFIG_MACH_EMBTF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMBTF -# endif -# define machine_is_embtf() (machine_arch_type == MACH_TYPE_EMBTF) -#else -# define machine_is_embtf() (0) -#endif - -#ifdef CONFIG_MACH_HPM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPM -# endif -# define machine_is_hpm() (machine_arch_type == MACH_TYPE_HPM) -#else -# define machine_is_hpm() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2410TK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2410TK -# endif -# define machine_is_smdk2410tk() (machine_arch_type == MACH_TYPE_SMDK2410TK) -#else -# define machine_is_smdk2410tk() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2410AJ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2410AJ -# endif -# define machine_is_smdk2410aj() (machine_arch_type == MACH_TYPE_SMDK2410AJ) -#else -# define machine_is_smdk2410aj() (0) -#endif - -#ifdef CONFIG_MACH_STREETRACER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STREETRACER -# endif -# define machine_is_streetracer() (machine_arch_type == MACH_TYPE_STREETRACER) -#else -# define machine_is_streetracer() (0) -#endif - -#ifdef CONFIG_MACH_EFRAME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EFRAME -# endif -# define machine_is_eframe() (machine_arch_type == MACH_TYPE_EFRAME) -#else -# define machine_is_eframe() (0) -#endif - -#ifdef CONFIG_MACH_CSB337 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB337 -# endif -# define machine_is_csb337() (machine_arch_type == MACH_TYPE_CSB337) -#else -# define machine_is_csb337() (0) -#endif - -#ifdef CONFIG_MACH_PXA_LARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_LARK -# endif -# define machine_is_pxa_lark() (machine_arch_type == MACH_TYPE_PXA_LARK) -#else -# define machine_is_pxa_lark() (0) -#endif - -#ifdef CONFIG_MACH_PNP2110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNP2110 -# endif -# define machine_is_pxa_pnp2110() (machine_arch_type == MACH_TYPE_PNP2110) -#else -# define machine_is_pxa_pnp2110() (0) -#endif - -#ifdef CONFIG_MACH_TCC72X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCC72X -# endif -# define machine_is_tcc72x() (machine_arch_type == MACH_TYPE_TCC72X) -#else -# define machine_is_tcc72x() (0) -#endif - -#ifdef CONFIG_MACH_ALTAIR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALTAIR -# endif -# define machine_is_altair() (machine_arch_type == MACH_TYPE_ALTAIR) -#else -# define machine_is_altair() (0) -#endif - -#ifdef CONFIG_MACH_KC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KC3 -# endif -# define machine_is_kc3() (machine_arch_type == MACH_TYPE_KC3) -#else -# define machine_is_kc3() (0) -#endif - -#ifdef CONFIG_MACH_SINTEFTD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SINTEFTD -# endif -# define machine_is_sinteftd() (machine_arch_type == MACH_TYPE_SINTEFTD) -#else -# define machine_is_sinteftd() (0) -#endif - -#ifdef CONFIG_MACH_MAINSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAINSTONE -# endif -# define machine_is_mainstone() (machine_arch_type == MACH_TYPE_MAINSTONE) -#else -# define machine_is_mainstone() (0) -#endif - -#ifdef CONFIG_MACH_ADAY4X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADAY4X -# endif -# define machine_is_aday4x() (machine_arch_type == MACH_TYPE_ADAY4X) -#else -# define machine_is_aday4x() (0) -#endif - -#ifdef CONFIG_MACH_LITE300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LITE300 -# endif -# define machine_is_lite300() (machine_arch_type == MACH_TYPE_LITE300) -#else -# define machine_is_lite300() (0) -#endif - -#ifdef CONFIG_MACH_S5C7376 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5C7376 -# endif -# define machine_is_s5c7376() (machine_arch_type == MACH_TYPE_S5C7376) -#else -# define machine_is_s5c7376() (0) -#endif - -#ifdef CONFIG_MACH_MT02 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MT02 -# endif -# define machine_is_mt02() (machine_arch_type == MACH_TYPE_MT02) -#else -# define machine_is_mt02() (0) -#endif - -#ifdef CONFIG_MACH_MPORT3S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPORT3S -# endif -# define machine_is_mport3s() (machine_arch_type == MACH_TYPE_MPORT3S) -#else -# define machine_is_mport3s() (0) -#endif - -#ifdef CONFIG_MACH_RA_ALPHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RA_ALPHA -# endif -# define machine_is_ra_alpha() (machine_arch_type == MACH_TYPE_RA_ALPHA) -#else -# define machine_is_ra_alpha() (0) -#endif - -#ifdef CONFIG_MACH_XCEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XCEP -# endif -# define machine_is_xcep() (machine_arch_type == MACH_TYPE_XCEP) -#else -# define machine_is_xcep() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_VULCAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_VULCAN -# endif -# define machine_is_arcom_vulcan() (machine_arch_type == MACH_TYPE_ARCOM_VULCAN) -#else -# define machine_is_arcom_vulcan() (0) -#endif - -#ifdef CONFIG_MACH_STARGATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGATE -# endif -# define machine_is_stargate() (machine_arch_type == MACH_TYPE_STARGATE) -#else -# define machine_is_stargate() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLOJ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLOJ -# endif -# define machine_is_armadilloj() (machine_arch_type == MACH_TYPE_ARMADILLOJ) -#else -# define machine_is_armadilloj() (0) -#endif - -#ifdef CONFIG_MACH_ELROY_JACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELROY_JACK -# endif -# define machine_is_elroy_jack() (machine_arch_type == MACH_TYPE_ELROY_JACK) -#else -# define machine_is_elroy_jack() (0) -#endif - -#ifdef CONFIG_MACH_BACKEND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BACKEND -# endif -# define machine_is_backend() (machine_arch_type == MACH_TYPE_BACKEND) -#else -# define machine_is_backend() (0) -#endif - -#ifdef CONFIG_MACH_S5LINBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5LINBOX -# endif -# define machine_is_s5linbox() (machine_arch_type == MACH_TYPE_S5LINBOX) -#else -# define machine_is_s5linbox() (0) -#endif - -#ifdef CONFIG_MACH_NOMADIK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOMADIK -# endif -# define machine_is_nomadik() (machine_arch_type == MACH_TYPE_NOMADIK) -#else -# define machine_is_nomadik() (0) -#endif - -#ifdef CONFIG_MACH_IA_CPU_9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IA_CPU_9200 -# endif -# define machine_is_ia_cpu_9200() (machine_arch_type == MACH_TYPE_IA_CPU_9200) -#else -# define machine_is_ia_cpu_9200() (0) -#endif - -#ifdef CONFIG_MACH_AT91_BJA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91_BJA1 -# endif -# define machine_is_at91_bja1() (machine_arch_type == MACH_TYPE_AT91_BJA1) -#else -# define machine_is_at91_bja1() (0) -#endif - -#ifdef CONFIG_MACH_CORGI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORGI -# endif -# define machine_is_corgi() (machine_arch_type == MACH_TYPE_CORGI) -#else -# define machine_is_corgi() (0) -#endif - -#ifdef CONFIG_MACH_POODLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POODLE -# endif -# define machine_is_poodle() (machine_arch_type == MACH_TYPE_POODLE) -#else -# define machine_is_poodle() (0) -#endif - -#ifdef CONFIG_MACH_TEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEN -# endif -# define machine_is_ten() (machine_arch_type == MACH_TYPE_TEN) -#else -# define machine_is_ten() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP5P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP5P -# endif -# define machine_is_roverp5p() (machine_arch_type == MACH_TYPE_ROVERP5P) -#else -# define machine_is_roverp5p() (0) -#endif - -#ifdef CONFIG_MACH_SC2700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SC2700 -# endif -# define machine_is_sc2700() (machine_arch_type == MACH_TYPE_SC2700) -#else -# define machine_is_sc2700() (0) -#endif - -#ifdef CONFIG_MACH_EX_EAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EX_EAGLE -# endif -# define machine_is_ex_eagle() (machine_arch_type == MACH_TYPE_EX_EAGLE) -#else -# define machine_is_ex_eagle() (0) -#endif - -#ifdef CONFIG_MACH_NX_PXA12 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX_PXA12 -# endif -# define machine_is_nx_pxa12() (machine_arch_type == MACH_TYPE_NX_PXA12) -#else -# define machine_is_nx_pxa12() (0) -#endif - -#ifdef CONFIG_MACH_NX_PXA5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX_PXA5 -# endif -# define machine_is_nx_pxa5() (machine_arch_type == MACH_TYPE_NX_PXA5) -#else -# define machine_is_nx_pxa5() (0) -#endif - -#ifdef CONFIG_MACH_BLACKBOARD2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLACKBOARD2 -# endif -# define machine_is_blackboard2() (machine_arch_type == MACH_TYPE_BLACKBOARD2) -#else -# define machine_is_blackboard2() (0) -#endif - -#ifdef CONFIG_MACH_I819 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I819 -# endif -# define machine_is_i819() (machine_arch_type == MACH_TYPE_I819) -#else -# define machine_is_i819() (0) -#endif - -#ifdef CONFIG_MACH_IXMB995E -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXMB995E -# endif -# define machine_is_ixmb995e() (machine_arch_type == MACH_TYPE_IXMB995E) -#else -# define machine_is_ixmb995e() (0) -#endif - -#ifdef CONFIG_MACH_SKYRIDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYRIDER -# endif -# define machine_is_skyrider() (machine_arch_type == MACH_TYPE_SKYRIDER) -#else -# define machine_is_skyrider() (0) -#endif - -#ifdef CONFIG_MACH_SKYHAWK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYHAWK -# endif -# define machine_is_skyhawk() (machine_arch_type == MACH_TYPE_SKYHAWK) -#else -# define machine_is_skyhawk() (0) -#endif - -#ifdef CONFIG_MACH_ENTERPRISE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENTERPRISE -# endif -# define machine_is_enterprise() (machine_arch_type == MACH_TYPE_ENTERPRISE) -#else -# define machine_is_enterprise() (0) -#endif - -#ifdef CONFIG_MACH_DEP2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2410 -# endif -# define machine_is_dep2410() (machine_arch_type == MACH_TYPE_DEP2410) -#else -# define machine_is_dep2410() (0) -#endif - -#ifdef CONFIG_MACH_ARMCORE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMCORE -# endif -# define machine_is_armcore() (machine_arch_type == MACH_TYPE_ARMCORE) -#else -# define machine_is_armcore() (0) -#endif - -#ifdef CONFIG_MACH_HOBBIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HOBBIT -# endif -# define machine_is_hobbit() (machine_arch_type == MACH_TYPE_HOBBIT) -#else -# define machine_is_hobbit() (0) -#endif - -#ifdef CONFIG_MACH_H7210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7210 -# endif -# define machine_is_h7210() (machine_arch_type == MACH_TYPE_H7210) -#else -# define machine_is_h7210() (0) -#endif - -#ifdef CONFIG_MACH_PXA_NETDCU5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_NETDCU5 -# endif -# define machine_is_pxa_netdcu5() (machine_arch_type == MACH_TYPE_PXA_NETDCU5) -#else -# define machine_is_pxa_netdcu5() (0) -#endif - -#ifdef CONFIG_MACH_ACC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACC -# endif -# define machine_is_acc() (machine_arch_type == MACH_TYPE_ACC) -#else -# define machine_is_acc() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA -# endif -# define machine_is_esl_sarva() (machine_arch_type == MACH_TYPE_ESL_SARVA) -#else -# define machine_is_esl_sarva() (0) -#endif - -#ifdef CONFIG_MACH_XM250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XM250 -# endif -# define machine_is_xm250() (machine_arch_type == MACH_TYPE_XM250) -#else -# define machine_is_xm250() (0) -#endif - -#ifdef CONFIG_MACH_T6TC1XB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T6TC1XB -# endif -# define machine_is_t6tc1xb() (machine_arch_type == MACH_TYPE_T6TC1XB) -#else -# define machine_is_t6tc1xb() (0) -#endif - -#ifdef CONFIG_MACH_ESS710 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESS710 -# endif -# define machine_is_ess710() (machine_arch_type == MACH_TYPE_ESS710) -#else -# define machine_is_ess710() (0) -#endif - -#ifdef CONFIG_MACH_MX31ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31ADS -# endif -# define machine_is_mx31ads() (machine_arch_type == MACH_TYPE_MX31ADS) -#else -# define machine_is_mx31ads() (0) -#endif - -#ifdef CONFIG_MACH_HIMALAYA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIMALAYA -# endif -# define machine_is_himalaya() (machine_arch_type == MACH_TYPE_HIMALAYA) -#else -# define machine_is_himalaya() (0) -#endif - -#ifdef CONFIG_MACH_BOLFENK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BOLFENK -# endif -# define machine_is_bolfenk() (machine_arch_type == MACH_TYPE_BOLFENK) -#else -# define machine_is_bolfenk() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200KR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200KR -# endif -# define machine_is_at91rm9200kr() (machine_arch_type == MACH_TYPE_AT91RM9200KR) -#else -# define machine_is_at91rm9200kr() (0) -#endif - -#ifdef CONFIG_MACH_EDB9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9312 -# endif -# define machine_is_edb9312() (machine_arch_type == MACH_TYPE_EDB9312) -#else -# define machine_is_edb9312() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_GENERIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_GENERIC -# endif -# define machine_is_omap_generic() (machine_arch_type == MACH_TYPE_OMAP_GENERIC) -#else -# define machine_is_omap_generic() (0) -#endif - -#ifdef CONFIG_MACH_AXIMX3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXIMX3 -# endif -# define machine_is_aximx3() (machine_arch_type == MACH_TYPE_AXIMX3) -#else -# define machine_is_aximx3() (0) -#endif - -#ifdef CONFIG_MACH_EB67XDIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EB67XDIP -# endif -# define machine_is_eb67xdip() (machine_arch_type == MACH_TYPE_EB67XDIP) -#else -# define machine_is_eb67xdip() (0) -#endif - -#ifdef CONFIG_MACH_WEBTXS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBTXS -# endif -# define machine_is_webtxs() (machine_arch_type == MACH_TYPE_WEBTXS) -#else -# define machine_is_webtxs() (0) -#endif - -#ifdef CONFIG_MACH_HAWK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HAWK -# endif -# define machine_is_hawk() (machine_arch_type == MACH_TYPE_HAWK) -#else -# define machine_is_hawk() (0) -#endif - -#ifdef CONFIG_MACH_CCAT91SBC001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCAT91SBC001 -# endif -# define machine_is_ccat91sbc001() (machine_arch_type == MACH_TYPE_CCAT91SBC001) -#else -# define machine_is_ccat91sbc001() (0) -#endif - -#ifdef CONFIG_MACH_EXPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXPRESSO -# endif -# define machine_is_expresso() (machine_arch_type == MACH_TYPE_EXPRESSO) -#else -# define machine_is_expresso() (0) -#endif - -#ifdef CONFIG_MACH_H4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H4000 -# endif -# define machine_is_h4000() (machine_arch_type == MACH_TYPE_H4000) -#else -# define machine_is_h4000() (0) -#endif - -#ifdef CONFIG_MACH_DINO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DINO -# endif -# define machine_is_dino() (machine_arch_type == MACH_TYPE_DINO) -#else -# define machine_is_dino() (0) -#endif - -#ifdef CONFIG_MACH_ML675K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML675K -# endif -# define machine_is_ml675k() (machine_arch_type == MACH_TYPE_ML675K) -#else -# define machine_is_ml675k() (0) -#endif - -#ifdef CONFIG_MACH_EDB9301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9301 -# endif -# define machine_is_edb9301() (machine_arch_type == MACH_TYPE_EDB9301) -#else -# define machine_is_edb9301() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315 -# endif -# define machine_is_edb9315() (machine_arch_type == MACH_TYPE_EDB9315) -#else -# define machine_is_edb9315() (0) -#endif - -#ifdef CONFIG_MACH_RECIVA_TT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RECIVA_TT -# endif -# define machine_is_reciva_tt() (machine_arch_type == MACH_TYPE_RECIVA_TT) -#else -# define machine_is_reciva_tt() (0) -#endif - -#ifdef CONFIG_MACH_CSTCB01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSTCB01 -# endif -# define machine_is_cstcb01() (machine_arch_type == MACH_TYPE_CSTCB01) -#else -# define machine_is_cstcb01() (0) -#endif - -#ifdef CONFIG_MACH_CSTCB1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSTCB1 -# endif -# define machine_is_cstcb1() (machine_arch_type == MACH_TYPE_CSTCB1) -#else -# define machine_is_cstcb1() (0) -#endif - -#ifdef CONFIG_MACH_SHADWELL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHADWELL -# endif -# define machine_is_shadwell() (machine_arch_type == MACH_TYPE_SHADWELL) -#else -# define machine_is_shadwell() (0) -#endif - -#ifdef CONFIG_MACH_GOEPEL263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GOEPEL263 -# endif -# define machine_is_goepel263() (machine_arch_type == MACH_TYPE_GOEPEL263) -#else -# define machine_is_goepel263() (0) -#endif - -#ifdef CONFIG_MACH_ACQ100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ100 -# endif -# define machine_is_acq100() (machine_arch_type == MACH_TYPE_ACQ100) -#else -# define machine_is_acq100() (0) -#endif - -#ifdef CONFIG_MACH_MX1FS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX1FS2 -# endif -# define machine_is_mx1fs2() (machine_arch_type == MACH_TYPE_MX1FS2) -#else -# define machine_is_mx1fs2() (0) -#endif - -#ifdef CONFIG_MACH_HIPTOP_G1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIPTOP_G1 -# endif -# define machine_is_hiptop_g1() (machine_arch_type == MACH_TYPE_HIPTOP_G1) -#else -# define machine_is_hiptop_g1() (0) -#endif - -#ifdef CONFIG_MACH_SPARKY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPARKY -# endif -# define machine_is_sparky() (machine_arch_type == MACH_TYPE_SPARKY) -#else -# define machine_is_sparky() (0) -#endif - -#ifdef CONFIG_MACH_NS9750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NS9750 -# endif -# define machine_is_ns9750() (machine_arch_type == MACH_TYPE_NS9750) -#else -# define machine_is_ns9750() (0) -#endif - -#ifdef CONFIG_MACH_PHOENIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHOENIX -# endif -# define machine_is_phoenix() (machine_arch_type == MACH_TYPE_PHOENIX) -#else -# define machine_is_phoenix() (0) -#endif - -#ifdef CONFIG_MACH_VR1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VR1000 -# endif -# define machine_is_vr1000() (machine_arch_type == MACH_TYPE_VR1000) -#else -# define machine_is_vr1000() (0) -#endif - -#ifdef CONFIG_MACH_DEISTERPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTERPXA -# endif -# define machine_is_deisterpxa() (machine_arch_type == MACH_TYPE_DEISTERPXA) -#else -# define machine_is_deisterpxa() (0) -#endif - -#ifdef CONFIG_MACH_BCM1160 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCM1160 -# endif -# define machine_is_bcm1160() (machine_arch_type == MACH_TYPE_BCM1160) -#else -# define machine_is_bcm1160() (0) -#endif - -#ifdef CONFIG_MACH_PCM022 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM022 -# endif -# define machine_is_pcm022() (machine_arch_type == MACH_TYPE_PCM022) -#else -# define machine_is_pcm022() (0) -#endif - -#ifdef CONFIG_MACH_ADSGCX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSGCX -# endif -# define machine_is_adsgcx() (machine_arch_type == MACH_TYPE_ADSGCX) -#else -# define machine_is_adsgcx() (0) -#endif - -#ifdef CONFIG_MACH_DREADNAUGHT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DREADNAUGHT -# endif -# define machine_is_dreadnaught() (machine_arch_type == MACH_TYPE_DREADNAUGHT) -#else -# define machine_is_dreadnaught() (0) -#endif - -#ifdef CONFIG_MACH_DM320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM320 -# endif -# define machine_is_dm320() (machine_arch_type == MACH_TYPE_DM320) -#else -# define machine_is_dm320() (0) -#endif - -#ifdef CONFIG_MACH_MARKOV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARKOV -# endif -# define machine_is_markov() (machine_arch_type == MACH_TYPE_MARKOV) -#else -# define machine_is_markov() (0) -#endif - -#ifdef CONFIG_MACH_COS7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COS7A400 -# endif -# define machine_is_cos7a400() (machine_arch_type == MACH_TYPE_COS7A400) -#else -# define machine_is_cos7a400() (0) -#endif - -#ifdef CONFIG_MACH_MILANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MILANO -# endif -# define machine_is_milano() (machine_arch_type == MACH_TYPE_MILANO) -#else -# define machine_is_milano() (0) -#endif - -#ifdef CONFIG_MACH_UE9328 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UE9328 -# endif -# define machine_is_ue9328() (machine_arch_type == MACH_TYPE_UE9328) -#else -# define machine_is_ue9328() (0) -#endif - -#ifdef CONFIG_MACH_UEX255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UEX255 -# endif -# define machine_is_uex255() (machine_arch_type == MACH_TYPE_UEX255) -#else -# define machine_is_uex255() (0) -#endif - -#ifdef CONFIG_MACH_UE2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UE2410 -# endif -# define machine_is_ue2410() (machine_arch_type == MACH_TYPE_UE2410) -#else -# define machine_is_ue2410() (0) -#endif - -#ifdef CONFIG_MACH_A620 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A620 -# endif -# define machine_is_a620() (machine_arch_type == MACH_TYPE_A620) -#else -# define machine_is_a620() (0) -#endif - -#ifdef CONFIG_MACH_OCELOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCELOT -# endif -# define machine_is_ocelot() (machine_arch_type == MACH_TYPE_OCELOT) -#else -# define machine_is_ocelot() (0) -#endif - -#ifdef CONFIG_MACH_CHEETAH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHEETAH -# endif -# define machine_is_cheetah() (machine_arch_type == MACH_TYPE_CHEETAH) -#else -# define machine_is_cheetah() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PERSEUS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PERSEUS2 -# endif -# define machine_is_omap_perseus2() (machine_arch_type == MACH_TYPE_OMAP_PERSEUS2) -#else -# define machine_is_omap_perseus2() (0) -#endif - -#ifdef CONFIG_MACH_ZVUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZVUE -# endif -# define machine_is_zvue() (machine_arch_type == MACH_TYPE_ZVUE) -#else -# define machine_is_zvue() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP1 -# endif -# define machine_is_roverp1() (machine_arch_type == MACH_TYPE_ROVERP1) -#else -# define machine_is_roverp1() (0) -#endif - -#ifdef CONFIG_MACH_ASIDIAL2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASIDIAL2 -# endif -# define machine_is_asidial2() (machine_arch_type == MACH_TYPE_ASIDIAL2) -#else -# define machine_is_asidial2() (0) -#endif - -#ifdef CONFIG_MACH_S3C24A0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C24A0 -# endif -# define machine_is_s3c24a0() (machine_arch_type == MACH_TYPE_S3C24A0) -#else -# define machine_is_s3c24a0() (0) -#endif - -#ifdef CONFIG_MACH_E800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E800 -# endif -# define machine_is_e800() (machine_arch_type == MACH_TYPE_E800) -#else -# define machine_is_e800() (0) -#endif - -#ifdef CONFIG_MACH_E750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E750 -# endif -# define machine_is_e750() (machine_arch_type == MACH_TYPE_E750) -#else -# define machine_is_e750() (0) -#endif - -#ifdef CONFIG_MACH_S3C5500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C5500 -# endif -# define machine_is_s3c5500() (machine_arch_type == MACH_TYPE_S3C5500) -#else -# define machine_is_s3c5500() (0) -#endif - -#ifdef CONFIG_MACH_SMDK5500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK5500 -# endif -# define machine_is_smdk5500() (machine_arch_type == MACH_TYPE_SMDK5500) -#else -# define machine_is_smdk5500() (0) -#endif - -#ifdef CONFIG_MACH_SIGNALSYNC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIGNALSYNC -# endif -# define machine_is_signalsync() (machine_arch_type == MACH_TYPE_SIGNALSYNC) -#else -# define machine_is_signalsync() (0) -#endif - -#ifdef CONFIG_MACH_NBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NBC -# endif -# define machine_is_nbc() (machine_arch_type == MACH_TYPE_NBC) -#else -# define machine_is_nbc() (0) -#endif - -#ifdef CONFIG_MACH_KODIAK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KODIAK -# endif -# define machine_is_kodiak() (machine_arch_type == MACH_TYPE_KODIAK) -#else -# define machine_is_kodiak() (0) -#endif - -#ifdef CONFIG_MACH_NETBOOKPRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETBOOKPRO -# endif -# define machine_is_netbookpro() (machine_arch_type == MACH_TYPE_NETBOOKPRO) -#else -# define machine_is_netbookpro() (0) -#endif - -#ifdef CONFIG_MACH_HW90200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90200 -# endif -# define machine_is_hw90200() (machine_arch_type == MACH_TYPE_HW90200) -#else -# define machine_is_hw90200() (0) -#endif - -#ifdef CONFIG_MACH_CONDOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONDOR -# endif -# define machine_is_condor() (machine_arch_type == MACH_TYPE_CONDOR) -#else -# define machine_is_condor() (0) -#endif - -#ifdef CONFIG_MACH_CUP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CUP -# endif -# define machine_is_cup() (machine_arch_type == MACH_TYPE_CUP) -#else -# define machine_is_cup() (0) -#endif - -#ifdef CONFIG_MACH_KITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KITE -# endif -# define machine_is_kite() (machine_arch_type == MACH_TYPE_KITE) -#else -# define machine_is_kite() (0) -#endif - -#ifdef CONFIG_MACH_SCB9328 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCB9328 -# endif -# define machine_is_scb9328() (machine_arch_type == MACH_TYPE_SCB9328) -#else -# define machine_is_scb9328() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H3 -# endif -# define machine_is_omap_h3() (machine_arch_type == MACH_TYPE_OMAP_H3) -#else -# define machine_is_omap_h3() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H4 -# endif -# define machine_is_omap_h4() (machine_arch_type == MACH_TYPE_OMAP_H4) -#else -# define machine_is_omap_h4() (0) -#endif - -#ifdef CONFIG_MACH_N10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N10 -# endif -# define machine_is_n10() (machine_arch_type == MACH_TYPE_N10) -#else -# define machine_is_n10() (0) -#endif - -#ifdef CONFIG_MACH_MONTAJADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MONTAJADE -# endif -# define machine_is_montejade() (machine_arch_type == MACH_TYPE_MONTAJADE) -#else -# define machine_is_montejade() (0) -#endif - -#ifdef CONFIG_MACH_SG560 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG560 -# endif -# define machine_is_sg560() (machine_arch_type == MACH_TYPE_SG560) -#else -# define machine_is_sg560() (0) -#endif - -#ifdef CONFIG_MACH_DP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DP1000 -# endif -# define machine_is_dp1000() (machine_arch_type == MACH_TYPE_DP1000) -#else -# define machine_is_dp1000() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_OSK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_OSK -# endif -# define machine_is_omap_osk() (machine_arch_type == MACH_TYPE_OMAP_OSK) -#else -# define machine_is_omap_osk() (0) -#endif - -#ifdef CONFIG_MACH_RG100V3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RG100V3 -# endif -# define machine_is_rg100v3() (machine_arch_type == MACH_TYPE_RG100V3) -#else -# define machine_is_rg100v3() (0) -#endif - -#ifdef CONFIG_MACH_MX2ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX2ADS -# endif -# define machine_is_mx2ads() (machine_arch_type == MACH_TYPE_MX2ADS) -#else -# define machine_is_mx2ads() (0) -#endif - -#ifdef CONFIG_MACH_PXA_KILO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_KILO -# endif -# define machine_is_pxa_kilo() (machine_arch_type == MACH_TYPE_PXA_KILO) -#else -# define machine_is_pxa_kilo() (0) -#endif - -#ifdef CONFIG_MACH_IXP4XX_EAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP4XX_EAGLE -# endif -# define machine_is_ixp4xx_eagle() (machine_arch_type == MACH_TYPE_IXP4XX_EAGLE) -#else -# define machine_is_ixp4xx_eagle() (0) -#endif - -#ifdef CONFIG_MACH_TOSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOSA -# endif -# define machine_is_tosa() (machine_arch_type == MACH_TYPE_TOSA) -#else -# define machine_is_tosa() (0) -#endif - -#ifdef CONFIG_MACH_MB2520F -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB2520F -# endif -# define machine_is_mb2520f() (machine_arch_type == MACH_TYPE_MB2520F) -#else -# define machine_is_mb2520f() (0) -#endif - -#ifdef CONFIG_MACH_EMC1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMC1000 -# endif -# define machine_is_emc1000() (machine_arch_type == MACH_TYPE_EMC1000) -#else -# define machine_is_emc1000() (0) -#endif - -#ifdef CONFIG_MACH_TIDSC25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIDSC25 -# endif -# define machine_is_tidsc25() (machine_arch_type == MACH_TYPE_TIDSC25) -#else -# define machine_is_tidsc25() (0) -#endif - -#ifdef CONFIG_MACH_AKCPMXL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKCPMXL -# endif -# define machine_is_akcpmxl() (machine_arch_type == MACH_TYPE_AKCPMXL) -#else -# define machine_is_akcpmxl() (0) -#endif - -#ifdef CONFIG_MACH_AV3XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AV3XX -# endif -# define machine_is_av3xx() (machine_arch_type == MACH_TYPE_AV3XX) -#else -# define machine_is_av3xx() (0) -#endif - -#ifdef CONFIG_MACH_AVILA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVILA -# endif -# define machine_is_avila() (machine_arch_type == MACH_TYPE_AVILA) -#else -# define machine_is_avila() (0) -#endif - -#ifdef CONFIG_MACH_PXA_MPM10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_MPM10 -# endif -# define machine_is_pxa_mpm10() (machine_arch_type == MACH_TYPE_PXA_MPM10) -#else -# define machine_is_pxa_mpm10() (0) -#endif - -#ifdef CONFIG_MACH_PXA_KYANITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_KYANITE -# endif -# define machine_is_pxa_kyanite() (machine_arch_type == MACH_TYPE_PXA_KYANITE) -#else -# define machine_is_pxa_kyanite() (0) -#endif - -#ifdef CONFIG_MACH_SGOLD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SGOLD -# endif -# define machine_is_sgold() (machine_arch_type == MACH_TYPE_SGOLD) -#else -# define machine_is_sgold() (0) -#endif - -#ifdef CONFIG_MACH_OSCAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSCAR -# endif -# define machine_is_oscar() (machine_arch_type == MACH_TYPE_OSCAR) -#else -# define machine_is_oscar() (0) -#endif - -#ifdef CONFIG_MACH_EPXA4USB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPXA4USB2 -# endif -# define machine_is_epxa4usb2() (machine_arch_type == MACH_TYPE_EPXA4USB2) -#else -# define machine_is_epxa4usb2() (0) -#endif - -#ifdef CONFIG_MACH_XSENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSENGINE -# endif -# define machine_is_xsengine() (machine_arch_type == MACH_TYPE_XSENGINE) -#else -# define machine_is_xsengine() (0) -#endif - -#ifdef CONFIG_MACH_IP600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IP600 -# endif -# define machine_is_ip600() (machine_arch_type == MACH_TYPE_IP600) -#else -# define machine_is_ip600() (0) -#endif - -#ifdef CONFIG_MACH_MCAN2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCAN2 -# endif -# define machine_is_mcan2() (machine_arch_type == MACH_TYPE_MCAN2) -#else -# define machine_is_mcan2() (0) -#endif - -#ifdef CONFIG_MACH_DDI_BLUERIDGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DDI_BLUERIDGE -# endif -# define machine_is_ddi_blueridge() (machine_arch_type == MACH_TYPE_DDI_BLUERIDGE) -#else -# define machine_is_ddi_blueridge() (0) -#endif - -#ifdef CONFIG_MACH_SKYMINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYMINDER -# endif -# define machine_is_skyminder() (machine_arch_type == MACH_TYPE_SKYMINDER) -#else -# define machine_is_skyminder() (0) -#endif - -#ifdef CONFIG_MACH_LPD79520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD79520 -# endif -# define machine_is_lpd79520() (machine_arch_type == MACH_TYPE_LPD79520) -#else -# define machine_is_lpd79520() (0) -#endif - -#ifdef CONFIG_MACH_EDB9302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9302 -# endif -# define machine_is_edb9302() (machine_arch_type == MACH_TYPE_EDB9302) -#else -# define machine_is_edb9302() (0) -#endif - -#ifdef CONFIG_MACH_HW90340 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90340 -# endif -# define machine_is_hw90340() (machine_arch_type == MACH_TYPE_HW90340) -#else -# define machine_is_hw90340() (0) -#endif - -#ifdef CONFIG_MACH_CIP_BOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CIP_BOX -# endif -# define machine_is_cip_box() (machine_arch_type == MACH_TYPE_CIP_BOX) -#else -# define machine_is_cip_box() (0) -#endif - -#ifdef CONFIG_MACH_IVPN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IVPN -# endif -# define machine_is_ivpn() (machine_arch_type == MACH_TYPE_IVPN) -#else -# define machine_is_ivpn() (0) -#endif - -#ifdef CONFIG_MACH_RSOC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSOC2 -# endif -# define machine_is_rsoc2() (machine_arch_type == MACH_TYPE_RSOC2) -#else -# define machine_is_rsoc2() (0) -#endif - -#ifdef CONFIG_MACH_HUSKY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUSKY -# endif -# define machine_is_husky() (machine_arch_type == MACH_TYPE_HUSKY) -#else -# define machine_is_husky() (0) -#endif - -#ifdef CONFIG_MACH_BOXER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BOXER -# endif -# define machine_is_boxer() (machine_arch_type == MACH_TYPE_BOXER) -#else -# define machine_is_boxer() (0) -#endif - -#ifdef CONFIG_MACH_SHEPHERD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHEPHERD -# endif -# define machine_is_shepherd() (machine_arch_type == MACH_TYPE_SHEPHERD) -#else -# define machine_is_shepherd() (0) -#endif - -#ifdef CONFIG_MACH_AML42800AA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML42800AA -# endif -# define machine_is_aml42800aa() (machine_arch_type == MACH_TYPE_AML42800AA) -#else -# define machine_is_aml42800aa() (0) -#endif - -#ifdef CONFIG_MACH_LPC2294 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC2294 -# endif -# define machine_is_lpc2294() (machine_arch_type == MACH_TYPE_LPC2294) -#else -# define machine_is_lpc2294() (0) -#endif - -#ifdef CONFIG_MACH_SWITCHGRASS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWITCHGRASS -# endif -# define machine_is_switchgrass() (machine_arch_type == MACH_TYPE_SWITCHGRASS) -#else -# define machine_is_switchgrass() (0) -#endif - -#ifdef CONFIG_MACH_ENS_CMU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENS_CMU -# endif -# define machine_is_ens_cmu() (machine_arch_type == MACH_TYPE_ENS_CMU) -#else -# define machine_is_ens_cmu() (0) -#endif - -#ifdef CONFIG_MACH_MM6_SDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MM6_SDB -# endif -# define machine_is_mm6_sdb() (machine_arch_type == MACH_TYPE_MM6_SDB) -#else -# define machine_is_mm6_sdb() (0) -#endif - -#ifdef CONFIG_MACH_SATURN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SATURN -# endif -# define machine_is_saturn() (machine_arch_type == MACH_TYPE_SATURN) -#else -# define machine_is_saturn() (0) -#endif - -#ifdef CONFIG_MACH_I30030EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I30030EVB -# endif -# define machine_is_i30030evb() (machine_arch_type == MACH_TYPE_I30030EVB) -#else -# define machine_is_i30030evb() (0) -#endif - -#ifdef CONFIG_MACH_MXC27530EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC27530EVB -# endif -# define machine_is_mxc27530evb() (machine_arch_type == MACH_TYPE_MXC27530EVB) -#else -# define machine_is_mxc27530evb() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2800 -# endif -# define machine_is_smdk2800() (machine_arch_type == MACH_TYPE_SMDK2800) -#else -# define machine_is_smdk2800() (0) -#endif - -#ifdef CONFIG_MACH_MTWILSON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MTWILSON -# endif -# define machine_is_mtwilson() (machine_arch_type == MACH_TYPE_MTWILSON) -#else -# define machine_is_mtwilson() (0) -#endif - -#ifdef CONFIG_MACH_ZITI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZITI -# endif -# define machine_is_ziti() (machine_arch_type == MACH_TYPE_ZITI) -#else -# define machine_is_ziti() (0) -#endif - -#ifdef CONFIG_MACH_GRANDFATHER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRANDFATHER -# endif -# define machine_is_grandfather() (machine_arch_type == MACH_TYPE_GRANDFATHER) -#else -# define machine_is_grandfather() (0) -#endif - -#ifdef CONFIG_MACH_TENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TENGINE -# endif -# define machine_is_tengine() (machine_arch_type == MACH_TYPE_TENGINE) -#else -# define machine_is_tengine() (0) -#endif - -#ifdef CONFIG_MACH_S3C2460 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2460 -# endif -# define machine_is_s3c2460() (machine_arch_type == MACH_TYPE_S3C2460) -#else -# define machine_is_s3c2460() (0) -#endif - -#ifdef CONFIG_MACH_PDM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDM -# endif -# define machine_is_pdm() (machine_arch_type == MACH_TYPE_PDM) -#else -# define machine_is_pdm() (0) -#endif - -#ifdef CONFIG_MACH_H4700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H4700 -# endif -# define machine_is_h4700() (machine_arch_type == MACH_TYPE_H4700) -#else -# define machine_is_h4700() (0) -#endif - -#ifdef CONFIG_MACH_H6300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6300 -# endif -# define machine_is_h6300() (machine_arch_type == MACH_TYPE_H6300) -#else -# define machine_is_h6300() (0) -#endif - -#ifdef CONFIG_MACH_RZ1700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RZ1700 -# endif -# define machine_is_rz1700() (machine_arch_type == MACH_TYPE_RZ1700) -#else -# define machine_is_rz1700() (0) -#endif - -#ifdef CONFIG_MACH_A716 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A716 -# endif -# define machine_is_a716() (machine_arch_type == MACH_TYPE_A716) -#else -# define machine_is_a716() (0) -#endif - -#ifdef CONFIG_MACH_ESTK2440A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESTK2440A -# endif -# define machine_is_estk2440a() (machine_arch_type == MACH_TYPE_ESTK2440A) -#else -# define machine_is_estk2440a() (0) -#endif - -#ifdef CONFIG_MACH_ATWIXP425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATWIXP425 -# endif -# define machine_is_atwixp425() (machine_arch_type == MACH_TYPE_ATWIXP425) -#else -# define machine_is_atwixp425() (0) -#endif - -#ifdef CONFIG_MACH_CSB336 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB336 -# endif -# define machine_is_csb336() (machine_arch_type == MACH_TYPE_CSB336) -#else -# define machine_is_csb336() (0) -#endif - -#ifdef CONFIG_MACH_RIRM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIRM2 -# endif -# define machine_is_rirm2() (machine_arch_type == MACH_TYPE_RIRM2) -#else -# define machine_is_rirm2() (0) -#endif - -#ifdef CONFIG_MACH_CX23518 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX23518 -# endif -# define machine_is_cx23518() (machine_arch_type == MACH_TYPE_CX23518) -#else -# define machine_is_cx23518() (0) -#endif - -#ifdef CONFIG_MACH_CX2351X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CX2351X -# endif -# define machine_is_cx2351x() (machine_arch_type == MACH_TYPE_CX2351X) -#else -# define machine_is_cx2351x() (0) -#endif - -#ifdef CONFIG_MACH_COMPUTIME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMPUTIME -# endif -# define machine_is_computime() (machine_arch_type == MACH_TYPE_COMPUTIME) -#else -# define machine_is_computime() (0) -#endif - -#ifdef CONFIG_MACH_IZARUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IZARUS -# endif -# define machine_is_izarus() (machine_arch_type == MACH_TYPE_IZARUS) -#else -# define machine_is_izarus() (0) -#endif - -#ifdef CONFIG_MACH_RTS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RTS -# endif -# define machine_is_pxa_rts() (machine_arch_type == MACH_TYPE_RTS) -#else -# define machine_is_pxa_rts() (0) -#endif - -#ifdef CONFIG_MACH_SE5100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE5100 -# endif -# define machine_is_se5100() (machine_arch_type == MACH_TYPE_SE5100) -#else -# define machine_is_se5100() (0) -#endif - -#ifdef CONFIG_MACH_S3C2510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2510 -# endif -# define machine_is_s3c2510() (machine_arch_type == MACH_TYPE_S3C2510) -#else -# define machine_is_s3c2510() (0) -#endif - -#ifdef CONFIG_MACH_CSB437TL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB437TL -# endif -# define machine_is_csb437tl() (machine_arch_type == MACH_TYPE_CSB437TL) -#else -# define machine_is_csb437tl() (0) -#endif - -#ifdef CONFIG_MACH_SLAUSON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SLAUSON -# endif -# define machine_is_slauson() (machine_arch_type == MACH_TYPE_SLAUSON) -#else -# define machine_is_slauson() (0) -#endif - -#ifdef CONFIG_MACH_PEARLRIVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PEARLRIVER -# endif -# define machine_is_pearlriver() (machine_arch_type == MACH_TYPE_PEARLRIVER) -#else -# define machine_is_pearlriver() (0) -#endif - -#ifdef CONFIG_MACH_TDC_P210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TDC_P210 -# endif -# define machine_is_tdc_p210() (machine_arch_type == MACH_TYPE_TDC_P210) -#else -# define machine_is_tdc_p210() (0) -#endif - -#ifdef CONFIG_MACH_SG580 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG580 -# endif -# define machine_is_sg580() (machine_arch_type == MACH_TYPE_SG580) -#else -# define machine_is_sg580() (0) -#endif - -#ifdef CONFIG_MACH_WRSBCARM7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WRSBCARM7 -# endif -# define machine_is_wrsbcarm7() (machine_arch_type == MACH_TYPE_WRSBCARM7) -#else -# define machine_is_wrsbcarm7() (0) -#endif - -#ifdef CONFIG_MACH_IPD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPD -# endif -# define machine_is_ipd() (machine_arch_type == MACH_TYPE_IPD) -#else -# define machine_is_ipd() (0) -#endif - -#ifdef CONFIG_MACH_PXA_DNP2110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_DNP2110 -# endif -# define machine_is_pxa_dnp2110() (machine_arch_type == MACH_TYPE_PXA_DNP2110) -#else -# define machine_is_pxa_dnp2110() (0) -#endif - -#ifdef CONFIG_MACH_XAENIAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XAENIAX -# endif -# define machine_is_xaeniax() (machine_arch_type == MACH_TYPE_XAENIAX) -#else -# define machine_is_xaeniax() (0) -#endif - -#ifdef CONFIG_MACH_SOMN4250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOMN4250 -# endif -# define machine_is_somn4250() (machine_arch_type == MACH_TYPE_SOMN4250) -#else -# define machine_is_somn4250() (0) -#endif - -#ifdef CONFIG_MACH_PLEB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLEB2 -# endif -# define machine_is_pleb2() (machine_arch_type == MACH_TYPE_PLEB2) -#else -# define machine_is_pleb2() (0) -#endif - -#ifdef CONFIG_MACH_CORNWALLIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORNWALLIS -# endif -# define machine_is_cornwallis() (machine_arch_type == MACH_TYPE_CORNWALLIS) -#else -# define machine_is_cornwallis() (0) -#endif - -#ifdef CONFIG_MACH_GURNEY_DRV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GURNEY_DRV -# endif -# define machine_is_gurney_drv() (machine_arch_type == MACH_TYPE_GURNEY_DRV) -#else -# define machine_is_gurney_drv() (0) -#endif - -#ifdef CONFIG_MACH_CHAFFEE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHAFFEE -# endif -# define machine_is_chaffee() (machine_arch_type == MACH_TYPE_CHAFFEE) -#else -# define machine_is_chaffee() (0) -#endif - -#ifdef CONFIG_MACH_RMS101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RMS101 -# endif -# define machine_is_rms101() (machine_arch_type == MACH_TYPE_RMS101) -#else -# define machine_is_rms101() (0) -#endif - -#ifdef CONFIG_MACH_RX3715 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RX3715 -# endif -# define machine_is_rx3715() (machine_arch_type == MACH_TYPE_RX3715) -#else -# define machine_is_rx3715() (0) -#endif - -#ifdef CONFIG_MACH_SWIFT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWIFT -# endif -# define machine_is_swift() (machine_arch_type == MACH_TYPE_SWIFT) -#else -# define machine_is_swift() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP7 -# endif -# define machine_is_roverp7() (machine_arch_type == MACH_TYPE_ROVERP7) -#else -# define machine_is_roverp7() (0) -#endif - -#ifdef CONFIG_MACH_PR818S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PR818S -# endif -# define machine_is_pr818s() (machine_arch_type == MACH_TYPE_PR818S) -#else -# define machine_is_pr818s() (0) -#endif - -#ifdef CONFIG_MACH_TRXPRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRXPRO -# endif -# define machine_is_trxpro() (machine_arch_type == MACH_TYPE_TRXPRO) -#else -# define machine_is_trxpro() (0) -#endif - -#ifdef CONFIG_MACH_NSLU2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSLU2 -# endif -# define machine_is_nslu2() (machine_arch_type == MACH_TYPE_NSLU2) -#else -# define machine_is_nslu2() (0) -#endif - -#ifdef CONFIG_MACH_E400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E400 -# endif -# define machine_is_e400() (machine_arch_type == MACH_TYPE_E400) -#else -# define machine_is_e400() (0) -#endif - -#ifdef CONFIG_MACH_TRAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRAB -# endif -# define machine_is_trab() (machine_arch_type == MACH_TYPE_TRAB) -#else -# define machine_is_trab() (0) -#endif - -#ifdef CONFIG_MACH_CMC_PU2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMC_PU2 -# endif -# define machine_is_cmc_pu2() (machine_arch_type == MACH_TYPE_CMC_PU2) -#else -# define machine_is_cmc_pu2() (0) -#endif - -#ifdef CONFIG_MACH_FULCRUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FULCRUM -# endif -# define machine_is_fulcrum() (machine_arch_type == MACH_TYPE_FULCRUM) -#else -# define machine_is_fulcrum() (0) -#endif - -#ifdef CONFIG_MACH_NETGATE42X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETGATE42X -# endif -# define machine_is_netgate42x() (machine_arch_type == MACH_TYPE_NETGATE42X) -#else -# define machine_is_netgate42x() (0) -#endif - -#ifdef CONFIG_MACH_STR710 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STR710 -# endif -# define machine_is_str710() (machine_arch_type == MACH_TYPE_STR710) -#else -# define machine_is_str710() (0) -#endif - -#ifdef CONFIG_MACH_IXDPG425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDPG425 -# endif -# define machine_is_ixdpg425() (machine_arch_type == MACH_TYPE_IXDPG425) -#else -# define machine_is_ixdpg425() (0) -#endif - -#ifdef CONFIG_MACH_TOMTOMGO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOMTOMGO -# endif -# define machine_is_tomtomgo() (machine_arch_type == MACH_TYPE_TOMTOMGO) -#else -# define machine_is_tomtomgo() (0) -#endif - -#ifdef CONFIG_MACH_VERSATILE_AB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERSATILE_AB -# endif -# define machine_is_versatile_ab() (machine_arch_type == MACH_TYPE_VERSATILE_AB) -#else -# define machine_is_versatile_ab() (0) -#endif - -#ifdef CONFIG_MACH_EDB9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9307 -# endif -# define machine_is_edb9307() (machine_arch_type == MACH_TYPE_EDB9307) -#else -# define machine_is_edb9307() (0) -#endif - -#ifdef CONFIG_MACH_SG565 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG565 -# endif -# define machine_is_sg565() (machine_arch_type == MACH_TYPE_SG565) -#else -# define machine_is_sg565() (0) -#endif - -#ifdef CONFIG_MACH_LPD79524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD79524 -# endif -# define machine_is_lpd79524() (machine_arch_type == MACH_TYPE_LPD79524) -#else -# define machine_is_lpd79524() (0) -#endif - -#ifdef CONFIG_MACH_LPD79525 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD79525 -# endif -# define machine_is_lpd79525() (machine_arch_type == MACH_TYPE_LPD79525) -#else -# define machine_is_lpd79525() (0) -#endif - -#ifdef CONFIG_MACH_RMS100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RMS100 -# endif -# define machine_is_rms100() (machine_arch_type == MACH_TYPE_RMS100) -#else -# define machine_is_rms100() (0) -#endif - -#ifdef CONFIG_MACH_KB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KB9200 -# endif -# define machine_is_kb9200() (machine_arch_type == MACH_TYPE_KB9200) -#else -# define machine_is_kb9200() (0) -#endif - -#ifdef CONFIG_MACH_SX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SX1 -# endif -# define machine_is_sx1() (machine_arch_type == MACH_TYPE_SX1) -#else -# define machine_is_sx1() (0) -#endif - -#ifdef CONFIG_MACH_HMS39C7092 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMS39C7092 -# endif -# define machine_is_hms39c7092() (machine_arch_type == MACH_TYPE_HMS39C7092) -#else -# define machine_is_hms39c7092() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO -# endif -# define machine_is_armadillo() (machine_arch_type == MACH_TYPE_ARMADILLO) -#else -# define machine_is_armadillo() (0) -#endif - -#ifdef CONFIG_MACH_IPCU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPCU -# endif -# define machine_is_ipcu() (machine_arch_type == MACH_TYPE_IPCU) -#else -# define machine_is_ipcu() (0) -#endif - -#ifdef CONFIG_MACH_LOOX720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOX720 -# endif -# define machine_is_loox720() (machine_arch_type == MACH_TYPE_LOOX720) -#else -# define machine_is_loox720() (0) -#endif - -#ifdef CONFIG_MACH_IXDP465 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP465 -# endif -# define machine_is_ixdp465() (machine_arch_type == MACH_TYPE_IXDP465) -#else -# define machine_is_ixdp465() (0) -#endif - -#ifdef CONFIG_MACH_IXDP2351 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2351 -# endif -# define machine_is_ixdp2351() (machine_arch_type == MACH_TYPE_IXDP2351) -#else -# define machine_is_ixdp2351() (0) -#endif - -#ifdef CONFIG_MACH_ADSVIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSVIX -# endif -# define machine_is_adsvix() (machine_arch_type == MACH_TYPE_ADSVIX) -#else -# define machine_is_adsvix() (0) -#endif - -#ifdef CONFIG_MACH_DM270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM270 -# endif -# define machine_is_dm270() (machine_arch_type == MACH_TYPE_DM270) -#else -# define machine_is_dm270() (0) -#endif - -#ifdef CONFIG_MACH_SOCLTPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOCLTPLUS -# endif -# define machine_is_socltplus() (machine_arch_type == MACH_TYPE_SOCLTPLUS) -#else -# define machine_is_socltplus() (0) -#endif - -#ifdef CONFIG_MACH_ECIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECIA -# endif -# define machine_is_ecia() (machine_arch_type == MACH_TYPE_ECIA) -#else -# define machine_is_ecia() (0) -#endif - -#ifdef CONFIG_MACH_CM4008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM4008 -# endif -# define machine_is_cm4008() (machine_arch_type == MACH_TYPE_CM4008) -#else -# define machine_is_cm4008() (0) -#endif - -#ifdef CONFIG_MACH_P2001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P2001 -# endif -# define machine_is_p2001() (machine_arch_type == MACH_TYPE_P2001) -#else -# define machine_is_p2001() (0) -#endif - -#ifdef CONFIG_MACH_TWISTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TWISTER -# endif -# define machine_is_twister() (machine_arch_type == MACH_TYPE_TWISTER) -#else -# define machine_is_twister() (0) -#endif - -#ifdef CONFIG_MACH_MUDSHARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MUDSHARK -# endif -# define machine_is_mudshark() (machine_arch_type == MACH_TYPE_MUDSHARK) -#else -# define machine_is_mudshark() (0) -#endif - -#ifdef CONFIG_MACH_HB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HB2 -# endif -# define machine_is_hb2() (machine_arch_type == MACH_TYPE_HB2) -#else -# define machine_is_hb2() (0) -#endif - -#ifdef CONFIG_MACH_IQ80332 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80332 -# endif -# define machine_is_iq80332() (machine_arch_type == MACH_TYPE_IQ80332) -#else -# define machine_is_iq80332() (0) -#endif - -#ifdef CONFIG_MACH_SENDT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SENDT -# endif -# define machine_is_sendt() (machine_arch_type == MACH_TYPE_SENDT) -#else -# define machine_is_sendt() (0) -#endif - -#ifdef CONFIG_MACH_MX2JAZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX2JAZZ -# endif -# define machine_is_mx2jazz() (machine_arch_type == MACH_TYPE_MX2JAZZ) -#else -# define machine_is_mx2jazz() (0) -#endif - -#ifdef CONFIG_MACH_MULTIIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTIIO -# endif -# define machine_is_multiio() (machine_arch_type == MACH_TYPE_MULTIIO) -#else -# define machine_is_multiio() (0) -#endif - -#ifdef CONFIG_MACH_HRDISPLAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HRDISPLAY -# endif -# define machine_is_hrdisplay() (machine_arch_type == MACH_TYPE_HRDISPLAY) -#else -# define machine_is_hrdisplay() (0) -#endif - -#ifdef CONFIG_MACH_MXC27530ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC27530ADS -# endif -# define machine_is_mxc27530ads() (machine_arch_type == MACH_TYPE_MXC27530ADS) -#else -# define machine_is_mxc27530ads() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS3 -# endif -# define machine_is_trizeps3() (machine_arch_type == MACH_TYPE_TRIZEPS3) -#else -# define machine_is_trizeps3() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZA -# endif -# define machine_is_zefeerdza() (machine_arch_type == MACH_TYPE_ZEFEERDZA) -#else -# define machine_is_zefeerdza() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZB -# endif -# define machine_is_zefeerdzb() (machine_arch_type == MACH_TYPE_ZEFEERDZB) -#else -# define machine_is_zefeerdzb() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZG -# endif -# define machine_is_zefeerdzg() (machine_arch_type == MACH_TYPE_ZEFEERDZG) -#else -# define machine_is_zefeerdzg() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZN -# endif -# define machine_is_zefeerdzn() (machine_arch_type == MACH_TYPE_ZEFEERDZN) -#else -# define machine_is_zefeerdzn() (0) -#endif - -#ifdef CONFIG_MACH_ZEFEERDZQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZEFEERDZQ -# endif -# define machine_is_zefeerdzq() (machine_arch_type == MACH_TYPE_ZEFEERDZQ) -#else -# define machine_is_zefeerdzq() (0) -#endif - -#ifdef CONFIG_MACH_GTWX5715 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GTWX5715 -# endif -# define machine_is_gtwx5715() (machine_arch_type == MACH_TYPE_GTWX5715) -#else -# define machine_is_gtwx5715() (0) -#endif - -#ifdef CONFIG_MACH_ASTRO_JACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASTRO_JACK -# endif -# define machine_is_astro_jack() (machine_arch_type == MACH_TYPE_ASTRO_JACK) -#else -# define machine_is_astro_jack() (0) -#endif - -#ifdef CONFIG_MACH_TIP03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIP03 -# endif -# define machine_is_tip03() (machine_arch_type == MACH_TYPE_TIP03) -#else -# define machine_is_tip03() (0) -#endif - -#ifdef CONFIG_MACH_A9200EC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9200EC -# endif -# define machine_is_a9200ec() (machine_arch_type == MACH_TYPE_A9200EC) -#else -# define machine_is_a9200ec() (0) -#endif - -#ifdef CONFIG_MACH_PNX0105 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX0105 -# endif -# define machine_is_pnx0105() (machine_arch_type == MACH_TYPE_PNX0105) -#else -# define machine_is_pnx0105() (0) -#endif - -#ifdef CONFIG_MACH_ADCPOECPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADCPOECPU -# endif -# define machine_is_adcpoecpu() (machine_arch_type == MACH_TYPE_ADCPOECPU) -#else -# define machine_is_adcpoecpu() (0) -#endif - -#ifdef CONFIG_MACH_CSB637 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB637 -# endif -# define machine_is_csb637() (machine_arch_type == MACH_TYPE_CSB637) -#else -# define machine_is_csb637() (0) -#endif - -#ifdef CONFIG_MACH_MB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9200 -# endif -# define machine_is_mb9200() (machine_arch_type == MACH_TYPE_MB9200) -#else -# define machine_is_mb9200() (0) -#endif - -#ifdef CONFIG_MACH_KULUN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KULUN -# endif -# define machine_is_kulun() (machine_arch_type == MACH_TYPE_KULUN) -#else -# define machine_is_kulun() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER -# endif -# define machine_is_snapper() (machine_arch_type == MACH_TYPE_SNAPPER) -#else -# define machine_is_snapper() (0) -#endif - -#ifdef CONFIG_MACH_OPTIMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPTIMA -# endif -# define machine_is_optima() (machine_arch_type == MACH_TYPE_OPTIMA) -#else -# define machine_is_optima() (0) -#endif - -#ifdef CONFIG_MACH_DLHSBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DLHSBC -# endif -# define machine_is_dlhsbc() (machine_arch_type == MACH_TYPE_DLHSBC) -#else -# define machine_is_dlhsbc() (0) -#endif - -#ifdef CONFIG_MACH_X30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_X30 -# endif -# define machine_is_x30() (machine_arch_type == MACH_TYPE_X30) -#else -# define machine_is_x30() (0) -#endif - -#ifdef CONFIG_MACH_N30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N30 -# endif -# define machine_is_n30() (machine_arch_type == MACH_TYPE_N30) -#else -# define machine_is_n30() (0) -#endif - -#ifdef CONFIG_MACH_MANGA_KS8695 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MANGA_KS8695 -# endif -# define machine_is_manga_ks8695() (machine_arch_type == MACH_TYPE_MANGA_KS8695) -#else -# define machine_is_manga_ks8695() (0) -#endif - -#ifdef CONFIG_MACH_AJAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AJAX -# endif -# define machine_is_ajax() (machine_arch_type == MACH_TYPE_AJAX) -#else -# define machine_is_ajax() (0) -#endif - -#ifdef CONFIG_MACH_NEC_MP900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEC_MP900 -# endif -# define machine_is_nec_mp900() (machine_arch_type == MACH_TYPE_NEC_MP900) -#else -# define machine_is_nec_mp900() (0) -#endif - -#ifdef CONFIG_MACH_VVTK1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VVTK1000 -# endif -# define machine_is_vvtk1000() (machine_arch_type == MACH_TYPE_VVTK1000) -#else -# define machine_is_vvtk1000() (0) -#endif - -#ifdef CONFIG_MACH_KAFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KAFA -# endif -# define machine_is_kafa() (machine_arch_type == MACH_TYPE_KAFA) -#else -# define machine_is_kafa() (0) -#endif - -#ifdef CONFIG_MACH_VVTK3000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VVTK3000 -# endif -# define machine_is_vvtk3000() (machine_arch_type == MACH_TYPE_VVTK3000) -#else -# define machine_is_vvtk3000() (0) -#endif - -#ifdef CONFIG_MACH_PIMX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PIMX1 -# endif -# define machine_is_pimx1() (machine_arch_type == MACH_TYPE_PIMX1) -#else -# define machine_is_pimx1() (0) -#endif - -#ifdef CONFIG_MACH_OLLIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OLLIE -# endif -# define machine_is_ollie() (machine_arch_type == MACH_TYPE_OLLIE) -#else -# define machine_is_ollie() (0) -#endif - -#ifdef CONFIG_MACH_SKYMAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKYMAX -# endif -# define machine_is_skymax() (machine_arch_type == MACH_TYPE_SKYMAX) -#else -# define machine_is_skymax() (0) -#endif - -#ifdef CONFIG_MACH_JAZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JAZZ -# endif -# define machine_is_jazz() (machine_arch_type == MACH_TYPE_JAZZ) -#else -# define machine_is_jazz() (0) -#endif - -#ifdef CONFIG_MACH_TEL_T3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEL_T3 -# endif -# define machine_is_tel_t3() (machine_arch_type == MACH_TYPE_TEL_T3) -#else -# define machine_is_tel_t3() (0) -#endif - -#ifdef CONFIG_MACH_AISINO_FCR255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AISINO_FCR255 -# endif -# define machine_is_aisino_fcr255() (machine_arch_type == MACH_TYPE_AISINO_FCR255) -#else -# define machine_is_aisino_fcr255() (0) -#endif - -#ifdef CONFIG_MACH_BTWEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTWEB -# endif -# define machine_is_btweb() (machine_arch_type == MACH_TYPE_BTWEB) -#else -# define machine_is_btweb() (0) -#endif - -#ifdef CONFIG_MACH_DBG_LH79520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DBG_LH79520 -# endif -# define machine_is_dbg_lh79520() (machine_arch_type == MACH_TYPE_DBG_LH79520) -#else -# define machine_is_dbg_lh79520() (0) -#endif - -#ifdef CONFIG_MACH_CM41XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM41XX -# endif -# define machine_is_cm41xx() (machine_arch_type == MACH_TYPE_CM41XX) -#else -# define machine_is_cm41xx() (0) -#endif - -#ifdef CONFIG_MACH_TS72XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS72XX -# endif -# define machine_is_ts72xx() (machine_arch_type == MACH_TYPE_TS72XX) -#else -# define machine_is_ts72xx() (0) -#endif - -#ifdef CONFIG_MACH_NGGPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NGGPXA -# endif -# define machine_is_nggpxa() (machine_arch_type == MACH_TYPE_NGGPXA) -#else -# define machine_is_nggpxa() (0) -#endif - -#ifdef CONFIG_MACH_CSB535 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB535 -# endif -# define machine_is_csb535() (machine_arch_type == MACH_TYPE_CSB535) -#else -# define machine_is_csb535() (0) -#endif - -#ifdef CONFIG_MACH_CSB536 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB536 -# endif -# define machine_is_csb536() (machine_arch_type == MACH_TYPE_CSB536) -#else -# define machine_is_csb536() (0) -#endif - -#ifdef CONFIG_MACH_PXA_TRAKPOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_TRAKPOD -# endif -# define machine_is_pxa_trakpod() (machine_arch_type == MACH_TYPE_PXA_TRAKPOD) -#else -# define machine_is_pxa_trakpod() (0) -#endif - -#ifdef CONFIG_MACH_PRAXIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRAXIS -# endif -# define machine_is_praxis() (machine_arch_type == MACH_TYPE_PRAXIS) -#else -# define machine_is_praxis() (0) -#endif - -#ifdef CONFIG_MACH_LH75411 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LH75411 -# endif -# define machine_is_lh75411() (machine_arch_type == MACH_TYPE_LH75411) -#else -# define machine_is_lh75411() (0) -#endif - -#ifdef CONFIG_MACH_OTOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTOM -# endif -# define machine_is_otom() (machine_arch_type == MACH_TYPE_OTOM) -#else -# define machine_is_otom() (0) -#endif - -#ifdef CONFIG_MACH_NEXCODER_2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXCODER_2440 -# endif -# define machine_is_nexcoder_2440() (machine_arch_type == MACH_TYPE_NEXCODER_2440) -#else -# define machine_is_nexcoder_2440() (0) -#endif - -#ifdef CONFIG_MACH_LOOX410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOX410 -# endif -# define machine_is_loox410() (machine_arch_type == MACH_TYPE_LOOX410) -#else -# define machine_is_loox410() (0) -#endif - -#ifdef CONFIG_MACH_WESTLAKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WESTLAKE -# endif -# define machine_is_westlake() (machine_arch_type == MACH_TYPE_WESTLAKE) -#else -# define machine_is_westlake() (0) -#endif - -#ifdef CONFIG_MACH_NSB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB -# endif -# define machine_is_nsb() (machine_arch_type == MACH_TYPE_NSB) -#else -# define machine_is_nsb() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_STN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_STN -# endif -# define machine_is_esl_sarva_stn() (machine_arch_type == MACH_TYPE_ESL_SARVA_STN) -#else -# define machine_is_esl_sarva_stn() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_TFT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_TFT -# endif -# define machine_is_esl_sarva_tft() (machine_arch_type == MACH_TYPE_ESL_SARVA_TFT) -#else -# define machine_is_esl_sarva_tft() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_IAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_IAD -# endif -# define machine_is_esl_sarva_iad() (machine_arch_type == MACH_TYPE_ESL_SARVA_IAD) -#else -# define machine_is_esl_sarva_iad() (0) -#endif - -#ifdef CONFIG_MACH_ESL_SARVA_ACC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_SARVA_ACC -# endif -# define machine_is_esl_sarva_acc() (machine_arch_type == MACH_TYPE_ESL_SARVA_ACC) -#else -# define machine_is_esl_sarva_acc() (0) -#endif - -#ifdef CONFIG_MACH_TYPHOON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TYPHOON -# endif -# define machine_is_typhoon() (machine_arch_type == MACH_TYPE_TYPHOON) -#else -# define machine_is_typhoon() (0) -#endif - -#ifdef CONFIG_MACH_CNAV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CNAV -# endif -# define machine_is_cnav() (machine_arch_type == MACH_TYPE_CNAV) -#else -# define machine_is_cnav() (0) -#endif - -#ifdef CONFIG_MACH_A730 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A730 -# endif -# define machine_is_a730() (machine_arch_type == MACH_TYPE_A730) -#else -# define machine_is_a730() (0) -#endif - -#ifdef CONFIG_MACH_NETSTAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETSTAR -# endif -# define machine_is_netstar() (machine_arch_type == MACH_TYPE_NETSTAR) -#else -# define machine_is_netstar() (0) -#endif - -#ifdef CONFIG_MACH_PHASEFALE_SUPERCON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHASEFALE_SUPERCON -# endif -# define machine_is_supercon() (machine_arch_type == MACH_TYPE_PHASEFALE_SUPERCON) -#else -# define machine_is_supercon() (0) -#endif - -#ifdef CONFIG_MACH_SHIVA1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHIVA1100 -# endif -# define machine_is_shiva1100() (machine_arch_type == MACH_TYPE_SHIVA1100) -#else -# define machine_is_shiva1100() (0) -#endif - -#ifdef CONFIG_MACH_ETEXSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETEXSC -# endif -# define machine_is_etexsc() (machine_arch_type == MACH_TYPE_ETEXSC) -#else -# define machine_is_etexsc() (0) -#endif - -#ifdef CONFIG_MACH_IXDPG465 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDPG465 -# endif -# define machine_is_ixdpg465() (machine_arch_type == MACH_TYPE_IXDPG465) -#else -# define machine_is_ixdpg465() (0) -#endif - -#ifdef CONFIG_MACH_A9M2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M2410 -# endif -# define machine_is_a9m2410() (machine_arch_type == MACH_TYPE_A9M2410) -#else -# define machine_is_a9m2410() (0) -#endif - -#ifdef CONFIG_MACH_A9M2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M2440 -# endif -# define machine_is_a9m2440() (machine_arch_type == MACH_TYPE_A9M2440) -#else -# define machine_is_a9m2440() (0) -#endif - -#ifdef CONFIG_MACH_A9M9750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M9750 -# endif -# define machine_is_a9m9750() (machine_arch_type == MACH_TYPE_A9M9750) -#else -# define machine_is_a9m9750() (0) -#endif - -#ifdef CONFIG_MACH_A9M9360 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9M9360 -# endif -# define machine_is_a9m9360() (machine_arch_type == MACH_TYPE_A9M9360) -#else -# define machine_is_a9m9360() (0) -#endif - -#ifdef CONFIG_MACH_UNC90 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNC90 -# endif -# define machine_is_unc90() (machine_arch_type == MACH_TYPE_UNC90) -#else -# define machine_is_unc90() (0) -#endif - -#ifdef CONFIG_MACH_ECO920 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECO920 -# endif -# define machine_is_eco920() (machine_arch_type == MACH_TYPE_ECO920) -#else -# define machine_is_eco920() (0) -#endif - -#ifdef CONFIG_MACH_SATVIEW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SATVIEW -# endif -# define machine_is_satview() (machine_arch_type == MACH_TYPE_SATVIEW) -#else -# define machine_is_satview() (0) -#endif - -#ifdef CONFIG_MACH_ROADRUNNER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROADRUNNER -# endif -# define machine_is_roadrunner() (machine_arch_type == MACH_TYPE_ROADRUNNER) -#else -# define machine_is_roadrunner() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200EK -# endif -# define machine_is_at91rm9200ek() (machine_arch_type == MACH_TYPE_AT91RM9200EK) -#else -# define machine_is_at91rm9200ek() (0) -#endif - -#ifdef CONFIG_MACH_GP32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GP32 -# endif -# define machine_is_gp32() (machine_arch_type == MACH_TYPE_GP32) -#else -# define machine_is_gp32() (0) -#endif - -#ifdef CONFIG_MACH_GEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEM -# endif -# define machine_is_gem() (machine_arch_type == MACH_TYPE_GEM) -#else -# define machine_is_gem() (0) -#endif - -#ifdef CONFIG_MACH_I858 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I858 -# endif -# define machine_is_i858() (machine_arch_type == MACH_TYPE_I858) -#else -# define machine_is_i858() (0) -#endif - -#ifdef CONFIG_MACH_HX2750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HX2750 -# endif -# define machine_is_hx2750() (machine_arch_type == MACH_TYPE_HX2750) -#else -# define machine_is_hx2750() (0) -#endif - -#ifdef CONFIG_MACH_MXC91131EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC91131EVB -# endif -# define machine_is_mxc91131evb() (machine_arch_type == MACH_TYPE_MXC91131EVB) -#else -# define machine_is_mxc91131evb() (0) -#endif - -#ifdef CONFIG_MACH_P700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P700 -# endif -# define machine_is_p700() (machine_arch_type == MACH_TYPE_P700) -#else -# define machine_is_p700() (0) -#endif - -#ifdef CONFIG_MACH_CPE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPE -# endif -# define machine_is_cpe() (machine_arch_type == MACH_TYPE_CPE) -#else -# define machine_is_cpe() (0) -#endif - -#ifdef CONFIG_MACH_SPITZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPITZ -# endif -# define machine_is_spitz() (machine_arch_type == MACH_TYPE_SPITZ) -#else -# define machine_is_spitz() (0) -#endif - -#ifdef CONFIG_MACH_NIMBRA340 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMBRA340 -# endif -# define machine_is_nimbra340() (machine_arch_type == MACH_TYPE_NIMBRA340) -#else -# define machine_is_nimbra340() (0) -#endif - -#ifdef CONFIG_MACH_LPC22XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC22XX -# endif -# define machine_is_lpc22xx() (machine_arch_type == MACH_TYPE_LPC22XX) -#else -# define machine_is_lpc22xx() (0) -#endif - -#ifdef CONFIG_MACH_COMET3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMET3 -# endif -# define machine_is_omap_comet3() (machine_arch_type == MACH_TYPE_COMET3) -#else -# define machine_is_omap_comet3() (0) -#endif - -#ifdef CONFIG_MACH_COMET4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMET4 -# endif -# define machine_is_omap_comet4() (machine_arch_type == MACH_TYPE_COMET4) -#else -# define machine_is_omap_comet4() (0) -#endif - -#ifdef CONFIG_MACH_CSB625 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB625 -# endif -# define machine_is_csb625() (machine_arch_type == MACH_TYPE_CSB625) -#else -# define machine_is_csb625() (0) -#endif - -#ifdef CONFIG_MACH_FORTUNET2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTUNET2 -# endif -# define machine_is_fortunet2() (machine_arch_type == MACH_TYPE_FORTUNET2) -#else -# define machine_is_fortunet2() (0) -#endif - -#ifdef CONFIG_MACH_S5H2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5H2200 -# endif -# define machine_is_s5h2200() (machine_arch_type == MACH_TYPE_S5H2200) -#else -# define machine_is_s5h2200() (0) -#endif - -#ifdef CONFIG_MACH_OPTORM920 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPTORM920 -# endif -# define machine_is_optorm920() (machine_arch_type == MACH_TYPE_OPTORM920) -#else -# define machine_is_optorm920() (0) -#endif - -#ifdef CONFIG_MACH_ADSBITSYXB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYXB -# endif -# define machine_is_adsbitsyxb() (machine_arch_type == MACH_TYPE_ADSBITSYXB) -#else -# define machine_is_adsbitsyxb() (0) -#endif - -#ifdef CONFIG_MACH_ADSSPHERE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSSPHERE -# endif -# define machine_is_adssphere() (machine_arch_type == MACH_TYPE_ADSSPHERE) -#else -# define machine_is_adssphere() (0) -#endif - -#ifdef CONFIG_MACH_ADSPORTAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSPORTAL -# endif -# define machine_is_adsportal() (machine_arch_type == MACH_TYPE_ADSPORTAL) -#else -# define machine_is_adsportal() (0) -#endif - -#ifdef CONFIG_MACH_LN2410SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LN2410SBC -# endif -# define machine_is_ln2410sbc() (machine_arch_type == MACH_TYPE_LN2410SBC) -#else -# define machine_is_ln2410sbc() (0) -#endif - -#ifdef CONFIG_MACH_CB3RUFC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CB3RUFC -# endif -# define machine_is_cb3rufc() (machine_arch_type == MACH_TYPE_CB3RUFC) -#else -# define machine_is_cb3rufc() (0) -#endif - -#ifdef CONFIG_MACH_MP2USB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP2USB -# endif -# define machine_is_mp2usb() (machine_arch_type == MACH_TYPE_MP2USB) -#else -# define machine_is_mp2usb() (0) -#endif - -#ifdef CONFIG_MACH_NTNP425C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NTNP425C -# endif -# define machine_is_ntnp425c() (machine_arch_type == MACH_TYPE_NTNP425C) -#else -# define machine_is_ntnp425c() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI -# endif -# define machine_is_colibri() (machine_arch_type == MACH_TYPE_COLIBRI) -#else -# define machine_is_colibri() (0) -#endif - -#ifdef CONFIG_MACH_PCM7220 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM7220 -# endif -# define machine_is_pcm7220() (machine_arch_type == MACH_TYPE_PCM7220) -#else -# define machine_is_pcm7220() (0) -#endif - -#ifdef CONFIG_MACH_GATEWAY7001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GATEWAY7001 -# endif -# define machine_is_gateway7001() (machine_arch_type == MACH_TYPE_GATEWAY7001) -#else -# define machine_is_gateway7001() (0) -#endif - -#ifdef CONFIG_MACH_PCM027 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM027 -# endif -# define machine_is_pcm027() (machine_arch_type == MACH_TYPE_PCM027) -#else -# define machine_is_pcm027() (0) -#endif - -#ifdef CONFIG_MACH_CMPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMPXA -# endif -# define machine_is_cmpxa() (machine_arch_type == MACH_TYPE_CMPXA) -#else -# define machine_is_cmpxa() (0) -#endif - -#ifdef CONFIG_MACH_ANUBIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANUBIS -# endif -# define machine_is_anubis() (machine_arch_type == MACH_TYPE_ANUBIS) -#else -# define machine_is_anubis() (0) -#endif - -#ifdef CONFIG_MACH_ITE8152 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ITE8152 -# endif -# define machine_is_ite8152() (machine_arch_type == MACH_TYPE_ITE8152) -#else -# define machine_is_ite8152() (0) -#endif - -#ifdef CONFIG_MACH_LPC3XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC3XXX -# endif -# define machine_is_lpc3xxx() (machine_arch_type == MACH_TYPE_LPC3XXX) -#else -# define machine_is_lpc3xxx() (0) -#endif - -#ifdef CONFIG_MACH_PUPPETEER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUPPETEER -# endif -# define machine_is_puppeteer() (machine_arch_type == MACH_TYPE_PUPPETEER) -#else -# define machine_is_puppeteer() (0) -#endif - -#ifdef CONFIG_MACH_E570 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E570 -# endif -# define machine_is_e570() (machine_arch_type == MACH_TYPE_E570) -#else -# define machine_is_e570() (0) -#endif - -#ifdef CONFIG_MACH_X50 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_X50 -# endif -# define machine_is_x50() (machine_arch_type == MACH_TYPE_X50) -#else -# define machine_is_x50() (0) -#endif - -#ifdef CONFIG_MACH_RECON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RECON -# endif -# define machine_is_recon() (machine_arch_type == MACH_TYPE_RECON) -#else -# define machine_is_recon() (0) -#endif - -#ifdef CONFIG_MACH_XBOARDGP8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XBOARDGP8 -# endif -# define machine_is_xboardgp8() (machine_arch_type == MACH_TYPE_XBOARDGP8) -#else -# define machine_is_xboardgp8() (0) -#endif - -#ifdef CONFIG_MACH_FPIC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FPIC2 -# endif -# define machine_is_fpic2() (machine_arch_type == MACH_TYPE_FPIC2) -#else -# define machine_is_fpic2() (0) -#endif - -#ifdef CONFIG_MACH_AKITA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKITA -# endif -# define machine_is_akita() (machine_arch_type == MACH_TYPE_AKITA) -#else -# define machine_is_akita() (0) -#endif - -#ifdef CONFIG_MACH_A81 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A81 -# endif -# define machine_is_a81() (machine_arch_type == MACH_TYPE_A81) -#else -# define machine_is_a81() (0) -#endif - -#ifdef CONFIG_MACH_SVM_SC25X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVM_SC25X -# endif -# define machine_is_svm_sc25x() (machine_arch_type == MACH_TYPE_SVM_SC25X) -#else -# define machine_is_svm_sc25x() (0) -#endif - -#ifdef CONFIG_MACH_VADATECH020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VADATECH020 -# endif -# define machine_is_vt020() (machine_arch_type == MACH_TYPE_VADATECH020) -#else -# define machine_is_vt020() (0) -#endif - -#ifdef CONFIG_MACH_TLI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TLI -# endif -# define machine_is_tli() (machine_arch_type == MACH_TYPE_TLI) -#else -# define machine_is_tli() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315LC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315LC -# endif -# define machine_is_edb9315lc() (machine_arch_type == MACH_TYPE_EDB9315LC) -#else -# define machine_is_edb9315lc() (0) -#endif - -#ifdef CONFIG_MACH_PASSEC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PASSEC -# endif -# define machine_is_passec() (machine_arch_type == MACH_TYPE_PASSEC) -#else -# define machine_is_passec() (0) -#endif - -#ifdef CONFIG_MACH_DS_TIGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS_TIGER -# endif -# define machine_is_ds_tiger() (machine_arch_type == MACH_TYPE_DS_TIGER) -#else -# define machine_is_ds_tiger() (0) -#endif - -#ifdef CONFIG_MACH_E310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E310 -# endif -# define machine_is_e310() (machine_arch_type == MACH_TYPE_E310) -#else -# define machine_is_e310() (0) -#endif - -#ifdef CONFIG_MACH_E330 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E330 -# endif -# define machine_is_e330() (machine_arch_type == MACH_TYPE_E330) -#else -# define machine_is_e330() (0) -#endif - -#ifdef CONFIG_MACH_RT3000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RT3000 -# endif -# define machine_is_rt3000() (machine_arch_type == MACH_TYPE_RT3000) -#else -# define machine_is_rt3000() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA770 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA770 -# endif -# define machine_is_nokia770() (machine_arch_type == MACH_TYPE_NOKIA770) -#else -# define machine_is_nokia770() (0) -#endif - -#ifdef CONFIG_MACH_PNX0106 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX0106 -# endif -# define machine_is_pnx0106() (machine_arch_type == MACH_TYPE_PNX0106) -#else -# define machine_is_pnx0106() (0) -#endif - -#ifdef CONFIG_MACH_HX21XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HX21XX -# endif -# define machine_is_hx21xx() (machine_arch_type == MACH_TYPE_HX21XX) -#else -# define machine_is_hx21xx() (0) -#endif - -#ifdef CONFIG_MACH_FARADAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FARADAY -# endif -# define machine_is_faraday() (machine_arch_type == MACH_TYPE_FARADAY) -#else -# define machine_is_faraday() (0) -#endif - -#ifdef CONFIG_MACH_SBC9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC9312 -# endif -# define machine_is_sbc9312() (machine_arch_type == MACH_TYPE_SBC9312) -#else -# define machine_is_sbc9312() (0) -#endif - -#ifdef CONFIG_MACH_BATMAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BATMAN -# endif -# define machine_is_batman() (machine_arch_type == MACH_TYPE_BATMAN) -#else -# define machine_is_batman() (0) -#endif - -#ifdef CONFIG_MACH_JPD201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JPD201 -# endif -# define machine_is_jpd201() (machine_arch_type == MACH_TYPE_JPD201) -#else -# define machine_is_jpd201() (0) -#endif - -#ifdef CONFIG_MACH_MIPSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIPSA -# endif -# define machine_is_mipsa() (machine_arch_type == MACH_TYPE_MIPSA) -#else -# define machine_is_mipsa() (0) -#endif - -#ifdef CONFIG_MACH_KACOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KACOM -# endif -# define machine_is_kacom() (machine_arch_type == MACH_TYPE_KACOM) -#else -# define machine_is_kacom() (0) -#endif - -#ifdef CONFIG_MACH_SWARCOCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCOCPU -# endif -# define machine_is_swarcocpu() (machine_arch_type == MACH_TYPE_SWARCOCPU) -#else -# define machine_is_swarcocpu() (0) -#endif - -#ifdef CONFIG_MACH_SWARCODSL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCODSL -# endif -# define machine_is_swarcodsl() (machine_arch_type == MACH_TYPE_SWARCODSL) -#else -# define machine_is_swarcodsl() (0) -#endif - -#ifdef CONFIG_MACH_BLUEANGEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUEANGEL -# endif -# define machine_is_blueangel() (machine_arch_type == MACH_TYPE_BLUEANGEL) -#else -# define machine_is_blueangel() (0) -#endif - -#ifdef CONFIG_MACH_HAIRYGRAMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HAIRYGRAMA -# endif -# define machine_is_hairygrama() (machine_arch_type == MACH_TYPE_HAIRYGRAMA) -#else -# define machine_is_hairygrama() (0) -#endif - -#ifdef CONFIG_MACH_BANFF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BANFF -# endif -# define machine_is_banff() (machine_arch_type == MACH_TYPE_BANFF) -#else -# define machine_is_banff() (0) -#endif - -#ifdef CONFIG_MACH_CARMEVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARMEVA -# endif -# define machine_is_carmeva() (machine_arch_type == MACH_TYPE_CARMEVA) -#else -# define machine_is_carmeva() (0) -#endif - -#ifdef CONFIG_MACH_SAM255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM255 -# endif -# define machine_is_sam255() (machine_arch_type == MACH_TYPE_SAM255) -#else -# define machine_is_sam255() (0) -#endif - -#ifdef CONFIG_MACH_PPM10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PPM10 -# endif -# define machine_is_ppm10() (machine_arch_type == MACH_TYPE_PPM10) -#else -# define machine_is_ppm10() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315A -# endif -# define machine_is_edb9315a() (machine_arch_type == MACH_TYPE_EDB9315A) -#else -# define machine_is_edb9315a() (0) -#endif - -#ifdef CONFIG_MACH_SUNSET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUNSET -# endif -# define machine_is_sunset() (machine_arch_type == MACH_TYPE_SUNSET) -#else -# define machine_is_sunset() (0) -#endif - -#ifdef CONFIG_MACH_STARGATE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGATE2 -# endif -# define machine_is_stargate2() (machine_arch_type == MACH_TYPE_STARGATE2) -#else -# define machine_is_stargate2() (0) -#endif - -#ifdef CONFIG_MACH_INTELMOTE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTELMOTE2 -# endif -# define machine_is_intelmote2() (machine_arch_type == MACH_TYPE_INTELMOTE2) -#else -# define machine_is_intelmote2() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS4 -# endif -# define machine_is_trizeps4() (machine_arch_type == MACH_TYPE_TRIZEPS4) -#else -# define machine_is_trizeps4() (0) -#endif - -#ifdef CONFIG_MACH_MAINSTONE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAINSTONE2 -# endif -# define machine_is_mainstone2() (machine_arch_type == MACH_TYPE_MAINSTONE2) -#else -# define machine_is_mainstone2() (0) -#endif - -#ifdef CONFIG_MACH_EZ_IXP42X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_IXP42X -# endif -# define machine_is_ez_ixp42x() (machine_arch_type == MACH_TYPE_EZ_IXP42X) -#else -# define machine_is_ez_ixp42x() (0) -#endif - -#ifdef CONFIG_MACH_TAPWAVE_ZODIAC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAPWAVE_ZODIAC -# endif -# define machine_is_tapwave_zodiac() (machine_arch_type == MACH_TYPE_TAPWAVE_ZODIAC) -#else -# define machine_is_tapwave_zodiac() (0) -#endif - -#ifdef CONFIG_MACH_UNIVERSALMETER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIVERSALMETER -# endif -# define machine_is_universalmeter() (machine_arch_type == MACH_TYPE_UNIVERSALMETER) -#else -# define machine_is_universalmeter() (0) -#endif - -#ifdef CONFIG_MACH_HICOARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HICOARM9 -# endif -# define machine_is_hicoarm9() (machine_arch_type == MACH_TYPE_HICOARM9) -#else -# define machine_is_hicoarm9() (0) -#endif - -#ifdef CONFIG_MACH_PNX4008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX4008 -# endif -# define machine_is_pnx4008() (machine_arch_type == MACH_TYPE_PNX4008) -#else -# define machine_is_pnx4008() (0) -#endif - -#ifdef CONFIG_MACH_KWS6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KWS6000 -# endif -# define machine_is_kws6000() (machine_arch_type == MACH_TYPE_KWS6000) -#else -# define machine_is_kws6000() (0) -#endif - -#ifdef CONFIG_MACH_PORTUX920T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PORTUX920T -# endif -# define machine_is_portux920t() (machine_arch_type == MACH_TYPE_PORTUX920T) -#else -# define machine_is_portux920t() (0) -#endif - -#ifdef CONFIG_MACH_EZ_X5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_X5 -# endif -# define machine_is_ez_x5() (machine_arch_type == MACH_TYPE_EZ_X5) -#else -# define machine_is_ez_x5() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_RUDOLPH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_RUDOLPH -# endif -# define machine_is_omap_rudolph() (machine_arch_type == MACH_TYPE_OMAP_RUDOLPH) -#else -# define machine_is_omap_rudolph() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT91 -# endif -# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91) -#else -# define machine_is_cpuat91() (0) -#endif - -#ifdef CONFIG_MACH_REA9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REA9200 -# endif -# define machine_is_rea9200() (machine_arch_type == MACH_TYPE_REA9200) -#else -# define machine_is_rea9200() (0) -#endif - -#ifdef CONFIG_MACH_ACTS_PUNE_SA1110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTS_PUNE_SA1110 -# endif -# define machine_is_acts_pune_sa1110() (machine_arch_type == MACH_TYPE_ACTS_PUNE_SA1110) -#else -# define machine_is_acts_pune_sa1110() (0) -#endif - -#ifdef CONFIG_MACH_IXP425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP425 -# endif -# define machine_is_ixp425() (machine_arch_type == MACH_TYPE_IXP425) -#else -# define machine_is_ixp425() (0) -#endif - -#ifdef CONFIG_MACH_I30030ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I30030ADS -# endif -# define machine_is_i30030ads() (machine_arch_type == MACH_TYPE_I30030ADS) -#else -# define machine_is_i30030ads() (0) -#endif - -#ifdef CONFIG_MACH_PERCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERCH -# endif -# define machine_is_perch() (machine_arch_type == MACH_TYPE_PERCH) -#else -# define machine_is_perch() (0) -#endif - -#ifdef CONFIG_MACH_EIS05R1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EIS05R1 -# endif -# define machine_is_eis05r1() (machine_arch_type == MACH_TYPE_EIS05R1) -#else -# define machine_is_eis05r1() (0) -#endif - -#ifdef CONFIG_MACH_PEPPERPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PEPPERPAD -# endif -# define machine_is_pepperpad() (machine_arch_type == MACH_TYPE_PEPPERPAD) -#else -# define machine_is_pepperpad() (0) -#endif - -#ifdef CONFIG_MACH_SB3010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SB3010 -# endif -# define machine_is_sb3010() (machine_arch_type == MACH_TYPE_SB3010) -#else -# define machine_is_sb3010() (0) -#endif - -#ifdef CONFIG_MACH_RM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RM9200 -# endif -# define machine_is_rm9200() (machine_arch_type == MACH_TYPE_RM9200) -#else -# define machine_is_rm9200() (0) -#endif - -#ifdef CONFIG_MACH_DMA03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DMA03 -# endif -# define machine_is_dma03() (machine_arch_type == MACH_TYPE_DMA03) -#else -# define machine_is_dma03() (0) -#endif - -#ifdef CONFIG_MACH_ROAD_S101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROAD_S101 -# endif -# define machine_is_road_s101() (machine_arch_type == MACH_TYPE_ROAD_S101) -#else -# define machine_is_road_s101() (0) -#endif - -#ifdef CONFIG_MACH_IQ81340SC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ81340SC -# endif -# define machine_is_iq81340sc() (machine_arch_type == MACH_TYPE_IQ81340SC) -#else -# define machine_is_iq81340sc() (0) -#endif - -#ifdef CONFIG_MACH_IQ_NEXTGEN_B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_B -# endif -# define machine_is_iq_nextgen_b() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_B) -#else -# define machine_is_iq_nextgen_b() (0) -#endif - -#ifdef CONFIG_MACH_IQ81340MC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ81340MC -# endif -# define machine_is_iq81340mc() (machine_arch_type == MACH_TYPE_IQ81340MC) -#else -# define machine_is_iq81340mc() (0) -#endif - -#ifdef CONFIG_MACH_IQ_NEXTGEN_D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_D -# endif -# define machine_is_iq_nextgen_d() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_D) -#else -# define machine_is_iq_nextgen_d() (0) -#endif - -#ifdef CONFIG_MACH_IQ_NEXTGEN_E -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_E -# endif -# define machine_is_iq_nextgen_e() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_E) -#else -# define machine_is_iq_nextgen_e() (0) -#endif - -#ifdef CONFIG_MACH_MALLOW_AT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MALLOW_AT91 -# endif -# define machine_is_mallow_at91() (machine_arch_type == MACH_TYPE_MALLOW_AT91) -#else -# define machine_is_mallow_at91() (0) -#endif - -#ifdef CONFIG_MACH_CYBERTRACKER_I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBERTRACKER_I -# endif -# define machine_is_cybertracker_i() (machine_arch_type == MACH_TYPE_CYBERTRACKER_I) -#else -# define machine_is_cybertracker_i() (0) -#endif - -#ifdef CONFIG_MACH_GESBC931X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GESBC931X -# endif -# define machine_is_gesbc931x() (machine_arch_type == MACH_TYPE_GESBC931X) -#else -# define machine_is_gesbc931x() (0) -#endif - -#ifdef CONFIG_MACH_CENTIPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CENTIPAD -# endif -# define machine_is_centipad() (machine_arch_type == MACH_TYPE_CENTIPAD) -#else -# define machine_is_centipad() (0) -#endif - -#ifdef CONFIG_MACH_ARMSOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMSOC -# endif -# define machine_is_armsoc() (machine_arch_type == MACH_TYPE_ARMSOC) -#else -# define machine_is_armsoc() (0) -#endif - -#ifdef CONFIG_MACH_SE4200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE4200 -# endif -# define machine_is_se4200() (machine_arch_type == MACH_TYPE_SE4200) -#else -# define machine_is_se4200() (0) -#endif - -#ifdef CONFIG_MACH_EMS197A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMS197A -# endif -# define machine_is_ems197a() (machine_arch_type == MACH_TYPE_EMS197A) -#else -# define machine_is_ems197a() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9 -# endif -# define machine_is_micro9() (machine_arch_type == MACH_TYPE_MICRO9) -#else -# define machine_is_micro9() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9L -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9L -# endif -# define machine_is_micro9l() (machine_arch_type == MACH_TYPE_MICRO9L) -#else -# define machine_is_micro9l() (0) -#endif - -#ifdef CONFIG_MACH_UC5471DSP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UC5471DSP -# endif -# define machine_is_uc5471dsp() (machine_arch_type == MACH_TYPE_UC5471DSP) -#else -# define machine_is_uc5471dsp() (0) -#endif - -#ifdef CONFIG_MACH_SJ5471ENG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SJ5471ENG -# endif -# define machine_is_sj5471eng() (machine_arch_type == MACH_TYPE_SJ5471ENG) -#else -# define machine_is_sj5471eng() (0) -#endif - -#ifdef CONFIG_MACH_CMPXA26X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMPXA26X -# endif -# define machine_is_none() (machine_arch_type == MACH_TYPE_CMPXA26X) -#else -# define machine_is_none() (0) -#endif - -#ifdef CONFIG_MACH_NC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NC -# endif -# define machine_is_nc1() (machine_arch_type == MACH_TYPE_NC) -#else -# define machine_is_nc1() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTE -# endif -# define machine_is_omap_palmte() (machine_arch_type == MACH_TYPE_OMAP_PALMTE) -#else -# define machine_is_omap_palmte() (0) -#endif - -#ifdef CONFIG_MACH_AJAX52X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AJAX52X -# endif -# define machine_is_ajax52x() (machine_arch_type == MACH_TYPE_AJAX52X) -#else -# define machine_is_ajax52x() (0) -#endif - -#ifdef CONFIG_MACH_SIRIUSTAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIRIUSTAR -# endif -# define machine_is_siriustar() (machine_arch_type == MACH_TYPE_SIRIUSTAR) -#else -# define machine_is_siriustar() (0) -#endif - -#ifdef CONFIG_MACH_IODATA_HDLG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IODATA_HDLG -# endif -# define machine_is_iodata_hdlg() (machine_arch_type == MACH_TYPE_IODATA_HDLG) -#else -# define machine_is_iodata_hdlg() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200UTL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200UTL -# endif -# define machine_is_at91rm9200utl() (machine_arch_type == MACH_TYPE_AT91RM9200UTL) -#else -# define machine_is_at91rm9200utl() (0) -#endif - -#ifdef CONFIG_MACH_BIOSAFE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIOSAFE -# endif -# define machine_is_biosafe() (machine_arch_type == MACH_TYPE_BIOSAFE) -#else -# define machine_is_biosafe() (0) -#endif - -#ifdef CONFIG_MACH_MP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP1000 -# endif -# define machine_is_mp1000() (machine_arch_type == MACH_TYPE_MP1000) -#else -# define machine_is_mp1000() (0) -#endif - -#ifdef CONFIG_MACH_PARSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PARSY -# endif -# define machine_is_parsy() (machine_arch_type == MACH_TYPE_PARSY) -#else -# define machine_is_parsy() (0) -#endif - -#ifdef CONFIG_MACH_CCXP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCXP -# endif -# define machine_is_ccxp270() (machine_arch_type == MACH_TYPE_CCXP) -#else -# define machine_is_ccxp270() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_GSAMPLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_GSAMPLE -# endif -# define machine_is_omap_gsample() (machine_arch_type == MACH_TYPE_OMAP_GSAMPLE) -#else -# define machine_is_omap_gsample() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_EB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_EB -# endif -# define machine_is_realview_eb() (machine_arch_type == MACH_TYPE_REALVIEW_EB) -#else -# define machine_is_realview_eb() (0) -#endif - -#ifdef CONFIG_MACH_SAMOA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAMOA -# endif -# define machine_is_samoa() (machine_arch_type == MACH_TYPE_SAMOA) -#else -# define machine_is_samoa() (0) -#endif - -#ifdef CONFIG_MACH_PALMT3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMT3 -# endif -# define machine_is_palmt3() (machine_arch_type == MACH_TYPE_PALMT3) -#else -# define machine_is_palmt3() (0) -#endif - -#ifdef CONFIG_MACH_I878 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I878 -# endif -# define machine_is_i878() (machine_arch_type == MACH_TYPE_I878) -#else -# define machine_is_i878() (0) -#endif - -#ifdef CONFIG_MACH_BORZOI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BORZOI -# endif -# define machine_is_borzoi() (machine_arch_type == MACH_TYPE_BORZOI) -#else -# define machine_is_borzoi() (0) -#endif - -#ifdef CONFIG_MACH_GECKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GECKO -# endif -# define machine_is_gecko() (machine_arch_type == MACH_TYPE_GECKO) -#else -# define machine_is_gecko() (0) -#endif - -#ifdef CONFIG_MACH_DS101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS101 -# endif -# define machine_is_ds101() (machine_arch_type == MACH_TYPE_DS101) -#else -# define machine_is_ds101() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTT2 -# endif -# define machine_is_omap_palmtt2() (machine_arch_type == MACH_TYPE_OMAP_PALMTT2) -#else -# define machine_is_omap_palmtt2() (0) -#endif - -#ifdef CONFIG_MACH_PALMLD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMLD -# endif -# define machine_is_palmld() (machine_arch_type == MACH_TYPE_PALMLD) -#else -# define machine_is_palmld() (0) -#endif - -#ifdef CONFIG_MACH_CC9C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9C -# endif -# define machine_is_cc9c() (machine_arch_type == MACH_TYPE_CC9C) -#else -# define machine_is_cc9c() (0) -#endif - -#ifdef CONFIG_MACH_SBC1670 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC1670 -# endif -# define machine_is_sbc1670() (machine_arch_type == MACH_TYPE_SBC1670) -#else -# define machine_is_sbc1670() (0) -#endif - -#ifdef CONFIG_MACH_IXDP28X5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP28X5 -# endif -# define machine_is_ixdp28x5() (machine_arch_type == MACH_TYPE_IXDP28X5) -#else -# define machine_is_ixdp28x5() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTT -# endif -# define machine_is_omap_palmtt() (machine_arch_type == MACH_TYPE_OMAP_PALMTT) -#else -# define machine_is_omap_palmtt() (0) -#endif - -#ifdef CONFIG_MACH_ML696K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML696K -# endif -# define machine_is_ml696k() (machine_arch_type == MACH_TYPE_ML696K) -#else -# define machine_is_ml696k() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_ZEUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_ZEUS -# endif -# define machine_is_arcom_zeus() (machine_arch_type == MACH_TYPE_ARCOM_ZEUS) -#else -# define machine_is_arcom_zeus() (0) -#endif - -#ifdef CONFIG_MACH_OSIRIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSIRIS -# endif -# define machine_is_osiris() (machine_arch_type == MACH_TYPE_OSIRIS) -#else -# define machine_is_osiris() (0) -#endif - -#ifdef CONFIG_MACH_MAESTRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAESTRO -# endif -# define machine_is_maestro() (machine_arch_type == MACH_TYPE_MAESTRO) -#else -# define machine_is_maestro() (0) -#endif - -#ifdef CONFIG_MACH_PALMTE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTE2 -# endif -# define machine_is_palmte2() (machine_arch_type == MACH_TYPE_PALMTE2) -#else -# define machine_is_palmte2() (0) -#endif - -#ifdef CONFIG_MACH_IXBBM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXBBM -# endif -# define machine_is_ixbbm() (machine_arch_type == MACH_TYPE_IXBBM) -#else -# define machine_is_ixbbm() (0) -#endif - -#ifdef CONFIG_MACH_MX27ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27ADS -# endif -# define machine_is_mx27ads() (machine_arch_type == MACH_TYPE_MX27ADS) -#else -# define machine_is_mx27ads() (0) -#endif - -#ifdef CONFIG_MACH_AX8004 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AX8004 -# endif -# define machine_is_ax8004() (machine_arch_type == MACH_TYPE_AX8004) -#else -# define machine_is_ax8004() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9261EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9261EK -# endif -# define machine_is_at91sam9261ek() (machine_arch_type == MACH_TYPE_AT91SAM9261EK) -#else -# define machine_is_at91sam9261ek() (0) -#endif - -#ifdef CONFIG_MACH_LOFT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOFT -# endif -# define machine_is_loft() (machine_arch_type == MACH_TYPE_LOFT) -#else -# define machine_is_loft() (0) -#endif - -#ifdef CONFIG_MACH_MAGPIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGPIE -# endif -# define machine_is_magpie() (machine_arch_type == MACH_TYPE_MAGPIE) -#else -# define machine_is_magpie() (0) -#endif - -#ifdef CONFIG_MACH_MX21ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX21ADS -# endif -# define machine_is_mx21ads() (machine_arch_type == MACH_TYPE_MX21ADS) -#else -# define machine_is_mx21ads() (0) -#endif - -#ifdef CONFIG_MACH_MB87M3400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB87M3400 -# endif -# define machine_is_mb87m3400() (machine_arch_type == MACH_TYPE_MB87M3400) -#else -# define machine_is_mb87m3400() (0) -#endif - -#ifdef CONFIG_MACH_MGUARD_DELTA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MGUARD_DELTA -# endif -# define machine_is_mguard_delta() (machine_arch_type == MACH_TYPE_MGUARD_DELTA) -#else -# define machine_is_mguard_delta() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DVDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DVDP -# endif -# define machine_is_davinci_dvdp() (machine_arch_type == MACH_TYPE_DAVINCI_DVDP) -#else -# define machine_is_davinci_dvdp() (0) -#endif - -#ifdef CONFIG_MACH_HTCUNIVERSAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCUNIVERSAL -# endif -# define machine_is_htcuniversal() (machine_arch_type == MACH_TYPE_HTCUNIVERSAL) -#else -# define machine_is_htcuniversal() (0) -#endif - -#ifdef CONFIG_MACH_TPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPAD -# endif -# define machine_is_tpad() (machine_arch_type == MACH_TYPE_TPAD) -#else -# define machine_is_tpad() (0) -#endif - -#ifdef CONFIG_MACH_ROVERP3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERP3 -# endif -# define machine_is_roverp3() (machine_arch_type == MACH_TYPE_ROVERP3) -#else -# define machine_is_roverp3() (0) -#endif - -#ifdef CONFIG_MACH_JORNADA928 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA928 -# endif -# define machine_is_jornada928() (machine_arch_type == MACH_TYPE_JORNADA928) -#else -# define machine_is_jornada928() (0) -#endif - -#ifdef CONFIG_MACH_MV88FXX81 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV88FXX81 -# endif -# define machine_is_mv88fxx81() (machine_arch_type == MACH_TYPE_MV88FXX81) -#else -# define machine_is_mv88fxx81() (0) -#endif - -#ifdef CONFIG_MACH_STMP36XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP36XX -# endif -# define machine_is_stmp36xx() (machine_arch_type == MACH_TYPE_STMP36XX) -#else -# define machine_is_stmp36xx() (0) -#endif - -#ifdef CONFIG_MACH_SXNI79524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SXNI79524 -# endif -# define machine_is_sxni79524() (machine_arch_type == MACH_TYPE_SXNI79524) -#else -# define machine_is_sxni79524() (0) -#endif - -#ifdef CONFIG_MACH_AMS_DELTA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMS_DELTA -# endif -# define machine_is_ams_delta() (machine_arch_type == MACH_TYPE_AMS_DELTA) -#else -# define machine_is_ams_delta() (0) -#endif - -#ifdef CONFIG_MACH_URANIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_URANIUM -# endif -# define machine_is_uranium() (machine_arch_type == MACH_TYPE_URANIUM) -#else -# define machine_is_uranium() (0) -#endif - -#ifdef CONFIG_MACH_UCON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCON -# endif -# define machine_is_ucon() (machine_arch_type == MACH_TYPE_UCON) -#else -# define machine_is_ucon() (0) -#endif - -#ifdef CONFIG_MACH_NAS100D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS100D -# endif -# define machine_is_nas100d() (machine_arch_type == MACH_TYPE_NAS100D) -#else -# define machine_is_nas100d() (0) -#endif - -#ifdef CONFIG_MACH_L083_1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_L083_1000 -# endif -# define machine_is_l083() (machine_arch_type == MACH_TYPE_L083_1000) -#else -# define machine_is_l083() (0) -#endif - -#ifdef CONFIG_MACH_EZX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX -# endif -# define machine_is_ezx() (machine_arch_type == MACH_TYPE_EZX) -#else -# define machine_is_ezx() (0) -#endif - -#ifdef CONFIG_MACH_PNX5220 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX5220 -# endif -# define machine_is_pnx5220() (machine_arch_type == MACH_TYPE_PNX5220) -#else -# define machine_is_pnx5220() (0) -#endif - -#ifdef CONFIG_MACH_BUTTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUTTE -# endif -# define machine_is_butte() (machine_arch_type == MACH_TYPE_BUTTE) -#else -# define machine_is_butte() (0) -#endif - -#ifdef CONFIG_MACH_SRM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SRM2 -# endif -# define machine_is_srm2() (machine_arch_type == MACH_TYPE_SRM2) -#else -# define machine_is_srm2() (0) -#endif - -#ifdef CONFIG_MACH_DSBR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSBR -# endif -# define machine_is_dsbr() (machine_arch_type == MACH_TYPE_DSBR) -#else -# define machine_is_dsbr() (0) -#endif - -#ifdef CONFIG_MACH_CRYSTALBALL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CRYSTALBALL -# endif -# define machine_is_crystalball() (machine_arch_type == MACH_TYPE_CRYSTALBALL) -#else -# define machine_is_crystalball() (0) -#endif - -#ifdef CONFIG_MACH_TINYPXA27X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TINYPXA27X -# endif -# define machine_is_tinypxa27x() (machine_arch_type == MACH_TYPE_TINYPXA27X) -#else -# define machine_is_tinypxa27x() (0) -#endif - -#ifdef CONFIG_MACH_HERBIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERBIE -# endif -# define machine_is_herbie() (machine_arch_type == MACH_TYPE_HERBIE) -#else -# define machine_is_herbie() (0) -#endif - -#ifdef CONFIG_MACH_MAGICIAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGICIAN -# endif -# define machine_is_magician() (machine_arch_type == MACH_TYPE_MAGICIAN) -#else -# define machine_is_magician() (0) -#endif - -#ifdef CONFIG_MACH_CM4002 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM4002 -# endif -# define machine_is_cm4002() (machine_arch_type == MACH_TYPE_CM4002) -#else -# define machine_is_cm4002() (0) -#endif - -#ifdef CONFIG_MACH_B4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_B4 -# endif -# define machine_is_b4() (machine_arch_type == MACH_TYPE_B4) -#else -# define machine_is_b4() (0) -#endif - -#ifdef CONFIG_MACH_MAUI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAUI -# endif -# define machine_is_maui() (machine_arch_type == MACH_TYPE_MAUI) -#else -# define machine_is_maui() (0) -#endif - -#ifdef CONFIG_MACH_CYBERTRACKER_G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBERTRACKER_G -# endif -# define machine_is_cybertracker_g() (machine_arch_type == MACH_TYPE_CYBERTRACKER_G) -#else -# define machine_is_cybertracker_g() (0) -#endif - -#ifdef CONFIG_MACH_NXDKN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXDKN -# endif -# define machine_is_nxdkn() (machine_arch_type == MACH_TYPE_NXDKN) -#else -# define machine_is_nxdkn() (0) -#endif - -#ifdef CONFIG_MACH_MIO8390 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIO8390 -# endif -# define machine_is_mio8390() (machine_arch_type == MACH_TYPE_MIO8390) -#else -# define machine_is_mio8390() (0) -#endif - -#ifdef CONFIG_MACH_OMI_BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMI_BOARD -# endif -# define machine_is_omi_board() (machine_arch_type == MACH_TYPE_OMI_BOARD) -#else -# define machine_is_omi_board() (0) -#endif - -#ifdef CONFIG_MACH_MX21CIV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX21CIV -# endif -# define machine_is_mx21civ() (machine_arch_type == MACH_TYPE_MX21CIV) -#else -# define machine_is_mx21civ() (0) -#endif - -#ifdef CONFIG_MACH_MAHI_CDAC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAHI_CDAC -# endif -# define machine_is_mahi_cdac() (machine_arch_type == MACH_TYPE_MAHI_CDAC) -#else -# define machine_is_mahi_cdac() (0) -#endif - -#ifdef CONFIG_MACH_PALMTX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTX -# endif -# define machine_is_palmtx() (machine_arch_type == MACH_TYPE_PALMTX) -#else -# define machine_is_palmtx() (0) -#endif - -#ifdef CONFIG_MACH_S3C2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2413 -# endif -# define machine_is_s3c2413() (machine_arch_type == MACH_TYPE_S3C2413) -#else -# define machine_is_s3c2413() (0) -#endif - -#ifdef CONFIG_MACH_SAMSYS_EP0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAMSYS_EP0 -# endif -# define machine_is_samsys_ep0() (machine_arch_type == MACH_TYPE_SAMSYS_EP0) -#else -# define machine_is_samsys_ep0() (0) -#endif - -#ifdef CONFIG_MACH_WG302V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WG302V1 -# endif -# define machine_is_wg302v1() (machine_arch_type == MACH_TYPE_WG302V1) -#else -# define machine_is_wg302v1() (0) -#endif - -#ifdef CONFIG_MACH_WG302V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WG302V2 -# endif -# define machine_is_wg302v2() (machine_arch_type == MACH_TYPE_WG302V2) -#else -# define machine_is_wg302v2() (0) -#endif - -#ifdef CONFIG_MACH_EB42X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EB42X -# endif -# define machine_is_eb42x() (machine_arch_type == MACH_TYPE_EB42X) -#else -# define machine_is_eb42x() (0) -#endif - -#ifdef CONFIG_MACH_IQ331ES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ331ES -# endif -# define machine_is_iq331es() (machine_arch_type == MACH_TYPE_IQ331ES) -#else -# define machine_is_iq331es() (0) -#endif - -#ifdef CONFIG_MACH_COSYDSP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COSYDSP -# endif -# define machine_is_cosydsp() (machine_arch_type == MACH_TYPE_COSYDSP) -#else -# define machine_is_cosydsp() (0) -#endif - -#ifdef CONFIG_MACH_UPLAT7D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UPLAT7D -# endif -# define machine_is_uplat7d_proto() (machine_arch_type == MACH_TYPE_UPLAT7D) -#else -# define machine_is_uplat7d_proto() (0) -#endif - -#ifdef CONFIG_MACH_PTDAVINCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTDAVINCI -# endif -# define machine_is_ptdavinci() (machine_arch_type == MACH_TYPE_PTDAVINCI) -#else -# define machine_is_ptdavinci() (0) -#endif - -#ifdef CONFIG_MACH_MBUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MBUS -# endif -# define machine_is_mbus() (machine_arch_type == MACH_TYPE_MBUS) -#else -# define machine_is_mbus() (0) -#endif - -#ifdef CONFIG_MACH_NADIA2VB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NADIA2VB -# endif -# define machine_is_nadia2vb() (machine_arch_type == MACH_TYPE_NADIA2VB) -#else -# define machine_is_nadia2vb() (0) -#endif - -#ifdef CONFIG_MACH_R1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_R1000 -# endif -# define machine_is_r1000() (machine_arch_type == MACH_TYPE_R1000) -#else -# define machine_is_r1000() (0) -#endif - -#ifdef CONFIG_MACH_HW90250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90250 -# endif -# define machine_is_hw90250() (machine_arch_type == MACH_TYPE_HW90250) -#else -# define machine_is_hw90250() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430SDP -# endif -# define machine_is_omap_2430sdp() (machine_arch_type == MACH_TYPE_OMAP_2430SDP) -#else -# define machine_is_omap_2430sdp() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_EVM -# endif -# define machine_is_davinci_evm() (machine_arch_type == MACH_TYPE_DAVINCI_EVM) -#else -# define machine_is_davinci_evm() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_TORNADO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_TORNADO -# endif -# define machine_is_omap_tornado() (machine_arch_type == MACH_TYPE_OMAP_TORNADO) -#else -# define machine_is_omap_tornado() (0) -#endif - -#ifdef CONFIG_MACH_OLOCREEK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OLOCREEK -# endif -# define machine_is_olocreek() (machine_arch_type == MACH_TYPE_OLOCREEK) -#else -# define machine_is_olocreek() (0) -#endif - -#ifdef CONFIG_MACH_PALMZ72 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMZ72 -# endif -# define machine_is_palmz72() (machine_arch_type == MACH_TYPE_PALMZ72) -#else -# define machine_is_palmz72() (0) -#endif - -#ifdef CONFIG_MACH_NXDB500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXDB500 -# endif -# define machine_is_nxdb500() (machine_arch_type == MACH_TYPE_NXDB500) -#else -# define machine_is_nxdb500() (0) -#endif - -#ifdef CONFIG_MACH_APF9328 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APF9328 -# endif -# define machine_is_apf9328() (machine_arch_type == MACH_TYPE_APF9328) -#else -# define machine_is_apf9328() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_WIPOQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_WIPOQ -# endif -# define machine_is_omap_wipoq() (machine_arch_type == MACH_TYPE_OMAP_WIPOQ) -#else -# define machine_is_omap_wipoq() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_TWIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_TWIP -# endif -# define machine_is_omap_twip() (machine_arch_type == MACH_TYPE_OMAP_TWIP) -#else -# define machine_is_omap_twip() (0) -#endif - -#ifdef CONFIG_MACH_TREO650 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO650 -# endif -# define machine_is_treo650() (machine_arch_type == MACH_TYPE_TREO650) -#else -# define machine_is_treo650() (0) -#endif - -#ifdef CONFIG_MACH_ACUMEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACUMEN -# endif -# define machine_is_acumen() (machine_arch_type == MACH_TYPE_ACUMEN) -#else -# define machine_is_acumen() (0) -#endif - -#ifdef CONFIG_MACH_XP100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP100 -# endif -# define machine_is_xp100() (machine_arch_type == MACH_TYPE_XP100) -#else -# define machine_is_xp100() (0) -#endif - -#ifdef CONFIG_MACH_FS2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FS2410 -# endif -# define machine_is_fs2410() (machine_arch_type == MACH_TYPE_FS2410) -#else -# define machine_is_fs2410() (0) -#endif - -#ifdef CONFIG_MACH_PXA270_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA270_CERF -# endif -# define machine_is_pxa270_cerf() (machine_arch_type == MACH_TYPE_PXA270_CERF) -#else -# define machine_is_pxa270_cerf() (0) -#endif - -#ifdef CONFIG_MACH_SQ2FTLPALM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SQ2FTLPALM -# endif -# define machine_is_sq2ftlpalm() (machine_arch_type == MACH_TYPE_SQ2FTLPALM) -#else -# define machine_is_sq2ftlpalm() (0) -#endif - -#ifdef CONFIG_MACH_BSEMSERVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSEMSERVER -# endif -# define machine_is_bsemserver() (machine_arch_type == MACH_TYPE_BSEMSERVER) -#else -# define machine_is_bsemserver() (0) -#endif - -#ifdef CONFIG_MACH_NETCLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETCLIENT -# endif -# define machine_is_netclient() (machine_arch_type == MACH_TYPE_NETCLIENT) -#else -# define machine_is_netclient() (0) -#endif - -#ifdef CONFIG_MACH_PALMT5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMT5 -# endif -# define machine_is_palmt5() (machine_arch_type == MACH_TYPE_PALMT5) -#else -# define machine_is_palmt5() (0) -#endif - -#ifdef CONFIG_MACH_PALMTC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTC -# endif -# define machine_is_palmtc() (machine_arch_type == MACH_TYPE_PALMTC) -#else -# define machine_is_palmtc() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_APOLLON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_APOLLON -# endif -# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON) -#else -# define machine_is_omap_apollon() (0) -#endif - -#ifdef CONFIG_MACH_MXC30030EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30030EVB -# endif -# define machine_is_mxc30030evb() (machine_arch_type == MACH_TYPE_MXC30030EVB) -#else -# define machine_is_mxc30030evb() (0) -#endif - -#ifdef CONFIG_MACH_REA_2D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REA_2D -# endif -# define machine_is_rea_cpu2() (machine_arch_type == MACH_TYPE_REA_2D) -#else -# define machine_is_rea_cpu2() (0) -#endif - -#ifdef CONFIG_MACH_TI3E524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI3E524 -# endif -# define machine_is_eti3e524() (machine_arch_type == MACH_TYPE_TI3E524) -#else -# define machine_is_eti3e524() (0) -#endif - -#ifdef CONFIG_MACH_ATEB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATEB9200 -# endif -# define machine_is_ateb9200() (machine_arch_type == MACH_TYPE_ATEB9200) -#else -# define machine_is_ateb9200() (0) -#endif - -#ifdef CONFIG_MACH_AUCKLAND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUCKLAND -# endif -# define machine_is_auckland() (machine_arch_type == MACH_TYPE_AUCKLAND) -#else -# define machine_is_auckland() (0) -#endif - -#ifdef CONFIG_MACH_AK3320M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AK3320M -# endif -# define machine_is_ak3220m() (machine_arch_type == MACH_TYPE_AK3320M) -#else -# define machine_is_ak3220m() (0) -#endif - -#ifdef CONFIG_MACH_DURAMAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DURAMAX -# endif -# define machine_is_duramax() (machine_arch_type == MACH_TYPE_DURAMAX) -#else -# define machine_is_duramax() (0) -#endif - -#ifdef CONFIG_MACH_N35 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N35 -# endif -# define machine_is_n35() (machine_arch_type == MACH_TYPE_N35) -#else -# define machine_is_n35() (0) -#endif - -#ifdef CONFIG_MACH_PRONGHORN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRONGHORN -# endif -# define machine_is_pronghorn() (machine_arch_type == MACH_TYPE_PRONGHORN) -#else -# define machine_is_pronghorn() (0) -#endif - -#ifdef CONFIG_MACH_FUNDY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUNDY -# endif -# define machine_is_fundy() (machine_arch_type == MACH_TYPE_FUNDY) -#else -# define machine_is_fundy() (0) -#endif - -#ifdef CONFIG_MACH_LOGICPD_PXA270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGICPD_PXA270 -# endif -# define machine_is_logicpd_pxa270() (machine_arch_type == MACH_TYPE_LOGICPD_PXA270) -#else -# define machine_is_logicpd_pxa270() (0) -#endif - -#ifdef CONFIG_MACH_CPU777 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPU777 -# endif -# define machine_is_cpu777() (machine_arch_type == MACH_TYPE_CPU777) -#else -# define machine_is_cpu777() (0) -#endif - -#ifdef CONFIG_MACH_SIMICON9201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMICON9201 -# endif -# define machine_is_simicon9201() (machine_arch_type == MACH_TYPE_SIMICON9201) -#else -# define machine_is_simicon9201() (0) -#endif - -#ifdef CONFIG_MACH_LEAP2_HPM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEAP2_HPM -# endif -# define machine_is_leap2_hpm() (machine_arch_type == MACH_TYPE_LEAP2_HPM) -#else -# define machine_is_leap2_hpm() (0) -#endif - -#ifdef CONFIG_MACH_CM922TXA10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM922TXA10 -# endif -# define machine_is_cm922txa10() (machine_arch_type == MACH_TYPE_CM922TXA10) -#else -# define machine_is_cm922txa10() (0) -#endif - -#ifdef CONFIG_MACH_PXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA -# endif -# define machine_is_sandgate() (machine_arch_type == MACH_TYPE_PXA) -#else -# define machine_is_sandgate() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE2 -# endif -# define machine_is_sandgate2() (machine_arch_type == MACH_TYPE_SANDGATE2) -#else -# define machine_is_sandgate2() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE2G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE2G -# endif -# define machine_is_sandgate2g() (machine_arch_type == MACH_TYPE_SANDGATE2G) -#else -# define machine_is_sandgate2g() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE2P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE2P -# endif -# define machine_is_sandgate2p() (machine_arch_type == MACH_TYPE_SANDGATE2P) -#else -# define machine_is_sandgate2p() (0) -#endif - -#ifdef CONFIG_MACH_FRED_JACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRED_JACK -# endif -# define machine_is_fred_jack() (machine_arch_type == MACH_TYPE_FRED_JACK) -#else -# define machine_is_fred_jack() (0) -#endif - -#ifdef CONFIG_MACH_TTG_COLOR1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TTG_COLOR1 -# endif -# define machine_is_ttg_color1() (machine_arch_type == MACH_TYPE_TTG_COLOR1) -#else -# define machine_is_ttg_color1() (0) -#endif - -#ifdef CONFIG_MACH_NXEB500HMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXEB500HMI -# endif -# define machine_is_nxeb500hmi() (machine_arch_type == MACH_TYPE_NXEB500HMI) -#else -# define machine_is_nxeb500hmi() (0) -#endif - -#ifdef CONFIG_MACH_NETDCU8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETDCU8 -# endif -# define machine_is_netdcu8() (machine_arch_type == MACH_TYPE_NETDCU8) -#else -# define machine_is_netdcu8() (0) -#endif - -#ifdef CONFIG_MACH_NG_FVX538 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NG_FVX538 -# endif -# define machine_is_ng_fvx538() (machine_arch_type == MACH_TYPE_NG_FVX538) -#else -# define machine_is_ng_fvx538() (0) -#endif - -#ifdef CONFIG_MACH_NG_FVS338 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NG_FVS338 -# endif -# define machine_is_ng_fvs338() (machine_arch_type == MACH_TYPE_NG_FVS338) -#else -# define machine_is_ng_fvs338() (0) -#endif - -#ifdef CONFIG_MACH_PNX4103 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX4103 -# endif -# define machine_is_pnx4103() (machine_arch_type == MACH_TYPE_PNX4103) -#else -# define machine_is_pnx4103() (0) -#endif - -#ifdef CONFIG_MACH_HESDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HESDB -# endif -# define machine_is_hesdb() (machine_arch_type == MACH_TYPE_HESDB) -#else -# define machine_is_hesdb() (0) -#endif - -#ifdef CONFIG_MACH_XSILO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSILO -# endif -# define machine_is_xsilo() (machine_arch_type == MACH_TYPE_XSILO) -#else -# define machine_is_xsilo() (0) -#endif - -#ifdef CONFIG_MACH_ESPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESPRESSO -# endif -# define machine_is_espresso() (machine_arch_type == MACH_TYPE_ESPRESSO) -#else -# define machine_is_espresso() (0) -#endif - -#ifdef CONFIG_MACH_EMLC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMLC -# endif -# define machine_is_emlc() (machine_arch_type == MACH_TYPE_EMLC) -#else -# define machine_is_emlc() (0) -#endif - -#ifdef CONFIG_MACH_SISTERON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SISTERON -# endif -# define machine_is_sisteron() (machine_arch_type == MACH_TYPE_SISTERON) -#else -# define machine_is_sisteron() (0) -#endif - -#ifdef CONFIG_MACH_RX1950 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RX1950 -# endif -# define machine_is_rx1950() (machine_arch_type == MACH_TYPE_RX1950) -#else -# define machine_is_rx1950() (0) -#endif - -#ifdef CONFIG_MACH_TSC_VENUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TSC_VENUS -# endif -# define machine_is_tsc_venus() (machine_arch_type == MACH_TYPE_TSC_VENUS) -#else -# define machine_is_tsc_venus() (0) -#endif - -#ifdef CONFIG_MACH_DS101J -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS101J -# endif -# define machine_is_ds101j() (machine_arch_type == MACH_TYPE_DS101J) -#else -# define machine_is_ds101j() (0) -#endif - -#ifdef CONFIG_MACH_MXC30030ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30030ADS -# endif -# define machine_is_mxc30030ads() (machine_arch_type == MACH_TYPE_MXC30030ADS) -#else -# define machine_is_mxc30030ads() (0) -#endif - -#ifdef CONFIG_MACH_FUJITSU_WIMAXSOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJITSU_WIMAXSOC -# endif -# define machine_is_fujitsu_wimaxsoc() (machine_arch_type == MACH_TYPE_FUJITSU_WIMAXSOC) -#else -# define machine_is_fujitsu_wimaxsoc() (0) -#endif - -#ifdef CONFIG_MACH_DUALPCMODEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DUALPCMODEM -# endif -# define machine_is_dualpcmodem() (machine_arch_type == MACH_TYPE_DUALPCMODEM) -#else -# define machine_is_dualpcmodem() (0) -#endif - -#ifdef CONFIG_MACH_GESBC9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GESBC9312 -# endif -# define machine_is_gesbc9312() (machine_arch_type == MACH_TYPE_GESBC9312) -#else -# define machine_is_gesbc9312() (0) -#endif - -#ifdef CONFIG_MACH_HTCAPACHE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCAPACHE -# endif -# define machine_is_htcapache() (machine_arch_type == MACH_TYPE_HTCAPACHE) -#else -# define machine_is_htcapache() (0) -#endif - -#ifdef CONFIG_MACH_IXDP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP435 -# endif -# define machine_is_ixdp435() (machine_arch_type == MACH_TYPE_IXDP435) -#else -# define machine_is_ixdp435() (0) -#endif - -#ifdef CONFIG_MACH_CATPROVT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CATPROVT100 -# endif -# define machine_is_catprovt100() (machine_arch_type == MACH_TYPE_CATPROVT100) -#else -# define machine_is_catprovt100() (0) -#endif - -#ifdef CONFIG_MACH_PICOTUX1XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOTUX1XX -# endif -# define machine_is_picotux1xx() (machine_arch_type == MACH_TYPE_PICOTUX1XX) -#else -# define machine_is_picotux1xx() (0) -#endif - -#ifdef CONFIG_MACH_PICOTUX2XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOTUX2XX -# endif -# define machine_is_picotux2xx() (machine_arch_type == MACH_TYPE_PICOTUX2XX) -#else -# define machine_is_picotux2xx() (0) -#endif - -#ifdef CONFIG_MACH_DSMG600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSMG600 -# endif -# define machine_is_dsmg600() (machine_arch_type == MACH_TYPE_DSMG600) -#else -# define machine_is_dsmg600() (0) -#endif - -#ifdef CONFIG_MACH_EMPC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPC2 -# endif -# define machine_is_empc2() (machine_arch_type == MACH_TYPE_EMPC2) -#else -# define machine_is_empc2() (0) -#endif - -#ifdef CONFIG_MACH_VENTURA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VENTURA -# endif -# define machine_is_ventura() (machine_arch_type == MACH_TYPE_VENTURA) -#else -# define machine_is_ventura() (0) -#endif - -#ifdef CONFIG_MACH_PHIDGET_SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHIDGET_SBC -# endif -# define machine_is_phidget_sbc() (machine_arch_type == MACH_TYPE_PHIDGET_SBC) -#else -# define machine_is_phidget_sbc() (0) -#endif - -#ifdef CONFIG_MACH_IJ3K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IJ3K -# endif -# define machine_is_ij3k() (machine_arch_type == MACH_TYPE_IJ3K) -#else -# define machine_is_ij3k() (0) -#endif - -#ifdef CONFIG_MACH_PISGAH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PISGAH -# endif -# define machine_is_pisgah() (machine_arch_type == MACH_TYPE_PISGAH) -#else -# define machine_is_pisgah() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_FSAMPLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_FSAMPLE -# endif -# define machine_is_omap_fsample() (machine_arch_type == MACH_TYPE_OMAP_FSAMPLE) -#else -# define machine_is_omap_fsample() (0) -#endif - -#ifdef CONFIG_MACH_SG720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG720 -# endif -# define machine_is_sg720() (machine_arch_type == MACH_TYPE_SG720) -#else -# define machine_is_sg720() (0) -#endif - -#ifdef CONFIG_MACH_REDFOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REDFOX -# endif -# define machine_is_redfox() (machine_arch_type == MACH_TYPE_REDFOX) -#else -# define machine_is_redfox() (0) -#endif - -#ifdef CONFIG_MACH_MYSH_EP9315_1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MYSH_EP9315_1 -# endif -# define machine_is_mysh_ep9315_1() (machine_arch_type == MACH_TYPE_MYSH_EP9315_1) -#else -# define machine_is_mysh_ep9315_1() (0) -#endif - -#ifdef CONFIG_MACH_TPF106 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPF106 -# endif -# define machine_is_tpf106() (machine_arch_type == MACH_TYPE_TPF106) -#else -# define machine_is_tpf106() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200KG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200KG -# endif -# define machine_is_at91rm9200kg() (machine_arch_type == MACH_TYPE_AT91RM9200KG) -#else -# define machine_is_at91rm9200kg() (0) -#endif - -#ifdef CONFIG_MACH_SLEDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SLEDB -# endif -# define machine_is_rcmt2() (machine_arch_type == MACH_TYPE_SLEDB) -#else -# define machine_is_rcmt2() (0) -#endif - -#ifdef CONFIG_MACH_ONTRACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ONTRACK -# endif -# define machine_is_ontrack() (machine_arch_type == MACH_TYPE_ONTRACK) -#else -# define machine_is_ontrack() (0) -#endif - -#ifdef CONFIG_MACH_PM1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM1200 -# endif -# define machine_is_pm1200() (machine_arch_type == MACH_TYPE_PM1200) -#else -# define machine_is_pm1200() (0) -#endif - -#ifdef CONFIG_MACH_ESS24XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESS24XXX -# endif -# define machine_is_ess24562() (machine_arch_type == MACH_TYPE_ESS24XXX) -#else -# define machine_is_ess24562() (0) -#endif - -#ifdef CONFIG_MACH_COREMP7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COREMP7 -# endif -# define machine_is_coremp7() (machine_arch_type == MACH_TYPE_COREMP7) -#else -# define machine_is_coremp7() (0) -#endif - -#ifdef CONFIG_MACH_NEXCODER_6446 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXCODER_6446 -# endif -# define machine_is_nexcoder_6446() (machine_arch_type == MACH_TYPE_NEXCODER_6446) -#else -# define machine_is_nexcoder_6446() (0) -#endif - -#ifdef CONFIG_MACH_STVC8380 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STVC8380 -# endif -# define machine_is_stvc8380() (machine_arch_type == MACH_TYPE_STVC8380) -#else -# define machine_is_stvc8380() (0) -#endif - -#ifdef CONFIG_MACH_TEKLYNX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEKLYNX -# endif -# define machine_is_teklynx() (machine_arch_type == MACH_TYPE_TEKLYNX) -#else -# define machine_is_teklynx() (0) -#endif - -#ifdef CONFIG_MACH_CARBONADO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARBONADO -# endif -# define machine_is_carbonado() (machine_arch_type == MACH_TYPE_CARBONADO) -#else -# define machine_is_carbonado() (0) -#endif - -#ifdef CONFIG_MACH_SYSMOS_MP730 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYSMOS_MP730 -# endif -# define machine_is_sysmos_mp730() (machine_arch_type == MACH_TYPE_SYSMOS_MP730) -#else -# define machine_is_sysmos_mp730() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_CL15 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_CL15 -# endif -# define machine_is_snapper_cl15() (machine_arch_type == MACH_TYPE_SNAPPER_CL15) -#else -# define machine_is_snapper_cl15() (0) -#endif - -#ifdef CONFIG_MACH_PGIGIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PGIGIM -# endif -# define machine_is_pgigim() (machine_arch_type == MACH_TYPE_PGIGIM) -#else -# define machine_is_pgigim() (0) -#endif - -#ifdef CONFIG_MACH_PTX9160P2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTX9160P2 -# endif -# define machine_is_ptx9160p2() (machine_arch_type == MACH_TYPE_PTX9160P2) -#else -# define machine_is_ptx9160p2() (0) -#endif - -#ifdef CONFIG_MACH_DCORE1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DCORE1 -# endif -# define machine_is_dcore1() (machine_arch_type == MACH_TYPE_DCORE1) -#else -# define machine_is_dcore1() (0) -#endif - -#ifdef CONFIG_MACH_VICTORPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VICTORPXA -# endif -# define machine_is_victorpxa() (machine_arch_type == MACH_TYPE_VICTORPXA) -#else -# define machine_is_victorpxa() (0) -#endif - -#ifdef CONFIG_MACH_MX2DTB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX2DTB -# endif -# define machine_is_mx2dtb() (machine_arch_type == MACH_TYPE_MX2DTB) -#else -# define machine_is_mx2dtb() (0) -#endif - -#ifdef CONFIG_MACH_PXA_IREX_ER0100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_IREX_ER0100 -# endif -# define machine_is_pxa_irex_er0100() (machine_arch_type == MACH_TYPE_PXA_IREX_ER0100) -#else -# define machine_is_pxa_irex_er0100() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMZ71 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMZ71 -# endif -# define machine_is_omap_palmz71() (machine_arch_type == MACH_TYPE_OMAP_PALMZ71) -#else -# define machine_is_omap_palmz71() (0) -#endif - -#ifdef CONFIG_MACH_BARTEC_DEG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BARTEC_DEG -# endif -# define machine_is_bartec_deg() (machine_arch_type == MACH_TYPE_BARTEC_DEG) -#else -# define machine_is_bartec_deg() (0) -#endif - -#ifdef CONFIG_MACH_HW50251 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW50251 -# endif -# define machine_is_hw50251() (machine_arch_type == MACH_TYPE_HW50251) -#else -# define machine_is_hw50251() (0) -#endif - -#ifdef CONFIG_MACH_IBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IBOX -# endif -# define machine_is_ibox() (machine_arch_type == MACH_TYPE_IBOX) -#else -# define machine_is_ibox() (0) -#endif - -#ifdef CONFIG_MACH_ATLASLH7A404 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATLASLH7A404 -# endif -# define machine_is_atlaslh7a404() (machine_arch_type == MACH_TYPE_ATLASLH7A404) -#else -# define machine_is_atlaslh7a404() (0) -#endif - -#ifdef CONFIG_MACH_PT2026 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PT2026 -# endif -# define machine_is_pt2026() (machine_arch_type == MACH_TYPE_PT2026) -#else -# define machine_is_pt2026() (0) -#endif - -#ifdef CONFIG_MACH_HTCALPINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCALPINE -# endif -# define machine_is_htcalpine() (machine_arch_type == MACH_TYPE_HTCALPINE) -#else -# define machine_is_htcalpine() (0) -#endif - -#ifdef CONFIG_MACH_BARTEC_VTU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BARTEC_VTU -# endif -# define machine_is_bartec_vtu() (machine_arch_type == MACH_TYPE_BARTEC_VTU) -#else -# define machine_is_bartec_vtu() (0) -#endif - -#ifdef CONFIG_MACH_VCOREII -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCOREII -# endif -# define machine_is_vcoreii() (machine_arch_type == MACH_TYPE_VCOREII) -#else -# define machine_is_vcoreii() (0) -#endif - -#ifdef CONFIG_MACH_PDNB3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PDNB3 -# endif -# define machine_is_pdnb3() (machine_arch_type == MACH_TYPE_PDNB3) -#else -# define machine_is_pdnb3() (0) -#endif - -#ifdef CONFIG_MACH_HTCBEETLES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCBEETLES -# endif -# define machine_is_htcbeetles() (machine_arch_type == MACH_TYPE_HTCBEETLES) -#else -# define machine_is_htcbeetles() (0) -#endif - -#ifdef CONFIG_MACH_S3C6400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C6400 -# endif -# define machine_is_s3c6400() (machine_arch_type == MACH_TYPE_S3C6400) -#else -# define machine_is_s3c6400() (0) -#endif - -#ifdef CONFIG_MACH_S3C2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2443 -# endif -# define machine_is_s3c2443() (machine_arch_type == MACH_TYPE_S3C2443) -#else -# define machine_is_s3c2443() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_LDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_LDK -# endif -# define machine_is_omap_ldk() (machine_arch_type == MACH_TYPE_OMAP_LDK) -#else -# define machine_is_omap_ldk() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2460 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2460 -# endif -# define machine_is_smdk2460() (machine_arch_type == MACH_TYPE_SMDK2460) -#else -# define machine_is_smdk2460() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2440 -# endif -# define machine_is_smdk2440() (machine_arch_type == MACH_TYPE_SMDK2440) -#else -# define machine_is_smdk2440() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2412 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2412 -# endif -# define machine_is_smdk2412() (machine_arch_type == MACH_TYPE_SMDK2412) -#else -# define machine_is_smdk2412() (0) -#endif - -#ifdef CONFIG_MACH_WEBBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WEBBOX -# endif -# define machine_is_webbox() (machine_arch_type == MACH_TYPE_WEBBOX) -#else -# define machine_is_webbox() (0) -#endif - -#ifdef CONFIG_MACH_CWWNDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWWNDP -# endif -# define machine_is_cwwndp() (machine_arch_type == MACH_TYPE_CWWNDP) -#else -# define machine_is_cwwndp() (0) -#endif - -#ifdef CONFIG_MACH_DRAGON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DRAGON -# endif -# define machine_is_i839() (machine_arch_type == MACH_TYPE_DRAGON) -#else -# define machine_is_i839() (0) -#endif - -#ifdef CONFIG_MACH_OPENDO_CPU_BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENDO_CPU_BOARD -# endif -# define machine_is_opendo_cpu_board() (machine_arch_type == MACH_TYPE_OPENDO_CPU_BOARD) -#else -# define machine_is_opendo_cpu_board() (0) -#endif - -#ifdef CONFIG_MACH_CCM2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCM2200 -# endif -# define machine_is_ccm2200() (machine_arch_type == MACH_TYPE_CCM2200) -#else -# define machine_is_ccm2200() (0) -#endif - -#ifdef CONFIG_MACH_ETWARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETWARM -# endif -# define machine_is_etwarm() (machine_arch_type == MACH_TYPE_ETWARM) -#else -# define machine_is_etwarm() (0) -#endif - -#ifdef CONFIG_MACH_M93030 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M93030 -# endif -# define machine_is_m93030() (machine_arch_type == MACH_TYPE_M93030) -#else -# define machine_is_m93030() (0) -#endif - -#ifdef CONFIG_MACH_CC7U -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC7U -# endif -# define machine_is_cc7u() (machine_arch_type == MACH_TYPE_CC7U) -#else -# define machine_is_cc7u() (0) -#endif - -#ifdef CONFIG_MACH_MTT_RANGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MTT_RANGER -# endif -# define machine_is_mtt_ranger() (machine_arch_type == MACH_TYPE_MTT_RANGER) -#else -# define machine_is_mtt_ranger() (0) -#endif - -#ifdef CONFIG_MACH_NEXUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXUS -# endif -# define machine_is_nexus() (machine_arch_type == MACH_TYPE_NEXUS) -#else -# define machine_is_nexus() (0) -#endif - -#ifdef CONFIG_MACH_DESMAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DESMAN -# endif -# define machine_is_desman() (machine_arch_type == MACH_TYPE_DESMAN) -#else -# define machine_is_desman() (0) -#endif - -#ifdef CONFIG_MACH_BKDE303 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BKDE303 -# endif -# define machine_is_bkde303() (machine_arch_type == MACH_TYPE_BKDE303) -#else -# define machine_is_bkde303() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2413 -# endif -# define machine_is_smdk2413() (machine_arch_type == MACH_TYPE_SMDK2413) -#else -# define machine_is_smdk2413() (0) -#endif - -#ifdef CONFIG_MACH_AML_M7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M7200 -# endif -# define machine_is_aml_m7200() (machine_arch_type == MACH_TYPE_AML_M7200) -#else -# define machine_is_aml_m7200() (0) -#endif - -#ifdef CONFIG_MACH_AML_M5900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M5900 -# endif -# define machine_is_aml_m5900() (machine_arch_type == MACH_TYPE_AML_M5900) -#else -# define machine_is_aml_m5900() (0) -#endif - -#ifdef CONFIG_MACH_SG640 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG640 -# endif -# define machine_is_sg640() (machine_arch_type == MACH_TYPE_SG640) -#else -# define machine_is_sg640() (0) -#endif - -#ifdef CONFIG_MACH_EDG79524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDG79524 -# endif -# define machine_is_edg79524() (machine_arch_type == MACH_TYPE_EDG79524) -#else -# define machine_is_edg79524() (0) -#endif - -#ifdef CONFIG_MACH_AI2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AI2410 -# endif -# define machine_is_ai2410() (machine_arch_type == MACH_TYPE_AI2410) -#else -# define machine_is_ai2410() (0) -#endif - -#ifdef CONFIG_MACH_IXP465 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXP465 -# endif -# define machine_is_ixp465() (machine_arch_type == MACH_TYPE_IXP465) -#else -# define machine_is_ixp465() (0) -#endif - -#ifdef CONFIG_MACH_BALLOON3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLOON3 -# endif -# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3) -#else -# define machine_is_balloon3() (0) -#endif - -#ifdef CONFIG_MACH_HEINS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HEINS -# endif -# define machine_is_heins() (machine_arch_type == MACH_TYPE_HEINS) -#else -# define machine_is_heins() (0) -#endif - -#ifdef CONFIG_MACH_MPLUSEVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPLUSEVA -# endif -# define machine_is_mpluseva() (machine_arch_type == MACH_TYPE_MPLUSEVA) -#else -# define machine_is_mpluseva() (0) -#endif - -#ifdef CONFIG_MACH_RT042 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RT042 -# endif -# define machine_is_rt042() (machine_arch_type == MACH_TYPE_RT042) -#else -# define machine_is_rt042() (0) -#endif - -#ifdef CONFIG_MACH_CWIEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWIEM -# endif -# define machine_is_cwiem() (machine_arch_type == MACH_TYPE_CWIEM) -#else -# define machine_is_cwiem() (0) -#endif - -#ifdef CONFIG_MACH_CM_X270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_X270 -# endif -# define machine_is_cm_x270() (machine_arch_type == MACH_TYPE_CM_X270) -#else -# define machine_is_cm_x270() (0) -#endif - -#ifdef CONFIG_MACH_CM_X255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_X255 -# endif -# define machine_is_cm_x255() (machine_arch_type == MACH_TYPE_CM_X255) -#else -# define machine_is_cm_x255() (0) -#endif - -#ifdef CONFIG_MACH_ESH_AT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESH_AT91 -# endif -# define machine_is_esh_at91() (machine_arch_type == MACH_TYPE_ESH_AT91) -#else -# define machine_is_esh_at91() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATE3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATE3 -# endif -# define machine_is_sandgate3() (machine_arch_type == MACH_TYPE_SANDGATE3) -#else -# define machine_is_sandgate3() (0) -#endif - -#ifdef CONFIG_MACH_PRIMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRIMO -# endif -# define machine_is_primo() (machine_arch_type == MACH_TYPE_PRIMO) -#else -# define machine_is_primo() (0) -#endif - -#ifdef CONFIG_MACH_GEMSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMSTONE -# endif -# define machine_is_gemstone() (machine_arch_type == MACH_TYPE_GEMSTONE) -#else -# define machine_is_gemstone() (0) -#endif - -#ifdef CONFIG_MACH_PRONGHORNMETRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRONGHORNMETRO -# endif -# define machine_is_pronghorn_metro() (machine_arch_type == MACH_TYPE_PRONGHORNMETRO) -#else -# define machine_is_pronghorn_metro() (0) -#endif - -#ifdef CONFIG_MACH_SIDEWINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIDEWINDER -# endif -# define machine_is_sidewinder() (machine_arch_type == MACH_TYPE_SIDEWINDER) -#else -# define machine_is_sidewinder() (0) -#endif - -#ifdef CONFIG_MACH_PICOMOD1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOMOD1 -# endif -# define machine_is_picomod1() (machine_arch_type == MACH_TYPE_PICOMOD1) -#else -# define machine_is_picomod1() (0) -#endif - -#ifdef CONFIG_MACH_SG590 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG590 -# endif -# define machine_is_sg590() (machine_arch_type == MACH_TYPE_SG590) -#else -# define machine_is_sg590() (0) -#endif - -#ifdef CONFIG_MACH_AKAI9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKAI9307 -# endif -# define machine_is_akai9307() (machine_arch_type == MACH_TYPE_AKAI9307) -#else -# define machine_is_akai9307() (0) -#endif - -#ifdef CONFIG_MACH_FONTAINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FONTAINE -# endif -# define machine_is_fontaine() (machine_arch_type == MACH_TYPE_FONTAINE) -#else -# define machine_is_fontaine() (0) -#endif - -#ifdef CONFIG_MACH_WOMBAT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WOMBAT -# endif -# define machine_is_wombat() (machine_arch_type == MACH_TYPE_WOMBAT) -#else -# define machine_is_wombat() (0) -#endif - -#ifdef CONFIG_MACH_ACQ300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ300 -# endif -# define machine_is_acq300() (machine_arch_type == MACH_TYPE_ACQ300) -#else -# define machine_is_acq300() (0) -#endif - -#ifdef CONFIG_MACH_MOD_270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOD_270 -# endif -# define machine_is_mod272() (machine_arch_type == MACH_TYPE_MOD_270) -#else -# define machine_is_mod272() (0) -#endif - -#ifdef CONFIG_MACH_VC0820 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC0820 -# endif -# define machine_is_vmc_vc0820() (machine_arch_type == MACH_TYPE_VC0820) -#else -# define machine_is_vmc_vc0820() (0) -#endif - -#ifdef CONFIG_MACH_ANI_AIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANI_AIM -# endif -# define machine_is_ani_aim() (machine_arch_type == MACH_TYPE_ANI_AIM) -#else -# define machine_is_ani_aim() (0) -#endif - -#ifdef CONFIG_MACH_JELLYFISH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JELLYFISH -# endif -# define machine_is_jellyfish() (machine_arch_type == MACH_TYPE_JELLYFISH) -#else -# define machine_is_jellyfish() (0) -#endif - -#ifdef CONFIG_MACH_AMANITA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMANITA -# endif -# define machine_is_amanita() (machine_arch_type == MACH_TYPE_AMANITA) -#else -# define machine_is_amanita() (0) -#endif - -#ifdef CONFIG_MACH_VLINK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VLINK -# endif -# define machine_is_vlink() (machine_arch_type == MACH_TYPE_VLINK) -#else -# define machine_is_vlink() (0) -#endif - -#ifdef CONFIG_MACH_DEXFLEX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEXFLEX -# endif -# define machine_is_dexflex() (machine_arch_type == MACH_TYPE_DEXFLEX) -#else -# define machine_is_dexflex() (0) -#endif - -#ifdef CONFIG_MACH_EIGEN_TTQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EIGEN_TTQ -# endif -# define machine_is_eigen_ttq() (machine_arch_type == MACH_TYPE_EIGEN_TTQ) -#else -# define machine_is_eigen_ttq() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_TITAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_TITAN -# endif -# define machine_is_arcom_titan() (machine_arch_type == MACH_TYPE_ARCOM_TITAN) -#else -# define machine_is_arcom_titan() (0) -#endif - -#ifdef CONFIG_MACH_TABLA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TABLA -# endif -# define machine_is_tabla() (machine_arch_type == MACH_TYPE_TABLA) -#else -# define machine_is_tabla() (0) -#endif - -#ifdef CONFIG_MACH_MDIRAC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MDIRAC3 -# endif -# define machine_is_mdirac3() (machine_arch_type == MACH_TYPE_MDIRAC3) -#else -# define machine_is_mdirac3() (0) -#endif - -#ifdef CONFIG_MACH_MRHFBP2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MRHFBP2 -# endif -# define machine_is_mrhfbp2() (machine_arch_type == MACH_TYPE_MRHFBP2) -#else -# define machine_is_mrhfbp2() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200RB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200RB -# endif -# define machine_is_at91rm9200rb() (machine_arch_type == MACH_TYPE_AT91RM9200RB) -#else -# define machine_is_at91rm9200rb() (0) -#endif - -#ifdef CONFIG_MACH_ANI_APM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANI_APM -# endif -# define machine_is_ani_apm() (machine_arch_type == MACH_TYPE_ANI_APM) -#else -# define machine_is_ani_apm() (0) -#endif - -#ifdef CONFIG_MACH_ELLA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELLA1 -# endif -# define machine_is_ella1() (machine_arch_type == MACH_TYPE_ELLA1) -#else -# define machine_is_ella1() (0) -#endif - -#ifdef CONFIG_MACH_INHAND_PXA27X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHAND_PXA27X -# endif -# define machine_is_inhand_pxa27x() (machine_arch_type == MACH_TYPE_INHAND_PXA27X) -#else -# define machine_is_inhand_pxa27x() (0) -#endif - -#ifdef CONFIG_MACH_INHAND_PXA25X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHAND_PXA25X -# endif -# define machine_is_inhand_pxa25x() (machine_arch_type == MACH_TYPE_INHAND_PXA25X) -#else -# define machine_is_inhand_pxa25x() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS_XM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS_XM -# endif -# define machine_is_empos_xm() (machine_arch_type == MACH_TYPE_EMPOS_XM) -#else -# define machine_is_empos_xm() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS -# endif -# define machine_is_empos() (machine_arch_type == MACH_TYPE_EMPOS) -#else -# define machine_is_empos() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS_TINY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS_TINY -# endif -# define machine_is_empos_tiny() (machine_arch_type == MACH_TYPE_EMPOS_TINY) -#else -# define machine_is_empos_tiny() (0) -#endif - -#ifdef CONFIG_MACH_EMPOS_SM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPOS_SM -# endif -# define machine_is_empos_sm() (machine_arch_type == MACH_TYPE_EMPOS_SM) -#else -# define machine_is_empos_sm() (0) -#endif - -#ifdef CONFIG_MACH_EGRET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EGRET -# endif -# define machine_is_egret() (machine_arch_type == MACH_TYPE_EGRET) -#else -# define machine_is_egret() (0) -#endif - -#ifdef CONFIG_MACH_OSTRICH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSTRICH -# endif -# define machine_is_ostrich() (machine_arch_type == MACH_TYPE_OSTRICH) -#else -# define machine_is_ostrich() (0) -#endif - -#ifdef CONFIG_MACH_N50 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N50 -# endif -# define machine_is_n50() (machine_arch_type == MACH_TYPE_N50) -#else -# define machine_is_n50() (0) -#endif - -#ifdef CONFIG_MACH_ECBAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECBAT91 -# endif -# define machine_is_ecbat91() (machine_arch_type == MACH_TYPE_ECBAT91) -#else -# define machine_is_ecbat91() (0) -#endif - -#ifdef CONFIG_MACH_STAREAST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAREAST -# endif -# define machine_is_stareast() (machine_arch_type == MACH_TYPE_STAREAST) -#else -# define machine_is_stareast() (0) -#endif - -#ifdef CONFIG_MACH_DSPG_DW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSPG_DW -# endif -# define machine_is_dspg_dw() (machine_arch_type == MACH_TYPE_DSPG_DW) -#else -# define machine_is_dspg_dw() (0) -#endif - -#ifdef CONFIG_MACH_ONEARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ONEARM -# endif -# define machine_is_onearm() (machine_arch_type == MACH_TYPE_ONEARM) -#else -# define machine_is_onearm() (0) -#endif - -#ifdef CONFIG_MACH_MRG110_6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MRG110_6 -# endif -# define machine_is_mrg110_6() (machine_arch_type == MACH_TYPE_MRG110_6) -#else -# define machine_is_mrg110_6() (0) -#endif - -#ifdef CONFIG_MACH_WRT300NV2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WRT300NV2 -# endif -# define machine_is_wrt300nv2() (machine_arch_type == MACH_TYPE_WRT300NV2) -#else -# define machine_is_wrt300nv2() (0) -#endif - -#ifdef CONFIG_MACH_XM_BULVERDE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XM_BULVERDE -# endif -# define machine_is_xm_bulverde() (machine_arch_type == MACH_TYPE_XM_BULVERDE) -#else -# define machine_is_xm_bulverde() (0) -#endif - -#ifdef CONFIG_MACH_MSM6100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM6100 -# endif -# define machine_is_msm6100() (machine_arch_type == MACH_TYPE_MSM6100) -#else -# define machine_is_msm6100() (0) -#endif - -#ifdef CONFIG_MACH_ETI_B1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETI_B1 -# endif -# define machine_is_eti_b1() (machine_arch_type == MACH_TYPE_ETI_B1) -#else -# define machine_is_eti_b1() (0) -#endif - -#ifdef CONFIG_MACH_ZILOG_ZA9L -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZILOG_ZA9L -# endif -# define machine_is_za9l_series() (machine_arch_type == MACH_TYPE_ZILOG_ZA9L) -#else -# define machine_is_za9l_series() (0) -#endif - -#ifdef CONFIG_MACH_BIT2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIT2440 -# endif -# define machine_is_bit2440() (machine_arch_type == MACH_TYPE_BIT2440) -#else -# define machine_is_bit2440() (0) -#endif - -#ifdef CONFIG_MACH_NBI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NBI -# endif -# define machine_is_nbi() (machine_arch_type == MACH_TYPE_NBI) -#else -# define machine_is_nbi() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2443 -# endif -# define machine_is_smdk2443() (machine_arch_type == MACH_TYPE_SMDK2443) -#else -# define machine_is_smdk2443() (0) -#endif - -#ifdef CONFIG_MACH_VDAVINCI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VDAVINCI -# endif -# define machine_is_vdavinci() (machine_arch_type == MACH_TYPE_VDAVINCI) -#else -# define machine_is_vdavinci() (0) -#endif - -#ifdef CONFIG_MACH_ATC6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATC6 -# endif -# define machine_is_atc6() (machine_arch_type == MACH_TYPE_ATC6) -#else -# define machine_is_atc6() (0) -#endif - -#ifdef CONFIG_MACH_MULTMDW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTMDW -# endif -# define machine_is_multmdw() (machine_arch_type == MACH_TYPE_MULTMDW) -#else -# define machine_is_multmdw() (0) -#endif - -#ifdef CONFIG_MACH_MBA2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MBA2440 -# endif -# define machine_is_mba2440() (machine_arch_type == MACH_TYPE_MBA2440) -#else -# define machine_is_mba2440() (0) -#endif - -#ifdef CONFIG_MACH_ECSD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECSD -# endif -# define machine_is_ecsd() (machine_arch_type == MACH_TYPE_ECSD) -#else -# define machine_is_ecsd() (0) -#endif - -#ifdef CONFIG_MACH_PALMZ31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMZ31 -# endif -# define machine_is_palmz31() (machine_arch_type == MACH_TYPE_PALMZ31) -#else -# define machine_is_palmz31() (0) -#endif - -#ifdef CONFIG_MACH_FSG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FSG -# endif -# define machine_is_fsg() (machine_arch_type == MACH_TYPE_FSG) -#else -# define machine_is_fsg() (0) -#endif - -#ifdef CONFIG_MACH_RAZOR101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAZOR101 -# endif -# define machine_is_razor101() (machine_arch_type == MACH_TYPE_RAZOR101) -#else -# define machine_is_razor101() (0) -#endif - -#ifdef CONFIG_MACH_OPERA_TDM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPERA_TDM -# endif -# define machine_is_opera_tdm() (machine_arch_type == MACH_TYPE_OPERA_TDM) -#else -# define machine_is_opera_tdm() (0) -#endif - -#ifdef CONFIG_MACH_COMCERTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMCERTO -# endif -# define machine_is_comcerto() (machine_arch_type == MACH_TYPE_COMCERTO) -#else -# define machine_is_comcerto() (0) -#endif - -#ifdef CONFIG_MACH_TB0319 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TB0319 -# endif -# define machine_is_tb0319() (machine_arch_type == MACH_TYPE_TB0319) -#else -# define machine_is_tb0319() (0) -#endif - -#ifdef CONFIG_MACH_KWS8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KWS8000 -# endif -# define machine_is_kws8000() (machine_arch_type == MACH_TYPE_KWS8000) -#else -# define machine_is_kws8000() (0) -#endif - -#ifdef CONFIG_MACH_B2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_B2 -# endif -# define machine_is_b2() (machine_arch_type == MACH_TYPE_B2) -#else -# define machine_is_b2() (0) -#endif - -#ifdef CONFIG_MACH_LCL54 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LCL54 -# endif -# define machine_is_lcl54() (machine_arch_type == MACH_TYPE_LCL54) -#else -# define machine_is_lcl54() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260EK -# endif -# define machine_is_at91sam9260ek() (machine_arch_type == MACH_TYPE_AT91SAM9260EK) -#else -# define machine_is_at91sam9260ek() (0) -#endif - -#ifdef CONFIG_MACH_GLANTANK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GLANTANK -# endif -# define machine_is_glantank() (machine_arch_type == MACH_TYPE_GLANTANK) -#else -# define machine_is_glantank() (0) -#endif - -#ifdef CONFIG_MACH_N2100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N2100 -# endif -# define machine_is_n2100() (machine_arch_type == MACH_TYPE_N2100) -#else -# define machine_is_n2100() (0) -#endif - -#ifdef CONFIG_MACH_N4100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N4100 -# endif -# define machine_is_n4100() (machine_arch_type == MACH_TYPE_N4100) -#else -# define machine_is_n4100() (0) -#endif - -#ifdef CONFIG_MACH_VERTICAL_RSC4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERTICAL_RSC4 -# endif -# define machine_is_rsc4() (machine_arch_type == MACH_TYPE_VERTICAL_RSC4) -#else -# define machine_is_rsc4() (0) -#endif - -#ifdef CONFIG_MACH_SG8100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG8100 -# endif -# define machine_is_sg8100() (machine_arch_type == MACH_TYPE_SG8100) -#else -# define machine_is_sg8100() (0) -#endif - -#ifdef CONFIG_MACH_IM42XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IM42XX -# endif -# define machine_is_im42xx() (machine_arch_type == MACH_TYPE_IM42XX) -#else -# define machine_is_im42xx() (0) -#endif - -#ifdef CONFIG_MACH_FTXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FTXX -# endif -# define machine_is_ftxx() (machine_arch_type == MACH_TYPE_FTXX) -#else -# define machine_is_ftxx() (0) -#endif - -#ifdef CONFIG_MACH_LWFUSION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LWFUSION -# endif -# define machine_is_lwfusion() (machine_arch_type == MACH_TYPE_LWFUSION) -#else -# define machine_is_lwfusion() (0) -#endif - -#ifdef CONFIG_MACH_QT2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QT2410 -# endif -# define machine_is_qt2410() (machine_arch_type == MACH_TYPE_QT2410) -#else -# define machine_is_qt2410() (0) -#endif - -#ifdef CONFIG_MACH_KIXRP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIXRP435 -# endif -# define machine_is_kixrp435() (machine_arch_type == MACH_TYPE_KIXRP435) -#else -# define machine_is_kixrp435() (0) -#endif - -#ifdef CONFIG_MACH_CCW9C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9C -# endif -# define machine_is_ccw9c() (machine_arch_type == MACH_TYPE_CCW9C) -#else -# define machine_is_ccw9c() (0) -#endif - -#ifdef CONFIG_MACH_DABHS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DABHS -# endif -# define machine_is_dabhs() (machine_arch_type == MACH_TYPE_DABHS) -#else -# define machine_is_dabhs() (0) -#endif - -#ifdef CONFIG_MACH_GZMX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GZMX -# endif -# define machine_is_gzmx() (machine_arch_type == MACH_TYPE_GZMX) -#else -# define machine_is_gzmx() (0) -#endif - -#ifdef CONFIG_MACH_IPNW100AP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPNW100AP -# endif -# define machine_is_ipnw100ap() (machine_arch_type == MACH_TYPE_IPNW100AP) -#else -# define machine_is_ipnw100ap() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360DEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360DEV -# endif -# define machine_is_cc9p9360dev() (machine_arch_type == MACH_TYPE_CC9P9360DEV) -#else -# define machine_is_cc9p9360dev() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9750DEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9750DEV -# endif -# define machine_is_cc9p9750dev() (machine_arch_type == MACH_TYPE_CC9P9750DEV) -#else -# define machine_is_cc9p9750dev() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360VAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360VAL -# endif -# define machine_is_cc9p9360val() (machine_arch_type == MACH_TYPE_CC9P9360VAL) -#else -# define machine_is_cc9p9360val() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9750VAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9750VAL -# endif -# define machine_is_cc9p9750val() (machine_arch_type == MACH_TYPE_CC9P9750VAL) -#else -# define machine_is_cc9p9750val() (0) -#endif - -#ifdef CONFIG_MACH_NX70V -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NX70V -# endif -# define machine_is_nx70v() (machine_arch_type == MACH_TYPE_NX70V) -#else -# define machine_is_nx70v() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200DF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200DF -# endif -# define machine_is_at91rm9200df() (machine_arch_type == MACH_TYPE_AT91RM9200DF) -#else -# define machine_is_at91rm9200df() (0) -#endif - -#ifdef CONFIG_MACH_SE_PILOT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE_PILOT2 -# endif -# define machine_is_se_pilot2() (machine_arch_type == MACH_TYPE_SE_PILOT2) -#else -# define machine_is_se_pilot2() (0) -#endif - -#ifdef CONFIG_MACH_MTCN_T800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MTCN_T800 -# endif -# define machine_is_mtcn_t800() (machine_arch_type == MACH_TYPE_MTCN_T800) -#else -# define machine_is_mtcn_t800() (0) -#endif - -#ifdef CONFIG_MACH_VCMX212 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCMX212 -# endif -# define machine_is_vcmx212() (machine_arch_type == MACH_TYPE_VCMX212) -#else -# define machine_is_vcmx212() (0) -#endif - -#ifdef CONFIG_MACH_LYNX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LYNX -# endif -# define machine_is_lynx() (machine_arch_type == MACH_TYPE_LYNX) -#else -# define machine_is_lynx() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260ID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260ID -# endif -# define machine_is_at91sam9260id() (machine_arch_type == MACH_TYPE_AT91SAM9260ID) -#else -# define machine_is_at91sam9260id() (0) -#endif - -#ifdef CONFIG_MACH_HW86052 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW86052 -# endif -# define machine_is_hw86052() (machine_arch_type == MACH_TYPE_HW86052) -#else -# define machine_is_hw86052() (0) -#endif - -#ifdef CONFIG_MACH_PILZ_PMI3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PILZ_PMI3 -# endif -# define machine_is_pilz_pmi3() (machine_arch_type == MACH_TYPE_PILZ_PMI3) -#else -# define machine_is_pilz_pmi3() (0) -#endif - -#ifdef CONFIG_MACH_EDB9302A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9302A -# endif -# define machine_is_edb9302a() (machine_arch_type == MACH_TYPE_EDB9302A) -#else -# define machine_is_edb9302a() (0) -#endif - -#ifdef CONFIG_MACH_EDB9307A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9307A -# endif -# define machine_is_edb9307a() (machine_arch_type == MACH_TYPE_EDB9307A) -#else -# define machine_is_edb9307a() (0) -#endif - -#ifdef CONFIG_MACH_CT_DFS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT_DFS -# endif -# define machine_is_ct_dfs() (machine_arch_type == MACH_TYPE_CT_DFS) -#else -# define machine_is_ct_dfs() (0) -#endif - -#ifdef CONFIG_MACH_PILZ_PMI4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PILZ_PMI4 -# endif -# define machine_is_pilz_pmi4() (machine_arch_type == MACH_TYPE_PILZ_PMI4) -#else -# define machine_is_pilz_pmi4() (0) -#endif - -#ifdef CONFIG_MACH_XCEEDNP_IXP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XCEEDNP_IXP -# endif -# define machine_is_xceednp_ixp() (machine_arch_type == MACH_TYPE_XCEEDNP_IXP) -#else -# define machine_is_xceednp_ixp() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2442B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2442B -# endif -# define machine_is_smdk2442b() (machine_arch_type == MACH_TYPE_SMDK2442B) -#else -# define machine_is_smdk2442b() (0) -#endif - -#ifdef CONFIG_MACH_XNODE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XNODE -# endif -# define machine_is_xnode() (machine_arch_type == MACH_TYPE_XNODE) -#else -# define machine_is_xnode() (0) -#endif - -#ifdef CONFIG_MACH_AIDX270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AIDX270 -# endif -# define machine_is_aidx270() (machine_arch_type == MACH_TYPE_AIDX270) -#else -# define machine_is_aidx270() (0) -#endif - -#ifdef CONFIG_MACH_REMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REMA -# endif -# define machine_is_rema() (machine_arch_type == MACH_TYPE_REMA) -#else -# define machine_is_rema() (0) -#endif - -#ifdef CONFIG_MACH_BPS1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BPS1000 -# endif -# define machine_is_bps1000() (machine_arch_type == MACH_TYPE_BPS1000) -#else -# define machine_is_bps1000() (0) -#endif - -#ifdef CONFIG_MACH_HW90350 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90350 -# endif -# define machine_is_hw90350() (machine_arch_type == MACH_TYPE_HW90350) -#else -# define machine_is_hw90350() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_3430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_3430SDP -# endif -# define machine_is_omap_3430sdp() (machine_arch_type == MACH_TYPE_OMAP_3430SDP) -#else -# define machine_is_omap_3430sdp() (0) -#endif - -#ifdef CONFIG_MACH_BLUETOUCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUETOUCH -# endif -# define machine_is_bluetouch() (machine_arch_type == MACH_TYPE_BLUETOUCH) -#else -# define machine_is_bluetouch() (0) -#endif - -#ifdef CONFIG_MACH_VSTMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VSTMS -# endif -# define machine_is_vstms() (machine_arch_type == MACH_TYPE_VSTMS) -#else -# define machine_is_vstms() (0) -#endif - -#ifdef CONFIG_MACH_XSBASE270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSBASE270 -# endif -# define machine_is_xsbase270() (machine_arch_type == MACH_TYPE_XSBASE270) -#else -# define machine_is_xsbase270() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260EK_CN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260EK_CN -# endif -# define machine_is_at91sam9260ek_cn() (machine_arch_type == MACH_TYPE_AT91SAM9260EK_CN) -#else -# define machine_is_at91sam9260ek_cn() (0) -#endif - -#ifdef CONFIG_MACH_ADSTURBOXB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSTURBOXB -# endif -# define machine_is_adsturboxb() (machine_arch_type == MACH_TYPE_ADSTURBOXB) -#else -# define machine_is_adsturboxb() (0) -#endif - -#ifdef CONFIG_MACH_OTI4110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTI4110 -# endif -# define machine_is_oti4110() (machine_arch_type == MACH_TYPE_OTI4110) -#else -# define machine_is_oti4110() (0) -#endif - -#ifdef CONFIG_MACH_HME_PXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HME_PXA -# endif -# define machine_is_hme_pxa() (machine_arch_type == MACH_TYPE_HME_PXA) -#else -# define machine_is_hme_pxa() (0) -#endif - -#ifdef CONFIG_MACH_DEISTERDCA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTERDCA -# endif -# define machine_is_deisterdca() (machine_arch_type == MACH_TYPE_DEISTERDCA) -#else -# define machine_is_deisterdca() (0) -#endif - -#ifdef CONFIG_MACH_CES_SSEM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CES_SSEM2 -# endif -# define machine_is_ces_ssem2() (machine_arch_type == MACH_TYPE_CES_SSEM2) -#else -# define machine_is_ces_ssem2() (0) -#endif - -#ifdef CONFIG_MACH_CES_MTR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CES_MTR -# endif -# define machine_is_ces_mtr() (machine_arch_type == MACH_TYPE_CES_MTR) -#else -# define machine_is_ces_mtr() (0) -#endif - -#ifdef CONFIG_MACH_TDS_AVNG_SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TDS_AVNG_SBC -# endif -# define machine_is_tds_avng_sbc() (machine_arch_type == MACH_TYPE_TDS_AVNG_SBC) -#else -# define machine_is_tds_avng_sbc() (0) -#endif - -#ifdef CONFIG_MACH_EVEREST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EVEREST -# endif -# define machine_is_everest() (machine_arch_type == MACH_TYPE_EVEREST) -#else -# define machine_is_everest() (0) -#endif - -#ifdef CONFIG_MACH_PNX4010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX4010 -# endif -# define machine_is_pnx4010() (machine_arch_type == MACH_TYPE_PNX4010) -#else -# define machine_is_pnx4010() (0) -#endif - -#ifdef CONFIG_MACH_OXNAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OXNAS -# endif -# define machine_is_oxnas() (machine_arch_type == MACH_TYPE_OXNAS) -#else -# define machine_is_oxnas() (0) -#endif - -#ifdef CONFIG_MACH_FIORI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FIORI -# endif -# define machine_is_fiori() (machine_arch_type == MACH_TYPE_FIORI) -#else -# define machine_is_fiori() (0) -#endif - -#ifdef CONFIG_MACH_ML1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML1200 -# endif -# define machine_is_ml1200() (machine_arch_type == MACH_TYPE_ML1200) -#else -# define machine_is_ml1200() (0) -#endif - -#ifdef CONFIG_MACH_PECOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PECOS -# endif -# define machine_is_pecos() (machine_arch_type == MACH_TYPE_PECOS) -#else -# define machine_is_pecos() (0) -#endif - -#ifdef CONFIG_MACH_NB2XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NB2XXX -# endif -# define machine_is_nb2xxx() (machine_arch_type == MACH_TYPE_NB2XXX) -#else -# define machine_is_nb2xxx() (0) -#endif - -#ifdef CONFIG_MACH_HW6900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW6900 -# endif -# define machine_is_hw6900() (machine_arch_type == MACH_TYPE_HW6900) -#else -# define machine_is_hw6900() (0) -#endif - -#ifdef CONFIG_MACH_CDCS_QUOLL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CDCS_QUOLL -# endif -# define machine_is_cdcs_quoll() (machine_arch_type == MACH_TYPE_CDCS_QUOLL) -#else -# define machine_is_cdcs_quoll() (0) -#endif - -#ifdef CONFIG_MACH_QUICKSILVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUICKSILVER -# endif -# define machine_is_quicksilver() (machine_arch_type == MACH_TYPE_QUICKSILVER) -#else -# define machine_is_quicksilver() (0) -#endif - -#ifdef CONFIG_MACH_UPLAT926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UPLAT926 -# endif -# define machine_is_uplat926() (machine_arch_type == MACH_TYPE_UPLAT926) -#else -# define machine_is_uplat926() (0) -#endif - -#ifdef CONFIG_MACH_DEP2410_THOMAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2410_THOMAS -# endif -# define machine_is_dep2410_dep2410() (machine_arch_type == MACH_TYPE_DEP2410_THOMAS) -#else -# define machine_is_dep2410_dep2410() (0) -#endif - -#ifdef CONFIG_MACH_DTK2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DTK2410 -# endif -# define machine_is_dtk2410() (machine_arch_type == MACH_TYPE_DTK2410) -#else -# define machine_is_dtk2410() (0) -#endif - -#ifdef CONFIG_MACH_CHILI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHILI -# endif -# define machine_is_chili() (machine_arch_type == MACH_TYPE_CHILI) -#else -# define machine_is_chili() (0) -#endif - -#ifdef CONFIG_MACH_DEMETER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEMETER -# endif -# define machine_is_demeter() (machine_arch_type == MACH_TYPE_DEMETER) -#else -# define machine_is_demeter() (0) -#endif - -#ifdef CONFIG_MACH_DIONYSUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIONYSUS -# endif -# define machine_is_dionysus() (machine_arch_type == MACH_TYPE_DIONYSUS) -#else -# define machine_is_dionysus() (0) -#endif - -#ifdef CONFIG_MACH_AS352X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AS352X -# endif -# define machine_is_as352x() (machine_arch_type == MACH_TYPE_AS352X) -#else -# define machine_is_as352x() (0) -#endif - -#ifdef CONFIG_MACH_SERVICE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SERVICE -# endif -# define machine_is_service() (machine_arch_type == MACH_TYPE_SERVICE) -#else -# define machine_is_service() (0) -#endif - -#ifdef CONFIG_MACH_CS_E9301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS_E9301 -# endif -# define machine_is_cs_e9301() (machine_arch_type == MACH_TYPE_CS_E9301) -#else -# define machine_is_cs_e9301() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9M -# endif -# define machine_is_micro9m() (machine_arch_type == MACH_TYPE_MICRO9M) -#else -# define machine_is_micro9m() (0) -#endif - -#ifdef CONFIG_MACH_IA_MOSPCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IA_MOSPCK -# endif -# define machine_is_ia_mospck() (machine_arch_type == MACH_TYPE_IA_MOSPCK) -#else -# define machine_is_ia_mospck() (0) -#endif - -#ifdef CONFIG_MACH_QL201B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QL201B -# endif -# define machine_is_ql201b() (machine_arch_type == MACH_TYPE_QL201B) -#else -# define machine_is_ql201b() (0) -#endif - -#ifdef CONFIG_MACH_BBM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BBM -# endif -# define machine_is_bbm() (machine_arch_type == MACH_TYPE_BBM) -#else -# define machine_is_bbm() (0) -#endif - -#ifdef CONFIG_MACH_EXXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXXX -# endif -# define machine_is_exxx() (machine_arch_type == MACH_TYPE_EXXX) -#else -# define machine_is_exxx() (0) -#endif - -#ifdef CONFIG_MACH_WMA11B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WMA11B -# endif -# define machine_is_wma11b() (machine_arch_type == MACH_TYPE_WMA11B) -#else -# define machine_is_wma11b() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ATLAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ATLAS -# endif -# define machine_is_pelco_atlas() (machine_arch_type == MACH_TYPE_PELCO_ATLAS) -#else -# define machine_is_pelco_atlas() (0) -#endif - -#ifdef CONFIG_MACH_G500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G500 -# endif -# define machine_is_g500() (machine_arch_type == MACH_TYPE_G500) -#else -# define machine_is_g500() (0) -#endif - -#ifdef CONFIG_MACH_BUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUG -# endif -# define machine_is_bug() (machine_arch_type == MACH_TYPE_BUG) -#else -# define machine_is_bug() (0) -#endif - -#ifdef CONFIG_MACH_MX33ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX33ADS -# endif -# define machine_is_mx33ads() (machine_arch_type == MACH_TYPE_MX33ADS) -#else -# define machine_is_mx33ads() (0) -#endif - -#ifdef CONFIG_MACH_CHUB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHUB -# endif -# define machine_is_chub() (machine_arch_type == MACH_TYPE_CHUB) -#else -# define machine_is_chub() (0) -#endif - -#ifdef CONFIG_MACH_NEO1973_GTA01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEO1973_GTA01 -# endif -# define machine_is_neo1973_gta01() (machine_arch_type == MACH_TYPE_NEO1973_GTA01) -#else -# define machine_is_neo1973_gta01() (0) -#endif - -#ifdef CONFIG_MACH_W90N740 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90N740 -# endif -# define machine_is_w90n740() (machine_arch_type == MACH_TYPE_W90N740) -#else -# define machine_is_w90n740() (0) -#endif - -#ifdef CONFIG_MACH_MEDALLION_SA2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEDALLION_SA2410 -# endif -# define machine_is_medallion_sa2410() (machine_arch_type == MACH_TYPE_MEDALLION_SA2410) -#else -# define machine_is_medallion_sa2410() (0) -#endif - -#ifdef CONFIG_MACH_IA_CPU_9200_2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IA_CPU_9200_2 -# endif -# define machine_is_ia_cpu_9200_2() (machine_arch_type == MACH_TYPE_IA_CPU_9200_2) -#else -# define machine_is_ia_cpu_9200_2() (0) -#endif - -#ifdef CONFIG_MACH_DIMMRM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIMMRM9200 -# endif -# define machine_is_dimmrm9200() (machine_arch_type == MACH_TYPE_DIMMRM9200) -#else -# define machine_is_dimmrm9200() (0) -#endif - -#ifdef CONFIG_MACH_PM9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM9261 -# endif -# define machine_is_pm9261() (machine_arch_type == MACH_TYPE_PM9261) -#else -# define machine_is_pm9261() (0) -#endif - -#ifdef CONFIG_MACH_ML7304 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ML7304 -# endif -# define machine_is_ml7304() (machine_arch_type == MACH_TYPE_ML7304) -#else -# define machine_is_ml7304() (0) -#endif - -#ifdef CONFIG_MACH_UCP250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCP250 -# endif -# define machine_is_ucp250() (machine_arch_type == MACH_TYPE_UCP250) -#else -# define machine_is_ucp250() (0) -#endif - -#ifdef CONFIG_MACH_INTBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTBOARD -# endif -# define machine_is_intboard() (machine_arch_type == MACH_TYPE_INTBOARD) -#else -# define machine_is_intboard() (0) -#endif - -#ifdef CONFIG_MACH_GULFSTREAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GULFSTREAM -# endif -# define machine_is_gulfstream() (machine_arch_type == MACH_TYPE_GULFSTREAM) -#else -# define machine_is_gulfstream() (0) -#endif - -#ifdef CONFIG_MACH_LABQUEST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LABQUEST -# endif -# define machine_is_labquest() (machine_arch_type == MACH_TYPE_LABQUEST) -#else -# define machine_is_labquest() (0) -#endif - -#ifdef CONFIG_MACH_VCMX313 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCMX313 -# endif -# define machine_is_vcmx313() (machine_arch_type == MACH_TYPE_VCMX313) -#else -# define machine_is_vcmx313() (0) -#endif - -#ifdef CONFIG_MACH_URG200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_URG200 -# endif -# define machine_is_urg200() (machine_arch_type == MACH_TYPE_URG200) -#else -# define machine_is_urg200() (0) -#endif - -#ifdef CONFIG_MACH_CPUX255LCDNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUX255LCDNET -# endif -# define machine_is_cpux255lcdnet() (machine_arch_type == MACH_TYPE_CPUX255LCDNET) -#else -# define machine_is_cpux255lcdnet() (0) -#endif - -#ifdef CONFIG_MACH_NETDCU9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETDCU9 -# endif -# define machine_is_netdcu9() (machine_arch_type == MACH_TYPE_NETDCU9) -#else -# define machine_is_netdcu9() (0) -#endif - -#ifdef CONFIG_MACH_NETDCU10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETDCU10 -# endif -# define machine_is_netdcu10() (machine_arch_type == MACH_TYPE_NETDCU10) -#else -# define machine_is_netdcu10() (0) -#endif - -#ifdef CONFIG_MACH_DSPG_DGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSPG_DGA -# endif -# define machine_is_dspg_dga() (machine_arch_type == MACH_TYPE_DSPG_DGA) -#else -# define machine_is_dspg_dga() (0) -#endif - -#ifdef CONFIG_MACH_DSPG_DVW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSPG_DVW -# endif -# define machine_is_dspg_dvw() (machine_arch_type == MACH_TYPE_DSPG_DVW) -#else -# define machine_is_dspg_dvw() (0) -#endif - -#ifdef CONFIG_MACH_SOLOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOLOS -# endif -# define machine_is_solos() (machine_arch_type == MACH_TYPE_SOLOS) -#else -# define machine_is_solos() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9263EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9263EK -# endif -# define machine_is_at91sam9263ek() (machine_arch_type == MACH_TYPE_AT91SAM9263EK) -#else -# define machine_is_at91sam9263ek() (0) -#endif - -#ifdef CONFIG_MACH_OSSTBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSSTBOX -# endif -# define machine_is_osstbox() (machine_arch_type == MACH_TYPE_OSSTBOX) -#else -# define machine_is_osstbox() (0) -#endif - -#ifdef CONFIG_MACH_KBAT9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KBAT9261 -# endif -# define machine_is_kbat9261() (machine_arch_type == MACH_TYPE_KBAT9261) -#else -# define machine_is_kbat9261() (0) -#endif - -#ifdef CONFIG_MACH_CT1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT1100 -# endif -# define machine_is_ct1100() (machine_arch_type == MACH_TYPE_CT1100) -#else -# define machine_is_ct1100() (0) -#endif - -#ifdef CONFIG_MACH_AKCPPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKCPPXA -# endif -# define machine_is_akcppxa() (machine_arch_type == MACH_TYPE_AKCPPXA) -#else -# define machine_is_akcppxa() (0) -#endif - -#ifdef CONFIG_MACH_OCHAYA1020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCHAYA1020 -# endif -# define machine_is_ochaya1020() (machine_arch_type == MACH_TYPE_OCHAYA1020) -#else -# define machine_is_ochaya1020() (0) -#endif - -#ifdef CONFIG_MACH_HITRACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HITRACK -# endif -# define machine_is_hitrack() (machine_arch_type == MACH_TYPE_HITRACK) -#else -# define machine_is_hitrack() (0) -#endif - -#ifdef CONFIG_MACH_SYME1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYME1 -# endif -# define machine_is_syme1() (machine_arch_type == MACH_TYPE_SYME1) -#else -# define machine_is_syme1() (0) -#endif - -#ifdef CONFIG_MACH_SYHL1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYHL1 -# endif -# define machine_is_syhl1() (machine_arch_type == MACH_TYPE_SYHL1) -#else -# define machine_is_syhl1() (0) -#endif - -#ifdef CONFIG_MACH_EMPCA400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMPCA400 -# endif -# define machine_is_empca400() (machine_arch_type == MACH_TYPE_EMPCA400) -#else -# define machine_is_empca400() (0) -#endif - -#ifdef CONFIG_MACH_EM7210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM7210 -# endif -# define machine_is_em7210() (machine_arch_type == MACH_TYPE_EM7210) -#else -# define machine_is_em7210() (0) -#endif - -#ifdef CONFIG_MACH_HTCHERMES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCHERMES -# endif -# define machine_is_htchermes() (machine_arch_type == MACH_TYPE_HTCHERMES) -#else -# define machine_is_htchermes() (0) -#endif - -#ifdef CONFIG_MACH_ETI_C1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETI_C1 -# endif -# define machine_is_eti_c1() (machine_arch_type == MACH_TYPE_ETI_C1) -#else -# define machine_is_eti_c1() (0) -#endif - -#ifdef CONFIG_MACH_AC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AC100 -# endif -# define machine_is_ac100() (machine_arch_type == MACH_TYPE_AC100) -#else -# define machine_is_ac100() (0) -#endif - -#ifdef CONFIG_MACH_SNEETCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNEETCH -# endif -# define machine_is_sneetch() (machine_arch_type == MACH_TYPE_SNEETCH) -#else -# define machine_is_sneetch() (0) -#endif - -#ifdef CONFIG_MACH_STUDENTMATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STUDENTMATE -# endif -# define machine_is_studentmate() (machine_arch_type == MACH_TYPE_STUDENTMATE) -#else -# define machine_is_studentmate() (0) -#endif - -#ifdef CONFIG_MACH_ZIR2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR2410 -# endif -# define machine_is_zir2410() (machine_arch_type == MACH_TYPE_ZIR2410) -#else -# define machine_is_zir2410() (0) -#endif - -#ifdef CONFIG_MACH_ZIR2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR2413 -# endif -# define machine_is_zir2413() (machine_arch_type == MACH_TYPE_ZIR2413) -#else -# define machine_is_zir2413() (0) -#endif - -#ifdef CONFIG_MACH_DLONIP3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DLONIP3 -# endif -# define machine_is_dlonip3() (machine_arch_type == MACH_TYPE_DLONIP3) -#else -# define machine_is_dlonip3() (0) -#endif - -#ifdef CONFIG_MACH_INSTREAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INSTREAM -# endif -# define machine_is_instream() (machine_arch_type == MACH_TYPE_INSTREAM) -#else -# define machine_is_instream() (0) -#endif - -#ifdef CONFIG_MACH_AMBARELLA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMBARELLA -# endif -# define machine_is_ambarella() (machine_arch_type == MACH_TYPE_AMBARELLA) -#else -# define machine_is_ambarella() (0) -#endif - -#ifdef CONFIG_MACH_NEVIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEVIS -# endif -# define machine_is_nevis() (machine_arch_type == MACH_TYPE_NEVIS) -#else -# define machine_is_nevis() (0) -#endif - -#ifdef CONFIG_MACH_HTC_TRINITY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_TRINITY -# endif -# define machine_is_htc_trinity() (machine_arch_type == MACH_TYPE_HTC_TRINITY) -#else -# define machine_is_htc_trinity() (0) -#endif - -#ifdef CONFIG_MACH_QL202B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QL202B -# endif -# define machine_is_ql202b() (machine_arch_type == MACH_TYPE_QL202B) -#else -# define machine_is_ql202b() (0) -#endif - -#ifdef CONFIG_MACH_VPAC270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VPAC270 -# endif -# define machine_is_vpac270() (machine_arch_type == MACH_TYPE_VPAC270) -#else -# define machine_is_vpac270() (0) -#endif - -#ifdef CONFIG_MACH_RD129 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD129 -# endif -# define machine_is_rd129() (machine_arch_type == MACH_TYPE_RD129) -#else -# define machine_is_rd129() (0) -#endif - -#ifdef CONFIG_MACH_HTCWIZARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCWIZARD -# endif -# define machine_is_htcwizard() (machine_arch_type == MACH_TYPE_HTCWIZARD) -#else -# define machine_is_htcwizard() (0) -#endif - -#ifdef CONFIG_MACH_TREO680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO680 -# endif -# define machine_is_treo680() (machine_arch_type == MACH_TYPE_TREO680) -#else -# define machine_is_treo680() (0) -#endif - -#ifdef CONFIG_MACH_TECON_TMEZON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TECON_TMEZON -# endif -# define machine_is_tecon_tmezon() (machine_arch_type == MACH_TYPE_TECON_TMEZON) -#else -# define machine_is_tecon_tmezon() (0) -#endif - -#ifdef CONFIG_MACH_ZYLONITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZYLONITE -# endif -# define machine_is_zylonite() (machine_arch_type == MACH_TYPE_ZYLONITE) -#else -# define machine_is_zylonite() (0) -#endif - -#ifdef CONFIG_MACH_GENE1270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GENE1270 -# endif -# define machine_is_gene1270() (machine_arch_type == MACH_TYPE_GENE1270) -#else -# define machine_is_gene1270() (0) -#endif - -#ifdef CONFIG_MACH_ZIR2412 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR2412 -# endif -# define machine_is_zir2412() (machine_arch_type == MACH_TYPE_ZIR2412) -#else -# define machine_is_zir2412() (0) -#endif - -#ifdef CONFIG_MACH_MX31LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31LITE -# endif -# define machine_is_mx31lite() (machine_arch_type == MACH_TYPE_MX31LITE) -#else -# define machine_is_mx31lite() (0) -#endif - -#ifdef CONFIG_MACH_T700WX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T700WX -# endif -# define machine_is_t700wx() (machine_arch_type == MACH_TYPE_T700WX) -#else -# define machine_is_t700wx() (0) -#endif - -#ifdef CONFIG_MACH_VF100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VF100 -# endif -# define machine_is_vf100() (machine_arch_type == MACH_TYPE_VF100) -#else -# define machine_is_vf100() (0) -#endif - -#ifdef CONFIG_MACH_NSB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB2 -# endif -# define machine_is_nsb2() (machine_arch_type == MACH_TYPE_NSB2) -#else -# define machine_is_nsb2() (0) -#endif - -#ifdef CONFIG_MACH_NXHMI_BB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXHMI_BB -# endif -# define machine_is_nxhmi_bb() (machine_arch_type == MACH_TYPE_NXHMI_BB) -#else -# define machine_is_nxhmi_bb() (0) -#endif - -#ifdef CONFIG_MACH_NXHMI_RE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXHMI_RE -# endif -# define machine_is_nxhmi_re() (machine_arch_type == MACH_TYPE_NXHMI_RE) -#else -# define machine_is_nxhmi_re() (0) -#endif - -#ifdef CONFIG_MACH_N4100PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N4100PRO -# endif -# define machine_is_n4100pro() (machine_arch_type == MACH_TYPE_N4100PRO) -#else -# define machine_is_n4100pro() (0) -#endif - -#ifdef CONFIG_MACH_SAM9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9260 -# endif -# define machine_is_sam9260() (machine_arch_type == MACH_TYPE_SAM9260) -#else -# define machine_is_sam9260() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_TREO600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_TREO600 -# endif -# define machine_is_omap_treo600() (machine_arch_type == MACH_TYPE_OMAP_TREO600) -#else -# define machine_is_omap_treo600() (0) -#endif - -#ifdef CONFIG_MACH_INDY2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INDY2410 -# endif -# define machine_is_indy2410() (machine_arch_type == MACH_TYPE_INDY2410) -#else -# define machine_is_indy2410() (0) -#endif - -#ifdef CONFIG_MACH_NELT_A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NELT_A -# endif -# define machine_is_nelt_a() (machine_arch_type == MACH_TYPE_NELT_A) -#else -# define machine_is_nelt_a() (0) -#endif - -#ifdef CONFIG_MACH_N311 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N311 -# endif -# define machine_is_n311() (machine_arch_type == MACH_TYPE_N311) -#else -# define machine_is_n311() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260VGK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260VGK -# endif -# define machine_is_at91sam9260vgk() (machine_arch_type == MACH_TYPE_AT91SAM9260VGK) -#else -# define machine_is_at91sam9260vgk() (0) -#endif - -#ifdef CONFIG_MACH_AT91LEPPE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91LEPPE -# endif -# define machine_is_at91leppe() (machine_arch_type == MACH_TYPE_AT91LEPPE) -#else -# define machine_is_at91leppe() (0) -#endif - -#ifdef CONFIG_MACH_AT91LEPCCN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91LEPCCN -# endif -# define machine_is_at91lepccn() (machine_arch_type == MACH_TYPE_AT91LEPCCN) -#else -# define machine_is_at91lepccn() (0) -#endif - -#ifdef CONFIG_MACH_APC7100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APC7100 -# endif -# define machine_is_apc7100() (machine_arch_type == MACH_TYPE_APC7100) -#else -# define machine_is_apc7100() (0) -#endif - -#ifdef CONFIG_MACH_STARGAZER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGAZER -# endif -# define machine_is_stargazer() (machine_arch_type == MACH_TYPE_STARGAZER) -#else -# define machine_is_stargazer() (0) -#endif - -#ifdef CONFIG_MACH_SONATA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONATA -# endif -# define machine_is_sonata() (machine_arch_type == MACH_TYPE_SONATA) -#else -# define machine_is_sonata() (0) -#endif - -#ifdef CONFIG_MACH_SCHMOOGIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCHMOOGIE -# endif -# define machine_is_schmoogie() (machine_arch_type == MACH_TYPE_SCHMOOGIE) -#else -# define machine_is_schmoogie() (0) -#endif - -#ifdef CONFIG_MACH_AZTOOL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AZTOOL -# endif -# define machine_is_aztool() (machine_arch_type == MACH_TYPE_AZTOOL) -#else -# define machine_is_aztool() (0) -#endif - -#ifdef CONFIG_MACH_MIOA701 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIOA701 -# endif -# define machine_is_mioa701() (machine_arch_type == MACH_TYPE_MIOA701) -#else -# define machine_is_mioa701() (0) -#endif - -#ifdef CONFIG_MACH_SXNI9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SXNI9260 -# endif -# define machine_is_sxni9260() (machine_arch_type == MACH_TYPE_SXNI9260) -#else -# define machine_is_sxni9260() (0) -#endif - -#ifdef CONFIG_MACH_MXC27520EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC27520EVB -# endif -# define machine_is_mxc27520evb() (machine_arch_type == MACH_TYPE_MXC27520EVB) -#else -# define machine_is_mxc27520evb() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO5X0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO5X0 -# endif -# define machine_is_armadillo5x0() (machine_arch_type == MACH_TYPE_ARMADILLO5X0) -#else -# define machine_is_armadillo5x0() (0) -#endif - -#ifdef CONFIG_MACH_MB9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9260 -# endif -# define machine_is_mb9260() (machine_arch_type == MACH_TYPE_MB9260) -#else -# define machine_is_mb9260() (0) -#endif - -#ifdef CONFIG_MACH_MB9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9263 -# endif -# define machine_is_mb9263() (machine_arch_type == MACH_TYPE_MB9263) -#else -# define machine_is_mb9263() (0) -#endif - -#ifdef CONFIG_MACH_IPAC9302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPAC9302 -# endif -# define machine_is_ipac9302() (machine_arch_type == MACH_TYPE_IPAC9302) -#else -# define machine_is_ipac9302() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360JS -# endif -# define machine_is_cc9p9360js() (machine_arch_type == MACH_TYPE_CC9P9360JS) -#else -# define machine_is_cc9p9360js() (0) -#endif - -#ifdef CONFIG_MACH_GALLIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GALLIUM -# endif -# define machine_is_gallium() (machine_arch_type == MACH_TYPE_GALLIUM) -#else -# define machine_is_gallium() (0) -#endif - -#ifdef CONFIG_MACH_MSC2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSC2410 -# endif -# define machine_is_msc2410() (machine_arch_type == MACH_TYPE_MSC2410) -#else -# define machine_is_msc2410() (0) -#endif - -#ifdef CONFIG_MACH_GHI270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GHI270 -# endif -# define machine_is_ghi270() (machine_arch_type == MACH_TYPE_GHI270) -#else -# define machine_is_ghi270() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_LEONARDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_LEONARDO -# endif -# define machine_is_davinci_leonardo() (machine_arch_type == MACH_TYPE_DAVINCI_LEONARDO) -#else -# define machine_is_davinci_leonardo() (0) -#endif - -#ifdef CONFIG_MACH_OIAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OIAB -# endif -# define machine_is_oiab() (machine_arch_type == MACH_TYPE_OIAB) -#else -# define machine_is_oiab() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6400 -# endif -# define machine_is_smdk6400() (machine_arch_type == MACH_TYPE_SMDK6400) -#else -# define machine_is_smdk6400() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N800 -# endif -# define machine_is_nokia_n800() (machine_arch_type == MACH_TYPE_NOKIA_N800) -#else -# define machine_is_nokia_n800() (0) -#endif - -#ifdef CONFIG_MACH_GREENPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GREENPHONE -# endif -# define machine_is_greenphone() (machine_arch_type == MACH_TYPE_GREENPHONE) -#else -# define machine_is_greenphone() (0) -#endif - -#ifdef CONFIG_MACH_COMPEXWP18 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMPEXWP18 -# endif -# define machine_is_compex42x() (machine_arch_type == MACH_TYPE_COMPEXWP18) -#else -# define machine_is_compex42x() (0) -#endif - -#ifdef CONFIG_MACH_XMATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XMATE -# endif -# define machine_is_xmate() (machine_arch_type == MACH_TYPE_XMATE) -#else -# define machine_is_xmate() (0) -#endif - -#ifdef CONFIG_MACH_ENERGIZER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENERGIZER -# endif -# define machine_is_energizer() (machine_arch_type == MACH_TYPE_ENERGIZER) -#else -# define machine_is_energizer() (0) -#endif - -#ifdef CONFIG_MACH_IME1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IME1 -# endif -# define machine_is_ime1() (machine_arch_type == MACH_TYPE_IME1) -#else -# define machine_is_ime1() (0) -#endif - -#ifdef CONFIG_MACH_SWEDATMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWEDATMS -# endif -# define machine_is_sweda_tms() (machine_arch_type == MACH_TYPE_SWEDATMS) -#else -# define machine_is_sweda_tms() (0) -#endif - -#ifdef CONFIG_MACH_NTNP435C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NTNP435C -# endif -# define machine_is_ntnp435c() (machine_arch_type == MACH_TYPE_NTNP435C) -#else -# define machine_is_ntnp435c() (0) -#endif - -#ifdef CONFIG_MACH_SPECTRO2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPECTRO2 -# endif -# define machine_is_spectro2() (machine_arch_type == MACH_TYPE_SPECTRO2) -#else -# define machine_is_spectro2() (0) -#endif - -#ifdef CONFIG_MACH_H6039 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6039 -# endif -# define machine_is_h6039() (machine_arch_type == MACH_TYPE_H6039) -#else -# define machine_is_h6039() (0) -#endif - -#ifdef CONFIG_MACH_EP80219 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EP80219 -# endif -# define machine_is_ep80219() (machine_arch_type == MACH_TYPE_EP80219) -#else -# define machine_is_ep80219() (0) -#endif - -#ifdef CONFIG_MACH_SAMOA_II -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAMOA_II -# endif -# define machine_is_samoa_ii() (machine_arch_type == MACH_TYPE_SAMOA_II) -#else -# define machine_is_samoa_ii() (0) -#endif - -#ifdef CONFIG_MACH_CWMXL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWMXL -# endif -# define machine_is_cwmxl() (machine_arch_type == MACH_TYPE_CWMXL) -#else -# define machine_is_cwmxl() (0) -#endif - -#ifdef CONFIG_MACH_AS9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AS9200 -# endif -# define machine_is_as9200() (machine_arch_type == MACH_TYPE_AS9200) -#else -# define machine_is_as9200() (0) -#endif - -#ifdef CONFIG_MACH_SFX1149 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SFX1149 -# endif -# define machine_is_sfx1149() (machine_arch_type == MACH_TYPE_SFX1149) -#else -# define machine_is_sfx1149() (0) -#endif - -#ifdef CONFIG_MACH_NAVI010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAVI010 -# endif -# define machine_is_navi010() (machine_arch_type == MACH_TYPE_NAVI010) -#else -# define machine_is_navi010() (0) -#endif - -#ifdef CONFIG_MACH_MULTMDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTMDP -# endif -# define machine_is_multmdp() (machine_arch_type == MACH_TYPE_MULTMDP) -#else -# define machine_is_multmdp() (0) -#endif - -#ifdef CONFIG_MACH_SCB9520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCB9520 -# endif -# define machine_is_scb9520() (machine_arch_type == MACH_TYPE_SCB9520) -#else -# define machine_is_scb9520() (0) -#endif - -#ifdef CONFIG_MACH_HTCATHENA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCATHENA -# endif -# define machine_is_htcathena() (machine_arch_type == MACH_TYPE_HTCATHENA) -#else -# define machine_is_htcathena() (0) -#endif - -#ifdef CONFIG_MACH_XP179 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP179 -# endif -# define machine_is_xp179() (machine_arch_type == MACH_TYPE_XP179) -#else -# define machine_is_xp179() (0) -#endif - -#ifdef CONFIG_MACH_H4300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H4300 -# endif -# define machine_is_h4300() (machine_arch_type == MACH_TYPE_H4300) -#else -# define machine_is_h4300() (0) -#endif - -#ifdef CONFIG_MACH_GORAMO_MLR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GORAMO_MLR -# endif -# define machine_is_goramo_mlr() (machine_arch_type == MACH_TYPE_GORAMO_MLR) -#else -# define machine_is_goramo_mlr() (0) -#endif - -#ifdef CONFIG_MACH_MXC30020EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30020EVB -# endif -# define machine_is_mxc30020evb() (machine_arch_type == MACH_TYPE_MXC30020EVB) -#else -# define machine_is_mxc30020evb() (0) -#endif - -#ifdef CONFIG_MACH_ADSBITSYG5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSYG5 -# endif -# define machine_is_adsbitsyg5() (machine_arch_type == MACH_TYPE_ADSBITSYG5) -#else -# define machine_is_adsbitsyg5() (0) -#endif - -#ifdef CONFIG_MACH_ADSPORTALPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSPORTALPLUS -# endif -# define machine_is_adsportalplus() (machine_arch_type == MACH_TYPE_ADSPORTALPLUS) -#else -# define machine_is_adsportalplus() (0) -#endif - -#ifdef CONFIG_MACH_MMSP2PLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMSP2PLUS -# endif -# define machine_is_mmsp2plus() (machine_arch_type == MACH_TYPE_MMSP2PLUS) -#else -# define machine_is_mmsp2plus() (0) -#endif - -#ifdef CONFIG_MACH_EM_X270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM_X270 -# endif -# define machine_is_em_x270() (machine_arch_type == MACH_TYPE_EM_X270) -#else -# define machine_is_em_x270() (0) -#endif - -#ifdef CONFIG_MACH_TPP302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPP302 -# endif -# define machine_is_tpp302() (machine_arch_type == MACH_TYPE_TPP302) -#else -# define machine_is_tpp302() (0) -#endif - -#ifdef CONFIG_MACH_TPM104 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPM104 -# endif -# define machine_is_tpp104() (machine_arch_type == MACH_TYPE_TPM104) -#else -# define machine_is_tpp104() (0) -#endif - -#ifdef CONFIG_MACH_TPM102 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPM102 -# endif -# define machine_is_tpm102() (machine_arch_type == MACH_TYPE_TPM102) -#else -# define machine_is_tpm102() (0) -#endif - -#ifdef CONFIG_MACH_TPM109 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPM109 -# endif -# define machine_is_tpm109() (machine_arch_type == MACH_TYPE_TPM109) -#else -# define machine_is_tpm109() (0) -#endif - -#ifdef CONFIG_MACH_FBXO1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FBXO1 -# endif -# define machine_is_fbxo1() (machine_arch_type == MACH_TYPE_FBXO1) -#else -# define machine_is_fbxo1() (0) -#endif - -#ifdef CONFIG_MACH_HXD8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HXD8 -# endif -# define machine_is_hxd8() (machine_arch_type == MACH_TYPE_HXD8) -#else -# define machine_is_hxd8() (0) -#endif - -#ifdef CONFIG_MACH_NEO1973_GTA02 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEO1973_GTA02 -# endif -# define machine_is_neo1973_gta02() (machine_arch_type == MACH_TYPE_NEO1973_GTA02) -#else -# define machine_is_neo1973_gta02() (0) -#endif - -#ifdef CONFIG_MACH_EMTEST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMTEST -# endif -# define machine_is_emtest() (machine_arch_type == MACH_TYPE_EMTEST) -#else -# define machine_is_emtest() (0) -#endif - -#ifdef CONFIG_MACH_AD6900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AD6900 -# endif -# define machine_is_ad6900() (machine_arch_type == MACH_TYPE_AD6900) -#else -# define machine_is_ad6900() (0) -#endif - -#ifdef CONFIG_MACH_EUROPA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EUROPA -# endif -# define machine_is_europa() (machine_arch_type == MACH_TYPE_EUROPA) -#else -# define machine_is_europa() (0) -#endif - -#ifdef CONFIG_MACH_METROCONNECT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_METROCONNECT -# endif -# define machine_is_metroconnect() (machine_arch_type == MACH_TYPE_METROCONNECT) -#else -# define machine_is_metroconnect() (0) -#endif - -#ifdef CONFIG_MACH_EZ_S2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_S2410 -# endif -# define machine_is_ez_s2410() (machine_arch_type == MACH_TYPE_EZ_S2410) -#else -# define machine_is_ez_s2410() (0) -#endif - -#ifdef CONFIG_MACH_EZ_S2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_S2440 -# endif -# define machine_is_ez_s2440() (machine_arch_type == MACH_TYPE_EZ_S2440) -#else -# define machine_is_ez_s2440() (0) -#endif - -#ifdef CONFIG_MACH_EZ_EP9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_EP9312 -# endif -# define machine_is_ez_ep9312() (machine_arch_type == MACH_TYPE_EZ_EP9312) -#else -# define machine_is_ez_ep9312() (0) -#endif - -#ifdef CONFIG_MACH_EZ_EP9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_EP9315 -# endif -# define machine_is_ez_ep9315() (machine_arch_type == MACH_TYPE_EZ_EP9315) -#else -# define machine_is_ez_ep9315() (0) -#endif - -#ifdef CONFIG_MACH_EZ_X7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZ_X7 -# endif -# define machine_is_ez_x7() (machine_arch_type == MACH_TYPE_EZ_X7) -#else -# define machine_is_ez_x7() (0) -#endif - -#ifdef CONFIG_MACH_GODOTDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GODOTDB -# endif -# define machine_is_godotdb() (machine_arch_type == MACH_TYPE_GODOTDB) -#else -# define machine_is_godotdb() (0) -#endif - -#ifdef CONFIG_MACH_MISTRAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MISTRAL -# endif -# define machine_is_mistral() (machine_arch_type == MACH_TYPE_MISTRAL) -#else -# define machine_is_mistral() (0) -#endif - -#ifdef CONFIG_MACH_MSM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM -# endif -# define machine_is_msm() (machine_arch_type == MACH_TYPE_MSM) -#else -# define machine_is_msm() (0) -#endif - -#ifdef CONFIG_MACH_CT5910 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT5910 -# endif -# define machine_is_ct5910() (machine_arch_type == MACH_TYPE_CT5910) -#else -# define machine_is_ct5910() (0) -#endif - -#ifdef CONFIG_MACH_CT5912 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CT5912 -# endif -# define machine_is_ct5912() (machine_arch_type == MACH_TYPE_CT5912) -#else -# define machine_is_ct5912() (0) -#endif - -#ifdef CONFIG_MACH_HYNET_INE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HYNET_INE -# endif -# define machine_is_hynet_ine() (machine_arch_type == MACH_TYPE_HYNET_INE) -#else -# define machine_is_hynet_ine() (0) -#endif - -#ifdef CONFIG_MACH_HYNET_APP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HYNET_APP -# endif -# define machine_is_hynet_app() (machine_arch_type == MACH_TYPE_HYNET_APP) -#else -# define machine_is_hynet_app() (0) -#endif - -#ifdef CONFIG_MACH_MSM7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7200 -# endif -# define machine_is_msm7200() (machine_arch_type == MACH_TYPE_MSM7200) -#else -# define machine_is_msm7200() (0) -#endif - -#ifdef CONFIG_MACH_MSM7600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7600 -# endif -# define machine_is_msm7600() (machine_arch_type == MACH_TYPE_MSM7600) -#else -# define machine_is_msm7600() (0) -#endif - -#ifdef CONFIG_MACH_CEB255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEB255 -# endif -# define machine_is_ceb255() (machine_arch_type == MACH_TYPE_CEB255) -#else -# define machine_is_ceb255() (0) -#endif - -#ifdef CONFIG_MACH_CIEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CIEL -# endif -# define machine_is_ciel() (machine_arch_type == MACH_TYPE_CIEL) -#else -# define machine_is_ciel() (0) -#endif - -#ifdef CONFIG_MACH_SLM5650 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SLM5650 -# endif -# define machine_is_slm5650() (machine_arch_type == MACH_TYPE_SLM5650) -#else -# define machine_is_slm5650() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9RLEK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9RLEK -# endif -# define machine_is_at91sam9rlek() (machine_arch_type == MACH_TYPE_AT91SAM9RLEK) -#else -# define machine_is_at91sam9rlek() (0) -#endif - -#ifdef CONFIG_MACH_COMTECH_ROUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMTECH_ROUTER -# endif -# define machine_is_comtech_router() (machine_arch_type == MACH_TYPE_COMTECH_ROUTER) -#else -# define machine_is_comtech_router() (0) -#endif - -#ifdef CONFIG_MACH_SBC2410X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2410X -# endif -# define machine_is_sbc2410x() (machine_arch_type == MACH_TYPE_SBC2410X) -#else -# define machine_is_sbc2410x() (0) -#endif - -#ifdef CONFIG_MACH_AT4X0BD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT4X0BD -# endif -# define machine_is_at4x0bd() (machine_arch_type == MACH_TYPE_AT4X0BD) -#else -# define machine_is_at4x0bd() (0) -#endif - -#ifdef CONFIG_MACH_CBIFR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CBIFR -# endif -# define machine_is_cbifr() (machine_arch_type == MACH_TYPE_CBIFR) -#else -# define machine_is_cbifr() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_QUANTUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_QUANTUM -# endif -# define machine_is_arcom_quantum() (machine_arch_type == MACH_TYPE_ARCOM_QUANTUM) -#else -# define machine_is_arcom_quantum() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX520 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX520 -# endif -# define machine_is_matrix520() (machine_arch_type == MACH_TYPE_MATRIX520) -#else -# define machine_is_matrix520() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX510 -# endif -# define machine_is_matrix510() (machine_arch_type == MACH_TYPE_MATRIX510) -#else -# define machine_is_matrix510() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX500 -# endif -# define machine_is_matrix500() (machine_arch_type == MACH_TYPE_MATRIX500) -#else -# define machine_is_matrix500() (0) -#endif - -#ifdef CONFIG_MACH_M501 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M501 -# endif -# define machine_is_m501() (machine_arch_type == MACH_TYPE_M501) -#else -# define machine_is_m501() (0) -#endif - -#ifdef CONFIG_MACH_AAEON1270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AAEON1270 -# endif -# define machine_is_aaeon1270() (machine_arch_type == MACH_TYPE_AAEON1270) -#else -# define machine_is_aaeon1270() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX500EV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX500EV -# endif -# define machine_is_matrix500ev() (machine_arch_type == MACH_TYPE_MATRIX500EV) -#else -# define machine_is_matrix500ev() (0) -#endif - -#ifdef CONFIG_MACH_PAC500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PAC500 -# endif -# define machine_is_pac500() (machine_arch_type == MACH_TYPE_PAC500) -#else -# define machine_is_pac500() (0) -#endif - -#ifdef CONFIG_MACH_PNX8181 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX8181 -# endif -# define machine_is_pnx8181() (machine_arch_type == MACH_TYPE_PNX8181) -#else -# define machine_is_pnx8181() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI320 -# endif -# define machine_is_colibri320() (machine_arch_type == MACH_TYPE_COLIBRI320) -#else -# define machine_is_colibri320() (0) -#endif - -#ifdef CONFIG_MACH_AZTOOLBB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AZTOOLBB -# endif -# define machine_is_aztoolbb() (machine_arch_type == MACH_TYPE_AZTOOLBB) -#else -# define machine_is_aztoolbb() (0) -#endif - -#ifdef CONFIG_MACH_AZTOOLG2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AZTOOLG2 -# endif -# define machine_is_aztoolg2() (machine_arch_type == MACH_TYPE_AZTOOLG2) -#else -# define machine_is_aztoolg2() (0) -#endif - -#ifdef CONFIG_MACH_DVLHOST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DVLHOST -# endif -# define machine_is_dvlhost() (machine_arch_type == MACH_TYPE_DVLHOST) -#else -# define machine_is_dvlhost() (0) -#endif - -#ifdef CONFIG_MACH_ZIR9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR9200 -# endif -# define machine_is_zir9200() (machine_arch_type == MACH_TYPE_ZIR9200) -#else -# define machine_is_zir9200() (0) -#endif - -#ifdef CONFIG_MACH_ZIR9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIR9260 -# endif -# define machine_is_zir9260() (machine_arch_type == MACH_TYPE_ZIR9260) -#else -# define machine_is_zir9260() (0) -#endif - -#ifdef CONFIG_MACH_COCOPAH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COCOPAH -# endif -# define machine_is_cocopah() (machine_arch_type == MACH_TYPE_COCOPAH) -#else -# define machine_is_cocopah() (0) -#endif - -#ifdef CONFIG_MACH_NDS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NDS -# endif -# define machine_is_nds() (machine_arch_type == MACH_TYPE_NDS) -#else -# define machine_is_nds() (0) -#endif - -#ifdef CONFIG_MACH_ROSENCRANTZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROSENCRANTZ -# endif -# define machine_is_rosencrantz() (machine_arch_type == MACH_TYPE_ROSENCRANTZ) -#else -# define machine_is_rosencrantz() (0) -#endif - -#ifdef CONFIG_MACH_FTTX_ODSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FTTX_ODSC -# endif -# define machine_is_fttx_odsc() (machine_arch_type == MACH_TYPE_FTTX_ODSC) -#else -# define machine_is_fttx_odsc() (0) -#endif - -#ifdef CONFIG_MACH_CLASSE_R6904 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLASSE_R6904 -# endif -# define machine_is_classe_r6904() (machine_arch_type == MACH_TYPE_CLASSE_R6904) -#else -# define machine_is_classe_r6904() (0) -#endif - -#ifdef CONFIG_MACH_CAM60 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAM60 -# endif -# define machine_is_cam60() (machine_arch_type == MACH_TYPE_CAM60) -#else -# define machine_is_cam60() (0) -#endif - -#ifdef CONFIG_MACH_MXC30031ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30031ADS -# endif -# define machine_is_mxc30031ads() (machine_arch_type == MACH_TYPE_MXC30031ADS) -#else -# define machine_is_mxc30031ads() (0) -#endif - -#ifdef CONFIG_MACH_DATACALL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DATACALL -# endif -# define machine_is_datacall() (machine_arch_type == MACH_TYPE_DATACALL) -#else -# define machine_is_datacall() (0) -#endif - -#ifdef CONFIG_MACH_AT91EB01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91EB01 -# endif -# define machine_is_at91eb01() (machine_arch_type == MACH_TYPE_AT91EB01) -#else -# define machine_is_at91eb01() (0) -#endif - -#ifdef CONFIG_MACH_RTY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RTY -# endif -# define machine_is_rty() (machine_arch_type == MACH_TYPE_RTY) -#else -# define machine_is_rty() (0) -#endif - -#ifdef CONFIG_MACH_DWL2100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DWL2100 -# endif -# define machine_is_dwl2100() (machine_arch_type == MACH_TYPE_DWL2100) -#else -# define machine_is_dwl2100() (0) -#endif - -#ifdef CONFIG_MACH_VINSI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VINSI -# endif -# define machine_is_vinsi() (machine_arch_type == MACH_TYPE_VINSI) -#else -# define machine_is_vinsi() (0) -#endif - -#ifdef CONFIG_MACH_DB88F5281 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB88F5281 -# endif -# define machine_is_db88f5281() (machine_arch_type == MACH_TYPE_DB88F5281) -#else -# define machine_is_db88f5281() (0) -#endif - -#ifdef CONFIG_MACH_CSB726 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB726 -# endif -# define machine_is_csb726() (machine_arch_type == MACH_TYPE_CSB726) -#else -# define machine_is_csb726() (0) -#endif - -#ifdef CONFIG_MACH_TIK27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIK27 -# endif -# define machine_is_tik27() (machine_arch_type == MACH_TYPE_TIK27) -#else -# define machine_is_tik27() (0) -#endif - -#ifdef CONFIG_MACH_MX_UC7420 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX_UC7420 -# endif -# define machine_is_mx_uc7420() (machine_arch_type == MACH_TYPE_MX_UC7420) -#else -# define machine_is_mx_uc7420() (0) -#endif - -#ifdef CONFIG_MACH_RIRM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIRM3 -# endif -# define machine_is_rirm3() (machine_arch_type == MACH_TYPE_RIRM3) -#else -# define machine_is_rirm3() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ODYSSEY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ODYSSEY -# endif -# define machine_is_pelco_odyssey() (machine_arch_type == MACH_TYPE_PELCO_ODYSSEY) -#else -# define machine_is_pelco_odyssey() (0) -#endif - -#ifdef CONFIG_MACH_ADX_ABOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_ABOX -# endif -# define machine_is_adx_abox() (machine_arch_type == MACH_TYPE_ADX_ABOX) -#else -# define machine_is_adx_abox() (0) -#endif - -#ifdef CONFIG_MACH_ADX_TPID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_TPID -# endif -# define machine_is_adx_tpid() (machine_arch_type == MACH_TYPE_ADX_TPID) -#else -# define machine_is_adx_tpid() (0) -#endif - -#ifdef CONFIG_MACH_MINICHECK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINICHECK -# endif -# define machine_is_minicheck() (machine_arch_type == MACH_TYPE_MINICHECK) -#else -# define machine_is_minicheck() (0) -#endif - -#ifdef CONFIG_MACH_IDAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IDAM -# endif -# define machine_is_idam() (machine_arch_type == MACH_TYPE_IDAM) -#else -# define machine_is_idam() (0) -#endif - -#ifdef CONFIG_MACH_MARIO_MX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARIO_MX -# endif -# define machine_is_mario_mx() (machine_arch_type == MACH_TYPE_MARIO_MX) -#else -# define machine_is_mario_mx() (0) -#endif - -#ifdef CONFIG_MACH_VI1888 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VI1888 -# endif -# define machine_is_vi1888() (machine_arch_type == MACH_TYPE_VI1888) -#else -# define machine_is_vi1888() (0) -#endif - -#ifdef CONFIG_MACH_ZR4230 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZR4230 -# endif -# define machine_is_zr4230() (machine_arch_type == MACH_TYPE_ZR4230) -#else -# define machine_is_zr4230() (0) -#endif - -#ifdef CONFIG_MACH_T1_IX_BLUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T1_IX_BLUE -# endif -# define machine_is_t1_ix_blue() (machine_arch_type == MACH_TYPE_T1_IX_BLUE) -#else -# define machine_is_t1_ix_blue() (0) -#endif - -#ifdef CONFIG_MACH_SYHQ2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYHQ2 -# endif -# define machine_is_syhq2() (machine_arch_type == MACH_TYPE_SYHQ2) -#else -# define machine_is_syhq2() (0) -#endif - -#ifdef CONFIG_MACH_COMPUTIME_R3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMPUTIME_R3 -# endif -# define machine_is_computime_r3() (machine_arch_type == MACH_TYPE_COMPUTIME_R3) -#else -# define machine_is_computime_r3() (0) -#endif - -#ifdef CONFIG_MACH_ORATIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATIS -# endif -# define machine_is_oratis() (machine_arch_type == MACH_TYPE_ORATIS) -#else -# define machine_is_oratis() (0) -#endif - -#ifdef CONFIG_MACH_MIKKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIKKO -# endif -# define machine_is_mikko() (machine_arch_type == MACH_TYPE_MIKKO) -#else -# define machine_is_mikko() (0) -#endif - -#ifdef CONFIG_MACH_HOLON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HOLON -# endif -# define machine_is_holon() (machine_arch_type == MACH_TYPE_HOLON) -#else -# define machine_is_holon() (0) -#endif - -#ifdef CONFIG_MACH_OLIP8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OLIP8 -# endif -# define machine_is_olip8() (machine_arch_type == MACH_TYPE_OLIP8) -#else -# define machine_is_olip8() (0) -#endif - -#ifdef CONFIG_MACH_GHI270HG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GHI270HG -# endif -# define machine_is_ghi270hg() (machine_arch_type == MACH_TYPE_GHI270HG) -#else -# define machine_is_ghi270hg() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM6467_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM6467_EVM -# endif -# define machine_is_davinci_dm6467_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467_EVM) -#else -# define machine_is_davinci_dm6467_evm() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM355_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM355_EVM -# endif -# define machine_is_davinci_dm355_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM) -#else -# define machine_is_davinci_dm355_evm() (0) -#endif - -#ifdef CONFIG_MACH_BLACKRIVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLACKRIVER -# endif -# define machine_is_blackriver() (machine_arch_type == MACH_TYPE_BLACKRIVER) -#else -# define machine_is_blackriver() (0) -#endif - -#ifdef CONFIG_MACH_SANDGATEWP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDGATEWP -# endif -# define machine_is_sandgate_wp() (machine_arch_type == MACH_TYPE_SANDGATEWP) -#else -# define machine_is_sandgate_wp() (0) -#endif - -#ifdef CONFIG_MACH_CDOTBWSG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CDOTBWSG -# endif -# define machine_is_cdotbwsg() (machine_arch_type == MACH_TYPE_CDOTBWSG) -#else -# define machine_is_cdotbwsg() (0) -#endif - -#ifdef CONFIG_MACH_QUARK963 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUARK963 -# endif -# define machine_is_quark963() (machine_arch_type == MACH_TYPE_QUARK963) -#else -# define machine_is_quark963() (0) -#endif - -#ifdef CONFIG_MACH_CSB735 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB735 -# endif -# define machine_is_csb735() (machine_arch_type == MACH_TYPE_CSB735) -#else -# define machine_is_csb735() (0) -#endif - -#ifdef CONFIG_MACH_LITTLETON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LITTLETON -# endif -# define machine_is_littleton() (machine_arch_type == MACH_TYPE_LITTLETON) -#else -# define machine_is_littleton() (0) -#endif - -#ifdef CONFIG_MACH_MIO_P550 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIO_P550 -# endif -# define machine_is_mio_p550() (machine_arch_type == MACH_TYPE_MIO_P550) -#else -# define machine_is_mio_p550() (0) -#endif - -#ifdef CONFIG_MACH_MOTION2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTION2440 -# endif -# define machine_is_motion2440() (machine_arch_type == MACH_TYPE_MOTION2440) -#else -# define machine_is_motion2440() (0) -#endif - -#ifdef CONFIG_MACH_IMM500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMM500 -# endif -# define machine_is_imm500() (machine_arch_type == MACH_TYPE_IMM500) -#else -# define machine_is_imm500() (0) -#endif - -#ifdef CONFIG_MACH_HOMEMATIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HOMEMATIC -# endif -# define machine_is_homematic() (machine_arch_type == MACH_TYPE_HOMEMATIC) -#else -# define machine_is_homematic() (0) -#endif - -#ifdef CONFIG_MACH_ERMINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ERMINE -# endif -# define machine_is_ermine() (machine_arch_type == MACH_TYPE_ERMINE) -#else -# define machine_is_ermine() (0) -#endif - -#ifdef CONFIG_MACH_KB9202B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KB9202B -# endif -# define machine_is_kb9202b() (machine_arch_type == MACH_TYPE_KB9202B) -#else -# define machine_is_kb9202b() (0) -#endif - -#ifdef CONFIG_MACH_HS1XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HS1XX -# endif -# define machine_is_hs1xx() (machine_arch_type == MACH_TYPE_HS1XX) -#else -# define machine_is_hs1xx() (0) -#endif - -#ifdef CONFIG_MACH_STUDENTMATE2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STUDENTMATE2440 -# endif -# define machine_is_studentmate2440() (machine_arch_type == MACH_TYPE_STUDENTMATE2440) -#else -# define machine_is_studentmate2440() (0) -#endif - -#ifdef CONFIG_MACH_ARVOO_L1_Z1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARVOO_L1_Z1 -# endif -# define machine_is_arvoo_l1_z1() (machine_arch_type == MACH_TYPE_ARVOO_L1_Z1) -#else -# define machine_is_arvoo_l1_z1() (0) -#endif - -#ifdef CONFIG_MACH_DEP2410K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2410K -# endif -# define machine_is_dep2410k() (machine_arch_type == MACH_TYPE_DEP2410K) -#else -# define machine_is_dep2410k() (0) -#endif - -#ifdef CONFIG_MACH_XXSVIDEO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XXSVIDEO -# endif -# define machine_is_xxsvideo() (machine_arch_type == MACH_TYPE_XXSVIDEO) -#else -# define machine_is_xxsvideo() (0) -#endif - -#ifdef CONFIG_MACH_IM4004 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IM4004 -# endif -# define machine_is_im4004() (machine_arch_type == MACH_TYPE_IM4004) -#else -# define machine_is_im4004() (0) -#endif - -#ifdef CONFIG_MACH_OCHAYA1050 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCHAYA1050 -# endif -# define machine_is_ochaya1050() (machine_arch_type == MACH_TYPE_OCHAYA1050) -#else -# define machine_is_ochaya1050() (0) -#endif - -#ifdef CONFIG_MACH_LEP9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEP9261 -# endif -# define machine_is_lep9261() (machine_arch_type == MACH_TYPE_LEP9261) -#else -# define machine_is_lep9261() (0) -#endif - -#ifdef CONFIG_MACH_SVENMEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVENMEB -# endif -# define machine_is_svenmeb() (machine_arch_type == MACH_TYPE_SVENMEB) -#else -# define machine_is_svenmeb() (0) -#endif - -#ifdef CONFIG_MACH_FORTUNET2NE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTUNET2NE -# endif -# define machine_is_fortunet2ne() (machine_arch_type == MACH_TYPE_FORTUNET2NE) -#else -# define machine_is_fortunet2ne() (0) -#endif - -#ifdef CONFIG_MACH_NXHX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXHX -# endif -# define machine_is_nxhx() (machine_arch_type == MACH_TYPE_NXHX) -#else -# define machine_is_nxhx() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PB11MP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PB11MP -# endif -# define machine_is_realview_pb11mp() (machine_arch_type == MACH_TYPE_REALVIEW_PB11MP) -#else -# define machine_is_realview_pb11mp() (0) -#endif - -#ifdef CONFIG_MACH_IDS500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IDS500 -# endif -# define machine_is_ids500() (machine_arch_type == MACH_TYPE_IDS500) -#else -# define machine_is_ids500() (0) -#endif - -#ifdef CONFIG_MACH_ORS_N725 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORS_N725 -# endif -# define machine_is_ors_n725() (machine_arch_type == MACH_TYPE_ORS_N725) -#else -# define machine_is_ors_n725() (0) -#endif - -#ifdef CONFIG_MACH_HSDARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HSDARM -# endif -# define machine_is_hsdarm() (machine_arch_type == MACH_TYPE_HSDARM) -#else -# define machine_is_hsdarm() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON003 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON003 -# endif -# define machine_is_sha_pon003() (machine_arch_type == MACH_TYPE_SHA_PON003) -#else -# define machine_is_sha_pon003() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON004 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON004 -# endif -# define machine_is_sha_pon004() (machine_arch_type == MACH_TYPE_SHA_PON004) -#else -# define machine_is_sha_pon004() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON007 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON007 -# endif -# define machine_is_sha_pon007() (machine_arch_type == MACH_TYPE_SHA_PON007) -#else -# define machine_is_sha_pon007() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON011 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON011 -# endif -# define machine_is_sha_pon011() (machine_arch_type == MACH_TYPE_SHA_PON011) -#else -# define machine_is_sha_pon011() (0) -#endif - -#ifdef CONFIG_MACH_H6042 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6042 -# endif -# define machine_is_h6042() (machine_arch_type == MACH_TYPE_H6042) -#else -# define machine_is_h6042() (0) -#endif - -#ifdef CONFIG_MACH_H6043 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6043 -# endif -# define machine_is_h6043() (machine_arch_type == MACH_TYPE_H6043) -#else -# define machine_is_h6043() (0) -#endif - -#ifdef CONFIG_MACH_LOOXC550 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOXC550 -# endif -# define machine_is_looxc550() (machine_arch_type == MACH_TYPE_LOOXC550) -#else -# define machine_is_looxc550() (0) -#endif - -#ifdef CONFIG_MACH_CNTY_TITAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CNTY_TITAN -# endif -# define machine_is_cnty_titan() (machine_arch_type == MACH_TYPE_CNTY_TITAN) -#else -# define machine_is_cnty_titan() (0) -#endif - -#ifdef CONFIG_MACH_APP3XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APP3XX -# endif -# define machine_is_app3xx() (machine_arch_type == MACH_TYPE_APP3XX) -#else -# define machine_is_app3xx() (0) -#endif - -#ifdef CONFIG_MACH_SIDEOATSGRAMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIDEOATSGRAMA -# endif -# define machine_is_sideoatsgrama() (machine_arch_type == MACH_TYPE_SIDEOATSGRAMA) -#else -# define machine_is_sideoatsgrama() (0) -#endif - -#ifdef CONFIG_MACH_TREO700P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO700P -# endif -# define machine_is_treo700p() (machine_arch_type == MACH_TYPE_TREO700P) -#else -# define machine_is_treo700p() (0) -#endif - -#ifdef CONFIG_MACH_TREO700W -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO700W -# endif -# define machine_is_treo700w() (machine_arch_type == MACH_TYPE_TREO700W) -#else -# define machine_is_treo700w() (0) -#endif - -#ifdef CONFIG_MACH_TREO750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO750 -# endif -# define machine_is_treo750() (machine_arch_type == MACH_TYPE_TREO750) -#else -# define machine_is_treo750() (0) -#endif - -#ifdef CONFIG_MACH_TREO755P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO755P -# endif -# define machine_is_treo755p() (machine_arch_type == MACH_TYPE_TREO755P) -#else -# define machine_is_treo755p() (0) -#endif - -#ifdef CONFIG_MACH_EZREGANUT9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZREGANUT9200 -# endif -# define machine_is_ezreganut9200() (machine_arch_type == MACH_TYPE_EZREGANUT9200) -#else -# define machine_is_ezreganut9200() (0) -#endif - -#ifdef CONFIG_MACH_SARGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SARGE -# endif -# define machine_is_sarge() (machine_arch_type == MACH_TYPE_SARGE) -#else -# define machine_is_sarge() (0) -#endif - -#ifdef CONFIG_MACH_A696 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A696 -# endif -# define machine_is_a696() (machine_arch_type == MACH_TYPE_A696) -#else -# define machine_is_a696() (0) -#endif - -#ifdef CONFIG_MACH_TURTLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TURTLE -# endif -# define machine_is_turtle1916() (machine_arch_type == MACH_TYPE_TURTLE) -#else -# define machine_is_turtle1916() (0) -#endif - -#ifdef CONFIG_MACH_MX27_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27_3DS -# endif -# define machine_is_mx27_3ds() (machine_arch_type == MACH_TYPE_MX27_3DS) -#else -# define machine_is_mx27_3ds() (0) -#endif - -#ifdef CONFIG_MACH_BISHOP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BISHOP -# endif -# define machine_is_bishop() (machine_arch_type == MACH_TYPE_BISHOP) -#else -# define machine_is_bishop() (0) -#endif - -#ifdef CONFIG_MACH_PXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXX -# endif -# define machine_is_pxx() (machine_arch_type == MACH_TYPE_PXX) -#else -# define machine_is_pxx() (0) -#endif - -#ifdef CONFIG_MACH_REDWOOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REDWOOD -# endif -# define machine_is_redwood() (machine_arch_type == MACH_TYPE_REDWOOD) -#else -# define machine_is_redwood() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430DLP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430DLP -# endif -# define machine_is_omap_2430dlp() (machine_arch_type == MACH_TYPE_OMAP_2430DLP) -#else -# define machine_is_omap_2430dlp() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430OSK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430OSK -# endif -# define machine_is_omap_2430osk() (machine_arch_type == MACH_TYPE_OMAP_2430OSK) -#else -# define machine_is_omap_2430osk() (0) -#endif - -#ifdef CONFIG_MACH_SARDINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SARDINE -# endif -# define machine_is_sardine() (machine_arch_type == MACH_TYPE_SARDINE) -#else -# define machine_is_sardine() (0) -#endif - -#ifdef CONFIG_MACH_HALIBUT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HALIBUT -# endif -# define machine_is_halibut() (machine_arch_type == MACH_TYPE_HALIBUT) -#else -# define machine_is_halibut() (0) -#endif - -#ifdef CONFIG_MACH_TROUT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TROUT -# endif -# define machine_is_trout() (machine_arch_type == MACH_TYPE_TROUT) -#else -# define machine_is_trout() (0) -#endif - -#ifdef CONFIG_MACH_GOLDFISH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GOLDFISH -# endif -# define machine_is_goldfish() (machine_arch_type == MACH_TYPE_GOLDFISH) -#else -# define machine_is_goldfish() (0) -#endif - -#ifdef CONFIG_MACH_GESBC2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GESBC2440 -# endif -# define machine_is_gesbc2440() (machine_arch_type == MACH_TYPE_GESBC2440) -#else -# define machine_is_gesbc2440() (0) -#endif - -#ifdef CONFIG_MACH_NOMAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOMAD -# endif -# define machine_is_nomad() (machine_arch_type == MACH_TYPE_NOMAD) -#else -# define machine_is_nomad() (0) -#endif - -#ifdef CONFIG_MACH_ROSALIND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROSALIND -# endif -# define machine_is_rosalind() (machine_arch_type == MACH_TYPE_ROSALIND) -#else -# define machine_is_rosalind() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9215 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9215 -# endif -# define machine_is_cc9p9215() (machine_arch_type == MACH_TYPE_CC9P9215) -#else -# define machine_is_cc9p9215() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9210 -# endif -# define machine_is_cc9p9210() (machine_arch_type == MACH_TYPE_CC9P9210) -#else -# define machine_is_cc9p9210() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9215JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9215JS -# endif -# define machine_is_cc9p9215js() (machine_arch_type == MACH_TYPE_CC9P9215JS) -#else -# define machine_is_cc9p9215js() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9210JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9210JS -# endif -# define machine_is_cc9p9210js() (machine_arch_type == MACH_TYPE_CC9P9210JS) -#else -# define machine_is_cc9p9210js() (0) -#endif - -#ifdef CONFIG_MACH_NASFFE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NASFFE -# endif -# define machine_is_nasffe() (machine_arch_type == MACH_TYPE_NASFFE) -#else -# define machine_is_nasffe() (0) -#endif - -#ifdef CONFIG_MACH_TN2X0BD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TN2X0BD -# endif -# define machine_is_tn2x0bd() (machine_arch_type == MACH_TYPE_TN2X0BD) -#else -# define machine_is_tn2x0bd() (0) -#endif - -#ifdef CONFIG_MACH_GWMPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GWMPXA -# endif -# define machine_is_gwmpxa() (machine_arch_type == MACH_TYPE_GWMPXA) -#else -# define machine_is_gwmpxa() (0) -#endif - -#ifdef CONFIG_MACH_EXYPLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXYPLUS -# endif -# define machine_is_exyplus() (machine_arch_type == MACH_TYPE_EXYPLUS) -#else -# define machine_is_exyplus() (0) -#endif - -#ifdef CONFIG_MACH_JADOO21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADOO21 -# endif -# define machine_is_jadoo21() (machine_arch_type == MACH_TYPE_JADOO21) -#else -# define machine_is_jadoo21() (0) -#endif - -#ifdef CONFIG_MACH_LOOXN560 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOOXN560 -# endif -# define machine_is_looxn560() (machine_arch_type == MACH_TYPE_LOOXN560) -#else -# define machine_is_looxn560() (0) -#endif - -#ifdef CONFIG_MACH_BONSAI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BONSAI -# endif -# define machine_is_bonsai() (machine_arch_type == MACH_TYPE_BONSAI) -#else -# define machine_is_bonsai() (0) -#endif - -#ifdef CONFIG_MACH_ADSMILGATO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSMILGATO -# endif -# define machine_is_adsmilgato() (machine_arch_type == MACH_TYPE_ADSMILGATO) -#else -# define machine_is_adsmilgato() (0) -#endif - -#ifdef CONFIG_MACH_GBA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GBA -# endif -# define machine_is_gba() (machine_arch_type == MACH_TYPE_GBA) -#else -# define machine_is_gba() (0) -#endif - -#ifdef CONFIG_MACH_H6044 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6044 -# endif -# define machine_is_h6044() (machine_arch_type == MACH_TYPE_H6044) -#else -# define machine_is_h6044() (0) -#endif - -#ifdef CONFIG_MACH_APP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APP -# endif -# define machine_is_app() (machine_arch_type == MACH_TYPE_APP) -#else -# define machine_is_app() (0) -#endif - -#ifdef CONFIG_MACH_TCT_HAMMER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCT_HAMMER -# endif -# define machine_is_tct_hammer() (machine_arch_type == MACH_TYPE_TCT_HAMMER) -#else -# define machine_is_tct_hammer() (0) -#endif - -#ifdef CONFIG_MACH_HERALD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERALD -# endif -# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERALD) -#else -# define machine_is_herald() (0) -#endif - -#ifdef CONFIG_MACH_ARTEMIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARTEMIS -# endif -# define machine_is_artemis() (machine_arch_type == MACH_TYPE_ARTEMIS) -#else -# define machine_is_artemis() (0) -#endif - -#ifdef CONFIG_MACH_HTCTITAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCTITAN -# endif -# define machine_is_htctitan() (machine_arch_type == MACH_TYPE_HTCTITAN) -#else -# define machine_is_htctitan() (0) -#endif - -#ifdef CONFIG_MACH_QRANIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QRANIUM -# endif -# define machine_is_qranium() (machine_arch_type == MACH_TYPE_QRANIUM) -#else -# define machine_is_qranium() (0) -#endif - -#ifdef CONFIG_MACH_ADX_WSC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_WSC2 -# endif -# define machine_is_adx_wsc2() (machine_arch_type == MACH_TYPE_ADX_WSC2) -#else -# define machine_is_adx_wsc2() (0) -#endif - -#ifdef CONFIG_MACH_ADX_MEDCOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_MEDCOM -# endif -# define machine_is_adx_medcom() (machine_arch_type == MACH_TYPE_ADX_MEDCOM) -#else -# define machine_is_adx_medcom() (0) -#endif - -#ifdef CONFIG_MACH_BBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BBOARD -# endif -# define machine_is_bboard() (machine_arch_type == MACH_TYPE_BBOARD) -#else -# define machine_is_bboard() (0) -#endif - -#ifdef CONFIG_MACH_CAMBRIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAMBRIA -# endif -# define machine_is_cambria() (machine_arch_type == MACH_TYPE_CAMBRIA) -#else -# define machine_is_cambria() (0) -#endif - -#ifdef CONFIG_MACH_MT7XXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MT7XXX -# endif -# define machine_is_mt7xxx() (machine_arch_type == MACH_TYPE_MT7XXX) -#else -# define machine_is_mt7xxx() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX512 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX512 -# endif -# define machine_is_matrix512() (machine_arch_type == MACH_TYPE_MATRIX512) -#else -# define machine_is_matrix512() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX522 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX522 -# endif -# define machine_is_matrix522() (machine_arch_type == MACH_TYPE_MATRIX522) -#else -# define machine_is_matrix522() (0) -#endif - -#ifdef CONFIG_MACH_IPAC5010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPAC5010 -# endif -# define machine_is_ipac5010() (machine_arch_type == MACH_TYPE_IPAC5010) -#else -# define machine_is_ipac5010() (0) -#endif - -#ifdef CONFIG_MACH_SAKURA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAKURA -# endif -# define machine_is_sakura() (machine_arch_type == MACH_TYPE_SAKURA) -#else -# define machine_is_sakura() (0) -#endif - -#ifdef CONFIG_MACH_GROCX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GROCX -# endif -# define machine_is_grocx() (machine_arch_type == MACH_TYPE_GROCX) -#else -# define machine_is_grocx() (0) -#endif - -#ifdef CONFIG_MACH_PM9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM9263 -# endif -# define machine_is_pm9263() (machine_arch_type == MACH_TYPE_PM9263) -#else -# define machine_is_pm9263() (0) -#endif - -#ifdef CONFIG_MACH_SIM_ONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIM_ONE -# endif -# define machine_is_sim_one() (machine_arch_type == MACH_TYPE_SIM_ONE) -#else -# define machine_is_sim_one() (0) -#endif - -#ifdef CONFIG_MACH_ACQ132 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACQ132 -# endif -# define machine_is_acq132() (machine_arch_type == MACH_TYPE_ACQ132) -#else -# define machine_is_acq132() (0) -#endif - -#ifdef CONFIG_MACH_DATR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DATR -# endif -# define machine_is_datr() (machine_arch_type == MACH_TYPE_DATR) -#else -# define machine_is_datr() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX1 -# endif -# define machine_is_actux1() (machine_arch_type == MACH_TYPE_ACTUX1) -#else -# define machine_is_actux1() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX2 -# endif -# define machine_is_actux2() (machine_arch_type == MACH_TYPE_ACTUX2) -#else -# define machine_is_actux2() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX3 -# endif -# define machine_is_actux3() (machine_arch_type == MACH_TYPE_ACTUX3) -#else -# define machine_is_actux3() (0) -#endif - -#ifdef CONFIG_MACH_FLEXIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEXIT -# endif -# define machine_is_flexit() (machine_arch_type == MACH_TYPE_FLEXIT) -#else -# define machine_is_flexit() (0) -#endif - -#ifdef CONFIG_MACH_BH2X0BD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BH2X0BD -# endif -# define machine_is_bh2x0bd() (machine_arch_type == MACH_TYPE_BH2X0BD) -#else -# define machine_is_bh2x0bd() (0) -#endif - -#ifdef CONFIG_MACH_ATB2002 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATB2002 -# endif -# define machine_is_atb2002() (machine_arch_type == MACH_TYPE_ATB2002) -#else -# define machine_is_atb2002() (0) -#endif - -#ifdef CONFIG_MACH_XENON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XENON -# endif -# define machine_is_xenon() (machine_arch_type == MACH_TYPE_XENON) -#else -# define machine_is_xenon() (0) -#endif - -#ifdef CONFIG_MACH_FM607 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FM607 -# endif -# define machine_is_fm607() (machine_arch_type == MACH_TYPE_FM607) -#else -# define machine_is_fm607() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX514 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX514 -# endif -# define machine_is_matrix514() (machine_arch_type == MACH_TYPE_MATRIX514) -#else -# define machine_is_matrix514() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX524 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX524 -# endif -# define machine_is_matrix524() (machine_arch_type == MACH_TYPE_MATRIX524) -#else -# define machine_is_matrix524() (0) -#endif - -#ifdef CONFIG_MACH_INPOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INPOD -# endif -# define machine_is_inpod() (machine_arch_type == MACH_TYPE_INPOD) -#else -# define machine_is_inpod() (0) -#endif - -#ifdef CONFIG_MACH_JIVE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JIVE -# endif -# define machine_is_jive() (machine_arch_type == MACH_TYPE_JIVE) -#else -# define machine_is_jive() (0) -#endif - -#ifdef CONFIG_MACH_TLL_MX21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TLL_MX21 -# endif -# define machine_is_tll_mx21() (machine_arch_type == MACH_TYPE_TLL_MX21) -#else -# define machine_is_tll_mx21() (0) -#endif - -#ifdef CONFIG_MACH_SBC2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2800 -# endif -# define machine_is_sbc2800() (machine_arch_type == MACH_TYPE_SBC2800) -#else -# define machine_is_sbc2800() (0) -#endif - -#ifdef CONFIG_MACH_CC7UCAMRY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC7UCAMRY -# endif -# define machine_is_cc7ucamry() (machine_arch_type == MACH_TYPE_CC7UCAMRY) -#else -# define machine_is_cc7ucamry() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_SC15 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_SC15 -# endif -# define machine_is_ubisys_p9_sc15() (machine_arch_type == MACH_TYPE_UBISYS_P9_SC15) -#else -# define machine_is_ubisys_p9_sc15() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_SSC2D10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_SSC2D10 -# endif -# define machine_is_ubisys_p9_ssc2d10() (machine_arch_type == MACH_TYPE_UBISYS_P9_SSC2D10) -#else -# define machine_is_ubisys_p9_ssc2d10() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_RCU3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_RCU3 -# endif -# define machine_is_ubisys_p9_rcu3() (machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3) -#else -# define machine_is_ubisys_p9_rcu3() (0) -#endif - -#ifdef CONFIG_MACH_AML_M8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M8000 -# endif -# define machine_is_aml_m8000() (machine_arch_type == MACH_TYPE_AML_M8000) -#else -# define machine_is_aml_m8000() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_270 -# endif -# define machine_is_snapper_270() (machine_arch_type == MACH_TYPE_SNAPPER_270) -#else -# define machine_is_snapper_270() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_BBX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_BBX -# endif -# define machine_is_omap_bbx() (machine_arch_type == MACH_TYPE_OMAP_BBX) -#else -# define machine_is_omap_bbx() (0) -#endif - -#ifdef CONFIG_MACH_UCN2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCN2410 -# endif -# define machine_is_ucn2410() (machine_arch_type == MACH_TYPE_UCN2410) -#else -# define machine_is_ucn2410() (0) -#endif - -#ifdef CONFIG_MACH_SAM9_L9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9_L9260 -# endif -# define machine_is_sam9_l9260() (machine_arch_type == MACH_TYPE_SAM9_L9260) -#else -# define machine_is_sam9_l9260() (0) -#endif - -#ifdef CONFIG_MACH_ETI_C2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETI_C2 -# endif -# define machine_is_eti_c2() (machine_arch_type == MACH_TYPE_ETI_C2) -#else -# define machine_is_eti_c2() (0) -#endif - -#ifdef CONFIG_MACH_AVALANCHE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVALANCHE -# endif -# define machine_is_avalanche() (machine_arch_type == MACH_TYPE_AVALANCHE) -#else -# define machine_is_avalanche() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PB1176 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PB1176 -# endif -# define machine_is_realview_pb1176() (machine_arch_type == MACH_TYPE_REALVIEW_PB1176) -#else -# define machine_is_realview_pb1176() (0) -#endif - -#ifdef CONFIG_MACH_DP1500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DP1500 -# endif -# define machine_is_dp1500() (machine_arch_type == MACH_TYPE_DP1500) -#else -# define machine_is_dp1500() (0) -#endif - -#ifdef CONFIG_MACH_APPLE_IPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APPLE_IPHONE -# endif -# define machine_is_apple_iphone() (machine_arch_type == MACH_TYPE_APPLE_IPHONE) -#else -# define machine_is_apple_iphone() (0) -#endif - -#ifdef CONFIG_MACH_YL9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YL9200 -# endif -# define machine_is_yl9200() (machine_arch_type == MACH_TYPE_YL9200) -#else -# define machine_is_yl9200() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5182 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5182 -# endif -# define machine_is_rd88f5182() (machine_arch_type == MACH_TYPE_RD88F5182) -#else -# define machine_is_rd88f5182() (0) -#endif - -#ifdef CONFIG_MACH_KUROBOX_PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KUROBOX_PRO -# endif -# define machine_is_kurobox_pro() (machine_arch_type == MACH_TYPE_KUROBOX_PRO) -#else -# define machine_is_kurobox_pro() (0) -#endif - -#ifdef CONFIG_MACH_SE_POET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SE_POET -# endif -# define machine_is_se_poet() (machine_arch_type == MACH_TYPE_SE_POET) -#else -# define machine_is_se_poet() (0) -#endif - -#ifdef CONFIG_MACH_MX31_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31_3DS -# endif -# define machine_is_mx31_3ds() (machine_arch_type == MACH_TYPE_MX31_3DS) -#else -# define machine_is_mx31_3ds() (0) -#endif - -#ifdef CONFIG_MACH_R270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_R270 -# endif -# define machine_is_r270() (machine_arch_type == MACH_TYPE_R270) -#else -# define machine_is_r270() (0) -#endif - -#ifdef CONFIG_MACH_ARMOUR21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMOUR21 -# endif -# define machine_is_armour21() (machine_arch_type == MACH_TYPE_ARMOUR21) -#else -# define machine_is_armour21() (0) -#endif - -#ifdef CONFIG_MACH_DT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DT2 -# endif -# define machine_is_dt2() (machine_arch_type == MACH_TYPE_DT2) -#else -# define machine_is_dt2() (0) -#endif - -#ifdef CONFIG_MACH_VT4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VT4 -# endif -# define machine_is_vt4() (machine_arch_type == MACH_TYPE_VT4) -#else -# define machine_is_vt4() (0) -#endif - -#ifdef CONFIG_MACH_TYCO320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TYCO320 -# endif -# define machine_is_tyco320() (machine_arch_type == MACH_TYPE_TYCO320) -#else -# define machine_is_tyco320() (0) -#endif - -#ifdef CONFIG_MACH_ADMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADMA -# endif -# define machine_is_adma() (machine_arch_type == MACH_TYPE_ADMA) -#else -# define machine_is_adma() (0) -#endif - -#ifdef CONFIG_MACH_WP188 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WP188 -# endif -# define machine_is_wp188() (machine_arch_type == MACH_TYPE_WP188) -#else -# define machine_is_wp188() (0) -#endif - -#ifdef CONFIG_MACH_CORSICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORSICA -# endif -# define machine_is_corsica() (machine_arch_type == MACH_TYPE_CORSICA) -#else -# define machine_is_corsica() (0) -#endif - -#ifdef CONFIG_MACH_BIGEYE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIGEYE -# endif -# define machine_is_bigeye() (machine_arch_type == MACH_TYPE_BIGEYE) -#else -# define machine_is_bigeye() (0) -#endif - -#ifdef CONFIG_MACH_TLL5000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TLL5000 -# endif -# define machine_is_tll5000() (machine_arch_type == MACH_TYPE_TLL5000) -#else -# define machine_is_tll5000() (0) -#endif - -#ifdef CONFIG_MACH_BEBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BEBOT -# endif -# define machine_is_bebot() (machine_arch_type == MACH_TYPE_BEBOT) -#else -# define machine_is_bebot() (0) -#endif - -#ifdef CONFIG_MACH_QONG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QONG -# endif -# define machine_is_qong() (machine_arch_type == MACH_TYPE_QONG) -#else -# define machine_is_qong() (0) -#endif - -#ifdef CONFIG_MACH_TCOMPACT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCOMPACT -# endif -# define machine_is_tcompact() (machine_arch_type == MACH_TYPE_TCOMPACT) -#else -# define machine_is_tcompact() (0) -#endif - -#ifdef CONFIG_MACH_PUMA5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUMA5 -# endif -# define machine_is_puma5() (machine_arch_type == MACH_TYPE_PUMA5) -#else -# define machine_is_puma5() (0) -#endif - -#ifdef CONFIG_MACH_ELARA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELARA -# endif -# define machine_is_elara() (machine_arch_type == MACH_TYPE_ELARA) -#else -# define machine_is_elara() (0) -#endif - -#ifdef CONFIG_MACH_ELLINGTON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELLINGTON -# endif -# define machine_is_ellington() (machine_arch_type == MACH_TYPE_ELLINGTON) -#else -# define machine_is_ellington() (0) -#endif - -#ifdef CONFIG_MACH_XDA_ATOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDA_ATOM -# endif -# define machine_is_xda_atom() (machine_arch_type == MACH_TYPE_XDA_ATOM) -#else -# define machine_is_xda_atom() (0) -#endif - -#ifdef CONFIG_MACH_ENERGIZER2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENERGIZER2 -# endif -# define machine_is_energizer2() (machine_arch_type == MACH_TYPE_ENERGIZER2) -#else -# define machine_is_energizer2() (0) -#endif - -#ifdef CONFIG_MACH_ODIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ODIN -# endif -# define machine_is_odin() (machine_arch_type == MACH_TYPE_ODIN) -#else -# define machine_is_odin() (0) -#endif - -#ifdef CONFIG_MACH_ACTUX4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTUX4 -# endif -# define machine_is_actux4() (machine_arch_type == MACH_TYPE_ACTUX4) -#else -# define machine_is_actux4() (0) -#endif - -#ifdef CONFIG_MACH_ESL_OMAP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_OMAP -# endif -# define machine_is_esl_omap() (machine_arch_type == MACH_TYPE_ESL_OMAP) -#else -# define machine_is_esl_omap() (0) -#endif - -#ifdef CONFIG_MACH_OMAP2EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP2EVM -# endif -# define machine_is_omap2evm() (machine_arch_type == MACH_TYPE_OMAP2EVM) -#else -# define machine_is_omap2evm() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3EVM -# endif -# define machine_is_omap3evm() (machine_arch_type == MACH_TYPE_OMAP3EVM) -#else -# define machine_is_omap3evm() (0) -#endif - -#ifdef CONFIG_MACH_ADX_PCU57 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_PCU57 -# endif -# define machine_is_adx_pcu57() (machine_arch_type == MACH_TYPE_ADX_PCU57) -#else -# define machine_is_adx_pcu57() (0) -#endif - -#ifdef CONFIG_MACH_MONACO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MONACO -# endif -# define machine_is_monaco() (machine_arch_type == MACH_TYPE_MONACO) -#else -# define machine_is_monaco() (0) -#endif - -#ifdef CONFIG_MACH_LEVANTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEVANTE -# endif -# define machine_is_levante() (machine_arch_type == MACH_TYPE_LEVANTE) -#else -# define machine_is_levante() (0) -#endif - -#ifdef CONFIG_MACH_TMXIPX425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TMXIPX425 -# endif -# define machine_is_tmxipx425() (machine_arch_type == MACH_TYPE_TMXIPX425) -#else -# define machine_is_tmxipx425() (0) -#endif - -#ifdef CONFIG_MACH_LEEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEEP -# endif -# define machine_is_leep() (machine_arch_type == MACH_TYPE_LEEP) -#else -# define machine_is_leep() (0) -#endif - -#ifdef CONFIG_MACH_RAAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAAD -# endif -# define machine_is_raad() (machine_arch_type == MACH_TYPE_RAAD) -#else -# define machine_is_raad() (0) -#endif - -#ifdef CONFIG_MACH_DNS323 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DNS323 -# endif -# define machine_is_dns323() (machine_arch_type == MACH_TYPE_DNS323) -#else -# define machine_is_dns323() (0) -#endif - -#ifdef CONFIG_MACH_AP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AP1000 -# endif -# define machine_is_ap1000() (machine_arch_type == MACH_TYPE_AP1000) -#else -# define machine_is_ap1000() (0) -#endif - -#ifdef CONFIG_MACH_A9SAM6432 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9SAM6432 -# endif -# define machine_is_a9sam6432() (machine_arch_type == MACH_TYPE_A9SAM6432) -#else -# define machine_is_a9sam6432() (0) -#endif - -#ifdef CONFIG_MACH_SHINY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHINY -# endif -# define machine_is_shiny() (machine_arch_type == MACH_TYPE_SHINY) -#else -# define machine_is_shiny() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_BEAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_BEAGLE -# endif -# define machine_is_omap3_beagle() (machine_arch_type == MACH_TYPE_OMAP3_BEAGLE) -#else -# define machine_is_omap3_beagle() (0) -#endif - -#ifdef CONFIG_MACH_CSR_BDB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSR_BDB2 -# endif -# define machine_is_csr_bdb2() (machine_arch_type == MACH_TYPE_CSR_BDB2) -#else -# define machine_is_csr_bdb2() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N810 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N810 -# endif -# define machine_is_nokia_n810() (machine_arch_type == MACH_TYPE_NOKIA_N810) -#else -# define machine_is_nokia_n810() (0) -#endif - -#ifdef CONFIG_MACH_C270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C270 -# endif -# define machine_is_c270() (machine_arch_type == MACH_TYPE_C270) -#else -# define machine_is_c270() (0) -#endif - -#ifdef CONFIG_MACH_SENTRY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SENTRY -# endif -# define machine_is_sentry() (machine_arch_type == MACH_TYPE_SENTRY) -#else -# define machine_is_sentry() (0) -#endif - -#ifdef CONFIG_MACH_PCM038 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM038 -# endif -# define machine_is_pcm038() (machine_arch_type == MACH_TYPE_PCM038) -#else -# define machine_is_pcm038() (0) -#endif - -#ifdef CONFIG_MACH_ANC300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANC300 -# endif -# define machine_is_anc300() (machine_arch_type == MACH_TYPE_ANC300) -#else -# define machine_is_anc300() (0) -#endif - -#ifdef CONFIG_MACH_HTCKAISER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCKAISER -# endif -# define machine_is_htckaiser() (machine_arch_type == MACH_TYPE_HTCKAISER) -#else -# define machine_is_htckaiser() (0) -#endif - -#ifdef CONFIG_MACH_SBAT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBAT100 -# endif -# define machine_is_sbat100() (machine_arch_type == MACH_TYPE_SBAT100) -#else -# define machine_is_sbat100() (0) -#endif - -#ifdef CONFIG_MACH_MODUNORM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MODUNORM -# endif -# define machine_is_modunorm() (machine_arch_type == MACH_TYPE_MODUNORM) -#else -# define machine_is_modunorm() (0) -#endif - -#ifdef CONFIG_MACH_PELOS_TWARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELOS_TWARM -# endif -# define machine_is_pelos_twarm() (machine_arch_type == MACH_TYPE_PELOS_TWARM) -#else -# define machine_is_pelos_twarm() (0) -#endif - -#ifdef CONFIG_MACH_FLANK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLANK -# endif -# define machine_is_flank() (machine_arch_type == MACH_TYPE_FLANK) -#else -# define machine_is_flank() (0) -#endif - -#ifdef CONFIG_MACH_SIRLOIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIRLOIN -# endif -# define machine_is_sirloin() (machine_arch_type == MACH_TYPE_SIRLOIN) -#else -# define machine_is_sirloin() (0) -#endif - -#ifdef CONFIG_MACH_BRISKET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRISKET -# endif -# define machine_is_brisket() (machine_arch_type == MACH_TYPE_BRISKET) -#else -# define machine_is_brisket() (0) -#endif - -#ifdef CONFIG_MACH_CHUCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHUCK -# endif -# define machine_is_chuck() (machine_arch_type == MACH_TYPE_CHUCK) -#else -# define machine_is_chuck() (0) -#endif - -#ifdef CONFIG_MACH_OTTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTTER -# endif -# define machine_is_otter() (machine_arch_type == MACH_TYPE_OTTER) -#else -# define machine_is_otter() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_LDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_LDK -# endif -# define machine_is_davinci_ldk() (machine_arch_type == MACH_TYPE_DAVINCI_LDK) -#else -# define machine_is_davinci_ldk() (0) -#endif - -#ifdef CONFIG_MACH_PHREEDOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHREEDOM -# endif -# define machine_is_phreedom() (machine_arch_type == MACH_TYPE_PHREEDOM) -#else -# define machine_is_phreedom() (0) -#endif - -#ifdef CONFIG_MACH_SG310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG310 -# endif -# define machine_is_sg310() (machine_arch_type == MACH_TYPE_SG310) -#else -# define machine_is_sg310() (0) -#endif - -#ifdef CONFIG_MACH_TS209 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS209 -# endif -# define machine_is_ts_x09() (machine_arch_type == MACH_TYPE_TS209) -#else -# define machine_is_ts_x09() (0) -#endif - -#ifdef CONFIG_MACH_AT91CAP9ADK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91CAP9ADK -# endif -# define machine_is_at91cap9adk() (machine_arch_type == MACH_TYPE_AT91CAP9ADK) -#else -# define machine_is_at91cap9adk() (0) -#endif - -#ifdef CONFIG_MACH_TION9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TION9315 -# endif -# define machine_is_tion9315() (machine_arch_type == MACH_TYPE_TION9315) -#else -# define machine_is_tion9315() (0) -#endif - -#ifdef CONFIG_MACH_MAST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAST -# endif -# define machine_is_mast() (machine_arch_type == MACH_TYPE_MAST) -#else -# define machine_is_mast() (0) -#endif - -#ifdef CONFIG_MACH_PFW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PFW -# endif -# define machine_is_pfw() (machine_arch_type == MACH_TYPE_PFW) -#else -# define machine_is_pfw() (0) -#endif - -#ifdef CONFIG_MACH_YL_P2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YL_P2440 -# endif -# define machine_is_yl_p2440() (machine_arch_type == MACH_TYPE_YL_P2440) -#else -# define machine_is_yl_p2440() (0) -#endif - -#ifdef CONFIG_MACH_ZSBC32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZSBC32 -# endif -# define machine_is_zsbc32() (machine_arch_type == MACH_TYPE_ZSBC32) -#else -# define machine_is_zsbc32() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PACE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PACE2 -# endif -# define machine_is_omap_pace2() (machine_arch_type == MACH_TYPE_OMAP_PACE2) -#else -# define machine_is_omap_pace2() (0) -#endif - -#ifdef CONFIG_MACH_IMX_PACE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX_PACE2 -# endif -# define machine_is_imx_pace2() (machine_arch_type == MACH_TYPE_IMX_PACE2) -#else -# define machine_is_imx_pace2() (0) -#endif - -#ifdef CONFIG_MACH_MX31MOBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31MOBOARD -# endif -# define machine_is_mx31moboard() (machine_arch_type == MACH_TYPE_MX31MOBOARD) -#else -# define machine_is_mx31moboard() (0) -#endif - -#ifdef CONFIG_MACH_MX37_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX37_3DS -# endif -# define machine_is_mx37_3ds() (machine_arch_type == MACH_TYPE_MX37_3DS) -#else -# define machine_is_mx37_3ds() (0) -#endif - -#ifdef CONFIG_MACH_RCC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RCC -# endif -# define machine_is_rcc() (machine_arch_type == MACH_TYPE_RCC) -#else -# define machine_is_rcc() (0) -#endif - -#ifdef CONFIG_MACH_ARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM9 -# endif -# define machine_is_dmp() (machine_arch_type == MACH_TYPE_ARM9) -#else -# define machine_is_dmp() (0) -#endif - -#ifdef CONFIG_MACH_VISION_EP9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VISION_EP9307 -# endif -# define machine_is_vision_ep9307() (machine_arch_type == MACH_TYPE_VISION_EP9307) -#else -# define machine_is_vision_ep9307() (0) -#endif - -#ifdef CONFIG_MACH_SCLY1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCLY1000 -# endif -# define machine_is_scly1000() (machine_arch_type == MACH_TYPE_SCLY1000) -#else -# define machine_is_scly1000() (0) -#endif - -#ifdef CONFIG_MACH_FONTEL_EP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FONTEL_EP -# endif -# define machine_is_fontel_ep() (machine_arch_type == MACH_TYPE_FONTEL_EP) -#else -# define machine_is_fontel_ep() (0) -#endif - -#ifdef CONFIG_MACH_VOICEBLUE3G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOICEBLUE3G -# endif -# define machine_is_voiceblue3g() (machine_arch_type == MACH_TYPE_VOICEBLUE3G) -#else -# define machine_is_voiceblue3g() (0) -#endif - -#ifdef CONFIG_MACH_TT9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT9200 -# endif -# define machine_is_tt9200() (machine_arch_type == MACH_TYPE_TT9200) -#else -# define machine_is_tt9200() (0) -#endif - -#ifdef CONFIG_MACH_DIGI2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIGI2410 -# endif -# define machine_is_digi2410() (machine_arch_type == MACH_TYPE_DIGI2410) -#else -# define machine_is_digi2410() (0) -#endif - -#ifdef CONFIG_MACH_TERASTATION_PRO2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TERASTATION_PRO2 -# endif -# define machine_is_terastation_pro2() (machine_arch_type == MACH_TYPE_TERASTATION_PRO2) -#else -# define machine_is_terastation_pro2() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_PRO -# endif -# define machine_is_linkstation_pro() (machine_arch_type == MACH_TYPE_LINKSTATION_PRO) -#else -# define machine_is_linkstation_pro() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_A780 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_A780 -# endif -# define machine_is_motorola_a780() (machine_arch_type == MACH_TYPE_MOTOROLA_A780) -#else -# define machine_is_motorola_a780() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_E6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_E6 -# endif -# define machine_is_motorola_e6() (machine_arch_type == MACH_TYPE_MOTOROLA_E6) -#else -# define machine_is_motorola_e6() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_E2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_E2 -# endif -# define machine_is_motorola_e2() (machine_arch_type == MACH_TYPE_MOTOROLA_E2) -#else -# define machine_is_motorola_e2() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_E680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_E680 -# endif -# define machine_is_motorola_e680() (machine_arch_type == MACH_TYPE_MOTOROLA_E680) -#else -# define machine_is_motorola_e680() (0) -#endif - -#ifdef CONFIG_MACH_UR2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UR2410 -# endif -# define machine_is_ur2410() (machine_arch_type == MACH_TYPE_UR2410) -#else -# define machine_is_ur2410() (0) -#endif - -#ifdef CONFIG_MACH_TAS9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAS9261 -# endif -# define machine_is_tas9261() (machine_arch_type == MACH_TYPE_TAS9261) -#else -# define machine_is_tas9261() (0) -#endif - -#ifdef CONFIG_MACH_HERMES_HD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERMES_HD -# endif -# define machine_is_davinci_hermes_hd() (machine_arch_type == MACH_TYPE_HERMES_HD) -#else -# define machine_is_davinci_hermes_hd() (0) -#endif - -#ifdef CONFIG_MACH_PERSEO_HD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERSEO_HD -# endif -# define machine_is_davinci_perseo_hd() (machine_arch_type == MACH_TYPE_PERSEO_HD) -#else -# define machine_is_davinci_perseo_hd() (0) -#endif - -#ifdef CONFIG_MACH_STARGAZER2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGAZER2 -# endif -# define machine_is_stargazer2() (machine_arch_type == MACH_TYPE_STARGAZER2) -#else -# define machine_is_stargazer2() (0) -#endif - -#ifdef CONFIG_MACH_E350 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E350 -# endif -# define machine_is_e350() (machine_arch_type == MACH_TYPE_E350) -#else -# define machine_is_e350() (0) -#endif - -#ifdef CONFIG_MACH_WPCM450 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WPCM450 -# endif -# define machine_is_wpcm450() (machine_arch_type == MACH_TYPE_WPCM450) -#else -# define machine_is_wpcm450() (0) -#endif - -#ifdef CONFIG_MACH_CARTESIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARTESIO -# endif -# define machine_is_cartesio() (machine_arch_type == MACH_TYPE_CARTESIO) -#else -# define machine_is_cartesio() (0) -#endif - -#ifdef CONFIG_MACH_TOYBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOYBOX -# endif -# define machine_is_toybox() (machine_arch_type == MACH_TYPE_TOYBOX) -#else -# define machine_is_toybox() (0) -#endif - -#ifdef CONFIG_MACH_TX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX27 -# endif -# define machine_is_tx27() (machine_arch_type == MACH_TYPE_TX27) -#else -# define machine_is_tx27() (0) -#endif - -#ifdef CONFIG_MACH_TS409 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS409 -# endif -# define machine_is_ts409() (machine_arch_type == MACH_TYPE_TS409) -#else -# define machine_is_ts409() (0) -#endif - -#ifdef CONFIG_MACH_P300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P300 -# endif -# define machine_is_p300() (machine_arch_type == MACH_TYPE_P300) -#else -# define machine_is_p300() (0) -#endif - -#ifdef CONFIG_MACH_XDACOMET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDACOMET -# endif -# define machine_is_xdacomet() (machine_arch_type == MACH_TYPE_XDACOMET) -#else -# define machine_is_xdacomet() (0) -#endif - -#ifdef CONFIG_MACH_DEXFLEX2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEXFLEX2 -# endif -# define machine_is_dexflex2() (machine_arch_type == MACH_TYPE_DEXFLEX2) -#else -# define machine_is_dexflex2() (0) -#endif - -#ifdef CONFIG_MACH_OW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OW -# endif -# define machine_is_ow() (machine_arch_type == MACH_TYPE_OW) -#else -# define machine_is_ow() (0) -#endif - -#ifdef CONFIG_MACH_ARMEBS3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMEBS3 -# endif -# define machine_is_armebs3() (machine_arch_type == MACH_TYPE_ARMEBS3) -#else -# define machine_is_armebs3() (0) -#endif - -#ifdef CONFIG_MACH_U3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U3 -# endif -# define machine_is_u3() (machine_arch_type == MACH_TYPE_U3) -#else -# define machine_is_u3() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2450 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2450 -# endif -# define machine_is_smdk2450() (machine_arch_type == MACH_TYPE_SMDK2450) -#else -# define machine_is_smdk2450() (0) -#endif - -#ifdef CONFIG_MACH_RSI_EWS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSI_EWS -# endif -# define machine_is_rsi_ews() (machine_arch_type == MACH_TYPE_RSI_EWS) -#else -# define machine_is_rsi_ews() (0) -#endif - -#ifdef CONFIG_MACH_TNB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNB -# endif -# define machine_is_tnb() (machine_arch_type == MACH_TYPE_TNB) -#else -# define machine_is_tnb() (0) -#endif - -#ifdef CONFIG_MACH_TOEPATH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOEPATH -# endif -# define machine_is_toepath() (machine_arch_type == MACH_TYPE_TOEPATH) -#else -# define machine_is_toepath() (0) -#endif - -#ifdef CONFIG_MACH_KB9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KB9263 -# endif -# define machine_is_kb9263() (machine_arch_type == MACH_TYPE_KB9263) -#else -# define machine_is_kb9263() (0) -#endif - -#ifdef CONFIG_MACH_MT7108 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MT7108 -# endif -# define machine_is_mt7108() (machine_arch_type == MACH_TYPE_MT7108) -#else -# define machine_is_mt7108() (0) -#endif - -#ifdef CONFIG_MACH_SMTR2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMTR2440 -# endif -# define machine_is_smtr2440() (machine_arch_type == MACH_TYPE_SMTR2440) -#else -# define machine_is_smtr2440() (0) -#endif - -#ifdef CONFIG_MACH_MANAO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MANAO -# endif -# define machine_is_manao() (machine_arch_type == MACH_TYPE_MANAO) -#else -# define machine_is_manao() (0) -#endif - -#ifdef CONFIG_MACH_CM_X300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_X300 -# endif -# define machine_is_cm_x300() (machine_arch_type == MACH_TYPE_CM_X300) -#else -# define machine_is_cm_x300() (0) -#endif - -#ifdef CONFIG_MACH_GULFSTREAM_KP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GULFSTREAM_KP -# endif -# define machine_is_gulfstream_kp() (machine_arch_type == MACH_TYPE_GULFSTREAM_KP) -#else -# define machine_is_gulfstream_kp() (0) -#endif - -#ifdef CONFIG_MACH_LANREADYFN522 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LANREADYFN522 -# endif -# define machine_is_lanreadyfn522() (machine_arch_type == MACH_TYPE_LANREADYFN522) -#else -# define machine_is_lanreadyfn522() (0) -#endif - -#ifdef CONFIG_MACH_ARMA37 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMA37 -# endif -# define machine_is_arma37() (machine_arch_type == MACH_TYPE_ARMA37) -#else -# define machine_is_arma37() (0) -#endif - -#ifdef CONFIG_MACH_MENDEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MENDEL -# endif -# define machine_is_mendel() (machine_arch_type == MACH_TYPE_MENDEL) -#else -# define machine_is_mendel() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ILIAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ILIAD -# endif -# define machine_is_pelco_iliad() (machine_arch_type == MACH_TYPE_PELCO_ILIAD) -#else -# define machine_is_pelco_iliad() (0) -#endif - -#ifdef CONFIG_MACH_UNIT2P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIT2P -# endif -# define machine_is_unit2p() (machine_arch_type == MACH_TYPE_UNIT2P) -#else -# define machine_is_unit2p() (0) -#endif - -#ifdef CONFIG_MACH_INC20OTTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INC20OTTER -# endif -# define machine_is_inc20otter() (machine_arch_type == MACH_TYPE_INC20OTTER) -#else -# define machine_is_inc20otter() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20EK -# endif -# define machine_is_at91sam9g20ek() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK) -#else -# define machine_is_at91sam9g20ek() (0) -#endif - -#ifdef CONFIG_MACH_STORCENTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STORCENTER -# endif -# define machine_is_sc_ge2() (machine_arch_type == MACH_TYPE_STORCENTER) -#else -# define machine_is_sc_ge2() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6410 -# endif -# define machine_is_smdk6410() (machine_arch_type == MACH_TYPE_SMDK6410) -#else -# define machine_is_smdk6410() (0) -#endif - -#ifdef CONFIG_MACH_U300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U300 -# endif -# define machine_is_u300() (machine_arch_type == MACH_TYPE_U300) -#else -# define machine_is_u300() (0) -#endif - -#ifdef CONFIG_MACH_U500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U500 -# endif -# define machine_is_u500() (machine_arch_type == MACH_TYPE_U500) -#else -# define machine_is_u500() (0) -#endif - -#ifdef CONFIG_MACH_DS9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS9260 -# endif -# define machine_is_ds9260() (machine_arch_type == MACH_TYPE_DS9260) -#else -# define machine_is_ds9260() (0) -#endif - -#ifdef CONFIG_MACH_RIVERROCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIVERROCK -# endif -# define machine_is_riverrock() (machine_arch_type == MACH_TYPE_RIVERROCK) -#else -# define machine_is_riverrock() (0) -#endif - -#ifdef CONFIG_MACH_SCIBATH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCIBATH -# endif -# define machine_is_scibath() (machine_arch_type == MACH_TYPE_SCIBATH) -#else -# define machine_is_scibath() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM7SE512EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM7SE512EK -# endif -# define machine_is_at91sam7se() (machine_arch_type == MACH_TYPE_AT91SAM7SE512EK) -#else -# define machine_is_at91sam7se() (0) -#endif - -#ifdef CONFIG_MACH_WRT350N_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WRT350N_V2 -# endif -# define machine_is_wrt350n_v2() (machine_arch_type == MACH_TYPE_WRT350N_V2) -#else -# define machine_is_wrt350n_v2() (0) -#endif - -#ifdef CONFIG_MACH_MULTIMEDIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTIMEDIA -# endif -# define machine_is_multimedia() (machine_arch_type == MACH_TYPE_MULTIMEDIA) -#else -# define machine_is_multimedia() (0) -#endif - -#ifdef CONFIG_MACH_MARVIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVIN -# endif -# define machine_is_marvin() (machine_arch_type == MACH_TYPE_MARVIN) -#else -# define machine_is_marvin() (0) -#endif - -#ifdef CONFIG_MACH_X500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_X500 -# endif -# define machine_is_x500() (machine_arch_type == MACH_TYPE_X500) -#else -# define machine_is_x500() (0) -#endif - -#ifdef CONFIG_MACH_AWLUG4LCU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AWLUG4LCU -# endif -# define machine_is_awlug4lcu() (machine_arch_type == MACH_TYPE_AWLUG4LCU) -#else -# define machine_is_awlug4lcu() (0) -#endif - -#ifdef CONFIG_MACH_PALERMOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALERMOC -# endif -# define machine_is_palermoc() (machine_arch_type == MACH_TYPE_PALERMOC) -#else -# define machine_is_palermoc() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_LDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_LDP -# endif -# define machine_is_omap_ldp() (machine_arch_type == MACH_TYPE_OMAP_LDP) -#else -# define machine_is_omap_ldp() (0) -#endif - -#ifdef CONFIG_MACH_IP500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IP500 -# endif -# define machine_is_ip500() (machine_arch_type == MACH_TYPE_IP500) -#else -# define machine_is_ip500() (0) -#endif - -#ifdef CONFIG_MACH_ASE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASE2 -# endif -# define machine_is_ase2() (machine_arch_type == MACH_TYPE_ASE2) -#else -# define machine_is_ase2() (0) -#endif - -#ifdef CONFIG_MACH_MX35EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35EVB -# endif -# define machine_is_mx35evb() (machine_arch_type == MACH_TYPE_MX35EVB) -#else -# define machine_is_mx35evb() (0) -#endif - -#ifdef CONFIG_MACH_AML_M8050 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M8050 -# endif -# define machine_is_aml_m8050() (machine_arch_type == MACH_TYPE_AML_M8050) -#else -# define machine_is_aml_m8050() (0) -#endif - -#ifdef CONFIG_MACH_MX35_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35_3DS -# endif -# define machine_is_mx35_3ds() (machine_arch_type == MACH_TYPE_MX35_3DS) -#else -# define machine_is_mx35_3ds() (0) -#endif - -#ifdef CONFIG_MACH_MARS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARS -# endif -# define machine_is_mars() (machine_arch_type == MACH_TYPE_MARS) -#else -# define machine_is_mars() (0) -#endif - -#ifdef CONFIG_MACH_NEUROS_OSD2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEUROS_OSD2 -# endif -# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2) -#else -# define machine_is_neuros_osd2() (0) -#endif - -#ifdef CONFIG_MACH_BADGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BADGER -# endif -# define machine_is_badger() (machine_arch_type == MACH_TYPE_BADGER) -#else -# define machine_is_badger() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS4WL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS4WL -# endif -# define machine_is_trizeps4wl() (machine_arch_type == MACH_TYPE_TRIZEPS4WL) -#else -# define machine_is_trizeps4wl() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS5 -# endif -# define machine_is_trizeps5() (machine_arch_type == MACH_TYPE_TRIZEPS5) -#else -# define machine_is_trizeps5() (0) -#endif - -#ifdef CONFIG_MACH_MARLIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARLIN -# endif -# define machine_is_marlin() (machine_arch_type == MACH_TYPE_MARLIN) -#else -# define machine_is_marlin() (0) -#endif - -#ifdef CONFIG_MACH_TS78XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS78XX -# endif -# define machine_is_ts78xx() (machine_arch_type == MACH_TYPE_TS78XX) -#else -# define machine_is_ts78xx() (0) -#endif - -#ifdef CONFIG_MACH_HPIPAQ214 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPIPAQ214 -# endif -# define machine_is_hpipaq214() (machine_arch_type == MACH_TYPE_HPIPAQ214) -#else -# define machine_is_hpipaq214() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940DCM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940DCM -# endif -# define machine_is_at572d940dcm() (machine_arch_type == MACH_TYPE_AT572D940DCM) -#else -# define machine_is_at572d940dcm() (0) -#endif - -#ifdef CONFIG_MACH_NE1BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NE1BOARD -# endif -# define machine_is_ne1board() (machine_arch_type == MACH_TYPE_NE1BOARD) -#else -# define machine_is_ne1board() (0) -#endif - -#ifdef CONFIG_MACH_ZANTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZANTE -# endif -# define machine_is_zante() (machine_arch_type == MACH_TYPE_ZANTE) -#else -# define machine_is_zante() (0) -#endif - -#ifdef CONFIG_MACH_SFFSDR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SFFSDR -# endif -# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR) -#else -# define machine_is_sffsdr() (0) -#endif - -#ifdef CONFIG_MACH_TW2662 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TW2662 -# endif -# define machine_is_tw2662() (machine_arch_type == MACH_TYPE_TW2662) -#else -# define machine_is_tw2662() (0) -#endif - -#ifdef CONFIG_MACH_VF10XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VF10XX -# endif -# define machine_is_vf10xx() (machine_arch_type == MACH_TYPE_VF10XX) -#else -# define machine_is_vf10xx() (0) -#endif - -#ifdef CONFIG_MACH_ZORAN43XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZORAN43XX -# endif -# define machine_is_zoran43xx() (machine_arch_type == MACH_TYPE_ZORAN43XX) -#else -# define machine_is_zoran43xx() (0) -#endif - -#ifdef CONFIG_MACH_SONIX926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONIX926 -# endif -# define machine_is_sonix926() (machine_arch_type == MACH_TYPE_SONIX926) -#else -# define machine_is_sonix926() (0) -#endif - -#ifdef CONFIG_MACH_CELESTIALSEMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CELESTIALSEMI -# endif -# define machine_is_celestialsemi() (machine_arch_type == MACH_TYPE_CELESTIALSEMI) -#else -# define machine_is_celestialsemi() (0) -#endif - -#ifdef CONFIG_MACH_CC9M2443JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9M2443JS -# endif -# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS) -#else -# define machine_is_cc9m2443js() (0) -#endif - -#ifdef CONFIG_MACH_TW5334 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TW5334 -# endif -# define machine_is_tw5334() (machine_arch_type == MACH_TYPE_TW5334) -#else -# define machine_is_tw5334() (0) -#endif - -#ifdef CONFIG_MACH_HTCARTEMIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCARTEMIS -# endif -# define machine_is_omap_htcartemis() (machine_arch_type == MACH_TYPE_HTCARTEMIS) -#else -# define machine_is_omap_htcartemis() (0) -#endif - -#ifdef CONFIG_MACH_NAL_HLITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAL_HLITE -# endif -# define machine_is_nal_hlite() (machine_arch_type == MACH_TYPE_NAL_HLITE) -#else -# define machine_is_nal_hlite() (0) -#endif - -#ifdef CONFIG_MACH_HTCVOGUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCVOGUE -# endif -# define machine_is_htcvogue() (machine_arch_type == MACH_TYPE_HTCVOGUE) -#else -# define machine_is_htcvogue() (0) -#endif - -#ifdef CONFIG_MACH_SMARTWEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTWEB -# endif -# define machine_is_smartweb() (machine_arch_type == MACH_TYPE_SMARTWEB) -#else -# define machine_is_smartweb() (0) -#endif - -#ifdef CONFIG_MACH_MV86XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV86XX -# endif -# define machine_is_mv86xx() (machine_arch_type == MACH_TYPE_MV86XX) -#else -# define machine_is_mv86xx() (0) -#endif - -#ifdef CONFIG_MACH_MV87XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV87XX -# endif -# define machine_is_mv87xx() (machine_arch_type == MACH_TYPE_MV87XX) -#else -# define machine_is_mv87xx() (0) -#endif - -#ifdef CONFIG_MACH_SONGYOUNGHO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONGYOUNGHO -# endif -# define machine_is_songyoungho() (machine_arch_type == MACH_TYPE_SONGYOUNGHO) -#else -# define machine_is_songyoungho() (0) -#endif - -#ifdef CONFIG_MACH_YOUNGHOTEMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YOUNGHOTEMA -# endif -# define machine_is_younghotema() (machine_arch_type == MACH_TYPE_YOUNGHOTEMA) -#else -# define machine_is_younghotema() (0) -#endif - -#ifdef CONFIG_MACH_PCM037 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM037 -# endif -# define machine_is_pcm037() (machine_arch_type == MACH_TYPE_PCM037) -#else -# define machine_is_pcm037() (0) -#endif - -#ifdef CONFIG_MACH_MMVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMVP -# endif -# define machine_is_mmvp() (machine_arch_type == MACH_TYPE_MMVP) -#else -# define machine_is_mmvp() (0) -#endif - -#ifdef CONFIG_MACH_MMAP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMAP -# endif -# define machine_is_mmap() (machine_arch_type == MACH_TYPE_MMAP) -#else -# define machine_is_mmap() (0) -#endif - -#ifdef CONFIG_MACH_PTID2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTID2410 -# endif -# define machine_is_ptid2410() (machine_arch_type == MACH_TYPE_PTID2410) -#else -# define machine_is_ptid2410() (0) -#endif - -#ifdef CONFIG_MACH_JAMES_926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JAMES_926 -# endif -# define machine_is_james_926() (machine_arch_type == MACH_TYPE_JAMES_926) -#else -# define machine_is_james_926() (0) -#endif - -#ifdef CONFIG_MACH_FM6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FM6000 -# endif -# define machine_is_fm6000() (machine_arch_type == MACH_TYPE_FM6000) -#else -# define machine_is_fm6000() (0) -#endif - -#ifdef CONFIG_MACH_DB88F6281_BP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB88F6281_BP -# endif -# define machine_is_db88f6281_bp() (machine_arch_type == MACH_TYPE_DB88F6281_BP) -#else -# define machine_is_db88f6281_bp() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6192_NAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6192_NAS -# endif -# define machine_is_rd88f6192_nas() (machine_arch_type == MACH_TYPE_RD88F6192_NAS) -#else -# define machine_is_rd88f6192_nas() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6281 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6281 -# endif -# define machine_is_rd88f6281() (machine_arch_type == MACH_TYPE_RD88F6281) -#else -# define machine_is_rd88f6281() (0) -#endif - -#ifdef CONFIG_MACH_DB78X00_BP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB78X00_BP -# endif -# define machine_is_db78x00_bp() (machine_arch_type == MACH_TYPE_DB78X00_BP) -#else -# define machine_is_db78x00_bp() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2416 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2416 -# endif -# define machine_is_smdk2416() (machine_arch_type == MACH_TYPE_SMDK2416) -#else -# define machine_is_smdk2416() (0) -#endif - -#ifdef CONFIG_MACH_OCE_SPIDER_SI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCE_SPIDER_SI -# endif -# define machine_is_oce_spider_si() (machine_arch_type == MACH_TYPE_OCE_SPIDER_SI) -#else -# define machine_is_oce_spider_si() (0) -#endif - -#ifdef CONFIG_MACH_OCE_SPIDER_SK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCE_SPIDER_SK -# endif -# define machine_is_oce_spider_sk() (machine_arch_type == MACH_TYPE_OCE_SPIDER_SK) -#else -# define machine_is_oce_spider_sk() (0) -#endif - -#ifdef CONFIG_MACH_ROVERN6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERN6 -# endif -# define machine_is_rovern6() (machine_arch_type == MACH_TYPE_ROVERN6) -#else -# define machine_is_rovern6() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_EVOLUTION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_EVOLUTION -# endif -# define machine_is_pelco_evolution() (machine_arch_type == MACH_TYPE_PELCO_EVOLUTION) -#else -# define machine_is_pelco_evolution() (0) -#endif - -#ifdef CONFIG_MACH_WBD111 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WBD111 -# endif -# define machine_is_wbd111() (machine_arch_type == MACH_TYPE_WBD111) -#else -# define machine_is_wbd111() (0) -#endif - -#ifdef CONFIG_MACH_ELARACPE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELARACPE -# endif -# define machine_is_elaracpe() (machine_arch_type == MACH_TYPE_ELARACPE) -#else -# define machine_is_elaracpe() (0) -#endif - -#ifdef CONFIG_MACH_MABV3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MABV3 -# endif -# define machine_is_mabv3() (machine_arch_type == MACH_TYPE_MABV3) -#else -# define machine_is_mabv3() (0) -#endif - -#ifdef CONFIG_MACH_MV2120 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV2120 -# endif -# define machine_is_mv2120() (machine_arch_type == MACH_TYPE_MV2120) -#else -# define machine_is_mv2120() (0) -#endif - -#ifdef CONFIG_MACH_CSB737 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB737 -# endif -# define machine_is_csb737() (machine_arch_type == MACH_TYPE_CSB737) -#else -# define machine_is_csb737() (0) -#endif - -#ifdef CONFIG_MACH_MX51_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_3DS -# endif -# define machine_is_mx51_3ds() (machine_arch_type == MACH_TYPE_MX51_3DS) -#else -# define machine_is_mx51_3ds() (0) -#endif - -#ifdef CONFIG_MACH_G900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G900 -# endif -# define machine_is_g900() (machine_arch_type == MACH_TYPE_G900) -#else -# define machine_is_g900() (0) -#endif - -#ifdef CONFIG_MACH_APF27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APF27 -# endif -# define machine_is_apf27() (machine_arch_type == MACH_TYPE_APF27) -#else -# define machine_is_apf27() (0) -#endif - -#ifdef CONFIG_MACH_GGUS2000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GGUS2000 -# endif -# define machine_is_ggus2000() (machine_arch_type == MACH_TYPE_GGUS2000) -#else -# define machine_is_ggus2000() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430_MIMIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430_MIMIC -# endif -# define machine_is_omap_2430_mimic() (machine_arch_type == MACH_TYPE_OMAP_2430_MIMIC) -#else -# define machine_is_omap_2430_mimic() (0) -#endif - -#ifdef CONFIG_MACH_IMX27LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27LITE -# endif -# define machine_is_imx27lite() (machine_arch_type == MACH_TYPE_IMX27LITE) -#else -# define machine_is_imx27lite() (0) -#endif - -#ifdef CONFIG_MACH_ALMEX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALMEX -# endif -# define machine_is_almex() (machine_arch_type == MACH_TYPE_ALMEX) -#else -# define machine_is_almex() (0) -#endif - -#ifdef CONFIG_MACH_CONTROL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONTROL -# endif -# define machine_is_control() (machine_arch_type == MACH_TYPE_CONTROL) -#else -# define machine_is_control() (0) -#endif - -#ifdef CONFIG_MACH_MBA2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MBA2410 -# endif -# define machine_is_mba2410() (machine_arch_type == MACH_TYPE_MBA2410) -#else -# define machine_is_mba2410() (0) -#endif - -#ifdef CONFIG_MACH_VOLCANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOLCANO -# endif -# define machine_is_volcano() (machine_arch_type == MACH_TYPE_VOLCANO) -#else -# define machine_is_volcano() (0) -#endif - -#ifdef CONFIG_MACH_ZENITH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZENITH -# endif -# define machine_is_zenith() (machine_arch_type == MACH_TYPE_ZENITH) -#else -# define machine_is_zenith() (0) -#endif - -#ifdef CONFIG_MACH_MUCHIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MUCHIP -# endif -# define machine_is_muchip() (machine_arch_type == MACH_TYPE_MUCHIP) -#else -# define machine_is_muchip() (0) -#endif - -#ifdef CONFIG_MACH_MAGELLAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGELLAN -# endif -# define machine_is_magellan() (machine_arch_type == MACH_TYPE_MAGELLAN) -#else -# define machine_is_magellan() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9260 -# endif -# define machine_is_usb_a9260() (machine_arch_type == MACH_TYPE_USB_A9260) -#else -# define machine_is_usb_a9260() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9263 -# endif -# define machine_is_usb_a9263() (machine_arch_type == MACH_TYPE_USB_A9263) -#else -# define machine_is_usb_a9263() (0) -#endif - -#ifdef CONFIG_MACH_QIL_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QIL_A9260 -# endif -# define machine_is_qil_a9260() (machine_arch_type == MACH_TYPE_QIL_A9260) -#else -# define machine_is_qil_a9260() (0) -#endif - -#ifdef CONFIG_MACH_CME9210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CME9210 -# endif -# define machine_is_cme9210() (machine_arch_type == MACH_TYPE_CME9210) -#else -# define machine_is_cme9210() (0) -#endif - -#ifdef CONFIG_MACH_HCZH4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HCZH4 -# endif -# define machine_is_hczh4() (machine_arch_type == MACH_TYPE_HCZH4) -#else -# define machine_is_hczh4() (0) -#endif - -#ifdef CONFIG_MACH_SPEARBASIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEARBASIC -# endif -# define machine_is_spearbasic() (machine_arch_type == MACH_TYPE_SPEARBASIC) -#else -# define machine_is_spearbasic() (0) -#endif - -#ifdef CONFIG_MACH_DEP2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEP2440 -# endif -# define machine_is_dep2440() (machine_arch_type == MACH_TYPE_DEP2440) -#else -# define machine_is_dep2440() (0) -#endif - -#ifdef CONFIG_MACH_HDL_GXR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_GXR -# endif -# define machine_is_hdl_gxr() (machine_arch_type == MACH_TYPE_HDL_GXR) -#else -# define machine_is_hdl_gxr() (0) -#endif - -#ifdef CONFIG_MACH_HDL_GT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_GT -# endif -# define machine_is_hdl_gt() (machine_arch_type == MACH_TYPE_HDL_GT) -#else -# define machine_is_hdl_gt() (0) -#endif - -#ifdef CONFIG_MACH_HDL_4G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_4G -# endif -# define machine_is_hdl_4g() (machine_arch_type == MACH_TYPE_HDL_4G) -#else -# define machine_is_hdl_4g() (0) -#endif - -#ifdef CONFIG_MACH_S3C6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C6000 -# endif -# define machine_is_s3c6000() (machine_arch_type == MACH_TYPE_S3C6000) -#else -# define machine_is_s3c6000() (0) -#endif - -#ifdef CONFIG_MACH_MMSP2_MDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMSP2_MDK -# endif -# define machine_is_mmsp2_mdk() (machine_arch_type == MACH_TYPE_MMSP2_MDK) -#else -# define machine_is_mmsp2_mdk() (0) -#endif - -#ifdef CONFIG_MACH_MPX220 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPX220 -# endif -# define machine_is_mpx220() (machine_arch_type == MACH_TYPE_MPX220) -#else -# define machine_is_mpx220() (0) -#endif - -#ifdef CONFIG_MACH_KZM_ARM11_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KZM_ARM11_01 -# endif -# define machine_is_kzm_arm11_01() (machine_arch_type == MACH_TYPE_KZM_ARM11_01) -#else -# define machine_is_kzm_arm11_01() (0) -#endif - -#ifdef CONFIG_MACH_HTC_POLARIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_POLARIS -# endif -# define machine_is_htc_polaris() (machine_arch_type == MACH_TYPE_HTC_POLARIS) -#else -# define machine_is_htc_polaris() (0) -#endif - -#ifdef CONFIG_MACH_HTC_KAISER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_KAISER -# endif -# define machine_is_htc_kaiser() (machine_arch_type == MACH_TYPE_HTC_KAISER) -#else -# define machine_is_htc_kaiser() (0) -#endif - -#ifdef CONFIG_MACH_LG_KS20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LG_KS20 -# endif -# define machine_is_lg_ks20() (machine_arch_type == MACH_TYPE_LG_KS20) -#else -# define machine_is_lg_ks20() (0) -#endif - -#ifdef CONFIG_MACH_HHGPS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HHGPS -# endif -# define machine_is_hhgps() (machine_arch_type == MACH_TYPE_HHGPS) -#else -# define machine_is_hhgps() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N810_WIMAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N810_WIMAX -# endif -# define machine_is_nokia_n810_wimax() (machine_arch_type == MACH_TYPE_NOKIA_N810_WIMAX) -#else -# define machine_is_nokia_n810_wimax() (0) -#endif - -#ifdef CONFIG_MACH_INSIGHT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INSIGHT -# endif -# define machine_is_insight() (machine_arch_type == MACH_TYPE_INSIGHT) -#else -# define machine_is_insight() (0) -#endif - -#ifdef CONFIG_MACH_SAPPHIRE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAPPHIRE -# endif -# define machine_is_sapphire() (machine_arch_type == MACH_TYPE_SAPPHIRE) -#else -# define machine_is_sapphire() (0) -#endif - -#ifdef CONFIG_MACH_CSB637XO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB637XO -# endif -# define machine_is_csb637xo() (machine_arch_type == MACH_TYPE_CSB637XO) -#else -# define machine_is_csb637xo() (0) -#endif - -#ifdef CONFIG_MACH_EVISIONG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EVISIONG -# endif -# define machine_is_evisiong() (machine_arch_type == MACH_TYPE_EVISIONG) -#else -# define machine_is_evisiong() (0) -#endif - -#ifdef CONFIG_MACH_STMP37XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP37XX -# endif -# define machine_is_stmp37xx() (machine_arch_type == MACH_TYPE_STMP37XX) -#else -# define machine_is_stmp37xx() (0) -#endif - -#ifdef CONFIG_MACH_STMP378X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP378X -# endif -# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP378X) -#else -# define machine_is_stmp378x() (0) -#endif - -#ifdef CONFIG_MACH_TNT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNT -# endif -# define machine_is_tnt() (machine_arch_type == MACH_TYPE_TNT) -#else -# define machine_is_tnt() (0) -#endif - -#ifdef CONFIG_MACH_TBXT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TBXT -# endif -# define machine_is_tbxt() (machine_arch_type == MACH_TYPE_TBXT) -#else -# define machine_is_tbxt() (0) -#endif - -#ifdef CONFIG_MACH_PLAYMATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLAYMATE -# endif -# define machine_is_playmate() (machine_arch_type == MACH_TYPE_PLAYMATE) -#else -# define machine_is_playmate() (0) -#endif - -#ifdef CONFIG_MACH_PNS10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNS10 -# endif -# define machine_is_pns10() (machine_arch_type == MACH_TYPE_PNS10) -#else -# define machine_is_pns10() (0) -#endif - -#ifdef CONFIG_MACH_EZNAVI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZNAVI -# endif -# define machine_is_eznavi() (machine_arch_type == MACH_TYPE_EZNAVI) -#else -# define machine_is_eznavi() (0) -#endif - -#ifdef CONFIG_MACH_PS4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PS4000 -# endif -# define machine_is_ps4000() (machine_arch_type == MACH_TYPE_PS4000) -#else -# define machine_is_ps4000() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A780 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A780 -# endif -# define machine_is_ezx_a780() (machine_arch_type == MACH_TYPE_EZX_A780) -#else -# define machine_is_ezx_a780() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E680 -# endif -# define machine_is_ezx_e680() (machine_arch_type == MACH_TYPE_EZX_E680) -#else -# define machine_is_ezx_e680() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A1200 -# endif -# define machine_is_ezx_a1200() (machine_arch_type == MACH_TYPE_EZX_A1200) -#else -# define machine_is_ezx_a1200() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E6 -# endif -# define machine_is_ezx_e6() (machine_arch_type == MACH_TYPE_EZX_E6) -#else -# define machine_is_ezx_e6() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E2 -# endif -# define machine_is_ezx_e2() (machine_arch_type == MACH_TYPE_EZX_E2) -#else -# define machine_is_ezx_e2() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A910 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A910 -# endif -# define machine_is_ezx_a910() (machine_arch_type == MACH_TYPE_EZX_A910) -#else -# define machine_is_ezx_a910() (0) -#endif - -#ifdef CONFIG_MACH_CWMX31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWMX31 -# endif -# define machine_is_cwmx31() (machine_arch_type == MACH_TYPE_CWMX31) -#else -# define machine_is_cwmx31() (0) -#endif - -#ifdef CONFIG_MACH_SL2312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SL2312 -# endif -# define machine_is_sl2312() (machine_arch_type == MACH_TYPE_SL2312) -#else -# define machine_is_sl2312() (0) -#endif - -#ifdef CONFIG_MACH_BLENNY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLENNY -# endif -# define machine_is_blenny() (machine_arch_type == MACH_TYPE_BLENNY) -#else -# define machine_is_blenny() (0) -#endif - -#ifdef CONFIG_MACH_DS107 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DS107 -# endif -# define machine_is_ds107() (machine_arch_type == MACH_TYPE_DS107) -#else -# define machine_is_ds107() (0) -#endif - -#ifdef CONFIG_MACH_DSX07 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSX07 -# endif -# define machine_is_dsx07() (machine_arch_type == MACH_TYPE_DSX07) -#else -# define machine_is_dsx07() (0) -#endif - -#ifdef CONFIG_MACH_PICOCOM1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOCOM1 -# endif -# define machine_is_picocom1() (machine_arch_type == MACH_TYPE_PICOCOM1) -#else -# define machine_is_picocom1() (0) -#endif - -#ifdef CONFIG_MACH_LYNX_WOLVERINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LYNX_WOLVERINE -# endif -# define machine_is_lynx_wolverine() (machine_arch_type == MACH_TYPE_LYNX_WOLVERINE) -#else -# define machine_is_lynx_wolverine() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_SC19 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_SC19 -# endif -# define machine_is_ubisys_p9_sc19() (machine_arch_type == MACH_TYPE_UBISYS_P9_SC19) -#else -# define machine_is_ubisys_p9_sc19() (0) -#endif - -#ifdef CONFIG_MACH_KRATOS_LOW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KRATOS_LOW -# endif -# define machine_is_kratos_low() (machine_arch_type == MACH_TYPE_KRATOS_LOW) -#else -# define machine_is_kratos_low() (0) -#endif - -#ifdef CONFIG_MACH_M700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M700 -# endif -# define machine_is_m700() (machine_arch_type == MACH_TYPE_M700) -#else -# define machine_is_m700() (0) -#endif - -#ifdef CONFIG_MACH_EDMINI_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDMINI_V2 -# endif -# define machine_is_edmini_v2() (machine_arch_type == MACH_TYPE_EDMINI_V2) -#else -# define machine_is_edmini_v2() (0) -#endif - -#ifdef CONFIG_MACH_ZIPIT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIPIT2 -# endif -# define machine_is_zipit2() (machine_arch_type == MACH_TYPE_ZIPIT2) -#else -# define machine_is_zipit2() (0) -#endif - -#ifdef CONFIG_MACH_HSLFEMTOCELL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HSLFEMTOCELL -# endif -# define machine_is_hslfemtocell() (machine_arch_type == MACH_TYPE_HSLFEMTOCELL) -#else -# define machine_is_hslfemtocell() (0) -#endif - -#ifdef CONFIG_MACH_DAINTREE_AT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAINTREE_AT91 -# endif -# define machine_is_daintree_at91() (machine_arch_type == MACH_TYPE_DAINTREE_AT91) -#else -# define machine_is_daintree_at91() (0) -#endif - -#ifdef CONFIG_MACH_SG560USB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG560USB -# endif -# define machine_is_sg560usb() (machine_arch_type == MACH_TYPE_SG560USB) -#else -# define machine_is_sg560usb() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_PANDORA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_PANDORA -# endif -# define machine_is_omap3_pandora() (machine_arch_type == MACH_TYPE_OMAP3_PANDORA) -#else -# define machine_is_omap3_pandora() (0) -#endif - -#ifdef CONFIG_MACH_USR8200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USR8200 -# endif -# define machine_is_usr8200() (machine_arch_type == MACH_TYPE_USR8200) -#else -# define machine_is_usr8200() (0) -#endif - -#ifdef CONFIG_MACH_S1S65K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S1S65K -# endif -# define machine_is_s1s65k() (machine_arch_type == MACH_TYPE_S1S65K) -#else -# define machine_is_s1s65k() (0) -#endif - -#ifdef CONFIG_MACH_S2S65A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S2S65A -# endif -# define machine_is_s2s65a() (machine_arch_type == MACH_TYPE_S2S65A) -#else -# define machine_is_s2s65a() (0) -#endif - -#ifdef CONFIG_MACH_ICORE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICORE -# endif -# define machine_is_icore() (machine_arch_type == MACH_TYPE_ICORE) -#else -# define machine_is_icore() (0) -#endif - -#ifdef CONFIG_MACH_MSS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSS2 -# endif -# define machine_is_mss2() (machine_arch_type == MACH_TYPE_MSS2) -#else -# define machine_is_mss2() (0) -#endif - -#ifdef CONFIG_MACH_BELMONT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BELMONT -# endif -# define machine_is_belmont() (machine_arch_type == MACH_TYPE_BELMONT) -#else -# define machine_is_belmont() (0) -#endif - -#ifdef CONFIG_MACH_ASUSP525 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASUSP525 -# endif -# define machine_is_asusp525() (machine_arch_type == MACH_TYPE_ASUSP525) -#else -# define machine_is_asusp525() (0) -#endif - -#ifdef CONFIG_MACH_LB88RC8480 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LB88RC8480 -# endif -# define machine_is_lb88rc8480() (machine_arch_type == MACH_TYPE_LB88RC8480) -#else -# define machine_is_lb88rc8480() (0) -#endif - -#ifdef CONFIG_MACH_HIPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIPXA -# endif -# define machine_is_hipxa() (machine_arch_type == MACH_TYPE_HIPXA) -#else -# define machine_is_hipxa() (0) -#endif - -#ifdef CONFIG_MACH_MX25_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX25_3DS -# endif -# define machine_is_mx25_3ds() (machine_arch_type == MACH_TYPE_MX25_3DS) -#else -# define machine_is_mx25_3ds() (0) -#endif - -#ifdef CONFIG_MACH_M800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M800 -# endif -# define machine_is_m800() (machine_arch_type == MACH_TYPE_M800) -#else -# define machine_is_m800() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3530_LV_SOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3530_LV_SOM -# endif -# define machine_is_omap3530_lv_som() (machine_arch_type == MACH_TYPE_OMAP3530_LV_SOM) -#else -# define machine_is_omap3530_lv_som() (0) -#endif - -#ifdef CONFIG_MACH_PRIMA_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRIMA_EVB -# endif -# define machine_is_prima_evb() (machine_arch_type == MACH_TYPE_PRIMA_EVB) -#else -# define machine_is_prima_evb() (0) -#endif - -#ifdef CONFIG_MACH_MX31BT1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31BT1 -# endif -# define machine_is_mx31bt1() (machine_arch_type == MACH_TYPE_MX31BT1) -#else -# define machine_is_mx31bt1() (0) -#endif - -#ifdef CONFIG_MACH_ATLAS4_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATLAS4_EVB -# endif -# define machine_is_atlas4_evb() (machine_arch_type == MACH_TYPE_ATLAS4_EVB) -#else -# define machine_is_atlas4_evb() (0) -#endif - -#ifdef CONFIG_MACH_MX31CICADA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31CICADA -# endif -# define machine_is_mx31cicada() (machine_arch_type == MACH_TYPE_MX31CICADA) -#else -# define machine_is_mx31cicada() (0) -#endif - -#ifdef CONFIG_MACH_MI424WR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MI424WR -# endif -# define machine_is_mi424wr() (machine_arch_type == MACH_TYPE_MI424WR) -#else -# define machine_is_mi424wr() (0) -#endif - -#ifdef CONFIG_MACH_AXS_ULTRAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXS_ULTRAX -# endif -# define machine_is_axs_ultrax() (machine_arch_type == MACH_TYPE_AXS_ULTRAX) -#else -# define machine_is_axs_ultrax() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940DEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940DEB -# endif -# define machine_is_at572d940deb() (machine_arch_type == MACH_TYPE_AT572D940DEB) -#else -# define machine_is_at572d940deb() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DA830_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DA830_EVM -# endif -# define machine_is_davinci_da830_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM) -#else -# define machine_is_davinci_da830_evm() (0) -#endif - -#ifdef CONFIG_MACH_EP9302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EP9302 -# endif -# define machine_is_ep9302() (machine_arch_type == MACH_TYPE_EP9302) -#else -# define machine_is_ep9302() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940HFEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940HFEB -# endif -# define machine_is_at572d940hfek() (machine_arch_type == MACH_TYPE_AT572D940HFEB) -#else -# define machine_is_at572d940hfek() (0) -#endif - -#ifdef CONFIG_MACH_CYBOOK3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBOOK3 -# endif -# define machine_is_cybook3() (machine_arch_type == MACH_TYPE_CYBOOK3) -#else -# define machine_is_cybook3() (0) -#endif - -#ifdef CONFIG_MACH_WDG002 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WDG002 -# endif -# define machine_is_wdg002() (machine_arch_type == MACH_TYPE_WDG002) -#else -# define machine_is_wdg002() (0) -#endif - -#ifdef CONFIG_MACH_SG560ADSL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SG560ADSL -# endif -# define machine_is_sg560adsl() (machine_arch_type == MACH_TYPE_SG560ADSL) -#else -# define machine_is_sg560adsl() (0) -#endif - -#ifdef CONFIG_MACH_NEXTIO_N2800_ICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXTIO_N2800_ICA -# endif -# define machine_is_nextio_n2800_ica() (machine_arch_type == MACH_TYPE_NEXTIO_N2800_ICA) -#else -# define machine_is_nextio_n2800_ica() (0) -#endif - -#ifdef CONFIG_MACH_DOVE_DB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOVE_DB -# endif -# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_DOVE_DB) -#else -# define machine_is_dove_db() (0) -#endif - -#ifdef CONFIG_MACH_MARVELL_NEWDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVELL_NEWDB -# endif -# define machine_is_marvell_newdb() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) -#else -# define machine_is_marvell_newdb() (0) -#endif - -#ifdef CONFIG_MACH_VANDIHUD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VANDIHUD -# endif -# define machine_is_vandihud() (machine_arch_type == MACH_TYPE_VANDIHUD) -#else -# define machine_is_vandihud() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_E8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_E8 -# endif -# define machine_is_magx_e8() (machine_arch_type == MACH_TYPE_MAGX_E8) -#else -# define machine_is_magx_e8() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_Z6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_Z6 -# endif -# define machine_is_magx_z6() (machine_arch_type == MACH_TYPE_MAGX_Z6) -#else -# define machine_is_magx_z6() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_V8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_V8 -# endif -# define machine_is_magx_v8() (machine_arch_type == MACH_TYPE_MAGX_V8) -#else -# define machine_is_magx_v8() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_U9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_U9 -# endif -# define machine_is_magx_u9() (machine_arch_type == MACH_TYPE_MAGX_U9) -#else -# define machine_is_magx_u9() (0) -#endif - -#ifdef CONFIG_MACH_TOUGHCF08 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOUGHCF08 -# endif -# define machine_is_toughcf08() (machine_arch_type == MACH_TYPE_TOUGHCF08) -#else -# define machine_is_toughcf08() (0) -#endif - -#ifdef CONFIG_MACH_ZW4400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZW4400 -# endif -# define machine_is_zw4400() (machine_arch_type == MACH_TYPE_ZW4400) -#else -# define machine_is_zw4400() (0) -#endif - -#ifdef CONFIG_MACH_MARAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARAT91 -# endif -# define machine_is_marat91() (machine_arch_type == MACH_TYPE_MARAT91) -#else -# define machine_is_marat91() (0) -#endif - -#ifdef CONFIG_MACH_OVERO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OVERO -# endif -# define machine_is_overo() (machine_arch_type == MACH_TYPE_OVERO) -#else -# define machine_is_overo() (0) -#endif - -#ifdef CONFIG_MACH_AT2440EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT2440EVB -# endif -# define machine_is_at2440evb() (machine_arch_type == MACH_TYPE_AT2440EVB) -#else -# define machine_is_at2440evb() (0) -#endif - -#ifdef CONFIG_MACH_NEOCORE926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEOCORE926 -# endif -# define machine_is_neocore926() (machine_arch_type == MACH_TYPE_NEOCORE926) -#else -# define machine_is_neocore926() (0) -#endif - -#ifdef CONFIG_MACH_WNR854T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WNR854T -# endif -# define machine_is_wnr854t() (machine_arch_type == MACH_TYPE_WNR854T) -#else -# define machine_is_wnr854t() (0) -#endif - -#ifdef CONFIG_MACH_IMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27 -# endif -# define machine_is_imx27() (machine_arch_type == MACH_TYPE_IMX27) -#else -# define machine_is_imx27() (0) -#endif - -#ifdef CONFIG_MACH_MOOSE_DB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOOSE_DB -# endif -# define machine_is_moose_db() (machine_arch_type == MACH_TYPE_MOOSE_DB) -#else -# define machine_is_moose_db() (0) -#endif - -#ifdef CONFIG_MACH_FAB4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FAB4 -# endif -# define machine_is_fab4() (machine_arch_type == MACH_TYPE_FAB4) -#else -# define machine_is_fab4() (0) -#endif - -#ifdef CONFIG_MACH_HTCDIAMOND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCDIAMOND -# endif -# define machine_is_htcdiamond() (machine_arch_type == MACH_TYPE_HTCDIAMOND) -#else -# define machine_is_htcdiamond() (0) -#endif - -#ifdef CONFIG_MACH_FIONA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FIONA -# endif -# define machine_is_fiona() (machine_arch_type == MACH_TYPE_FIONA) -#else -# define machine_is_fiona() (0) -#endif - -#ifdef CONFIG_MACH_MXC30030_X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC30030_X -# endif -# define machine_is_mxc30030_x() (machine_arch_type == MACH_TYPE_MXC30030_X) -#else -# define machine_is_mxc30030_x() (0) -#endif - -#ifdef CONFIG_MACH_BMP1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BMP1000 -# endif -# define machine_is_bmp1000() (machine_arch_type == MACH_TYPE_BMP1000) -#else -# define machine_is_bmp1000() (0) -#endif - -#ifdef CONFIG_MACH_LOGI9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGI9200 -# endif -# define machine_is_logi9200() (machine_arch_type == MACH_TYPE_LOGI9200) -#else -# define machine_is_logi9200() (0) -#endif - -#ifdef CONFIG_MACH_TQMA31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TQMA31 -# endif -# define machine_is_tqma31() (machine_arch_type == MACH_TYPE_TQMA31) -#else -# define machine_is_tqma31() (0) -#endif - -#ifdef CONFIG_MACH_CCW9P9215JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9P9215JS -# endif -# define machine_is_ccw9p9215js() (machine_arch_type == MACH_TYPE_CCW9P9215JS) -#else -# define machine_is_ccw9p9215js() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5181L_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5181L_GE -# endif -# define machine_is_rd88f5181l_ge() (machine_arch_type == MACH_TYPE_RD88F5181L_GE) -#else -# define machine_is_rd88f5181l_ge() (0) -#endif - -#ifdef CONFIG_MACH_SIFMAIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIFMAIN -# endif -# define machine_is_sifmain() (machine_arch_type == MACH_TYPE_SIFMAIN) -#else -# define machine_is_sifmain() (0) -#endif - -#ifdef CONFIG_MACH_SAM9_L9261 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9_L9261 -# endif -# define machine_is_sam9_l9261() (machine_arch_type == MACH_TYPE_SAM9_L9261) -#else -# define machine_is_sam9_l9261() (0) -#endif - -#ifdef CONFIG_MACH_CC9M2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9M2443 -# endif -# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443) -#else -# define machine_is_cc9m2443() (0) -#endif - -#ifdef CONFIG_MACH_XARIA300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XARIA300 -# endif -# define machine_is_xaria300() (machine_arch_type == MACH_TYPE_XARIA300) -#else -# define machine_is_xaria300() (0) -#endif - -#ifdef CONFIG_MACH_IT9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IT9200 -# endif -# define machine_is_it9200() (machine_arch_type == MACH_TYPE_IT9200) -#else -# define machine_is_it9200() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5181L_FXO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5181L_FXO -# endif -# define machine_is_rd88f5181l_fxo() (machine_arch_type == MACH_TYPE_RD88F5181L_FXO) -#else -# define machine_is_rd88f5181l_fxo() (0) -#endif - -#ifdef CONFIG_MACH_KRISS_SENSOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KRISS_SENSOR -# endif -# define machine_is_kriss_sensor() (machine_arch_type == MACH_TYPE_KRISS_SENSOR) -#else -# define machine_is_kriss_sensor() (0) -#endif - -#ifdef CONFIG_MACH_PILZ_PMI5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PILZ_PMI5 -# endif -# define machine_is_pilz_pmi5() (machine_arch_type == MACH_TYPE_PILZ_PMI5) -#else -# define machine_is_pilz_pmi5() (0) -#endif - -#ifdef CONFIG_MACH_JADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADE -# endif -# define machine_is_jade() (machine_arch_type == MACH_TYPE_JADE) -#else -# define machine_is_jade() (0) -#endif - -#ifdef CONFIG_MACH_KS8695_SOFTPLC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KS8695_SOFTPLC -# endif -# define machine_is_ks8695_softplc() (machine_arch_type == MACH_TYPE_KS8695_SOFTPLC) -#else -# define machine_is_ks8695_softplc() (0) -#endif - -#ifdef CONFIG_MACH_GPRISC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GPRISC3 -# endif -# define machine_is_gprisc3() (machine_arch_type == MACH_TYPE_GPRISC3) -#else -# define machine_is_gprisc3() (0) -#endif - -#ifdef CONFIG_MACH_STAMP9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAMP9G20 -# endif -# define machine_is_stamp9g20() (machine_arch_type == MACH_TYPE_STAMP9G20) -#else -# define machine_is_stamp9g20() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6430 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6430 -# endif -# define machine_is_smdk6430() (machine_arch_type == MACH_TYPE_SMDK6430) -#else -# define machine_is_smdk6430() (0) -#endif - -#ifdef CONFIG_MACH_SMDKC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKC100 -# endif -# define machine_is_smdkc100() (machine_arch_type == MACH_TYPE_SMDKC100) -#else -# define machine_is_smdkc100() (0) -#endif - -#ifdef CONFIG_MACH_TAVOREVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAVOREVB -# endif -# define machine_is_tavorevb() (machine_arch_type == MACH_TYPE_TAVOREVB) -#else -# define machine_is_tavorevb() (0) -#endif - -#ifdef CONFIG_MACH_SAAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAAR -# endif -# define machine_is_saar() (machine_arch_type == MACH_TYPE_SAAR) -#else -# define machine_is_saar() (0) -#endif - -#ifdef CONFIG_MACH_DEISTER_EYECAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTER_EYECAM -# endif -# define machine_is_deister_eyecam() (machine_arch_type == MACH_TYPE_DEISTER_EYECAM) -#else -# define machine_is_deister_eyecam() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9M10G45EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9M10G45EK -# endif -# define machine_is_at91sam9m10g45ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK) -#else -# define machine_is_at91sam9m10g45ek() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_PRODUO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_PRODUO -# endif -# define machine_is_linkstation_produo() (machine_arch_type == MACH_TYPE_LINKSTATION_PRODUO) -#else -# define machine_is_linkstation_produo() (0) -#endif - -#ifdef CONFIG_MACH_HIT_B0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIT_B0 -# endif -# define machine_is_hit_b0() (machine_arch_type == MACH_TYPE_HIT_B0) -#else -# define machine_is_hit_b0() (0) -#endif - -#ifdef CONFIG_MACH_ADX_RMU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADX_RMU -# endif -# define machine_is_adx_rmu() (machine_arch_type == MACH_TYPE_ADX_RMU) -#else -# define machine_is_adx_rmu() (0) -#endif - -#ifdef CONFIG_MACH_XG_CPE_MAIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XG_CPE_MAIN -# endif -# define machine_is_xg_cpe_main() (machine_arch_type == MACH_TYPE_XG_CPE_MAIN) -#else -# define machine_is_xg_cpe_main() (0) -#endif - -#ifdef CONFIG_MACH_EDB9407A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9407A -# endif -# define machine_is_edb9407a() (machine_arch_type == MACH_TYPE_EDB9407A) -#else -# define machine_is_edb9407a() (0) -#endif - -#ifdef CONFIG_MACH_DTB9608 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DTB9608 -# endif -# define machine_is_dtb9608() (machine_arch_type == MACH_TYPE_DTB9608) -#else -# define machine_is_dtb9608() (0) -#endif - -#ifdef CONFIG_MACH_EM104V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM104V1 -# endif -# define machine_is_em104v1() (machine_arch_type == MACH_TYPE_EM104V1) -#else -# define machine_is_em104v1() (0) -#endif - -#ifdef CONFIG_MACH_DEMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEMO -# endif -# define machine_is_demo() (machine_arch_type == MACH_TYPE_DEMO) -#else -# define machine_is_demo() (0) -#endif - -#ifdef CONFIG_MACH_LOGI9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGI9260 -# endif -# define machine_is_logi9260() (machine_arch_type == MACH_TYPE_LOGI9260) -#else -# define machine_is_logi9260() (0) -#endif - -#ifdef CONFIG_MACH_MX31_EXM32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31_EXM32 -# endif -# define machine_is_mx31_exm32() (machine_arch_type == MACH_TYPE_MX31_EXM32) -#else -# define machine_is_mx31_exm32() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9G20 -# endif -# define machine_is_usb_a9g20() (machine_arch_type == MACH_TYPE_USB_A9G20) -#else -# define machine_is_usb_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_PICPROJE2008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICPROJE2008 -# endif -# define machine_is_picproje2008() (machine_arch_type == MACH_TYPE_PICPROJE2008) -#else -# define machine_is_picproje2008() (0) -#endif - -#ifdef CONFIG_MACH_CS_E9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS_E9315 -# endif -# define machine_is_cs_e9315() (machine_arch_type == MACH_TYPE_CS_E9315) -#else -# define machine_is_cs_e9315() (0) -#endif - -#ifdef CONFIG_MACH_QIL_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QIL_A9G20 -# endif -# define machine_is_qil_a9g20() (machine_arch_type == MACH_TYPE_QIL_A9G20) -#else -# define machine_is_qil_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_SHA_PON020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHA_PON020 -# endif -# define machine_is_sha_pon020() (machine_arch_type == MACH_TYPE_SHA_PON020) -#else -# define machine_is_sha_pon020() (0) -#endif - -#ifdef CONFIG_MACH_NAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAD -# endif -# define machine_is_nad() (machine_arch_type == MACH_TYPE_NAD) -#else -# define machine_is_nad() (0) -#endif - -#ifdef CONFIG_MACH_SBC35_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC35_A9260 -# endif -# define machine_is_sbc35_a9260() (machine_arch_type == MACH_TYPE_SBC35_A9260) -#else -# define machine_is_sbc35_a9260() (0) -#endif - -#ifdef CONFIG_MACH_SBC35_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC35_A9G20 -# endif -# define machine_is_sbc35_a9g20() (machine_arch_type == MACH_TYPE_SBC35_A9G20) -#else -# define machine_is_sbc35_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_BEGINNING -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_BEGINNING -# endif -# define machine_is_davinci_beginning() (machine_arch_type == MACH_TYPE_DAVINCI_BEGINNING) -#else -# define machine_is_davinci_beginning() (0) -#endif - -#ifdef CONFIG_MACH_UWC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UWC -# endif -# define machine_is_uwc() (machine_arch_type == MACH_TYPE_UWC) -#else -# define machine_is_uwc() (0) -#endif - -#ifdef CONFIG_MACH_MXLADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXLADS -# endif -# define machine_is_mxlads() (machine_arch_type == MACH_TYPE_MXLADS) -#else -# define machine_is_mxlads() (0) -#endif - -#ifdef CONFIG_MACH_HTCNIKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCNIKE -# endif -# define machine_is_htcnike() (machine_arch_type == MACH_TYPE_HTCNIKE) -#else -# define machine_is_htcnike() (0) -#endif - -#ifdef CONFIG_MACH_DEISTER_PXA270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEISTER_PXA270 -# endif -# define machine_is_deister_pxa270() (machine_arch_type == MACH_TYPE_DEISTER_PXA270) -#else -# define machine_is_deister_pxa270() (0) -#endif - -#ifdef CONFIG_MACH_CME9210JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CME9210JS -# endif -# define machine_is_cme9210js() (machine_arch_type == MACH_TYPE_CME9210JS) -#else -# define machine_is_cme9210js() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360 -# endif -# define machine_is_cc9p9360() (machine_arch_type == MACH_TYPE_CC9P9360) -#else -# define machine_is_cc9p9360() (0) -#endif - -#ifdef CONFIG_MACH_MOCHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOCHA -# endif -# define machine_is_mocha() (machine_arch_type == MACH_TYPE_MOCHA) -#else -# define machine_is_mocha() (0) -#endif - -#ifdef CONFIG_MACH_WAPD170AG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WAPD170AG -# endif -# define machine_is_wapd170ag() (machine_arch_type == MACH_TYPE_WAPD170AG) -#else -# define machine_is_wapd170ag() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_MINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_MINI -# endif -# define machine_is_linkstation_mini() (machine_arch_type == MACH_TYPE_LINKSTATION_MINI) -#else -# define machine_is_linkstation_mini() (0) -#endif - -#ifdef CONFIG_MACH_AFEB9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AFEB9260 -# endif -# define machine_is_afeb9260() (machine_arch_type == MACH_TYPE_AFEB9260) -#else -# define machine_is_afeb9260() (0) -#endif - -#ifdef CONFIG_MACH_W90X900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90X900 -# endif -# define machine_is_w90x900() (machine_arch_type == MACH_TYPE_W90X900) -#else -# define machine_is_w90x900() (0) -#endif - -#ifdef CONFIG_MACH_W90X700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90X700 -# endif -# define machine_is_w90x700() (machine_arch_type == MACH_TYPE_W90X700) -#else -# define machine_is_w90x700() (0) -#endif - -#ifdef CONFIG_MACH_KT300IP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KT300IP -# endif -# define machine_is_kt300ip() (machine_arch_type == MACH_TYPE_KT300IP) -#else -# define machine_is_kt300ip() (0) -#endif - -#ifdef CONFIG_MACH_KT300IP_G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KT300IP_G20 -# endif -# define machine_is_kt300ip_g20() (machine_arch_type == MACH_TYPE_KT300IP_G20) -#else -# define machine_is_kt300ip_g20() (0) -#endif - -#ifdef CONFIG_MACH_SRCM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SRCM -# endif -# define machine_is_srcm() (machine_arch_type == MACH_TYPE_SRCM) -#else -# define machine_is_srcm() (0) -#endif - -#ifdef CONFIG_MACH_WLNX_9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WLNX_9260 -# endif -# define machine_is_wlnx_9260() (machine_arch_type == MACH_TYPE_WLNX_9260) -#else -# define machine_is_wlnx_9260() (0) -#endif - -#ifdef CONFIG_MACH_OPENMOKO_GTA03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENMOKO_GTA03 -# endif -# define machine_is_openmoko_gta03() (machine_arch_type == MACH_TYPE_OPENMOKO_GTA03) -#else -# define machine_is_openmoko_gta03() (0) -#endif - -#ifdef CONFIG_MACH_OSPREY2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSPREY2 -# endif -# define machine_is_osprey2() (machine_arch_type == MACH_TYPE_OSPREY2) -#else -# define machine_is_osprey2() (0) -#endif - -#ifdef CONFIG_MACH_KBIO9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KBIO9260 -# endif -# define machine_is_kbio9260() (machine_arch_type == MACH_TYPE_KBIO9260) -#else -# define machine_is_kbio9260() (0) -#endif - -#ifdef CONFIG_MACH_GINZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GINZA -# endif -# define machine_is_ginza() (machine_arch_type == MACH_TYPE_GINZA) -#else -# define machine_is_ginza() (0) -#endif - -#ifdef CONFIG_MACH_A636N -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A636N -# endif -# define machine_is_a636n() (machine_arch_type == MACH_TYPE_A636N) -#else -# define machine_is_a636n() (0) -#endif - -#ifdef CONFIG_MACH_IMX27IPCAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27IPCAM -# endif -# define machine_is_imx27ipcam() (machine_arch_type == MACH_TYPE_IMX27IPCAM) -#else -# define machine_is_imx27ipcam() (0) -#endif - -#ifdef CONFIG_MACH_NEMOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEMOC -# endif -# define machine_is_nemoc() (machine_arch_type == MACH_TYPE_NEMOC) -#else -# define machine_is_nemoc() (0) -#endif - -#ifdef CONFIG_MACH_GENEVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GENEVA -# endif -# define machine_is_geneva() (machine_arch_type == MACH_TYPE_GENEVA) -#else -# define machine_is_geneva() (0) -#endif - -#ifdef CONFIG_MACH_HTCPHAROS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCPHAROS -# endif -# define machine_is_htcpharos() (machine_arch_type == MACH_TYPE_HTCPHAROS) -#else -# define machine_is_htcpharos() (0) -#endif - -#ifdef CONFIG_MACH_NEONC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEONC -# endif -# define machine_is_neonc() (machine_arch_type == MACH_TYPE_NEONC) -#else -# define machine_is_neonc() (0) -#endif - -#ifdef CONFIG_MACH_NAS7100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS7100 -# endif -# define machine_is_nas7100() (machine_arch_type == MACH_TYPE_NAS7100) -#else -# define machine_is_nas7100() (0) -#endif - -#ifdef CONFIG_MACH_TEUPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEUPHONE -# endif -# define machine_is_teuphone() (machine_arch_type == MACH_TYPE_TEUPHONE) -#else -# define machine_is_teuphone() (0) -#endif - -#ifdef CONFIG_MACH_ANNAX_ETH2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANNAX_ETH2 -# endif -# define machine_is_annax_eth2() (machine_arch_type == MACH_TYPE_ANNAX_ETH2) -#else -# define machine_is_annax_eth2() (0) -#endif - -#ifdef CONFIG_MACH_CSB733 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB733 -# endif -# define machine_is_csb733() (machine_arch_type == MACH_TYPE_CSB733) -#else -# define machine_is_csb733() (0) -#endif - -#ifdef CONFIG_MACH_BK3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BK3 -# endif -# define machine_is_bk3() (machine_arch_type == MACH_TYPE_BK3) -#else -# define machine_is_bk3() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_EM32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_EM32 -# endif -# define machine_is_omap_em32() (machine_arch_type == MACH_TYPE_OMAP_EM32) -#else -# define machine_is_omap_em32() (0) -#endif - -#ifdef CONFIG_MACH_ET9261CP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ET9261CP -# endif -# define machine_is_et9261cp() (machine_arch_type == MACH_TYPE_ET9261CP) -#else -# define machine_is_et9261cp() (0) -#endif - -#ifdef CONFIG_MACH_JASPERC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JASPERC -# endif -# define machine_is_jasperc() (machine_arch_type == MACH_TYPE_JASPERC) -#else -# define machine_is_jasperc() (0) -#endif - -#ifdef CONFIG_MACH_ISSI_ARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ISSI_ARM9 -# endif -# define machine_is_issi_arm9() (machine_arch_type == MACH_TYPE_ISSI_ARM9) -#else -# define machine_is_issi_arm9() (0) -#endif - -#ifdef CONFIG_MACH_UED -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UED -# endif -# define machine_is_ued() (machine_arch_type == MACH_TYPE_UED) -#else -# define machine_is_ued() (0) -#endif - -#ifdef CONFIG_MACH_ESIBLADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESIBLADE -# endif -# define machine_is_esiblade() (machine_arch_type == MACH_TYPE_ESIBLADE) -#else -# define machine_is_esiblade() (0) -#endif - -#ifdef CONFIG_MACH_EYE02 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EYE02 -# endif -# define machine_is_eye02() (machine_arch_type == MACH_TYPE_EYE02) -#else -# define machine_is_eye02() (0) -#endif - -#ifdef CONFIG_MACH_IMX27KBD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27KBD -# endif -# define machine_is_imx27kbd() (machine_arch_type == MACH_TYPE_IMX27KBD) -#else -# define machine_is_imx27kbd() (0) -#endif - -#ifdef CONFIG_MACH_SST61VC010_FPGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SST61VC010_FPGA -# endif -# define machine_is_sst61vc010_fpga() (machine_arch_type == MACH_TYPE_SST61VC010_FPGA) -#else -# define machine_is_sst61vc010_fpga() (0) -#endif - -#ifdef CONFIG_MACH_KIXVP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIXVP435 -# endif -# define machine_is_kixvp435() (machine_arch_type == MACH_TYPE_KIXVP435) -#else -# define machine_is_kixvp435() (0) -#endif - -#ifdef CONFIG_MACH_KIXNP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIXNP435 -# endif -# define machine_is_kixnp435() (machine_arch_type == MACH_TYPE_KIXNP435) -#else -# define machine_is_kixnp435() (0) -#endif - -#ifdef CONFIG_MACH_AFRICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AFRICA -# endif -# define machine_is_africa() (machine_arch_type == MACH_TYPE_AFRICA) -#else -# define machine_is_africa() (0) -#endif - -#ifdef CONFIG_MACH_NH233 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NH233 -# endif -# define machine_is_nh233() (machine_arch_type == MACH_TYPE_NH233) -#else -# define machine_is_nh233() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6183AP_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6183AP_GE -# endif -# define machine_is_rd88f6183ap_ge() (machine_arch_type == MACH_TYPE_RD88F6183AP_GE) -#else -# define machine_is_rd88f6183ap_ge() (0) -#endif - -#ifdef CONFIG_MACH_BCM4760 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCM4760 -# endif -# define machine_is_bcm4760() (machine_arch_type == MACH_TYPE_BCM4760) -#else -# define machine_is_bcm4760() (0) -#endif - -#ifdef CONFIG_MACH_EDDY_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDDY_V2 -# endif -# define machine_is_eddy_v2() (machine_arch_type == MACH_TYPE_EDDY_V2) -#else -# define machine_is_eddy_v2() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PBA8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PBA8 -# endif -# define machine_is_realview_pba8() (machine_arch_type == MACH_TYPE_REALVIEW_PBA8) -#else -# define machine_is_realview_pba8() (0) -#endif - -#ifdef CONFIG_MACH_HID_A7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HID_A7 -# endif -# define machine_is_hid_a7() (machine_arch_type == MACH_TYPE_HID_A7) -#else -# define machine_is_hid_a7() (0) -#endif - -#ifdef CONFIG_MACH_HERO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERO -# endif -# define machine_is_hero() (machine_arch_type == MACH_TYPE_HERO) -#else -# define machine_is_hero() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_POSEIDON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_POSEIDON -# endif -# define machine_is_omap_poseidon() (machine_arch_type == MACH_TYPE_OMAP_POSEIDON) -#else -# define machine_is_omap_poseidon() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PBX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PBX -# endif -# define machine_is_realview_pbx() (machine_arch_type == MACH_TYPE_REALVIEW_PBX) -#else -# define machine_is_realview_pbx() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9S -# endif -# define machine_is_micro9s() (machine_arch_type == MACH_TYPE_MICRO9S) -#else -# define machine_is_micro9s() (0) -#endif - -#ifdef CONFIG_MACH_MAKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAKO -# endif -# define machine_is_mako() (machine_arch_type == MACH_TYPE_MAKO) -#else -# define machine_is_mako() (0) -#endif - -#ifdef CONFIG_MACH_XDAFLAME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XDAFLAME -# endif -# define machine_is_xdaflame() (machine_arch_type == MACH_TYPE_XDAFLAME) -#else -# define machine_is_xdaflame() (0) -#endif - -#ifdef CONFIG_MACH_PHIDGET_SBC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHIDGET_SBC2 -# endif -# define machine_is_phidget_sbc2() (machine_arch_type == MACH_TYPE_PHIDGET_SBC2) -#else -# define machine_is_phidget_sbc2() (0) -#endif - -#ifdef CONFIG_MACH_LIMESTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIMESTONE -# endif -# define machine_is_limestone() (machine_arch_type == MACH_TYPE_LIMESTONE) -#else -# define machine_is_limestone() (0) -#endif - -#ifdef CONFIG_MACH_IPROBE_C32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPROBE_C32 -# endif -# define machine_is_iprobe_c32() (machine_arch_type == MACH_TYPE_IPROBE_C32) -#else -# define machine_is_iprobe_c32() (0) -#endif - -#ifdef CONFIG_MACH_RUT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RUT100 -# endif -# define machine_is_rut100() (machine_arch_type == MACH_TYPE_RUT100) -#else -# define machine_is_rut100() (0) -#endif - -#ifdef CONFIG_MACH_ASUSP535 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASUSP535 -# endif -# define machine_is_asusp535() (machine_arch_type == MACH_TYPE_ASUSP535) -#else -# define machine_is_asusp535() (0) -#endif - -#ifdef CONFIG_MACH_HTCRAPHAEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRAPHAEL -# endif -# define machine_is_htcraphael() (machine_arch_type == MACH_TYPE_HTCRAPHAEL) -#else -# define machine_is_htcraphael() (0) -#endif - -#ifdef CONFIG_MACH_SYGDG1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYGDG1 -# endif -# define machine_is_sygdg1() (machine_arch_type == MACH_TYPE_SYGDG1) -#else -# define machine_is_sygdg1() (0) -#endif - -#ifdef CONFIG_MACH_SYGDG2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYGDG2 -# endif -# define machine_is_sygdg2() (machine_arch_type == MACH_TYPE_SYGDG2) -#else -# define machine_is_sygdg2() (0) -#endif - -#ifdef CONFIG_MACH_SEOUL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SEOUL -# endif -# define machine_is_seoul() (machine_arch_type == MACH_TYPE_SEOUL) -#else -# define machine_is_seoul() (0) -#endif - -#ifdef CONFIG_MACH_SALERNO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SALERNO -# endif -# define machine_is_salerno() (machine_arch_type == MACH_TYPE_SALERNO) -#else -# define machine_is_salerno() (0) -#endif - -#ifdef CONFIG_MACH_UCN_S3C64XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UCN_S3C64XX -# endif -# define machine_is_ucn_s3c64xx() (machine_arch_type == MACH_TYPE_UCN_S3C64XX) -#else -# define machine_is_ucn_s3c64xx() (0) -#endif - -#ifdef CONFIG_MACH_MSM7201A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7201A -# endif -# define machine_is_msm7201a() (machine_arch_type == MACH_TYPE_MSM7201A) -#else -# define machine_is_msm7201a() (0) -#endif - -#ifdef CONFIG_MACH_LPR1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPR1 -# endif -# define machine_is_lpr1() (machine_arch_type == MACH_TYPE_LPR1) -#else -# define machine_is_lpr1() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO500FX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO500FX -# endif -# define machine_is_armadillo500fx() (machine_arch_type == MACH_TYPE_ARMADILLO500FX) -#else -# define machine_is_armadillo500fx() (0) -#endif - -#ifdef CONFIG_MACH_G3EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G3EVM -# endif -# define machine_is_g3evm() (machine_arch_type == MACH_TYPE_G3EVM) -#else -# define machine_is_g3evm() (0) -#endif - -#ifdef CONFIG_MACH_Z3_DM355 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Z3_DM355 -# endif -# define machine_is_z3_dm355() (machine_arch_type == MACH_TYPE_Z3_DM355) -#else -# define machine_is_z3_dm355() (0) -#endif - -#ifdef CONFIG_MACH_W90P910EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P910EVB -# endif -# define machine_is_w90p910evb() (machine_arch_type == MACH_TYPE_W90P910EVB) -#else -# define machine_is_w90p910evb() (0) -#endif - -#ifdef CONFIG_MACH_W90P920EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P920EVB -# endif -# define machine_is_w90p920evb() (machine_arch_type == MACH_TYPE_W90P920EVB) -#else -# define machine_is_w90p920evb() (0) -#endif - -#ifdef CONFIG_MACH_W90P950EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P950EVB -# endif -# define machine_is_w90p950evb() (machine_arch_type == MACH_TYPE_W90P950EVB) -#else -# define machine_is_w90p950evb() (0) -#endif - -#ifdef CONFIG_MACH_W90N960EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90N960EVB -# endif -# define machine_is_w90n960evb() (machine_arch_type == MACH_TYPE_W90N960EVB) -#else -# define machine_is_w90n960evb() (0) -#endif - -#ifdef CONFIG_MACH_CAMHD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAMHD -# endif -# define machine_is_camhd() (machine_arch_type == MACH_TYPE_CAMHD) -#else -# define machine_is_camhd() (0) -#endif - -#ifdef CONFIG_MACH_MVC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MVC100 -# endif -# define machine_is_mvc100() (machine_arch_type == MACH_TYPE_MVC100) -#else -# define machine_is_mvc100() (0) -#endif - -#ifdef CONFIG_MACH_ELECTRUM_200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELECTRUM_200 -# endif -# define machine_is_electrum_200() (machine_arch_type == MACH_TYPE_ELECTRUM_200) -#else -# define machine_is_electrum_200() (0) -#endif - -#ifdef CONFIG_MACH_HTCJADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCJADE -# endif -# define machine_is_htcjade() (machine_arch_type == MACH_TYPE_HTCJADE) -#else -# define machine_is_htcjade() (0) -#endif - -#ifdef CONFIG_MACH_MEMPHIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEMPHIS -# endif -# define machine_is_memphis() (machine_arch_type == MACH_TYPE_MEMPHIS) -#else -# define machine_is_memphis() (0) -#endif - -#ifdef CONFIG_MACH_IMX27SBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27SBC -# endif -# define machine_is_imx27sbc() (machine_arch_type == MACH_TYPE_IMX27SBC) -#else -# define machine_is_imx27sbc() (0) -#endif - -#ifdef CONFIG_MACH_LEXTAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEXTAR -# endif -# define machine_is_lextar() (machine_arch_type == MACH_TYPE_LEXTAR) -#else -# define machine_is_lextar() (0) -#endif - -#ifdef CONFIG_MACH_MV88F6281GTW_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV88F6281GTW_GE -# endif -# define machine_is_mv88f6281gtw_ge() (machine_arch_type == MACH_TYPE_MV88F6281GTW_GE) -#else -# define machine_is_mv88f6281gtw_ge() (0) -#endif - -#ifdef CONFIG_MACH_NCP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NCP -# endif -# define machine_is_ncp() (machine_arch_type == MACH_TYPE_NCP) -#else -# define machine_is_ncp() (0) -#endif - -#ifdef CONFIG_MACH_Z32AN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Z32AN -# endif -# define machine_is_z32an_series() (machine_arch_type == MACH_TYPE_Z32AN) -#else -# define machine_is_z32an_series() (0) -#endif - -#ifdef CONFIG_MACH_TMQ_CAPD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TMQ_CAPD -# endif -# define machine_is_tmq_capd() (machine_arch_type == MACH_TYPE_TMQ_CAPD) -#else -# define machine_is_tmq_capd() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_WL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_WL -# endif -# define machine_is_omap3_wl() (machine_arch_type == MACH_TYPE_OMAP3_WL) -#else -# define machine_is_omap3_wl() (0) -#endif - -#ifdef CONFIG_MACH_CHUMBY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHUMBY -# endif -# define machine_is_chumby() (machine_arch_type == MACH_TYPE_CHUMBY) -#else -# define machine_is_chumby() (0) -#endif - -#ifdef CONFIG_MACH_ATSARM9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATSARM9 -# endif -# define machine_is_atsarm9() (machine_arch_type == MACH_TYPE_ATSARM9) -#else -# define machine_is_atsarm9() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM365_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM365_EVM -# endif -# define machine_is_davinci_dm365_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM) -#else -# define machine_is_davinci_dm365_evm() (0) -#endif - -#ifdef CONFIG_MACH_BAHAMAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BAHAMAS -# endif -# define machine_is_bahamas() (machine_arch_type == MACH_TYPE_BAHAMAS) -#else -# define machine_is_bahamas() (0) -#endif - -#ifdef CONFIG_MACH_DAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAS -# endif -# define machine_is_das() (machine_arch_type == MACH_TYPE_DAS) -#else -# define machine_is_das() (0) -#endif - -#ifdef CONFIG_MACH_MINIDAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINIDAS -# endif -# define machine_is_minidas() (machine_arch_type == MACH_TYPE_MINIDAS) -#else -# define machine_is_minidas() (0) -#endif - -#ifdef CONFIG_MACH_VK1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VK1000 -# endif -# define machine_is_vk1000() (machine_arch_type == MACH_TYPE_VK1000) -#else -# define machine_is_vk1000() (0) -#endif - -#ifdef CONFIG_MACH_CENTRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CENTRO -# endif -# define machine_is_centro() (machine_arch_type == MACH_TYPE_CENTRO) -#else -# define machine_is_centro() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_2BAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_2BAY -# endif -# define machine_is_ctera_2bay() (machine_arch_type == MACH_TYPE_CTERA_2BAY) -#else -# define machine_is_ctera_2bay() (0) -#endif - -#ifdef CONFIG_MACH_EDGECONNECT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDGECONNECT -# endif -# define machine_is_edgeconnect() (machine_arch_type == MACH_TYPE_EDGECONNECT) -#else -# define machine_is_edgeconnect() (0) -#endif - -#ifdef CONFIG_MACH_ND27000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ND27000 -# endif -# define machine_is_nd27000() (machine_arch_type == MACH_TYPE_ND27000) -#else -# define machine_is_nd27000() (0) -#endif - -#ifdef CONFIG_MACH_GEMALTO_COBRA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMALTO_COBRA -# endif -# define machine_is_cobra() (machine_arch_type == MACH_TYPE_GEMALTO_COBRA) -#else -# define machine_is_cobra() (0) -#endif - -#ifdef CONFIG_MACH_INGELABS_COMET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INGELABS_COMET -# endif -# define machine_is_ingelabs_comet() (machine_arch_type == MACH_TYPE_INGELABS_COMET) -#else -# define machine_is_ingelabs_comet() (0) -#endif - -#ifdef CONFIG_MACH_POLLUX_WIZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POLLUX_WIZ -# endif -# define machine_is_pollux_wiz() (machine_arch_type == MACH_TYPE_POLLUX_WIZ) -#else -# define machine_is_pollux_wiz() (0) -#endif - -#ifdef CONFIG_MACH_BLACKSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLACKSTONE -# endif -# define machine_is_blackstone() (machine_arch_type == MACH_TYPE_BLACKSTONE) -#else -# define machine_is_blackstone() (0) -#endif - -#ifdef CONFIG_MACH_TOPAZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOPAZ -# endif -# define machine_is_topaz() (machine_arch_type == MACH_TYPE_TOPAZ) -#else -# define machine_is_topaz() (0) -#endif - -#ifdef CONFIG_MACH_AIXLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AIXLE -# endif -# define machine_is_aixle() (machine_arch_type == MACH_TYPE_AIXLE) -#else -# define machine_is_aixle() (0) -#endif - -#ifdef CONFIG_MACH_MW998 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MW998 -# endif -# define machine_is_mw998() (machine_arch_type == MACH_TYPE_MW998) -#else -# define machine_is_mw998() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_RX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_RX51 -# endif -# define machine_is_nokia_rx51() (machine_arch_type == MACH_TYPE_NOKIA_RX51) -#else -# define machine_is_nokia_rx51() (0) -#endif - -#ifdef CONFIG_MACH_VSC5605EV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VSC5605EV -# endif -# define machine_is_vsc5605ev() (machine_arch_type == MACH_TYPE_VSC5605EV) -#else -# define machine_is_vsc5605ev() (0) -#endif - -#ifdef CONFIG_MACH_NT98700DK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NT98700DK -# endif -# define machine_is_nt98700dk() (machine_arch_type == MACH_TYPE_NT98700DK) -#else -# define machine_is_nt98700dk() (0) -#endif - -#ifdef CONFIG_MACH_ICONTACT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICONTACT -# endif -# define machine_is_icontact() (machine_arch_type == MACH_TYPE_ICONTACT) -#else -# define machine_is_icontact() (0) -#endif - -#ifdef CONFIG_MACH_SWARCO_FRCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCO_FRCPU -# endif -# define machine_is_swarco_frcpu() (machine_arch_type == MACH_TYPE_SWARCO_FRCPU) -#else -# define machine_is_swarco_frcpu() (0) -#endif - -#ifdef CONFIG_MACH_SWARCO_SCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCO_SCPU -# endif -# define machine_is_swarco_scpu() (machine_arch_type == MACH_TYPE_SWARCO_SCPU) -#else -# define machine_is_swarco_scpu() (0) -#endif - -#ifdef CONFIG_MACH_BBOX_P16 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BBOX_P16 -# endif -# define machine_is_bbox_p16() (machine_arch_type == MACH_TYPE_BBOX_P16) -#else -# define machine_is_bbox_p16() (0) -#endif - -#ifdef CONFIG_MACH_BSTD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSTD -# endif -# define machine_is_bstd() (machine_arch_type == MACH_TYPE_BSTD) -#else -# define machine_is_bstd() (0) -#endif - -#ifdef CONFIG_MACH_SBC2440II -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2440II -# endif -# define machine_is_sbc2440ii() (machine_arch_type == MACH_TYPE_SBC2440II) -#else -# define machine_is_sbc2440ii() (0) -#endif - -#ifdef CONFIG_MACH_PCM034 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM034 -# endif -# define machine_is_pcm034() (machine_arch_type == MACH_TYPE_PCM034) -#else -# define machine_is_pcm034() (0) -#endif - -#ifdef CONFIG_MACH_NESO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NESO -# endif -# define machine_is_neso() (machine_arch_type == MACH_TYPE_NESO) -#else -# define machine_is_neso() (0) -#endif - -#ifdef CONFIG_MACH_WLNX_9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WLNX_9G20 -# endif -# define machine_is_wlnx_9g20() (machine_arch_type == MACH_TYPE_WLNX_9G20) -#else -# define machine_is_wlnx_9g20() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_ZOOM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_ZOOM2 -# endif -# define machine_is_omap_zoom2() (machine_arch_type == MACH_TYPE_OMAP_ZOOM2) -#else -# define machine_is_omap_zoom2() (0) -#endif - -#ifdef CONFIG_MACH_TOTEMNOVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOTEMNOVA -# endif -# define machine_is_totemnova() (machine_arch_type == MACH_TYPE_TOTEMNOVA) -#else -# define machine_is_totemnova() (0) -#endif - -#ifdef CONFIG_MACH_C5000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C5000 -# endif -# define machine_is_c5000() (machine_arch_type == MACH_TYPE_C5000) -#else -# define machine_is_c5000() (0) -#endif - -#ifdef CONFIG_MACH_UNIPO_AT91SAM9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIPO_AT91SAM9263 -# endif -# define machine_is_unipo_at91sam9263() (machine_arch_type == MACH_TYPE_UNIPO_AT91SAM9263) -#else -# define machine_is_unipo_at91sam9263() (0) -#endif - -#ifdef CONFIG_MACH_ETHERNUT5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETHERNUT5 -# endif -# define machine_is_ethernut5() (machine_arch_type == MACH_TYPE_ETHERNUT5) -#else -# define machine_is_ethernut5() (0) -#endif - -#ifdef CONFIG_MACH_ARM11 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM11 -# endif -# define machine_is_arm11() (machine_arch_type == MACH_TYPE_ARM11) -#else -# define machine_is_arm11() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT9260 -# endif -# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260) -#else -# define machine_is_cpuat9260() (0) -#endif - -#ifdef CONFIG_MACH_CPUPXA255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUPXA255 -# endif -# define machine_is_cpupxa255() (machine_arch_type == MACH_TYPE_CPUPXA255) -#else -# define machine_is_cpupxa255() (0) -#endif - -#ifdef CONFIG_MACH_CPUIMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUIMX27 -# endif -# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) -#else -# define machine_is_eukrea_cpuimx27() (0) -#endif - -#ifdef CONFIG_MACH_CHEFLUX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHEFLUX -# endif -# define machine_is_cheflux() (machine_arch_type == MACH_TYPE_CHEFLUX) -#else -# define machine_is_cheflux() (0) -#endif - -#ifdef CONFIG_MACH_EB_CPUX9K2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EB_CPUX9K2 -# endif -# define machine_is_eb_cpux9k2() (machine_arch_type == MACH_TYPE_EB_CPUX9K2) -#else -# define machine_is_eb_cpux9k2() (0) -#endif - -#ifdef CONFIG_MACH_OPCOTEC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPCOTEC -# endif -# define machine_is_opcotec() (machine_arch_type == MACH_TYPE_OPCOTEC) -#else -# define machine_is_opcotec() (0) -#endif - -#ifdef CONFIG_MACH_YT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YT -# endif -# define machine_is_yt() (machine_arch_type == MACH_TYPE_YT) -#else -# define machine_is_yt() (0) -#endif - -#ifdef CONFIG_MACH_MOTOQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOQ -# endif -# define machine_is_motoq() (machine_arch_type == MACH_TYPE_MOTOQ) -#else -# define machine_is_motoq() (0) -#endif - -#ifdef CONFIG_MACH_BSB1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSB1 -# endif -# define machine_is_bsb1() (machine_arch_type == MACH_TYPE_BSB1) -#else -# define machine_is_bsb1() (0) -#endif - -#ifdef CONFIG_MACH_ACS5K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACS5K -# endif -# define machine_is_acs5k() (machine_arch_type == MACH_TYPE_ACS5K) -#else -# define machine_is_acs5k() (0) -#endif - -#ifdef CONFIG_MACH_MILAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MILAN -# endif -# define machine_is_milan() (machine_arch_type == MACH_TYPE_MILAN) -#else -# define machine_is_milan() (0) -#endif - -#ifdef CONFIG_MACH_QUARTZV2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUARTZV2 -# endif -# define machine_is_quartzv2() (machine_arch_type == MACH_TYPE_QUARTZV2) -#else -# define machine_is_quartzv2() (0) -#endif - -#ifdef CONFIG_MACH_RSVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSVP -# endif -# define machine_is_rsvp() (machine_arch_type == MACH_TYPE_RSVP) -#else -# define machine_is_rsvp() (0) -#endif - -#ifdef CONFIG_MACH_RMP200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RMP200 -# endif -# define machine_is_rmp200() (machine_arch_type == MACH_TYPE_RMP200) -#else -# define machine_is_rmp200() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_9260 -# endif -# define machine_is_snapper_9260() (machine_arch_type == MACH_TYPE_SNAPPER_9260) -#else -# define machine_is_snapper_9260() (0) -#endif - -#ifdef CONFIG_MACH_DSM320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSM320 -# endif -# define machine_is_dsm320() (machine_arch_type == MACH_TYPE_DSM320) -#else -# define machine_is_dsm320() (0) -#endif - -#ifdef CONFIG_MACH_ADSGCM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSGCM -# endif -# define machine_is_adsgcm() (machine_arch_type == MACH_TYPE_ADSGCM) -#else -# define machine_is_adsgcm() (0) -#endif - -#ifdef CONFIG_MACH_ASE2_400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASE2_400 -# endif -# define machine_is_ase2_400() (machine_arch_type == MACH_TYPE_ASE2_400) -#else -# define machine_is_ase2_400() (0) -#endif - -#ifdef CONFIG_MACH_PIZZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PIZZA -# endif -# define machine_is_pizza() (machine_arch_type == MACH_TYPE_PIZZA) -#else -# define machine_is_pizza() (0) -#endif - -#ifdef CONFIG_MACH_SPOT_NGPL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPOT_NGPL -# endif -# define machine_is_spot_ngpl() (machine_arch_type == MACH_TYPE_SPOT_NGPL) -#else -# define machine_is_spot_ngpl() (0) -#endif - -#ifdef CONFIG_MACH_ARMATA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMATA -# endif -# define machine_is_armata() (machine_arch_type == MACH_TYPE_ARMATA) -#else -# define machine_is_armata() (0) -#endif - -#ifdef CONFIG_MACH_EXEDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXEDA -# endif -# define machine_is_exeda() (machine_arch_type == MACH_TYPE_EXEDA) -#else -# define machine_is_exeda() (0) -#endif - -#ifdef CONFIG_MACH_MX31SF005 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31SF005 -# endif -# define machine_is_mx31sf005() (machine_arch_type == MACH_TYPE_MX31SF005) -#else -# define machine_is_mx31sf005() (0) -#endif - -#ifdef CONFIG_MACH_F5D8231_4_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_F5D8231_4_V2 -# endif -# define machine_is_f5d8231_4_v2() (machine_arch_type == MACH_TYPE_F5D8231_4_V2) -#else -# define machine_is_f5d8231_4_v2() (0) -#endif - -#ifdef CONFIG_MACH_Q2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Q2440 -# endif -# define machine_is_q2440() (machine_arch_type == MACH_TYPE_Q2440) -#else -# define machine_is_q2440() (0) -#endif - -#ifdef CONFIG_MACH_QQ2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QQ2440 -# endif -# define machine_is_qq2440() (machine_arch_type == MACH_TYPE_QQ2440) -#else -# define machine_is_qq2440() (0) -#endif - -#ifdef CONFIG_MACH_MINI2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI2440 -# endif -# define machine_is_mini2440() (machine_arch_type == MACH_TYPE_MINI2440) -#else -# define machine_is_mini2440() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI300 -# endif -# define machine_is_colibri300() (machine_arch_type == MACH_TYPE_COLIBRI300) -#else -# define machine_is_colibri300() (0) -#endif - -#ifdef CONFIG_MACH_JADES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADES -# endif -# define machine_is_jades() (machine_arch_type == MACH_TYPE_JADES) -#else -# define machine_is_jades() (0) -#endif - -#ifdef CONFIG_MACH_SPARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPARK -# endif -# define machine_is_spark() (machine_arch_type == MACH_TYPE_SPARK) -#else -# define machine_is_spark() (0) -#endif - -#ifdef CONFIG_MACH_BENZINA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BENZINA -# endif -# define machine_is_benzina() (machine_arch_type == MACH_TYPE_BENZINA) -#else -# define machine_is_benzina() (0) -#endif - -#ifdef CONFIG_MACH_BLAZE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLAZE -# endif -# define machine_is_blaze() (machine_arch_type == MACH_TYPE_BLAZE) -#else -# define machine_is_blaze() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_LS_HGL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_LS_HGL -# endif -# define machine_is_linkstation_ls_hgl() (machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL) -#else -# define machine_is_linkstation_ls_hgl() (0) -#endif - -#ifdef CONFIG_MACH_HTCVENUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCVENUS -# endif -# define machine_is_htckovsky() (machine_arch_type == MACH_TYPE_HTCVENUS) -#else -# define machine_is_htckovsky() (0) -#endif - -#ifdef CONFIG_MACH_SONY_PRS505 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SONY_PRS505 -# endif -# define machine_is_sony_prs505() (machine_arch_type == MACH_TYPE_SONY_PRS505) -#else -# define machine_is_sony_prs505() (0) -#endif - -#ifdef CONFIG_MACH_HANLIN_V3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HANLIN_V3 -# endif -# define machine_is_hanlin_v3() (machine_arch_type == MACH_TYPE_HANLIN_V3) -#else -# define machine_is_hanlin_v3() (0) -#endif - -#ifdef CONFIG_MACH_SAPPHIRA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAPPHIRA -# endif -# define machine_is_sapphira() (machine_arch_type == MACH_TYPE_SAPPHIRA) -#else -# define machine_is_sapphira() (0) -#endif - -#ifdef CONFIG_MACH_DACK_SDA_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DACK_SDA_01 -# endif -# define machine_is_dack_sda_01() (machine_arch_type == MACH_TYPE_DACK_SDA_01) -#else -# define machine_is_dack_sda_01() (0) -#endif - -#ifdef CONFIG_MACH_ARMBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMBOX -# endif -# define machine_is_armbox() (machine_arch_type == MACH_TYPE_ARMBOX) -#else -# define machine_is_armbox() (0) -#endif - -#ifdef CONFIG_MACH_HARRIS_RVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HARRIS_RVP -# endif -# define machine_is_harris_rvp() (machine_arch_type == MACH_TYPE_HARRIS_RVP) -#else -# define machine_is_harris_rvp() (0) -#endif - -#ifdef CONFIG_MACH_RIBALDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIBALDO -# endif -# define machine_is_ribaldo() (machine_arch_type == MACH_TYPE_RIBALDO) -#else -# define machine_is_ribaldo() (0) -#endif - -#ifdef CONFIG_MACH_AGORA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AGORA -# endif -# define machine_is_agora() (machine_arch_type == MACH_TYPE_AGORA) -#else -# define machine_is_agora() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_MINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_MINI -# endif -# define machine_is_omap3_mini() (machine_arch_type == MACH_TYPE_OMAP3_MINI) -#else -# define machine_is_omap3_mini() (0) -#endif - -#ifdef CONFIG_MACH_A9SAM6432_B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A9SAM6432_B -# endif -# define machine_is_a9sam6432_b() (machine_arch_type == MACH_TYPE_A9SAM6432_B) -#else -# define machine_is_a9sam6432_b() (0) -#endif - -#ifdef CONFIG_MACH_USG2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USG2410 -# endif -# define machine_is_usg2410() (machine_arch_type == MACH_TYPE_USG2410) -#else -# define machine_is_usg2410() (0) -#endif - -#ifdef CONFIG_MACH_PC72052_I10_REVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC72052_I10_REVB -# endif -# define machine_is_pc72052_i10_revb() (machine_arch_type == MACH_TYPE_PC72052_I10_REVB) -#else -# define machine_is_pc72052_i10_revb() (0) -#endif - -#ifdef CONFIG_MACH_MX35_EXM32 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35_EXM32 -# endif -# define machine_is_mx35_exm32() (machine_arch_type == MACH_TYPE_MX35_EXM32) -#else -# define machine_is_mx35_exm32() (0) -#endif - -#ifdef CONFIG_MACH_TOPAS910 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOPAS910 -# endif -# define machine_is_topas910() (machine_arch_type == MACH_TYPE_TOPAS910) -#else -# define machine_is_topas910() (0) -#endif - -#ifdef CONFIG_MACH_HYENA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HYENA -# endif -# define machine_is_hyena() (machine_arch_type == MACH_TYPE_HYENA) -#else -# define machine_is_hyena() (0) -#endif - -#ifdef CONFIG_MACH_POSPAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POSPAX -# endif -# define machine_is_pospax() (machine_arch_type == MACH_TYPE_POSPAX) -#else -# define machine_is_pospax() (0) -#endif - -#ifdef CONFIG_MACH_HDL_GX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDL_GX -# endif -# define machine_is_hdl_gx() (machine_arch_type == MACH_TYPE_HDL_GX) -#else -# define machine_is_hdl_gx() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_4BAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_4BAY -# endif -# define machine_is_ctera_4bay() (machine_arch_type == MACH_TYPE_CTERA_4BAY) -#else -# define machine_is_ctera_4bay() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_PLUG_C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_PLUG_C -# endif -# define machine_is_ctera_plug_c() (machine_arch_type == MACH_TYPE_CTERA_PLUG_C) -#else -# define machine_is_ctera_plug_c() (0) -#endif - -#ifdef CONFIG_MACH_CRWEA_PLUG_I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CRWEA_PLUG_I -# endif -# define machine_is_crwea_plug_i() (machine_arch_type == MACH_TYPE_CRWEA_PLUG_I) -#else -# define machine_is_crwea_plug_i() (0) -#endif - -#ifdef CONFIG_MACH_EGAUGE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EGAUGE2 -# endif -# define machine_is_egauge2() (machine_arch_type == MACH_TYPE_EGAUGE2) -#else -# define machine_is_egauge2() (0) -#endif - -#ifdef CONFIG_MACH_DIDJ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIDJ -# endif -# define machine_is_didj() (machine_arch_type == MACH_TYPE_DIDJ) -#else -# define machine_is_didj() (0) -#endif - -#ifdef CONFIG_MACH_MEISTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEISTER -# endif -# define machine_is_m_s3c2443() (machine_arch_type == MACH_TYPE_MEISTER) -#else -# define machine_is_m_s3c2443() (0) -#endif - -#ifdef CONFIG_MACH_HTCBLACKSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCBLACKSTONE -# endif -# define machine_is_htcblackstone() (machine_arch_type == MACH_TYPE_HTCBLACKSTONE) -#else -# define machine_is_htcblackstone() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT9G20 -# endif -# define machine_is_cpuat9g20() (machine_arch_type == MACH_TYPE_CPUAT9G20) -#else -# define machine_is_cpuat9g20() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6440 -# endif -# define machine_is_smdk6440() (machine_arch_type == MACH_TYPE_SMDK6440) -#else -# define machine_is_smdk6440() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_35XX_MVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_35XX_MVP -# endif -# define machine_is_omap_35xx_mvp() (machine_arch_type == MACH_TYPE_OMAP_35XX_MVP) -#else -# define machine_is_omap_35xx_mvp() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_PLUG_I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_PLUG_I -# endif -# define machine_is_ctera_plug_i() (machine_arch_type == MACH_TYPE_CTERA_PLUG_I) -#else -# define machine_is_ctera_plug_i() (0) -#endif - -#ifdef CONFIG_MACH_PVG610 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PVG610 -# endif -# define machine_is_pvg610_100() (machine_arch_type == MACH_TYPE_PVG610) -#else -# define machine_is_pvg610_100() (0) -#endif - -#ifdef CONFIG_MACH_HPRW6815 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPRW6815 -# endif -# define machine_is_hprw6815() (machine_arch_type == MACH_TYPE_HPRW6815) -#else -# define machine_is_hprw6815() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_OSWALD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_OSWALD -# endif -# define machine_is_omap3_oswald() (machine_arch_type == MACH_TYPE_OMAP3_OSWALD) -#else -# define machine_is_omap3_oswald() (0) -#endif - -#ifdef CONFIG_MACH_NAS4220B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS4220B -# endif -# define machine_is_nas4220b() (machine_arch_type == MACH_TYPE_NAS4220B) -#else -# define machine_is_nas4220b() (0) -#endif - -#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA -# endif -# define machine_is_htcraphael_cdma() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA) -#else -# define machine_is_htcraphael_cdma() (0) -#endif - -#ifdef CONFIG_MACH_HTCDIAMOND_CDMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCDIAMOND_CDMA -# endif -# define machine_is_htcdiamond_cdma() (machine_arch_type == MACH_TYPE_HTCDIAMOND_CDMA) -#else -# define machine_is_htcdiamond_cdma() (0) -#endif - -#ifdef CONFIG_MACH_SCALER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCALER -# endif -# define machine_is_scaler() (machine_arch_type == MACH_TYPE_SCALER) -#else -# define machine_is_scaler() (0) -#endif - -#ifdef CONFIG_MACH_ZYLONITE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZYLONITE2 -# endif -# define machine_is_zylonite2() (machine_arch_type == MACH_TYPE_ZYLONITE2) -#else -# define machine_is_zylonite2() (0) -#endif - -#ifdef CONFIG_MACH_ASPENITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASPENITE -# endif -# define machine_is_aspenite() (machine_arch_type == MACH_TYPE_ASPENITE) -#else -# define machine_is_aspenite() (0) -#endif - -#ifdef CONFIG_MACH_TETON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TETON -# endif -# define machine_is_teton() (machine_arch_type == MACH_TYPE_TETON) -#else -# define machine_is_teton() (0) -#endif - -#ifdef CONFIG_MACH_TTC_DKB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TTC_DKB -# endif -# define machine_is_ttc_dkb() (machine_arch_type == MACH_TYPE_TTC_DKB) -#else -# define machine_is_ttc_dkb() (0) -#endif - -#ifdef CONFIG_MACH_BISHOP2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BISHOP2 -# endif -# define machine_is_bishop2() (machine_arch_type == MACH_TYPE_BISHOP2) -#else -# define machine_is_bishop2() (0) -#endif - -#ifdef CONFIG_MACH_IPPV5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IPPV5 -# endif -# define machine_is_ippv5() (machine_arch_type == MACH_TYPE_IPPV5) -#else -# define machine_is_ippv5() (0) -#endif - -#ifdef CONFIG_MACH_FARM926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FARM926 -# endif -# define machine_is_farm926() (machine_arch_type == MACH_TYPE_FARM926) -#else -# define machine_is_farm926() (0) -#endif - -#ifdef CONFIG_MACH_MMCCPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMCCPU -# endif -# define machine_is_mmccpu() (machine_arch_type == MACH_TYPE_MMCCPU) -#else -# define machine_is_mmccpu() (0) -#endif - -#ifdef CONFIG_MACH_SGMSFL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SGMSFL -# endif -# define machine_is_sgmsfl() (machine_arch_type == MACH_TYPE_SGMSFL) -#else -# define machine_is_sgmsfl() (0) -#endif - -#ifdef CONFIG_MACH_TT8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT8000 -# endif -# define machine_is_tt8000() (machine_arch_type == MACH_TYPE_TT8000) -#else -# define machine_is_tt8000() (0) -#endif - -#ifdef CONFIG_MACH_ZRN4300LP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZRN4300LP -# endif -# define machine_is_zrn4300lp() (machine_arch_type == MACH_TYPE_ZRN4300LP) -#else -# define machine_is_zrn4300lp() (0) -#endif - -#ifdef CONFIG_MACH_MPTC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPTC -# endif -# define machine_is_mptc() (machine_arch_type == MACH_TYPE_MPTC) -#else -# define machine_is_mptc() (0) -#endif - -#ifdef CONFIG_MACH_H6051 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H6051 -# endif -# define machine_is_h6051() (machine_arch_type == MACH_TYPE_H6051) -#else -# define machine_is_h6051() (0) -#endif - -#ifdef CONFIG_MACH_PVG610_101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PVG610_101 -# endif -# define machine_is_pvg610_101() (machine_arch_type == MACH_TYPE_PVG610_101) -#else -# define machine_is_pvg610_101() (0) -#endif - -#ifdef CONFIG_MACH_STAMP9261_PC_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAMP9261_PC_EVB -# endif -# define machine_is_stamp9261_pc_evb() (machine_arch_type == MACH_TYPE_STAMP9261_PC_EVB) -#else -# define machine_is_stamp9261_pc_evb() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_ODYSSEUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_ODYSSEUS -# endif -# define machine_is_pelco_odysseus() (machine_arch_type == MACH_TYPE_PELCO_ODYSSEUS) -#else -# define machine_is_pelco_odysseus() (0) -#endif - -#ifdef CONFIG_MACH_TNY_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNY_A9260 -# endif -# define machine_is_tny_a9260() (machine_arch_type == MACH_TYPE_TNY_A9260) -#else -# define machine_is_tny_a9260() (0) -#endif - -#ifdef CONFIG_MACH_TNY_A9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNY_A9G20 -# endif -# define machine_is_tny_a9g20() (machine_arch_type == MACH_TYPE_TNY_A9G20) -#else -# define machine_is_tny_a9g20() (0) -#endif - -#ifdef CONFIG_MACH_AESOP_MP2530F -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AESOP_MP2530F -# endif -# define machine_is_aesop_mp2530f() (machine_arch_type == MACH_TYPE_AESOP_MP2530F) -#else -# define machine_is_aesop_mp2530f() (0) -#endif - -#ifdef CONFIG_MACH_DX900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DX900 -# endif -# define machine_is_dx900() (machine_arch_type == MACH_TYPE_DX900) -#else -# define machine_is_dx900() (0) -#endif - -#ifdef CONFIG_MACH_CPODC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPODC2 -# endif -# define machine_is_cpodc2() (machine_arch_type == MACH_TYPE_CPODC2) -#else -# define machine_is_cpodc2() (0) -#endif - -#ifdef CONFIG_MACH_TILT_8925 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TILT_8925 -# endif -# define machine_is_tilt_8925() (machine_arch_type == MACH_TYPE_TILT_8925) -#else -# define machine_is_tilt_8925() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM357_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM357_EVM -# endif -# define machine_is_davinci_dm357_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM357_EVM) -#else -# define machine_is_davinci_dm357_evm() (0) -#endif - -#ifdef CONFIG_MACH_SWORDFISH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWORDFISH -# endif -# define machine_is_swordfish() (machine_arch_type == MACH_TYPE_SWORDFISH) -#else -# define machine_is_swordfish() (0) -#endif - -#ifdef CONFIG_MACH_CORVUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORVUS -# endif -# define machine_is_corvus() (machine_arch_type == MACH_TYPE_CORVUS) -#else -# define machine_is_corvus() (0) -#endif - -#ifdef CONFIG_MACH_TAURUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAURUS -# endif -# define machine_is_taurus() (machine_arch_type == MACH_TYPE_TAURUS) -#else -# define machine_is_taurus() (0) -#endif - -#ifdef CONFIG_MACH_AXM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXM -# endif -# define machine_is_axm() (machine_arch_type == MACH_TYPE_AXM) -#else -# define machine_is_axm() (0) -#endif - -#ifdef CONFIG_MACH_AXC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXC -# endif -# define machine_is_axc() (machine_arch_type == MACH_TYPE_AXC) -#else -# define machine_is_axc() (0) -#endif - -#ifdef CONFIG_MACH_BABY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BABY -# endif -# define machine_is_baby() (machine_arch_type == MACH_TYPE_BABY) -#else -# define machine_is_baby() (0) -#endif - -#ifdef CONFIG_MACH_MP200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP200 -# endif -# define machine_is_mp200() (machine_arch_type == MACH_TYPE_MP200) -#else -# define machine_is_mp200() (0) -#endif - -#ifdef CONFIG_MACH_PCM043 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM043 -# endif -# define machine_is_pcm043() (machine_arch_type == MACH_TYPE_PCM043) -#else -# define machine_is_pcm043() (0) -#endif - -#ifdef CONFIG_MACH_HANLIN_V3C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HANLIN_V3C -# endif -# define machine_is_hanlin_v3c() (machine_arch_type == MACH_TYPE_HANLIN_V3C) -#else -# define machine_is_hanlin_v3c() (0) -#endif - -#ifdef CONFIG_MACH_KBK9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KBK9G20 -# endif -# define machine_is_kbk9g20() (machine_arch_type == MACH_TYPE_KBK9G20) -#else -# define machine_is_kbk9g20() (0) -#endif - -#ifdef CONFIG_MACH_ADSTURBOG5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSTURBOG5 -# endif -# define machine_is_adsturbog5() (machine_arch_type == MACH_TYPE_ADSTURBOG5) -#else -# define machine_is_adsturbog5() (0) -#endif - -#ifdef CONFIG_MACH_AVENGER_LITE1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVENGER_LITE1 -# endif -# define machine_is_avenger_lite1() (machine_arch_type == MACH_TYPE_AVENGER_LITE1) -#else -# define machine_is_avenger_lite1() (0) -#endif - -#ifdef CONFIG_MACH_SUC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUC -# endif -# define machine_is_suc82x() (machine_arch_type == MACH_TYPE_SUC) -#else -# define machine_is_suc82x() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM7S256 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM7S256 -# endif -# define machine_is_at91sam7s256() (machine_arch_type == MACH_TYPE_AT91SAM7S256) -#else -# define machine_is_at91sam7s256() (0) -#endif - -#ifdef CONFIG_MACH_MENDOZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MENDOZA -# endif -# define machine_is_mendoza() (machine_arch_type == MACH_TYPE_MENDOZA) -#else -# define machine_is_mendoza() (0) -#endif - -#ifdef CONFIG_MACH_KIRA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIRA -# endif -# define machine_is_kira() (machine_arch_type == MACH_TYPE_KIRA) -#else -# define machine_is_kira() (0) -#endif - -#ifdef CONFIG_MACH_MX1HBM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX1HBM -# endif -# define machine_is_mx1hbm() (machine_arch_type == MACH_TYPE_MX1HBM) -#else -# define machine_is_mx1hbm() (0) -#endif - -#ifdef CONFIG_MACH_QUATRO43XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUATRO43XX -# endif -# define machine_is_quatro43xx() (machine_arch_type == MACH_TYPE_QUATRO43XX) -#else -# define machine_is_quatro43xx() (0) -#endif - -#ifdef CONFIG_MACH_QUATRO4230 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUATRO4230 -# endif -# define machine_is_quatro4230() (machine_arch_type == MACH_TYPE_QUATRO4230) -#else -# define machine_is_quatro4230() (0) -#endif - -#ifdef CONFIG_MACH_NSB400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB400 -# endif -# define machine_is_nsb400() (machine_arch_type == MACH_TYPE_NSB400) -#else -# define machine_is_nsb400() (0) -#endif - -#ifdef CONFIG_MACH_DRP255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DRP255 -# endif -# define machine_is_drp255() (machine_arch_type == MACH_TYPE_DRP255) -#else -# define machine_is_drp255() (0) -#endif - -#ifdef CONFIG_MACH_THOTH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_THOTH -# endif -# define machine_is_thoth() (machine_arch_type == MACH_TYPE_THOTH) -#else -# define machine_is_thoth() (0) -#endif - -#ifdef CONFIG_MACH_FIRESTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FIRESTONE -# endif -# define machine_is_firestone() (machine_arch_type == MACH_TYPE_FIRESTONE) -#else -# define machine_is_firestone() (0) -#endif - -#ifdef CONFIG_MACH_ASUSP750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASUSP750 -# endif -# define machine_is_asusp750() (machine_arch_type == MACH_TYPE_ASUSP750) -#else -# define machine_is_asusp750() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_DL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_DL -# endif -# define machine_is_ctera_dl() (machine_arch_type == MACH_TYPE_CTERA_DL) -#else -# define machine_is_ctera_dl() (0) -#endif - -#ifdef CONFIG_MACH_SOCR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOCR -# endif -# define machine_is_socr() (machine_arch_type == MACH_TYPE_SOCR) -#else -# define machine_is_socr() (0) -#endif - -#ifdef CONFIG_MACH_HTCOXYGEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCOXYGEN -# endif -# define machine_is_htcoxygen() (machine_arch_type == MACH_TYPE_HTCOXYGEN) -#else -# define machine_is_htcoxygen() (0) -#endif - -#ifdef CONFIG_MACH_HEROC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HEROC -# endif -# define machine_is_heroc() (machine_arch_type == MACH_TYPE_HEROC) -#else -# define machine_is_heroc() (0) -#endif - -#ifdef CONFIG_MACH_ZENO6800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZENO6800 -# endif -# define machine_is_zeno6800() (machine_arch_type == MACH_TYPE_ZENO6800) -#else -# define machine_is_zeno6800() (0) -#endif - -#ifdef CONFIG_MACH_SC2MCS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SC2MCS -# endif -# define machine_is_sc2mcs() (machine_arch_type == MACH_TYPE_SC2MCS) -#else -# define machine_is_sc2mcs() (0) -#endif - -#ifdef CONFIG_MACH_GENE100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GENE100 -# endif -# define machine_is_gene100() (machine_arch_type == MACH_TYPE_GENE100) -#else -# define machine_is_gene100() (0) -#endif - -#ifdef CONFIG_MACH_AS353X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AS353X -# endif -# define machine_is_as353x() (machine_arch_type == MACH_TYPE_AS353X) -#else -# define machine_is_as353x() (0) -#endif - -#ifdef CONFIG_MACH_SHEEVAPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHEEVAPLUG -# endif -# define machine_is_sheevaplug() (machine_arch_type == MACH_TYPE_SHEEVAPLUG) -#else -# define machine_is_sheevaplug() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20 -# endif -# define machine_is_at91sam9g20() (machine_arch_type == MACH_TYPE_AT91SAM9G20) -#else -# define machine_is_at91sam9g20() (0) -#endif - -#ifdef CONFIG_MACH_MV88F6192GTW_FE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV88F6192GTW_FE -# endif -# define machine_is_mv88f6192gtw_fe() (machine_arch_type == MACH_TYPE_MV88F6192GTW_FE) -#else -# define machine_is_mv88f6192gtw_fe() (0) -#endif - -#ifdef CONFIG_MACH_CC9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9200 -# endif -# define machine_is_cc9200() (machine_arch_type == MACH_TYPE_CC9200) -#else -# define machine_is_cc9200() (0) -#endif - -#ifdef CONFIG_MACH_SM9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SM9200 -# endif -# define machine_is_sm9200() (machine_arch_type == MACH_TYPE_SM9200) -#else -# define machine_is_sm9200() (0) -#endif - -#ifdef CONFIG_MACH_TP9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TP9200 -# endif -# define machine_is_tp9200() (machine_arch_type == MACH_TYPE_TP9200) -#else -# define machine_is_tp9200() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPERDV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPERDV -# endif -# define machine_is_snapperdv() (machine_arch_type == MACH_TYPE_SNAPPERDV) -#else -# define machine_is_snapperdv() (0) -#endif - -#ifdef CONFIG_MACH_AVENGERS_LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVENGERS_LITE -# endif -# define machine_is_avengers_lite() (machine_arch_type == MACH_TYPE_AVENGERS_LITE) -#else -# define machine_is_avengers_lite() (0) -#endif - -#ifdef CONFIG_MACH_AVENGERS_LITE1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVENGERS_LITE1 -# endif -# define machine_is_avengers_lite1() (machine_arch_type == MACH_TYPE_AVENGERS_LITE1) -#else -# define machine_is_avengers_lite1() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3AXON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3AXON -# endif -# define machine_is_omap3axon() (machine_arch_type == MACH_TYPE_OMAP3AXON) -#else -# define machine_is_omap3axon() (0) -#endif - -#ifdef CONFIG_MACH_MA8XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MA8XX -# endif -# define machine_is_ma8xx() (machine_arch_type == MACH_TYPE_MA8XX) -#else -# define machine_is_ma8xx() (0) -#endif - -#ifdef CONFIG_MACH_MP201EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MP201EK -# endif -# define machine_is_mp201ek() (machine_arch_type == MACH_TYPE_MP201EK) -#else -# define machine_is_mp201ek() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_TUX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_TUX -# endif -# define machine_is_davinci_tux() (machine_arch_type == MACH_TYPE_DAVINCI_TUX) -#else -# define machine_is_davinci_tux() (0) -#endif - -#ifdef CONFIG_MACH_MPA1600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MPA1600 -# endif -# define machine_is_mpa1600() (machine_arch_type == MACH_TYPE_MPA1600) -#else -# define machine_is_mpa1600() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_TROY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_TROY -# endif -# define machine_is_pelco_troy() (machine_arch_type == MACH_TYPE_PELCO_TROY) -#else -# define machine_is_pelco_troy() (0) -#endif - -#ifdef CONFIG_MACH_NSB667 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB667 -# endif -# define machine_is_nsb667() (machine_arch_type == MACH_TYPE_NSB667) -#else -# define machine_is_nsb667() (0) -#endif - -#ifdef CONFIG_MACH_ROVERS5_4MPIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERS5_4MPIX -# endif -# define machine_is_rovers5_4mpix() (machine_arch_type == MACH_TYPE_ROVERS5_4MPIX) -#else -# define machine_is_rovers5_4mpix() (0) -#endif - -#ifdef CONFIG_MACH_TWOCOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TWOCOM -# endif -# define machine_is_twocom() (machine_arch_type == MACH_TYPE_TWOCOM) -#else -# define machine_is_twocom() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9_RCU3R2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9_RCU3R2 -# endif -# define machine_is_ubisys_p9_rcu3r2() (machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3R2) -#else -# define machine_is_ubisys_p9_rcu3r2() (0) -#endif - -#ifdef CONFIG_MACH_HERO_ESPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERO_ESPRESSO -# endif -# define machine_is_hero_espresso() (machine_arch_type == MACH_TYPE_HERO_ESPRESSO) -#else -# define machine_is_hero_espresso() (0) -#endif - -#ifdef CONFIG_MACH_AFEUSB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AFEUSB -# endif -# define machine_is_afeusb() (machine_arch_type == MACH_TYPE_AFEUSB) -#else -# define machine_is_afeusb() (0) -#endif - -#ifdef CONFIG_MACH_T830 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T830 -# endif -# define machine_is_t830() (machine_arch_type == MACH_TYPE_T830) -#else -# define machine_is_t830() (0) -#endif - -#ifdef CONFIG_MACH_SPD8020_CC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPD8020_CC -# endif -# define machine_is_spd8020_cc() (machine_arch_type == MACH_TYPE_SPD8020_CC) -#else -# define machine_is_spd8020_cc() (0) -#endif - -#ifdef CONFIG_MACH_OM_3D7K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OM_3D7K -# endif -# define machine_is_om_3d7k() (machine_arch_type == MACH_TYPE_OM_3D7K) -#else -# define machine_is_om_3d7k() (0) -#endif - -#ifdef CONFIG_MACH_PICOCOM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOCOM2 -# endif -# define machine_is_picocom2() (machine_arch_type == MACH_TYPE_PICOCOM2) -#else -# define machine_is_picocom2() (0) -#endif - -#ifdef CONFIG_MACH_UWG4MX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UWG4MX27 -# endif -# define machine_is_uwg4mx27() (machine_arch_type == MACH_TYPE_UWG4MX27) -#else -# define machine_is_uwg4mx27() (0) -#endif - -#ifdef CONFIG_MACH_UWG4MX31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UWG4MX31 -# endif -# define machine_is_uwg4mx31() (machine_arch_type == MACH_TYPE_UWG4MX31) -#else -# define machine_is_uwg4mx31() (0) -#endif - -#ifdef CONFIG_MACH_CHERRY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHERRY -# endif -# define machine_is_cherry() (machine_arch_type == MACH_TYPE_CHERRY) -#else -# define machine_is_cherry() (0) -#endif - -#ifdef CONFIG_MACH_MX51_BABBAGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_BABBAGE -# endif -# define machine_is_mx51_babbage() (machine_arch_type == MACH_TYPE_MX51_BABBAGE) -#else -# define machine_is_mx51_babbage() (0) -#endif - -#ifdef CONFIG_MACH_S3C2440TURKIYE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2440TURKIYE -# endif -# define machine_is_s3c2440turkiye() (machine_arch_type == MACH_TYPE_S3C2440TURKIYE) -#else -# define machine_is_s3c2440turkiye() (0) -#endif - -#ifdef CONFIG_MACH_TX37 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX37 -# endif -# define machine_is_tx37() (machine_arch_type == MACH_TYPE_TX37) -#else -# define machine_is_tx37() (0) -#endif - -#ifdef CONFIG_MACH_SBC2800_9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC2800_9G20 -# endif -# define machine_is_sbc2800_9g20() (machine_arch_type == MACH_TYPE_SBC2800_9G20) -#else -# define machine_is_sbc2800_9g20() (0) -#endif - -#ifdef CONFIG_MACH_BENZGLB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BENZGLB -# endif -# define machine_is_benzglb() (machine_arch_type == MACH_TYPE_BENZGLB) -#else -# define machine_is_benzglb() (0) -#endif - -#ifdef CONFIG_MACH_BENZTD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BENZTD -# endif -# define machine_is_benztd() (machine_arch_type == MACH_TYPE_BENZTD) -#else -# define machine_is_benztd() (0) -#endif - -#ifdef CONFIG_MACH_CARTESIO_PLUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARTESIO_PLUS -# endif -# define machine_is_cartesio_plus() (machine_arch_type == MACH_TYPE_CARTESIO_PLUS) -#else -# define machine_is_cartesio_plus() (0) -#endif - -#ifdef CONFIG_MACH_SOLRAD_G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOLRAD_G20 -# endif -# define machine_is_solrad_g20() (machine_arch_type == MACH_TYPE_SOLRAD_G20) -#else -# define machine_is_solrad_g20() (0) -#endif - -#ifdef CONFIG_MACH_MX27WALLACE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27WALLACE -# endif -# define machine_is_mx27wallace() (machine_arch_type == MACH_TYPE_MX27WALLACE) -#else -# define machine_is_mx27wallace() (0) -#endif - -#ifdef CONFIG_MACH_FMZWEBMODUL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FMZWEBMODUL -# endif -# define machine_is_fmzwebmodul() (machine_arch_type == MACH_TYPE_FMZWEBMODUL) -#else -# define machine_is_fmzwebmodul() (0) -#endif - -#ifdef CONFIG_MACH_RD78X00_MASA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD78X00_MASA -# endif -# define machine_is_rd78x00_masa() (machine_arch_type == MACH_TYPE_RD78X00_MASA) -#else -# define machine_is_rd78x00_masa() (0) -#endif - -#ifdef CONFIG_MACH_SMALLOGGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMALLOGGER -# endif -# define machine_is_smallogger() (machine_arch_type == MACH_TYPE_SMALLOGGER) -#else -# define machine_is_smallogger() (0) -#endif - -#ifdef CONFIG_MACH_CCW9P9215 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9P9215 -# endif -# define machine_is_ccw9p9215() (machine_arch_type == MACH_TYPE_CCW9P9215) -#else -# define machine_is_ccw9p9215() (0) -#endif - -#ifdef CONFIG_MACH_DM355_LEOPARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM355_LEOPARD -# endif -# define machine_is_dm355_leopard() (machine_arch_type == MACH_TYPE_DM355_LEOPARD) -#else -# define machine_is_dm355_leopard() (0) -#endif - -#ifdef CONFIG_MACH_TS219 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS219 -# endif -# define machine_is_ts219() (machine_arch_type == MACH_TYPE_TS219) -#else -# define machine_is_ts219() (0) -#endif - -#ifdef CONFIG_MACH_TNY_A9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNY_A9263 -# endif -# define machine_is_tny_a9263() (machine_arch_type == MACH_TYPE_TNY_A9263) -#else -# define machine_is_tny_a9263() (0) -#endif - -#ifdef CONFIG_MACH_APOLLO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APOLLO -# endif -# define machine_is_apollo() (machine_arch_type == MACH_TYPE_APOLLO) -#else -# define machine_is_apollo() (0) -#endif - -#ifdef CONFIG_MACH_AT91CAP9STK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91CAP9STK -# endif -# define machine_is_at91cap9stk() (machine_arch_type == MACH_TYPE_AT91CAP9STK) -#else -# define machine_is_at91cap9stk() (0) -#endif - -#ifdef CONFIG_MACH_SPC300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPC300 -# endif -# define machine_is_spc300() (machine_arch_type == MACH_TYPE_SPC300) -#else -# define machine_is_spc300() (0) -#endif - -#ifdef CONFIG_MACH_EKO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EKO -# endif -# define machine_is_eko() (machine_arch_type == MACH_TYPE_EKO) -#else -# define machine_is_eko() (0) -#endif - -#ifdef CONFIG_MACH_CCW9M2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9M2443 -# endif -# define machine_is_ccw9m2443() (machine_arch_type == MACH_TYPE_CCW9M2443) -#else -# define machine_is_ccw9m2443() (0) -#endif - -#ifdef CONFIG_MACH_CCW9M2443JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCW9M2443JS -# endif -# define machine_is_ccw9m2443js() (machine_arch_type == MACH_TYPE_CCW9M2443JS) -#else -# define machine_is_ccw9m2443js() (0) -#endif - -#ifdef CONFIG_MACH_M2M_ROUTER_DEVICE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M2M_ROUTER_DEVICE -# endif -# define machine_is_m2m_router_device() (machine_arch_type == MACH_TYPE_M2M_ROUTER_DEVICE) -#else -# define machine_is_m2m_router_device() (0) -#endif - -#ifdef CONFIG_MACH_STAR9104NAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAR9104NAS -# endif -# define machine_is_str9104nas() (machine_arch_type == MACH_TYPE_STAR9104NAS) -#else -# define machine_is_str9104nas() (0) -#endif - -#ifdef CONFIG_MACH_PCA100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCA100 -# endif -# define machine_is_pca100() (machine_arch_type == MACH_TYPE_PCA100) -#else -# define machine_is_pca100() (0) -#endif - -#ifdef CONFIG_MACH_Z3_DM365_MOD_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Z3_DM365_MOD_01 -# endif -# define machine_is_z3_dm365_mod_01() (machine_arch_type == MACH_TYPE_Z3_DM365_MOD_01) -#else -# define machine_is_z3_dm365_mod_01() (0) -#endif - -#ifdef CONFIG_MACH_HIPOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIPOX -# endif -# define machine_is_hipox() (machine_arch_type == MACH_TYPE_HIPOX) -#else -# define machine_is_hipox() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_PITEDS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_PITEDS -# endif -# define machine_is_omap3_piteds() (machine_arch_type == MACH_TYPE_OMAP3_PITEDS) -#else -# define machine_is_omap3_piteds() (0) -#endif - -#ifdef CONFIG_MACH_BM150R -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BM150R -# endif -# define machine_is_bm150r() (machine_arch_type == MACH_TYPE_BM150R) -#else -# define machine_is_bm150r() (0) -#endif - -#ifdef CONFIG_MACH_TBONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TBONE -# endif -# define machine_is_tbone() (machine_arch_type == MACH_TYPE_TBONE) -#else -# define machine_is_tbone() (0) -#endif - -#ifdef CONFIG_MACH_MERLIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MERLIN -# endif -# define machine_is_merlin() (machine_arch_type == MACH_TYPE_MERLIN) -#else -# define machine_is_merlin() (0) -#endif - -#ifdef CONFIG_MACH_FALCON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FALCON -# endif -# define machine_is_falcon() (machine_arch_type == MACH_TYPE_FALCON) -#else -# define machine_is_falcon() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DA850_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DA850_EVM -# endif -# define machine_is_davinci_da850_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) -#else -# define machine_is_davinci_da850_evm() (0) -#endif - -#ifdef CONFIG_MACH_S5P6440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5P6440 -# endif -# define machine_is_s5p6440() (machine_arch_type == MACH_TYPE_S5P6440) -#else -# define machine_is_s5p6440() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G10EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G10EK -# endif -# define machine_is_at91sam9g10ek() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK) -#else -# define machine_is_at91sam9g10ek() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_4430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_4430SDP -# endif -# define machine_is_omap_4430sdp() (machine_arch_type == MACH_TYPE_OMAP_4430SDP) -#else -# define machine_is_omap_4430sdp() (0) -#endif - -#ifdef CONFIG_MACH_LPC313X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC313X -# endif -# define machine_is_lpc313x() (machine_arch_type == MACH_TYPE_LPC313X) -#else -# define machine_is_lpc313x() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_ZN5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_ZN5 -# endif -# define machine_is_magx_zn5() (machine_arch_type == MACH_TYPE_MAGX_ZN5) -#else -# define machine_is_magx_zn5() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_EM30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_EM30 -# endif -# define machine_is_magx_em30() (machine_arch_type == MACH_TYPE_MAGX_EM30) -#else -# define machine_is_magx_em30() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_VE66 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_VE66 -# endif -# define machine_is_magx_ve66() (machine_arch_type == MACH_TYPE_MAGX_VE66) -#else -# define machine_is_magx_ve66() (0) -#endif - -#ifdef CONFIG_MACH_MEESC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEESC -# endif -# define machine_is_meesc() (machine_arch_type == MACH_TYPE_MEESC) -#else -# define machine_is_meesc() (0) -#endif - -#ifdef CONFIG_MACH_OTC570 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTC570 -# endif -# define machine_is_otc570() (machine_arch_type == MACH_TYPE_OTC570) -#else -# define machine_is_otc570() (0) -#endif - -#ifdef CONFIG_MACH_BCU2412 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCU2412 -# endif -# define machine_is_bcu2412() (machine_arch_type == MACH_TYPE_BCU2412) -#else -# define machine_is_bcu2412() (0) -#endif - -#ifdef CONFIG_MACH_BEACON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BEACON -# endif -# define machine_is_beacon() (machine_arch_type == MACH_TYPE_BEACON) -#else -# define machine_is_beacon() (0) -#endif - -#ifdef CONFIG_MACH_ACTIA_TGW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACTIA_TGW -# endif -# define machine_is_actia_tgw() (machine_arch_type == MACH_TYPE_ACTIA_TGW) -#else -# define machine_is_actia_tgw() (0) -#endif - -#ifdef CONFIG_MACH_E4430 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E4430 -# endif -# define machine_is_e4430() (machine_arch_type == MACH_TYPE_E4430) -#else -# define machine_is_e4430() (0) -#endif - -#ifdef CONFIG_MACH_QL300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QL300 -# endif -# define machine_is_ql300() (machine_arch_type == MACH_TYPE_QL300) -#else -# define machine_is_ql300() (0) -#endif - -#ifdef CONFIG_MACH_BTMAVB101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTMAVB101 -# endif -# define machine_is_btmavb101() (machine_arch_type == MACH_TYPE_BTMAVB101) -#else -# define machine_is_btmavb101() (0) -#endif - -#ifdef CONFIG_MACH_BTMAWB101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTMAWB101 -# endif -# define machine_is_btmawb101() (machine_arch_type == MACH_TYPE_BTMAWB101) -#else -# define machine_is_btmawb101() (0) -#endif - -#ifdef CONFIG_MACH_SQ201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SQ201 -# endif -# define machine_is_sq201() (machine_arch_type == MACH_TYPE_SQ201) -#else -# define machine_is_sq201() (0) -#endif - -#ifdef CONFIG_MACH_QUATRO45XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUATRO45XX -# endif -# define machine_is_quatro45xx() (machine_arch_type == MACH_TYPE_QUATRO45XX) -#else -# define machine_is_quatro45xx() (0) -#endif - -#ifdef CONFIG_MACH_OPENPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENPAD -# endif -# define machine_is_openpad() (machine_arch_type == MACH_TYPE_OPENPAD) -#else -# define machine_is_openpad() (0) -#endif - -#ifdef CONFIG_MACH_TX25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX25 -# endif -# define machine_is_tx25() (machine_arch_type == MACH_TYPE_TX25) -#else -# define machine_is_tx25() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_TORPEDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_TORPEDO -# endif -# define machine_is_omap3_torpedo() (machine_arch_type == MACH_TYPE_OMAP3_TORPEDO) -#else -# define machine_is_omap3_torpedo() (0) -#endif - -#ifdef CONFIG_MACH_HTCRAPHAEL_K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRAPHAEL_K -# endif -# define machine_is_htcraphael_k() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_K) -#else -# define machine_is_htcraphael_k() (0) -#endif - -#ifdef CONFIG_MACH_LAL43 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LAL43 -# endif -# define machine_is_lal43() (machine_arch_type == MACH_TYPE_LAL43) -#else -# define machine_is_lal43() (0) -#endif - -#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA500 -# endif -# define machine_is_htcraphael_cdma500() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA500) -#else -# define machine_is_htcraphael_cdma500() (0) -#endif - -#ifdef CONFIG_MACH_ANW6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANW6410 -# endif -# define machine_is_anw6410() (machine_arch_type == MACH_TYPE_ANW6410) -#else -# define machine_is_anw6410() (0) -#endif - -#ifdef CONFIG_MACH_HTCPROPHET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCPROPHET -# endif -# define machine_is_htcprophet() (machine_arch_type == MACH_TYPE_HTCPROPHET) -#else -# define machine_is_htcprophet() (0) -#endif - -#ifdef CONFIG_MACH_CFA_10022 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CFA_10022 -# endif -# define machine_is_cfa_10022() (machine_arch_type == MACH_TYPE_CFA_10022) -#else -# define machine_is_cfa_10022() (0) -#endif - -#ifdef CONFIG_MACH_IMX27_VISSTRIM_M10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27_VISSTRIM_M10 -# endif -# define machine_is_imx27_visstrim_m10() (machine_arch_type == MACH_TYPE_IMX27_VISSTRIM_M10) -#else -# define machine_is_imx27_visstrim_m10() (0) -#endif - -#ifdef CONFIG_MACH_PX2IMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PX2IMX27 -# endif -# define machine_is_px2imx27() (machine_arch_type == MACH_TYPE_PX2IMX27) -#else -# define machine_is_px2imx27() (0) -#endif - -#ifdef CONFIG_MACH_STM3210E_EVAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STM3210E_EVAL -# endif -# define machine_is_stm3210e_eval() (machine_arch_type == MACH_TYPE_STM3210E_EVAL) -#else -# define machine_is_stm3210e_eval() (0) -#endif - -#ifdef CONFIG_MACH_DVS10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DVS10 -# endif -# define machine_is_dvs10() (machine_arch_type == MACH_TYPE_DVS10) -#else -# define machine_is_dvs10() (0) -#endif - -#ifdef CONFIG_MACH_PORTUXG20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PORTUXG20 -# endif -# define machine_is_portuxg20() (machine_arch_type == MACH_TYPE_PORTUXG20) -#else -# define machine_is_portuxg20() (0) -#endif - -#ifdef CONFIG_MACH_ARM_SPV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM_SPV -# endif -# define machine_is_arm_spv() (machine_arch_type == MACH_TYPE_ARM_SPV) -#else -# define machine_is_arm_spv() (0) -#endif - -#ifdef CONFIG_MACH_SMDKC110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKC110 -# endif -# define machine_is_smdkc110() (machine_arch_type == MACH_TYPE_SMDKC110) -#else -# define machine_is_smdkc110() (0) -#endif - -#ifdef CONFIG_MACH_CABESPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CABESPRESSO -# endif -# define machine_is_cabespresso() (machine_arch_type == MACH_TYPE_CABESPRESSO) -#else -# define machine_is_cabespresso() (0) -#endif - -#ifdef CONFIG_MACH_HMC800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMC800 -# endif -# define machine_is_hmc800() (machine_arch_type == MACH_TYPE_HMC800) -#else -# define machine_is_hmc800() (0) -#endif - -#ifdef CONFIG_MACH_SHOLES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHOLES -# endif -# define machine_is_sholes() (machine_arch_type == MACH_TYPE_SHOLES) -#else -# define machine_is_sholes() (0) -#endif - -#ifdef CONFIG_MACH_BTMXC31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTMXC31 -# endif -# define machine_is_btmxc31() (machine_arch_type == MACH_TYPE_BTMXC31) -#else -# define machine_is_btmxc31() (0) -#endif - -#ifdef CONFIG_MACH_DT501 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DT501 -# endif -# define machine_is_dt501() (machine_arch_type == MACH_TYPE_DT501) -#else -# define machine_is_dt501() (0) -#endif - -#ifdef CONFIG_MACH_KTX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KTX -# endif -# define machine_is_ktx() (machine_arch_type == MACH_TYPE_KTX) -#else -# define machine_is_ktx() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3517EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3517EVM -# endif -# define machine_is_omap3517evm() (machine_arch_type == MACH_TYPE_OMAP3517EVM) -#else -# define machine_is_omap3517evm() (0) -#endif - -#ifdef CONFIG_MACH_NETSPACE_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETSPACE_V2 -# endif -# define machine_is_netspace_v2() (machine_arch_type == MACH_TYPE_NETSPACE_V2) -#else -# define machine_is_netspace_v2() (0) -#endif - -#ifdef CONFIG_MACH_NETSPACE_MAX_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETSPACE_MAX_V2 -# endif -# define machine_is_netspace_max_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MAX_V2) -#else -# define machine_is_netspace_max_v2() (0) -#endif - -#ifdef CONFIG_MACH_D2NET_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D2NET_V2 -# endif -# define machine_is_d2net_v2() (machine_arch_type == MACH_TYPE_D2NET_V2) -#else -# define machine_is_d2net_v2() (0) -#endif - -#ifdef CONFIG_MACH_NET2BIG_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET2BIG_V2 -# endif -# define machine_is_net2big_v2() (machine_arch_type == MACH_TYPE_NET2BIG_V2) -#else -# define machine_is_net2big_v2() (0) -#endif - -#ifdef CONFIG_MACH_NET4BIG_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET4BIG_V2 -# endif -# define machine_is_net4big_v2() (machine_arch_type == MACH_TYPE_NET4BIG_V2) -#else -# define machine_is_net4big_v2() (0) -#endif - -#ifdef CONFIG_MACH_NET5BIG_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET5BIG_V2 -# endif -# define machine_is_net5big_v2() (machine_arch_type == MACH_TYPE_NET5BIG_V2) -#else -# define machine_is_net5big_v2() (0) -#endif - -#ifdef CONFIG_MACH_ENDB2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENDB2443 -# endif -# define machine_is_endb2443() (machine_arch_type == MACH_TYPE_ENDB2443) -#else -# define machine_is_endb2443() (0) -#endif - -#ifdef CONFIG_MACH_INETSPACE_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INETSPACE_V2 -# endif -# define machine_is_inetspace_v2() (machine_arch_type == MACH_TYPE_INETSPACE_V2) -#else -# define machine_is_inetspace_v2() (0) -#endif - -#ifdef CONFIG_MACH_TROS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TROS -# endif -# define machine_is_tros() (machine_arch_type == MACH_TYPE_TROS) -#else -# define machine_is_tros() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_HOMER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_HOMER -# endif -# define machine_is_pelco_homer() (machine_arch_type == MACH_TYPE_PELCO_HOMER) -#else -# define machine_is_pelco_homer() (0) -#endif - -#ifdef CONFIG_MACH_OFSP8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OFSP8 -# endif -# define machine_is_ofsp8() (machine_arch_type == MACH_TYPE_OFSP8) -#else -# define machine_is_ofsp8() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G45EKES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G45EKES -# endif -# define machine_is_at91sam9g45ekes() (machine_arch_type == MACH_TYPE_AT91SAM9G45EKES) -#else -# define machine_is_at91sam9g45ekes() (0) -#endif - -#ifdef CONFIG_MACH_GUF_CUPID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUF_CUPID -# endif -# define machine_is_guf_cupid() (machine_arch_type == MACH_TYPE_GUF_CUPID) -#else -# define machine_is_guf_cupid() (0) -#endif - -#ifdef CONFIG_MACH_EAB1R -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EAB1R -# endif -# define machine_is_eab1r() (machine_arch_type == MACH_TYPE_EAB1R) -#else -# define machine_is_eab1r() (0) -#endif - -#ifdef CONFIG_MACH_DESIREC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DESIREC -# endif -# define machine_is_desirec() (machine_arch_type == MACH_TYPE_DESIREC) -#else -# define machine_is_desirec() (0) -#endif - -#ifdef CONFIG_MACH_CORDOBA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORDOBA -# endif -# define machine_is_cordoba() (machine_arch_type == MACH_TYPE_CORDOBA) -#else -# define machine_is_cordoba() (0) -#endif - -#ifdef CONFIG_MACH_IRVINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IRVINE -# endif -# define machine_is_irvine() (machine_arch_type == MACH_TYPE_IRVINE) -#else -# define machine_is_irvine() (0) -#endif - -#ifdef CONFIG_MACH_SFF772 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SFF772 -# endif -# define machine_is_sff772() (machine_arch_type == MACH_TYPE_SFF772) -#else -# define machine_is_sff772() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_MILANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_MILANO -# endif -# define machine_is_pelco_milano() (machine_arch_type == MACH_TYPE_PELCO_MILANO) -#else -# define machine_is_pelco_milano() (0) -#endif - -#ifdef CONFIG_MACH_PC7302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC7302 -# endif -# define machine_is_pc7302() (machine_arch_type == MACH_TYPE_PC7302) -#else -# define machine_is_pc7302() (0) -#endif - -#ifdef CONFIG_MACH_BIP6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIP6000 -# endif -# define machine_is_bip6000() (machine_arch_type == MACH_TYPE_BIP6000) -#else -# define machine_is_bip6000() (0) -#endif - -#ifdef CONFIG_MACH_SILVERMOON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SILVERMOON -# endif -# define machine_is_silvermoon() (machine_arch_type == MACH_TYPE_SILVERMOON) -#else -# define machine_is_silvermoon() (0) -#endif - -#ifdef CONFIG_MACH_VC0830 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC0830 -# endif -# define machine_is_vc0830() (machine_arch_type == MACH_TYPE_VC0830) -#else -# define machine_is_vc0830() (0) -#endif - -#ifdef CONFIG_MACH_DT430 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DT430 -# endif -# define machine_is_dt430() (machine_arch_type == MACH_TYPE_DT430) -#else -# define machine_is_dt430() (0) -#endif - -#ifdef CONFIG_MACH_JI42PF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JI42PF -# endif -# define machine_is_ji42pf() (machine_arch_type == MACH_TYPE_JI42PF) -#else -# define machine_is_ji42pf() (0) -#endif - -#ifdef CONFIG_MACH_GNET_KSM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_KSM -# endif -# define machine_is_gnet_ksm() (machine_arch_type == MACH_TYPE_GNET_KSM) -#else -# define machine_is_gnet_ksm() (0) -#endif - -#ifdef CONFIG_MACH_GNET_SGM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_SGM -# endif -# define machine_is_gnet_sgm() (machine_arch_type == MACH_TYPE_GNET_SGM) -#else -# define machine_is_gnet_sgm() (0) -#endif - -#ifdef CONFIG_MACH_GNET_SGR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_SGR -# endif -# define machine_is_gnet_sgr() (machine_arch_type == MACH_TYPE_GNET_SGR) -#else -# define machine_is_gnet_sgr() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_ICETEKEVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_ICETEKEVM -# endif -# define machine_is_omap3_icetekevm() (machine_arch_type == MACH_TYPE_OMAP3_ICETEKEVM) -#else -# define machine_is_omap3_icetekevm() (0) -#endif - -#ifdef CONFIG_MACH_PNP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNP -# endif -# define machine_is_pnp() (machine_arch_type == MACH_TYPE_PNP) -#else -# define machine_is_pnp() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_2BAY_K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_2BAY_K -# endif -# define machine_is_ctera_2bay_k() (machine_arch_type == MACH_TYPE_CTERA_2BAY_K) -#else -# define machine_is_ctera_2bay_k() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_2BAY_U -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_2BAY_U -# endif -# define machine_is_ctera_2bay_u() (machine_arch_type == MACH_TYPE_CTERA_2BAY_U) -#else -# define machine_is_ctera_2bay_u() (0) -#endif - -#ifdef CONFIG_MACH_SAS_C -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAS_C -# endif -# define machine_is_sas_c() (machine_arch_type == MACH_TYPE_SAS_C) -#else -# define machine_is_sas_c() (0) -#endif - -#ifdef CONFIG_MACH_VMA2315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VMA2315 -# endif -# define machine_is_vma2315() (machine_arch_type == MACH_TYPE_VMA2315) -#else -# define machine_is_vma2315() (0) -#endif - -#ifdef CONFIG_MACH_VCS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VCS -# endif -# define machine_is_vcs() (machine_arch_type == MACH_TYPE_VCS) -#else -# define machine_is_vcs() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR600 -# endif -# define machine_is_spear600() (machine_arch_type == MACH_TYPE_SPEAR600) -#else -# define machine_is_spear600() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR300 -# endif -# define machine_is_spear300() (machine_arch_type == MACH_TYPE_SPEAR300) -#else -# define machine_is_spear300() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR1300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR1300 -# endif -# define machine_is_spear1300() (machine_arch_type == MACH_TYPE_SPEAR1300) -#else -# define machine_is_spear1300() (0) -#endif - -#ifdef CONFIG_MACH_LILLY1131 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LILLY1131 -# endif -# define machine_is_lilly1131() (machine_arch_type == MACH_TYPE_LILLY1131) -#else -# define machine_is_lilly1131() (0) -#endif - -#ifdef CONFIG_MACH_ARVOO_AX301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARVOO_AX301 -# endif -# define machine_is_arvoo_ax301() (machine_arch_type == MACH_TYPE_ARVOO_AX301) -#else -# define machine_is_arvoo_ax301() (0) -#endif - -#ifdef CONFIG_MACH_MAPPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAPPHONE -# endif -# define machine_is_mapphone() (machine_arch_type == MACH_TYPE_MAPPHONE) -#else -# define machine_is_mapphone() (0) -#endif - -#ifdef CONFIG_MACH_LEGEND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEGEND -# endif -# define machine_is_legend() (machine_arch_type == MACH_TYPE_LEGEND) -#else -# define machine_is_legend() (0) -#endif - -#ifdef CONFIG_MACH_SALSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SALSA -# endif -# define machine_is_salsa() (machine_arch_type == MACH_TYPE_SALSA) -#else -# define machine_is_salsa() (0) -#endif - -#ifdef CONFIG_MACH_LOUNGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOUNGE -# endif -# define machine_is_lounge() (machine_arch_type == MACH_TYPE_LOUNGE) -#else -# define machine_is_lounge() (0) -#endif - -#ifdef CONFIG_MACH_VISION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VISION -# endif -# define machine_is_vision() (machine_arch_type == MACH_TYPE_VISION) -#else -# define machine_is_vision() (0) -#endif - -#ifdef CONFIG_MACH_VMB20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VMB20 -# endif -# define machine_is_vmb20() (machine_arch_type == MACH_TYPE_VMB20) -#else -# define machine_is_vmb20() (0) -#endif - -#ifdef CONFIG_MACH_HY2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HY2410 -# endif -# define machine_is_hy2410() (machine_arch_type == MACH_TYPE_HY2410) -#else -# define machine_is_hy2410() (0) -#endif - -#ifdef CONFIG_MACH_HY9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HY9315 -# endif -# define machine_is_hy9315() (machine_arch_type == MACH_TYPE_HY9315) -#else -# define machine_is_hy9315() (0) -#endif - -#ifdef CONFIG_MACH_BULLWINKLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BULLWINKLE -# endif -# define machine_is_bullwinkle() (machine_arch_type == MACH_TYPE_BULLWINKLE) -#else -# define machine_is_bullwinkle() (0) -#endif - -#ifdef CONFIG_MACH_ARM_ULTIMATOR2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM_ULTIMATOR2 -# endif -# define machine_is_arm_ultimator2() (machine_arch_type == MACH_TYPE_ARM_ULTIMATOR2) -#else -# define machine_is_arm_ultimator2() (0) -#endif - -#ifdef CONFIG_MACH_VS_V210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VS_V210 -# endif -# define machine_is_vs_v210() (machine_arch_type == MACH_TYPE_VS_V210) -#else -# define machine_is_vs_v210() (0) -#endif - -#ifdef CONFIG_MACH_VS_V212 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VS_V212 -# endif -# define machine_is_vs_v212() (machine_arch_type == MACH_TYPE_VS_V212) -#else -# define machine_is_vs_v212() (0) -#endif - -#ifdef CONFIG_MACH_HMT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMT -# endif -# define machine_is_hmt() (machine_arch_type == MACH_TYPE_HMT) -#else -# define machine_is_hmt() (0) -#endif - -#ifdef CONFIG_MACH_SUEN3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUEN3 -# endif -# define machine_is_suen3() (machine_arch_type == MACH_TYPE_SUEN3) -#else -# define machine_is_suen3() (0) -#endif - -#ifdef CONFIG_MACH_VESPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VESPER -# endif -# define machine_is_vesper() (machine_arch_type == MACH_TYPE_VESPER) -#else -# define machine_is_vesper() (0) -#endif - -#ifdef CONFIG_MACH_STR9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STR9 -# endif -# define machine_is_str9() (machine_arch_type == MACH_TYPE_STR9) -#else -# define machine_is_str9() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_WL_FF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_WL_FF -# endif -# define machine_is_omap3_wl_ff() (machine_arch_type == MACH_TYPE_OMAP3_WL_FF) -#else -# define machine_is_omap3_wl_ff() (0) -#endif - -#ifdef CONFIG_MACH_SIMCOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMCOM -# endif -# define machine_is_simcom() (machine_arch_type == MACH_TYPE_SIMCOM) -#else -# define machine_is_simcom() (0) -#endif - -#ifdef CONFIG_MACH_MCWEBIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCWEBIO -# endif -# define machine_is_mcwebio() (machine_arch_type == MACH_TYPE_MCWEBIO) -#else -# define machine_is_mcwebio() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_PHRAZER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_PHRAZER -# endif -# define machine_is_omap3_phrazer() (machine_arch_type == MACH_TYPE_OMAP3_PHRAZER) -#else -# define machine_is_omap3_phrazer() (0) -#endif - -#ifdef CONFIG_MACH_DARWIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DARWIN -# endif -# define machine_is_darwin() (machine_arch_type == MACH_TYPE_DARWIN) -#else -# define machine_is_darwin() (0) -#endif - -#ifdef CONFIG_MACH_ORATISCOMU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISCOMU -# endif -# define machine_is_oratiscomu() (machine_arch_type == MACH_TYPE_ORATISCOMU) -#else -# define machine_is_oratiscomu() (0) -#endif - -#ifdef CONFIG_MACH_RTSBC20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RTSBC20 -# endif -# define machine_is_rtsbc20() (machine_arch_type == MACH_TYPE_RTSBC20) -#else -# define machine_is_rtsbc20() (0) -#endif - -#ifdef CONFIG_MACH_I780 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_I780 -# endif -# define machine_is_sgh_i780() (machine_arch_type == MACH_TYPE_I780) -#else -# define machine_is_sgh_i780() (0) -#endif - -#ifdef CONFIG_MACH_GEMINI324 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEMINI324 -# endif -# define machine_is_gemini324() (machine_arch_type == MACH_TYPE_GEMINI324) -#else -# define machine_is_gemini324() (0) -#endif - -#ifdef CONFIG_MACH_ORATISLAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISLAN -# endif -# define machine_is_oratislan() (machine_arch_type == MACH_TYPE_ORATISLAN) -#else -# define machine_is_oratislan() (0) -#endif - -#ifdef CONFIG_MACH_ORATISALOG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISALOG -# endif -# define machine_is_oratisalog() (machine_arch_type == MACH_TYPE_ORATISALOG) -#else -# define machine_is_oratisalog() (0) -#endif - -#ifdef CONFIG_MACH_ORATISMADI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISMADI -# endif -# define machine_is_oratismadi() (machine_arch_type == MACH_TYPE_ORATISMADI) -#else -# define machine_is_oratismadi() (0) -#endif - -#ifdef CONFIG_MACH_ORATISOT16 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISOT16 -# endif -# define machine_is_oratisot16() (machine_arch_type == MACH_TYPE_ORATISOT16) -#else -# define machine_is_oratisot16() (0) -#endif - -#ifdef CONFIG_MACH_ORATISDESK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISDESK -# endif -# define machine_is_oratisdesk() (machine_arch_type == MACH_TYPE_ORATISDESK) -#else -# define machine_is_oratisdesk() (0) -#endif - -#ifdef CONFIG_MACH_VEXPRESS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VEXPRESS -# endif -# define machine_is_vexpress() (machine_arch_type == MACH_TYPE_VEXPRESS) -#else -# define machine_is_vexpress() (0) -#endif - -#ifdef CONFIG_MACH_SINTEXO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SINTEXO -# endif -# define machine_is_sintexo() (machine_arch_type == MACH_TYPE_SINTEXO) -#else -# define machine_is_sintexo() (0) -#endif - -#ifdef CONFIG_MACH_CM3389 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM3389 -# endif -# define machine_is_cm3389() (machine_arch_type == MACH_TYPE_CM3389) -#else -# define machine_is_cm3389() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_CIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_CIO -# endif -# define machine_is_omap3_cio() (machine_arch_type == MACH_TYPE_OMAP3_CIO) -#else -# define machine_is_omap3_cio() (0) -#endif - -#ifdef CONFIG_MACH_SGH_I900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SGH_I900 -# endif -# define machine_is_sgh_i900() (machine_arch_type == MACH_TYPE_SGH_I900) -#else -# define machine_is_sgh_i900() (0) -#endif - -#ifdef CONFIG_MACH_BST100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BST100 -# endif -# define machine_is_bst100() (machine_arch_type == MACH_TYPE_BST100) -#else -# define machine_is_bst100() (0) -#endif - -#ifdef CONFIG_MACH_PASSION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PASSION -# endif -# define machine_is_passion() (machine_arch_type == MACH_TYPE_PASSION) -#else -# define machine_is_passion() (0) -#endif - -#ifdef CONFIG_MACH_INDESIGN_AT91SAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INDESIGN_AT91SAM -# endif -# define machine_is_indesign_at91sam() (machine_arch_type == MACH_TYPE_INDESIGN_AT91SAM) -#else -# define machine_is_indesign_at91sam() (0) -#endif - -#ifdef CONFIG_MACH_C4_BADGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C4_BADGER -# endif -# define machine_is_c4_badger() (machine_arch_type == MACH_TYPE_C4_BADGER) -#else -# define machine_is_c4_badger() (0) -#endif - -#ifdef CONFIG_MACH_C4_VIPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C4_VIPER -# endif -# define machine_is_c4_viper() (machine_arch_type == MACH_TYPE_C4_VIPER) -#else -# define machine_is_c4_viper() (0) -#endif - -#ifdef CONFIG_MACH_D2NET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D2NET -# endif -# define machine_is_d2net() (machine_arch_type == MACH_TYPE_D2NET) -#else -# define machine_is_d2net() (0) -#endif - -#ifdef CONFIG_MACH_BIGDISK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIGDISK -# endif -# define machine_is_bigdisk() (machine_arch_type == MACH_TYPE_BIGDISK) -#else -# define machine_is_bigdisk() (0) -#endif - -#ifdef CONFIG_MACH_NOTALVISION -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOTALVISION -# endif -# define machine_is_notalvision() (machine_arch_type == MACH_TYPE_NOTALVISION) -#else -# define machine_is_notalvision() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_KBOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_KBOC -# endif -# define machine_is_omap3_kboc() (machine_arch_type == MACH_TYPE_OMAP3_KBOC) -#else -# define machine_is_omap3_kboc() (0) -#endif - -#ifdef CONFIG_MACH_CYCLONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYCLONE -# endif -# define machine_is_cyclone() (machine_arch_type == MACH_TYPE_CYCLONE) -#else -# define machine_is_cyclone() (0) -#endif - -#ifdef CONFIG_MACH_NINJA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NINJA -# endif -# define machine_is_ninja() (machine_arch_type == MACH_TYPE_NINJA) -#else -# define machine_is_ninja() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20EK_2MMC -# endif -# define machine_is_at91sam9g20ek_2mmc() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC) -#else -# define machine_is_at91sam9g20ek_2mmc() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING -# endif -# define machine_is_bcmring() (machine_arch_type == MACH_TYPE_BCMRING) -#else -# define machine_is_bcmring() (0) -#endif - -#ifdef CONFIG_MACH_RESOL_DL2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RESOL_DL2 -# endif -# define machine_is_resol_dl2() (machine_arch_type == MACH_TYPE_RESOL_DL2) -#else -# define machine_is_resol_dl2() (0) -#endif - -#ifdef CONFIG_MACH_IFOSW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IFOSW -# endif -# define machine_is_ifosw() (machine_arch_type == MACH_TYPE_IFOSW) -#else -# define machine_is_ifosw() (0) -#endif - -#ifdef CONFIG_MACH_HTCRHODIUM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCRHODIUM -# endif -# define machine_is_htcrhodium() (machine_arch_type == MACH_TYPE_HTCRHODIUM) -#else -# define machine_is_htcrhodium() (0) -#endif - -#ifdef CONFIG_MACH_HTCTOPAZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCTOPAZ -# endif -# define machine_is_htctopaz() (machine_arch_type == MACH_TYPE_HTCTOPAZ) -#else -# define machine_is_htctopaz() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX504 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX504 -# endif -# define machine_is_matrix504() (machine_arch_type == MACH_TYPE_MATRIX504) -#else -# define machine_is_matrix504() (0) -#endif - -#ifdef CONFIG_MACH_MRFSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MRFSA -# endif -# define machine_is_mrfsa() (machine_arch_type == MACH_TYPE_MRFSA) -#else -# define machine_is_mrfsa() (0) -#endif - -#ifdef CONFIG_MACH_SC_P270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SC_P270 -# endif -# define machine_is_sc_p270() (machine_arch_type == MACH_TYPE_SC_P270) -#else -# define machine_is_sc_p270() (0) -#endif - -#ifdef CONFIG_MACH_ATLAS5_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATLAS5_EVB -# endif -# define machine_is_atlas5_evb() (machine_arch_type == MACH_TYPE_ATLAS5_EVB) -#else -# define machine_is_atlas5_evb() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_LOBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_LOBOX -# endif -# define machine_is_pelco_lobox() (machine_arch_type == MACH_TYPE_PELCO_LOBOX) -#else -# define machine_is_pelco_lobox() (0) -#endif - -#ifdef CONFIG_MACH_DILAX_PCU200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DILAX_PCU200 -# endif -# define machine_is_dilax_pcu200() (machine_arch_type == MACH_TYPE_DILAX_PCU200) -#else -# define machine_is_dilax_pcu200() (0) -#endif - -#ifdef CONFIG_MACH_LEONARDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEONARDO -# endif -# define machine_is_leonardo() (machine_arch_type == MACH_TYPE_LEONARDO) -#else -# define machine_is_leonardo() (0) -#endif - -#ifdef CONFIG_MACH_ZORAN_APPROACH7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZORAN_APPROACH7 -# endif -# define machine_is_zoran_approach7() (machine_arch_type == MACH_TYPE_ZORAN_APPROACH7) -#else -# define machine_is_zoran_approach7() (0) -#endif - -#ifdef CONFIG_MACH_DP6XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DP6XX -# endif -# define machine_is_dp6xx() (machine_arch_type == MACH_TYPE_DP6XX) -#else -# define machine_is_dp6xx() (0) -#endif - -#ifdef CONFIG_MACH_BCM2153_VESPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCM2153_VESPER -# endif -# define machine_is_bcm2153_vesper() (machine_arch_type == MACH_TYPE_BCM2153_VESPER) -#else -# define machine_is_bcm2153_vesper() (0) -#endif - -#ifdef CONFIG_MACH_MAHIMAHI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAHIMAHI -# endif -# define machine_is_mahimahi() (machine_arch_type == MACH_TYPE_MAHIMAHI) -#else -# define machine_is_mahimahi() (0) -#endif - -#ifdef CONFIG_MACH_CLICKC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLICKC -# endif -# define machine_is_clickc() (machine_arch_type == MACH_TYPE_CLICKC) -#else -# define machine_is_clickc() (0) -#endif - -#ifdef CONFIG_MACH_ZB_GATEWAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZB_GATEWAY -# endif -# define machine_is_zb_gateway() (machine_arch_type == MACH_TYPE_ZB_GATEWAY) -#else -# define machine_is_zb_gateway() (0) -#endif - -#ifdef CONFIG_MACH_TAZCARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAZCARD -# endif -# define machine_is_tazcard() (machine_arch_type == MACH_TYPE_TAZCARD) -#else -# define machine_is_tazcard() (0) -#endif - -#ifdef CONFIG_MACH_TAZDEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAZDEV -# endif -# define machine_is_tazdev() (machine_arch_type == MACH_TYPE_TAZDEV) -#else -# define machine_is_tazdev() (0) -#endif - -#ifdef CONFIG_MACH_ANNAX_CB_ARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANNAX_CB_ARM -# endif -# define machine_is_annax_cb_arm() (machine_arch_type == MACH_TYPE_ANNAX_CB_ARM) -#else -# define machine_is_annax_cb_arm() (0) -#endif - -#ifdef CONFIG_MACH_ANNAX_DM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANNAX_DM3 -# endif -# define machine_is_annax_dm3() (machine_arch_type == MACH_TYPE_ANNAX_DM3) -#else -# define machine_is_annax_dm3() (0) -#endif - -#ifdef CONFIG_MACH_CEREBRIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEREBRIC -# endif -# define machine_is_cerebric() (machine_arch_type == MACH_TYPE_CEREBRIC) -#else -# define machine_is_cerebric() (0) -#endif - -#ifdef CONFIG_MACH_ORCA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORCA -# endif -# define machine_is_orca() (machine_arch_type == MACH_TYPE_ORCA) -#else -# define machine_is_orca() (0) -#endif - -#ifdef CONFIG_MACH_PC9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC9260 -# endif -# define machine_is_pc9260() (machine_arch_type == MACH_TYPE_PC9260) -#else -# define machine_is_pc9260() (0) -#endif - -#ifdef CONFIG_MACH_EMS285A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMS285A -# endif -# define machine_is_ems285a() (machine_arch_type == MACH_TYPE_EMS285A) -#else -# define machine_is_ems285a() (0) -#endif - -#ifdef CONFIG_MACH_GEC2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEC2410 -# endif -# define machine_is_gec2410() (machine_arch_type == MACH_TYPE_GEC2410) -#else -# define machine_is_gec2410() (0) -#endif - -#ifdef CONFIG_MACH_GEC2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GEC2440 -# endif -# define machine_is_gec2440() (machine_arch_type == MACH_TYPE_GEC2440) -#else -# define machine_is_gec2440() (0) -#endif - -#ifdef CONFIG_MACH_ARCH_MW903 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCH_MW903 -# endif -# define machine_is_mw903() (machine_arch_type == MACH_TYPE_ARCH_MW903) -#else -# define machine_is_mw903() (0) -#endif - -#ifdef CONFIG_MACH_MW2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MW2440 -# endif -# define machine_is_mw2440() (machine_arch_type == MACH_TYPE_MW2440) -#else -# define machine_is_mw2440() (0) -#endif - -#ifdef CONFIG_MACH_ECAC2378 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECAC2378 -# endif -# define machine_is_ecac2378() (machine_arch_type == MACH_TYPE_ECAC2378) -#else -# define machine_is_ecac2378() (0) -#endif - -#ifdef CONFIG_MACH_TAZKIOSK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAZKIOSK -# endif -# define machine_is_tazkiosk() (machine_arch_type == MACH_TYPE_TAZKIOSK) -#else -# define machine_is_tazkiosk() (0) -#endif - -#ifdef CONFIG_MACH_WHITERABBIT_MCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WHITERABBIT_MCH -# endif -# define machine_is_whiterabbit_mch() (machine_arch_type == MACH_TYPE_WHITERABBIT_MCH) -#else -# define machine_is_whiterabbit_mch() (0) -#endif - -#ifdef CONFIG_MACH_SBOX9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBOX9263 -# endif -# define machine_is_sbox9263() (machine_arch_type == MACH_TYPE_SBOX9263) -#else -# define machine_is_sbox9263() (0) -#endif - -#ifdef CONFIG_MACH_OREO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OREO -# endif -# define machine_is_oreo() (machine_arch_type == MACH_TYPE_OREO) -#else -# define machine_is_oreo() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6442 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6442 -# endif -# define machine_is_smdk6442() (machine_arch_type == MACH_TYPE_SMDK6442) -#else -# define machine_is_smdk6442() (0) -#endif - -#ifdef CONFIG_MACH_OPENRD_BASE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENRD_BASE -# endif -# define machine_is_openrd_base() (machine_arch_type == MACH_TYPE_OPENRD_BASE) -#else -# define machine_is_openrd_base() (0) -#endif - -#ifdef CONFIG_MACH_INCREDIBLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INCREDIBLE -# endif -# define machine_is_incredible() (machine_arch_type == MACH_TYPE_INCREDIBLE) -#else -# define machine_is_incredible() (0) -#endif - -#ifdef CONFIG_MACH_INCREDIBLEC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INCREDIBLEC -# endif -# define machine_is_incrediblec() (machine_arch_type == MACH_TYPE_INCREDIBLEC) -#else -# define machine_is_incrediblec() (0) -#endif - -#ifdef CONFIG_MACH_HEROCT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HEROCT -# endif -# define machine_is_heroct() (machine_arch_type == MACH_TYPE_HEROCT) -#else -# define machine_is_heroct() (0) -#endif - -#ifdef CONFIG_MACH_MMNET1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMNET1000 -# endif -# define machine_is_mmnet1000() (machine_arch_type == MACH_TYPE_MMNET1000) -#else -# define machine_is_mmnet1000() (0) -#endif - -#ifdef CONFIG_MACH_DEVKIT8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEVKIT8000 -# endif -# define machine_is_devkit8000() (machine_arch_type == MACH_TYPE_DEVKIT8000) -#else -# define machine_is_devkit8000() (0) -#endif - -#ifdef CONFIG_MACH_DEVKIT9000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEVKIT9000 -# endif -# define machine_is_devkit9000() (machine_arch_type == MACH_TYPE_DEVKIT9000) -#else -# define machine_is_devkit9000() (0) -#endif - -#ifdef CONFIG_MACH_MX31TXTR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31TXTR -# endif -# define machine_is_mx31txtr() (machine_arch_type == MACH_TYPE_MX31TXTR) -#else -# define machine_is_mx31txtr() (0) -#endif - -#ifdef CONFIG_MACH_U380 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U380 -# endif -# define machine_is_u380() (machine_arch_type == MACH_TYPE_U380) -#else -# define machine_is_u380() (0) -#endif - -#ifdef CONFIG_MACH_HUALU_BOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUALU_BOARD -# endif -# define machine_is_oamp3_hualu() (machine_arch_type == MACH_TYPE_HUALU_BOARD) -#else -# define machine_is_oamp3_hualu() (0) -#endif - -#ifdef CONFIG_MACH_NPCMX50 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NPCMX50 -# endif -# define machine_is_npcmx50() (machine_arch_type == MACH_TYPE_NPCMX50) -#else -# define machine_is_npcmx50() (0) -#endif - -#ifdef CONFIG_MACH_MX51_LANGE51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_LANGE51 -# endif -# define machine_is_mx51_lange51() (machine_arch_type == MACH_TYPE_MX51_LANGE51) -#else -# define machine_is_mx51_lange51() (0) -#endif - -#ifdef CONFIG_MACH_MX51_LANGE52 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_LANGE52 -# endif -# define machine_is_mx51_lange52() (machine_arch_type == MACH_TYPE_MX51_LANGE52) -#else -# define machine_is_mx51_lange52() (0) -#endif - -#ifdef CONFIG_MACH_RIOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIOM -# endif -# define machine_is_riom() (machine_arch_type == MACH_TYPE_RIOM) -#else -# define machine_is_riom() (0) -#endif - -#ifdef CONFIG_MACH_COMCAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMCAS -# endif -# define machine_is_comcas() (machine_arch_type == MACH_TYPE_COMCAS) -#else -# define machine_is_comcas() (0) -#endif - -#ifdef CONFIG_MACH_WSI_MX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WSI_MX27 -# endif -# define machine_is_wsi_mx27() (machine_arch_type == MACH_TYPE_WSI_MX27) -#else -# define machine_is_wsi_mx27() (0) -#endif - -#ifdef CONFIG_MACH_CM_T35 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_T35 -# endif -# define machine_is_cm_t35() (machine_arch_type == MACH_TYPE_CM_T35) -#else -# define machine_is_cm_t35() (0) -#endif - -#ifdef CONFIG_MACH_NET2BIG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET2BIG -# endif -# define machine_is_net2big() (machine_arch_type == MACH_TYPE_NET2BIG) -#else -# define machine_is_net2big() (0) -#endif - -#ifdef CONFIG_MACH_MOTOROLA_A1600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOTOROLA_A1600 -# endif -# define machine_is_motorola_a1600() (machine_arch_type == MACH_TYPE_MOTOROLA_A1600) -#else -# define machine_is_motorola_a1600() (0) -#endif - -#ifdef CONFIG_MACH_IGEP0020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGEP0020 -# endif -# define machine_is_igep0020() (machine_arch_type == MACH_TYPE_IGEP0020) -#else -# define machine_is_igep0020() (0) -#endif - -#ifdef CONFIG_MACH_IGEP0010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGEP0010 -# endif -# define machine_is_igep0010() (machine_arch_type == MACH_TYPE_IGEP0010) -#else -# define machine_is_igep0010() (0) -#endif - -#ifdef CONFIG_MACH_MV6281GTWGE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV6281GTWGE2 -# endif -# define machine_is_mv6281gtwge2() (machine_arch_type == MACH_TYPE_MV6281GTWGE2) -#else -# define machine_is_mv6281gtwge2() (0) -#endif - -#ifdef CONFIG_MACH_SCAT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCAT100 -# endif -# define machine_is_scat100() (machine_arch_type == MACH_TYPE_SCAT100) -#else -# define machine_is_scat100() (0) -#endif - -#ifdef CONFIG_MACH_SANMINA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANMINA -# endif -# define machine_is_sanmina() (machine_arch_type == MACH_TYPE_SANMINA) -#else -# define machine_is_sanmina() (0) -#endif - -#ifdef CONFIG_MACH_MOMENTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOMENTO -# endif -# define machine_is_momento() (machine_arch_type == MACH_TYPE_MOMENTO) -#else -# define machine_is_momento() (0) -#endif - -#ifdef CONFIG_MACH_NUC9XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC9XX -# endif -# define machine_is_nuc9xx() (machine_arch_type == MACH_TYPE_NUC9XX) -#else -# define machine_is_nuc9xx() (0) -#endif - -#ifdef CONFIG_MACH_NUC910EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC910EVB -# endif -# define machine_is_nuc910evb() (machine_arch_type == MACH_TYPE_NUC910EVB) -#else -# define machine_is_nuc910evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC920EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC920EVB -# endif -# define machine_is_nuc920evb() (machine_arch_type == MACH_TYPE_NUC920EVB) -#else -# define machine_is_nuc920evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC950EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC950EVB -# endif -# define machine_is_nuc950evb() (machine_arch_type == MACH_TYPE_NUC950EVB) -#else -# define machine_is_nuc950evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC945EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC945EVB -# endif -# define machine_is_nuc945evb() (machine_arch_type == MACH_TYPE_NUC945EVB) -#else -# define machine_is_nuc945evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC960EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC960EVB -# endif -# define machine_is_nuc960evb() (machine_arch_type == MACH_TYPE_NUC960EVB) -#else -# define machine_is_nuc960evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC932EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC932EVB -# endif -# define machine_is_nuc932evb() (machine_arch_type == MACH_TYPE_NUC932EVB) -#else -# define machine_is_nuc932evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC900 -# endif -# define machine_is_nuc900() (machine_arch_type == MACH_TYPE_NUC900) -#else -# define machine_is_nuc900() (0) -#endif - -#ifdef CONFIG_MACH_SD1SOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SD1SOC -# endif -# define machine_is_sd1soc() (machine_arch_type == MACH_TYPE_SD1SOC) -#else -# define machine_is_sd1soc() (0) -#endif - -#ifdef CONFIG_MACH_LN2440BC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LN2440BC -# endif -# define machine_is_ln2440bc() (machine_arch_type == MACH_TYPE_LN2440BC) -#else -# define machine_is_ln2440bc() (0) -#endif - -#ifdef CONFIG_MACH_RSBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RSBC -# endif -# define machine_is_rsbc() (machine_arch_type == MACH_TYPE_RSBC) -#else -# define machine_is_rsbc() (0) -#endif - -#ifdef CONFIG_MACH_OPENRD_CLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENRD_CLIENT -# endif -# define machine_is_openrd_client() (machine_arch_type == MACH_TYPE_OPENRD_CLIENT) -#else -# define machine_is_openrd_client() (0) -#endif - -#ifdef CONFIG_MACH_HPIPAQ11X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPIPAQ11X -# endif -# define machine_is_hpipaq11x() (machine_arch_type == MACH_TYPE_HPIPAQ11X) -#else -# define machine_is_hpipaq11x() (0) -#endif - -#ifdef CONFIG_MACH_WAYLAND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WAYLAND -# endif -# define machine_is_wayland() (machine_arch_type == MACH_TYPE_WAYLAND) -#else -# define machine_is_wayland() (0) -#endif - -#ifdef CONFIG_MACH_ACNBSX102 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACNBSX102 -# endif -# define machine_is_acnbsx102() (machine_arch_type == MACH_TYPE_ACNBSX102) -#else -# define machine_is_acnbsx102() (0) -#endif - -#ifdef CONFIG_MACH_HWAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HWAT91 -# endif -# define machine_is_hwat91() (machine_arch_type == MACH_TYPE_HWAT91) -#else -# define machine_is_hwat91() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9263CS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9263CS -# endif -# define machine_is_at91sam9263cs() (machine_arch_type == MACH_TYPE_AT91SAM9263CS) -#else -# define machine_is_at91sam9263cs() (0) -#endif - -#ifdef CONFIG_MACH_CSB732 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB732 -# endif -# define machine_is_csb732() (machine_arch_type == MACH_TYPE_CSB732) -#else -# define machine_is_csb732() (0) -#endif - -#ifdef CONFIG_MACH_U8500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U8500 -# endif -# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500) -#else -# define machine_is_u8500() (0) -#endif - -#ifdef CONFIG_MACH_HUQIU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUQIU -# endif -# define machine_is_huqiu() (machine_arch_type == MACH_TYPE_HUQIU) -#else -# define machine_is_huqiu() (0) -#endif - -#ifdef CONFIG_MACH_MX51_KUNLUN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_KUNLUN -# endif -# define machine_is_mx51_kunlun() (machine_arch_type == MACH_TYPE_MX51_KUNLUN) -#else -# define machine_is_mx51_kunlun() (0) -#endif - -#ifdef CONFIG_MACH_PMT1G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PMT1G -# endif -# define machine_is_pmt1g() (machine_arch_type == MACH_TYPE_PMT1G) -#else -# define machine_is_pmt1g() (0) -#endif - -#ifdef CONFIG_MACH_HTCELF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCELF -# endif -# define machine_is_htcelf() (machine_arch_type == MACH_TYPE_HTCELF) -#else -# define machine_is_htcelf() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO420 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO420 -# endif -# define machine_is_armadillo420() (machine_arch_type == MACH_TYPE_ARMADILLO420) -#else -# define machine_is_armadillo420() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO440 -# endif -# define machine_is_armadillo440() (machine_arch_type == MACH_TYPE_ARMADILLO440) -#else -# define machine_is_armadillo440() (0) -#endif - -#ifdef CONFIG_MACH_U_CHIP_DUAL_ARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U_CHIP_DUAL_ARM -# endif -# define machine_is_u_chip_dual_arm() (machine_arch_type == MACH_TYPE_U_CHIP_DUAL_ARM) -#else -# define machine_is_u_chip_dual_arm() (0) -#endif - -#ifdef CONFIG_MACH_CSR_BDB3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSR_BDB3 -# endif -# define machine_is_csr_bdb3() (machine_arch_type == MACH_TYPE_CSR_BDB3) -#else -# define machine_is_csr_bdb3() (0) -#endif - -#ifdef CONFIG_MACH_DOLBY_CAT1018 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOLBY_CAT1018 -# endif -# define machine_is_dolby_cat1018() (machine_arch_type == MACH_TYPE_DOLBY_CAT1018) -#else -# define machine_is_dolby_cat1018() (0) -#endif - -#ifdef CONFIG_MACH_HY9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HY9307 -# endif -# define machine_is_hy9307() (machine_arch_type == MACH_TYPE_HY9307) -#else -# define machine_is_hy9307() (0) -#endif - -#ifdef CONFIG_MACH_A_ES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A_ES -# endif -# define machine_is_aspire_easystore() (machine_arch_type == MACH_TYPE_A_ES) -#else -# define machine_is_aspire_easystore() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_IRIF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_IRIF -# endif -# define machine_is_davinci_irif() (machine_arch_type == MACH_TYPE_DAVINCI_IRIF) -#else -# define machine_is_davinci_irif() (0) -#endif - -#ifdef CONFIG_MACH_AGAMA9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AGAMA9263 -# endif -# define machine_is_agama9263() (machine_arch_type == MACH_TYPE_AGAMA9263) -#else -# define machine_is_agama9263() (0) -#endif - -#ifdef CONFIG_MACH_MARVELL_JASPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVELL_JASPER -# endif -# define machine_is_marvell_jasper() (machine_arch_type == MACH_TYPE_MARVELL_JASPER) -#else -# define machine_is_marvell_jasper() (0) -#endif - -#ifdef CONFIG_MACH_FLINT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLINT -# endif -# define machine_is_flint() (machine_arch_type == MACH_TYPE_FLINT) -#else -# define machine_is_flint() (0) -#endif - -#ifdef CONFIG_MACH_TAVOREVB3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAVOREVB3 -# endif -# define machine_is_tavorevb3() (machine_arch_type == MACH_TYPE_TAVOREVB3) -#else -# define machine_is_tavorevb3() (0) -#endif - -#ifdef CONFIG_MACH_SCH_M490 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCH_M490 -# endif -# define machine_is_sch_m490() (machine_arch_type == MACH_TYPE_SCH_M490) -#else -# define machine_is_sch_m490() (0) -#endif - -#ifdef CONFIG_MACH_RBL01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RBL01 -# endif -# define machine_is_rbl01() (machine_arch_type == MACH_TYPE_RBL01) -#else -# define machine_is_rbl01() (0) -#endif - -#ifdef CONFIG_MACH_OMNIFI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMNIFI -# endif -# define machine_is_omnifi() (machine_arch_type == MACH_TYPE_OMNIFI) -#else -# define machine_is_omnifi() (0) -#endif - -#ifdef CONFIG_MACH_OTAVALO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTAVALO -# endif -# define machine_is_otavalo() (machine_arch_type == MACH_TYPE_OTAVALO) -#else -# define machine_is_otavalo() (0) -#endif - -#ifdef CONFIG_MACH_SIENNA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIENNA -# endif -# define machine_is_siena() (machine_arch_type == MACH_TYPE_SIENNA) -#else -# define machine_is_siena() (0) -#endif - -#ifdef CONFIG_MACH_HTC_EXCALIBUR_S620 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_EXCALIBUR_S620 -# endif -# define machine_is_htc_excalibur_s620() (machine_arch_type == MACH_TYPE_HTC_EXCALIBUR_S620) -#else -# define machine_is_htc_excalibur_s620() (0) -#endif - -#ifdef CONFIG_MACH_HTC_OPAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_OPAL -# endif -# define machine_is_htc_opal() (machine_arch_type == MACH_TYPE_HTC_OPAL) -#else -# define machine_is_htc_opal() (0) -#endif - -#ifdef CONFIG_MACH_TOUCHBOOK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOUCHBOOK -# endif -# define machine_is_touchbook() (machine_arch_type == MACH_TYPE_TOUCHBOOK) -#else -# define machine_is_touchbook() (0) -#endif - -#ifdef CONFIG_MACH_LATTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LATTE -# endif -# define machine_is_latte() (machine_arch_type == MACH_TYPE_LATTE) -#else -# define machine_is_latte() (0) -#endif - -#ifdef CONFIG_MACH_XA200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XA200 -# endif -# define machine_is_xa200() (machine_arch_type == MACH_TYPE_XA200) -#else -# define machine_is_xa200() (0) -#endif - -#ifdef CONFIG_MACH_NIMROD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIMROD -# endif -# define machine_is_nimrod() (machine_arch_type == MACH_TYPE_NIMROD) -#else -# define machine_is_nimrod() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9215_3G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9215_3G -# endif -# define machine_is_cc9p9215_3g() (machine_arch_type == MACH_TYPE_CC9P9215_3G) -#else -# define machine_is_cc9p9215_3g() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9215_3GJS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9215_3GJS -# endif -# define machine_is_cc9p9215_3gjs() (machine_arch_type == MACH_TYPE_CC9P9215_3GJS) -#else -# define machine_is_cc9p9215_3gjs() (0) -#endif - -#ifdef CONFIG_MACH_TK71 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TK71 -# endif -# define machine_is_tk71() (machine_arch_type == MACH_TYPE_TK71) -#else -# define machine_is_tk71() (0) -#endif - -#ifdef CONFIG_MACH_COMHAM3525 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COMHAM3525 -# endif -# define machine_is_comham3525() (machine_arch_type == MACH_TYPE_COMHAM3525) -#else -# define machine_is_comham3525() (0) -#endif - -#ifdef CONFIG_MACH_MX31EREBUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31EREBUS -# endif -# define machine_is_mx31erebus() (machine_arch_type == MACH_TYPE_MX31EREBUS) -#else -# define machine_is_mx31erebus() (0) -#endif - -#ifdef CONFIG_MACH_MCARDMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCARDMX27 -# endif -# define machine_is_mcardmx27() (machine_arch_type == MACH_TYPE_MCARDMX27) -#else -# define machine_is_mcardmx27() (0) -#endif - -#ifdef CONFIG_MACH_PARADISE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PARADISE -# endif -# define machine_is_paradise() (machine_arch_type == MACH_TYPE_PARADISE) -#else -# define machine_is_paradise() (0) -#endif - -#ifdef CONFIG_MACH_TIDE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIDE -# endif -# define machine_is_tide() (machine_arch_type == MACH_TYPE_TIDE) -#else -# define machine_is_tide() (0) -#endif - -#ifdef CONFIG_MACH_WZL2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WZL2440 -# endif -# define machine_is_wzl2440() (machine_arch_type == MACH_TYPE_WZL2440) -#else -# define machine_is_wzl2440() (0) -#endif - -#ifdef CONFIG_MACH_SDRDEMO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SDRDEMO -# endif -# define machine_is_sdrdemo() (machine_arch_type == MACH_TYPE_SDRDEMO) -#else -# define machine_is_sdrdemo() (0) -#endif - -#ifdef CONFIG_MACH_ETHERCAN2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETHERCAN2 -# endif -# define machine_is_ethercan2() (machine_arch_type == MACH_TYPE_ETHERCAN2) -#else -# define machine_is_ethercan2() (0) -#endif - -#ifdef CONFIG_MACH_ECMIMG20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECMIMG20 -# endif -# define machine_is_ecmimg20() (machine_arch_type == MACH_TYPE_ECMIMG20) -#else -# define machine_is_ecmimg20() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_DRAGON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_DRAGON -# endif -# define machine_is_omap_dragon() (machine_arch_type == MACH_TYPE_OMAP_DRAGON) -#else -# define machine_is_omap_dragon() (0) -#endif - -#ifdef CONFIG_MACH_HALO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HALO -# endif -# define machine_is_halo() (machine_arch_type == MACH_TYPE_HALO) -#else -# define machine_is_halo() (0) -#endif - -#ifdef CONFIG_MACH_HUANGSHAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUANGSHAN -# endif -# define machine_is_huangshan() (machine_arch_type == MACH_TYPE_HUANGSHAN) -#else -# define machine_is_huangshan() (0) -#endif - -#ifdef CONFIG_MACH_VL_MA2SC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VL_MA2SC -# endif -# define machine_is_vl_ma2sc() (machine_arch_type == MACH_TYPE_VL_MA2SC) -#else -# define machine_is_vl_ma2sc() (0) -#endif - -#ifdef CONFIG_MACH_RAUMFELD_RC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAUMFELD_RC -# endif -# define machine_is_raumfeld_rc() (machine_arch_type == MACH_TYPE_RAUMFELD_RC) -#else -# define machine_is_raumfeld_rc() (0) -#endif - -#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAUMFELD_CONNECTOR -# endif -# define machine_is_raumfeld_connector() (machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR) -#else -# define machine_is_raumfeld_connector() (0) -#endif - -#ifdef CONFIG_MACH_RAUMFELD_SPEAKER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAUMFELD_SPEAKER -# endif -# define machine_is_raumfeld_speaker() (machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER) -#else -# define machine_is_raumfeld_speaker() (0) -#endif - -#ifdef CONFIG_MACH_MULTIBUS_MASTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTIBUS_MASTER -# endif -# define machine_is_multibus_master() (machine_arch_type == MACH_TYPE_MULTIBUS_MASTER) -#else -# define machine_is_multibus_master() (0) -#endif - -#ifdef CONFIG_MACH_MULTIBUS_PBK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTIBUS_PBK -# endif -# define machine_is_multibus_pbk() (machine_arch_type == MACH_TYPE_MULTIBUS_PBK) -#else -# define machine_is_multibus_pbk() (0) -#endif - -#ifdef CONFIG_MACH_TNETV107X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNETV107X -# endif -# define machine_is_tnetv107x() (machine_arch_type == MACH_TYPE_TNETV107X) -#else -# define machine_is_tnetv107x() (0) -#endif - -#ifdef CONFIG_MACH_SNAKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAKE -# endif -# define machine_is_snake() (machine_arch_type == MACH_TYPE_SNAKE) -#else -# define machine_is_snake() (0) -#endif - -#ifdef CONFIG_MACH_CWMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWMX27 -# endif -# define machine_is_cwmx27() (machine_arch_type == MACH_TYPE_CWMX27) -#else -# define machine_is_cwmx27() (0) -#endif - -#ifdef CONFIG_MACH_SCH_M480 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCH_M480 -# endif -# define machine_is_sch_m480() (machine_arch_type == MACH_TYPE_SCH_M480) -#else -# define machine_is_sch_m480() (0) -#endif - -#ifdef CONFIG_MACH_PLATYPUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLATYPUS -# endif -# define machine_is_platypus() (machine_arch_type == MACH_TYPE_PLATYPUS) -#else -# define machine_is_platypus() (0) -#endif - -#ifdef CONFIG_MACH_PSS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PSS2 -# endif -# define machine_is_pss2() (machine_arch_type == MACH_TYPE_PSS2) -#else -# define machine_is_pss2() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_APM150 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_APM150 -# endif -# define machine_is_davinci_apm150() (machine_arch_type == MACH_TYPE_DAVINCI_APM150) -#else -# define machine_is_davinci_apm150() (0) -#endif - -#ifdef CONFIG_MACH_STR9100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STR9100 -# endif -# define machine_is_str9100() (machine_arch_type == MACH_TYPE_STR9100) -#else -# define machine_is_str9100() (0) -#endif - -#ifdef CONFIG_MACH_NET5BIG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET5BIG -# endif -# define machine_is_net5big() (machine_arch_type == MACH_TYPE_NET5BIG) -#else -# define machine_is_net5big() (0) -#endif - -#ifdef CONFIG_MACH_SEABED9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SEABED9263 -# endif -# define machine_is_seabed9263() (machine_arch_type == MACH_TYPE_SEABED9263) -#else -# define machine_is_seabed9263() (0) -#endif - -#ifdef CONFIG_MACH_MX51_M2ID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_M2ID -# endif -# define machine_is_mx51_m2id() (machine_arch_type == MACH_TYPE_MX51_M2ID) -#else -# define machine_is_mx51_m2id() (0) -#endif - -#ifdef CONFIG_MACH_OCTVOCPLUS_EB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCTVOCPLUS_EB -# endif -# define machine_is_octvocplus_eb() (machine_arch_type == MACH_TYPE_OCTVOCPLUS_EB) -#else -# define machine_is_octvocplus_eb() (0) -#endif - -#ifdef CONFIG_MACH_KLK_FIREFOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KLK_FIREFOX -# endif -# define machine_is_klk_firefox() (machine_arch_type == MACH_TYPE_KLK_FIREFOX) -#else -# define machine_is_klk_firefox() (0) -#endif - -#ifdef CONFIG_MACH_KLK_WIRMA_MODULE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KLK_WIRMA_MODULE -# endif -# define machine_is_klk_wirma_module() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MODULE) -#else -# define machine_is_klk_wirma_module() (0) -#endif - -#ifdef CONFIG_MACH_KLK_WIRMA_MMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KLK_WIRMA_MMI -# endif -# define machine_is_klk_wirma_mmi() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MMI) -#else -# define machine_is_klk_wirma_mmi() (0) -#endif - -#ifdef CONFIG_MACH_SUPERSONIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUPERSONIC -# endif -# define machine_is_supersonic() (machine_arch_type == MACH_TYPE_SUPERSONIC) -#else -# define machine_is_supersonic() (0) -#endif - -#ifdef CONFIG_MACH_LIBERTY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIBERTY -# endif -# define machine_is_liberty() (machine_arch_type == MACH_TYPE_LIBERTY) -#else -# define machine_is_liberty() (0) -#endif - -#ifdef CONFIG_MACH_MH355 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MH355 -# endif -# define machine_is_mh355() (machine_arch_type == MACH_TYPE_MH355) -#else -# define machine_is_mh355() (0) -#endif - -#ifdef CONFIG_MACH_PC7802 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC7802 -# endif -# define machine_is_pc7802() (machine_arch_type == MACH_TYPE_PC7802) -#else -# define machine_is_pc7802() (0) -#endif - -#ifdef CONFIG_MACH_GNET_SGC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_SGC -# endif -# define machine_is_gnet_sgc() (machine_arch_type == MACH_TYPE_GNET_SGC) -#else -# define machine_is_gnet_sgc() (0) -#endif - -#ifdef CONFIG_MACH_EINSTEIN15 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EINSTEIN15 -# endif -# define machine_is_einstein15() (machine_arch_type == MACH_TYPE_EINSTEIN15) -#else -# define machine_is_einstein15() (0) -#endif - -#ifdef CONFIG_MACH_CMPD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMPD -# endif -# define machine_is_cmpd() (machine_arch_type == MACH_TYPE_CMPD) -#else -# define machine_is_cmpd() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_HASE1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_HASE1 -# endif -# define machine_is_davinci_hase1() (machine_arch_type == MACH_TYPE_DAVINCI_HASE1) -#else -# define machine_is_davinci_hase1() (0) -#endif - -#ifdef CONFIG_MACH_LGEINCITEPHONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LGEINCITEPHONE -# endif -# define machine_is_lgeincitephone() (machine_arch_type == MACH_TYPE_LGEINCITEPHONE) -#else -# define machine_is_lgeincitephone() (0) -#endif - -#ifdef CONFIG_MACH_EA313X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EA313X -# endif -# define machine_is_ea313x() (machine_arch_type == MACH_TYPE_EA313X) -#else -# define machine_is_ea313x() (0) -#endif - -#ifdef CONFIG_MACH_FWBD_39064 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FWBD_39064 -# endif -# define machine_is_fwbd_39064() (machine_arch_type == MACH_TYPE_FWBD_39064) -#else -# define machine_is_fwbd_39064() (0) -#endif - -#ifdef CONFIG_MACH_FWBD_390128 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FWBD_390128 -# endif -# define machine_is_fwbd_390128() (machine_arch_type == MACH_TYPE_FWBD_390128) -#else -# define machine_is_fwbd_390128() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_MOE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_MOE -# endif -# define machine_is_pelco_moe() (machine_arch_type == MACH_TYPE_PELCO_MOE) -#else -# define machine_is_pelco_moe() (0) -#endif - -#ifdef CONFIG_MACH_MINIMIX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINIMIX27 -# endif -# define machine_is_minimix27() (machine_arch_type == MACH_TYPE_MINIMIX27) -#else -# define machine_is_minimix27() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_THUNDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_THUNDER -# endif -# define machine_is_omap3_thunder() (machine_arch_type == MACH_TYPE_OMAP3_THUNDER) -#else -# define machine_is_omap3_thunder() (0) -#endif - -#ifdef CONFIG_MACH_PASSIONC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PASSIONC -# endif -# define machine_is_passionc() (machine_arch_type == MACH_TYPE_PASSIONC) -#else -# define machine_is_passionc() (0) -#endif - -#ifdef CONFIG_MACH_MX27AMATA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27AMATA -# endif -# define machine_is_mx27amata() (machine_arch_type == MACH_TYPE_MX27AMATA) -#else -# define machine_is_mx27amata() (0) -#endif - -#ifdef CONFIG_MACH_BGAT1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BGAT1 -# endif -# define machine_is_bgat1() (machine_arch_type == MACH_TYPE_BGAT1) -#else -# define machine_is_bgat1() (0) -#endif - -#ifdef CONFIG_MACH_BUZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUZZ -# endif -# define machine_is_buzz() (machine_arch_type == MACH_TYPE_BUZZ) -#else -# define machine_is_buzz() (0) -#endif - -#ifdef CONFIG_MACH_MB9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB9G20 -# endif -# define machine_is_mb9g20() (machine_arch_type == MACH_TYPE_MB9G20) -#else -# define machine_is_mb9g20() (0) -#endif - -#ifdef CONFIG_MACH_YUSHAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YUSHAN -# endif -# define machine_is_yushan() (machine_arch_type == MACH_TYPE_YUSHAN) -#else -# define machine_is_yushan() (0) -#endif - -#ifdef CONFIG_MACH_LIZARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIZARD -# endif -# define machine_is_lizard() (machine_arch_type == MACH_TYPE_LIZARD) -#else -# define machine_is_lizard() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3POLYCOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3POLYCOM -# endif -# define machine_is_omap3polycom() (machine_arch_type == MACH_TYPE_OMAP3POLYCOM) -#else -# define machine_is_omap3polycom() (0) -#endif - -#ifdef CONFIG_MACH_SMDKV210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKV210 -# endif -# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210) -#else -# define machine_is_smdkv210() (0) -#endif - -#ifdef CONFIG_MACH_BRAVO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRAVO -# endif -# define machine_is_bravo() (machine_arch_type == MACH_TYPE_BRAVO) -#else -# define machine_is_bravo() (0) -#endif - -#ifdef CONFIG_MACH_SIOGENTOO1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIOGENTOO1 -# endif -# define machine_is_siogentoo1() (machine_arch_type == MACH_TYPE_SIOGENTOO1) -#else -# define machine_is_siogentoo1() (0) -#endif - -#ifdef CONFIG_MACH_SIOGENTOO2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIOGENTOO2 -# endif -# define machine_is_siogentoo2() (machine_arch_type == MACH_TYPE_SIOGENTOO2) -#else -# define machine_is_siogentoo2() (0) -#endif - -#ifdef CONFIG_MACH_SM3K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SM3K -# endif -# define machine_is_sm3k() (machine_arch_type == MACH_TYPE_SM3K) -#else -# define machine_is_sm3k() (0) -#endif - -#ifdef CONFIG_MACH_ACER_TEMPO_F900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_TEMPO_F900 -# endif -# define machine_is_acer_tempo_f900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_F900) -#else -# define machine_is_acer_tempo_f900() (0) -#endif - -#ifdef CONFIG_MACH_SST61VC010_DEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SST61VC010_DEV -# endif -# define machine_is_sst61vc010_dev() (machine_arch_type == MACH_TYPE_SST61VC010_DEV) -#else -# define machine_is_sst61vc010_dev() (0) -#endif - -#ifdef CONFIG_MACH_GLITTERTIND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GLITTERTIND -# endif -# define machine_is_glittertind() (machine_arch_type == MACH_TYPE_GLITTERTIND) -#else -# define machine_is_glittertind() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_ZOOM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_ZOOM3 -# endif -# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3) -#else -# define machine_is_omap_zoom3() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_3630SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_3630SDP -# endif -# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP) -#else -# define machine_is_omap_3630sdp() (0) -#endif - -#ifdef CONFIG_MACH_CYBOOK2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBOOK2440 -# endif -# define machine_is_cybook2440() (machine_arch_type == MACH_TYPE_CYBOOK2440) -#else -# define machine_is_cybook2440() (0) -#endif - -#ifdef CONFIG_MACH_TORINO_S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TORINO_S -# endif -# define machine_is_torino_s() (machine_arch_type == MACH_TYPE_TORINO_S) -#else -# define machine_is_torino_s() (0) -#endif - -#ifdef CONFIG_MACH_HAVANA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HAVANA -# endif -# define machine_is_havana() (machine_arch_type == MACH_TYPE_HAVANA) -#else -# define machine_is_havana() (0) -#endif - -#ifdef CONFIG_MACH_BEAUMONT_11 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BEAUMONT_11 -# endif -# define machine_is_beaumont_11() (machine_arch_type == MACH_TYPE_BEAUMONT_11) -#else -# define machine_is_beaumont_11() (0) -#endif - -#ifdef CONFIG_MACH_VANGUARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VANGUARD -# endif -# define machine_is_vanguard() (machine_arch_type == MACH_TYPE_VANGUARD) -#else -# define machine_is_vanguard() (0) -#endif - -#ifdef CONFIG_MACH_S5PC110_DRACO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5PC110_DRACO -# endif -# define machine_is_s5pc110_draco() (machine_arch_type == MACH_TYPE_S5PC110_DRACO) -#else -# define machine_is_s5pc110_draco() (0) -#endif - -#ifdef CONFIG_MACH_CARTESIO_TWO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARTESIO_TWO -# endif -# define machine_is_cartesio_two() (machine_arch_type == MACH_TYPE_CARTESIO_TWO) -#else -# define machine_is_cartesio_two() (0) -#endif - -#ifdef CONFIG_MACH_ASTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASTER -# endif -# define machine_is_aster() (machine_arch_type == MACH_TYPE_ASTER) -#else -# define machine_is_aster() (0) -#endif - -#ifdef CONFIG_MACH_VOGUESV210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOGUESV210 -# endif -# define machine_is_voguesv210() (machine_arch_type == MACH_TYPE_VOGUESV210) -#else -# define machine_is_voguesv210() (0) -#endif - -#ifdef CONFIG_MACH_ACM500X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACM500X -# endif -# define machine_is_acm500x() (machine_arch_type == MACH_TYPE_ACM500X) -#else -# define machine_is_acm500x() (0) -#endif - -#ifdef CONFIG_MACH_KM9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KM9260 -# endif -# define machine_is_km9260() (machine_arch_type == MACH_TYPE_KM9260) -#else -# define machine_is_km9260() (0) -#endif - -#ifdef CONFIG_MACH_NIDEFLEXG1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NIDEFLEXG1 -# endif -# define machine_is_nideflexg1() (machine_arch_type == MACH_TYPE_NIDEFLEXG1) -#else -# define machine_is_nideflexg1() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_PLUG_IO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_PLUG_IO -# endif -# define machine_is_ctera_plug_io() (machine_arch_type == MACH_TYPE_CTERA_PLUG_IO) -#else -# define machine_is_ctera_plug_io() (0) -#endif - -#ifdef CONFIG_MACH_SMARTQ7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTQ7 -# endif -# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7) -#else -# define machine_is_smartq7() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G10EK2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G10EK2 -# endif -# define machine_is_at91sam9g10ek2() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK2) -#else -# define machine_is_at91sam9g10ek2() (0) -#endif - -#ifdef CONFIG_MACH_ASUSP527 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASUSP527 -# endif -# define machine_is_asusp527() (machine_arch_type == MACH_TYPE_ASUSP527) -#else -# define machine_is_asusp527() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20MPM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20MPM2 -# endif -# define machine_is_at91sam9g20mpm2() (machine_arch_type == MACH_TYPE_AT91SAM9G20MPM2) -#else -# define machine_is_at91sam9g20mpm2() (0) -#endif - -#ifdef CONFIG_MACH_TOPASA900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOPASA900 -# endif -# define machine_is_topasa900() (machine_arch_type == MACH_TYPE_TOPASA900) -#else -# define machine_is_topasa900() (0) -#endif - -#ifdef CONFIG_MACH_ELECTRUM_100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELECTRUM_100 -# endif -# define machine_is_electrum_100() (machine_arch_type == MACH_TYPE_ELECTRUM_100) -#else -# define machine_is_electrum_100() (0) -#endif - -#ifdef CONFIG_MACH_MX51GRB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51GRB -# endif -# define machine_is_mx51grb() (machine_arch_type == MACH_TYPE_MX51GRB) -#else -# define machine_is_mx51grb() (0) -#endif - -#ifdef CONFIG_MACH_XEA300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XEA300 -# endif -# define machine_is_xea300() (machine_arch_type == MACH_TYPE_XEA300) -#else -# define machine_is_xea300() (0) -#endif - -#ifdef CONFIG_MACH_HTCSTARTREK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCSTARTREK -# endif -# define machine_is_htcstartrek() (machine_arch_type == MACH_TYPE_HTCSTARTREK) -#else -# define machine_is_htcstartrek() (0) -#endif - -#ifdef CONFIG_MACH_LIMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIMA -# endif -# define machine_is_lima() (machine_arch_type == MACH_TYPE_LIMA) -#else -# define machine_is_lima() (0) -#endif - -#ifdef CONFIG_MACH_CSB740 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB740 -# endif -# define machine_is_csb740() (machine_arch_type == MACH_TYPE_CSB740) -#else -# define machine_is_csb740() (0) -#endif - -#ifdef CONFIG_MACH_USB_S8815 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_S8815 -# endif -# define machine_is_usb_s8815() (machine_arch_type == MACH_TYPE_USB_S8815) -#else -# define machine_is_usb_s8815() (0) -#endif - -#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN -# endif -# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN) -#else -# define machine_is_watson_efm_plugin() (0) -#endif - -#ifdef CONFIG_MACH_MILKYWAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MILKYWAY -# endif -# define machine_is_milkyway() (machine_arch_type == MACH_TYPE_MILKYWAY) -#else -# define machine_is_milkyway() (0) -#endif - -#ifdef CONFIG_MACH_G4EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G4EVM -# endif -# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM) -#else -# define machine_is_g4evm() (0) -#endif - -#ifdef CONFIG_MACH_PICOMOD6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOMOD6 -# endif -# define machine_is_picomod6() (machine_arch_type == MACH_TYPE_PICOMOD6) -#else -# define machine_is_picomod6() (0) -#endif - -#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD -# endif -# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD) -#else -# define machine_is_omapl138_hawkboard() (0) -#endif - -#ifdef CONFIG_MACH_IP6000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IP6000 -# endif -# define machine_is_ip6000() (machine_arch_type == MACH_TYPE_IP6000) -#else -# define machine_is_ip6000() (0) -#endif - -#ifdef CONFIG_MACH_IP6010 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IP6010 -# endif -# define machine_is_ip6010() (machine_arch_type == MACH_TYPE_IP6010) -#else -# define machine_is_ip6010() (0) -#endif - -#ifdef CONFIG_MACH_UTM400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UTM400 -# endif -# define machine_is_utm400() (machine_arch_type == MACH_TYPE_UTM400) -#else -# define machine_is_utm400() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_ZYBEX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_ZYBEX -# endif -# define machine_is_omap3_zybex() (machine_arch_type == MACH_TYPE_OMAP3_ZYBEX) -#else -# define machine_is_omap3_zybex() (0) -#endif - -#ifdef CONFIG_MACH_WIRELESS_SPACE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WIRELESS_SPACE -# endif -# define machine_is_wireless_space() (machine_arch_type == MACH_TYPE_WIRELESS_SPACE) -#else -# define machine_is_wireless_space() (0) -#endif - -#ifdef CONFIG_MACH_SX560 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SX560 -# endif -# define machine_is_sx560() (machine_arch_type == MACH_TYPE_SX560) -#else -# define machine_is_sx560() (0) -#endif - -#ifdef CONFIG_MACH_TS41X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS41X -# endif -# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X) -#else -# define machine_is_ts41x() (0) -#endif - -#ifdef CONFIG_MACH_ELPHEL10373 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELPHEL10373 -# endif -# define machine_is_elphel10373() (machine_arch_type == MACH_TYPE_ELPHEL10373) -#else -# define machine_is_elphel10373() (0) -#endif - -#ifdef CONFIG_MACH_RHOBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RHOBOT -# endif -# define machine_is_rhobot() (machine_arch_type == MACH_TYPE_RHOBOT) -#else -# define machine_is_rhobot() (0) -#endif - -#ifdef CONFIG_MACH_MX51_REFRESH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_REFRESH -# endif -# define machine_is_mx51_refresh() (machine_arch_type == MACH_TYPE_MX51_REFRESH) -#else -# define machine_is_mx51_refresh() (0) -#endif - -#ifdef CONFIG_MACH_LS9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LS9260 -# endif -# define machine_is_ls9260() (machine_arch_type == MACH_TYPE_LS9260) -#else -# define machine_is_ls9260() (0) -#endif - -#ifdef CONFIG_MACH_SHANK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHANK -# endif -# define machine_is_shank() (machine_arch_type == MACH_TYPE_SHANK) -#else -# define machine_is_shank() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50_ST1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50_ST1 -# endif -# define machine_is_qsd8x50_st1() (machine_arch_type == MACH_TYPE_QSD8X50_ST1) -#else -# define machine_is_qsd8x50_st1() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9M10EKES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9M10EKES -# endif -# define machine_is_at91sam9m10ekes() (machine_arch_type == MACH_TYPE_AT91SAM9M10EKES) -#else -# define machine_is_at91sam9m10ekes() (0) -#endif - -#ifdef CONFIG_MACH_HIRAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIRAM -# endif -# define machine_is_hiram() (machine_arch_type == MACH_TYPE_HIRAM) -#else -# define machine_is_hiram() (0) -#endif - -#ifdef CONFIG_MACH_PHY3250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHY3250 -# endif -# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250) -#else -# define machine_is_phy3250() (0) -#endif - -#ifdef CONFIG_MACH_EA3250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EA3250 -# endif -# define machine_is_ea3250() (machine_arch_type == MACH_TYPE_EA3250) -#else -# define machine_is_ea3250() (0) -#endif - -#ifdef CONFIG_MACH_FDI3250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FDI3250 -# endif -# define machine_is_fdi3250() (machine_arch_type == MACH_TYPE_FDI3250) -#else -# define machine_is_fdi3250() (0) -#endif - -#ifdef CONFIG_MACH_WHITESTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WHITESTONE -# endif -# define machine_is_whitestone() (machine_arch_type == MACH_TYPE_WHITESTONE) -#else -# define machine_is_whitestone() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9263NIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9263NIT -# endif -# define machine_is_at91sam9263nit() (machine_arch_type == MACH_TYPE_AT91SAM9263NIT) -#else -# define machine_is_at91sam9263nit() (0) -#endif - -#ifdef CONFIG_MACH_CCMX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCMX51 -# endif -# define machine_is_ccmx51() (machine_arch_type == MACH_TYPE_CCMX51) -#else -# define machine_is_ccmx51() (0) -#endif - -#ifdef CONFIG_MACH_CCMX51JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCMX51JS -# endif -# define machine_is_ccmx51js() (machine_arch_type == MACH_TYPE_CCMX51JS) -#else -# define machine_is_ccmx51js() (0) -#endif - -#ifdef CONFIG_MACH_CCWMX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCWMX51 -# endif -# define machine_is_ccwmx51() (machine_arch_type == MACH_TYPE_CCWMX51) -#else -# define machine_is_ccwmx51() (0) -#endif - -#ifdef CONFIG_MACH_CCWMX51JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCWMX51JS -# endif -# define machine_is_ccwmx51js() (machine_arch_type == MACH_TYPE_CCWMX51JS) -#else -# define machine_is_ccwmx51js() (0) -#endif - -#ifdef CONFIG_MACH_MINI6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI6410 -# endif -# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410) -#else -# define machine_is_mini6410() (0) -#endif - -#ifdef CONFIG_MACH_TINY6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TINY6410 -# endif -# define machine_is_tiny6410() (machine_arch_type == MACH_TYPE_TINY6410) -#else -# define machine_is_tiny6410() (0) -#endif - -#ifdef CONFIG_MACH_NANO6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NANO6410 -# endif -# define machine_is_nano6410() (machine_arch_type == MACH_TYPE_NANO6410) -#else -# define machine_is_nano6410() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940HFNLDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940HFNLDB -# endif -# define machine_is_at572d940hfnldb() (machine_arch_type == MACH_TYPE_AT572D940HFNLDB) -#else -# define machine_is_at572d940hfnldb() (0) -#endif - -#ifdef CONFIG_MACH_HTCLEO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCLEO -# endif -# define machine_is_htcleo() (machine_arch_type == MACH_TYPE_HTCLEO) -#else -# define machine_is_htcleo() (0) -#endif - -#ifdef CONFIG_MACH_AVP13 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVP13 -# endif -# define machine_is_avp13() (machine_arch_type == MACH_TYPE_AVP13) -#else -# define machine_is_avp13() (0) -#endif - -#ifdef CONFIG_MACH_XXSVIDEOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XXSVIDEOD -# endif -# define machine_is_xxsvideod() (machine_arch_type == MACH_TYPE_XXSVIDEOD) -#else -# define machine_is_xxsvideod() (0) -#endif - -#ifdef CONFIG_MACH_VPNEXT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VPNEXT -# endif -# define machine_is_vpnext() (machine_arch_type == MACH_TYPE_VPNEXT) -#else -# define machine_is_vpnext() (0) -#endif - -#ifdef CONFIG_MACH_SWARCO_ITC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCO_ITC3 -# endif -# define machine_is_swarco_itc3() (machine_arch_type == MACH_TYPE_SWARCO_ITC3) -#else -# define machine_is_swarco_itc3() (0) -#endif - -#ifdef CONFIG_MACH_TX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX51 -# endif -# define machine_is_tx51() (machine_arch_type == MACH_TYPE_TX51) -#else -# define machine_is_tx51() (0) -#endif - -#ifdef CONFIG_MACH_DOLBY_CAT1021 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOLBY_CAT1021 -# endif -# define machine_is_dolby_cat1021() (machine_arch_type == MACH_TYPE_DOLBY_CAT1021) -#else -# define machine_is_dolby_cat1021() (0) -#endif - -#ifdef CONFIG_MACH_MX28EVK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX28EVK -# endif -# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK) -#else -# define machine_is_mx28evk() (0) -#endif - -#ifdef CONFIG_MACH_PHOENIX260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHOENIX260 -# endif -# define machine_is_phoenix260() (machine_arch_type == MACH_TYPE_PHOENIX260) -#else -# define machine_is_phoenix260() (0) -#endif - -#ifdef CONFIG_MACH_UVACA_STORK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UVACA_STORK -# endif -# define machine_is_uvaca_stork() (machine_arch_type == MACH_TYPE_UVACA_STORK) -#else -# define machine_is_uvaca_stork() (0) -#endif - -#ifdef CONFIG_MACH_SMARTQ5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTQ5 -# endif -# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5) -#else -# define machine_is_smartq5() (0) -#endif - -#ifdef CONFIG_MACH_ALL3078 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ALL3078 -# endif -# define machine_is_all3078() (machine_arch_type == MACH_TYPE_ALL3078) -#else -# define machine_is_all3078() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_2BAY_DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_2BAY_DS -# endif -# define machine_is_ctera_2bay_ds() (machine_arch_type == MACH_TYPE_CTERA_2BAY_DS) -#else -# define machine_is_ctera_2bay_ds() (0) -#endif - -#ifdef CONFIG_MACH_SIOGENTOO3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIOGENTOO3 -# endif -# define machine_is_siogentoo3() (machine_arch_type == MACH_TYPE_SIOGENTOO3) -#else -# define machine_is_siogentoo3() (0) -#endif - -#ifdef CONFIG_MACH_EPB5000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPB5000 -# endif -# define machine_is_epb5000() (machine_arch_type == MACH_TYPE_EPB5000) -#else -# define machine_is_epb5000() (0) -#endif - -#ifdef CONFIG_MACH_HY9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HY9263 -# endif -# define machine_is_hy9263() (machine_arch_type == MACH_TYPE_HY9263) -#else -# define machine_is_hy9263() (0) -#endif - -#ifdef CONFIG_MACH_ACER_TEMPO_M900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_TEMPO_M900 -# endif -# define machine_is_acer_tempo_m900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_M900) -#else -# define machine_is_acer_tempo_m900() (0) -#endif - -#ifdef CONFIG_MACH_ACER_TEMPO_DX900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_TEMPO_DX900 -# endif -# define machine_is_acer_tempo_dx650() (machine_arch_type == MACH_TYPE_ACER_TEMPO_DX900) -#else -# define machine_is_acer_tempo_dx650() (0) -#endif - -#ifdef CONFIG_MACH_ACER_TEMPO_X960 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_TEMPO_X960 -# endif -# define machine_is_acer_tempo_x960() (machine_arch_type == MACH_TYPE_ACER_TEMPO_X960) -#else -# define machine_is_acer_tempo_x960() (0) -#endif - -#ifdef CONFIG_MACH_ACER_ETEN_V900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_ETEN_V900 -# endif -# define machine_is_acer_eten_v900() (machine_arch_type == MACH_TYPE_ACER_ETEN_V900) -#else -# define machine_is_acer_eten_v900() (0) -#endif - -#ifdef CONFIG_MACH_ACER_ETEN_X900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_ETEN_X900 -# endif -# define machine_is_acer_eten_x900() (machine_arch_type == MACH_TYPE_ACER_ETEN_X900) -#else -# define machine_is_acer_eten_x900() (0) -#endif - -#ifdef CONFIG_MACH_BONNELL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BONNELL -# endif -# define machine_is_bonnell() (machine_arch_type == MACH_TYPE_BONNELL) -#else -# define machine_is_bonnell() (0) -#endif - -#ifdef CONFIG_MACH_OHT_MX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OHT_MX27 -# endif -# define machine_is_oht_mx27() (machine_arch_type == MACH_TYPE_OHT_MX27) -#else -# define machine_is_oht_mx27() (0) -#endif - -#ifdef CONFIG_MACH_HTCQUARTZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCQUARTZ -# endif -# define machine_is_htcquartz() (machine_arch_type == MACH_TYPE_HTCQUARTZ) -#else -# define machine_is_htcquartz() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM -# endif -# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM) -#else -# define machine_is_davinci_dm6467tevm() (0) -#endif - -#ifdef CONFIG_MACH_C3AX03 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C3AX03 -# endif -# define machine_is_c3ax03() (machine_arch_type == MACH_TYPE_C3AX03) -#else -# define machine_is_c3ax03() (0) -#endif - -#ifdef CONFIG_MACH_MXT_TD60 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXT_TD60 -# endif -# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60) -#else -# define machine_is_mxt_td60() (0) -#endif - -#ifdef CONFIG_MACH_ESYX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESYX -# endif -# define machine_is_esyx() (machine_arch_type == MACH_TYPE_ESYX) -#else -# define machine_is_esyx() (0) -#endif - -#ifdef CONFIG_MACH_DOVE_DB2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOVE_DB2 -# endif -# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB2) -#else -# define machine_is_dove_db2() (0) -#endif - -#ifdef CONFIG_MACH_BULLDOG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BULLDOG -# endif -# define machine_is_bulldog() (machine_arch_type == MACH_TYPE_BULLDOG) -#else -# define machine_is_bulldog() (0) -#endif - -#ifdef CONFIG_MACH_DERELL_ME2000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DERELL_ME2000 -# endif -# define machine_is_derell_me2000() (machine_arch_type == MACH_TYPE_DERELL_ME2000) -#else -# define machine_is_derell_me2000() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_BASE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_BASE -# endif -# define machine_is_bcmring_base() (machine_arch_type == MACH_TYPE_BCMRING_BASE) -#else -# define machine_is_bcmring_base() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_EVM -# endif -# define machine_is_bcmring_evm() (machine_arch_type == MACH_TYPE_BCMRING_EVM) -#else -# define machine_is_bcmring_evm() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_EVM_JAZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_EVM_JAZZ -# endif -# define machine_is_bcmring_evm_jazz() (machine_arch_type == MACH_TYPE_BCMRING_EVM_JAZZ) -#else -# define machine_is_bcmring_evm_jazz() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_SP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_SP -# endif -# define machine_is_bcmring_sp() (machine_arch_type == MACH_TYPE_BCMRING_SP) -#else -# define machine_is_bcmring_sp() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_SV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_SV -# endif -# define machine_is_bcmring_sv() (machine_arch_type == MACH_TYPE_BCMRING_SV) -#else -# define machine_is_bcmring_sv() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_SV_JAZZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_SV_JAZZ -# endif -# define machine_is_bcmring_sv_jazz() (machine_arch_type == MACH_TYPE_BCMRING_SV_JAZZ) -#else -# define machine_is_bcmring_sv_jazz() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_TABLET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_TABLET -# endif -# define machine_is_bcmring_tablet() (machine_arch_type == MACH_TYPE_BCMRING_TABLET) -#else -# define machine_is_bcmring_tablet() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_VP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_VP -# endif -# define machine_is_bcmring_vp() (machine_arch_type == MACH_TYPE_BCMRING_VP) -#else -# define machine_is_bcmring_vp() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_EVM_SEIKOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_EVM_SEIKOR -# endif -# define machine_is_bcmring_evm_seikor() (machine_arch_type == MACH_TYPE_BCMRING_EVM_SEIKOR) -#else -# define machine_is_bcmring_evm_seikor() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_SP_WQVGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_SP_WQVGA -# endif -# define machine_is_bcmring_sp_wqvga() (machine_arch_type == MACH_TYPE_BCMRING_SP_WQVGA) -#else -# define machine_is_bcmring_sp_wqvga() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING_CUSTOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING_CUSTOM -# endif -# define machine_is_bcmring_custom() (machine_arch_type == MACH_TYPE_BCMRING_CUSTOM) -#else -# define machine_is_bcmring_custom() (0) -#endif - -#ifdef CONFIG_MACH_ACER_S200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_S200 -# endif -# define machine_is_acer_s200() (machine_arch_type == MACH_TYPE_ACER_S200) -#else -# define machine_is_acer_s200() (0) -#endif - -#ifdef CONFIG_MACH_BT270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BT270 -# endif -# define machine_is_bt270() (machine_arch_type == MACH_TYPE_BT270) -#else -# define machine_is_bt270() (0) -#endif - -#ifdef CONFIG_MACH_ISEO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ISEO -# endif -# define machine_is_iseo() (machine_arch_type == MACH_TYPE_ISEO) -#else -# define machine_is_iseo() (0) -#endif - -#ifdef CONFIG_MACH_CEZANNE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEZANNE -# endif -# define machine_is_cezanne() (machine_arch_type == MACH_TYPE_CEZANNE) -#else -# define machine_is_cezanne() (0) -#endif - -#ifdef CONFIG_MACH_LUCCA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUCCA -# endif -# define machine_is_lucca() (machine_arch_type == MACH_TYPE_LUCCA) -#else -# define machine_is_lucca() (0) -#endif - -#ifdef CONFIG_MACH_SUPERSMART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUPERSMART -# endif -# define machine_is_supersmart() (machine_arch_type == MACH_TYPE_SUPERSMART) -#else -# define machine_is_supersmart() (0) -#endif - -#ifdef CONFIG_MACH_CS_MISANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CS_MISANO -# endif -# define machine_is_arm11_board() (machine_arch_type == MACH_TYPE_CS_MISANO) -#else -# define machine_is_arm11_board() (0) -#endif - -#ifdef CONFIG_MACH_MAGNOLIA2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGNOLIA2 -# endif -# define machine_is_magnolia2() (machine_arch_type == MACH_TYPE_MAGNOLIA2) -#else -# define machine_is_magnolia2() (0) -#endif - -#ifdef CONFIG_MACH_EMXX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMXX -# endif -# define machine_is_emxx() (machine_arch_type == MACH_TYPE_EMXX) -#else -# define machine_is_emxx() (0) -#endif - -#ifdef CONFIG_MACH_OUTLAW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OUTLAW -# endif -# define machine_is_outlaw() (machine_arch_type == MACH_TYPE_OUTLAW) -#else -# define machine_is_outlaw() (0) -#endif - -#ifdef CONFIG_MACH_RIOT_BEI2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIOT_BEI2 -# endif -# define machine_is_riot_bei2() (machine_arch_type == MACH_TYPE_RIOT_BEI2) -#else -# define machine_is_riot_bei2() (0) -#endif - -#ifdef CONFIG_MACH_RIOT_VOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIOT_VOX -# endif -# define machine_is_riot_vox() (machine_arch_type == MACH_TYPE_RIOT_VOX) -#else -# define machine_is_riot_vox() (0) -#endif - -#ifdef CONFIG_MACH_RIOT_X37 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIOT_X37 -# endif -# define machine_is_riot_x37() (machine_arch_type == MACH_TYPE_RIOT_X37) -#else -# define machine_is_riot_x37() (0) -#endif - -#ifdef CONFIG_MACH_MEGA25MX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MEGA25MX -# endif -# define machine_is_mega25mx() (machine_arch_type == MACH_TYPE_MEGA25MX) -#else -# define machine_is_mega25mx() (0) -#endif - -#ifdef CONFIG_MACH_BENZINA2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BENZINA2 -# endif -# define machine_is_benzina2() (machine_arch_type == MACH_TYPE_BENZINA2) -#else -# define machine_is_benzina2() (0) -#endif - -#ifdef CONFIG_MACH_IGNITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGNITE -# endif -# define machine_is_ignite() (machine_arch_type == MACH_TYPE_IGNITE) -#else -# define machine_is_ignite() (0) -#endif - -#ifdef CONFIG_MACH_FOGGIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FOGGIA -# endif -# define machine_is_foggia() (machine_arch_type == MACH_TYPE_FOGGIA) -#else -# define machine_is_foggia() (0) -#endif - -#ifdef CONFIG_MACH_AREZZO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AREZZO -# endif -# define machine_is_arezzo() (machine_arch_type == MACH_TYPE_AREZZO) -#else -# define machine_is_arezzo() (0) -#endif - -#ifdef CONFIG_MACH_LEICA_SKYWALKER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEICA_SKYWALKER -# endif -# define machine_is_leica_skywalker() (machine_arch_type == MACH_TYPE_LEICA_SKYWALKER) -#else -# define machine_is_leica_skywalker() (0) -#endif - -#ifdef CONFIG_MACH_JACINTO2_JAMR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JACINTO2_JAMR -# endif -# define machine_is_jacinto2_jamr() (machine_arch_type == MACH_TYPE_JACINTO2_JAMR) -#else -# define machine_is_jacinto2_jamr() (0) -#endif - -#ifdef CONFIG_MACH_GTS_NOVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GTS_NOVA -# endif -# define machine_is_gts_nova() (machine_arch_type == MACH_TYPE_GTS_NOVA) -#else -# define machine_is_gts_nova() (0) -#endif - -#ifdef CONFIG_MACH_P3600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P3600 -# endif -# define machine_is_p3600() (machine_arch_type == MACH_TYPE_P3600) -#else -# define machine_is_p3600() (0) -#endif - -#ifdef CONFIG_MACH_DLT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DLT2 -# endif -# define machine_is_dlt2() (machine_arch_type == MACH_TYPE_DLT2) -#else -# define machine_is_dlt2() (0) -#endif - -#ifdef CONFIG_MACH_DF3120 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DF3120 -# endif -# define machine_is_df3120() (machine_arch_type == MACH_TYPE_DF3120) -#else -# define machine_is_df3120() (0) -#endif - -#ifdef CONFIG_MACH_ECUCORE_9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECUCORE_9G20 -# endif -# define machine_is_ecucore_9g20() (machine_arch_type == MACH_TYPE_ECUCORE_9G20) -#else -# define machine_is_ecucore_9g20() (0) -#endif - -#ifdef CONFIG_MACH_NAUTEL_LPC3240 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAUTEL_LPC3240 -# endif -# define machine_is_nautel_lpc3240() (machine_arch_type == MACH_TYPE_NAUTEL_LPC3240) -#else -# define machine_is_nautel_lpc3240() (0) -#endif - -#ifdef CONFIG_MACH_GLACIER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GLACIER -# endif -# define machine_is_glacier() (machine_arch_type == MACH_TYPE_GLACIER) -#else -# define machine_is_glacier() (0) -#endif - -#ifdef CONFIG_MACH_PHRAZER_BULLDOG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHRAZER_BULLDOG -# endif -# define machine_is_phrazer_bulldog() (machine_arch_type == MACH_TYPE_PHRAZER_BULLDOG) -#else -# define machine_is_phrazer_bulldog() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_BULLDOG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_BULLDOG -# endif -# define machine_is_omap3_bulldog() (machine_arch_type == MACH_TYPE_OMAP3_BULLDOG) -#else -# define machine_is_omap3_bulldog() (0) -#endif - -#ifdef CONFIG_MACH_PCA101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCA101 -# endif -# define machine_is_pca101() (machine_arch_type == MACH_TYPE_PCA101) -#else -# define machine_is_pca101() (0) -#endif - -#ifdef CONFIG_MACH_BUZZC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUZZC -# endif -# define machine_is_buzzc() (machine_arch_type == MACH_TYPE_BUZZC) -#else -# define machine_is_buzzc() (0) -#endif - -#ifdef CONFIG_MACH_SASIE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SASIE2 -# endif -# define machine_is_sasie2() (machine_arch_type == MACH_TYPE_SASIE2) -#else -# define machine_is_sasie2() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_CIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_CIO -# endif -# define machine_is_davinci_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO) -#else -# define machine_is_davinci_cio() (0) -#endif - -#ifdef CONFIG_MACH_SMARTMETER_DL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTMETER_DL -# endif -# define machine_is_smartmeter_dl() (machine_arch_type == MACH_TYPE_SMARTMETER_DL) -#else -# define machine_is_smartmeter_dl() (0) -#endif - -#ifdef CONFIG_MACH_WZL6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WZL6410 -# endif -# define machine_is_wzl6410() (machine_arch_type == MACH_TYPE_WZL6410) -#else -# define machine_is_wzl6410() (0) -#endif - -#ifdef CONFIG_MACH_WZL6410M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WZL6410M -# endif -# define machine_is_wzl6410m() (machine_arch_type == MACH_TYPE_WZL6410M) -#else -# define machine_is_wzl6410m() (0) -#endif - -#ifdef CONFIG_MACH_WZL6410F -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WZL6410F -# endif -# define machine_is_wzl6410f() (machine_arch_type == MACH_TYPE_WZL6410F) -#else -# define machine_is_wzl6410f() (0) -#endif - -#ifdef CONFIG_MACH_WZL6410I -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WZL6410I -# endif -# define machine_is_wzl6410i() (machine_arch_type == MACH_TYPE_WZL6410I) -#else -# define machine_is_wzl6410i() (0) -#endif - -#ifdef CONFIG_MACH_SPACECOM1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPACECOM1 -# endif -# define machine_is_spacecom1() (machine_arch_type == MACH_TYPE_SPACECOM1) -#else -# define machine_is_spacecom1() (0) -#endif - -#ifdef CONFIG_MACH_PINGU920 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PINGU920 -# endif -# define machine_is_pingu920() (machine_arch_type == MACH_TYPE_PINGU920) -#else -# define machine_is_pingu920() (0) -#endif - -#ifdef CONFIG_MACH_BRAVOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRAVOC -# endif -# define machine_is_bravoc() (machine_arch_type == MACH_TYPE_BRAVOC) -#else -# define machine_is_bravoc() (0) -#endif - -#ifdef CONFIG_MACH_CYBO2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CYBO2440 -# endif -# define machine_is_cybo2440() (machine_arch_type == MACH_TYPE_CYBO2440) -#else -# define machine_is_cybo2440() (0) -#endif - -#ifdef CONFIG_MACH_VDSSW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VDSSW -# endif -# define machine_is_vdssw() (machine_arch_type == MACH_TYPE_VDSSW) -#else -# define machine_is_vdssw() (0) -#endif - -#ifdef CONFIG_MACH_ROMULUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROMULUS -# endif -# define machine_is_romulus() (machine_arch_type == MACH_TYPE_ROMULUS) -#else -# define machine_is_romulus() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_MAGIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_MAGIC -# endif -# define machine_is_omap_magic() (machine_arch_type == MACH_TYPE_OMAP_MAGIC) -#else -# define machine_is_omap_magic() (0) -#endif - -#ifdef CONFIG_MACH_ELTD100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELTD100 -# endif -# define machine_is_eltd100() (machine_arch_type == MACH_TYPE_ELTD100) -#else -# define machine_is_eltd100() (0) -#endif - -#ifdef CONFIG_MACH_CAPC7117 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAPC7117 -# endif -# define machine_is_capc7117() (machine_arch_type == MACH_TYPE_CAPC7117) -#else -# define machine_is_capc7117() (0) -#endif - -#ifdef CONFIG_MACH_SWAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWAN -# endif -# define machine_is_swan() (machine_arch_type == MACH_TYPE_SWAN) -#else -# define machine_is_swan() (0) -#endif - -#ifdef CONFIG_MACH_VEU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VEU -# endif -# define machine_is_veu() (machine_arch_type == MACH_TYPE_VEU) -#else -# define machine_is_veu() (0) -#endif - -#ifdef CONFIG_MACH_RM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RM2 -# endif -# define machine_is_rm2() (machine_arch_type == MACH_TYPE_RM2) -#else -# define machine_is_rm2() (0) -#endif - -#ifdef CONFIG_MACH_TT2100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TT2100 -# endif -# define machine_is_tt2100() (machine_arch_type == MACH_TYPE_TT2100) -#else -# define machine_is_tt2100() (0) -#endif - -#ifdef CONFIG_MACH_VENICE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VENICE -# endif -# define machine_is_venice() (machine_arch_type == MACH_TYPE_VENICE) -#else -# define machine_is_venice() (0) -#endif - -#ifdef CONFIG_MACH_PC7323 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC7323 -# endif -# define machine_is_pc7323() (machine_arch_type == MACH_TYPE_PC7323) -#else -# define machine_is_pc7323() (0) -#endif - -#ifdef CONFIG_MACH_MASP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MASP -# endif -# define machine_is_masp() (machine_arch_type == MACH_TYPE_MASP) -#else -# define machine_is_masp() (0) -#endif - -#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC -# endif -# define machine_is_fujitsu_tvstbsoc0() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC) -#else -# define machine_is_fujitsu_tvstbsoc0() (0) -#endif - -#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC1 -# endif -# define machine_is_fujitsu_tvstbsoc1() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC1) -#else -# define machine_is_fujitsu_tvstbsoc1() (0) -#endif - -#ifdef CONFIG_MACH_LEXIKON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEXIKON -# endif -# define machine_is_lexikon() (machine_arch_type == MACH_TYPE_LEXIKON) -#else -# define machine_is_lexikon() (0) -#endif - -#ifdef CONFIG_MACH_MINI2440V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI2440V2 -# endif -# define machine_is_mini2440v2() (machine_arch_type == MACH_TYPE_MINI2440V2) -#else -# define machine_is_mini2440v2() (0) -#endif - -#ifdef CONFIG_MACH_ICONTROL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICONTROL -# endif -# define machine_is_icontrol() (machine_arch_type == MACH_TYPE_ICONTROL) -#else -# define machine_is_icontrol() (0) -#endif - -#ifdef CONFIG_MACH_SHEEVAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHEEVAD -# endif -# define machine_is_sheevad() (machine_arch_type == MACH_TYPE_SHEEVAD) -#else -# define machine_is_sheevad() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50A_ST1_1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_1 -# endif -# define machine_is_qsd8x50a_st1_1() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_1) -#else -# define machine_is_qsd8x50a_st1_1() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50A_ST1_5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_5 -# endif -# define machine_is_qsd8x50a_st1_5() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5) -#else -# define machine_is_qsd8x50a_st1_5() (0) -#endif - -#ifdef CONFIG_MACH_BEE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BEE -# endif -# define machine_is_bee() (machine_arch_type == MACH_TYPE_BEE) -#else -# define machine_is_bee() (0) -#endif - -#ifdef CONFIG_MACH_MX23EVK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX23EVK -# endif -# define machine_is_mx23evk() (machine_arch_type == MACH_TYPE_MX23EVK) -#else -# define machine_is_mx23evk() (0) -#endif - -#ifdef CONFIG_MACH_AP4EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AP4EVB -# endif -# define machine_is_ap4evb() (machine_arch_type == MACH_TYPE_AP4EVB) -#else -# define machine_is_ap4evb() (0) -#endif - -#ifdef CONFIG_MACH_STOCKHOLM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STOCKHOLM -# endif -# define machine_is_stockholm() (machine_arch_type == MACH_TYPE_STOCKHOLM) -#else -# define machine_is_stockholm() (0) -#endif - -#ifdef CONFIG_MACH_LPC_H3131 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC_H3131 -# endif -# define machine_is_lpc_h3131() (machine_arch_type == MACH_TYPE_LPC_H3131) -#else -# define machine_is_lpc_h3131() (0) -#endif - -#ifdef CONFIG_MACH_STINGRAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STINGRAY -# endif -# define machine_is_stingray() (machine_arch_type == MACH_TYPE_STINGRAY) -#else -# define machine_is_stingray() (0) -#endif - -#ifdef CONFIG_MACH_KRAKEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KRAKEN -# endif -# define machine_is_kraken() (machine_arch_type == MACH_TYPE_KRAKEN) -#else -# define machine_is_kraken() (0) -#endif - -#ifdef CONFIG_MACH_GW2388 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GW2388 -# endif -# define machine_is_gw2388() (machine_arch_type == MACH_TYPE_GW2388) -#else -# define machine_is_gw2388() (0) -#endif - -#ifdef CONFIG_MACH_JADECPU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JADECPU -# endif -# define machine_is_jadecpu() (machine_arch_type == MACH_TYPE_JADECPU) -#else -# define machine_is_jadecpu() (0) -#endif - -#ifdef CONFIG_MACH_CARLISLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARLISLE -# endif -# define machine_is_carlisle() (machine_arch_type == MACH_TYPE_CARLISLE) -#else -# define machine_is_carlisle() (0) -#endif - -#ifdef CONFIG_MACH_LUX_SFT9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUX_SFT9 -# endif -# define machine_is_lux_sf9() (machine_arch_type == MACH_TYPE_LUX_SFT9) -#else -# define machine_is_lux_sf9() (0) -#endif - -#ifdef CONFIG_MACH_NEMID_TB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEMID_TB -# endif -# define machine_is_nemid_tb() (machine_arch_type == MACH_TYPE_NEMID_TB) -#else -# define machine_is_nemid_tb() (0) -#endif - -#ifdef CONFIG_MACH_TERRIER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TERRIER -# endif -# define machine_is_terrier() (machine_arch_type == MACH_TYPE_TERRIER) -#else -# define machine_is_terrier() (0) -#endif - -#ifdef CONFIG_MACH_TURBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TURBOT -# endif -# define machine_is_turbot() (machine_arch_type == MACH_TYPE_TURBOT) -#else -# define machine_is_turbot() (0) -#endif - -#ifdef CONFIG_MACH_SANDDAB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANDDAB -# endif -# define machine_is_sanddab() (machine_arch_type == MACH_TYPE_SANDDAB) -#else -# define machine_is_sanddab() (0) -#endif - -#ifdef CONFIG_MACH_MX35_CICADA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35_CICADA -# endif -# define machine_is_mx35_cicada() (machine_arch_type == MACH_TYPE_MX35_CICADA) -#else -# define machine_is_mx35_cicada() (0) -#endif - -#ifdef CONFIG_MACH_GHI2703D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GHI2703D -# endif -# define machine_is_ghi2703d() (machine_arch_type == MACH_TYPE_GHI2703D) -#else -# define machine_is_ghi2703d() (0) -#endif - -#ifdef CONFIG_MACH_LUX_SFX9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUX_SFX9 -# endif -# define machine_is_lux_sfx9() (machine_arch_type == MACH_TYPE_LUX_SFX9) -#else -# define machine_is_lux_sfx9() (0) -#endif - -#ifdef CONFIG_MACH_LUX_SF9G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUX_SF9G -# endif -# define machine_is_lux_sf9g() (machine_arch_type == MACH_TYPE_LUX_SF9G) -#else -# define machine_is_lux_sf9g() (0) -#endif - -#ifdef CONFIG_MACH_LUX_EDK9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUX_EDK9 -# endif -# define machine_is_lux_edk9() (machine_arch_type == MACH_TYPE_LUX_EDK9) -#else -# define machine_is_lux_edk9() (0) -#endif - -#ifdef CONFIG_MACH_HW90240 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HW90240 -# endif -# define machine_is_hw90240() (machine_arch_type == MACH_TYPE_HW90240) -#else -# define machine_is_hw90240() (0) -#endif - -#ifdef CONFIG_MACH_DM365_LEOPARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM365_LEOPARD -# endif -# define machine_is_dm365_leopard() (machine_arch_type == MACH_TYPE_DM365_LEOPARD) -#else -# define machine_is_dm365_leopard() (0) -#endif - -#ifdef CONFIG_MACH_MITYOMAPL138 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MITYOMAPL138 -# endif -# define machine_is_mityomapl138() (machine_arch_type == MACH_TYPE_MITYOMAPL138) -#else -# define machine_is_mityomapl138() (0) -#endif - -#ifdef CONFIG_MACH_SCAT110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCAT110 -# endif -# define machine_is_scat110() (machine_arch_type == MACH_TYPE_SCAT110) -#else -# define machine_is_scat110() (0) -#endif - -#ifdef CONFIG_MACH_ACER_A1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_A1 -# endif -# define machine_is_acer_a1() (machine_arch_type == MACH_TYPE_ACER_A1) -#else -# define machine_is_acer_a1() (0) -#endif - -#ifdef CONFIG_MACH_CMCONTROL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CMCONTROL -# endif -# define machine_is_cmcontrol() (machine_arch_type == MACH_TYPE_CMCONTROL) -#else -# define machine_is_cmcontrol() (0) -#endif - -#ifdef CONFIG_MACH_PELCO_LAMAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PELCO_LAMAR -# endif -# define machine_is_pelco_lamar() (machine_arch_type == MACH_TYPE_PELCO_LAMAR) -#else -# define machine_is_pelco_lamar() (0) -#endif - -#ifdef CONFIG_MACH_RFP43 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RFP43 -# endif -# define machine_is_rfp43() (machine_arch_type == MACH_TYPE_RFP43) -#else -# define machine_is_rfp43() (0) -#endif - -#ifdef CONFIG_MACH_SK86R0301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SK86R0301 -# endif -# define machine_is_sk86r0301() (machine_arch_type == MACH_TYPE_SK86R0301) -#else -# define machine_is_sk86r0301() (0) -#endif - -#ifdef CONFIG_MACH_CTPXA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTPXA -# endif -# define machine_is_ctpxa() (machine_arch_type == MACH_TYPE_CTPXA) -#else -# define machine_is_ctpxa() (0) -#endif - -#ifdef CONFIG_MACH_EPB_ARM9_A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPB_ARM9_A -# endif -# define machine_is_epb_arm9_a() (machine_arch_type == MACH_TYPE_EPB_ARM9_A) -#else -# define machine_is_epb_arm9_a() (0) -#endif - -#ifdef CONFIG_MACH_GURUPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GURUPLUG -# endif -# define machine_is_guruplug() (machine_arch_type == MACH_TYPE_GURUPLUG) -#else -# define machine_is_guruplug() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR310 -# endif -# define machine_is_spear310() (machine_arch_type == MACH_TYPE_SPEAR310) -#else -# define machine_is_spear310() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR320 -# endif -# define machine_is_spear320() (machine_arch_type == MACH_TYPE_SPEAR320) -#else -# define machine_is_spear320() (0) -#endif - -#ifdef CONFIG_MACH_ROBOTX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROBOTX -# endif -# define machine_is_robotx() (machine_arch_type == MACH_TYPE_ROBOTX) -#else -# define machine_is_robotx() (0) -#endif - -#ifdef CONFIG_MACH_LSXHL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LSXHL -# endif -# define machine_is_lsxhl() (machine_arch_type == MACH_TYPE_LSXHL) -#else -# define machine_is_lsxhl() (0) -#endif - -#ifdef CONFIG_MACH_SMARTLITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTLITE -# endif -# define machine_is_smartlite() (machine_arch_type == MACH_TYPE_SMARTLITE) -#else -# define machine_is_smartlite() (0) -#endif - -#ifdef CONFIG_MACH_CWS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWS2 -# endif -# define machine_is_cws2() (machine_arch_type == MACH_TYPE_CWS2) -#else -# define machine_is_cws2() (0) -#endif - -#ifdef CONFIG_MACH_M619 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M619 -# endif -# define machine_is_m619() (machine_arch_type == MACH_TYPE_M619) -#else -# define machine_is_m619() (0) -#endif - -#ifdef CONFIG_MACH_SMARTVIEW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTVIEW -# endif -# define machine_is_smartview() (machine_arch_type == MACH_TYPE_SMARTVIEW) -#else -# define machine_is_smartview() (0) -#endif - -#ifdef CONFIG_MACH_LSA_SALSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LSA_SALSA -# endif -# define machine_is_lsa_salsa() (machine_arch_type == MACH_TYPE_LSA_SALSA) -#else -# define machine_is_lsa_salsa() (0) -#endif - -#ifdef CONFIG_MACH_KIZBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIZBOX -# endif -# define machine_is_kizbox() (machine_arch_type == MACH_TYPE_KIZBOX) -#else -# define machine_is_kizbox() (0) -#endif - -#ifdef CONFIG_MACH_HTCCHARMER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCCHARMER -# endif -# define machine_is_htccharmer() (machine_arch_type == MACH_TYPE_HTCCHARMER) -#else -# define machine_is_htccharmer() (0) -#endif - -#ifdef CONFIG_MACH_GUF_NESO_LT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUF_NESO_LT -# endif -# define machine_is_guf_neso_lt() (machine_arch_type == MACH_TYPE_GUF_NESO_LT) -#else -# define machine_is_guf_neso_lt() (0) -#endif - -#ifdef CONFIG_MACH_PM9G45 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PM9G45 -# endif -# define machine_is_pm9g45() (machine_arch_type == MACH_TYPE_PM9G45) -#else -# define machine_is_pm9g45() (0) -#endif - -#ifdef CONFIG_MACH_HTCPANTHER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCPANTHER -# endif -# define machine_is_htcpanther() (machine_arch_type == MACH_TYPE_HTCPANTHER) -#else -# define machine_is_htcpanther() (0) -#endif - -#ifdef CONFIG_MACH_HTCPANTHER_CDMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCPANTHER_CDMA -# endif -# define machine_is_htcpanther_cdma() (machine_arch_type == MACH_TYPE_HTCPANTHER_CDMA) -#else -# define machine_is_htcpanther_cdma() (0) -#endif - -#ifdef CONFIG_MACH_REB01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REB01 -# endif -# define machine_is_reb01() (machine_arch_type == MACH_TYPE_REB01) -#else -# define machine_is_reb01() (0) -#endif - -#ifdef CONFIG_MACH_AQUILA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AQUILA -# endif -# define machine_is_aquila() (machine_arch_type == MACH_TYPE_AQUILA) -#else -# define machine_is_aquila() (0) -#endif - -#ifdef CONFIG_MACH_SPARK_SLS_HW2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPARK_SLS_HW2 -# endif -# define machine_is_spark_sls_hw2() (machine_arch_type == MACH_TYPE_SPARK_SLS_HW2) -#else -# define machine_is_spark_sls_hw2() (0) -#endif - -#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESATA_SHEEVAPLUG -# endif -# define machine_is_sheeva_esata() (machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG) -#else -# define machine_is_sheeva_esata() (0) -#endif - -#ifdef CONFIG_MACH_SURF7X30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SURF7X30 -# endif -# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_SURF7X30) -#else -# define machine_is_msm7x30_surf() (0) -#endif - -#ifdef CONFIG_MACH_MICRO2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO2440 -# endif -# define machine_is_micro2440() (machine_arch_type == MACH_TYPE_MICRO2440) -#else -# define machine_is_micro2440() (0) -#endif - -#ifdef CONFIG_MACH_AM2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AM2440 -# endif -# define machine_is_am2440() (machine_arch_type == MACH_TYPE_AM2440) -#else -# define machine_is_am2440() (0) -#endif - -#ifdef CONFIG_MACH_TQ2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TQ2440 -# endif -# define machine_is_tq2440() (machine_arch_type == MACH_TYPE_TQ2440) -#else -# define machine_is_tq2440() (0) -#endif - -#ifdef CONFIG_MACH_LPC2478OEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC2478OEM -# endif -# define machine_is_lpc2478oem() (machine_arch_type == MACH_TYPE_LPC2478OEM) -#else -# define machine_is_lpc2478oem() (0) -#endif - -#ifdef CONFIG_MACH_AK880X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AK880X -# endif -# define machine_is_ak880x() (machine_arch_type == MACH_TYPE_AK880X) -#else -# define machine_is_ak880x() (0) -#endif - -#ifdef CONFIG_MACH_COBRA3530 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COBRA3530 -# endif -# define machine_is_cobra3530() (machine_arch_type == MACH_TYPE_COBRA3530) -#else -# define machine_is_cobra3530() (0) -#endif - -#ifdef CONFIG_MACH_PMPPB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PMPPB -# endif -# define machine_is_pmppb() (machine_arch_type == MACH_TYPE_PMPPB) -#else -# define machine_is_pmppb() (0) -#endif - -#ifdef CONFIG_MACH_U6715 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U6715 -# endif -# define machine_is_u6715() (machine_arch_type == MACH_TYPE_U6715) -#else -# define machine_is_u6715() (0) -#endif - -#ifdef CONFIG_MACH_AXAR1500_SENDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXAR1500_SENDER -# endif -# define machine_is_axar1500_sender() (machine_arch_type == MACH_TYPE_AXAR1500_SENDER) -#else -# define machine_is_axar1500_sender() (0) -#endif - -#ifdef CONFIG_MACH_G30_DVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G30_DVB -# endif -# define machine_is_g30_dvb() (machine_arch_type == MACH_TYPE_G30_DVB) -#else -# define machine_is_g30_dvb() (0) -#endif - -#ifdef CONFIG_MACH_VC088X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC088X -# endif -# define machine_is_vc088x() (machine_arch_type == MACH_TYPE_VC088X) -#else -# define machine_is_vc088x() (0) -#endif - -#ifdef CONFIG_MACH_MIOA702 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIOA702 -# endif -# define machine_is_mioa702() (machine_arch_type == MACH_TYPE_MIOA702) -#else -# define machine_is_mioa702() (0) -#endif - -#ifdef CONFIG_MACH_HPMIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HPMIN -# endif -# define machine_is_hpmin() (machine_arch_type == MACH_TYPE_HPMIN) -#else -# define machine_is_hpmin() (0) -#endif - -#ifdef CONFIG_MACH_AK880XAK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AK880XAK -# endif -# define machine_is_ak880xak() (machine_arch_type == MACH_TYPE_AK880XAK) -#else -# define machine_is_ak880xak() (0) -#endif - -#ifdef CONFIG_MACH_ARM926TOMAP850 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARM926TOMAP850 -# endif -# define machine_is_arm926tomap850() (machine_arch_type == MACH_TYPE_ARM926TOMAP850) -#else -# define machine_is_arm926tomap850() (0) -#endif - -#ifdef CONFIG_MACH_LKEVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LKEVM -# endif -# define machine_is_lkevm() (machine_arch_type == MACH_TYPE_LKEVM) -#else -# define machine_is_lkevm() (0) -#endif - -#ifdef CONFIG_MACH_MW6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MW6410 -# endif -# define machine_is_mw6410() (machine_arch_type == MACH_TYPE_MW6410) -#else -# define machine_is_mw6410() (0) -#endif - -#ifdef CONFIG_MACH_TERASTATION_WXL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TERASTATION_WXL -# endif -# define machine_is_terastation_wxl() (machine_arch_type == MACH_TYPE_TERASTATION_WXL) -#else -# define machine_is_terastation_wxl() (0) -#endif - -#ifdef CONFIG_MACH_CPU8000E -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPU8000E -# endif -# define machine_is_cpu8000e() (machine_arch_type == MACH_TYPE_CPU8000E) -#else -# define machine_is_cpu8000e() (0) -#endif - -#ifdef CONFIG_MACH_CATANIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CATANIA -# endif -# define machine_is_catania() (machine_arch_type == MACH_TYPE_CATANIA) -#else -# define machine_is_catania() (0) -#endif - -#ifdef CONFIG_MACH_TOKYO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOKYO -# endif -# define machine_is_tokyo() (machine_arch_type == MACH_TYPE_TOKYO) -#else -# define machine_is_tokyo() (0) -#endif - -#ifdef CONFIG_MACH_MSM7201A_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7201A_SURF -# endif -# define machine_is_msm7201a_surf() (machine_arch_type == MACH_TYPE_MSM7201A_SURF) -#else -# define machine_is_msm7201a_surf() (0) -#endif - -#ifdef CONFIG_MACH_MSM7201A_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7201A_FFA -# endif -# define machine_is_msm7201a_ffa() (machine_arch_type == MACH_TYPE_MSM7201A_FFA) -#else -# define machine_is_msm7201a_ffa() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X25_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X25_SURF -# endif -# define machine_is_msm7x25_surf() (machine_arch_type == MACH_TYPE_MSM7X25_SURF) -#else -# define machine_is_msm7x25_surf() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X25_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X25_FFA -# endif -# define machine_is_msm7x25_ffa() (machine_arch_type == MACH_TYPE_MSM7X25_FFA) -#else -# define machine_is_msm7x25_ffa() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X27_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X27_SURF -# endif -# define machine_is_msm7x27_surf() (machine_arch_type == MACH_TYPE_MSM7X27_SURF) -#else -# define machine_is_msm7x27_surf() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X27_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X27_FFA -# endif -# define machine_is_msm7x27_ffa() (machine_arch_type == MACH_TYPE_MSM7X27_FFA) -#else -# define machine_is_msm7x27_ffa() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X30_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X30_FFA -# endif -# define machine_is_msm7x30_ffa() (machine_arch_type == MACH_TYPE_MSM7X30_FFA) -#else -# define machine_is_msm7x30_ffa() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50_SURF -# endif -# define machine_is_qsd8x50_surf() (machine_arch_type == MACH_TYPE_QSD8X50_SURF) -#else -# define machine_is_qsd8x50_surf() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50_COMET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50_COMET -# endif -# define machine_is_qsd8x50_comet() (machine_arch_type == MACH_TYPE_QSD8X50_COMET) -#else -# define machine_is_qsd8x50_comet() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50_FFA -# endif -# define machine_is_qsd8x50_ffa() (machine_arch_type == MACH_TYPE_QSD8X50_FFA) -#else -# define machine_is_qsd8x50_ffa() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50A_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50A_SURF -# endif -# define machine_is_qsd8x50a_surf() (machine_arch_type == MACH_TYPE_QSD8X50A_SURF) -#else -# define machine_is_qsd8x50a_surf() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50A_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50A_FFA -# endif -# define machine_is_qsd8x50a_ffa() (machine_arch_type == MACH_TYPE_QSD8X50A_FFA) -#else -# define machine_is_qsd8x50a_ffa() (0) -#endif - -#ifdef CONFIG_MACH_XGCP10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XGCP10 -# endif -# define machine_is_adx_xgcp10() (machine_arch_type == MACH_TYPE_XGCP10) -#else -# define machine_is_adx_xgcp10() (0) -#endif - -#ifdef CONFIG_MACH_MCGWUMTS2A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCGWUMTS2A -# endif -# define machine_is_mcgwumts2a() (machine_arch_type == MACH_TYPE_MCGWUMTS2A) -#else -# define machine_is_mcgwumts2a() (0) -#endif - -#ifdef CONFIG_MACH_MOBIKT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOBIKT -# endif -# define machine_is_mobikt() (machine_arch_type == MACH_TYPE_MOBIKT) -#else -# define machine_is_mobikt() (0) -#endif - -#ifdef CONFIG_MACH_MX53_EVK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX53_EVK -# endif -# define machine_is_mx53_evk() (machine_arch_type == MACH_TYPE_MX53_EVK) -#else -# define machine_is_mx53_evk() (0) -#endif - -#ifdef CONFIG_MACH_IGEP0030 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGEP0030 -# endif -# define machine_is_igep0030() (machine_arch_type == MACH_TYPE_IGEP0030) -#else -# define machine_is_igep0030() (0) -#endif - -#ifdef CONFIG_MACH_AXELL_H40_H50_CTRL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AXELL_H40_H50_CTRL -# endif -# define machine_is_axell_h40_h50_ctrl() (machine_arch_type == MACH_TYPE_AXELL_H40_H50_CTRL) -#else -# define machine_is_axell_h40_h50_ctrl() (0) -#endif - -/* - * These have not yet been registered - */ - -#ifndef machine_arch_type -#define machine_arch_type __machine_arch_type -#endif - -#endif diff --git a/include/asm-arm/macro.h b/include/asm-arm/macro.h deleted file mode 100644 index 57b5260..0000000 --- a/include/asm-arm/macro.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * include/asm-arm/macro.h - * - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARM_MACRO_H__ -#define __ASM_ARM_MACRO_H__ -#ifdef __ASSEMBLY__ - -/* - * These macros provide a convenient way to write 8, 16 and 32 bit data - * to any address. - * Registers r4 and r5 are used, any data in these registers are - * overwritten by the macros. - * The macros are valid for any ARM architecture, they do not implement - * any memory barriers so caution is recommended when using these when the - * caches are enabled or on a multi-core system. - */ - -.macro write32, addr, data - ldr r4, =\addr - ldr r5, =\data - str r5, [r4] -.endm - -.macro write16, addr, data - ldr r4, =\addr - ldrh r5, =\data - strh r5, [r4] -.endm - -.macro write8, addr, data - ldr r4, =\addr - ldrb r5, =\data - strb r5, [r4] -.endm - -/* - * This macro generates a loop that can be used for delays in the code. - * Register r4 is used, any data in this register is overwritten by the - * macro. - * The macro is valid for any ARM architeture. The actual time spent in the - * loop will vary from CPU to CPU though. - */ - -.macro wait_timer, time - ldr r4, =\time -1: - nop - subs r4, r4, #1 - bcs 1b -.endm - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARM_MACRO_H__ */ diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h deleted file mode 100644 index c3b2afd..0000000 --- a/include/asm-arm/memory.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * linux/include/asm-arm/memory.h - * - * Copyright (C) 2000-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: this file should not be included by non-asm/.h files - */ -#ifndef __ASM_ARM_MEMORY_H -#define __ASM_ARM_MEMORY_H - -#if 0 /* XXX###XXX */ - -#include -#include - -/* - * PFNs are used to describe any physical page; this means - * PFN 0 == physical address 0. - * - * This is the PFN of the first RAM page in the kernel - * direct-mapped view. We assume this is the first page - * of RAM in the mem_map as well. - */ -#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) - -/* - * These are *only* valid on the kernel direct mapped RAM memory. - */ -static inline unsigned long virt_to_phys(void *x) -{ - return __virt_to_phys((unsigned long)(x)); -} - -static inline void *phys_to_virt(unsigned long x) -{ - return (void *)(__phys_to_virt((unsigned long)(x))); -} - -#define __pa(x) __virt_to_phys((unsigned long)(x)) -#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) - -/* - * Virtual <-> DMA view memory address translations - * Again, these are *only* valid on the kernel direct mapped RAM - * memory. Use of these is *depreciated*. - */ -#define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) -#define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) - -/* - * Conversion between a struct page and a physical address. - * - * Note: when converting an unknown physical address to a - * struct page, the resulting pointer must be validated - * using VALID_PAGE(). It must return an invalid struct page - * for any physical address not corresponding to a system - * RAM address. - * - * page_to_pfn(page) convert a struct page * to a PFN number - * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * - * pfn_valid(pfn) indicates whether a PFN number is valid - * - * virt_to_page(k) convert a _valid_ virtual address to struct page * - * virt_addr_valid(k) indicates whether a virtual address is valid - */ -#ifndef CONFIG_DISCONTIGMEM - -#define page_to_pfn(page) (((page) - mem_map) + PHYS_PFN_OFFSET) -#define pfn_to_page(pfn) ((mem_map + (pfn)) - PHYS_PFN_OFFSET) -#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) - -#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) -#define virt_addr_valid(kaddr) ((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory) - -#define PHYS_TO_NID(addr) (0) - -#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) - -#else - -/* - * This is more complex. We have a set of mem_map arrays spread - * around in memory. - */ -#define page_to_pfn(page) \ - (((page) - page_zone(page)->zone_mem_map) \ - + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT)) - -#define pfn_to_page(pfn) \ - (PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT)) - -#define pfn_valid(pfn) \ - ({ \ - unsigned int node = PFN_TO_NID(pfn); \ - struct pglist_data *nd = NODE_DATA(node); \ - ((node < NR_NODES) && \ - ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\ - }) - -#define virt_to_page(kaddr) \ - (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) - -#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < NR_NODES) - -/* - * Common discontigmem stuff. - * PHYS_TO_NID is used by the ARM kernel/setup.c - */ -#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) - -/* - * 2.4 compatibility - * - * VALID_PAGE returns a non-zero value if given page pointer is valid. - * This assumes all node's mem_maps are stored within the node they - * refer to. This is actually inherently buggy. - */ -#define VALID_PAGE(page) \ -({ unsigned int node = KVADDR_TO_NID(page); \ - ((node < NR_NODES) && \ - ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \ -}) - -#endif - -/* - * We should really eliminate virt_to_bus() here - it's depreciated. - */ -#define page_to_bus(page) (virt_to_bus(page_address(page))) - -#endif /* XXX###XXX */ - -#endif /* __ASM_ARM_MEMORY_H */ diff --git a/include/asm-arm/posix_types.h b/include/asm-arm/posix_types.h deleted file mode 100644 index c412486..0000000 --- a/include/asm-arm/posix_types.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * linux/include/asm-arm/posix_types.h - * - * Copyright (C) 1996-1998 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - */ -#ifndef __ARCH_ARM_POSIX_TYPES_H -#define __ARCH_ARM_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) - -#undef __FD_CLR -#define __FD_CLR(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) - -#undef __FD_ISSET -#define __FD_ISSET(fd, fdsetp) \ - ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ - (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) - -#endif - -#endif diff --git a/include/asm-arm/proc-armv/domain.h b/include/asm-arm/proc-armv/domain.h deleted file mode 100644 index aadc831..0000000 --- a/include/asm-arm/proc-armv/domain.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * linux/include/asm-arm/proc-armv/domain.h - * - * Copyright (C) 1999 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_PROC_DOMAIN_H -#define __ASM_PROC_DOMAIN_H - -/* - * Domain numbers - * - * DOMAIN_IO - domain 2 includes all IO only - * DOMAIN_KERNEL - domain 1 includes all kernel memory only - * DOMAIN_USER - domain 0 includes all user memory only - */ -#define DOMAIN_USER 0 -#define DOMAIN_KERNEL 1 -#define DOMAIN_TABLE 1 -#define DOMAIN_IO 2 - -/* - * Domain types - */ -#define DOMAIN_NOACCESS 0 -#define DOMAIN_CLIENT 1 -#define DOMAIN_MANAGER 3 - -#define domain_val(dom,type) ((type) << 2*(dom)) - -#define set_domain(x) \ - do { \ - __asm__ __volatile__( \ - "mcr p15, 0, %0, c3, c0 @ set domain" \ - : : "r" (x)); \ - } while (0) - -#define modify_domain(dom,type) \ - do { \ - unsigned int domain = current->thread.domain; \ - domain &= ~domain_val(dom, DOMAIN_MANAGER); \ - domain |= domain_val(dom, type); \ - current->thread.domain = domain; \ - set_domain(current->thread.domain); \ - } while (0) - -#endif diff --git a/include/asm-arm/proc-armv/processor.h b/include/asm-arm/proc-armv/processor.h deleted file mode 100644 index 5bfab7f..0000000 --- a/include/asm-arm/proc-armv/processor.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * linux/include/asm-arm/proc-armv/processor.h - * - * Copyright (C) 1996-1999 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 20-09-1996 RMK Created - * 26-09-1996 RMK Added 'EXTRA_THREAD_STRUCT*' - * 28-09-1996 RMK Moved start_thread into the processor dependencies - * 09-09-1998 PJB Delete redundant `wp_works_ok' - * 30-05-1999 PJB Save sl across context switches - * 31-07-1999 RMK Added 'domain' stuff - */ -#ifndef __ASM_PROC_PROCESSOR_H -#define __ASM_PROC_PROCESSOR_H - -#include - -#define KERNEL_STACK_SIZE PAGE_SIZE - -struct context_save_struct { - unsigned long cpsr; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long sl; - unsigned long fp; - unsigned long pc; -}; - -#define INIT_CSS (struct context_save_struct){ SVC_MODE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } - -#define EXTRA_THREAD_STRUCT \ - unsigned int domain; - -#define EXTRA_THREAD_STRUCT_INIT \ - domain: domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \ - domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_IO, DOMAIN_CLIENT) - -#define start_thread(regs,pc,sp) \ -({ \ - unsigned long *stack = (unsigned long *)sp; \ - set_fs(USER_DS); \ - memzero(regs->uregs, sizeof(regs->uregs)); \ - if (current->personality & ADDR_LIMIT_32BIT) \ - regs->ARM_cpsr = USR_MODE; \ - else \ - regs->ARM_cpsr = USR26_MODE; \ - regs->ARM_pc = pc; /* pc */ \ - regs->ARM_sp = sp; /* sp */ \ - regs->ARM_r2 = stack[2]; /* r2 (envp) */ \ - regs->ARM_r1 = stack[1]; /* r1 (argv) */ \ - regs->ARM_r0 = stack[0]; /* r0 (argc) */ \ -}) - -#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019]) -#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1017]) - -/* Allocation and freeing of basic task resources. */ -/* - * NOTE! The task struct and the stack go together - */ -#define ll_alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define ll_free_task_struct(p) free_pages((unsigned long)(p),1) - -#endif diff --git a/include/asm-arm/proc-armv/ptrace.h b/include/asm-arm/proc-armv/ptrace.h deleted file mode 100644 index 79cc644..0000000 --- a/include/asm-arm/proc-armv/ptrace.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * linux/include/asm-arm/proc-armv/ptrace.h - * - * Copyright (C) 1996-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_PROC_PTRACE_H -#define __ASM_PROC_PTRACE_H - -#include - -#define USR26_MODE 0x00 -#define FIQ26_MODE 0x01 -#define IRQ26_MODE 0x02 -#define SVC26_MODE 0x03 -#define USR_MODE 0x10 -#define FIQ_MODE 0x11 -#define IRQ_MODE 0x12 -#define SVC_MODE 0x13 -#define ABT_MODE 0x17 -#define UND_MODE 0x1b -#define SYSTEM_MODE 0x1f -#define MODE_MASK 0x1f -#define T_BIT 0x20 -#define F_BIT 0x40 -#define I_BIT 0x80 -#define CC_V_BIT (1 << 28) -#define CC_C_BIT (1 << 29) -#define CC_Z_BIT (1 << 30) -#define CC_N_BIT (1 << 31) -#define PCMASK 0 - -#ifndef __ASSEMBLY__ - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long uregs[18]; -}; - -#define ARM_cpsr uregs[16] -#define ARM_pc uregs[15] -#define ARM_lr uregs[14] -#define ARM_sp uregs[13] -#define ARM_ip uregs[12] -#define ARM_fp uregs[11] -#define ARM_r10 uregs[10] -#define ARM_r9 uregs[9] -#define ARM_r8 uregs[8] -#define ARM_r7 uregs[7] -#define ARM_r6 uregs[6] -#define ARM_r5 uregs[5] -#define ARM_r4 uregs[4] -#define ARM_r3 uregs[3] -#define ARM_r2 uregs[2] -#define ARM_r1 uregs[1] -#define ARM_r0 uregs[0] -#define ARM_ORIG_r0 uregs[17] - -#ifdef __KERNEL__ - -#define user_mode(regs) \ - (((regs)->ARM_cpsr & 0xf) == 0) - -#ifdef CONFIG_ARM_THUMB -#define thumb_mode(regs) \ - (((regs)->ARM_cpsr & T_BIT)) -#else -#define thumb_mode(regs) (0) -#endif - -#define processor_mode(regs) \ - ((regs)->ARM_cpsr & MODE_MASK) - -#define interrupts_enabled(regs) \ - (!((regs)->ARM_cpsr & I_BIT)) - -#define fast_interrupts_enabled(regs) \ - (!((regs)->ARM_cpsr & F_BIT)) - -#define condition_codes(regs) \ - ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT)) - -/* Are the current registers suitable for user mode? - * (used to maintain security in signal handlers) - */ -static inline int valid_user_regs(struct pt_regs *regs) -{ - if ((regs->ARM_cpsr & 0xf) == 0 && - (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0) - return 1; - - /* - * Force CPSR to something logical... - */ - regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10); - - return 0; -} - -#endif /* __KERNEL__ */ - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-arm/proc-armv/system.h b/include/asm-arm/proc-armv/system.h deleted file mode 100644 index b4cfa68..0000000 --- a/include/asm-arm/proc-armv/system.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * linux/include/asm-arm/proc-armv/system.h - * - * Copyright (C) 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_PROC_SYSTEM_H -#define __ASM_PROC_SYSTEM_H - -#include - -/* - * Save the current interrupt enable state & disable IRQs - */ -#define local_irq_save(x) \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_save\n" \ -" orr %1, %0, #128\n" \ -" msr cpsr_c, %1" \ - : "=r" (x), "=r" (temp) \ - : \ - : "memory"); \ - }) - -/* - * Enable IRQs - */ -#define local_irq_enable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_enable\n" \ -" bic %0, %0, #128\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory"); \ - }) - -/* - * Disable IRQs - */ -#define local_irq_disable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_disable\n" \ -" orr %0, %0, #128\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory"); \ - }) - -/* - * Enable FIQs - */ -#define __stf() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ stf\n" \ -" bic %0, %0, #64\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory"); \ - }) - -/* - * Disable FIQs - */ -#define __clf() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ clf\n" \ -" orr %0, %0, #64\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory"); \ - }) - -/* - * Save the current interrupt enable state. - */ -#define local_save_flags(x) \ - ({ \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_save_flags\n" \ - : "=r" (x) \ - : \ - : "memory"); \ - }) - -/* - * restore saved IRQ & FIQ state - */ -#define local_irq_restore(x) \ - __asm__ __volatile__( \ - "msr cpsr_c, %0 @ local_irq_restore\n" \ - : \ - : "r" (x) \ - : "memory") - -#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) -/* - * On the StrongARM, "swp" is terminally broken since it bypasses the - * cache totally. This means that the cache becomes inconsistent, and, - * since we use normal loads/stores as well, this is really bad. - * Typically, this causes oopsen in filp_close, but could have other, - * more disasterous effects. There are two work-arounds: - * 1. Disable interrupts and emulate the atomic swap - * 2. Clean the cache, perform atomic swap, flush the cache - * - * We choose (1) since its the "easiest" to achieve here and is not - * dependent on the processor type. - */ -#define swp_is_buggy -#endif - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) -{ - extern void __bad_xchg(volatile void *, int); - unsigned long ret; -#ifdef swp_is_buggy - unsigned long flags; -#endif - - switch (size) { -#ifdef swp_is_buggy - case 1: - local_irq_save(flags); - ret = *(volatile unsigned char *)ptr; - *(volatile unsigned char *)ptr = x; - local_irq_restore(flags); - break; - - case 4: - local_irq_save(flags); - ret = *(volatile unsigned long *)ptr; - *(volatile unsigned long *)ptr = x; - local_irq_restore(flags); - break; -#else - case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]" - : "=&r" (ret) - : "r" (x), "r" (ptr) - : "memory"); - break; - case 4: __asm__ __volatile__ ("swp %0, %1, [%2]" - : "=&r" (ret) - : "r" (x), "r" (ptr) - : "memory"); - break; -#endif - default: __bad_xchg(ptr, size), ret = 0; - } - - return ret; -} - -#endif diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h deleted file mode 100644 index 445d449..0000000 --- a/include/asm-arm/processor.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * linux/include/asm-arm/processor.h - * - * Copyright (C) 1995-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_PROCESSOR_H -#define __ASM_ARM_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#define FP_SIZE 35 - -struct fp_hard_struct { - unsigned int save[FP_SIZE]; /* as yet undefined */ -}; - -struct fp_soft_struct { - unsigned int save[FP_SIZE]; /* undefined information */ -}; - -union fp_state { - struct fp_hard_struct hard; - struct fp_soft_struct soft; -}; - -typedef unsigned long mm_segment_t; /* domain register */ - -#ifdef __KERNEL__ - -#define EISA_bus 0 -#define MCA_bus 0 -#define MCA_bus__is_a_macro - -#include -#include -#if 0 /* XXX###XXX */ -#include -#endif /* XXX###XXX */ -#include -#include - -union debug_insn { - u32 arm; - u16 thumb; -}; - -struct debug_entry { - u32 address; - union debug_insn insn; -}; - -struct debug_info { - int nsaved; - struct debug_entry bp[2]; -}; - -struct thread_struct { - atomic_t refcount; - /* fault info */ - unsigned long address; - unsigned long trap_no; - unsigned long error_code; - /* floating point */ - union fp_state fpstate; - /* debugging */ - struct debug_info debug; - /* context info */ - struct context_save_struct *save; - EXTRA_THREAD_STRUCT -}; - -#define INIT_THREAD { \ - refcount: ATOMIC_INIT(1), \ - EXTRA_THREAD_STRUCT_INIT \ -} - -/* - * Return saved PC of a blocked thread. - */ -static inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - return t->save ? pc_pointer(t->save->pc) : 0; -} - -static inline unsigned long thread_saved_fp(struct thread_struct *t) -{ - return t->save ? t->save->fp : 0; -} - -/* Forward declaration, a strange C thing */ -struct task_struct; - -/* Free all resources held by a thread. */ -extern void release_thread(struct task_struct *); - -/* Copy and release all segment info associated with a VM */ -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) - -unsigned long get_wchan(struct task_struct *p); - -#define THREAD_SIZE (8192) - -extern struct task_struct *alloc_task_struct(void); -extern void __free_task_struct(struct task_struct *); -#define get_task_struct(p) atomic_inc(&(p)->thread.refcount) -#define free_task_struct(p) \ - do { \ - if (atomic_dec_and_test(&(p)->thread.refcount)) \ - __free_task_struct((p)); \ - } while (0) - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -#define cpu_relax() barrier() - -/* - * Create a new kernel thread - */ -extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -#endif - -#endif /* __ASM_ARM_PROCESSOR_H */ diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h deleted file mode 100644 index 73c9087..0000000 --- a/include/asm-arm/ptrace.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_ARM_PTRACE_H -#define __ASM_ARM_PTRACE_H - -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 - -#define PTRACE_SETOPTIONS 21 - -/* options set using PTRACE_SETOPTIONS */ -#define PTRACE_O_TRACESYSGOOD 0x00000001 - -#include - -#ifndef __ASSEMBLY__ -#define pc_pointer(v) \ - ((v) & ~PCMASK) - -#define instruction_pointer(regs) \ - (pc_pointer((regs)->ARM_pc)) - -#ifdef __KERNEL__ -extern void show_regs(struct pt_regs *); - -#define predicate(x) (x & 0xf0000000) -#define PREDICATE_ALWAYS 0xe0000000 - -#endif - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h deleted file mode 100644 index 89df4dc..0000000 --- a/include/asm-arm/setup.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * linux/include/asm/setup.h - * - * Copyright (C) 1997-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Structure passed to kernel to tell it about the - * hardware it's running on. See linux/Documentation/arm/Setup - * for more info. - * - * NOTE: - * This file contains two ways to pass information from the boot - * loader to the kernel. The old struct param_struct is deprecated, - * but it will be kept in the kernel for 5 years from now - * (2001). This will allow boot loaders to convert to the new struct - * tag way. - */ -#ifndef __ASMARM_SETUP_H -#define __ASMARM_SETUP_H - -/* - * Usage: - * - do not go blindly adding fields, add them at the end - * - when adding fields, don't rely on the address until - * a patch from me has been released - * - unused fields should be zero (for future expansion) - * - this structure is relatively short-lived - only - * guaranteed to contain useful data in setup_arch() - */ -#define COMMAND_LINE_SIZE 1024 - -/* This is the old deprecated way to pass parameters to the kernel */ -struct param_struct { - union { - struct { - unsigned long page_size; /* 0 */ - unsigned long nr_pages; /* 4 */ - unsigned long ramdisk_size; /* 8 */ - unsigned long flags; /* 12 */ -#define FLAG_READONLY 1 -#define FLAG_RDLOAD 4 -#define FLAG_RDPROMPT 8 - unsigned long rootdev; /* 16 */ - unsigned long video_num_cols; /* 20 */ - unsigned long video_num_rows; /* 24 */ - unsigned long video_x; /* 28 */ - unsigned long video_y; /* 32 */ - unsigned long memc_control_reg; /* 36 */ - unsigned char sounddefault; /* 40 */ - unsigned char adfsdrives; /* 41 */ - unsigned char bytes_per_char_h; /* 42 */ - unsigned char bytes_per_char_v; /* 43 */ - unsigned long pages_in_bank[4]; /* 44 */ - unsigned long pages_in_vram; /* 60 */ - unsigned long initrd_start; /* 64 */ - unsigned long initrd_size; /* 68 */ - unsigned long rd_start; /* 72 */ - unsigned long system_rev; /* 76 */ - unsigned long system_serial_low; /* 80 */ - unsigned long system_serial_high; /* 84 */ - unsigned long mem_fclk_21285; /* 88 */ - } s; - char unused[256]; - } u1; - union { - char paths[8][128]; - struct { - unsigned long magic; - char n[1024 - sizeof(unsigned long)]; - } s; - } u2; - char commandline[COMMAND_LINE_SIZE]; -}; - - -/* - * The new way of passing information: a list of tagged entries - */ - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; /* bit 0 = read-only */ - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 - -struct tag_mem32 { - u32 size; - u32 start; /* physical start address */ -}; - -/* VGA text type displays */ -#define ATAG_VIDEOTEXT 0x54410003 - -struct tag_videotext { - u8 x; - u8 y; - u16 video_page; - u8 video_mode; - u8 video_cols; - u16 video_ega_bx; - u8 video_lines; - u8 video_isvga; - u16 video_points; -}; - -/* describes how the ramdisk will be used in kernel */ -#define ATAG_RAMDISK 0x54410004 - -struct tag_ramdisk { - u32 flags; /* bit 0 = load, bit 1 = prompt */ - u32 size; /* decompressed ramdisk size in _kilo_ bytes */ - u32 start; /* starting block of floppy-based RAM disk image */ -}; - -/* describes where the compressed ramdisk image lives (virtual address) */ -/* - * this one accidentally used virtual addresses - as such, - * its depreciated. - */ -#define ATAG_INITRD 0x54410005 - -/* describes where the compressed ramdisk image lives (physical address) */ -#define ATAG_INITRD2 0x54420005 - -struct tag_initrd { - u32 start; /* physical start address */ - u32 size; /* size of compressed ramdisk image in bytes */ -}; - -/* board serial number. "64 bits should be enough for everybody" */ -#define ATAG_SERIAL 0x54410006 - -struct tag_serialnr { - u32 low; - u32 high; -}; - -/* board revision */ -#define ATAG_REVISION 0x54410007 - -struct tag_revision { - u32 rev; -}; - -/* initial values for vesafb-type framebuffers. see struct screen_info - * in include/linux/tty.h - */ -#define ATAG_VIDEOLFB 0x54410008 - -struct tag_videolfb { - u16 lfb_width; - u16 lfb_height; - u16 lfb_depth; - u16 lfb_linelength; - u32 lfb_base; - u32 lfb_size; - u8 red_size; - u8 red_pos; - u8 green_size; - u8 green_pos; - u8 blue_size; - u8 blue_pos; - u8 rsvd_size; - u8 rsvd_pos; -}; - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410009 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* acorn RiscPC specific information */ -#define ATAG_ACORN 0x41000101 - -struct tag_acorn { - u32 memc_control_reg; - u32 vram_pages; - u8 sounddefault; - u8 adfsdrives; -}; - -/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ -#define ATAG_MEMCLK 0x41000402 - -struct tag_memclk { - u32 fmemclk; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem32 mem; - struct tag_videotext videotext; - struct tag_ramdisk ramdisk; - struct tag_initrd initrd; - struct tag_serialnr serialnr; - struct tag_revision revision; - struct tag_videolfb videolfb; - struct tag_cmdline cmdline; - - /* - * Acorn specific - */ - struct tag_acorn acorn; - - /* - * DC21285 specific - */ - struct tag_memclk memclk; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(const struct tag *); -}; - -#define __tag __attribute__((unused, __section__(".taglist"))) -#define __tagtable(tag, fn) \ -static struct tagtable __tagtable_##fn __tag = { tag, fn } - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -/* - * Memory map description - */ -#define NR_BANKS 8 - -struct meminfo { - int nr_banks; - unsigned long end; - struct { - unsigned long start; - unsigned long size; - int node; - } bank[NR_BANKS]; -}; - -extern struct meminfo meminfo; - -#endif diff --git a/include/asm-arm/sizes.h b/include/asm-arm/sizes.h deleted file mode 100644 index f8d92ca..0000000 --- a/include/asm-arm/sizes.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ diff --git a/include/asm-arm/string.h b/include/asm-arm/string.h deleted file mode 100644 index c3ea582..0000000 --- a/include/asm-arm/string.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef __ASM_ARM_STRING_H -#define __ASM_ARM_STRING_H - -/* - * We don't do inline string functions, since the - * optimised inline asm versions are not small. - */ - -#undef __HAVE_ARCH_STRRCHR -extern char * strrchr(const char * s, int c); - -#undef __HAVE_ARCH_STRCHR -extern char * strchr(const char * s, int c); - -#undef __HAVE_ARCH_MEMCPY -extern void * memcpy(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMMOVE -extern void * memmove(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMCHR -extern void * memchr(const void *, int, __kernel_size_t); - -#undef __HAVE_ARCH_MEMZERO -#undef __HAVE_ARCH_MEMSET -extern void * memset(void *, int, __kernel_size_t); - -#if 0 -extern void __memzero(void *ptr, __kernel_size_t n); - -#define memset(p,v,n) \ - ({ \ - if ((n) != 0) { \ - if (__builtin_constant_p((v)) && (v) == 0) \ - __memzero((p),(n)); \ - else \ - memset((p),(v),(n)); \ - } \ - (p); \ - }) - -#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) -#else -extern void memzero(void *ptr, __kernel_size_t n); -#endif - -#endif diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h deleted file mode 100644 index 2b28a26..0000000 --- a/include/asm-arm/system.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef __ASM_ARM_SYSTEM_H -#define __ASM_ARM_SYSTEM_H - -#ifdef __KERNEL__ - -#define CPU_ARCH_UNKNOWN 0 -#define CPU_ARCH_ARMv3 1 -#define CPU_ARCH_ARMv4 2 -#define CPU_ARCH_ARMv4T 3 -#define CPU_ARCH_ARMv5 4 -#define CPU_ARCH_ARMv5T 5 -#define CPU_ARCH_ARMv5TE 6 -#define CPU_ARCH_ARMv5TEJ 7 -#define CPU_ARCH_ARMv6 8 -#define CPU_ARCH_ARMv7 9 - -/* - * CR1 bits (CP#15 CR1) - */ -#define CR_M (1 << 0) /* MMU enable */ -#define CR_A (1 << 1) /* Alignment abort enable */ -#define CR_C (1 << 2) /* Dcache enable */ -#define CR_W (1 << 3) /* Write buffer enable */ -#define CR_P (1 << 4) /* 32-bit exception handler */ -#define CR_D (1 << 5) /* 32-bit data address range */ -#define CR_L (1 << 6) /* Implementation defined */ -#define CR_B (1 << 7) /* Big endian */ -#define CR_S (1 << 8) /* System MMU protection */ -#define CR_R (1 << 9) /* ROM MMU protection */ -#define CR_F (1 << 10) /* Implementation defined */ -#define CR_Z (1 << 11) /* Implementation defined */ -#define CR_I (1 << 12) /* Icache enable */ -#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ -#define CR_RR (1 << 14) /* Round Robin cache replacement */ -#define CR_L4 (1 << 15) /* LDR pc can set T bit */ -#define CR_DT (1 << 16) -#define CR_IT (1 << 18) -#define CR_ST (1 << 19) -#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ -#define CR_U (1 << 22) /* Unaligned access operation */ -#define CR_XP (1 << 23) /* Extended page tables */ -#define CR_VE (1 << 24) /* Vectored interrupts */ -#define CR_EE (1 << 25) /* Exception (Big) Endian */ -#define CR_TRE (1 << 28) /* TEX remap enable */ -#define CR_AFE (1 << 29) /* Access flag enable */ -#define CR_TE (1 << 30) /* Thumb exception enable */ - -/* - * This is used to ensure the compiler did actually allocate the register we - * asked it for some inline assembly sequences. Apparently we can't trust - * the compiler from one version to another so a bit of paranoia won't hurt. - * This string is meant to be concatenated with the inline asm string and - * will cause compilation to stop on mismatch. - * (for details, see gcc PR 15089) - */ -#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" - -#ifndef __ASSEMBLY__ - -#define isb() __asm__ __volatile__ ("" : : : "memory") - -#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); - -static inline unsigned int get_cr(void) -{ - unsigned int val; - asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); - return val; -} - -static inline void set_cr(unsigned int val) -{ - asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" - : : "r" (val) : "cc"); - isb(); -} - -#endif /* __ASSEMBLY__ */ - -#define arch_align_stack(x) (x) - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h deleted file mode 100644 index 71dc049..0000000 --- a/include/asm-arm/types.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef __ASM_ARM_TYPES_H -#define __ASM_ARM_TYPES_H - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h deleted file mode 100644 index 6d2f8bc..0000000 --- a/include/asm-arm/u-boot-arm.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _U_BOOT_ARM_H_ -#define _U_BOOT_ARM_H_ 1 - -/* for the following variables, see start.S */ -extern ulong _armboot_start; /* code start */ -extern ulong _bss_start; /* code + data end == BSS start */ -extern ulong _bss_end; /* BSS end */ -extern ulong IRQ_STACK_START; /* top of IRQ stack */ -extern ulong FIQ_STACK_START; /* top of FIQ stack */ - -/* cpu/.../cpu.c */ -int cpu_init(void); -int cleanup_before_linux(void); - -/* cpu/.../arch/cpu.c */ -int arch_cpu_init(void); -int arch_misc_init(void); - -/* board/.../... */ -int board_init(void); -int dram_init (void); -void setup_serial_tag (struct tag **params); -void setup_revision_tag (struct tag **params); - -/* ------------------------------------------------------------ */ -/* Here is a list of some prototypes which are incompatible to */ -/* the U-Boot implementation */ -/* To be fixed! */ -/* ------------------------------------------------------------ */ -/* common/cmd_nvedit.c */ -int setenv (char *, char *); - -/* cpu/.../interrupt.c */ -int arch_interrupt_init (void); -void reset_timer_masked (void); -ulong get_timer_masked (void); -void udelay_masked (unsigned long usec); - -/* cpu/.../timer.c */ -int timer_init (void); - -#endif /* _U_BOOT_ARM_H_ */ diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h deleted file mode 100644 index cfd5a9b..0000000 --- a/include/asm-arm/u-boot.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef _U_BOOT_H_ -#define _U_BOOT_H_ 1 - -typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ - unsigned long bi_ip_addr; /* IP Address */ - struct environment_s *bi_env; - ulong bi_arch_number; /* unique id for this board */ - ulong bi_boot_params; /* where this board expects params */ - struct /* RAM configuration */ - { - ulong start; - ulong size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; -} bd_t; - -#define bi_env_data bi_env->data -#define bi_env_crc bi_env->crc - -#endif /* _U_BOOT_H_ */ diff --git a/include/asm-arm/unaligned.h b/include/asm-arm/unaligned.h deleted file mode 100644 index 44593a8..0000000 --- a/include/asm-arm/unaligned.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _ASM_ARM_UNALIGNED_H -#define _ASM_ARM_UNALIGNED_H - -#include -#include -#include - -/* - * Select endianness - */ -#ifndef __ARMEB__ -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#else -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#endif - -#endif /* _ASM_ARM_UNALIGNED_H */ diff --git a/include/asm-avr32/arch-at32ap700x/addrspace.h b/include/asm-avr32/arch-at32ap700x/addrspace.h deleted file mode 100644 index 409eee3..0000000 --- a/include/asm-avr32/arch-at32ap700x/addrspace.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ADDRSPACE_H -#define __ASM_AVR32_ADDRSPACE_H - -#include - -/* Memory segments when segmentation is enabled */ -#define P0SEG 0x00000000 -#define P1SEG 0x80000000 -#define P2SEG 0xa0000000 -#define P3SEG 0xc0000000 -#define P4SEG 0xe0000000 - -/* Returns the privileged segment base of a given address */ -#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) - -/* Returns the physical address of a PnSEG (n=1,2) address */ -#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) - -/* - * Map an address to a certain privileged segment - */ -#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) -#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) -#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) -#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) - -/* virt_to_phys will only work when address is in P1 or P2 */ -static inline unsigned long virt_to_phys(volatile void *address) -{ - return PHYSADDR(address); -} - -static inline void * phys_to_virt(unsigned long address) -{ - return (void *)P1SEGADDR(address); -} - -#define cached(addr) ((void *)P1SEGADDR(addr)) -#define uncached(addr) ((void *)P2SEGADDR(addr)) - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - * - * This implementation works for memory below 512MiB (flash, etc.) as - * well as above 3.5GiB (internal peripherals.) - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (1 << 7) -#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) -#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0)) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - if (flags == MAP_WRBACK) - return (void *)P1SEGADDR(paddr); - else - return (void *)P2SEGADDR(paddr); -} - -#endif /* __ASM_AVR32_ADDRSPACE_H */ diff --git a/include/asm-avr32/arch-at32ap700x/cacheflush.h b/include/asm-avr32/arch-at32ap700x/cacheflush.h deleted file mode 100644 index 929f68e..0000000 --- a/include/asm-avr32/arch-at32ap700x/cacheflush.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_CACHEFLUSH_H -#define __ASM_AVR32_CACHEFLUSH_H - -/* - * Invalidate any cacheline containing virtual address vaddr without - * writing anything back to memory. - * - * Note that this function may corrupt unrelated data structures when - * applied on buffers that are not cacheline aligned in both ends. - */ -static inline void dcache_invalidate_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory"); -} - -/* - * Make sure any cacheline containing virtual address vaddr is written - * to memory. - */ -static inline void dcache_clean_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory"); -} - -/* - * Make sure any cacheline containing virtual address vaddr is written - * to memory and then invalidate it. - */ -static inline void dcache_flush_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory"); -} - -/* - * Invalidate any instruction cacheline containing virtual address - * vaddr. - */ -static inline void icache_invalidate_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory"); -} - -/* - * Applies the above functions on all lines that are touched by the - * specified virtual address range. - */ -void dcache_invalidate_range(volatile void *start, size_t len); -void dcache_clean_range(volatile void *start, size_t len); -void dcache_flush_range(volatile void *start, size_t len); -void icache_invalidate_range(volatile void *start, size_t len); - -static inline void dcache_flush_unlocked(void) -{ - asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory"); -} - -/* - * Make sure any pending writes are completed before continuing. - */ -#define sync_write_buffer() asm volatile("sync 0" : : : "memory") - -#endif /* __ASM_AVR32_CACHEFLUSH_H */ diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h deleted file mode 100644 index 40a2476..0000000 --- a/include/asm-avr32/arch-at32ap700x/chip-features.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2007 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__ -#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__ - -/* Currently, all the AP700x chips have these */ -#define AT32AP700x_CHIP_HAS_USART -#define AT32AP700x_CHIP_HAS_MMCI -#define AT32AP700x_CHIP_HAS_SPI - -/* Only AP7000 has ethernet interface */ -#ifdef CONFIG_AT32AP7000 -#define AT32AP700x_CHIP_HAS_MACB -#endif - -/* AP7000 and AP7002 have LCD controller, but AP7001 does not */ -#if defined(CONFIG_AT32AP7000) || defined(CONFIG_AT32AP7002) -#define AT32AP700x_CHIP_HAS_LCDC -#endif - -#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h deleted file mode 100644 index 7a0b655..0000000 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ARCH_CLK_H__ -#define __ASM_AVR32_ARCH_CLK_H__ - -#include -#include - -#ifdef CONFIG_PLL -#define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \ - * CONFIG_SYS_PLL0_MUL) -#define MAIN_CLK_RATE PLL0_RATE -#else -#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ) -#endif - -static inline unsigned long get_cpu_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU; -} -static inline unsigned long get_hsb_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB; -} -static inline unsigned long get_pba_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA; -} -static inline unsigned long get_pbb_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB; -} - -/* Accessors for specific devices. More will be added as needed. */ -static inline unsigned long get_sdram_clk_rate(void) -{ - return get_hsb_clk_rate(); -} -#ifdef AT32AP700x_CHIP_HAS_USART -static inline unsigned long get_usart_clk_rate(unsigned int dev_id) -{ - return get_pba_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_MACB -static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) -{ - return get_pbb_clk_rate(); -} -static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) -{ - return get_hsb_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_MMCI -static inline unsigned long get_mci_clk_rate(void) -{ - return get_pbb_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_SPI -static inline unsigned long get_spi_clk_rate(unsigned int dev_id) -{ - return get_pba_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_LCDC -static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) -{ - return get_hsb_clk_rate(); -} -#endif - -extern void clk_init(void); - -/* Board code may need the SDRAM base clock as a compile-time constant */ -#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB) - -/* Generic clock control */ -enum gclk_parent { - GCLK_PARENT_OSC0 = 0, - GCLK_PARENT_OSC1 = 1, - GCLK_PARENT_PLL0 = 2, - GCLK_PARENT_PLL1 = 3, -}; - -/* Some generic clocks have specific roles */ -#define GCLK_DAC_SAMPLE_CLK 6 -#define GCLK_LCDC_PIXCLK 7 - -extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, - unsigned long rate, unsigned long parent_rate); - -/** - * gclk_set_rate - configure and enable a generic clock - * @id: Which GCLK[id] to enable - * @parent: Parent clock feeding the GCLK - * @rate: Target rate of the GCLK in Hz - * - * Returns the actual GCLK rate in Hz, after rounding to the nearest - * supported rate. - * - * All three parameters are usually constant, hence the inline. - */ -static inline unsigned long gclk_set_rate(unsigned int id, - enum gclk_parent parent, unsigned long rate) -{ - unsigned long parent_rate; - - if (id > 7) - return 0; - - switch (parent) { - case GCLK_PARENT_OSC0: - parent_rate = CONFIG_SYS_OSC0_HZ; - break; -#ifdef CONFIG_SYS_OSC1_HZ - case GCLK_PARENT_OSC1: - parent_rate = CONFIG_SYS_OSC1_HZ; - break; -#endif -#ifdef PLL0_RATE - case GCLK_PARENT_PLL0: - parent_rate = PLL0_RATE; - break; -#endif -#ifdef PLL1_RATE - case GCLK_PARENT_PLL1: - parent_rate = PLL1_RATE; - break; -#endif - default: - parent_rate = 0; - break; - } - - return __gclk_set_rate(id, parent, rate, parent_rate); -} - -/** - * gclk_enable_output - enable output on a GCLK pin - * @id: Which GCLK[id] pin to enable - * @drive_strength: Drive strength of external GCLK pin, if applicable - */ -static inline void gclk_enable_output(unsigned int id, - unsigned long drive_strength) -{ - switch (id) { - case 0: - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, - PORTMUX_FUNC_A, drive_strength); - break; - case 1: - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31, - PORTMUX_FUNC_A, drive_strength); - break; - case 2: - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19, - PORTMUX_FUNC_A, drive_strength); - break; - case 3: - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29, - PORTMUX_FUNC_A, drive_strength); - break; - case 4: - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30, - PORTMUX_FUNC_A, drive_strength); - break; - } -} - -#endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/gpio-impl.h b/include/asm-avr32/arch-at32ap700x/gpio-impl.h deleted file mode 100644 index 8801bd0..0000000 --- a/include/asm-avr32/arch-at32ap700x/gpio-impl.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__ -#define __ASM_AVR32_ARCH_GPIO_IMPL_H__ - -/* Register offsets */ -struct gpio_regs { - u32 GPER; - u32 GPERS; - u32 GPERC; - u32 GPERT; - u32 PMR0; - u32 PMR0S; - u32 PMR0C; - u32 PMR0T; - u32 PMR1; - u32 PMR1S; - u32 PMR1C; - u32 PMR1T; - u32 __reserved0[4]; - u32 ODER; - u32 ODERS; - u32 ODERC; - u32 ODERT; - u32 OVR; - u32 OVRS; - u32 OVRC; - u32 OVRT; - u32 PVR; - u32 __reserved_PVRS; - u32 __reserved_PVRC; - u32 __reserved_PVRT; - u32 PUER; - u32 PUERS; - u32 PUERC; - u32 PUERT; - u32 PDER; - u32 PDERS; - u32 PDERC; - u32 PDERT; - u32 IER; - u32 IERS; - u32 IERC; - u32 IERT; - u32 IMR0; - u32 IMR0S; - u32 IMR0C; - u32 IMR0T; - u32 IMR1; - u32 IMR1S; - u32 IMR1C; - u32 IMR1T; - u32 GFER; - u32 GFERS; - u32 GFERC; - u32 GFERT; - u32 IFR; - u32 __reserved_IFRS; - u32 IFRC; - u32 __reserved_IFRT; - u32 ODMER; - u32 ODMERS; - u32 ODMERC; - u32 ODMERT; - u32 __reserved1[4]; - u32 ODCR0; - u32 ODCR0S; - u32 ODCR0C; - u32 ODCR0T; - u32 ODCR1; - u32 ODCR1S; - u32 ODCR1C; - u32 ODCR1T; - u32 __reserved2[4]; - u32 OSRR0; - u32 OSRR0S; - u32 OSRR0C; - u32 OSRR0T; - u32 __reserved3[8]; - u32 STER; - u32 STERS; - u32 STERC; - u32 STERT; - u32 __reserved4[35]; - u32 VERSION; -}; - -#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h deleted file mode 100644 index 303e353..0000000 --- a/include/asm-avr32/arch-at32ap700x/gpio.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ARCH_GPIO_H__ -#define __ASM_AVR32_ARCH_GPIO_H__ - -#include -#include - -#define NR_GPIO_CONTROLLERS 5 - -/* - * Pin numbers identifying specific GPIO pins on the chip. - */ -#define GPIO_PIOA_BASE (0) -#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) -#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) -#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) -#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) -#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x)) -#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x)) -#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x)) -#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x)) -#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x)) - -static inline void *pio_pin_to_port(unsigned int pin) -{ - switch (pin >> 5) { - case 0: - return (void *)PIOA_BASE; - case 1: - return (void *)PIOB_BASE; - case 2: - return (void *)PIOC_BASE; - case 3: - return (void *)PIOD_BASE; - case 4: - return (void *)PIOE_BASE; - default: - return NULL; - } -} - -#include - -#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix.h b/include/asm-avr32/arch-at32ap700x/hmatrix.h deleted file mode 100644 index d6b6263..0000000 --- a/include/asm-avr32/arch-at32ap700x/hmatrix.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ARCH_HMATRIX_H__ -#define __ASM_AVR32_ARCH_HMATRIX_H__ - -#include - -/* Bitfields in SFR4 (EBI) */ -#define HMATRIX_EBI_SDRAM_ENABLE_OFFSET 1 -#define HMATRIX_EBI_SDRAM_ENABLE_SIZE 1 -#define HMATRIX_EBI_NAND_ENABLE_OFFSET 3 -#define HMATRIX_EBI_NAND_ENABLE_SIZE 1 -#define HMATRIX_EBI_CF0_ENABLE_OFFSET 4 -#define HMATRIX_EBI_CF0_ENABLE_SIZE 1 -#define HMATRIX_EBI_CF1_ENABLE_OFFSET 5 -#define HMATRIX_EBI_CF1_ENABLE_SIZE 1 -#define HMATRIX_EBI_PULLUP_DISABLE_OFFSET 8 -#define HMATRIX_EBI_PULLUP_DISABLE_SIZE 1 - -/* HSB masters */ -#define HMATRIX_MASTER_CPU_DCACHE 0 -#define HMATRIX_MASTER_CPU_ICACHE 1 -#define HMATRIX_MASTER_PDC 2 -#define HMATRIX_MASTER_ISI 3 -#define HMATRIX_MASTER_USBA 4 -#define HMATRIX_MASTER_LCDC 5 -#define HMATRIX_MASTER_MACB0 6 -#define HMATRIX_MASTER_MACB1 7 -#define HMATRIX_MASTER_DMACA_M0 8 -#define HMATRIX_MASTER_DMACA_M1 9 - -/* HSB slaves */ -#define HMATRIX_SLAVE_SRAM0 0 -#define HMATRIX_SLAVE_SRAM1 1 -#define HMATRIX_SLAVE_PBA 2 -#define HMATRIX_SLAVE_PBB 3 -#define HMATRIX_SLAVE_EBI 4 -#define HMATRIX_SLAVE_USBA 5 -#define HMATRIX_SLAVE_LCDC 6 -#define HMATRIX_SLAVE_DMACA 7 - -#endif /* __ASM_AVR32_ARCH_HMATRIX_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h deleted file mode 100644 index 6592c03..0000000 --- a/include/asm-avr32/arch-at32ap700x/memory-map.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __AT32AP7000_MEMORY_MAP_H__ -#define __AT32AP7000_MEMORY_MAP_H__ - -/* Internal and external memories */ -#define EBI_SRAM_CS0_BASE 0x00000000 -#define EBI_SRAM_CS0_SIZE 0x04000000 -#define EBI_SRAM_CS4_BASE 0x04000000 -#define EBI_SRAM_CS4_SIZE 0x04000000 -#define EBI_SRAM_CS2_BASE 0x08000000 -#define EBI_SRAM_CS2_SIZE 0x04000000 -#define EBI_SRAM_CS3_BASE 0x0c000000 -#define EBI_SRAM_CS3_SIZE 0x04000000 -#define EBI_SRAM_CS1_BASE 0x10000000 -#define EBI_SRAM_CS1_SIZE 0x10000000 -#define EBI_SRAM_CS5_BASE 0x20000000 -#define EBI_SRAM_CS5_SIZE 0x04000000 - -#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE -#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE - -#define INTERNAL_SRAM_BASE 0x24000000 -#define INTERNAL_SRAM_SIZE 0x00008000 - -/* Devices on the High Speed Bus (HSB) */ -#define LCDC_BASE 0xFF000000 -#define DMAC_BASE 0xFF200000 -#define USB_FIFO 0xFF300000 - -/* Devices on Peripheral Bus A (PBA) */ -#define SPI0_BASE 0xFFE00000 -#define SPI1_BASE 0xFFE00400 -#define TWI_BASE 0xFFE00800 -#define USART0_BASE 0xFFE00C00 -#define USART1_BASE 0xFFE01000 -#define USART2_BASE 0xFFE01400 -#define USART3_BASE 0xFFE01800 -#define SSC0_BASE 0xFFE01C00 -#define SSC1_BASE 0xFFE02000 -#define SSC2_BASE 0xFFE02400 -#define PIOA_BASE 0xFFE02800 -#define PIOB_BASE 0xFFE02C00 -#define PIOC_BASE 0xFFE03000 -#define PIOD_BASE 0xFFE03400 -#define PIOE_BASE 0xFFE03800 -#define PSIF_BASE 0xFFE03C00 - -/* Devices on Peripheral Bus B (PBB) */ -#define SM_BASE 0xFFF00000 -#define INTC_BASE 0xFFF00400 -#define HMATRIX_BASE 0xFFF00800 -#define TIMER0_BASE 0xFFF00C00 -#define TIMER1_BASE 0xFFF01000 -#define PWM_BASE 0xFFF01400 -#define MACB0_BASE 0xFFF01800 -#define MACB1_BASE 0xFFF01C00 -#define DAC_BASE 0xFFF02000 -#define MMCI_BASE 0xFFF02400 -#define AUDIOC_BASE 0xFFF02800 -#define HISI_BASE 0xFFF02C00 -#define USB_BASE 0xFFF03000 -#define HSMC_BASE 0xFFF03400 -#define HSDRAMC_BASE 0xFFF03800 -#define ECC_BASE 0xFFF03C00 - -#endif /* __AT32AP7000_MEMORY_MAP_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/portmux.h b/include/asm-avr32/arch-at32ap700x/portmux.h deleted file mode 100644 index 1ba52e5..0000000 --- a/include/asm-avr32/arch-at32ap700x/portmux.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ARCH_PORTMUX_H__ -#define __ASM_AVR32_ARCH_PORTMUX_H__ - -#include - -#define PORTMUX_PORT_A ((void *)PIOA_BASE) -#define PORTMUX_PORT_B ((void *)PIOB_BASE) -#define PORTMUX_PORT_C ((void *)PIOC_BASE) -#define PORTMUX_PORT_D ((void *)PIOD_BASE) -#define PORTMUX_PORT_E ((void *)PIOE_BASE) - -void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, - unsigned long flags, unsigned long drive_strength); - -#define PORTMUX_EBI_CS(x) (1 << (x)) -#define PORTMUX_EBI_NAND (1 << 6) -#define PORTMUX_EBI_CF(x) (1 << ((x) + 7)) -#define PORTMUX_EBI_NWAIT (1 << 9) - -#ifdef AT32AP700x_CHIP_HAS_USART -static inline void portmux_enable_usart0(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9), - PORTMUX_FUNC_B, 0); -} - -static inline void portmux_enable_usart1(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18), - PORTMUX_FUNC_A, 0); -} - -static inline void portmux_enable_usart2(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27), - PORTMUX_FUNC_B, 0); -} - -static inline void portmux_enable_usart3(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18), - PORTMUX_FUNC_B, 0); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_MACB -void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength); -void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength); - -#define PORTMUX_MACB_RMII (0) -#define PORTMUX_MACB_MII (1 << 0) -#define PORTMUX_MACB_SPEED (1 << 1) - -#endif -#ifdef AT32AP700x_CHIP_HAS_MMCI -void portmux_enable_mmci(unsigned int slot, unsigned long flags, - unsigned long drive_strength); - -#define PORTMUX_MMCI_4BIT (1 << 0) -#define PORTMUX_MMCI_8BIT (PORTMUX_MMCI_4BIT | (1 << 1)) -#define PORTMUX_MMCI_EXT_PULLUP (1 << 2) - -#endif -#ifdef AT32AP700x_CHIP_HAS_SPI -void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength); -void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength); -#endif -#ifdef AT32AP700x_CHIP_HAS_LCDC -void portmux_enable_lcdc(int pin_config); -#endif - -#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */ diff --git a/include/asm-avr32/arch-common/portmux-gpio.h b/include/asm-avr32/arch-common/portmux-gpio.h deleted file mode 100644 index 1306cbe..0000000 --- a/include/asm-avr32/arch-common/portmux-gpio.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __AVR32_PORTMUX_GPIO_H__ -#define __AVR32_PORTMUX_GPIO_H__ - -#include - -/* Register layout for this specific device */ -#include - -/* Register access macros */ -#define gpio_readl(port, reg) \ - __raw_readl(&((struct gpio_regs *)port)->reg) -#define gpio_writel(gpio, reg, value) \ - __raw_writel(value, &((struct gpio_regs *)port)->reg) - -/* Portmux API starts here. See doc/README.AVR32-port-muxing */ - -enum portmux_function { - PORTMUX_FUNC_A, - PORTMUX_FUNC_B, - PORTMUX_FUNC_C, - PORTMUX_FUNC_D, -}; - -#define PORTMUX_DIR_INPUT (0 << 0) -#define PORTMUX_DIR_OUTPUT (1 << 0) -#define PORTMUX_INIT_LOW (0 << 1) -#define PORTMUX_INIT_HIGH (1 << 1) -#define PORTMUX_PULL_UP (1 << 2) -#define PORTMUX_PULL_DOWN (2 << 2) -#define PORTMUX_BUSKEEPER (3 << 2) -#define PORTMUX_DRIVE_MIN (0 << 4) -#define PORTMUX_DRIVE_LOW (1 << 4) -#define PORTMUX_DRIVE_HIGH (2 << 4) -#define PORTMUX_DRIVE_MAX (3 << 4) -#define PORTMUX_OPEN_DRAIN (1 << 6) - -void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags); -void portmux_select_gpio(void *port, unsigned long pin_mask, - unsigned long flags); - -/* Internal helper functions */ - -static inline void *gpio_pin_to_port(unsigned int pin) -{ - return (void *)GPIO_BASE + (pin >> 5) * 0x200; -} - -static inline void __gpio_set_output_value(void *port, unsigned int pin, - int value) -{ - if (value) - gpio_writel(port, OVRS, 1 << pin); - else - gpio_writel(port, OVRC, 1 << pin); -} - -static inline int __gpio_get_input_value(void *port, unsigned int pin) -{ - return (gpio_readl(port, PVR) >> pin) & 1; -} - -void gpio_set_output_value(unsigned int pin, int value); -int gpio_get_input_value(unsigned int pin); - -/* GPIO API starts here */ - -/* - * GCC doesn't realize that the constant case is extremely trivial, - * so we need to help it make the right decision by using - * always_inline. - */ -__attribute__((always_inline)) -static inline void gpio_set_value(unsigned int pin, int value) -{ - if (__builtin_constant_p(pin)) - __gpio_set_output_value(gpio_pin_to_port(pin), - pin & 0x1f, value); - else - gpio_set_output_value(pin, value); -} - -__attribute__((always_inline)) -static inline int gpio_get_value(unsigned int pin) -{ - if (__builtin_constant_p(pin)) - return __gpio_get_input_value(gpio_pin_to_port(pin), - pin & 0x1f); - else - return gpio_get_input_value(pin); -} - -#endif /* __AVR32_PORTMUX_GPIO_H__ */ diff --git a/include/asm-avr32/arch-common/portmux-pio.h b/include/asm-avr32/arch-common/portmux-pio.h deleted file mode 100644 index 1abe5be..0000000 --- a/include/asm-avr32/arch-common/portmux-pio.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __AVR32_PORTMUX_PIO_H__ -#define __AVR32_PORTMUX_PIO_H__ - -#include - -/* PIO register offsets */ -#define PIO_PER 0x0000 -#define PIO_PDR 0x0004 -#define PIO_PSR 0x0008 -#define PIO_OER 0x0010 -#define PIO_ODR 0x0014 -#define PIO_OSR 0x0018 -#define PIO_IFER 0x0020 -#define PIO_IFDR 0x0024 -#define PIO_ISFR 0x0028 -#define PIO_SODR 0x0030 -#define PIO_CODR 0x0034 -#define PIO_ODSR 0x0038 -#define PIO_PDSR 0x003c -#define PIO_IER 0x0040 -#define PIO_IDR 0x0044 -#define PIO_IMR 0x0048 -#define PIO_ISR 0x004c -#define PIO_MDER 0x0050 -#define PIO_MDDR 0x0054 -#define PIO_MDSR 0x0058 -#define PIO_PUDR 0x0060 -#define PIO_PUER 0x0064 -#define PIO_PUSR 0x0068 -#define PIO_ASR 0x0070 -#define PIO_BSR 0x0074 -#define PIO_ABSR 0x0078 -#define PIO_OWER 0x00a0 -#define PIO_OWDR 0x00a4 -#define PIO_OWSR 0x00a8 - -/* Hardware register access */ -#define pio_readl(base, reg) \ - __raw_readl((void *)base + PIO_##reg) -#define pio_writel(base, reg, value) \ - __raw_writel((value), (void *)base + PIO_##reg) - -/* Portmux API starts here. See doc/README.AVR32-port-muxing */ - -enum portmux_function { - PORTMUX_FUNC_A, - PORTMUX_FUNC_B, -}; - -/* Pull-down, buskeeper and drive strength are not supported */ -#define PORTMUX_DIR_INPUT (0 << 0) -#define PORTMUX_DIR_OUTPUT (1 << 0) -#define PORTMUX_INIT_LOW (0 << 1) -#define PORTMUX_INIT_HIGH (1 << 1) -#define PORTMUX_PULL_UP (1 << 2) -#define PORTMUX_PULL_DOWN (0) -#define PORTMUX_BUSKEEPER PORTMUX_PULL_UP -#define PORTMUX_DRIVE_MIN (0) -#define PORTMUX_DRIVE_LOW (0) -#define PORTMUX_DRIVE_HIGH (0) -#define PORTMUX_DRIVE_MAX (0) -#define PORTMUX_OPEN_DRAIN (1 << 3) - -void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags); -void portmux_select_gpio(void *port, unsigned long pin_mask, - unsigned long flags); - -/* Internal helper functions */ - -static inline void __pio_set_output_value(void *port, unsigned int pin, - int value) -{ - /* - * value will usually be constant, but it's pretty cheap - * either way. - */ - if (value) - pio_writel(port, SODR, 1 << pin); - else - pio_writel(port, CODR, 1 << pin); -} - -static inline int __pio_get_input_value(void *port, unsigned int pin) -{ - return (pio_readl(port, PDSR) >> pin) & 1; -} - -void pio_set_output_value(unsigned int pin, int value); -int pio_get_input_value(unsigned int pin); - -/* GPIO API starts here */ - -/* - * GCC doesn't realize that the constant case is extremely trivial, - * so we need to help it make the right decision by using - * always_inline. - */ -__attribute__((always_inline)) -static inline void gpio_set_value(unsigned int pin, int value) -{ - if (__builtin_constant_p(pin)) - __pio_set_output_value(pio_pin_to_port(pin), pin & 0x1f, value); - else - pio_set_output_value(pin, value); -} - -__attribute__((always_inline)) -static inline int gpio_get_value(unsigned int pin) -{ - if (__builtin_constant_p(pin)) - return __pio_get_input_value(pio_pin_to_port(pin), pin & 0x1f); - else - return pio_get_input_value(pin); -} - -#endif /* __AVR32_PORTMUX_PIO_H__ */ diff --git a/include/asm-avr32/bitops.h b/include/asm-avr32/bitops.h deleted file mode 100644 index f15fd46..0000000 --- a/include/asm-avr32/bitops.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_BITOPS_H -#define __ASM_AVR32_BITOPS_H - -#endif /* __ASM_AVR32_BITOPS_H */ diff --git a/include/asm-avr32/byteorder.h b/include/asm-avr32/byteorder.h deleted file mode 100644 index 2fe867e..0000000 --- a/include/asm-avr32/byteorder.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_BYTEORDER_H -#define __ASM_AVR32_BYTEORDER_H - -#include - -#define __arch__swab32(x) __builtin_bswap_32(x) -#define __arch__swab16(x) __builtin_bswap_16(x) - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#include - -#endif /* __ASM_AVR32_BYTEORDER_H */ diff --git a/include/asm-avr32/config.h b/include/asm-avr32/config.h deleted file mode 100644 index 049c44e..0000000 --- a/include/asm-avr32/config.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -#endif diff --git a/include/asm-avr32/dma-mapping.h b/include/asm-avr32/dma-mapping.h deleted file mode 100644 index 0be7804..0000000 --- a/include/asm-avr32/dma-mapping.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_DMA_MAPPING_H -#define __ASM_AVR32_DMA_MAPPING_H - -#include -#include - -enum dma_data_direction { - DMA_BIDIRECTIONAL = 0, - DMA_TO_DEVICE = 1, - DMA_FROM_DEVICE = 2, -}; -extern void *dma_alloc_coherent(size_t len, unsigned long *handle); - -static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, - enum dma_data_direction dir) -{ - extern void __bad_dma_data_direction(void); - - switch (dir) { - case DMA_BIDIRECTIONAL: - dcache_flush_range(vaddr, len); - break; - case DMA_TO_DEVICE: - dcache_clean_range(vaddr, len); - break; - case DMA_FROM_DEVICE: - dcache_invalidate_range(vaddr, len); - break; - default: - /* This will cause a linker error */ - __bad_dma_data_direction(); - } - - return virt_to_phys(vaddr); -} - -static inline void dma_unmap_single(volatile void *vaddr, size_t len, - unsigned long paddr) -{ - -} - -#endif /* __ASM_AVR32_DMA_MAPPING_H */ diff --git a/include/asm-avr32/errno.h b/include/asm-avr32/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/include/asm-avr32/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h deleted file mode 100644 index efbdda9..0000000 --- a/include/asm-avr32/global_data.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_GLOBAL_DATA_H__ -#define __ASM_GLOBAL_DATA_H__ - -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long stack_end; /* highest stack address */ - unsigned long have_console; /* serial_init() was called */ - unsigned long reloc_off; /* Relocation Offset */ - unsigned long env_addr; /* Address of env struct */ - unsigned long env_valid; /* Checksum of env valid? */ - unsigned long cpu_hz; /* cpu core clock frequency */ -#if defined(CONFIG_LCD) - void *fb_base; /* framebuffer address */ -#endif - void **jt; /* jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5") - -#endif /* __ASM_GLOBAL_DATA_H__ */ diff --git a/include/asm-avr32/hmatrix-common.h b/include/asm-avr32/hmatrix-common.h deleted file mode 100644 index 4b7e610..0000000 --- a/include/asm-avr32/hmatrix-common.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_HMATRIX_COMMON_H__ -#define __ASM_AVR32_HMATRIX_COMMON_H__ - -/* HMATRIX register offsets */ -struct hmatrix_regs { - u32 MCFG[16]; - u32 SCFG[16]; - struct { - u32 A; - u32 B; - } PRS[16]; - u32 MRCR; - u32 __reserved[3]; - u32 SFR[16]; -}; - -/* Bitfields in MCFG */ -#define HMATRIX_ULBT_OFFSET 0 -#define HMATRIX_ULBT_SIZE 3 - -/* Bitfields in SCFG */ -#define HMATRIX_SLOT_CYCLE_OFFSET 0 -#define HMATRIX_SLOT_CYCLE_SIZE 8 -#define HMATRIX_DEFMSTR_TYPE_OFFSET 16 -#define HMATRIX_DEFMSTR_TYPE_SIZE 2 -#define HMATRIX_FIXED_DEFMSTR_OFFSET 18 -#define HMATRIX_FIXED_DEFMSTR_SIZE 4 -#define HMATRIX_ARBT_OFFSET 24 -#define HMATRIX_ARBT_SIZE 1 - -/* Bitfields in PRS.A */ -#define HMATRIX_M0PR_OFFSET 0 -#define HMATRIX_M0PR_SIZE 4 -#define HMATRIX_M1PR_OFFSET 4 -#define HMATRIX_M1PR_SIZE 4 -#define HMATRIX_M2PR_OFFSET 8 -#define HMATRIX_M2PR_SIZE 4 -#define HMATRIX_M3PR_OFFSET 12 -#define HMATRIX_M3PR_SIZE 4 -#define HMATRIX_M4PR_OFFSET 16 -#define HMATRIX_M4PR_SIZE 4 -#define HMATRIX_M5PR_OFFSET 20 -#define HMATRIX_M5PR_SIZE 4 -#define HMATRIX_M6PR_OFFSET 24 -#define HMATRIX_M6PR_SIZE 4 -#define HMATRIX_M7PR_OFFSET 28 -#define HMATRIX_M7PR_SIZE 4 - -/* Bitfields in PRS.B */ -#define HMATRIX_M8PR_OFFSET 0 -#define HMATRIX_M8PR_SIZE 4 -#define HMATRIX_M9PR_OFFSET 4 -#define HMATRIX_M9PR_SIZE 4 -#define HMATRIX_M10PR_OFFSET 8 -#define HMATRIX_M10PR_SIZE 4 -#define HMATRIX_M11PR_OFFSET 12 -#define HMATRIX_M11PR_SIZE 4 -#define HMATRIX_M12PR_OFFSET 16 -#define HMATRIX_M12PR_SIZE 4 -#define HMATRIX_M13PR_OFFSET 20 -#define HMATRIX_M13PR_SIZE 4 -#define HMATRIX_M14PR_OFFSET 24 -#define HMATRIX_M14PR_SIZE 4 -#define HMATRIX_M15PR_OFFSET 28 -#define HMATRIX_M15PR_SIZE 4 - -/* Constants for ULBT */ -#define HMATRIX_ULBT_INFINITE 0 -#define HMATRIX_ULBT_SINGLE 1 -#define HMATRIX_ULBT_FOUR_BEAT 2 -#define HMATRIX_ULBT_EIGHT_BEAT 3 -#define HMATRIX_ULBT_SIXTEEN_BEAT 4 - -/* Constants for DEFMSTR_TYPE */ -#define HMATRIX_DEFMSTR_TYPE_NO_DEFAULT 0 -#define HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT 1 -#define HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT 2 - -/* Constants for ARBT */ -#define HMATRIX_ARBT_ROUND_ROBIN 0 -#define HMATRIX_ARBT_FIXED_PRIORITY 1 - -/* Bit manipulation macros */ -#define HMATRIX_BIT(name) \ - (1 << HMATRIX_##name##_OFFSET) -#define HMATRIX_BF(name,value) \ - (((value) & ((1 << HMATRIX_##name##_SIZE) - 1)) \ - << HMATRIX_##name##_OFFSET) -#define HMATRIX_BFEXT(name,value) \ - (((value) >> HMATRIX_##name##_OFFSET) \ - & ((1 << HMATRIX_##name##_SIZE) - 1)) -#define HMATRIX_BFINS(name,value,old) \ - (((old) & ~(((1 << HMATRIX_##name##_SIZE) - 1) \ - << HMATRIX_##name##_OFFSET)) \ - | HMATRIX_BF(name,value)) - -/* Register access macros */ -#define __hmatrix_reg(reg) \ - (((volatile struct hmatrix_regs *)HMATRIX_BASE)->reg) -#define hmatrix_read(reg) \ - (__hmatrix_reg(reg)) -#define hmatrix_write(reg, value) \ - do { __hmatrix_reg(reg) = (value); } while (0) - -#define hmatrix_slave_read(slave, reg) \ - hmatrix_read(reg[HMATRIX_SLAVE_##slave]) -#define hmatrix_slave_write(slave, reg, value) \ - hmatrix_write(reg[HMATRIX_SLAVE_##slave], value) - -#endif /* __ASM_AVR32_HMATRIX_COMMON_H__ */ diff --git a/include/asm-avr32/initcalls.h b/include/asm-avr32/initcalls.h deleted file mode 100644 index 57a278b..0000000 --- a/include/asm-avr32/initcalls.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2005, 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_INITCALLS_H__ -#define __ASM_AVR32_INITCALLS_H__ - -#include - -extern int cpu_init(void); -extern int timer_init(void); - -#endif /* __ASM_AVR32_INITCALLS_H__ */ diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h deleted file mode 100644 index 1cb17ea..0000000 --- a/include/asm-avr32/io.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_IO_H -#define __ASM_AVR32_IO_H - -#include - -#ifdef __KERNEL__ - -/* - * Generic IO read/write. These perform native-endian accesses. Note - * that some architectures will want to re-define __raw_{read,write}w. - */ -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -/* As long as I/O is only performed in P4 (or possibly P3), we're safe */ -#define writeb(v,a) __raw_writeb(v,a) -#define writew(v,a) __raw_writew(v,a) -#define writel(v,a) __raw_writel(v,a) - -#define readb(a) __raw_readb(a) -#define readw(a) __raw_readw(a) -#define readl(a) __raw_readl(a) - -/* - * Bad read/write accesses... - */ -extern void __readwrite_bug(const char *fn); - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * All I/O is memory mapped, so these macros doesn't make very much sense - */ -#define outb(v,p) __raw_writeb(v, p) -#define outw(v,p) __raw_writew(cpu_to_le16(v),p) -#define outl(v,p) __raw_writel(cpu_to_le32(v),p) - -#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) -#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) -#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) - -#include -/* Provides virt_to_phys, phys_to_virt, cached, uncached, map_physmem */ - -#endif /* __KERNEL__ */ - -static inline void sync(void) -{ -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long len) -{ - -} - -#endif /* __ASM_AVR32_IO_H */ diff --git a/include/asm-avr32/posix_types.h b/include/asm-avr32/posix_types.h deleted file mode 100644 index edf1bc1..0000000 --- a/include/asm-avr32/posix_types.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_POSIX_TYPES_H -#define __ASM_AVR32_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned long __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned int __kernel_uid_t; -typedef unsigned int __kernel_gid_t; -typedef unsigned long __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; -typedef unsigned short __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); -} - - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *__p) -{ - unsigned long *__tmp = __p->fds_bits; - int __i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 16: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - __tmp[ 8] = 0; __tmp[ 9] = 0; - __tmp[10] = 0; __tmp[11] = 0; - __tmp[12] = 0; __tmp[13] = 0; - __tmp[14] = 0; __tmp[15] = 0; - return; - - case 8: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - return; - - case 4: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - return; - } - } - __i = __FDSET_LONGS; - while (__i) { - __i--; - *__tmp = 0; - __tmp++; - } -} - -#endif /* defined(__KERNEL__) */ - -#endif /* __ASM_AVR32_POSIX_TYPES_H */ diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h deleted file mode 100644 index cc59dfa..0000000 --- a/include/asm-avr32/processor.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_PROCESSOR_H -#define __ASM_AVR32_PROCESSOR_H - -#ifndef __ASSEMBLY__ - -#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; }) - -struct avr32_cpuinfo { - unsigned long loops_per_jiffy; -}; - -extern struct avr32_cpuinfo boot_cpu_data; - -#ifdef CONFIG_SMP -extern struct avr32_cpuinfo cpu_data[]; -#define current_cpu_data cpu_data[smp_processor_id()] -#else -#define cpu_data (&boot_cpu_data) -#define current_cpu_data boot_cpu_data -#endif - -/* TODO: Make configurable (2GB will serve as a reasonable default) */ -#define TASK_SIZE 0x80000000 - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) - -#define cpu_relax() barrier() -#define cpu_sync_pipeline() asm volatile("sub pc, -2" : : : "memory") - -/* This struct contains the CPU context as stored by switch_to() */ -struct thread_struct { - unsigned long pc; - unsigned long ksp; /* Kernel stack pointer */ - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; -}; - -#define INIT_THREAD { \ - .ksp = sizeof(init_stack) + (long)&init_stack, \ -} - -/* - * Do necessary setup to start up a newly executed thread. - */ -#define start_thread(regs, new_pc, new_sp) \ - set_fs(USER_DS); \ - regs->sr = 0; /* User mode. */ \ - regs->gr[REG_PC] = new_pc; \ - regs->gr[REG_SP] = new_sp - -struct task_struct; - -/* Free all resources held by a thread */ -extern void release_thread(struct task_struct *); - -/* Create a kernel thread without removing it from tasklists */ -extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while(0) - -/* Return saved PC of a blocked thread */ -#define thread_saved_pc(tsk) (tsk->thread.pc) - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_AVR32_PROCESSOR_H */ diff --git a/include/asm-avr32/ptrace.h b/include/asm-avr32/ptrace.h deleted file mode 100644 index c770ba0..0000000 --- a/include/asm-avr32/ptrace.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_PTRACE_H -#define __ASM_AVR32_PTRACE_H - -/* - * Status Register bits - */ -#define SR_H 0x40000000 -#define SR_R 0x20000000 -#define SR_J 0x10000000 -#define SR_DM 0x08000000 -#define SR_D 0x04000000 -#define MODE_NMI 0x01c00000 -#define MODE_EXCEPTION 0x01800000 -#define MODE_INT3 0x01400000 -#define MODE_INT2 0x01000000 -#define MODE_INT1 0x00c00000 -#define MODE_INT0 0x00800000 -#define MODE_SUPERVISOR 0x00400000 -#define MODE_USER 0x00000000 -#define MODE_MASK 0x01c00000 -#define SR_EM 0x00200000 -#define SR_I3M 0x00100000 -#define SR_I2M 0x00080000 -#define SR_I1M 0x00040000 -#define SR_I0M 0x00020000 -#define SR_GM 0x00010000 - -#define MODE_SHIFT 22 -#define SR_EM_BIT 21 -#define SR_I3M_BIT 20 -#define SR_I2M_BIT 19 -#define SR_I1M_BIT 18 -#define SR_I0M_BIT 17 -#define SR_GM_BIT 16 - -/* The user-visible part */ -#define SR_Q 0x00000010 -#define SR_V 0x00000008 -#define SR_N 0x00000004 -#define SR_Z 0x00000002 -#define SR_C 0x00000001 - -/* - * The order is defined by the stdsp instruction. r0 is stored first, so it - * gets the highest address. - * - * Registers 0-12 are general-purpose registers (r12 is normally used for - * the function return value). - * Register 13 is the stack pointer - * Register 14 is the link register - * Register 15 is the program counter - */ -#define FRAME_SIZE_FULL 72 -#define REG_R12_ORIG 68 -#define REG_R0 64 -#define REG_R1 60 -#define REG_R2 56 -#define REG_R3 52 -#define REG_R4 48 -#define REG_R5 44 -#define REG_R6 40 -#define REG_R7 36 -#define REG_R8 32 -#define REG_R9 28 -#define REG_R10 34 -#define REG_R11 20 -#define REG_R12 16 -#define REG_SP 12 -#define REG_LR 8 - -#define FRAME_SIZE_MIN 8 -#define REG_PC 4 -#define REG_SR 0 - -#ifndef __ASSEMBLY__ -struct pt_regs { - /* These are always saved */ - unsigned long sr; - unsigned long pc; - - /* These are sometimes saved */ - unsigned long lr; - unsigned long sp; - unsigned long r12; - unsigned long r11; - unsigned long r10; - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - - /* Only saved on system call */ - unsigned long r12_orig; -}; - -#ifdef __KERNEL__ -# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER) -# define instruction_pointer(regs) ((regs)->pc) -extern void show_regs (struct pt_regs *); - -static __inline__ int valid_user_regs(struct pt_regs *regs) -{ - /* - * Some of the Java bits might be acceptable if/when we - * implement some support for that stuff... - */ - if ((regs->sr & 0xffff0000) == 0) - return 1; - - /* - * Force status register flags to be sane and report this - * illegal behaviour... - */ - regs->sr &= 0x0000ffff; - return 0; -} -#endif - -#endif /* ! __ASSEMBLY__ */ - -#endif /* __ASM_AVR32_PTRACE_H */ diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h deleted file mode 100644 index 762acfa..0000000 --- a/include/asm-avr32/sdram.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_SDRAM_H -#define __ASM_AVR32_SDRAM_H - -struct sdram_config { - /* Number of data bits. */ - enum { - SDRAM_DATA_16BIT = 16, - SDRAM_DATA_32BIT = 32, - } data_bits; - - /* Number of address bits */ - uint8_t row_bits, col_bits, bank_bits; - - /* SDRAM timings in cycles */ - uint8_t cas, twr, trc, trp, trcd, tras, txsr; - - /* SDRAM refresh period in cycles */ - unsigned long refresh_period; -}; - -/* - * Attempt to initialize the SDRAM controller using the specified - * parameters. Return the expected size of the memory area based on - * the number of address and data bits. - * - * The caller should verify that the configuration is correct by - * running a memory test, e.g. get_ram_size(). - */ -extern unsigned long sdram_init(void *sdram_base, - const struct sdram_config *config); - -#endif /* __ASM_AVR32_SDRAM_H */ diff --git a/include/asm-avr32/sections.h b/include/asm-avr32/sections.h deleted file mode 100644 index fe819b2..0000000 --- a/include/asm-avr32/sections.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_SECTIONS_H -#define __ASM_AVR32_SECTIONS_H - -/* References to section boundaries */ - -extern char _text[], _etext[]; -extern char _data[], __data_lma[], _edata[], __edata_lma[]; -extern char __got_start[], __got_lma[], __got_end[]; -extern char _end[]; - -#endif /* __ASM_AVR32_SECTIONS_H */ diff --git a/include/asm-avr32/setup.h b/include/asm-avr32/setup.h deleted file mode 100644 index e6ef8d6..0000000 --- a/include/asm-avr32/setup.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * Based on linux/include/asm-arm/setup.h - * Copyright (C) 1997-1999 Russel King - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_SETUP_H__ -#define __ASM_AVR32_SETUP_H__ - -#define COMMAND_LINE_SIZE 256 - -/* Magic number indicating that a tag table is present */ -#define ATAG_MAGIC 0xa2a25441 - -#ifndef __ASSEMBLY__ - -/* - * Generic memory range, used by several tags. - * - * addr is always physical. - * size is measured in bytes. - * next is for use by the OS, e.g. for grouping regions into - * linked lists. - */ -struct tag_mem_range { - u32 addr; - u32 size; - struct tag_mem_range * next; -}; - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 -/* ATAG_MEM uses tag_mem_range */ - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410003 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* Ramdisk image (may be compressed) */ -#define ATAG_RDIMG 0x54410004 -/* ATAG_RDIMG uses tag_mem_range */ - -/* Information about various clocks present in the system */ -#define ATAG_CLOCK 0x54410005 - -struct tag_clock { - u32 clock_id; /* Which clock are we talking about? */ - u32 clock_flags; /* Special features */ - u64 clock_hz; /* Clock speed in Hz */ -}; - -/* The clock types we know about */ -#define ACLOCK_BOOTCPU 0 /* The CPU we're booting from */ -#define ACLOCK_HSB 1 /* Deprecated */ - -/* Memory reserved for the system (e.g. the bootloader) */ -#define ATAG_RSVD_MEM 0x54410006 -/* ATAG_RSVD_MEM uses tag_mem_range */ - -/* Ethernet information */ - -#define ATAG_ETHERNET 0x54410007 - -struct tag_ethernet { - u8 mac_index; - u8 mii_phy_addr; - u8 hw_address[6]; -}; - -#define AETH_INVALID_PHY 0xff - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem_range mem_range; - struct tag_cmdline cmdline; - struct tag_clock clock; - struct tag_ethernet ethernet; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(struct tag *); -}; - -#define __tag __attribute_used__ __attribute__((__section__(".taglist"))) -#define __tagtable(tag, fn) \ - static struct tagtable __tagtable_##fn __tag = { tag, fn } - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -#endif /* !__ASSEMBLY__ */ - -#endif /* __ASM_AVR32_SETUP_H__ */ diff --git a/include/asm-avr32/string.h b/include/asm-avr32/string.h deleted file mode 100644 index 58582a3..0000000 --- a/include/asm-avr32/string.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_STRING_H -#define __ASM_AVR32_STRING_H - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *s, int c, __kernel_size_t n); - -#endif /* __ASM_AVR32_STRING_H */ diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h deleted file mode 100644 index 4f69704..0000000 --- a/include/asm-avr32/sysreg.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * System registers for AVR32 - */ -#ifndef __ASM_AVR32_SYSREG_H__ -#define __ASM_AVR32_SYSREG_H__ - -/* system register offsets */ -#define SYSREG_SR 0x0000 -#define SYSREG_EVBA 0x0004 -#define SYSREG_ACBA 0x0008 -#define SYSREG_CPUCR 0x000c -#define SYSREG_ECR 0x0010 -#define SYSREG_RSR_SUP 0x0014 -#define SYSREG_RSR_INT0 0x0018 -#define SYSREG_RSR_INT1 0x001c -#define SYSREG_RSR_INT2 0x0020 -#define SYSREG_RSR_INT3 0x0024 -#define SYSREG_RSR_EX 0x0028 -#define SYSREG_RSR_NMI 0x002c -#define SYSREG_RSR_DBG 0x0030 -#define SYSREG_RAR_SUP 0x0034 -#define SYSREG_RAR_INT0 0x0038 -#define SYSREG_RAR_INT1 0x003c -#define SYSREG_RAR_INT2 0x0040 -#define SYSREG_RAR_INT3 0x0044 -#define SYSREG_RAR_EX 0x0048 -#define SYSREG_RAR_NMI 0x004c -#define SYSREG_RAR_DBG 0x0050 -#define SYSREG_JECR 0x0054 -#define SYSREG_JOSP 0x0058 -#define SYSREG_JAVA_LV0 0x005c -#define SYSREG_JAVA_LV1 0x0060 -#define SYSREG_JAVA_LV2 0x0064 -#define SYSREG_JAVA_LV3 0x0068 -#define SYSREG_JAVA_LV4 0x006c -#define SYSREG_JAVA_LV5 0x0070 -#define SYSREG_JAVA_LV6 0x0074 -#define SYSREG_JAVA_LV7 0x0078 -#define SYSREG_JTBA 0x007c -#define SYSREG_JBCR 0x0080 -#define SYSREG_CONFIG0 0x0100 -#define SYSREG_CONFIG1 0x0104 -#define SYSREG_COUNT 0x0108 -#define SYSREG_COMPARE 0x010c -#define SYSREG_TLBEHI 0x0110 -#define SYSREG_TLBELO 0x0114 -#define SYSREG_PTBR 0x0118 -#define SYSREG_TLBEAR 0x011c -#define SYSREG_MMUCR 0x0120 -#define SYSREG_TLBARLO 0x0124 -#define SYSREG_TLBARHI 0x0128 -#define SYSREG_PCCNT 0x012c -#define SYSREG_PCNT0 0x0130 -#define SYSREG_PCNT1 0x0134 -#define SYSREG_PCCR 0x0138 -#define SYSREG_BEAR 0x013c -#define SYSREG_SABAL 0x0300 -#define SYSREG_SABAH 0x0304 -#define SYSREG_SABD 0x0308 - -/* Bitfields in SR */ -#define SYSREG_SR_C_OFFSET 0 -#define SYSREG_SR_C_SIZE 1 -#define SYSREG_Z_OFFSET 1 -#define SYSREG_Z_SIZE 1 -#define SYSREG_SR_N_OFFSET 2 -#define SYSREG_SR_N_SIZE 1 -#define SYSREG_SR_V_OFFSET 3 -#define SYSREG_SR_V_SIZE 1 -#define SYSREG_Q_OFFSET 4 -#define SYSREG_Q_SIZE 1 -#define SYSREG_L_OFFSET 5 -#define SYSREG_L_SIZE 1 -#define SYSREG_T_OFFSET 14 -#define SYSREG_T_SIZE 1 -#define SYSREG_SR_R_OFFSET 15 -#define SYSREG_SR_R_SIZE 1 -#define SYSREG_GM_OFFSET 16 -#define SYSREG_GM_SIZE 1 -#define SYSREG_I0M_OFFSET 17 -#define SYSREG_I0M_SIZE 1 -#define SYSREG_I1M_OFFSET 18 -#define SYSREG_I1M_SIZE 1 -#define SYSREG_I2M_OFFSET 19 -#define SYSREG_I2M_SIZE 1 -#define SYSREG_I3M_OFFSET 20 -#define SYSREG_I3M_SIZE 1 -#define SYSREG_EM_OFFSET 21 -#define SYSREG_EM_SIZE 1 -#define SYSREG_M0_OFFSET 22 -#define SYSREG_M0_SIZE 1 -#define SYSREG_M1_OFFSET 23 -#define SYSREG_M1_SIZE 1 -#define SYSREG_M2_OFFSET 24 -#define SYSREG_M2_SIZE 1 -#define SYSREG_SR_D_OFFSET 26 -#define SYSREG_SR_D_SIZE 1 -#define SYSREG_DM_OFFSET 27 -#define SYSREG_DM_SIZE 1 -#define SYSREG_SR_J_OFFSET 28 -#define SYSREG_SR_J_SIZE 1 -#define SYSREG_H_OFFSET 29 -#define SYSREG_H_SIZE 1 - -/* Bitfields in CPUCR */ -#define SYSREG_BI_OFFSET 0 -#define SYSREG_BI_SIZE 1 -#define SYSREG_BE_OFFSET 1 -#define SYSREG_BE_SIZE 1 -#define SYSREG_FE_OFFSET 2 -#define SYSREG_FE_SIZE 1 -#define SYSREG_RE_OFFSET 3 -#define SYSREG_RE_SIZE 1 -#define SYSREG_IBE_OFFSET 4 -#define SYSREG_IBE_SIZE 1 -#define SYSREG_IEE_OFFSET 5 -#define SYSREG_IEE_SIZE 1 - -/* Bitfields in ECR */ -#define SYSREG_ECR_OFFSET 0 -#define SYSREG_ECR_SIZE 32 - -/* Bitfields in CONFIG0 */ -#define SYSREG_CONFIG0_R_OFFSET 0 -#define SYSREG_CONFIG0_R_SIZE 1 -#define SYSREG_CONFIG0_D_OFFSET 1 -#define SYSREG_CONFIG0_D_SIZE 1 -#define SYSREG_CONFIG0_S_OFFSET 2 -#define SYSREG_CONFIG0_S_SIZE 1 -#define SYSREG_O_OFFSET 3 -#define SYSREG_O_SIZE 1 -#define SYSREG_P_OFFSET 4 -#define SYSREG_P_SIZE 1 -#define SYSREG_CONFIG0_J_OFFSET 5 -#define SYSREG_CONFIG0_J_SIZE 1 -#define SYSREG_F_OFFSET 6 -#define SYSREG_F_SIZE 1 -#define SYSREG_MMUT_OFFSET 7 -#define SYSREG_MMUT_SIZE 3 -#define SYSREG_AR_OFFSET 10 -#define SYSREG_AR_SIZE 3 -#define SYSREG_AT_OFFSET 13 -#define SYSREG_AT_SIZE 3 -#define SYSREG_PROCESSORREVISION_OFFSET 16 -#define SYSREG_PROCESSORREVISION_SIZE 8 -#define SYSREG_PROCESSORID_OFFSET 24 -#define SYSREG_PROCESSORID_SIZE 8 - -/* Bitfields in CONFIG1 */ -#define SYSREG_DASS_OFFSET 0 -#define SYSREG_DASS_SIZE 3 -#define SYSREG_DLSZ_OFFSET 3 -#define SYSREG_DLSZ_SIZE 3 -#define SYSREG_DSET_OFFSET 6 -#define SYSREG_DSET_SIZE 4 -#define SYSREG_IASS_OFFSET 10 -#define SYSREG_IASS_SIZE 3 -#define SYSREG_ILSZ_OFFSET 13 -#define SYSREG_ILSZ_SIZE 3 -#define SYSREG_ISET_OFFSET 16 -#define SYSREG_ISET_SIZE 4 -#define SYSREG_DMMUSZ_OFFSET 20 -#define SYSREG_DMMUSZ_SIZE 6 -#define SYSREG_IMMUSZ_OFFSET 26 -#define SYSREG_IMMUSZ_SIZE 6 - -/* Bitfields in TLBEHI */ -#define SYSREG_ASID_OFFSET 0 -#define SYSREG_ASID_SIZE 8 -#define SYSREG_TLBEHI_I_OFFSET 8 -#define SYSREG_TLBEHI_I_SIZE 1 -#define SYSREG_TLBEHI_V_OFFSET 9 -#define SYSREG_TLBEHI_V_SIZE 1 -#define SYSREG_VPN_OFFSET 10 -#define SYSREG_VPN_SIZE 22 - -/* Bitfields in TLBELO */ -#define SYSREG_W_OFFSET 0 -#define SYSREG_W_SIZE 1 -#define SYSREG_TLBELO_D_OFFSET 1 -#define SYSREG_TLBELO_D_SIZE 1 -#define SYSREG_SZ_OFFSET 2 -#define SYSREG_SZ_SIZE 2 -#define SYSREG_AP_OFFSET 4 -#define SYSREG_AP_SIZE 3 -#define SYSREG_B_OFFSET 7 -#define SYSREG_B_SIZE 1 -#define SYSREG_G_OFFSET 8 -#define SYSREG_G_SIZE 1 -#define SYSREG_TLBELO_C_OFFSET 9 -#define SYSREG_TLBELO_C_SIZE 1 -#define SYSREG_PFN_OFFSET 10 -#define SYSREG_PFN_SIZE 22 - -/* Bitfields in MMUCR */ -#define SYSREG_E_OFFSET 0 -#define SYSREG_E_SIZE 1 -#define SYSREG_M_OFFSET 1 -#define SYSREG_M_SIZE 1 -#define SYSREG_MMUCR_I_OFFSET 2 -#define SYSREG_MMUCR_I_SIZE 1 -#define SYSREG_MMUCR_N_OFFSET 3 -#define SYSREG_MMUCR_N_SIZE 1 -#define SYSREG_MMUCR_S_OFFSET 4 -#define SYSREG_MMUCR_S_SIZE 1 -#define SYSREG_DLA_OFFSET 8 -#define SYSREG_DLA_SIZE 6 -#define SYSREG_DRP_OFFSET 14 -#define SYSREG_DRP_SIZE 6 -#define SYSREG_ILA_OFFSET 20 -#define SYSREG_ILA_SIZE 6 -#define SYSREG_IRP_OFFSET 26 -#define SYSREG_IRP_SIZE 6 - -/* Bitfields in PCCR */ -#define SYSREG_PCCR_R_OFFSET 1 -#define SYSREG_PCCR_R_SIZE 1 -#define SYSREG_PCCR_C_OFFSET 2 -#define SYSREG_PCCR_C_SIZE 1 -#define SYSREG_PCCR_S_OFFSET 3 -#define SYSREG_PCCR_S_SIZE 1 -#define SYSREG_IEC_OFFSET 4 -#define SYSREG_IEC_SIZE 1 -#define SYSREG_IE0_OFFSET 5 -#define SYSREG_IE0_SIZE 1 -#define SYSREG_IE1_OFFSET 6 -#define SYSREG_IE1_SIZE 1 -#define SYSREG_FC_OFFSET 8 -#define SYSREG_FC_SIZE 1 -#define SYSREG_F0_OFFSET 9 -#define SYSREG_F0_SIZE 1 -#define SYSREG_F1_OFFSET 10 -#define SYSREG_F1_SIZE 1 -#define SYSREG_CONF0_OFFSET 12 -#define SYSREG_CONF0_SIZE 6 -#define SYSREG_CONF1_OFFSET 18 -#define SYSREG_CONF1_SIZE 6 - -/* Constants for ECR */ -#define ECR_UNRECOVERABLE 0 -#define ECR_TLB_MULTIPLE 1 -#define ECR_BUS_ERROR_WRITE 2 -#define ECR_BUS_ERROR_READ 3 -#define ECR_NMI 4 -#define ECR_ADDR_ALIGN_X 5 -#define ECR_PROTECTION_X 6 -#define ECR_DEBUG 7 -#define ECR_ILLEGAL_OPCODE 8 -#define ECR_UNIMPL_INSTRUCTION 9 -#define ECR_PRIVILEGE_VIOLATION 10 -#define ECR_FPE 11 -#define ECR_COPROC_ABSENT 12 -#define ECR_ADDR_ALIGN_R 13 -#define ECR_ADDR_ALIGN_W 14 -#define ECR_PROTECTION_R 15 -#define ECR_PROTECTION_W 16 -#define ECR_DTLB_MODIFIED 17 -#define ECR_TLB_MISS_X 20 -#define ECR_TLB_MISS_R 24 -#define ECR_TLB_MISS_W 28 - -/* Bit manipulation macros */ -#define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET) -#define SYSREG_BF(name,value) \ - (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \ - << SYSREG_##name##_OFFSET) -#define SYSREG_BFEXT(name,value) \ - (((value) >> SYSREG_##name##_OFFSET) \ - & ((1 << SYSREG_##name##_SIZE) - 1)) -#define SYSREG_BFINS(name,value,old) \ - (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \ - << SYSREG_##name##_OFFSET)) \ - | SYSREG_BF(name,value)) - -/* Register access macros */ -#define sysreg_read(reg) \ - ((unsigned long)__builtin_mfsr(SYSREG_##reg)) -#define sysreg_write(reg, value) \ - __builtin_mtsr(SYSREG_##reg, value) - -#endif /* __ASM_AVR32_SYSREG_H__ */ diff --git a/include/asm-avr32/types.h b/include/asm-avr32/types.h deleted file mode 100644 index c303e3c..0000000 --- a/include/asm-avr32/types.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_TYPES_H -#define __ASM_AVR32_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - -typedef __signed__ char s8; -typedef unsigned char u8; - -typedef __signed__ short s16; -typedef unsigned short u16; - -typedef __signed__ int s32; -typedef unsigned int u32; - -typedef __signed__ long long s64; -typedef unsigned long long u64; - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#ifdef CONFIG_LBD -typedef u64 sector_t; -#define HAVE_SECTOR_T -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - - -#endif /* __ASM_AVR32_TYPES_H */ diff --git a/include/asm-avr32/u-boot.h b/include/asm-avr32/u-boot.h deleted file mode 100644 index 7e4001f..0000000 --- a/include/asm-avr32/u-boot.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_U_BOOT_H__ -#define __ASM_U_BOOT_H__ 1 - -typedef struct bd_info { - unsigned long bi_baudrate; - unsigned long bi_ip_addr; - unsigned char bi_phy_id[4]; - struct environment_s *bi_env; - unsigned long bi_board_number; - void *bi_boot_params; - struct { - unsigned long start; - unsigned long size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; - unsigned long bi_flashstart; - unsigned long bi_flashsize; - unsigned long bi_flashoffset; -} bd_t; - -#define bi_memstart bi_dram[0].start -#define bi_memsize bi_dram[0].size - -#endif /* __ASM_U_BOOT_H__ */ diff --git a/include/asm-blackfin/bfin_logo_230x230.h b/include/asm-blackfin/bfin_logo_230x230.h deleted file mode 100644 index 3a79631..0000000 --- a/include/asm-blackfin/bfin_logo_230x230.h +++ /dev/null @@ -1,2377 +0,0 @@ -/* - * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi - * - * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y) - * - * Where: 'screen' is the pointer to the frame buffer - * 'width' is the screen width - * 'x' is the horizontal position - * 'y' is the vertical position - */ - -#define EASYLOGO_ENABLE_GZIP 37470 - -static unsigned char EASYLOGO_DECOMP_BUFFER[158700]; - -#include - -#define DEF_BFIN_LOGO_WIDTH 230 -#define DEF_BFIN_LOGO_HEIGHT 230 -#define DEF_BFIN_LOGO_PIXELS 52900 -#define DEF_BFIN_LOGO_BPP 24 -#define DEF_BFIN_LOGO_PIXEL_SIZE 3 -#define DEF_BFIN_LOGO_SIZE 158700 - -unsigned char DEF_BFIN_LOGO_DATA[] = { - 0x1f, 0x8b, 0x08, 0x00, 0x58, 0x7e, 0x68, 0x47, 0x00, 0x03, 0xec, 0x9d, 0x07, 0x5c, 0x53, 0xe7, - 0xfe, 0xc6, 0x55, 0xb6, 0x04, 0x42, 0x80, 0x40, 0x26, 0x59, 0x24, 0x04, 0x02, 0x01, 0xc2, 0x86, - 0x00, 0x61, 0x84, 0xbd, 0xf7, 0x5e, 0x22, 0x22, 0x88, 0xb6, 0x55, 0x71, 0xd4, 0x75, 0x6b, 0x7b, - 0xfd, 0x54, 0x6b, 0xeb, 0xac, 0xb7, 0xe3, 0x52, 0xad, 0x5e, 0x57, 0xd5, 0xf6, 0xfe, 0x6b, 0x5b, - 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* Generated by EasyLogo, (C) 2000 by Paolo Scaffardi - * - * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y) - * - * Where: 'screen' is the pointer to the frame buffer - * 'width' is the screen width - * 'x' is the horizontal position - * 'y' is the vertical position - */ - -#define EASYLOGO_ENABLE_GZIP 19303 - -static unsigned char EASYLOGO_DECOMP_BUFFER[105800]; - -#include - -#define DEF_BFIN_LOGO_WIDTH 230 -#define DEF_BFIN_LOGO_HEIGHT 230 -#define DEF_BFIN_LOGO_PIXELS 52900 -#define DEF_BFIN_LOGO_BPP 16 -#define DEF_BFIN_LOGO_PIXEL_SIZE 2 -#define DEF_BFIN_LOGO_SIZE 105800 - -unsigned char DEF_BFIN_LOGO_DATA[] = { - 0x1f, 0x8b, 0x08, 0x00, 0x9d, 0x56, 0x26, 0x4b, 0x00, 0x03, 0xec, 0x5d, 0x7f, 0x4c, 0x1b, 0x77, - 0x96, 0xb7, 0x2e, 0xe8, 0x3a, 0x52, 0xb8, 0xd3, 0x64, 0xc3, 0x36, 0xd3, 0x14, 0xac, 0xf1, 0xc6, - 0xa6, 0x36, 0x0c, 0xbd, 0x3a, 0xb8, 0x5a, 0x66, 0x01, 0x29, 0xb6, 0x82, 0x14, 0x5c, 0xb8, 0xdb, - 0xb8, 0xa1, 0x5b, 0x9c, 0x3a, 0x77, 0xc4, 0x41, 0x2a, 0x72, 0xd1, 0x2a, 0x75, 0x68, 0xeb, 0x38, - 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0xf8, 0x86, 0xe8, 0x13, 0xb4, 0x47, 0x11, 0xa7, 0x77, 0xa8, 0x98, 0xd8, 0xb4, 0x64, 0xd3, 0xa2, - 0x61, 0xd3, 0x38, 0xb3, 0xf3, 0xdc, 0x41, 0x90, 0xde, 0x0b, 0x95, 0xcb, 0xf7, 0xce, 0x14, 0xf8, - 0x86, 0x4f, 0xff, 0x11, 0x26, 0xe5, 0xd8, 0xcd, 0x96, 0xff, 0x17, 0xd8, 0x7d, 0xcf, 0x6f, 0x5c, - 0xec, 0xa7, 0xa1, 0x48, 0x9d, 0x01, 0x00 -}; - -fastimage_t bfin_logo = { - DEF_BFIN_LOGO_DATA, - DEF_BFIN_LOGO_WIDTH, - DEF_BFIN_LOGO_HEIGHT, - DEF_BFIN_LOGO_BPP, - DEF_BFIN_LOGO_PIXEL_SIZE, - DEF_BFIN_LOGO_SIZE -}; diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h deleted file mode 100644 index ab1fea5..0000000 --- a/include/asm-blackfin/bitops.h +++ /dev/null @@ -1,371 +0,0 @@ -/* - * U-boot - bitops.h Routines for bit operations - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BLACKFIN_BITOPS_H -#define _BLACKFIN_BITOPS_H - -/* - * Copyright 1992, Linus Torvalds. - */ - -#include -#include -#include - -#ifdef __KERNEL__ -/* - * Function prototypes to keep gcc -Wall happy - */ - -/* - * The __ functions are not atomic - */ - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static __inline__ unsigned long ffz(unsigned long word) -{ - unsigned long result = 0; - - while (word & 1) { - result++; - word >>= 1; - } - return result; -} - -static __inline__ void set_bit(int nr, volatile void *addr) -{ - int *a = (int *)addr; - int mask; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - *a |= mask; - local_irq_restore(flags); -} - -static __inline__ void __set_bit(int nr, volatile void *addr) -{ - int *a = (int *)addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a |= mask; -} -#define PLATFORM__SET_BIT - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -static __inline__ void clear_bit(int nr, volatile void *addr) -{ - int *a = (int *)addr; - int mask; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - *a &= ~mask; - local_irq_restore(flags); -} - -static __inline__ void change_bit(int nr, volatile void *addr) -{ - int mask, flags; - unsigned long *ADDR = (unsigned long *)addr; - - ADDR += nr >> 5; - mask = 1 << (nr & 31); - local_irq_save(flags); - *ADDR ^= mask; - local_irq_restore(flags); -} - -static __inline__ void __change_bit(int nr, volatile void *addr) -{ - int mask; - unsigned long *ADDR = (unsigned long *)addr; - - ADDR += nr >> 5; - mask = 1 << (nr & 31); - *ADDR ^= mask; -} - -static __inline__ int test_and_set_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - retval = (mask & *a) != 0; - *a |= mask; - local_irq_restore(flags); - - return retval; -} - -static __inline__ int __test_and_set_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a |= mask; - return retval; -} - -static __inline__ int test_and_clear_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - retval = (mask & *a) != 0; - *a &= ~mask; - local_irq_restore(flags); - - return retval; -} - -static __inline__ int __test_and_clear_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a &= ~mask; - return retval; -} - -static __inline__ int test_and_change_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - retval = (mask & *a) != 0; - *a ^= mask; - local_irq_restore(flags); - - return retval; -} - -static __inline__ int __test_and_change_bit(int nr, volatile void *addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a ^= mask; - return retval; -} - -/* - * This routine doesn't need to be atomic. - */ -static __inline__ int __constant_test_bit(int nr, const volatile void *addr) -{ - return ((1UL << (nr & 31)) & - (((const volatile unsigned int *)addr)[nr >> 5])) != 0; -} - -static __inline__ int __test_bit(int nr, volatile void *addr) -{ - int *a = (int *)addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - return ((mask & *a) != 0); -} - -#define test_bit(nr,addr) \ -(__builtin_constant_p(nr) ? \ - __constant_test_bit((nr),(addr)) : \ - __test_bit((nr),(addr))) - -#define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) - -static __inline__ int find_next_zero_bit(void *addr, int size, int offset) -{ - unsigned long *p = ((unsigned long *)addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (32 - offset); - if (size < 32) - goto found_first; - if (~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while (size & ~31UL) { - if (~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; - - found_first: - tmp |= ~0UL >> size; - found_middle: - return result + ffz(tmp); -} - -/* - * hweightN: returns the hamming weight (i.e. the number - * of bits set) of a N-bit word - */ - -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) - -static __inline__ int ext2_set_bit(int nr, volatile void *addr) -{ - int mask, retval; - unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *)addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - local_irq_save(flags); - retval = (mask & *ADDR) != 0; - *ADDR |= mask; - local_irq_restore(flags); - return retval; -} - -static __inline__ int ext2_clear_bit(int nr, volatile void *addr) -{ - int mask, retval; - unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *)addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - local_irq_save(flags); - retval = (mask & *ADDR) != 0; - *ADDR &= ~mask; - local_irq_restore(flags); - return retval; -} - -static __inline__ int ext2_test_bit(int nr, const volatile void *addr) -{ - int mask; - const volatile unsigned char *ADDR = (const unsigned char *)addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - return ((mask & *ADDR) != 0); -} - -#define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) - -static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, - unsigned long size, - unsigned long offset) -{ - unsigned long *p = ((unsigned long *)addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (32 - offset); - if (size < 32) - goto found_first; - if (~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while (size & ~31UL) { - if (~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; - - found_first: - tmp |= ~0UL >> size; - found_middle: - return result + ffz(tmp); -} - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -#endif - -#endif diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h deleted file mode 100644 index 204d02b..0000000 --- a/include/asm-blackfin/blackfin.h +++ /dev/null @@ -1,15 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh - * DO NOT EDIT THIS FILE - */ - -#ifndef __MACH_GLOB_BLACKFIN__ -#define __MACH_GLOB_BLACKFIN__ - -#include "blackfin_def.h" -#ifndef __ASSEMBLY__ -#include "blackfin_cdef.h" -#endif -#include "blackfin_local.h" - -#endif /* __MACH_GLOB_BLACKFIN__ */ diff --git a/include/asm-blackfin/blackfin_cdef.h b/include/asm-blackfin/blackfin_cdef.h deleted file mode 100644 index aa03f2c..0000000 --- a/include/asm-blackfin/blackfin_cdef.h +++ /dev/null @@ -1,67 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh - * DO NOT EDIT THIS FILE - */ - -#ifndef __MACH_CDEF_BLACKFIN__ -#define __MACH_CDEF_BLACKFIN__ - -#ifdef __ADSPBF522__ -# include "mach-bf527/BF522_cdef.h" -#endif -#ifdef __ADSPBF523__ -# include "mach-bf527/BF523_cdef.h" -#endif -#ifdef __ADSPBF524__ -# include "mach-bf527/BF524_cdef.h" -#endif -#ifdef __ADSPBF525__ -# include "mach-bf527/BF525_cdef.h" -#endif -#ifdef __ADSPBF526__ -# include "mach-bf527/BF526_cdef.h" -#endif -#ifdef __ADSPBF527__ -# include "mach-bf527/BF527_cdef.h" -#endif -#ifdef __ADSPBF531__ -# include "mach-bf533/BF531_cdef.h" -#endif -#ifdef __ADSPBF532__ -# include "mach-bf533/BF532_cdef.h" -#endif -#ifdef __ADSPBF533__ -# include "mach-bf533/BF533_cdef.h" -#endif -#ifdef __ADSPBF534__ -# include "mach-bf537/BF534_cdef.h" -#endif -#ifdef __ADSPBF536__ -# include "mach-bf537/BF536_cdef.h" -#endif -#ifdef __ADSPBF537__ -# include "mach-bf537/BF537_cdef.h" -#endif -#ifdef __ADSPBF541__ -# include "mach-bf548/BF541_cdef.h" -#endif -#ifdef __ADSPBF542__ -# include "mach-bf548/BF542_cdef.h" -#endif -#ifdef __ADSPBF544__ -# include "mach-bf548/BF544_cdef.h" -#endif -#ifdef __ADSPBF547__ -# include "mach-bf548/BF547_cdef.h" -#endif -#ifdef __ADSPBF548__ -# include "mach-bf548/BF548_cdef.h" -#endif -#ifdef __ADSPBF549__ -# include "mach-bf548/BF549_cdef.h" -#endif -#ifdef __ADSPBF561__ -# include "mach-bf561/BF561_cdef.h" -#endif - -#endif /* __MACH_CDEF_BLACKFIN__ */ diff --git a/include/asm-blackfin/blackfin_def.h b/include/asm-blackfin/blackfin_def.h deleted file mode 100644 index 18372f6..0000000 --- a/include/asm-blackfin/blackfin_def.h +++ /dev/null @@ -1,105 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh - * DO NOT EDIT THIS FILE - */ - -#ifndef __MACH_DEF_BLACKFIN__ -#define __MACH_DEF_BLACKFIN__ - -#ifdef __ADSPBF522__ -# include "mach-bf527/BF522_def.h" -# include "mach-bf527/anomaly.h" -# include "mach-bf527/def_local.h" -#endif -#ifdef __ADSPBF523__ -# include "mach-bf527/BF523_def.h" -# include "mach-bf527/anomaly.h" -# include "mach-bf527/def_local.h" -#endif -#ifdef __ADSPBF524__ -# include "mach-bf527/BF524_def.h" -# include "mach-bf527/anomaly.h" -# include "mach-bf527/def_local.h" -#endif -#ifdef __ADSPBF525__ -# include "mach-bf527/BF525_def.h" -# include "mach-bf527/anomaly.h" -# include "mach-bf527/def_local.h" -#endif -#ifdef __ADSPBF526__ -# include "mach-bf527/BF526_def.h" -# include "mach-bf527/anomaly.h" -# include "mach-bf527/def_local.h" -#endif -#ifdef __ADSPBF527__ -# include "mach-bf527/BF527_def.h" -# include "mach-bf527/anomaly.h" -# include "mach-bf527/def_local.h" -#endif -#ifdef __ADSPBF531__ -# include "mach-bf533/BF531_def.h" -# include "mach-bf533/anomaly.h" -# include "mach-bf533/def_local.h" -#endif -#ifdef __ADSPBF532__ -# include "mach-bf533/BF532_def.h" -# include "mach-bf533/anomaly.h" -# include "mach-bf533/def_local.h" -#endif -#ifdef __ADSPBF533__ -# include "mach-bf533/BF533_def.h" -# include "mach-bf533/anomaly.h" -# include "mach-bf533/def_local.h" -#endif -#ifdef __ADSPBF534__ -# include "mach-bf537/BF534_def.h" -# include "mach-bf537/anomaly.h" -# include "mach-bf537/def_local.h" -#endif -#ifdef __ADSPBF536__ -# include "mach-bf537/BF536_def.h" -# include "mach-bf537/anomaly.h" -# include "mach-bf537/def_local.h" -#endif -#ifdef __ADSPBF537__ -# include "mach-bf537/BF537_def.h" -# include "mach-bf537/anomaly.h" -# include "mach-bf537/def_local.h" -#endif -#ifdef __ADSPBF541__ -# include "mach-bf548/BF541_def.h" -# include "mach-bf548/anomaly.h" -# include "mach-bf548/def_local.h" -#endif -#ifdef __ADSPBF542__ -# include "mach-bf548/BF542_def.h" -# include "mach-bf548/anomaly.h" -# include "mach-bf548/def_local.h" -#endif -#ifdef __ADSPBF544__ -# include "mach-bf548/BF544_def.h" -# include "mach-bf548/anomaly.h" -# include "mach-bf548/def_local.h" -#endif -#ifdef __ADSPBF547__ -# include "mach-bf548/BF547_def.h" -# include "mach-bf548/anomaly.h" -# include "mach-bf548/def_local.h" -#endif -#ifdef __ADSPBF548__ -# include "mach-bf548/BF548_def.h" -# include "mach-bf548/anomaly.h" -# include "mach-bf548/def_local.h" -#endif -#ifdef __ADSPBF549__ -# include "mach-bf548/BF549_def.h" -# include "mach-bf548/anomaly.h" -# include "mach-bf548/def_local.h" -#endif -#ifdef __ADSPBF561__ -# include "mach-bf561/BF561_def.h" -# include "mach-bf561/anomaly.h" -# include "mach-bf561/def_local.h" -#endif - -#endif /* __MACH_DEF_BLACKFIN__ */ diff --git a/include/asm-blackfin/blackfin_local.h b/include/asm-blackfin/blackfin_local.h deleted file mode 100644 index 3fd34b3..0000000 --- a/include/asm-blackfin/blackfin_local.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * U-boot - blackfin_local.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __BLACKFIN_LOCAL_H__ -#define __BLACKFIN_LOCAL_H__ - -#include - -#define LO(con32) ((con32) & 0xFFFF) -#define lo(con32) ((con32) & 0xFFFF) -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#define hi(con32) (((con32) >> 16) & 0xFFFF) - -#define OFFSET_(x) (x & 0x0000FFFF) -#define MK_BMSK_(x) (1 << x) - -/* Ideally this should be USEC not MSEC, but the USEC multiplication - * likes to overflow 32bit quantities which is all our assembler - * currently supports ;( - */ -#define USEC_PER_MSEC 1000 -#define MSEC_PER_SEC 1000 -#define BFIN_SCLK (100000000) -#define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC)) -#define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC) - -#define L1_CACHE_SHIFT 5 -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -#include - -#ifndef __ASSEMBLY__ -# ifdef SHARED_RESOURCES -# include -# endif - -# include - -extern u_long get_vco(void); -extern u_long get_cclk(void); -extern u_long get_sclk(void); - -# define bfin_revid() (bfin_read_CHIPID() >> 28) - -extern bool bfin_os_log_check(void); -extern void bfin_os_log_dump(void); - -extern void blackfin_icache_flush_range(const void *, const void *); -extern void blackfin_dcache_flush_range(const void *, const void *); -extern void blackfin_icache_dcache_flush_range(const void *, const void *); -extern void blackfin_dcache_flush_invalidate_range(const void *, const void *); - -/* Use DMA to move data from on chip to external memory. The L1 instruction - * regions can only be accessed via DMA, so if the address in question is in - * that region, make sure we attempt to DMA indirectly. - */ -# define addr_bfin_on_chip_mem(addr) (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) - -# include - -#if ANOMALY_05000198 -# define NOP_PAD_ANOMALY_05000198 "nop;" -#else -# define NOP_PAD_ANOMALY_05000198 -#endif - -#define bfin_read8(addr) ({ \ - uint8_t __v; \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "%0 = b[%1] (z);" \ - : "=d" (__v) \ - : "a" (addr) \ - ); \ - __v; }) - -#define bfin_read16(addr) ({ \ - uint16_t __v; \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "%0 = w[%1] (z);" \ - : "=d" (__v) \ - : "a" (addr) \ - ); \ - __v; }) - -#define bfin_read32(addr) ({ \ - uint32_t __v; \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "%0 = [%1];" \ - : "=d" (__v) \ - : "a" (addr) \ - ); \ - __v; }) - -#define bfin_readPTR(addr) bfin_read32(addr) - -#define bfin_write8(addr, val) \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "b[%0] = %1;" \ - : \ - : "a" (addr), "d" (val) \ - : "memory" \ - ) - -#define bfin_write16(addr, val) \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "w[%0] = %1;" \ - : \ - : "a" (addr), "d" (val) \ - : "memory" \ - ) - -#define bfin_write32(addr, val) \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "[%0] = %1;" \ - : \ - : "a" (addr), "d" (val) \ - : "memory" \ - ) - -#define bfin_writePTR(addr, val) bfin_write32(addr, val) - -/* SSYNC implementation for C file */ -static inline void SSYNC(void) -{ - int _tmp; - if (ANOMALY_05000312) - __asm__ __volatile__( - "cli %0;" - "nop;" - "nop;" - "ssync;" - "sti %0;" - : "=d" (_tmp) - ); - else if (ANOMALY_05000244) - __asm__ __volatile__( - "nop;" - "nop;" - "nop;" - "ssync;" - ); - else - __asm__ __volatile__("ssync;"); -} - -/* CSYNC implementation for C file */ -static inline void CSYNC(void) -{ - int _tmp; - if (ANOMALY_05000312) - __asm__ __volatile__( - "cli %0;" - "nop;" - "nop;" - "csync;" - "sti %0;" - : "=d" (_tmp) - ); - else if (ANOMALY_05000244) - __asm__ __volatile__( - "nop;" - "nop;" - "nop;" - "csync;" - ); - else - __asm__ __volatile__("csync;"); -} - -#else /* __ASSEMBLY__ */ - -/* SSYNC & CSYNC implementations for assembly files */ - -#define ssync(x) SSYNC(x) -#define csync(x) CSYNC(x) - -#if ANOMALY_05000312 -#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch; -#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch; - -#elif ANOMALY_05000244 -#define SSYNC(scratch) nop; nop; nop; SSYNC; -#define CSYNC(scratch) nop; nop; nop; CSYNC; - -#else -#define SSYNC(scratch) SSYNC; -#define CSYNC(scratch) CSYNC; - -#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */ - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h deleted file mode 100644 index a1a52a5..0000000 --- a/include/asm-blackfin/byteorder.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * U-boot - byteorder.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BLACKFIN_BYTEORDER_H -#define _BLACKFIN_BYTEORDER_H - -#include - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#include - -#endif diff --git a/include/asm-blackfin/config-pre.h b/include/asm-blackfin/config-pre.h deleted file mode 100644 index 4531519..0000000 --- a/include/asm-blackfin/config-pre.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * config-pre.h - common defines for Blackfin boards in config.h - * - * Copyright (c) 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__ -#define __ASM_BLACKFIN_CONFIG_PRE_H__ - -/* Misc helper functions */ -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE. - * Depending on your cpu, some of these may not be valid, check your HRM. - * The actual values here are meaningless as long as they're unique. - */ -#define BFIN_BOOT_BYPASS 1 /* bypass bootrom */ -#define BFIN_BOOT_PARA 2 /* boot ldr out of parallel flash */ -#define BFIN_BOOT_SPI_MASTER 3 /* boot ldr out of serial flash */ -#define BFIN_BOOT_SPI_SLAVE 4 /* boot ldr as spi slave */ -#define BFIN_BOOT_TWI_MASTER 5 /* boot ldr over twi device */ -#define BFIN_BOOT_TWI_SLAVE 6 /* boot ldr over twi slave */ -#define BFIN_BOOT_UART 7 /* boot ldr over uart */ -#define BFIN_BOOT_IDLE 8 /* do nothing, just idle */ -#define BFIN_BOOT_FIFO 9 /* boot ldr out of FIFO */ -#define BFIN_BOOT_MEM 10 /* boot ldr out of memory (warmboot) */ -#define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */ -#define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */ -#define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */ - -#ifndef __ASSEMBLY__ -static inline const char *get_bfin_boot_mode(int bfin_boot) -{ - switch (bfin_boot) { - case BFIN_BOOT_BYPASS: return "bypass"; - case BFIN_BOOT_PARA: return "parallel flash"; - case BFIN_BOOT_SPI_MASTER: return "spi flash"; - case BFIN_BOOT_SPI_SLAVE: return "spi slave"; - case BFIN_BOOT_TWI_MASTER: return "i2c flash"; - case BFIN_BOOT_TWI_SLAVE: return "i2c slave"; - case BFIN_BOOT_UART: return "uart"; - case BFIN_BOOT_IDLE: return "idle"; - case BFIN_BOOT_FIFO: return "fifo"; - case BFIN_BOOT_MEM: return "memory"; - case BFIN_BOOT_16HOST_DMA: return "16bit dma"; - case BFIN_BOOT_8HOST_DMA: return "8bit dma"; - case BFIN_BOOT_NAND: return "nand flash"; - default: return "INVALID"; - } -} -#endif - -/* Most bootroms allow for EVT1 redirection */ -#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \ - && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__) -# undef CONFIG_BFIN_BOOTROM_USES_EVT1 -#else -# define CONFIG_BFIN_BOOTROM_USES_EVT1 -#endif - -/* Define the default SPI CS used when booting out of SPI */ -#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ - defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \ - defined(__ADSPBF51x__) -# define BFIN_BOOT_SPI_SSEL 2 -#else -# define BFIN_BOOT_SPI_SSEL 1 -#endif - -/* There is no Blackfin/NetBSD port */ -#undef CONFIG_BOOTM_NETBSD - -/* We rarely use interrupts, so favor throughput over latency */ -#define CONFIG_BFIN_INS_LOWOVERHEAD - -#endif diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h deleted file mode 100644 index 7455685..0000000 --- a/include/asm-blackfin/config.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * config.h - setup common defines for Blackfin boards based on config.h - * - * Copyright (c) 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BLACKFIN_CONFIG_POST_H__ -#define __ASM_BLACKFIN_CONFIG_POST_H__ - -/* Sanity check CONFIG_BFIN_CPU */ -#ifndef CONFIG_BFIN_CPU -# error CONFIG_BFIN_CPU: your board config needs to define this -#endif - -#ifndef CONFIG_BFIN_SCRATCH_REG -# define CONFIG_BFIN_SCRATCH_REG retn -#endif - -/* Relocation to SDRAM works on all Blackfin boards */ -#define CONFIG_RELOC_FIXUP_WORKS - -/* Make sure the structure is properly aligned */ -#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR) -# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned -#endif - -/* Set default CONFIG_VCO_HZ if need be */ -#if !defined(CONFIG_VCO_HZ) -# if (CONFIG_CLKIN_HALF == 0) -# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) -# else -# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2) -# endif -#endif - -/* Set default CONFIG_CCLK_HZ if need be */ -#if !defined(CONFIG_CCLK_HZ) -# if (CONFIG_PLL_BYPASS == 0) -# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV) -# else -# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -# endif -#endif - -/* Set default CONFIG_SCLK_HZ if need be */ -#if !defined(CONFIG_SCLK_HZ) -# if (CONFIG_PLL_BYPASS == 0) -# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV) -# else -# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -# endif -#endif - -/* Since we use these to program PLL registers directly, - * make sure the values are sane and won't screw us up. - */ -#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT -# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63) -#endif -#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF -# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1 -#endif -#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS -# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1 -#endif - -/* If we are using KGDB, make sure we defer exceptions */ -#ifdef CONFIG_CMD_KGDB -# define CONFIG_EXCEPTION_DEFER 1 -#endif - -/* Using L1 scratch pad makes sense for everyone by default. */ -#ifndef CONFIG_LINUX_CMDLINE_ADDR -# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH -#endif -#ifndef CONFIG_LINUX_CMDLINE_SIZE -# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE -#endif - -/* Set default SPI flash CS to the one we boot from */ -#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS) -# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL -#endif - -/* We need envcrc to embed the env into LDRs */ -#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR -# define CONFIG_BUILD_ENVCRC -#endif - -/* Default/common Blackfin memory layout */ -#ifndef CONFIG_SYS_SDRAM_BASE -# define CONFIG_SYS_SDRAM_BASE 0 -#endif -#ifndef CONFIG_SYS_MAX_RAM_SIZE -# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) -#endif -#ifndef CONFIG_SYS_MONITOR_BASE -# if CONFIG_SYS_MAX_RAM_SIZE -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN) -# else -# define CONFIG_SYS_MONITOR_BASE 0 -# endif -#endif -#ifndef CONFIG_SYS_MALLOC_BASE -# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#endif -#ifndef CONFIG_SYS_GBL_DATA_SIZE -# define CONFIG_SYS_GBL_DATA_SIZE (128) -#endif -#ifndef CONFIG_SYS_GBL_DATA_ADDR -# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#endif -#ifndef CONFIG_STACKBASE -# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4) -#endif -#ifndef CONFIG_SYS_MEMTEST_START -# define CONFIG_SYS_MEMTEST_START 0 -#endif -#ifndef CONFIG_SYS_MEMTEST_END -# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4) -#endif - -/* Check to make sure everything fits in external RAM */ -#if CONFIG_SYS_MAX_RAM_SIZE && \ - ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) -# error Memory Map does not fit into configuration -#endif - -/* Default/common Blackfin environment settings */ -#ifndef CONFIG_LOADADDR -# define CONFIG_LOADADDR 0x1000000 -#endif -#ifndef CONFIG_SYS_LOAD_ADDR -# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#endif -#ifndef CONFIG_SYS_BOOTM_LEN -# define CONFIG_SYS_BOOTM_LEN 0x4000000 -#endif -#ifndef CONFIG_SYS_PROMPT -# define CONFIG_SYS_PROMPT "bfin> " -#endif -#ifndef CONFIG_SYS_CBSIZE -# define CONFIG_SYS_CBSIZE 1024 -#elif defined(CONFIG_CMD_KGDB) && CONFIG_SYS_CBSIZE < 1024 -# error "kgdb needs cbsize to be >= 1024" -#endif -#ifndef CONFIG_SYS_BARGSIZE -# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#endif -#ifndef CONFIG_SYS_PBSIZE -# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#endif -#ifndef CONFIG_SYS_MAXARGS -# define CONFIG_SYS_MAXARGS 16 -#endif -#if defined(CONFIG_SYS_HZ) -# if (CONFIG_SYS_HZ != 1000) -# warning "CONFIG_SYS_HZ must always be 1000" -# endif -# undef CONFIG_SYS_HZ -#endif -#define CONFIG_SYS_HZ 1000 -#ifndef CONFIG_SYS_BAUDRATE_TABLE -# define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#endif - -#endif diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h deleted file mode 100644 index cc21e93..0000000 --- a/include/asm-blackfin/cplb.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * cplb.h - defines for managing CPLB tables - * - * Copyright (c) 2002-2007 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BLACKFIN_CPLB_H__ -#define __ASM_BLACKFIN_CPLB_H__ - -#include - -#define CPLB_ENABLE_ICACHE_P 0 -#define CPLB_ENABLE_DCACHE_P 1 -#define CPLB_ENABLE_DCACHE2_P 2 -#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */ -#define CPLB_ENABLE_ICPLBS_P 4 -#define CPLB_ENABLE_DCPLBS_P 5 - -#define CPLB_ENABLE_ICACHE (1< diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h deleted file mode 100644 index c7099e6..0000000 --- a/include/asm-blackfin/global_data.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * U-boot - global_data.h Declarations for global data of u-boot - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H - -#include - -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) - */ -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long board_type; - unsigned long baudrate; - unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - unsigned long post_log_word; /* Record POST activities */ - unsigned long post_init_f_time; /* When post_init_f started */ -#endif - - void **jt; /* jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P3") - -#endif diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h deleted file mode 100644 index 75244a0..0000000 --- a/include/asm-blackfin/io.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * U-boot - io.h IO routines - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_IO_H -#define _BLACKFIN_IO_H - -#ifdef __KERNEL__ - -#include - -#define __iomem - -static inline void sync(void) -{ - SSYNC(); -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -/* - * These are for ISA/PCI shared memory _only_ and should never be used - * on any other type of memory, including Zorro memory. They are meant to - * access the bus in the bus byte order which is little-endian!. - * - * readX/writeX() are used to access memory mapped devices. On some - * architectures the memory mapped IO stuff needs to be accessed - * differently. On the bfin architecture, we just read/write the - * memory location directly. - */ -#ifndef __ASSEMBLY__ - -static inline unsigned char readb(const volatile void __iomem *addr) -{ - unsigned int val; - int tmp; - - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = b [%2] (z);" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); - - return (unsigned char) val; -} - -static inline unsigned short readw(const volatile void __iomem *addr) -{ - unsigned int val; - int tmp; - - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = w [%2] (z);" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); - - return (unsigned short) val; -} - -static inline unsigned int readl(const volatile void __iomem *addr) -{ - unsigned int val; - int tmp; - - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = [%2];" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); - - return val; -} - -#endif /* __ASSEMBLY__ */ - -#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) - -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel -#define memset_io(a, b, c) memset((void *)(a), (b), (c)) -#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) -#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) - -/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */ -#define __io(port) ((void *)(unsigned long)(port)) - -#define inb(port) readb(__io(port)) -#define inw(port) readw(__io(port)) -#define inl(port) readl(__io(port)) -#define outb(x, port) writeb(x, __io(port)) -#define outw(x, port) writew(x, __io(port)) -#define outl(x, port) writel(x, __io(port)) - -#define inb_p(port) inb(__io(port)) -#define inw_p(port) inw(__io(port)) -#define inl_p(port) inl(__io(port)) -#define outb_p(x, port) outb(x, __io(port)) -#define outw_p(x, port) outw(x, __io(port)) -#define outl_p(x, port) outl(x, __io(port)) - -#define ioread8_rep(a, d, c) readsb(a, d, c) -#define ioread16_rep(a, d, c) readsw(a, d, c) -#define ioread32_rep(a, d, c) readsl(a, d, c) -#define iowrite8_rep(a, s, c) writesb(a, s, c) -#define iowrite16_rep(a, s, c) writesw(a, s, c) -#define iowrite32_rep(a, s, c) writesl(a, s, c) - -#define ioread8(x) readb(x) -#define ioread16(x) readw(x) -#define ioread32(x) readl(x) -#define iowrite8(val, x) writeb(val, x) -#define iowrite16(val, x) writew(val, x) -#define iowrite32(val, x) writel(val, x) - -#define mmiowb() wmb() - -#ifndef __ASSEMBLY__ - -extern void outsb(unsigned long port, const void *addr, unsigned long count); -extern void outsw(unsigned long port, const void *addr, unsigned long count); -extern void outsw_8(unsigned long port, const void *addr, unsigned long count); -extern void outsl(unsigned long port, const void *addr, unsigned long count); - -extern void insb(unsigned long port, void *addr, unsigned long count); -extern void insw(unsigned long port, void *addr, unsigned long count); -extern void insw_8(unsigned long port, void *addr, unsigned long count); -extern void insl(unsigned long port, void *addr, unsigned long count); -extern void insl_16(unsigned long port, void *addr, unsigned long count); - -static inline void readsl(const void __iomem *addr, void *buf, int len) -{ - insl((unsigned long)addr, buf, len); -} - -static inline void readsw(const void __iomem *addr, void *buf, int len) -{ - insw((unsigned long)addr, buf, len); -} - -static inline void readsb(const void __iomem *addr, void *buf, int len) -{ - insb((unsigned long)addr, buf, len); -} - -static inline void writesl(const void __iomem *addr, const void *buf, int len) -{ - outsl((unsigned long)addr, buf, len); -} - -static inline void writesw(const void __iomem *addr, const void *buf, int len) -{ - outsw((unsigned long)addr, buf, len); -} - -static inline void writesb(const void __iomem *addr, const void *buf, int len) -{ - outsb((unsigned long)addr, buf, len); -} - -#if defined(CONFIG_STAMP_CF) || defined(CONFIG_BFIN_IDE) -/* This hack for CF/IDE needs to be addressed at some point */ -extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); -extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); -extern unsigned char cf_inb(volatile unsigned char *addr); -extern void cf_outb(unsigned char val, volatile unsigned char *addr); -#undef inb -#undef outb -#undef insw -#undef outsw -#define inb(addr) cf_inb((void *)(addr)) -#define outb(x, addr) cf_outb((unsigned char)(x), (void *)(addr)) -#define insw(port, addr, cnt) cf_insw((void *)(addr), (void *)(port), cnt) -#define outsw(port, addr, cnt) cf_outsw((void *)(port), (void *)(addr), cnt) -#endif - -#endif - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h deleted file mode 100644 index fbb497c..0000000 --- a/include/asm-blackfin/linkage.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * U-boot - linkage.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _LINUX_LINKAGE_H -#define _LINUX_LINKAGE_H - -#include - -#ifdef __cplusplus -#define CPP_ASMLINKAGE extern "C" -#else -#define CPP_ASMLINKAGE -#endif - -#define asmlinkage CPP_ASMLINKAGE - -#define SYMBOL_NAME_STR(X) #X -#define SYMBOL_NAME(X) X -#ifdef __STDC__ -#define SYMBOL_NAME_LABEL(X) X##: -#else -#define SYMBOL_NAME_LABEL(X) X: -#endif - -#define __ALIGN .align 4 -#define __ALIGN_STR ".align 4" - -#ifdef __ASSEMBLY__ - -#define ALIGN __ALIGN -#define ALIGN_STR __ALIGN_STR - -#define LENTRY(name) \ - ALIGN; \ - SYMBOL_NAME_LABEL(name) - -#define ENTRY(name) \ - .globl SYMBOL_NAME(name); \ - LENTRY(name) -#endif - -#ifndef END -#define END(name) \ - .size name, .-name -#endif - -#ifndef ENDPROC -#define ENDPROC(name) \ - .type name, @function; \ - END(name) -#endif - -#endif diff --git a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h deleted file mode 100644 index f65b439..0000000 --- a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h +++ /dev/null @@ -1,1505 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__ -#define __BFIN_CDEF_ADSP_EDN_BF52x_extended__ - -#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ -#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */ -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */ -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */ -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */ -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */ -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* Interrupt Status Register */ -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* Interrupt Wakeup Register */ -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* Interrupt Mask register of SIC2 */ -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* Interrupt Assignment register4 */ -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* Interrupt Assignment register5 */ -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* Interrupt Assignment register6 */ -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* Interrupt Assignment register7 */ -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* Interrupt Status register */ -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* Interrupt Wakeup register */ -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */ -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */ -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */ -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_IER ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */ -#define bfin_read_UART0_IER() bfin_read16(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */ -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_IIR ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */ -#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) -#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */ -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pSPI_CTL ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */ -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define pSPI_FLG ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */ -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define pSPI_STAT ((uint16_t volatile *)SPI_STAT) /* SPI Status register */ -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */ -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */ -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */ -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */ -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */ -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */ -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */ -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define pTIMER_STATUS ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */ -#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) -#define pPORTFIO ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */ -#define bfin_read_PORTFIO() bfin_read16(PORTFIO) -#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define pPORTFIO_CLEAR ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */ -#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) -#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define pPORTFIO_SET ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */ -#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) -#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define pPORTFIO_TOGGLE ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */ -#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) -#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define pPORTFIO_MASKA ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */ -#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) -#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define pPORTFIO_MASKA_CLEAR ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */ -#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) -#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define pPORTFIO_MASKA_SET ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */ -#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) -#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define pPORTFIO_MASKA_TOGGLE ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) -#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define pPORTFIO_MASKB ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */ -#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) -#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define pPORTFIO_MASKB_CLEAR ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */ -#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) -#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define pPORTFIO_MASKB_SET ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */ -#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) -#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define pPORTFIO_MASKB_TOGGLE ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) -#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define pPORTFIO_DIR ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */ -#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) -#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define pPORTFIO_POLAR ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */ -#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) -#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define pPORTFIO_EDGE ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */ -#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) -#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define pPORTFIO_BOTH ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */ -#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) -#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define pPORTFIO_INEN ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register */ -#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) -#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */ -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */ -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */ -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */ -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */ -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */ -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */ -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */ -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */ -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */ -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */ -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */ -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */ -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */ -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */ -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */ -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */ -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */ -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */ -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */ -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ -#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ -#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ -#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ -#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ -#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ -#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ -#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ -#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ -#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ -#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ -#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ -#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ -#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ -#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ -#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ -#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ -#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ -#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ -#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ -#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ -#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ -#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ -#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ -#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */ -#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */ -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */ -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */ -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */ -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */ -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */ -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */ -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */ -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */ -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */ -#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */ -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */ -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */ -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */ -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */ -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */ -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */ -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */ -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */ -#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */ -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */ -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */ -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */ -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */ -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */ -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */ -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */ -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */ -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */ -#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */ -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */ -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */ -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */ -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */ -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */ -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */ -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */ -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */ -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */ -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */ -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */ -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */ -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) -#define pTWI_CLKDIV ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */ -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) -#define pTWI_CONTROL ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) -#define pTWI_SLAVE_CTL ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */ -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) -#define pTWI_SLAVE_STAT ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */ -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) -#define pTWI_SLAVE_ADDR ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */ -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) -#define pTWI_MASTER_CTL ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */ -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) -#define pTWI_MASTER_STAT ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */ -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) -#define pTWI_MASTER_ADDR ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */ -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) -#define pTWI_INT_STAT ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) -#define pTWI_INT_MASK ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */ -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) -#define pTWI_FIFO_CTL ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */ -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) -#define pTWI_FIFO_STAT ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */ -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) -#define pTWI_XMT_DATA8 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) -#define pTWI_XMT_DATA16 ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) -#define pTWI_RCV_DATA8 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) -#define pTWI_RCV_DATA16 ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) -#define pPORTGIO ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */ -#define bfin_read_PORTGIO() bfin_read16(PORTGIO) -#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) -#define pPORTGIO_CLEAR ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */ -#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) -#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) -#define pPORTGIO_SET ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */ -#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) -#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) -#define pPORTGIO_TOGGLE ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */ -#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) -#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) -#define pPORTGIO_MASKA ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */ -#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) -#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) -#define pPORTGIO_MASKA_CLEAR ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */ -#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) -#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) -#define pPORTGIO_MASKA_SET ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */ -#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) -#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) -#define pPORTGIO_MASKA_TOGGLE ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) -#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) -#define pPORTGIO_MASKB ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */ -#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) -#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) -#define pPORTGIO_MASKB_CLEAR ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */ -#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) -#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) -#define pPORTGIO_MASKB_SET ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */ -#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) -#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) -#define pPORTGIO_MASKB_TOGGLE ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) -#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) -#define pPORTGIO_DIR ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */ -#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) -#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) -#define pPORTGIO_POLAR ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */ -#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) -#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) -#define pPORTGIO_EDGE ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */ -#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) -#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) -#define pPORTGIO_BOTH ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */ -#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) -#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) -#define pPORTGIO_INEN ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */ -#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) -#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) -#define pPORTHIO ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */ -#define bfin_read_PORTHIO() bfin_read16(PORTHIO) -#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) -#define pPORTHIO_CLEAR ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */ -#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) -#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) -#define pPORTHIO_SET ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */ -#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) -#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) -#define pPORTHIO_TOGGLE ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */ -#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) -#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) -#define pPORTHIO_MASKA ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */ -#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) -#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) -#define pPORTHIO_MASKA_CLEAR ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */ -#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) -#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) -#define pPORTHIO_MASKA_SET ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */ -#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) -#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) -#define pPORTHIO_MASKA_TOGGLE ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) -#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) -#define pPORTHIO_MASKB ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */ -#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) -#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) -#define pPORTHIO_MASKB_CLEAR ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */ -#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) -#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) -#define pPORTHIO_MASKB_SET ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */ -#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) -#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) -#define pPORTHIO_MASKB_TOGGLE ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) -#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) -#define pPORTHIO_DIR ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */ -#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) -#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) -#define pPORTHIO_POLAR ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */ -#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) -#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) -#define pPORTHIO_EDGE ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */ -#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) -#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) -#define pPORTHIO_BOTH ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */ -#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) -#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) -#define pPORTHIO_INEN ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */ -#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) -#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */ -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */ -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_IER ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */ -#define bfin_read_UART1_IER() bfin_read16(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */ -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_IIR ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */ -#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) -#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */ -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */ -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */ -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */ -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */ -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */ -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */ -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */ -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */ -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */ -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */ -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pPORTF_MUX ((uint16_t volatile *)PORTF_MUX) /* Port F mux control */ -#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) -#define pPORTG_MUX ((uint16_t volatile *)PORTG_MUX) /* Port G mux control */ -#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) -#define pPORTH_MUX ((uint16_t volatile *)PORTH_MUX) /* Port H mux control */ -#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) -#define pPORTF_DRIVE ((uint16_t volatile *)PORTF_DRIVE) /* Port F drive strength control */ -#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) -#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) -#define pPORTG_DRIVE ((uint16_t volatile *)PORTG_DRIVE) /* Port G drive strength control */ -#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) -#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) -#define pPORTH_DRIVE ((uint16_t volatile *)PORTH_DRIVE) /* Port H drive strength control */ -#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) -#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) -#define pPORTF_SLEW ((uint16_t volatile *)PORTF_SLEW) /* Port F slew control */ -#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) -#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) -#define pPORTG_SLEW ((uint16_t volatile *)PORTG_SLEW) /* Port G slew control */ -#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) -#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) -#define pPORTH_SLEW ((uint16_t volatile *)PORTH_SLEW) /* Port H slew control */ -#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) -#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) -#define pPORTF_HYSTERESIS ((uint16_t volatile *)PORTF_HYSTERESIS) /* Port F Schmitt trigger control */ -#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS) -#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val) -#define pPORTG_HYSTERESIS ((uint16_t volatile *)PORTG_HYSTERESIS) /* Port G Schmitt trigger control */ -#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS) -#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val) -#define pPORTH_HYSTERESIS ((uint16_t volatile *)PORTH_HYSTERESIS) /* Port H Schmitt trigger control */ -#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS) -#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val) -#define pNONGPIO_DRIVE ((uint16_t volatile *)NONGPIO_DRIVE) /* Non-GPIO Port drive strength control */ -#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE) -#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val) -#define pNONGPIO_SLEW ((uint16_t volatile *)NONGPIO_SLEW) /* Non-GPIO Port slew control */ -#define bfin_read_NONGPIO_SLEW() bfin_read16(NONGPIO_SLEW) -#define bfin_write_NONGPIO_SLEW(val) bfin_write16(NONGPIO_SLEW, val) -#define pNONGPIO_HYSTERESIS ((uint16_t volatile *)NONGPIO_HYSTERESIS) /* Non-GPIO Port Schmitt trigger control */ -#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS) -#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val) -#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOST Control Register */ -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOST Status Register */ -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOST Acknowledge Mode Timeout Register */ -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration/Control Register */ -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Prescaler Register */ -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Boundary Value Register */ -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Boundary Value Register */ -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ -#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) -#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ -#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) -#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ -#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) -#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ -#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) -#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) -#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) -#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) -#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) -#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ -#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) -#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ -#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) -#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ -#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) -#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ -#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) -#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ -#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) -#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ -#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) -#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ -#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) -#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ -#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) -#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ -#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) -#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ -#define bfin_read_NFC_RST() bfin_read16(NFC_RST) -#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ -#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) -#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ -#define bfin_read_NFC_READ() bfin_read16(NFC_READ) -#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ -#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) -#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ -#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) -#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ -#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) -#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ -#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) -#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) -#define pPFCTL ((uint32_t volatile *)PFCTL) -#define bfin_read_PFCTL() bfin_read32(PFCTL) -#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) -#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) -#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) -#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) -#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) -#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) -#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) -#define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) -#define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER) -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_BF52x_extended__ */ diff --git a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_def.h b/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_def.h deleted file mode 100644 index 0b38480..0000000 --- a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_def.h +++ /dev/null @@ -1,509 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_BF52x_extended__ -#define __BFIN_DEF_ADSP_EDN_BF52x_extended__ - -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ -#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ -#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ -#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ -#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ -#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ -#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */ -#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ -#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ -#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ -#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ -#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ -#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ -#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ -#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ -#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ -#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ -#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ -#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ -#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ -#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ -#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ -#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ -#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ -#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ -#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ -#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ -#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ -#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ -#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ -#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ -#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ -#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ -#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ -#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ -#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ -#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ -#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ -#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ -#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ -#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ -#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ -#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ -#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ -#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ -#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ -#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ -#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ -#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ -#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ -#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ -#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ -#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ -#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ -#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ -#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ -#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ -#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ -#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ -#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ -#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ -#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ -#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ -#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ -#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ -#define PORTF_MUX 0xFFC03210 /* Port F mux control */ -#define PORTG_MUX 0xFFC03214 /* Port G mux control */ -#define PORTH_MUX 0xFFC03218 /* Port H mux control */ -#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ -#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ -#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ -#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ -#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ -#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ -#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ -#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ -#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ -#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */ -#define NONGPIO_SLEW 0xFFC03284 /* Non-GPIO Port slew control */ -#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */ -#define HOST_CONTROL 0xFFC03400 /* HOST Control Register */ -#define HOST_STATUS 0xFFC03404 /* HOST Status Register */ -#define HOST_TIMEOUT 0xFFC03408 /* HOST Acknowledge Mode Timeout Register */ -#define CNT_CONFIG 0xFFC03500 /* Configuration/Control Register */ -#define CNT_IMASK 0xFFC03504 /* Interrupt Mask Register */ -#define CNT_STATUS 0xFFC03508 /* Status Register */ -#define CNT_COMMAND 0xFFC0350C /* Command Register */ -#define CNT_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */ -#define CNT_COUNTER 0xFFC03514 /* Counter Register */ -#define CNT_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */ -#define CNT_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */ -#define OTP_CONTROL 0xFFC03600 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xFFC03604 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xFFC03608 /* OTP/Fuse Status */ -#define OTP_TIMING 0xFFC0360C /* OTP/Fuse Access Timing */ -#define SECURE_SYSSWT 0xFFC03620 /* Secure System Switches */ -#define SECURE_CONTROL 0xFFC03624 /* Secure Control */ -#define SECURE_STATUS 0xFFC03628 /* Secure Status */ -#define OTP_DATA0 0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define NFC_CTL 0xFFC03700 /* NAND Control Register */ -#define NFC_STAT 0xFFC03704 /* NAND Status Register */ -#define NFC_IRQSTAT 0xFFC03708 /* NAND Interrupt Status Register */ -#define NFC_IRQMASK 0xFFC0370C /* NAND Interrupt Mask Register */ -#define NFC_ECC0 0xFFC03710 /* NAND ECC Register 0 */ -#define NFC_ECC1 0xFFC03714 /* NAND ECC Register 1 */ -#define NFC_ECC2 0xFFC03718 /* NAND ECC Register 2 */ -#define NFC_ECC3 0xFFC0371C /* NAND ECC Register 3 */ -#define NFC_COUNT 0xFFC03720 /* NAND ECC Count Register */ -#define NFC_RST 0xFFC03724 /* NAND ECC Reset Register */ -#define NFC_PGCTL 0xFFC03728 /* NAND Page Control Register */ -#define NFC_READ 0xFFC0372C /* NAND Read Data Register */ -#define NFC_ADDR 0xFFC03740 /* NAND Address Register */ -#define NFC_CMD 0xFFC03744 /* NAND Command Register */ -#define NFC_DATA_WR 0xFFC03748 /* NAND Data Write Register */ -#define NFC_DATA_RD 0xFFC0374C /* NAND Data Read Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ -#define PFCTL 0xFFE08000 -#define PFCNTR0 0xFFE08100 -#define PFCNTR1 0xFFE08104 -#define DMA_TC_CNT 0xFFC00B0C -#define DMA_TC_PER 0xFFC00B10 - -#endif /* __BFIN_DEF_ADSP_EDN_BF52x_extended__ */ diff --git a/include/asm-blackfin/mach-bf527/BF522_cdef.h b/include/asm-blackfin/mach-bf527/BF522_cdef.h deleted file mode 100644 index 987cc86..0000000 --- a/include/asm-blackfin/mach-bf527/BF522_cdef.h +++ /dev/null @@ -1,341 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF522_proc__ -#define __BFIN_CDEF_ADSP_BF522_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) - -#endif /* __BFIN_CDEF_ADSP_BF522_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF522_def.h b/include/asm-blackfin/mach-bf527/BF522_def.h deleted file mode 100644 index bc05029..0000000 --- a/include/asm-blackfin/mach-bf527/BF522_def.h +++ /dev/null @@ -1,123 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF522_proc__ -#define __BFIN_DEF_ADSP_BF522_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ - -#endif /* __BFIN_DEF_ADSP_BF522_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF523_cdef.h b/include/asm-blackfin/mach-bf527/BF523_cdef.h deleted file mode 100644 index 390f3dc..0000000 --- a/include/asm-blackfin/mach-bf527/BF523_cdef.h +++ /dev/null @@ -1,341 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF523_proc__ -#define __BFIN_CDEF_ADSP_BF523_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) - -#endif /* __BFIN_CDEF_ADSP_BF523_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF523_def.h b/include/asm-blackfin/mach-bf527/BF523_def.h deleted file mode 100644 index c27fd64..0000000 --- a/include/asm-blackfin/mach-bf527/BF523_def.h +++ /dev/null @@ -1,123 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF523_proc__ -#define __BFIN_DEF_ADSP_BF523_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ - -#endif /* __BFIN_DEF_ADSP_BF523_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF524_cdef.h b/include/asm-blackfin/mach-bf527/BF524_cdef.h deleted file mode 100644 index 9ec89c6..0000000 --- a/include/asm-blackfin/mach-bf527/BF524_cdef.h +++ /dev/null @@ -1,848 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF524_proc__ -#define __BFIN_CDEF_ADSP_BF524_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) - -#endif /* __BFIN_CDEF_ADSP_BF524_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF524_def.h b/include/asm-blackfin/mach-bf527/BF524_def.h deleted file mode 100644 index bd6aa8f..0000000 --- a/include/asm-blackfin/mach-bf527/BF524_def.h +++ /dev/null @@ -1,292 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF524_proc__ -#define __BFIN_DEF_ADSP_BF524_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define USB_FADDR 0xFFC03800 /* Function address register */ -#define USB_POWER 0xFFC03804 /* Power management register */ -#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03820 /* USB frame number */ -#define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -#endif /* __BFIN_DEF_ADSP_BF524_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF525_cdef.h b/include/asm-blackfin/mach-bf527/BF525_cdef.h deleted file mode 100644 index 8fe29db..0000000 --- a/include/asm-blackfin/mach-bf527/BF525_cdef.h +++ /dev/null @@ -1,848 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF525_proc__ -#define __BFIN_CDEF_ADSP_BF525_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) - -#endif /* __BFIN_CDEF_ADSP_BF525_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF525_def.h b/include/asm-blackfin/mach-bf527/BF525_def.h deleted file mode 100644 index 5e88b3b..0000000 --- a/include/asm-blackfin/mach-bf527/BF525_def.h +++ /dev/null @@ -1,292 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF525_proc__ -#define __BFIN_DEF_ADSP_BF525_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define USB_FADDR 0xFFC03800 /* Function address register */ -#define USB_POWER 0xFFC03804 /* Power management register */ -#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03820 /* USB frame number */ -#define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -#endif /* __BFIN_DEF_ADSP_BF525_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF526_cdef.h b/include/asm-blackfin/mach-bf527/BF526_cdef.h deleted file mode 100644 index 9438862..0000000 --- a/include/asm-blackfin/mach-bf527/BF526_cdef.h +++ /dev/null @@ -1,1085 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF526_proc__ -#define __BFIN_CDEF_ADSP_BF526_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */ -#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) -#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */ -#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) -#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */ -#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) -#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */ -#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) -#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */ -#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) -#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */ -#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) -#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */ -#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) -#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */ -#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) -#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */ -#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) -#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */ -#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) -#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */ -#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) -#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) -#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) -#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) -#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) -#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */ -#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) -#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */ -#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) -#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) -#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) -#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) -#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */ -#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) -#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */ -#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) -#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */ -#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) -#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */ -#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) -#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) -#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */ -#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) -#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */ -#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) -#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) -#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) -#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */ -#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) -#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) -#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) -#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) -#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) -#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) -#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */ -#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) -#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */ -#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) -#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */ -#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) -#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */ -#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) -#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */ -#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) -#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */ -#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) -#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */ -#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) -#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */ -#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) -#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) -#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) -#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */ -#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) -#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */ -#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) -#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */ -#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) -#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */ -#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) -#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */ -#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) -#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */ -#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) -#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */ -#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) -#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */ -#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) -#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) -#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) -#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) -#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) -#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) -#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) -#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) -#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */ -#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) -#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */ -#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) -#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */ -#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) -#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */ -#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) -#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */ -#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) -#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */ -#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) -#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */ -#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) -#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */ -#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) -#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */ -#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) -#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */ -#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) -#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */ -#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) -#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */ -#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) -#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */ -#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) -#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */ -#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) -#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */ -#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) -#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */ -#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) -#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) -#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) -#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) -#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) -#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) -#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) -#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */ -#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) -#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) - -#endif /* __BFIN_CDEF_ADSP_BF526_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF526_def.h b/include/asm-blackfin/mach-bf527/BF526_def.h deleted file mode 100644 index 2644abf..0000000 --- a/include/asm-blackfin/mach-bf527/BF526_def.h +++ /dev/null @@ -1,371 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF526_proc__ -#define __BFIN_DEF_ADSP_BF526_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ -#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ -#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ -#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ -#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ -#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ -#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ -#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ -#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ -#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ -#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ -#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ -#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ -#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ -#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ -#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ -#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ -#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ -#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ -#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ -#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ -#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ -#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ -#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ -#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ -#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ -#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ -#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ -#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ -#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ -#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ -#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ -#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ -#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ -#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ -#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ -#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ -#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ -#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ -#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ -#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ -#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ -#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ -#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ -#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ -#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ -#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ -#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ -#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ -#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ -#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ -#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ -#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ -#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ -#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ -#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ -#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ -#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ -#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ -#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ -#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ -#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ -#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ -#define USB_FADDR 0xFFC03800 /* Function address register */ -#define USB_POWER 0xFFC03804 /* Power management register */ -#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03820 /* USB frame number */ -#define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -#endif /* __BFIN_DEF_ADSP_BF526_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF527_cdef.h b/include/asm-blackfin/mach-bf527/BF527_cdef.h deleted file mode 100644 index fb9b307..0000000 --- a/include/asm-blackfin/mach-bf527/BF527_cdef.h +++ /dev/null @@ -1,1085 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF527_proc__ -#define __BFIN_CDEF_ADSP_BF527_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */ -#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) -#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */ -#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) -#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */ -#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) -#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */ -#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) -#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */ -#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) -#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */ -#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) -#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */ -#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) -#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */ -#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) -#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */ -#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) -#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */ -#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) -#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */ -#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) -#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) -#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) -#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) -#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) -#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */ -#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) -#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */ -#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) -#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) -#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) -#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) -#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */ -#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) -#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */ -#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) -#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */ -#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) -#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */ -#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) -#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) -#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */ -#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) -#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */ -#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) -#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) -#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) -#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */ -#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) -#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) -#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) -#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) -#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) -#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) -#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */ -#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) -#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */ -#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) -#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */ -#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) -#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */ -#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) -#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */ -#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) -#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */ -#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) -#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */ -#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) -#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */ -#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) -#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) -#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) -#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */ -#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) -#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */ -#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) -#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */ -#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) -#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */ -#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) -#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */ -#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) -#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */ -#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) -#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */ -#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) -#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */ -#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) -#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) -#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) -#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) -#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) -#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) -#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) -#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) -#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */ -#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) -#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */ -#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) -#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */ -#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) -#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */ -#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) -#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */ -#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) -#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */ -#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) -#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */ -#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) -#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */ -#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) -#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */ -#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) -#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */ -#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) -#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */ -#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) -#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */ -#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) -#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */ -#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) -#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */ -#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) -#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */ -#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) -#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */ -#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) -#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) -#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) -#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) -#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) -#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) -#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) -#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */ -#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) -#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) - -#endif /* __BFIN_CDEF_ADSP_BF527_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF527_def.h b/include/asm-blackfin/mach-bf527/BF527_def.h deleted file mode 100644 index c46c2b0..0000000 --- a/include/asm-blackfin/mach-bf527/BF527_def.h +++ /dev/null @@ -1,371 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF527_proc__ -#define __BFIN_DEF_ADSP_BF527_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ -#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ -#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ -#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ -#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ -#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ -#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ -#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ -#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ -#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ -#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ -#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ -#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ -#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ -#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ -#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ -#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ -#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ -#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ -#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ -#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ -#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ -#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ -#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ -#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ -#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ -#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ -#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ -#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ -#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ -#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ -#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ -#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ -#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ -#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ -#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ -#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ -#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ -#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ -#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ -#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ -#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ -#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ -#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ -#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ -#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ -#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ -#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ -#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ -#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ -#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ -#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ -#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ -#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ -#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ -#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ -#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ -#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ -#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ -#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ -#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ -#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ -#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ -#define USB_FADDR 0xFFC03800 /* Function address register */ -#define USB_POWER 0xFFC03804 /* Power management register */ -#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03820 /* USB frame number */ -#define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -#endif /* __BFIN_DEF_ADSP_BF527_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h deleted file mode 100644 index 0fd7e31..0000000 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * File: include/asm-blackfin/mach-bf527/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -/* This file should be up to date with: - * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List - * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) -# define ANOMALY_BF526 1 -#else -# define ANOMALY_BF526 0 -#endif -#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__) -# define ANOMALY_BF527 1 -#else -# define ANOMALY_BF527 0 -#endif - -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ -#define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ -#define ANOMALY_05000254 (1) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (1) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (__SILICON_REVISION__ < 2) -/* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (__SILICON_REVISION__ < 2) -/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ -#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ -#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* USB Calibration Value to use */ -#define ANOMALY_05000346_value 0xE510 -/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Security Features Are Not Functional */ -#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1) -/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -#define ANOMALY_05000353 (ANOMALY_BF526) -/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Incorrect Default CSEL Value in PLL_DIV */ -#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Authentication Fails To Initiate */ -#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Data Read From L3 Memory by USB DMA May be Corrupted */ -#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* 8-Bit NAND Flash Boot Mode Not Functional */ -#define ANOMALY_05000382 (__SILICON_REVISION__ < 2) -/* Boot from OTP Memory Not Functional */ -#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* bfrom_SysControl() Firmware Routine Not Functional */ -#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Programmable Preboot Settings Not Functional */ -#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* CRC32 Checksum Support Not Functional */ -#define ANOMALY_05000388 (__SILICON_REVISION__ < 2) -/* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Log Buffer Not Functional */ -#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Hook Routine Not Functional */ -#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Header Indirect Bit Not Functional */ -#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ -#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ -#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ -#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ -#define ANOMALY_05000401 (__SILICON_REVISION__ < 2) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (__SILICON_REVISION__ < 2) -/* Lockbox SESR Disallows Certain User Interrupts */ -#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) -/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ -#define ANOMALY_05000405 (1) -/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ -#define ANOMALY_05000407 (__SILICON_REVISION__ < 2) -/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ -#define ANOMALY_05000408 (1) -/* Lockbox firmware leaves MDMA0 channel enabled */ -#define ANOMALY_05000409 (__SILICON_REVISION__ < 2) -/* Incorrect Default Internal Voltage Regulator Setting */ -#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (__SILICON_REVISION__ < 2) -/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ -#define ANOMALY_05000414 (__SILICON_REVISION__ < 2) -/* DEB2_URGENT Bit Not Functional */ -#define ANOMALY_05000415 (__SILICON_REVISION__ < 2) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ -#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ -#define ANOMALY_05000418 (__SILICON_REVISION__ < 2) -/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ -#define ANOMALY_05000420 (__SILICON_REVISION__ < 2) -/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ -#define ANOMALY_05000421 (1) -/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ -#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) -/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ -#define ANOMALY_05000423 (__SILICON_REVISION__ < 2) -/* Internal Voltage Regulator Not Trimmed */ -#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (__SILICON_REVISION__ < 2) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ -#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) -/* Software System Reset Corrupts PLL_LOCKCNT Register */ -#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) -/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ -#define ANOMALY_05000431 (1) -/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ -#define ANOMALY_05000432 (ANOMALY_BF526) -/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ -#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) -/* Preboot Cannot be Used to Alter the PLL_DIV Register */ -#define ANOMALY_05000439 (1) -/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ -#define ANOMALY_05000440 (1) -/* OTP Write Accesses Not Supported */ -#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) -/* The WURESET Bit in the SYSCR Register is not Functional */ -#define ANOMALY_05000445 (1) -/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ -#define ANOMALY_05000451 (1) -/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (1) -/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ -#define ANOMALY_05000456 (1) -/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ -#define ANOMALY_05000457 (1) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000125 (0) -#define ANOMALY_05000158 (0) -#define ANOMALY_05000171 (0) -#define ANOMALY_05000183 (0) -#define ANOMALY_05000198 (0) -#define ANOMALY_05000227 (0) -#define ANOMALY_05000230 (0) -#define ANOMALY_05000242 (0) -#define ANOMALY_05000244 (0) -#define ANOMALY_05000261 (0) -#define ANOMALY_05000263 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000273 (0) -#define ANOMALY_05000278 (0) -#define ANOMALY_05000285 (0) -#define ANOMALY_05000305 (0) -#define ANOMALY_05000307 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000312 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000363 (0) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) - -#endif diff --git a/include/asm-blackfin/mach-bf527/def_local.h b/include/asm-blackfin/mach-bf527/def_local.h deleted file mode 100644 index 81eca83..0000000 --- a/include/asm-blackfin/mach-bf527/def_local.h +++ /dev/null @@ -1,2 +0,0 @@ -#include "mem_map.h" -#include "ports.h" diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h deleted file mode 100644 index 8386b4b..0000000 --- a/include/asm-blackfin/mach-bf527/mem_map.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Common Blackfin memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BF52X_MEM_MAP_H__ -#define __BF52X_MEM_MAP_H__ - -#define L1_DATA_A_SRAM (0xFF800000) -#define L1_DATA_A_SRAM_SIZE (0x4000) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM (0xFF900000) -#define L1_DATA_B_SRAM_SIZE (0x4000) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM (0xFFA00000) -#define L1_INST_SRAM_SIZE (0xC000) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) - -#endif diff --git a/include/asm-blackfin/mach-bf527/ports.h b/include/asm-blackfin/mach-bf527/ports.h deleted file mode 100644 index e6b1df8..0000000 --- a/include/asm-blackfin/mach-bf527/ports.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Port Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT__ -#define __BFIN_PERIPHERAL_PORT__ - -/* PORTx_MUX Masks */ -#define PORT_x_MUX_0_MASK 0x0003 -#define PORT_x_MUX_1_MASK 0x000C -#define PORT_x_MUX_2_MASK 0x0030 -#define PORT_x_MUX_3_MASK 0x00C0 -#define PORT_x_MUX_4_MASK 0x0300 -#define PORT_x_MUX_5_MASK 0x0C00 -#define PORT_x_MUX_6_MASK 0x3000 -#define PORT_x_MUX_7_MASK 0xC000 - -#define PORT_x_MUX_FUNC_1 (0x0) -#define PORT_x_MUX_FUNC_2 (0x1) -#define PORT_x_MUX_FUNC_3 (0x2) -#define PORT_x_MUX_FUNC_4 (0x3) -#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0) -#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0) -#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0) -#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0) -#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2) -#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2) -#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2) -#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2) -#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4) -#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4) -#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4) -#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4) -#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6) -#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6) -#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6) -#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6) -#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8) -#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8) -#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8) -#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8) -#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10) -#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10) -#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10) -#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10) -#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12) -#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12) -#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12) -#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12) -#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) -#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) -#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) -#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) - -#include "../mach-common/bits/ports-f.h" -#include "../mach-common/bits/ports-g.h" -#include "../mach-common/bits/ports-h.h" -#include "../mach-common/bits/ports-j.h" - -#endif diff --git a/include/asm-blackfin/mach-bf533/BF531_cdef.h b/include/asm-blackfin/mach-bf533/BF531_cdef.h deleted file mode 100644 index 49a2b2e..0000000 --- a/include/asm-blackfin/mach-bf533/BF531_cdef.h +++ /dev/null @@ -1,14 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF531_proc__ -#define __BFIN_CDEF_ADSP_BF531_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "../mach-common/ADSP-EDN-extended_cdef.h" - - -#endif /* __BFIN_CDEF_ADSP_BF531_proc__ */ diff --git a/include/asm-blackfin/mach-bf533/BF531_def.h b/include/asm-blackfin/mach-bf533/BF531_def.h deleted file mode 100644 index d7278e5..0000000 --- a/include/asm-blackfin/mach-bf533/BF531_def.h +++ /dev/null @@ -1,23 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF531_proc__ -#define __BFIN_DEF_ADSP_BF531_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "../mach-common/ADSP-EDN-extended_def.h" - -#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) - -#endif /* __BFIN_DEF_ADSP_BF531_proc__ */ diff --git a/include/asm-blackfin/mach-bf533/BF532_cdef.h b/include/asm-blackfin/mach-bf533/BF532_cdef.h deleted file mode 100644 index 47b48ac..0000000 --- a/include/asm-blackfin/mach-bf533/BF532_cdef.h +++ /dev/null @@ -1,14 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF532_proc__ -#define __BFIN_CDEF_ADSP_BF532_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "../mach-common/ADSP-EDN-extended_cdef.h" - - -#endif /* __BFIN_CDEF_ADSP_BF532_proc__ */ diff --git a/include/asm-blackfin/mach-bf533/BF532_def.h b/include/asm-blackfin/mach-bf533/BF532_def.h deleted file mode 100644 index 86944d0..0000000 --- a/include/asm-blackfin/mach-bf533/BF532_def.h +++ /dev/null @@ -1,23 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF532_proc__ -#define __BFIN_DEF_ADSP_BF532_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "../mach-common/ADSP-EDN-extended_def.h" - -#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) - -#endif /* __BFIN_DEF_ADSP_BF532_proc__ */ diff --git a/include/asm-blackfin/mach-bf533/BF533_cdef.h b/include/asm-blackfin/mach-bf533/BF533_cdef.h deleted file mode 100644 index f270d01..0000000 --- a/include/asm-blackfin/mach-bf533/BF533_cdef.h +++ /dev/null @@ -1,14 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF533_proc__ -#define __BFIN_CDEF_ADSP_BF533_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "../mach-common/ADSP-EDN-extended_cdef.h" - - -#endif /* __BFIN_CDEF_ADSP_BF533_proc__ */ diff --git a/include/asm-blackfin/mach-bf533/BF533_def.h b/include/asm-blackfin/mach-bf533/BF533_def.h deleted file mode 100644 index 17b5d7f..0000000 --- a/include/asm-blackfin/mach-bf533/BF533_def.h +++ /dev/null @@ -1,29 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF533_proc__ -#define __BFIN_DEF_ADSP_BF533_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "../mach-common/ADSP-EDN-extended_def.h" - -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) - -#endif /* __BFIN_DEF_ADSP_BF533_proc__ */ diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h deleted file mode 100644 index c98747f..0000000 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ /dev/null @@ -1,338 +0,0 @@ -/* - * File: include/asm-blackfin/mach-bf533/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -/* This file should be up to date with: - * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.1 or 0.2 silicon - sorry */ -#if __SILICON_REVISION__ < 3 -# error will not work on BF533 silicon version 0.0, 0.1, or 0.2 -#endif - -#if defined(__ADSPBF531__) -# define ANOMALY_BF531 1 -#else -# define ANOMALY_BF531 0 -#endif -#if defined(__ADSPBF532__) -# define ANOMALY_BF532 1 -#else -# define ANOMALY_BF532 0 -#endif -#if defined(__ADSPBF533__) -# define ANOMALY_BF533 1 -#else -# define ANOMALY_BF533 0 -#endif - -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ -#define ANOMALY_05000074 (1) -/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ -#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ -#define ANOMALY_05000105 (__SILICON_REVISION__ > 2) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ -#define ANOMALY_05000158 (__SILICON_REVISION__ < 5) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ -#define ANOMALY_05000166 (1) -/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ -#define ANOMALY_05000167 (1) -/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ -#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) -/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ -#define ANOMALY_05000180 (1) -/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ -#define ANOMALY_05000183 (__SILICON_REVISION__ < 4) -/* False Protection Exceptions */ -#define ANOMALY_05000189 (__SILICON_REVISION__ < 4) -/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ -#define ANOMALY_05000193 (__SILICON_REVISION__ < 4) -/* Restarting SPORT in Specific Modes May Cause Data Corruption */ -#define ANOMALY_05000194 (__SILICON_REVISION__ < 4) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ -#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) -/* Current DMA Address Shows Wrong Value During Carry Fix */ -#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) -/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ -#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4) -/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ -#define ANOMALY_05000201 (__SILICON_REVISION__ == 3) -/* Possible Infinite Stall with Specific Dual-DAG Situation */ -#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Specific Sequence That Can Cause DMA Error or DMA Stopping */ -#define ANOMALY_05000203 (__SILICON_REVISION__ < 4) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ -#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) -/* Recovery from "Brown-Out" Condition */ -#define ANOMALY_05000207 (__SILICON_REVISION__ < 4) -/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ -#define ANOMALY_05000208 (1) -/* Speed Path in Computational Unit Affects Certain Instructions */ -#define ANOMALY_05000209 (__SILICON_REVISION__ < 4) -/* UART TX Interrupt Masked Erroneously */ -#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) -/* NMI Event at Boot Time Results in Unpredictable State */ -#define ANOMALY_05000219 (1) -/* Incorrect Pulse-Width of UART Start Bit */ -#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) -/* Scratchpad Memory Bank Reads May Return Incorrect Data */ -#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) -/* SPI Slave Boot Mode Modifies Registers from Reset Value */ -#define ANOMALY_05000229 (1) -/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ -#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) -/* UART STB Bit Incorrectly Affects Receiver Setting */ -#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ -#define ANOMALY_05000233 (__SILICON_REVISION__ < 6) -/* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000234 (__SILICON_REVISION__ == 4) -/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ -#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* Data CPLBs Should Prevent Spurious Hardware Errors */ -#define ANOMALY_05000246 (__SILICON_REVISION__ < 5) -/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ -#define ANOMALY_05000250 (__SILICON_REVISION__ == 4) -/* Maximum External Clock Speed for Timers */ -#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ -#define ANOMALY_05000254 (__SILICON_REVISION__ > 4) -/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ -#define ANOMALY_05000255 (__SILICON_REVISION__ < 5) -/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ -#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) -/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ -#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) -/* ICPLB_STATUS MMR Register May Be Corrupted */ -#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) -/* Stores To Data Cache May Be Lost */ -#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) -/* Hardware Loop Corrupted When Taking an ICPLB Exception */ -#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) -/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ -#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (1) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ -#define ANOMALY_05000269 (__SILICON_REVISION__ < 5) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ -#define ANOMALY_05000270 (__SILICON_REVISION__ < 5) -/* Spontaneous Reset of Internal Voltage Regulator */ -#define ANOMALY_05000271 (__SILICON_REVISION__ == 3) -/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) -/* Writes to Synchronous SDRAM Memory May Be Lost */ -#define ANOMALY_05000273 (__SILICON_REVISION__ < 6) -/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ -#define ANOMALY_05000276 (1) -/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 6) -/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error Exception When ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 6) -/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ -#define ANOMALY_05000282 (__SILICON_REVISION__ < 6) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ -#define ANOMALY_05000283 (__SILICON_REVISION__ < 6) -/* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (__SILICON_REVISION__ < 6) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ -#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) -/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ -#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ -#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) -/* SCKELOW Bit Does Not Maintain State Through Hibernate */ -#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ -#define ANOMALY_05000311 (__SILICON_REVISION__ < 6) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (__SILICON_REVISION__ < 6) -/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (__SILICON_REVISION__ < 6) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ -#define ANOMALY_05000315 (__SILICON_REVISION__ < 6) -/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ -#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (__SILICON_REVISION__ < 6) -/* UART Break Signal Issues */ -#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (__SILICON_REVISION__ < 6) -/* PPI Does Not Start Properly In Specific Mode */ -#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) - -/* These anomalies have been "phased" out of analog.com anomaly sheets and are - * here to show running on older silicon just isn't feasible. - */ - -/* Internal voltage regulator can't be modified via register writes */ -#define ANOMALY_05000066 (__SILICON_REVISION__ < 2) -/* Watchpoints (Hardware Breakpoints) are not supported */ -#define ANOMALY_05000067 (__SILICON_REVISION__ < 3) -/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */ -#define ANOMALY_05000070 (__SILICON_REVISION__ < 2) -/* Writing FIO_DIR can corrupt a programmable flag's data */ -#define ANOMALY_05000079 (__SILICON_REVISION__ < 2) -/* Timer Auto-Baud Mode requires the UART clock to be enabled */ -#define ANOMALY_05000086 (__SILICON_REVISION__ < 2) -/* Internal Clocking Modes on SPORT0 not supported */ -#define ANOMALY_05000088 (__SILICON_REVISION__ < 2) -/* Internal voltage regulator does not wake up from an RTC wakeup */ -#define ANOMALY_05000092 (__SILICON_REVISION__ < 2) -/* The IFLUSH instruction must be preceded by a CSYNC instruction */ -#define ANOMALY_05000093 (__SILICON_REVISION__ < 2) -/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */ -#define ANOMALY_05000095 (__SILICON_REVISION__ < 2) -/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */ -#define ANOMALY_05000096 (__SILICON_REVISION__ < 2) -/* Performance Monitor 0 and 1 are swapped when monitoring memory events */ -#define ANOMALY_05000097 (__SILICON_REVISION__ < 2) -/* 32-bit SPORT DMA will be word reversed */ -#define ANOMALY_05000098 (__SILICON_REVISION__ < 2) -/* Incorrect status in the UART_IIR register */ -#define ANOMALY_05000100 (__SILICON_REVISION__ < 2) -/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ -#define ANOMALY_05000101 (__SILICON_REVISION__ < 2) -/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ -#define ANOMALY_05000102 (__SILICON_REVISION__ < 2) -/* Incorrect value written to the cycle counters */ -#define ANOMALY_05000103 (__SILICON_REVISION__ < 2) -/* Stores to L1 Data memory incorrect when a specific sequence is followed */ -#define ANOMALY_05000104 (__SILICON_REVISION__ < 2) -/* Programmable Flag (PF3) functionality not supported in all PPI modes */ -#define ANOMALY_05000106 (__SILICON_REVISION__ < 2) -/* Data store can be lost when targeting a cache line fill */ -#define ANOMALY_05000107 (__SILICON_REVISION__ < 2) -/* Reserved bits in SYSCFG register not set at power on */ -#define ANOMALY_05000109 (__SILICON_REVISION__ < 3) -/* Infinite Core Stall */ -#define ANOMALY_05000114 (__SILICON_REVISION__ < 2) -/* PPI_FSx may glitch when generated by the on chip Timers */ -#define ANOMALY_05000115 (__SILICON_REVISION__ < 2) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ -#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ -#define ANOMALY_05000117 (__SILICON_REVISION__ < 2) -/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ -#define ANOMALY_05000118 (__SILICON_REVISION__ < 2) -/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ -#define ANOMALY_05000123 (__SILICON_REVISION__ < 3) -/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ -#define ANOMALY_05000124 (__SILICON_REVISION__ < 3) -/* Erroneous exception when enabling cache */ -#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* SPI clock polarity and phase bits incorrect during booting */ -#define ANOMALY_05000126 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL is not set on Reset */ -#define ANOMALY_05000137 (__SILICON_REVISION__ < 3) -/* SPI boot will not complete if there is a zero fill block in the loader file */ -#define ANOMALY_05000138 (__SILICON_REVISION__ == 2) -/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */ -#define ANOMALY_05000139 (__SILICON_REVISION__ < 2) -/* Allowing the SPORT RX FIFO to fill will cause an overflow */ -#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ -#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) -/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ -#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) -/* A read from external memory may return a wrong value with data cache enabled */ -#define ANOMALY_05000143 (__SILICON_REVISION__ < 3) -/* DMA and TESTSET conflict when both are accessing external memory */ -#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) -/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ -#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) -/* MDMA may lose the first few words of a descriptor chain */ -#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ -#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ -#define ANOMALY_05000148 (__SILICON_REVISION__ < 3) -/* Frame Delay in SPORT Multichannel Mode */ -#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ -#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) -/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ -#define ANOMALY_05000155 (__SILICON_REVISION__ < 3) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ -#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* SDRAM auto-refresh and subsequent Power Ups */ -#define ANOMALY_05000168 (__SILICON_REVISION__ < 3) -/* DATA CPLB page miss can result in lost write-through cache data writes */ -#define ANOMALY_05000169 (__SILICON_REVISION__ < 3) -/* DMA vs Core accesses to external memory */ -#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) -/* Cache Fill Buffer Data lost */ -#define ANOMALY_05000174 (__SILICON_REVISION__ < 3) -/* Overlapping Sequencer and Memory Stalls */ -#define ANOMALY_05000175 (__SILICON_REVISION__ < 3) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ -#define ANOMALY_05000176 (__SILICON_REVISION__ < 3) -/* Disabling the PPI resets the PPI configuration registers */ -#define ANOMALY_05000181 (__SILICON_REVISION__ < 3) -/* PPI TX Mode with 2 External Frame Syncs */ -#define ANOMALY_05000185 (__SILICON_REVISION__ < 3) -/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ -#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) -/* In PPI Transmit Modes with External Frame Syncs POLC */ -#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) -/* Internal Voltage Regulator may not start up */ -#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000171 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000353 (1) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000386 (1) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000430 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000435 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) - -#endif diff --git a/include/asm-blackfin/mach-bf533/def_local.h b/include/asm-blackfin/mach-bf533/def_local.h deleted file mode 100644 index 14c111f..0000000 --- a/include/asm-blackfin/mach-bf533/def_local.h +++ /dev/null @@ -1 +0,0 @@ -#include "ports.h" diff --git a/include/asm-blackfin/mach-bf533/ports.h b/include/asm-blackfin/mach-bf533/ports.h deleted file mode 100644 index 512d6df..0000000 --- a/include/asm-blackfin/mach-bf533/ports.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Port Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT__ -#define __BFIN_PERIPHERAL_PORT__ - -#include "../mach-common/bits/ports-f.h" - -#endif diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h deleted file mode 100644 index 0700875..0000000 --- a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h +++ /dev/null @@ -1,2750 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_BF534_extended__ -#define __BFIN_CDEF_ADSP_EDN_BF534_extended__ - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration Register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ -#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) -#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */ -#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) -#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */ -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */ -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */ -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */ -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_ISR ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */ -#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) -#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) -#define pSIC_IWR ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */ -#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) -#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */ -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */ -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */ -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_IER ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */ -#define bfin_read_UART0_IER() bfin_read16(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */ -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_IIR ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */ -#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) -#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */ -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pSPI_CTL ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */ -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define pSPI_FLG ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */ -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define pSPI_STAT ((uint16_t volatile *)SPI_STAT) /* SPI Status register */ -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */ -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */ -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */ -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */ -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */ -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */ -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */ -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define pTIMER_STATUS ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */ -#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) -#define pPORTFIO ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */ -#define bfin_read_PORTFIO() bfin_read16(PORTFIO) -#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define pPORTFIO_CLEAR ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */ -#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) -#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define pPORTFIO_SET ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */ -#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) -#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define pPORTFIO_TOGGLE ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */ -#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) -#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define pPORTFIO_MASKA ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */ -#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) -#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define pPORTFIO_MASKA_CLEAR ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */ -#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) -#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define pPORTFIO_MASKA_SET ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */ -#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) -#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define pPORTFIO_MASKA_TOGGLE ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) -#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define pPORTFIO_MASKB ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */ -#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) -#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define pPORTFIO_MASKB_CLEAR ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */ -#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) -#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define pPORTFIO_MASKB_SET ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */ -#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) -#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define pPORTFIO_MASKB_TOGGLE ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) -#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define pPORTFIO_DIR ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */ -#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) -#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define pPORTFIO_POLAR ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */ -#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) -#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define pPORTFIO_EDGE ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */ -#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) -#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define pPORTFIO_BOTH ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */ -#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) -#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define pPORTFIO_INEN ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register */ -#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) -#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */ -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */ -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */ -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */ -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */ -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */ -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */ -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */ -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */ -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */ -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */ -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */ -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */ -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */ -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */ -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */ -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */ -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */ -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */ -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */ -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ -#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ -#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ -#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ -#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ -#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ -#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ -#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ -#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ -#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ -#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ -#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ -#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ -#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ -#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ -#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ -#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ -#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ -#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ -#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ -#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ -#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ -#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ -#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ -#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */ -#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */ -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */ -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */ -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */ -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */ -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */ -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */ -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */ -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */ -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */ -#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */ -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */ -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */ -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */ -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */ -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */ -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */ -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */ -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */ -#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */ -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */ -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */ -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */ -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */ -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */ -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */ -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */ -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */ -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */ -#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */ -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */ -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */ -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */ -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */ -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */ -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */ -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */ -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */ -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */ -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */ -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */ -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */ -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) -#define pTWI_CLKDIV ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */ -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) -#define pTWI_CONTROL ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) -#define pTWI_SLAVE_CTL ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */ -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) -#define pTWI_SLAVE_STAT ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */ -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) -#define pTWI_SLAVE_ADDR ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */ -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) -#define pTWI_MASTER_CTL ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */ -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) -#define pTWI_MASTER_STAT ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */ -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) -#define pTWI_MASTER_ADDR ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */ -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) -#define pTWI_INT_STAT ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) -#define pTWI_INT_MASK ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */ -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) -#define pTWI_FIFO_CTL ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */ -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) -#define pTWI_FIFO_STAT ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */ -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) -#define pTWI_XMT_DATA8 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) -#define pTWI_XMT_DATA16 ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) -#define pTWI_RCV_DATA8 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) -#define pTWI_RCV_DATA16 ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) -#define pPORTGIO ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */ -#define bfin_read_PORTGIO() bfin_read16(PORTGIO) -#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) -#define pPORTGIO_CLEAR ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */ -#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) -#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) -#define pPORTGIO_SET ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */ -#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) -#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) -#define pPORTGIO_TOGGLE ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */ -#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) -#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) -#define pPORTGIO_MASKA ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */ -#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) -#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) -#define pPORTGIO_MASKA_CLEAR ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */ -#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) -#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) -#define pPORTGIO_MASKA_SET ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */ -#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) -#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) -#define pPORTGIO_MASKA_TOGGLE ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) -#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) -#define pPORTGIO_MASKB ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */ -#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) -#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) -#define pPORTGIO_MASKB_CLEAR ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */ -#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) -#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) -#define pPORTGIO_MASKB_SET ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */ -#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) -#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) -#define pPORTGIO_MASKB_TOGGLE ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) -#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) -#define pPORTGIO_DIR ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */ -#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) -#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) -#define pPORTGIO_POLAR ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */ -#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) -#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) -#define pPORTGIO_EDGE ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */ -#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) -#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) -#define pPORTGIO_BOTH ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */ -#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) -#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) -#define pPORTGIO_INEN ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */ -#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) -#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) -#define pPORTHIO ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */ -#define bfin_read_PORTHIO() bfin_read16(PORTHIO) -#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) -#define pPORTHIO_CLEAR ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */ -#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) -#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) -#define pPORTHIO_SET ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */ -#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) -#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) -#define pPORTHIO_TOGGLE ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */ -#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) -#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) -#define pPORTHIO_MASKA ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */ -#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) -#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) -#define pPORTHIO_MASKA_CLEAR ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */ -#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) -#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) -#define pPORTHIO_MASKA_SET ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */ -#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) -#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) -#define pPORTHIO_MASKA_TOGGLE ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) -#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) -#define pPORTHIO_MASKB ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */ -#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) -#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) -#define pPORTHIO_MASKB_CLEAR ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */ -#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) -#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) -#define pPORTHIO_MASKB_SET ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */ -#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) -#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) -#define pPORTHIO_MASKB_TOGGLE ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) -#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) -#define pPORTHIO_DIR ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */ -#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) -#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) -#define pPORTHIO_POLAR ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */ -#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) -#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) -#define pPORTHIO_EDGE ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */ -#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) -#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) -#define pPORTHIO_BOTH ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */ -#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) -#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) -#define pPORTHIO_INEN ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */ -#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) -#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */ -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */ -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_IER ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */ -#define bfin_read_UART1_IER() bfin_read16(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */ -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_IIR ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */ -#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) -#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */ -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pCAN_MC1 ((uint16_t volatile *)CAN_MC1) /* Mailbox config reg 1 */ -#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) -#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) -#define pCAN_MD1 ((uint16_t volatile *)CAN_MD1) /* Mailbox direction reg 1 */ -#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) -#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val) -#define pCAN_TRS1 ((uint16_t volatile *)CAN_TRS1) /* Transmit Request Set reg 1 */ -#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1) -#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val) -#define pCAN_TRR1 ((uint16_t volatile *)CAN_TRR1) /* Transmit Request Reset reg 1 */ -#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1) -#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val) -#define pCAN_TA1 ((uint16_t volatile *)CAN_TA1) /* Transmit Acknowledge reg 1 */ -#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1) -#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val) -#define pCAN_AA1 ((uint16_t volatile *)CAN_AA1) /* Transmit Abort Acknowledge reg 1 */ -#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1) -#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val) -#define pCAN_RMP1 ((uint16_t volatile *)CAN_RMP1) /* Receive Message Pending reg 1 */ -#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1) -#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val) -#define pCAN_RML1 ((uint16_t volatile *)CAN_RML1) /* Receive Message Lost reg 1 */ -#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1) -#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val) -#define pCAN_MBTIF1 ((uint16_t volatile *)CAN_MBTIF1) /* Mailbox Transmit Interrupt Flag reg 1 */ -#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1) -#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val) -#define pCAN_MBRIF1 ((uint16_t volatile *)CAN_MBRIF1) /* Mailbox Receive Interrupt Flag reg 1 */ -#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1) -#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val) -#define pCAN_MBIM1 ((uint16_t volatile *)CAN_MBIM1) /* Mailbox Interrupt Mask reg 1 */ -#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1) -#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val) -#define pCAN_RFH1 ((uint16_t volatile *)CAN_RFH1) /* Remote Frame Handling reg 1 */ -#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1) -#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val) -#define pCAN_OPSS1 ((uint16_t volatile *)CAN_OPSS1) /* Overwrite Protection Single Shot Xmission reg 1 */ -#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1) -#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val) -#define pCAN_MC2 ((uint16_t volatile *)CAN_MC2) /* Mailbox config reg 2 */ -#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2) -#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val) -#define pCAN_MD2 ((uint16_t volatile *)CAN_MD2) /* Mailbox direction reg 2 */ -#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2) -#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val) -#define pCAN_TRS2 ((uint16_t volatile *)CAN_TRS2) /* Transmit Request Set reg 2 */ -#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2) -#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val) -#define pCAN_TRR2 ((uint16_t volatile *)CAN_TRR2) /* Transmit Request Reset reg 2 */ -#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2) -#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val) -#define pCAN_TA2 ((uint16_t volatile *)CAN_TA2) /* Transmit Acknowledge reg 2 */ -#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2) -#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val) -#define pCAN_AA2 ((uint16_t volatile *)CAN_AA2) /* Transmit Abort Acknowledge reg 2 */ -#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2) -#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val) -#define pCAN_RMP2 ((uint16_t volatile *)CAN_RMP2) /* Receive Message Pending reg 2 */ -#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2) -#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val) -#define pCAN_RML2 ((uint16_t volatile *)CAN_RML2) /* Receive Message Lost reg 2 */ -#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2) -#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val) -#define pCAN_MBTIF2 ((uint16_t volatile *)CAN_MBTIF2) /* Mailbox Transmit Interrupt Flag reg 2 */ -#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2) -#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val) -#define pCAN_MBRIF2 ((uint16_t volatile *)CAN_MBRIF2) /* Mailbox Receive Interrupt Flag reg 2 */ -#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2) -#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val) -#define pCAN_MBIM2 ((uint16_t volatile *)CAN_MBIM2) /* Mailbox Interrupt Mask reg 2 */ -#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2) -#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val) -#define pCAN_RFH2 ((uint16_t volatile *)CAN_RFH2) /* Remote Frame Handling reg 2 */ -#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2) -#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val) -#define pCAN_OPSS2 ((uint16_t volatile *)CAN_OPSS2) /* Overwrite Protection Single Shot Xmission reg 2 */ -#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2) -#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val) -#define pCAN_CLOCK ((uint16_t volatile *)CAN_CLOCK) /* Bit Timing Configuration register 0 */ -#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK) -#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val) -#define pCAN_TIMING ((uint16_t volatile *)CAN_TIMING) /* Bit Timing Configuration register 1 */ -#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING) -#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val) -#define pCAN_DEBUG ((uint16_t volatile *)CAN_DEBUG) /* Config register */ -#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG) -#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val) -#define pCAN_STATUS ((uint16_t volatile *)CAN_STATUS) /* Global Status Register */ -#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS) -#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val) -#define pCAN_CEC ((uint16_t volatile *)CAN_CEC) /* Error Counter Register */ -#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC) -#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val) -#define pCAN_GIS ((uint16_t volatile *)CAN_GIS) /* Global Interrupt Status Register */ -#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS) -#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val) -#define pCAN_GIM ((uint16_t volatile *)CAN_GIM) /* Global Interrupt Mask Register */ -#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM) -#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val) -#define pCAN_GIF ((uint16_t volatile *)CAN_GIF) /* Global Interrupt Flag Register */ -#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF) -#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val) -#define pCAN_CONTROL ((uint16_t volatile *)CAN_CONTROL) /* Master Control Register */ -#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL) -#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val) -#define pCAN_INTR ((uint16_t volatile *)CAN_INTR) /* Interrupt Pending Register */ -#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR) -#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val) -#define pCAN_VERSION ((uint16_t volatile *)CAN_VERSION) /* Version Code Register */ -#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION) -#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val) -#define pCAN_MBTD ((uint16_t volatile *)CAN_MBTD) /* Mailbox Temporary Disable Feature */ -#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD) -#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val) -#define pCAN_EWR ((uint16_t volatile *)CAN_EWR) /* Programmable Warning Level */ -#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR) -#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val) -#define pCAN_ESR ((uint16_t volatile *)CAN_ESR) /* Error Status Register */ -#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR) -#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val) -#define pCAN_UCREG ((uint16_t volatile *)CAN_UCREG) /* Universal Counter Register/Capture Register */ -#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG) -#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val) -#define pCAN_UCCNT ((uint16_t volatile *)CAN_UCCNT) /* Universal Counter */ -#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT) -#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val) -#define pCAN_UCRC ((uint16_t volatile *)CAN_UCRC) /* Universal Counter Force Reload Register */ -#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC) -#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val) -#define pCAN_UCCNF ((uint16_t volatile *)CAN_UCCNF) /* Universal Counter Configuration Register */ -#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) -#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val) -#define pCAN_VERSION2 ((uint16_t volatile *)CAN_VERSION2) /* Version Code Register 2 */ -#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2) -#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val) -#define pCAN_AM00L ((uint16_t volatile *)CAN_AM00L) /* Mailbox 0 Low Acceptance Mask */ -#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) -#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val) -#define pCAN_AM00H ((uint16_t volatile *)CAN_AM00H) /* Mailbox 0 High Acceptance Mask */ -#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H) -#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val) -#define pCAN_AM01L ((uint16_t volatile *)CAN_AM01L) /* Mailbox 1 Low Acceptance Mask */ -#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L) -#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val) -#define pCAN_AM01H ((uint16_t volatile *)CAN_AM01H) /* Mailbox 1 High Acceptance Mask */ -#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H) -#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val) -#define pCAN_AM02L ((uint16_t volatile *)CAN_AM02L) /* Mailbox 2 Low Acceptance Mask */ -#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L) -#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val) -#define pCAN_AM02H ((uint16_t volatile *)CAN_AM02H) /* Mailbox 2 High Acceptance Mask */ -#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H) -#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val) -#define pCAN_AM03L ((uint16_t volatile *)CAN_AM03L) /* Mailbox 3 Low Acceptance Mask */ -#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L) -#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val) -#define pCAN_AM03H ((uint16_t volatile *)CAN_AM03H) /* Mailbox 3 High Acceptance Mask */ -#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H) -#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val) -#define pCAN_AM04L ((uint16_t volatile *)CAN_AM04L) /* Mailbox 4 Low Acceptance Mask */ -#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L) -#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val) -#define pCAN_AM04H ((uint16_t volatile *)CAN_AM04H) /* Mailbox 4 High Acceptance Mask */ -#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H) -#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val) -#define pCAN_AM05L ((uint16_t volatile *)CAN_AM05L) /* Mailbox 5 Low Acceptance Mask */ -#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L) -#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val) -#define pCAN_AM05H ((uint16_t volatile *)CAN_AM05H) /* Mailbox 5 High Acceptance Mask */ -#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H) -#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val) -#define pCAN_AM06L ((uint16_t volatile *)CAN_AM06L) /* Mailbox 6 Low Acceptance Mask */ -#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L) -#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val) -#define pCAN_AM06H ((uint16_t volatile *)CAN_AM06H) /* Mailbox 6 High Acceptance Mask */ -#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H) -#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val) -#define pCAN_AM07L ((uint16_t volatile *)CAN_AM07L) /* Mailbox 7 Low Acceptance Mask */ -#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L) -#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val) -#define pCAN_AM07H ((uint16_t volatile *)CAN_AM07H) /* Mailbox 7 High Acceptance Mask */ -#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H) -#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val) -#define pCAN_AM08L ((uint16_t volatile *)CAN_AM08L) /* Mailbox 8 Low Acceptance Mask */ -#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L) -#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val) -#define pCAN_AM08H ((uint16_t volatile *)CAN_AM08H) /* Mailbox 8 High Acceptance Mask */ -#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H) -#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val) -#define pCAN_AM09L ((uint16_t volatile *)CAN_AM09L) /* Mailbox 9 Low Acceptance Mask */ -#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L) -#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val) -#define pCAN_AM09H ((uint16_t volatile *)CAN_AM09H) /* Mailbox 9 High Acceptance Mask */ -#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H) -#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val) -#define pCAN_AM10L ((uint16_t volatile *)CAN_AM10L) /* Mailbox 10 Low Acceptance Mask */ -#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L) -#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val) -#define pCAN_AM10H ((uint16_t volatile *)CAN_AM10H) /* Mailbox 10 High Acceptance Mask */ -#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H) -#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val) -#define pCAN_AM11L ((uint16_t volatile *)CAN_AM11L) /* Mailbox 11 Low Acceptance Mask */ -#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L) -#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val) -#define pCAN_AM11H ((uint16_t volatile *)CAN_AM11H) /* Mailbox 11 High Acceptance Mask */ -#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H) -#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val) -#define pCAN_AM12L ((uint16_t volatile *)CAN_AM12L) /* Mailbox 12 Low Acceptance Mask */ -#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L) -#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val) -#define pCAN_AM12H ((uint16_t volatile *)CAN_AM12H) /* Mailbox 12 High Acceptance Mask */ -#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H) -#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val) -#define pCAN_AM13L ((uint16_t volatile *)CAN_AM13L) /* Mailbox 13 Low Acceptance Mask */ -#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L) -#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val) -#define pCAN_AM13H ((uint16_t volatile *)CAN_AM13H) /* Mailbox 13 High Acceptance Mask */ -#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H) -#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val) -#define pCAN_AM14L ((uint16_t volatile *)CAN_AM14L) /* Mailbox 14 Low Acceptance Mask */ -#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L) -#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val) -#define pCAN_AM14H ((uint16_t volatile *)CAN_AM14H) /* Mailbox 14 High Acceptance Mask */ -#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H) -#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val) -#define pCAN_AM15L ((uint16_t volatile *)CAN_AM15L) /* Mailbox 15 Low Acceptance Mask */ -#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L) -#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val) -#define pCAN_AM15H ((uint16_t volatile *)CAN_AM15H) /* Mailbox 15 High Acceptance Mask */ -#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H) -#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val) -#define pCAN_AM16L ((uint16_t volatile *)CAN_AM16L) /* Mailbox 16 Low Acceptance Mask */ -#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L) -#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val) -#define pCAN_AM16H ((uint16_t volatile *)CAN_AM16H) /* Mailbox 16 High Acceptance Mask */ -#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H) -#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val) -#define pCAN_AM17L ((uint16_t volatile *)CAN_AM17L) /* Mailbox 17 Low Acceptance Mask */ -#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L) -#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val) -#define pCAN_AM17H ((uint16_t volatile *)CAN_AM17H) /* Mailbox 17 High Acceptance Mask */ -#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H) -#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val) -#define pCAN_AM18L ((uint16_t volatile *)CAN_AM18L) /* Mailbox 18 Low Acceptance Mask */ -#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L) -#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val) -#define pCAN_AM18H ((uint16_t volatile *)CAN_AM18H) /* Mailbox 18 High Acceptance Mask */ -#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H) -#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val) -#define pCAN_AM19L ((uint16_t volatile *)CAN_AM19L) /* Mailbox 19 Low Acceptance Mask */ -#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L) -#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val) -#define pCAN_AM19H ((uint16_t volatile *)CAN_AM19H) /* Mailbox 19 High Acceptance Mask */ -#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H) -#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val) -#define pCAN_AM20L ((uint16_t volatile *)CAN_AM20L) /* Mailbox 20 Low Acceptance Mask */ -#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L) -#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val) -#define pCAN_AM20H ((uint16_t volatile *)CAN_AM20H) /* Mailbox 20 High Acceptance Mask */ -#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H) -#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val) -#define pCAN_AM21L ((uint16_t volatile *)CAN_AM21L) /* Mailbox 21 Low Acceptance Mask */ -#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L) -#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val) -#define pCAN_AM21H ((uint16_t volatile *)CAN_AM21H) /* Mailbox 21 High Acceptance Mask */ -#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H) -#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val) -#define pCAN_AM22L ((uint16_t volatile *)CAN_AM22L) /* Mailbox 22 Low Acceptance Mask */ -#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L) -#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val) -#define pCAN_AM22H ((uint16_t volatile *)CAN_AM22H) /* Mailbox 22 High Acceptance Mask */ -#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H) -#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val) -#define pCAN_AM23L ((uint16_t volatile *)CAN_AM23L) /* Mailbox 23 Low Acceptance Mask */ -#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L) -#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val) -#define pCAN_AM23H ((uint16_t volatile *)CAN_AM23H) /* Mailbox 23 High Acceptance Mask */ -#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H) -#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val) -#define pCAN_AM24L ((uint16_t volatile *)CAN_AM24L) /* Mailbox 24 Low Acceptance Mask */ -#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L) -#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val) -#define pCAN_AM24H ((uint16_t volatile *)CAN_AM24H) /* Mailbox 24 High Acceptance Mask */ -#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H) -#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val) -#define pCAN_AM25L ((uint16_t volatile *)CAN_AM25L) /* Mailbox 25 Low Acceptance Mask */ -#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L) -#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val) -#define pCAN_AM25H ((uint16_t volatile *)CAN_AM25H) /* Mailbox 25 High Acceptance Mask */ -#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H) -#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val) -#define pCAN_AM26L ((uint16_t volatile *)CAN_AM26L) /* Mailbox 26 Low Acceptance Mask */ -#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L) -#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val) -#define pCAN_AM26H ((uint16_t volatile *)CAN_AM26H) /* Mailbox 26 High Acceptance Mask */ -#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H) -#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val) -#define pCAN_AM27L ((uint16_t volatile *)CAN_AM27L) /* Mailbox 27 Low Acceptance Mask */ -#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L) -#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val) -#define pCAN_AM27H ((uint16_t volatile *)CAN_AM27H) /* Mailbox 27 High Acceptance Mask */ -#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H) -#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val) -#define pCAN_AM28L ((uint16_t volatile *)CAN_AM28L) /* Mailbox 28 Low Acceptance Mask */ -#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L) -#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val) -#define pCAN_AM28H ((uint16_t volatile *)CAN_AM28H) /* Mailbox 28 High Acceptance Mask */ -#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H) -#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val) -#define pCAN_AM29L ((uint16_t volatile *)CAN_AM29L) /* Mailbox 29 Low Acceptance Mask */ -#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L) -#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val) -#define pCAN_AM29H ((uint16_t volatile *)CAN_AM29H) /* Mailbox 29 High Acceptance Mask */ -#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H) -#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val) -#define pCAN_AM30L ((uint16_t volatile *)CAN_AM30L) /* Mailbox 30 Low Acceptance Mask */ -#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L) -#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val) -#define pCAN_AM30H ((uint16_t volatile *)CAN_AM30H) /* Mailbox 30 High Acceptance Mask */ -#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H) -#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val) -#define pCAN_AM31L ((uint16_t volatile *)CAN_AM31L) /* Mailbox 31 Low Acceptance Mask */ -#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L) -#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val) -#define pCAN_AM31H ((uint16_t volatile *)CAN_AM31H) /* Mailbox 31 High Acceptance Mask */ -#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H) -#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val) -#define pCAN_MB00_DATA0 ((uint16_t volatile *)CAN_MB00_DATA0) /* Mailbox 0 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0) -#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val) -#define pCAN_MB00_DATA1 ((uint16_t volatile *)CAN_MB00_DATA1) /* Mailbox 0 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1) -#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val) -#define pCAN_MB00_DATA2 ((uint16_t volatile *)CAN_MB00_DATA2) /* Mailbox 0 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2) -#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val) -#define pCAN_MB00_DATA3 ((uint16_t volatile *)CAN_MB00_DATA3) /* Mailbox 0 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3) -#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val) -#define pCAN_MB00_LENGTH ((uint16_t volatile *)CAN_MB00_LENGTH) /* Mailbox 0 Data Length Code Register */ -#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH) -#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val) -#define pCAN_MB00_TIMESTAMP ((uint16_t volatile *)CAN_MB00_TIMESTAMP) /* Mailbox 0 Time Stamp Value Register */ -#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP) -#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val) -#define pCAN_MB00_ID0 ((uint16_t volatile *)CAN_MB00_ID0) /* Mailbox 0 Identifier Low Register */ -#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0) -#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val) -#define pCAN_MB00_ID1 ((uint16_t volatile *)CAN_MB00_ID1) /* Mailbox 0 Identifier High Register */ -#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1) -#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val) -#define pCAN_MB01_DATA0 ((uint16_t volatile *)CAN_MB01_DATA0) /* Mailbox 1 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0) -#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val) -#define pCAN_MB01_DATA1 ((uint16_t volatile *)CAN_MB01_DATA1) /* Mailbox 1 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1) -#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val) -#define pCAN_MB01_DATA2 ((uint16_t volatile *)CAN_MB01_DATA2) /* Mailbox 1 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2) -#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val) -#define pCAN_MB01_DATA3 ((uint16_t volatile *)CAN_MB01_DATA3) /* Mailbox 1 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3) -#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val) -#define pCAN_MB01_LENGTH ((uint16_t volatile *)CAN_MB01_LENGTH) /* Mailbox 1 Data Length Code Register */ -#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH) -#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val) -#define pCAN_MB01_TIMESTAMP ((uint16_t volatile *)CAN_MB01_TIMESTAMP) /* Mailbox 1 Time Stamp Value Register */ -#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP) -#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val) -#define pCAN_MB01_ID0 ((uint16_t volatile *)CAN_MB01_ID0) /* Mailbox 1 Identifier Low Register */ -#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0) -#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val) -#define pCAN_MB01_ID1 ((uint16_t volatile *)CAN_MB01_ID1) /* Mailbox 1 Identifier High Register */ -#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1) -#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val) -#define pCAN_MB02_DATA0 ((uint16_t volatile *)CAN_MB02_DATA0) /* Mailbox 2 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0) -#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val) -#define pCAN_MB02_DATA1 ((uint16_t volatile *)CAN_MB02_DATA1) /* Mailbox 2 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1) -#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val) -#define pCAN_MB02_DATA2 ((uint16_t volatile *)CAN_MB02_DATA2) /* Mailbox 2 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2) -#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val) -#define pCAN_MB02_DATA3 ((uint16_t volatile *)CAN_MB02_DATA3) /* Mailbox 2 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3) -#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val) -#define pCAN_MB02_LENGTH ((uint16_t volatile *)CAN_MB02_LENGTH) /* Mailbox 2 Data Length Code Register */ -#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH) -#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val) -#define pCAN_MB02_TIMESTAMP ((uint16_t volatile *)CAN_MB02_TIMESTAMP) /* Mailbox 2 Time Stamp Value Register */ -#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP) -#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val) -#define pCAN_MB02_ID0 ((uint16_t volatile *)CAN_MB02_ID0) /* Mailbox 2 Identifier Low Register */ -#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0) -#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val) -#define pCAN_MB02_ID1 ((uint16_t volatile *)CAN_MB02_ID1) /* Mailbox 2 Identifier High Register */ -#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1) -#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val) -#define pCAN_MB03_DATA0 ((uint16_t volatile *)CAN_MB03_DATA0) /* Mailbox 3 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0) -#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val) -#define pCAN_MB03_DATA1 ((uint16_t volatile *)CAN_MB03_DATA1) /* Mailbox 3 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1) -#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val) -#define pCAN_MB03_DATA2 ((uint16_t volatile *)CAN_MB03_DATA2) /* Mailbox 3 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2) -#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val) -#define pCAN_MB03_DATA3 ((uint16_t volatile *)CAN_MB03_DATA3) /* Mailbox 3 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3) -#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val) -#define pCAN_MB03_LENGTH ((uint16_t volatile *)CAN_MB03_LENGTH) /* Mailbox 3 Data Length Code Register */ -#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH) -#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val) -#define pCAN_MB03_TIMESTAMP ((uint16_t volatile *)CAN_MB03_TIMESTAMP) /* Mailbox 3 Time Stamp Value Register */ -#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP) -#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val) -#define pCAN_MB03_ID0 ((uint16_t volatile *)CAN_MB03_ID0) /* Mailbox 3 Identifier Low Register */ -#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0) -#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val) -#define pCAN_MB03_ID1 ((uint16_t volatile *)CAN_MB03_ID1) /* Mailbox 3 Identifier High Register */ -#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1) -#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val) -#define pCAN_MB04_DATA0 ((uint16_t volatile *)CAN_MB04_DATA0) /* Mailbox 4 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0) -#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val) -#define pCAN_MB04_DATA1 ((uint16_t volatile *)CAN_MB04_DATA1) /* Mailbox 4 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1) -#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val) -#define pCAN_MB04_DATA2 ((uint16_t volatile *)CAN_MB04_DATA2) /* Mailbox 4 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2) -#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val) -#define pCAN_MB04_DATA3 ((uint16_t volatile *)CAN_MB04_DATA3) /* Mailbox 4 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3) -#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val) -#define pCAN_MB04_LENGTH ((uint16_t volatile *)CAN_MB04_LENGTH) /* Mailbox 4 Data Length Code Register */ -#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH) -#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val) -#define pCAN_MB04_TIMESTAMP ((uint16_t volatile *)CAN_MB04_TIMESTAMP) /* Mailbox 4 Time Stamp Value Register */ -#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP) -#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val) -#define pCAN_MB04_ID0 ((uint16_t volatile *)CAN_MB04_ID0) /* Mailbox 4 Identifier Low Register */ -#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0) -#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val) -#define pCAN_MB04_ID1 ((uint16_t volatile *)CAN_MB04_ID1) /* Mailbox 4 Identifier High Register */ -#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1) -#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val) -#define pCAN_MB05_DATA0 ((uint16_t volatile *)CAN_MB05_DATA0) /* Mailbox 5 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0) -#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val) -#define pCAN_MB05_DATA1 ((uint16_t volatile *)CAN_MB05_DATA1) /* Mailbox 5 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1) -#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val) -#define pCAN_MB05_DATA2 ((uint16_t volatile *)CAN_MB05_DATA2) /* Mailbox 5 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2) -#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val) -#define pCAN_MB05_DATA3 ((uint16_t volatile *)CAN_MB05_DATA3) /* Mailbox 5 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3) -#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val) -#define pCAN_MB05_LENGTH ((uint16_t volatile *)CAN_MB05_LENGTH) /* Mailbox 5 Data Length Code Register */ -#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH) -#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val) -#define pCAN_MB05_TIMESTAMP ((uint16_t volatile *)CAN_MB05_TIMESTAMP) /* Mailbox 5 Time Stamp Value Register */ -#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP) -#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val) -#define pCAN_MB05_ID0 ((uint16_t volatile *)CAN_MB05_ID0) /* Mailbox 5 Identifier Low Register */ -#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0) -#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val) -#define pCAN_MB05_ID1 ((uint16_t volatile *)CAN_MB05_ID1) /* Mailbox 5 Identifier High Register */ -#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1) -#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val) -#define pCAN_MB06_DATA0 ((uint16_t volatile *)CAN_MB06_DATA0) /* Mailbox 6 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0) -#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val) -#define pCAN_MB06_DATA1 ((uint16_t volatile *)CAN_MB06_DATA1) /* Mailbox 6 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1) -#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val) -#define pCAN_MB06_DATA2 ((uint16_t volatile *)CAN_MB06_DATA2) /* Mailbox 6 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2) -#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val) -#define pCAN_MB06_DATA3 ((uint16_t volatile *)CAN_MB06_DATA3) /* Mailbox 6 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3) -#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val) -#define pCAN_MB06_LENGTH ((uint16_t volatile *)CAN_MB06_LENGTH) /* Mailbox 6 Data Length Code Register */ -#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH) -#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val) -#define pCAN_MB06_TIMESTAMP ((uint16_t volatile *)CAN_MB06_TIMESTAMP) /* Mailbox 6 Time Stamp Value Register */ -#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP) -#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val) -#define pCAN_MB06_ID0 ((uint16_t volatile *)CAN_MB06_ID0) /* Mailbox 6 Identifier Low Register */ -#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0) -#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val) -#define pCAN_MB06_ID1 ((uint16_t volatile *)CAN_MB06_ID1) /* Mailbox 6 Identifier High Register */ -#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1) -#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val) -#define pCAN_MB07_DATA0 ((uint16_t volatile *)CAN_MB07_DATA0) /* Mailbox 7 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0) -#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val) -#define pCAN_MB07_DATA1 ((uint16_t volatile *)CAN_MB07_DATA1) /* Mailbox 7 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1) -#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val) -#define pCAN_MB07_DATA2 ((uint16_t volatile *)CAN_MB07_DATA2) /* Mailbox 7 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2) -#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val) -#define pCAN_MB07_DATA3 ((uint16_t volatile *)CAN_MB07_DATA3) /* Mailbox 7 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3) -#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val) -#define pCAN_MB07_LENGTH ((uint16_t volatile *)CAN_MB07_LENGTH) /* Mailbox 7 Data Length Code Register */ -#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH) -#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val) -#define pCAN_MB07_TIMESTAMP ((uint16_t volatile *)CAN_MB07_TIMESTAMP) /* Mailbox 7 Time Stamp Value Register */ -#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP) -#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val) -#define pCAN_MB07_ID0 ((uint16_t volatile *)CAN_MB07_ID0) /* Mailbox 7 Identifier Low Register */ -#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0) -#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val) -#define pCAN_MB07_ID1 ((uint16_t volatile *)CAN_MB07_ID1) /* Mailbox 7 Identifier High Register */ -#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1) -#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val) -#define pCAN_MB08_DATA0 ((uint16_t volatile *)CAN_MB08_DATA0) /* Mailbox 8 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0) -#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val) -#define pCAN_MB08_DATA1 ((uint16_t volatile *)CAN_MB08_DATA1) /* Mailbox 8 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1) -#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val) -#define pCAN_MB08_DATA2 ((uint16_t volatile *)CAN_MB08_DATA2) /* Mailbox 8 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2) -#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val) -#define pCAN_MB08_DATA3 ((uint16_t volatile *)CAN_MB08_DATA3) /* Mailbox 8 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3) -#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val) -#define pCAN_MB08_LENGTH ((uint16_t volatile *)CAN_MB08_LENGTH) /* Mailbox 8 Data Length Code Register */ -#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH) -#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val) -#define pCAN_MB08_TIMESTAMP ((uint16_t volatile *)CAN_MB08_TIMESTAMP) /* Mailbox 8 Time Stamp Value Register */ -#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP) -#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val) -#define pCAN_MB08_ID0 ((uint16_t volatile *)CAN_MB08_ID0) /* Mailbox 8 Identifier Low Register */ -#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0) -#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val) -#define pCAN_MB08_ID1 ((uint16_t volatile *)CAN_MB08_ID1) /* Mailbox 8 Identifier High Register */ -#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1) -#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val) -#define pCAN_MB09_DATA0 ((uint16_t volatile *)CAN_MB09_DATA0) /* Mailbox 9 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0) -#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val) -#define pCAN_MB09_DATA1 ((uint16_t volatile *)CAN_MB09_DATA1) /* Mailbox 9 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1) -#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val) -#define pCAN_MB09_DATA2 ((uint16_t volatile *)CAN_MB09_DATA2) /* Mailbox 9 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2) -#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val) -#define pCAN_MB09_DATA3 ((uint16_t volatile *)CAN_MB09_DATA3) /* Mailbox 9 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3) -#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val) -#define pCAN_MB09_LENGTH ((uint16_t volatile *)CAN_MB09_LENGTH) /* Mailbox 9 Data Length Code Register */ -#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH) -#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val) -#define pCAN_MB09_TIMESTAMP ((uint16_t volatile *)CAN_MB09_TIMESTAMP) /* Mailbox 9 Time Stamp Value Register */ -#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP) -#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val) -#define pCAN_MB09_ID0 ((uint16_t volatile *)CAN_MB09_ID0) /* Mailbox 9 Identifier Low Register */ -#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0) -#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val) -#define pCAN_MB09_ID1 ((uint16_t volatile *)CAN_MB09_ID1) /* Mailbox 9 Identifier High Register */ -#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1) -#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val) -#define pCAN_MB10_DATA0 ((uint16_t volatile *)CAN_MB10_DATA0) /* Mailbox 10 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0) -#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val) -#define pCAN_MB10_DATA1 ((uint16_t volatile *)CAN_MB10_DATA1) /* Mailbox 10 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1) -#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val) -#define pCAN_MB10_DATA2 ((uint16_t volatile *)CAN_MB10_DATA2) /* Mailbox 10 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2) -#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val) -#define pCAN_MB10_DATA3 ((uint16_t volatile *)CAN_MB10_DATA3) /* Mailbox 10 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3) -#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val) -#define pCAN_MB10_LENGTH ((uint16_t volatile *)CAN_MB10_LENGTH) /* Mailbox 10 Data Length Code Register */ -#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH) -#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val) -#define pCAN_MB10_TIMESTAMP ((uint16_t volatile *)CAN_MB10_TIMESTAMP) /* Mailbox 10 Time Stamp Value Register */ -#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP) -#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val) -#define pCAN_MB10_ID0 ((uint16_t volatile *)CAN_MB10_ID0) /* Mailbox 10 Identifier Low Register */ -#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0) -#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val) -#define pCAN_MB10_ID1 ((uint16_t volatile *)CAN_MB10_ID1) /* Mailbox 10 Identifier High Register */ -#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1) -#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val) -#define pCAN_MB11_DATA0 ((uint16_t volatile *)CAN_MB11_DATA0) /* Mailbox 11 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0) -#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val) -#define pCAN_MB11_DATA1 ((uint16_t volatile *)CAN_MB11_DATA1) /* Mailbox 11 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1) -#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val) -#define pCAN_MB11_DATA2 ((uint16_t volatile *)CAN_MB11_DATA2) /* Mailbox 11 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2) -#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val) -#define pCAN_MB11_DATA3 ((uint16_t volatile *)CAN_MB11_DATA3) /* Mailbox 11 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3) -#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val) -#define pCAN_MB11_LENGTH ((uint16_t volatile *)CAN_MB11_LENGTH) /* Mailbox 11 Data Length Code Register */ -#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH) -#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val) -#define pCAN_MB11_TIMESTAMP ((uint16_t volatile *)CAN_MB11_TIMESTAMP) /* Mailbox 11 Time Stamp Value Register */ -#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP) -#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val) -#define pCAN_MB11_ID0 ((uint16_t volatile *)CAN_MB11_ID0) /* Mailbox 11 Identifier Low Register */ -#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0) -#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val) -#define pCAN_MB11_ID1 ((uint16_t volatile *)CAN_MB11_ID1) /* Mailbox 11 Identifier High Register */ -#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1) -#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val) -#define pCAN_MB12_DATA0 ((uint16_t volatile *)CAN_MB12_DATA0) /* Mailbox 12 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0) -#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val) -#define pCAN_MB12_DATA1 ((uint16_t volatile *)CAN_MB12_DATA1) /* Mailbox 12 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1) -#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val) -#define pCAN_MB12_DATA2 ((uint16_t volatile *)CAN_MB12_DATA2) /* Mailbox 12 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2) -#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val) -#define pCAN_MB12_DATA3 ((uint16_t volatile *)CAN_MB12_DATA3) /* Mailbox 12 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3) -#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val) -#define pCAN_MB12_LENGTH ((uint16_t volatile *)CAN_MB12_LENGTH) /* Mailbox 12 Data Length Code Register */ -#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH) -#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val) -#define pCAN_MB12_TIMESTAMP ((uint16_t volatile *)CAN_MB12_TIMESTAMP) /* Mailbox 12 Time Stamp Value Register */ -#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP) -#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val) -#define pCAN_MB12_ID0 ((uint16_t volatile *)CAN_MB12_ID0) /* Mailbox 12 Identifier Low Register */ -#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0) -#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val) -#define pCAN_MB12_ID1 ((uint16_t volatile *)CAN_MB12_ID1) /* Mailbox 12 Identifier High Register */ -#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1) -#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val) -#define pCAN_MB13_DATA0 ((uint16_t volatile *)CAN_MB13_DATA0) /* Mailbox 13 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0) -#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val) -#define pCAN_MB13_DATA1 ((uint16_t volatile *)CAN_MB13_DATA1) /* Mailbox 13 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1) -#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val) -#define pCAN_MB13_DATA2 ((uint16_t volatile *)CAN_MB13_DATA2) /* Mailbox 13 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2) -#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val) -#define pCAN_MB13_DATA3 ((uint16_t volatile *)CAN_MB13_DATA3) /* Mailbox 13 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3) -#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val) -#define pCAN_MB13_LENGTH ((uint16_t volatile *)CAN_MB13_LENGTH) /* Mailbox 13 Data Length Code Register */ -#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH) -#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val) -#define pCAN_MB13_TIMESTAMP ((uint16_t volatile *)CAN_MB13_TIMESTAMP) /* Mailbox 13 Time Stamp Value Register */ -#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP) -#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val) -#define pCAN_MB13_ID0 ((uint16_t volatile *)CAN_MB13_ID0) /* Mailbox 13 Identifier Low Register */ -#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0) -#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val) -#define pCAN_MB13_ID1 ((uint16_t volatile *)CAN_MB13_ID1) /* Mailbox 13 Identifier High Register */ -#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1) -#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val) -#define pCAN_MB14_DATA0 ((uint16_t volatile *)CAN_MB14_DATA0) /* Mailbox 14 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0) -#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val) -#define pCAN_MB14_DATA1 ((uint16_t volatile *)CAN_MB14_DATA1) /* Mailbox 14 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1) -#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val) -#define pCAN_MB14_DATA2 ((uint16_t volatile *)CAN_MB14_DATA2) /* Mailbox 14 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2) -#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val) -#define pCAN_MB14_DATA3 ((uint16_t volatile *)CAN_MB14_DATA3) /* Mailbox 14 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3) -#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val) -#define pCAN_MB14_LENGTH ((uint16_t volatile *)CAN_MB14_LENGTH) /* Mailbox 14 Data Length Code Register */ -#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH) -#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val) -#define pCAN_MB14_TIMESTAMP ((uint16_t volatile *)CAN_MB14_TIMESTAMP) /* Mailbox 14 Time Stamp Value Register */ -#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP) -#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val) -#define pCAN_MB14_ID0 ((uint16_t volatile *)CAN_MB14_ID0) /* Mailbox 14 Identifier Low Register */ -#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0) -#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val) -#define pCAN_MB14_ID1 ((uint16_t volatile *)CAN_MB14_ID1) /* Mailbox 14 Identifier High Register */ -#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1) -#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val) -#define pCAN_MB15_DATA0 ((uint16_t volatile *)CAN_MB15_DATA0) /* Mailbox 15 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0) -#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val) -#define pCAN_MB15_DATA1 ((uint16_t volatile *)CAN_MB15_DATA1) /* Mailbox 15 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1) -#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val) -#define pCAN_MB15_DATA2 ((uint16_t volatile *)CAN_MB15_DATA2) /* Mailbox 15 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2) -#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val) -#define pCAN_MB15_DATA3 ((uint16_t volatile *)CAN_MB15_DATA3) /* Mailbox 15 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3) -#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val) -#define pCAN_MB15_LENGTH ((uint16_t volatile *)CAN_MB15_LENGTH) /* Mailbox 15 Data Length Code Register */ -#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH) -#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val) -#define pCAN_MB15_TIMESTAMP ((uint16_t volatile *)CAN_MB15_TIMESTAMP) /* Mailbox 15 Time Stamp Value Register */ -#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP) -#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val) -#define pCAN_MB15_ID0 ((uint16_t volatile *)CAN_MB15_ID0) /* Mailbox 15 Identifier Low Register */ -#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0) -#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val) -#define pCAN_MB15_ID1 ((uint16_t volatile *)CAN_MB15_ID1) /* Mailbox 15 Identifier High Register */ -#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1) -#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val) -#define pCAN_MB16_DATA0 ((uint16_t volatile *)CAN_MB16_DATA0) /* Mailbox 16 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0) -#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val) -#define pCAN_MB16_DATA1 ((uint16_t volatile *)CAN_MB16_DATA1) /* Mailbox 16 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1) -#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val) -#define pCAN_MB16_DATA2 ((uint16_t volatile *)CAN_MB16_DATA2) /* Mailbox 16 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2) -#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val) -#define pCAN_MB16_DATA3 ((uint16_t volatile *)CAN_MB16_DATA3) /* Mailbox 16 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3) -#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val) -#define pCAN_MB16_LENGTH ((uint16_t volatile *)CAN_MB16_LENGTH) /* Mailbox 16 Data Length Code Register */ -#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH) -#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val) -#define pCAN_MB16_TIMESTAMP ((uint16_t volatile *)CAN_MB16_TIMESTAMP) /* Mailbox 16 Time Stamp Value Register */ -#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP) -#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val) -#define pCAN_MB16_ID0 ((uint16_t volatile *)CAN_MB16_ID0) /* Mailbox 16 Identifier Low Register */ -#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0) -#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val) -#define pCAN_MB16_ID1 ((uint16_t volatile *)CAN_MB16_ID1) /* Mailbox 16 Identifier High Register */ -#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1) -#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val) -#define pCAN_MB17_DATA0 ((uint16_t volatile *)CAN_MB17_DATA0) /* Mailbox 17 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0) -#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val) -#define pCAN_MB17_DATA1 ((uint16_t volatile *)CAN_MB17_DATA1) /* Mailbox 17 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1) -#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val) -#define pCAN_MB17_DATA2 ((uint16_t volatile *)CAN_MB17_DATA2) /* Mailbox 17 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2) -#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val) -#define pCAN_MB17_DATA3 ((uint16_t volatile *)CAN_MB17_DATA3) /* Mailbox 17 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3) -#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val) -#define pCAN_MB17_LENGTH ((uint16_t volatile *)CAN_MB17_LENGTH) /* Mailbox 17 Data Length Code Register */ -#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH) -#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val) -#define pCAN_MB17_TIMESTAMP ((uint16_t volatile *)CAN_MB17_TIMESTAMP) /* Mailbox 17 Time Stamp Value Register */ -#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP) -#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val) -#define pCAN_MB17_ID0 ((uint16_t volatile *)CAN_MB17_ID0) /* Mailbox 17 Identifier Low Register */ -#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0) -#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val) -#define pCAN_MB17_ID1 ((uint16_t volatile *)CAN_MB17_ID1) /* Mailbox 17 Identifier High Register */ -#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1) -#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val) -#define pCAN_MB18_DATA0 ((uint16_t volatile *)CAN_MB18_DATA0) /* Mailbox 18 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0) -#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val) -#define pCAN_MB18_DATA1 ((uint16_t volatile *)CAN_MB18_DATA1) /* Mailbox 18 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1) -#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val) -#define pCAN_MB18_DATA2 ((uint16_t volatile *)CAN_MB18_DATA2) /* Mailbox 18 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2) -#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val) -#define pCAN_MB18_DATA3 ((uint16_t volatile *)CAN_MB18_DATA3) /* Mailbox 18 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3) -#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val) -#define pCAN_MB18_LENGTH ((uint16_t volatile *)CAN_MB18_LENGTH) /* Mailbox 18 Data Length Code Register */ -#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH) -#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val) -#define pCAN_MB18_TIMESTAMP ((uint16_t volatile *)CAN_MB18_TIMESTAMP) /* Mailbox 18 Time Stamp Value Register */ -#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP) -#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val) -#define pCAN_MB18_ID0 ((uint16_t volatile *)CAN_MB18_ID0) /* Mailbox 18 Identifier Low Register */ -#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0) -#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val) -#define pCAN_MB18_ID1 ((uint16_t volatile *)CAN_MB18_ID1) /* Mailbox 18 Identifier High Register */ -#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1) -#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val) -#define pCAN_MB19_DATA0 ((uint16_t volatile *)CAN_MB19_DATA0) /* Mailbox 19 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0) -#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val) -#define pCAN_MB19_DATA1 ((uint16_t volatile *)CAN_MB19_DATA1) /* Mailbox 19 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1) -#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val) -#define pCAN_MB19_DATA2 ((uint16_t volatile *)CAN_MB19_DATA2) /* Mailbox 19 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2) -#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val) -#define pCAN_MB19_DATA3 ((uint16_t volatile *)CAN_MB19_DATA3) /* Mailbox 19 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3) -#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val) -#define pCAN_MB19_LENGTH ((uint16_t volatile *)CAN_MB19_LENGTH) /* Mailbox 19 Data Length Code Register */ -#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH) -#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val) -#define pCAN_MB19_TIMESTAMP ((uint16_t volatile *)CAN_MB19_TIMESTAMP) /* Mailbox 19 Time Stamp Value Register */ -#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP) -#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val) -#define pCAN_MB19_ID0 ((uint16_t volatile *)CAN_MB19_ID0) /* Mailbox 19 Identifier Low Register */ -#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0) -#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val) -#define pCAN_MB19_ID1 ((uint16_t volatile *)CAN_MB19_ID1) /* Mailbox 19 Identifier High Register */ -#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1) -#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val) -#define pCAN_MB20_DATA0 ((uint16_t volatile *)CAN_MB20_DATA0) /* Mailbox 20 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0) -#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val) -#define pCAN_MB20_DATA1 ((uint16_t volatile *)CAN_MB20_DATA1) /* Mailbox 20 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1) -#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val) -#define pCAN_MB20_DATA2 ((uint16_t volatile *)CAN_MB20_DATA2) /* Mailbox 20 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2) -#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val) -#define pCAN_MB20_DATA3 ((uint16_t volatile *)CAN_MB20_DATA3) /* Mailbox 20 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3) -#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val) -#define pCAN_MB20_LENGTH ((uint16_t volatile *)CAN_MB20_LENGTH) /* Mailbox 20 Data Length Code Register */ -#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH) -#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val) -#define pCAN_MB20_TIMESTAMP ((uint16_t volatile *)CAN_MB20_TIMESTAMP) /* Mailbox 20 Time Stamp Value Register */ -#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP) -#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val) -#define pCAN_MB20_ID0 ((uint16_t volatile *)CAN_MB20_ID0) /* Mailbox 20 Identifier Low Register */ -#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0) -#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val) -#define pCAN_MB20_ID1 ((uint16_t volatile *)CAN_MB20_ID1) /* Mailbox 20 Identifier High Register */ -#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1) -#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val) -#define pCAN_MB21_DATA0 ((uint16_t volatile *)CAN_MB21_DATA0) /* Mailbox 21 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0) -#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val) -#define pCAN_MB21_DATA1 ((uint16_t volatile *)CAN_MB21_DATA1) /* Mailbox 21 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1) -#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val) -#define pCAN_MB21_DATA2 ((uint16_t volatile *)CAN_MB21_DATA2) /* Mailbox 21 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2) -#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val) -#define pCAN_MB21_DATA3 ((uint16_t volatile *)CAN_MB21_DATA3) /* Mailbox 21 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3) -#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val) -#define pCAN_MB21_LENGTH ((uint16_t volatile *)CAN_MB21_LENGTH) /* Mailbox 21 Data Length Code Register */ -#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH) -#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val) -#define pCAN_MB21_TIMESTAMP ((uint16_t volatile *)CAN_MB21_TIMESTAMP) /* Mailbox 21 Time Stamp Value Register */ -#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP) -#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val) -#define pCAN_MB21_ID0 ((uint16_t volatile *)CAN_MB21_ID0) /* Mailbox 21 Identifier Low Register */ -#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0) -#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val) -#define pCAN_MB21_ID1 ((uint16_t volatile *)CAN_MB21_ID1) /* Mailbox 21 Identifier High Register */ -#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1) -#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val) -#define pCAN_MB22_DATA0 ((uint16_t volatile *)CAN_MB22_DATA0) /* Mailbox 22 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0) -#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val) -#define pCAN_MB22_DATA1 ((uint16_t volatile *)CAN_MB22_DATA1) /* Mailbox 22 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1) -#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val) -#define pCAN_MB22_DATA2 ((uint16_t volatile *)CAN_MB22_DATA2) /* Mailbox 22 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2) -#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val) -#define pCAN_MB22_DATA3 ((uint16_t volatile *)CAN_MB22_DATA3) /* Mailbox 22 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3) -#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val) -#define pCAN_MB22_LENGTH ((uint16_t volatile *)CAN_MB22_LENGTH) /* Mailbox 22 Data Length Code Register */ -#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH) -#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val) -#define pCAN_MB22_TIMESTAMP ((uint16_t volatile *)CAN_MB22_TIMESTAMP) /* Mailbox 22 Time Stamp Value Register */ -#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP) -#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val) -#define pCAN_MB22_ID0 ((uint16_t volatile *)CAN_MB22_ID0) /* Mailbox 22 Identifier Low Register */ -#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0) -#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val) -#define pCAN_MB22_ID1 ((uint16_t volatile *)CAN_MB22_ID1) /* Mailbox 22 Identifier High Register */ -#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1) -#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val) -#define pCAN_MB23_DATA0 ((uint16_t volatile *)CAN_MB23_DATA0) /* Mailbox 23 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0) -#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val) -#define pCAN_MB23_DATA1 ((uint16_t volatile *)CAN_MB23_DATA1) /* Mailbox 23 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1) -#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val) -#define pCAN_MB23_DATA2 ((uint16_t volatile *)CAN_MB23_DATA2) /* Mailbox 23 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2) -#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val) -#define pCAN_MB23_DATA3 ((uint16_t volatile *)CAN_MB23_DATA3) /* Mailbox 23 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3) -#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val) -#define pCAN_MB23_LENGTH ((uint16_t volatile *)CAN_MB23_LENGTH) /* Mailbox 23 Data Length Code Register */ -#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH) -#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val) -#define pCAN_MB23_TIMESTAMP ((uint16_t volatile *)CAN_MB23_TIMESTAMP) /* Mailbox 23 Time Stamp Value Register */ -#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP) -#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val) -#define pCAN_MB23_ID0 ((uint16_t volatile *)CAN_MB23_ID0) /* Mailbox 23 Identifier Low Register */ -#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0) -#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val) -#define pCAN_MB23_ID1 ((uint16_t volatile *)CAN_MB23_ID1) /* Mailbox 23 Identifier High Register */ -#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1) -#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val) -#define pCAN_MB24_DATA0 ((uint16_t volatile *)CAN_MB24_DATA0) /* Mailbox 24 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0) -#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val) -#define pCAN_MB24_DATA1 ((uint16_t volatile *)CAN_MB24_DATA1) /* Mailbox 24 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1) -#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val) -#define pCAN_MB24_DATA2 ((uint16_t volatile *)CAN_MB24_DATA2) /* Mailbox 24 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2) -#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val) -#define pCAN_MB24_DATA3 ((uint16_t volatile *)CAN_MB24_DATA3) /* Mailbox 24 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3) -#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val) -#define pCAN_MB24_LENGTH ((uint16_t volatile *)CAN_MB24_LENGTH) /* Mailbox 24 Data Length Code Register */ -#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH) -#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val) -#define pCAN_MB24_TIMESTAMP ((uint16_t volatile *)CAN_MB24_TIMESTAMP) /* Mailbox 24 Time Stamp Value Register */ -#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP) -#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val) -#define pCAN_MB24_ID0 ((uint16_t volatile *)CAN_MB24_ID0) /* Mailbox 24 Identifier Low Register */ -#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0) -#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val) -#define pCAN_MB24_ID1 ((uint16_t volatile *)CAN_MB24_ID1) /* Mailbox 24 Identifier High Register */ -#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1) -#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val) -#define pCAN_MB25_DATA0 ((uint16_t volatile *)CAN_MB25_DATA0) /* Mailbox 25 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0) -#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val) -#define pCAN_MB25_DATA1 ((uint16_t volatile *)CAN_MB25_DATA1) /* Mailbox 25 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1) -#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val) -#define pCAN_MB25_DATA2 ((uint16_t volatile *)CAN_MB25_DATA2) /* Mailbox 25 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2) -#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val) -#define pCAN_MB25_DATA3 ((uint16_t volatile *)CAN_MB25_DATA3) /* Mailbox 25 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3) -#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val) -#define pCAN_MB25_LENGTH ((uint16_t volatile *)CAN_MB25_LENGTH) /* Mailbox 25 Data Length Code Register */ -#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH) -#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val) -#define pCAN_MB25_TIMESTAMP ((uint16_t volatile *)CAN_MB25_TIMESTAMP) /* Mailbox 25 Time Stamp Value Register */ -#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP) -#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val) -#define pCAN_MB25_ID0 ((uint16_t volatile *)CAN_MB25_ID0) /* Mailbox 25 Identifier Low Register */ -#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0) -#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val) -#define pCAN_MB25_ID1 ((uint16_t volatile *)CAN_MB25_ID1) /* Mailbox 25 Identifier High Register */ -#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1) -#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val) -#define pCAN_MB26_DATA0 ((uint16_t volatile *)CAN_MB26_DATA0) /* Mailbox 26 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0) -#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val) -#define pCAN_MB26_DATA1 ((uint16_t volatile *)CAN_MB26_DATA1) /* Mailbox 26 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1) -#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val) -#define pCAN_MB26_DATA2 ((uint16_t volatile *)CAN_MB26_DATA2) /* Mailbox 26 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2) -#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val) -#define pCAN_MB26_DATA3 ((uint16_t volatile *)CAN_MB26_DATA3) /* Mailbox 26 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3) -#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val) -#define pCAN_MB26_LENGTH ((uint16_t volatile *)CAN_MB26_LENGTH) /* Mailbox 26 Data Length Code Register */ -#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH) -#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val) -#define pCAN_MB26_TIMESTAMP ((uint16_t volatile *)CAN_MB26_TIMESTAMP) /* Mailbox 26 Time Stamp Value Register */ -#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP) -#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val) -#define pCAN_MB26_ID0 ((uint16_t volatile *)CAN_MB26_ID0) /* Mailbox 26 Identifier Low Register */ -#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0) -#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val) -#define pCAN_MB26_ID1 ((uint16_t volatile *)CAN_MB26_ID1) /* Mailbox 26 Identifier High Register */ -#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1) -#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val) -#define pCAN_MB27_DATA0 ((uint16_t volatile *)CAN_MB27_DATA0) /* Mailbox 27 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0) -#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val) -#define pCAN_MB27_DATA1 ((uint16_t volatile *)CAN_MB27_DATA1) /* Mailbox 27 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1) -#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val) -#define pCAN_MB27_DATA2 ((uint16_t volatile *)CAN_MB27_DATA2) /* Mailbox 27 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2) -#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val) -#define pCAN_MB27_DATA3 ((uint16_t volatile *)CAN_MB27_DATA3) /* Mailbox 27 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3) -#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val) -#define pCAN_MB27_LENGTH ((uint16_t volatile *)CAN_MB27_LENGTH) /* Mailbox 27 Data Length Code Register */ -#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH) -#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val) -#define pCAN_MB27_TIMESTAMP ((uint16_t volatile *)CAN_MB27_TIMESTAMP) /* Mailbox 27 Time Stamp Value Register */ -#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP) -#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val) -#define pCAN_MB27_ID0 ((uint16_t volatile *)CAN_MB27_ID0) /* Mailbox 27 Identifier Low Register */ -#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0) -#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val) -#define pCAN_MB27_ID1 ((uint16_t volatile *)CAN_MB27_ID1) /* Mailbox 27 Identifier High Register */ -#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1) -#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val) -#define pCAN_MB28_DATA0 ((uint16_t volatile *)CAN_MB28_DATA0) /* Mailbox 28 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0) -#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val) -#define pCAN_MB28_DATA1 ((uint16_t volatile *)CAN_MB28_DATA1) /* Mailbox 28 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1) -#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val) -#define pCAN_MB28_DATA2 ((uint16_t volatile *)CAN_MB28_DATA2) /* Mailbox 28 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2) -#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val) -#define pCAN_MB28_DATA3 ((uint16_t volatile *)CAN_MB28_DATA3) /* Mailbox 28 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3) -#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val) -#define pCAN_MB28_LENGTH ((uint16_t volatile *)CAN_MB28_LENGTH) /* Mailbox 28 Data Length Code Register */ -#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH) -#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val) -#define pCAN_MB28_TIMESTAMP ((uint16_t volatile *)CAN_MB28_TIMESTAMP) /* Mailbox 28 Time Stamp Value Register */ -#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP) -#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val) -#define pCAN_MB28_ID0 ((uint16_t volatile *)CAN_MB28_ID0) /* Mailbox 28 Identifier Low Register */ -#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0) -#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val) -#define pCAN_MB28_ID1 ((uint16_t volatile *)CAN_MB28_ID1) /* Mailbox 28 Identifier High Register */ -#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1) -#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val) -#define pCAN_MB29_DATA0 ((uint16_t volatile *)CAN_MB29_DATA0) /* Mailbox 29 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0) -#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val) -#define pCAN_MB29_DATA1 ((uint16_t volatile *)CAN_MB29_DATA1) /* Mailbox 29 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1) -#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val) -#define pCAN_MB29_DATA2 ((uint16_t volatile *)CAN_MB29_DATA2) /* Mailbox 29 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2) -#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val) -#define pCAN_MB29_DATA3 ((uint16_t volatile *)CAN_MB29_DATA3) /* Mailbox 29 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3) -#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val) -#define pCAN_MB29_LENGTH ((uint16_t volatile *)CAN_MB29_LENGTH) /* Mailbox 29 Data Length Code Register */ -#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH) -#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val) -#define pCAN_MB29_TIMESTAMP ((uint16_t volatile *)CAN_MB29_TIMESTAMP) /* Mailbox 29 Time Stamp Value Register */ -#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP) -#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val) -#define pCAN_MB29_ID0 ((uint16_t volatile *)CAN_MB29_ID0) /* Mailbox 29 Identifier Low Register */ -#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0) -#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val) -#define pCAN_MB29_ID1 ((uint16_t volatile *)CAN_MB29_ID1) /* Mailbox 29 Identifier High Register */ -#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1) -#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val) -#define pCAN_MB30_DATA0 ((uint16_t volatile *)CAN_MB30_DATA0) /* Mailbox 30 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0) -#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val) -#define pCAN_MB30_DATA1 ((uint16_t volatile *)CAN_MB30_DATA1) /* Mailbox 30 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1) -#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val) -#define pCAN_MB30_DATA2 ((uint16_t volatile *)CAN_MB30_DATA2) /* Mailbox 30 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2) -#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val) -#define pCAN_MB30_DATA3 ((uint16_t volatile *)CAN_MB30_DATA3) /* Mailbox 30 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3) -#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val) -#define pCAN_MB30_LENGTH ((uint16_t volatile *)CAN_MB30_LENGTH) /* Mailbox 30 Data Length Code Register */ -#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH) -#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val) -#define pCAN_MB30_TIMESTAMP ((uint16_t volatile *)CAN_MB30_TIMESTAMP) /* Mailbox 30 Time Stamp Value Register */ -#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP) -#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val) -#define pCAN_MB30_ID0 ((uint16_t volatile *)CAN_MB30_ID0) /* Mailbox 30 Identifier Low Register */ -#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0) -#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val) -#define pCAN_MB30_ID1 ((uint16_t volatile *)CAN_MB30_ID1) /* Mailbox 30 Identifier High Register */ -#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1) -#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val) -#define pCAN_MB31_DATA0 ((uint16_t volatile *)CAN_MB31_DATA0) /* Mailbox 31 Data Word 0 [15:0] Register */ -#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0) -#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val) -#define pCAN_MB31_DATA1 ((uint16_t volatile *)CAN_MB31_DATA1) /* Mailbox 31 Data Word 1 [31:16] Register */ -#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1) -#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val) -#define pCAN_MB31_DATA2 ((uint16_t volatile *)CAN_MB31_DATA2) /* Mailbox 31 Data Word 2 [47:32] Register */ -#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2) -#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val) -#define pCAN_MB31_DATA3 ((uint16_t volatile *)CAN_MB31_DATA3) /* Mailbox 31 Data Word 3 [63:48] Register */ -#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3) -#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val) -#define pCAN_MB31_LENGTH ((uint16_t volatile *)CAN_MB31_LENGTH) /* Mailbox 31 Data Length Code Register */ -#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH) -#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val) -#define pCAN_MB31_TIMESTAMP ((uint16_t volatile *)CAN_MB31_TIMESTAMP) /* Mailbox 31 Time Stamp Value Register */ -#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP) -#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val) -#define pCAN_MB31_ID0 ((uint16_t volatile *)CAN_MB31_ID0) /* Mailbox 31 Identifier Low Register */ -#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0) -#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val) -#define pCAN_MB31_ID1 ((uint16_t volatile *)CAN_MB31_ID1) /* Mailbox 31 Identifier High Register */ -#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) -#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */ -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */ -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORT_MUX ((uint16_t volatile *)PORT_MUX) /* Port Multiplexer Control Register */ -#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) -#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */ -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */ -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */ -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */ -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */ -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */ -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */ -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */ -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* L1 Data Memory Controller Register */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) -#define pPFCTL ((uint32_t volatile *)PFCTL) -#define bfin_read_PFCTL() bfin_read32(PFCTL) -#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) -#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) -#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) -#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) -#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) -#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) -#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) -#define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) -#define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER) -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_BF534_extended__ */ diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h deleted file mode 100644 index 61ffa14..0000000 --- a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_def.h +++ /dev/null @@ -1,924 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_BF534_extended__ -#define __BFIN_DEF_ADSP_EDN_BF534_extended__ - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration Register */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ -#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ -#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ -#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ -#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ -#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ -#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ -#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ -#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ -#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ -#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ -#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ -#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ -#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ -#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ -#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ -#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ -#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ -#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ -#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ -#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ -#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ -#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ -#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ -#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ -#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ -#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ -#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ -#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ -#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ -#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ -#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ -#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ -#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ -#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ -#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ -#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ -#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ -#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ -#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ -#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ -#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ -#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ -#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ -#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ -#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ -#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ -#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ -#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ -#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ -#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ -#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ -#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ -#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ -#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ -#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ -#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ -#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ -#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ -#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ -#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ -#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ -#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ -#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ -#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ -#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ -#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ -#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ -#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ -#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ -#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ -#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ -#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ -#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ -#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ -#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ -#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ -#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ -#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ -#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ -#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ -#define CAN_DEBUG 0xFFC02A88 /* Config register */ -#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ -#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ -#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ -#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ -#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ -#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ -#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ -#define CAN_VERSION 0xFFC02AA8 /* Version Code Register */ -#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ -#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ -#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ -#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ -#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ -#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ -#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ -#define CAN_VERSION2 0xFFC02AD4 /* Version Code Register 2 */ -#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ -#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ -#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ -#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ -#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ -#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ -#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ -#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ -#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ -#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ -#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ -#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ -#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ -#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ -#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ -#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ -#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ -#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ -#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ -#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ -#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ -#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ -#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ -#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ -#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ -#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ -#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ -#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ -#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ -#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ -#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ -#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ -#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ -#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ -#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ -#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ -#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ -#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ -#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ -#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ -#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ -#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ -#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ -#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ -#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ -#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ -#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ -#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ -#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ -#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ -#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ -#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ -#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ -#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ -#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ -#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ -#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ -#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ -#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ -#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ -#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ -#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ -#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ -#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ -#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ -#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ -#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ -#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ -#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ -#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ -#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ -#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ -#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ -#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ -#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ -#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ -#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ -#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ -#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ -#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ -#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ -#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ -#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ -#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ -#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ -#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ -#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ -#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ -#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ -#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ -#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ -#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ -#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ -#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ -#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ -#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ -#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ -#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ -#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ -#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ -#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ -#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ -#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ -#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ -#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ -#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ -#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ -#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ -#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ -#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ -#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ -#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ -#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ -#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ -#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ -#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ -#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ -#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ -#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ -#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ -#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ -#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ -#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ -#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ -#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ -#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ -#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ -#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ -#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ -#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ -#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ -#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ -#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ -#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ -#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ -#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ -#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ -#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ -#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ -#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ -#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ -#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ -#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ -#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ -#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ -#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ -#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ -#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ -#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ -#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ -#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ -#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ -#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ -#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ -#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ -#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ -#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ -#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ -#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ -#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ -#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ -#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ -#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ -#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ -#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ -#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ -#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ -#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ -#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ -#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ -#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ -#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ -#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ -#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ -#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ -#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ -#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ -#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ -#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ -#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ -#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ -#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ -#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ -#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ -#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ -#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ -#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ -#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ -#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ -#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ -#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ -#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ -#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ -#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ -#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ -#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ -#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ -#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ -#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ -#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ -#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ -#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ -#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ -#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ -#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ -#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ -#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ -#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ -#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ -#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ -#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ -#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ -#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ -#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ -#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ -#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ -#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ -#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ -#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ -#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ -#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ -#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ -#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ -#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ -#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ -#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ -#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ -#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ -#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ -#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ -#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ -#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ -#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ -#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ -#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ -#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ -#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ -#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ -#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ -#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ -#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ -#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ -#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ -#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ -#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ -#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ -#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ -#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ -#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ -#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ -#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ -#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ -#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ -#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ -#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ -#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ -#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ -#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ -#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ -#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ -#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ -#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ -#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ -#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ -#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ -#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ -#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ -#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ -#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ -#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ -#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ -#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ -#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ -#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ -#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ -#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ -#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ -#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ -#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ -#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ -#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ -#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ -#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ -#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ -#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ -#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ -#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ -#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ -#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ -#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ -#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ -#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ -#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ -#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ -#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ -#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ -#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ -#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ -#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ -#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ -#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ -#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ -#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ -#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ -#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ -#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ -#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ -#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ -#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ -#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ -#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ -#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ -#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ -#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ -#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ -#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ -#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ -#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ -#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ -#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ -#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ -#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ -#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ -#define PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ -#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ -#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* L1 Data Memory Controller Register */ -#define DCPLB_FAULT_ADDR 0xFFE0000C -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 -#define ICPLB_FAULT_ADDR 0xFFE0100C -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define CHIPID 0xFFC00014 -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ -#define PFCTL 0xFFE08000 -#define PFCNTR0 0xFFE08100 -#define PFCNTR1 0xFFE08104 -#define DMA_TC_CNT 0xFFC00B0C -#define DMA_TC_PER 0xFFC00B10 - -#endif /* __BFIN_DEF_ADSP_EDN_BF534_extended__ */ diff --git a/include/asm-blackfin/mach-bf537/BF534_cdef.h b/include/asm-blackfin/mach-bf537/BF534_cdef.h deleted file mode 100644 index 27842cc..0000000 --- a/include/asm-blackfin/mach-bf537/BF534_cdef.h +++ /dev/null @@ -1,14 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF534_proc__ -#define __BFIN_CDEF_ADSP_BF534_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF534-extended_cdef.h" - - -#endif /* __BFIN_CDEF_ADSP_BF534_proc__ */ diff --git a/include/asm-blackfin/mach-bf537/BF534_def.h b/include/asm-blackfin/mach-bf537/BF534_def.h deleted file mode 100644 index 5f0437b..0000000 --- a/include/asm-blackfin/mach-bf537/BF534_def.h +++ /dev/null @@ -1,29 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF534_proc__ -#define __BFIN_DEF_ADSP_BF534_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF534-extended_def.h" - -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) - -#endif /* __BFIN_DEF_ADSP_BF534_proc__ */ diff --git a/include/asm-blackfin/mach-bf537/BF536_cdef.h b/include/asm-blackfin/mach-bf537/BF536_cdef.h deleted file mode 100644 index d753b5e..0000000 --- a/include/asm-blackfin/mach-bf537/BF536_cdef.h +++ /dev/null @@ -1,251 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF536_proc__ -#define __BFIN_CDEF_ADSP_BF536_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF534-extended_cdef.h" - -#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */ -#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) -#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */ -#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) -#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */ -#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) -#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */ -#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) -#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */ -#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) -#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */ -#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) -#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */ -#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) -#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */ -#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) -#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */ -#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) -#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */ -#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) -#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */ -#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) -#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) -#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) -#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) -#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) -#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */ -#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) -#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */ -#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) -#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) -#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) -#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) -#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */ -#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) -#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */ -#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) -#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */ -#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) -#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */ -#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) -#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) -#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */ -#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) -#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */ -#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) -#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) -#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) -#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */ -#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) -#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) -#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) -#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) -#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) -#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) -#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */ -#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) -#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */ -#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) -#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */ -#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) -#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */ -#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) -#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */ -#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) -#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */ -#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) -#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */ -#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) -#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */ -#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) -#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) -#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) -#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */ -#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) -#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */ -#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) -#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */ -#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) -#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */ -#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) -#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */ -#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) -#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */ -#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) -#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */ -#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) -#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */ -#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) -#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) -#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) -#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) -#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) -#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) -#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) -#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) -#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */ -#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) -#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */ -#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) -#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */ -#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) -#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */ -#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) -#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */ -#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) -#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */ -#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) -#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */ -#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) -#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */ -#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) -#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */ -#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) -#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */ -#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) -#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */ -#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) -#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */ -#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) -#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */ -#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) -#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */ -#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) -#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */ -#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) -#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */ -#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) -#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) -#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) -#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) -#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) -#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) -#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) -#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */ -#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) -#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) - -#endif /* __BFIN_CDEF_ADSP_BF536_proc__ */ diff --git a/include/asm-blackfin/mach-bf537/BF536_def.h b/include/asm-blackfin/mach-bf537/BF536_def.h deleted file mode 100644 index 810fe91..0000000 --- a/include/asm-blackfin/mach-bf537/BF536_def.h +++ /dev/null @@ -1,102 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF536_proc__ -#define __BFIN_DEF_ADSP_BF536_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF534-extended_def.h" - -#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ -#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ -#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ -#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ -#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ -#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ -#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ -#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ -#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ -#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ -#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ -#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ -#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ -#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ -#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ -#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ -#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ -#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ -#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ -#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ -#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ -#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ -#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ -#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ -#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ -#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ -#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ -#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ -#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ -#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ -#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ -#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ -#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ -#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ -#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ -#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ -#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ -#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ -#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ -#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ -#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ -#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ -#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ -#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ -#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ -#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ -#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ -#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ -#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ -#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ -#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ -#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ -#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ -#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ -#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ -#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ -#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ -#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ -#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ -#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ -#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ -#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ -#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) - -#endif /* __BFIN_DEF_ADSP_BF536_proc__ */ diff --git a/include/asm-blackfin/mach-bf537/BF537_cdef.h b/include/asm-blackfin/mach-bf537/BF537_cdef.h deleted file mode 100644 index 5eff57d..0000000 --- a/include/asm-blackfin/mach-bf537/BF537_cdef.h +++ /dev/null @@ -1,251 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF537_proc__ -#define __BFIN_CDEF_ADSP_BF537_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF534-extended_cdef.h" - -#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */ -#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) -#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */ -#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) -#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */ -#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) -#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */ -#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) -#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */ -#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) -#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */ -#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) -#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */ -#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) -#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */ -#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) -#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */ -#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) -#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */ -#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) -#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */ -#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) -#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) -#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) -#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) -#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) -#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */ -#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) -#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */ -#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) -#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) -#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) -#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) -#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */ -#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) -#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */ -#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) -#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */ -#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) -#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */ -#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) -#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) -#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */ -#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) -#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */ -#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) -#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) -#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) -#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */ -#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) -#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) -#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) -#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) -#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) -#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) -#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */ -#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) -#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */ -#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) -#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */ -#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) -#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */ -#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) -#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */ -#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) -#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */ -#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) -#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */ -#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) -#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */ -#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) -#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) -#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) -#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */ -#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) -#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */ -#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) -#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */ -#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) -#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */ -#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) -#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */ -#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) -#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */ -#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) -#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */ -#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) -#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */ -#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) -#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) -#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) -#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) -#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) -#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) -#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) -#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) -#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */ -#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) -#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */ -#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) -#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */ -#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) -#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */ -#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) -#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */ -#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) -#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */ -#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) -#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */ -#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) -#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */ -#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) -#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */ -#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) -#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */ -#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) -#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */ -#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) -#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */ -#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) -#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */ -#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) -#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */ -#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) -#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */ -#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) -#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */ -#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) -#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) -#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) -#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) -#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) -#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) -#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) -#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */ -#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) -#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) - -#endif /* __BFIN_CDEF_ADSP_BF537_proc__ */ diff --git a/include/asm-blackfin/mach-bf537/BF537_def.h b/include/asm-blackfin/mach-bf537/BF537_def.h deleted file mode 100644 index 030fa64..0000000 --- a/include/asm-blackfin/mach-bf537/BF537_def.h +++ /dev/null @@ -1,108 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF537_proc__ -#define __BFIN_DEF_ADSP_BF537_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF534-extended_def.h" - -#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ -#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ -#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ -#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ -#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ -#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ -#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ -#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ -#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ -#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ -#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ -#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ -#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ -#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ -#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ -#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ -#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ -#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ -#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ -#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ -#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ -#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ -#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ -#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ -#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ -#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ -#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ -#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ -#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ -#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ -#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ -#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ -#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ -#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ -#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ -#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ -#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ -#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ -#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ -#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ -#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ -#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ -#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ -#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ -#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ -#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ -#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ -#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ -#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ -#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ -#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ -#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ -#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ -#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ -#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ -#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ -#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ -#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ -#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ -#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ -#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ -#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ -#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) - -#endif /* __BFIN_DEF_ADSP_BF537_proc__ */ diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h deleted file mode 100644 index b7f1a3f..0000000 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * File: include/asm-blackfin/mach-bf537/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -/* This file should be up to date with: - * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.1 silicon - sorry */ -#if __SILICON_REVISION__ < 2 -# error will not work on BF537 silicon version 0.0 or 0.1 -#endif - -#if defined(__ADSPBF534__) -# define ANOMALY_BF534 1 -#else -# define ANOMALY_BF534 0 -#endif -#if defined(__ADSPBF536__) -# define ANOMALY_BF536 1 -#else -# define ANOMALY_BF536 0 -#endif -#if defined(__ADSPBF537__) -# define ANOMALY_BF537 1 -#else -# define ANOMALY_BF537 0 -#endif - -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ -#define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) -/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ -#define ANOMALY_05000180 (1) -/* Instruction Cache Is Not Functional */ -#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ -#define ANOMALY_05000247 (1) -/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ -#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) -/* EMAC Tx DMA error after an early frame abort */ -#define ANOMALY_05000252 (__SILICON_REVISION__ < 3) -/* Maximum External Clock Speed for Timers */ -#define ANOMALY_05000253 (__SILICON_REVISION__ < 3) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ -#define ANOMALY_05000254 (__SILICON_REVISION__ > 2) -/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ -#define ANOMALY_05000255 (__SILICON_REVISION__ < 3) -/* EMAC MDIO input latched on wrong MDC edge */ -#define ANOMALY_05000256 (__SILICON_REVISION__ < 3) -/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ -#define ANOMALY_05000257 (__SILICON_REVISION__ < 3) -/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ -#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) -/* ICPLB_STATUS MMR Register May Be Corrupted */ -#define ANOMALY_05000260 (__SILICON_REVISION__ == 2) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) -/* Stores To Data Cache May Be Lost */ -#define ANOMALY_05000262 (__SILICON_REVISION__ < 3) -/* Hardware Loop Corrupted When Taking an ICPLB Exception */ -#define ANOMALY_05000263 (__SILICON_REVISION__ == 2) -/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ -#define ANOMALY_05000264 (__SILICON_REVISION__ < 3) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (1) -/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ -#define ANOMALY_05000268 (__SILICON_REVISION__ < 3) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ -#define ANOMALY_05000270 (__SILICON_REVISION__ < 3) -/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) -/* Writes to Synchronous SDRAM Memory May Be Lost */ -#define ANOMALY_05000273 (__SILICON_REVISION__ < 3) -/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) -/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) -/* SPI Master boot mode does not work well with Atmel Data flash devices */ -#define ANOMALY_05000280 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) -/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ -#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ -#define ANOMALY_05000283 (__SILICON_REVISION__ < 3) -/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ -#define ANOMALY_05000285 (__SILICON_REVISION__ < 3) -/* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (__SILICON_REVISION__ < 3) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) -/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) -/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ -#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) -/* SCKELOW Bit Does Not Maintain State Through Hibernate */ -#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) -/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ -#define ANOMALY_05000309 (__SILICON_REVISION__ < 3) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) -/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ -#define ANOMALY_05000315 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: collisions occur in Full Duplex mode */ -#define ANOMALY_05000316 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ -#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ -#define ANOMALY_05000322 (1) -/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ -#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) -/* New Feature: UART Remains Enabled after UART Boot */ -#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) -/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (1) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) -/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ -#define ANOMALY_05000359 (1) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000125 (0) -#define ANOMALY_05000158 (0) -#define ANOMALY_05000171 (0) -#define ANOMALY_05000183 (0) -#define ANOMALY_05000198 (0) -#define ANOMALY_05000227 (0) -#define ANOMALY_05000230 (0) -#define ANOMALY_05000242 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000353 (1) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000363 (0) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000386 (1) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000430 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000435 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) - -#endif diff --git a/include/asm-blackfin/mach-bf537/def_local.h b/include/asm-blackfin/mach-bf537/def_local.h deleted file mode 100644 index 14c111f..0000000 --- a/include/asm-blackfin/mach-bf537/def_local.h +++ /dev/null @@ -1 +0,0 @@ -#include "ports.h" diff --git a/include/asm-blackfin/mach-bf537/ports.h b/include/asm-blackfin/mach-bf537/ports.h deleted file mode 100644 index 2f62934..0000000 --- a/include/asm-blackfin/mach-bf537/ports.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Port Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT__ -#define __BFIN_PERIPHERAL_PORT__ - -/* PORT_MUX Masks */ -#define PJSE 0x0001 -#define PJCE_MASK 0x0006 -#define PJCE_SPORT 0x0000 -#define PJCE_CAN 0x0001 -#define PJCE_SPI 0x0002 -#define PFDE 0x0008 -#define PFTE 0x0010 -#define PFS6E 0x0020 -#define PFS5E 0x0040 -#define PFS4E 0x0080 -#define PFFE 0x0100 -#define PGSE 0x0200 -#define PGRE 0x0400 -#define PGTE 0x0800 - -#include "../mach-common/bits/ports-f.h" -#include "../mach-common/bits/ports-g.h" -#include "../mach-common/bits/ports-h.h" - -#endif diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h deleted file mode 100644 index 51d9cf2..0000000 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h +++ /dev/null @@ -1,4378 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_BF542_extended__ -#define __BFIN_CDEF_ADSP_EDN_BF542_extended__ - -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */ -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */ -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */ -#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) -#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */ -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */ -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */ -#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) -#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */ -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */ -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */ -#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) -#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */ -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */ -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */ -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */ -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */ -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */ -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */ -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */ -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */ -#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) -#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */ -#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) -#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */ -#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) -#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */ -#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) -#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) -#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */ -#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) -#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) -#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */ -#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) -#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) -#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */ -#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) -#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) -#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */ -#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) -#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) -#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */ -#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) -#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ -#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ -#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ -#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ -#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ -#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ -#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ -#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ -#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ -#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ -#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ -#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ -#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ -#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ -#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ -#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ -#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ -#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ -#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ -#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ -#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ -#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ -#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ -#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ -#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */ -#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) -#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */ -#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) -#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */ -#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) -#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */ -#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) -#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */ -#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) -#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */ -#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) -#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */ -#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) -#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */ -#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) -#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */ -#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) -#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */ -#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) -#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */ -#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) -#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */ -#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) -#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */ -#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) -#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */ -#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) -#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */ -#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) -#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */ -#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) -#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */ -#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) -#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */ -#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) -#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */ -#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) -#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */ -#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) -#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */ -#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) -#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */ -#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) -#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */ -#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) -#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */ -#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) -#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */ -#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) -#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */ -#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) -#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */ -#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) -#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */ -#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) -#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */ -#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) -#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */ -#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) -#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */ -#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) -#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */ -#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) -#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */ -#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) -#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */ -#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) -#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */ -#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) -#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */ -#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) -#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */ -#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) -#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */ -#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) -#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */ -#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) -#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */ -#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) -#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */ -#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) -#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */ -#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) -#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */ -#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) -#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */ -#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) -#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */ -#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) -#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */ -#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) -#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */ -#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) -#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */ -#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) -#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */ -#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) -#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */ -#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) -#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */ -#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) -#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */ -#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) -#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */ -#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) -#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */ -#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) -#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */ -#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) -#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */ -#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) -#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */ -#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) -#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */ -#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) -#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */ -#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) -#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */ -#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) -#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */ -#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) -#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */ -#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) -#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */ -#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) -#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */ -#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) -#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */ -#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) -#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */ -#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) -#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */ -#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) -#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */ -#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) -#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */ -#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) -#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */ -#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) -#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */ -#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) -#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */ -#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) -#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */ -#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) -#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */ -#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) -#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */ -#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) -#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */ -#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) -#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */ -#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) -#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */ -#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) -#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */ -#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) -#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */ -#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) -#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */ -#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) -#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */ -#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) -#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */ -#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) -#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */ -#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) -#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */ -#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) -#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */ -#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) -#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */ -#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) -#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */ -#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) -#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */ -#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) -#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */ -#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) -#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */ -#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) -#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */ -#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) -#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */ -#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) -#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */ -#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) -#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */ -#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) -#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */ -#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) -#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */ -#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) -#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */ -#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) -#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */ -#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) -#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */ -#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) -#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */ -#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) -#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */ -#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) -#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */ -#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) -#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */ -#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) -#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */ -#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR) -#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val) -#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */ -#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR) -#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val) -#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */ -#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) -#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */ -#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) -#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */ -#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) -#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */ -#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) -#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */ -#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) -#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */ -#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR) -#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val) -#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */ -#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR) -#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val) -#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */ -#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) -#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */ -#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) -#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */ -#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) -#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */ -#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) -#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) -#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */ -#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR) -#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val) -#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */ -#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR) -#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val) -#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */ -#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) -#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */ -#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) -#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */ -#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) -#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */ -#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) -#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */ -#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) -#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */ -#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR) -#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val) -#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */ -#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR) -#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val) -#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */ -#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) -#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */ -#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) -#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */ -#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) -#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */ -#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) -#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) -#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */ -#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR) -#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val) -#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */ -#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR) -#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val) -#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */ -#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) -#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */ -#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) -#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */ -#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) -#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */ -#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) -#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */ -#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) -#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */ -#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR) -#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val) -#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */ -#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR) -#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val) -#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */ -#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) -#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */ -#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) -#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */ -#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) -#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */ -#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) -#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) -#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */ -#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR) -#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val) -#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */ -#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR) -#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val) -#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */ -#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) -#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */ -#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) -#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */ -#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) -#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */ -#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) -#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */ -#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) -#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */ -#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR) -#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val) -#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */ -#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR) -#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val) -#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */ -#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) -#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */ -#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) -#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */ -#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) -#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */ -#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) -#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */ -#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */ -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */ -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */ -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */ -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */ -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */ -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */ -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */ -#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */ -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */ -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */ -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */ -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */ -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */ -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */ -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */ -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */ -#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */ -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */ -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */ -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */ -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */ -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */ -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */ -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */ -#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */ -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */ -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */ -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */ -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */ -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */ -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */ -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */ -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) -#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */ -#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) -#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */ -#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) -#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */ -#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) -#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */ -#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) -#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */ -#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) -#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */ -#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) -#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) -#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */ -#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) -#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) -#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) -#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */ -#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) -#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) -#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) -#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */ -#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) -#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */ -#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) -#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */ -#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) -#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */ -#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) -#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */ -#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) -#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */ -#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) -#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) -#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */ -#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) -#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) -#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) -#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */ -#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) -#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */ -#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) -#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) -#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */ -#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) -#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */ -#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) -#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */ -#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) -#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */ -#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) -#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */ -#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) -#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */ -#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) -#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) -#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */ -#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) -#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) -#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) -#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */ -#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) -#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) -#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) -#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */ -#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) -#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */ -#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) -#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */ -#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) -#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */ -#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) -#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */ -#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) -#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */ -#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) -#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) -#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */ -#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) -#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) -#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) -#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */ -#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) -#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */ -#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) -#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */ -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */ -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */ -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */ -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */ -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */ -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */ -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */ -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */ -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */ -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */ -#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL) -#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val) -#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */ -#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) -#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */ -#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) -#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */ -#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL) -#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val) -#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */ -#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) -#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */ -#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) -#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */ -#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) -#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */ -#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) -#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */ -#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) -#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */ -#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD) -#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val) -#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */ -#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) -#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */ -#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) -#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) -#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */ -#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) -#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */ -#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) -#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */ -#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) -#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */ -#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) -#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */ -#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) -#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */ -#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) -#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */ -#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) -#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */ -#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) -#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */ -#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) -#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */ -#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) -#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */ -#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) -#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */ -#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) -#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */ -#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) -#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */ -#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) -#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */ -#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) -#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */ -#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) -#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */ -#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) -#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */ -#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) -#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */ -#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) -#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */ -#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) -#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */ -#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) -#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */ -#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) -#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */ -#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) -#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */ -#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) -#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */ -#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) -#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) -#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */ -#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) -#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */ -#define bfin_read_PORTA() bfin_read16(PORTA) -#define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) -#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) -#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) -#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) -#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) -#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) -#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */ -#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) -#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */ -#define bfin_read_PORTB() bfin_read16(PORTB) -#define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) -#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) -#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) -#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) -#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) -#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) -#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */ -#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) -#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */ -#define bfin_read_PORTC() bfin_read16(PORTC) -#define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) -#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) -#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) -#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) -#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) -#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) -#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */ -#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) -#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */ -#define bfin_read_PORTD() bfin_read16(PORTD) -#define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) -#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) -#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) -#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) -#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) -#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) -#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */ -#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) -#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */ -#define bfin_read_PORTE() bfin_read16(PORTE) -#define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) -#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) -#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) -#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) -#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) -#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) -#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */ -#define bfin_read_PORTF() bfin_read16(PORTF) -#define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) -#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) -#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) -#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) -#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) -#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */ -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */ -#define bfin_read_PORTG() bfin_read16(PORTG) -#define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) -#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) -#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) -#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) -#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) -#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */ -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */ -#define bfin_read_PORTH() bfin_read16(PORTH) -#define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) -#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) -#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) -#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) -#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) -#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) -#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */ -#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) -#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */ -#define bfin_read_PORTI() bfin_read16(PORTI) -#define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) -#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) -#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) -#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) -#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) -#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) -#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) -#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */ -#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) -#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */ -#define bfin_read_PORTJ() bfin_read16(PORTJ) -#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) -#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) -#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) -#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) -#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) -#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) -#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) -#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */ -#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) -#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */ -#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) -#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */ -#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ) -#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val) -#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */ -#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) -#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) -#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) -#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */ -#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) -#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */ -#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) -#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */ -#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) -#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */ -#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) -#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) -#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */ -#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) -#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */ -#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) -#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */ -#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ) -#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val) -#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */ -#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) -#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) -#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) -#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */ -#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) -#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */ -#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) -#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */ -#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) -#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */ -#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) -#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) -#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */ -#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) -#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */ -#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) -#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */ -#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ) -#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val) -#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */ -#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) -#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) -#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) -#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */ -#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) -#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */ -#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) -#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */ -#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) -#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */ -#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) -#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) -#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */ -#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) -#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */ -#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) -#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */ -#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ) -#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val) -#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */ -#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) -#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) -#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) -#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */ -#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) -#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */ -#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) -#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */ -#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) -#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */ -#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) -#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */ -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */ -#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) -#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */ -#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) -#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */ -#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) -#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */ -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */ -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */ -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */ -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */ -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ -#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) -#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ -#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) -#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ -#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) -#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ -#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) -#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) -#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) -#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) -#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) -#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */ -#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) -#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) -#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */ -#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) -#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) -#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */ -#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) -#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) -#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */ -#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) -#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) -#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */ -#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) -#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) -#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */ -#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) -#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) -#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */ -#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) -#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) -#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */ -#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) -#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) -#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */ -#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) -#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) -#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */ -#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) -#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) -#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */ -#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) -#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) -#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */ -#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) -#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) -#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */ -#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) -#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) -#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */ -#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) -#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) -#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */ -#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) -#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) -#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */ -#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) -#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) -#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */ -#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) -#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) -#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */ -#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) -#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */ -#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) -#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) -#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */ -#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) -#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */ -#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) -#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) -#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */ -#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) -#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) -#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */ -#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) -#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) -#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */ -#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) -#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) -#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */ -#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) -#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) -#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */ -#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) -#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) -#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */ -#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) -#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) -#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */ -#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) -#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) -#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */ -#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) -#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) -#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */ -#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) -#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) -#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */ -#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) -#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) -#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */ -#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) -#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) -#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */ -#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) -#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) -#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */ -#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) -#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) -#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */ -#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) -#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) -#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */ -#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) -#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) -#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */ -#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) -#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) -#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */ -#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) -#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) -#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */ -#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) -#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) -#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */ -#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) -#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) -#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */ -#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) -#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) -#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */ -#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) -#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) -#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */ -#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) -#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) -#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */ -#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) -#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) -#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */ -#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) -#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) -#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */ -#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) -#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) -#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */ -#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) -#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) -#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */ -#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) -#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) -#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */ -#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) -#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) -#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */ -#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) -#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) -#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */ -#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) -#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) -#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */ -#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) -#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) -#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */ -#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) -#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) -#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */ -#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) -#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) -#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */ -#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) -#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) -#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */ -#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) -#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) -#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */ -#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) -#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) -#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */ -#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) -#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) -#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) -#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) -#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) -#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) -#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) -#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) -#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) -#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ -#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) -#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ -#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) -#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ -#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) -#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ -#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) -#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ -#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) -#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ -#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) -#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ -#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) -#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ -#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) -#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ -#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) -#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ -#define bfin_read_NFC_RST() bfin_read16(NFC_RST) -#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ -#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) -#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ -#define bfin_read_NFC_READ() bfin_read16(NFC_READ) -#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ -#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) -#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ -#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) -#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ -#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) -#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ -#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) -#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */ -#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) -#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */ -#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) -#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */ -#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) -#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */ -#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) -#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */ -#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) -#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */ -#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) -#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */ -#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) -#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */ -#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) -#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */ -#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) -#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) -#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) -#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) -#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) -#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */ -#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) -#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) -#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */ -#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) -#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */ -#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) -#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */ -#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) -#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */ -#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) -#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */ -#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) -#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */ -#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) -#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */ -#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) -#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */ -#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) -#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */ -#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) -#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) -#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) -#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) -#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) -#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */ -#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) -#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) -#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */ -#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) -#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) -#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */ -#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) -#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) -#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */ -#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) -#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) -#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */ -#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) -#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) -#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */ -#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) -#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) -#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */ -#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) -#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) -#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */ -#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) -#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) -#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */ -#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) -#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) -#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ -#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) -#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) -#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ -#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) -#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) -#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ -#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) -#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) -#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ -#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) -#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) -#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ -#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) -#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) -#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */ -#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) -#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) -#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */ -#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) -#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) -#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */ -#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) -#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) -#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */ -#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) -#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) -#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */ -#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) -#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) -#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */ -#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) -#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) -#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */ -#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) -#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) -#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */ -#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) -#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) -#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ -#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) -#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) -#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ -#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) -#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) -#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ -#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) -#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) -#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ -#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) -#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) -#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ -#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) -#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) -#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */ -#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) -#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) -#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */ -#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) -#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) -#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */ -#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) -#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) -#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */ -#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) -#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) -#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */ -#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) -#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) -#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */ -#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) -#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) -#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */ -#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) -#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) -#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */ -#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) -#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) -#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */ -#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) -#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) -#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */ -#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) -#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) -#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */ -#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) -#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) -#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */ -#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) -#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) -#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */ -#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) -#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) -#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */ -#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) -#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) -#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */ -#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) -#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) -#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */ -#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) -#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) -#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) -#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) -#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) -#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) -#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) -#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) -#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) -#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) -#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) -#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) -#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) -#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) -#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) -#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) -#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) -#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) -#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) -#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) -#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) -#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) -#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) -#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) -#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) -#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) -#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) -#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) -#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) -#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) -#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) -#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) -#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) -#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) -#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) -#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) -#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) -#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) -#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) -#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) -#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) -#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) -#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) -#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) -#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) -#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) -#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) -#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) -#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) -#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) -#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) -#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) -#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) -#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) -#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) -#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) -#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) -#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) -#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) -#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) -#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) -#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) -#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) -#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) -#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) -#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) -#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) -#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) -#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) -#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) -#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) -#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) -#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) -#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) -#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) -#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) -#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) -#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) -#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) -#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) -#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) -#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) -#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) -#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) -#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) -#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) -#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) -#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) -#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) -#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) -#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) -#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) -#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) -#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) -#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) -#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) -#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) -#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) -#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) -#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) -#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) -#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) -#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) -#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) -#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) -#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) -#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) -#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) -#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) -#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) -#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) -#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) -#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) -#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) -#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) -#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) -#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) -#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) -#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) -#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) -#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) -#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) -#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) -#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) -#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) -#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) -#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) -#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) -#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) -#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) -#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */ -#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) -#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) -#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */ -#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) -#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) -#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */ -#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) -#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) -#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */ -#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) -#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) -#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */ -#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) -#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) -#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */ -#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) -#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) -#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */ -#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) -#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) -#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */ -#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) -#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) -#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */ -#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) -#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) -#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */ -#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) -#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) -#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */ -#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) -#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) -#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */ -#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) -#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) -#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */ -#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) -#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) -#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */ -#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) -#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) -#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */ -#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) -#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) -#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */ -#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) -#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) -#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */ -#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) -#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) -#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */ -#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) -#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) -#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */ -#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) -#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) -#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */ -#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) -#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) -#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */ -#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) -#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) -#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */ -#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) -#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) -#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */ -#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) -#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) -#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */ -#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) -#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) -#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */ -#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) -#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) -#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */ -#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) -#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) -#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */ -#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) -#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) -#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */ -#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) -#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) -#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */ -#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) -#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) -#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */ -#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) -#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) -#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */ -#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) -#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) -#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */ -#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) -#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) -#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */ -#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) -#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) -#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */ -#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) -#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) -#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */ -#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) -#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) -#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */ -#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) -#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) -#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */ -#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) -#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) -#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */ -#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) -#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) -#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */ -#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) -#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) -#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */ -#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) -#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) -#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */ -#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) -#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) -#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */ -#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) -#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) -#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */ -#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) -#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) -#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */ -#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) -#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) -#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */ -#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) -#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) -#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */ -#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) -#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) -#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */ -#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) -#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) -#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */ -#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) -#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) -#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */ -#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) -#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) -#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */ -#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) -#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) -#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */ -#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) -#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) -#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */ -#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) -#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) -#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */ -#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) -#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) -#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */ -#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) -#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) -#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */ -#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) -#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) -#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */ -#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) -#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) -#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */ -#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) -#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) -#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */ -#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) -#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) -#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */ -#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) -#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) -#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */ -#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) -#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) -#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */ -#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) -#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) -#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */ -#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) -#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) -#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */ -#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) -#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) -#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */ -#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) -#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) -#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */ -#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) -#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) -#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */ -#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) -#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) -#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */ -#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) -#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) -#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */ -#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) -#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) -#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */ -#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) -#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) -#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */ -#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) -#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) -#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */ -#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) -#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) -#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */ -#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) -#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) -#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */ -#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) -#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) -#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */ -#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) -#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) -#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */ -#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) -#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) -#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */ -#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) -#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) -#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */ -#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) -#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) -#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */ -#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) -#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) -#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */ -#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) -#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) -#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */ -#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) -#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) -#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */ -#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) -#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) -#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */ -#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) -#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) -#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */ -#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) -#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) -#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */ -#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) -#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) -#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */ -#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) -#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) -#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */ -#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) -#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) -#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */ -#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) -#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) -#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */ -#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) -#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) -#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */ -#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) -#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) -#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */ -#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) -#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) -#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */ -#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) -#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) -#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */ -#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) -#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) -#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */ -#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) -#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) -#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */ -#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) -#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) -#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */ -#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) -#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) -#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */ -#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) -#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) -#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */ -#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) -#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) -#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */ -#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) -#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) -#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */ -#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) -#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) -#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */ -#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) -#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) -#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */ -#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) -#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) -#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */ -#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) -#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) -#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */ -#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) -#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) -#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */ -#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) -#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) -#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */ -#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) -#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) -#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */ -#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) -#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) -#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */ -#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) -#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) -#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */ -#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) -#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) -#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */ -#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) -#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) -#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */ -#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) -#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) -#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */ -#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) -#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) -#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */ -#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) -#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) -#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */ -#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) -#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) -#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */ -#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) -#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) -#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */ -#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) -#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) -#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */ -#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) -#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) -#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */ -#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) -#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) -#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */ -#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) -#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) -#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */ -#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) -#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) -#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */ -#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) -#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) -#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */ -#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) -#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) -#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */ -#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) -#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) -#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */ -#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) -#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) -#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */ -#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) -#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) -#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */ -#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) -#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) -#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */ -#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) -#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) -#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */ -#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) -#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) -#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */ -#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) -#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) -#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */ -#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) -#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) -#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */ -#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) -#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) -#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */ -#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) -#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) -#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */ -#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) -#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) -#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */ -#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) -#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) -#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */ -#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) -#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) -#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */ -#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) -#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) -#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */ -#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) -#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) -#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */ -#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) -#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) -#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */ -#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) -#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) -#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */ -#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) -#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) -#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */ -#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) -#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) -#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */ -#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) -#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) -#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */ -#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) -#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) -#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */ -#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) -#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) -#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */ -#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) -#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) -#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */ -#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) -#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) -#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */ -#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) -#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) -#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */ -#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) -#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) -#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */ -#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) -#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) -#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */ -#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) -#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) -#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */ -#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) -#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) -#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */ -#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) -#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) -#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */ -#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) -#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) -#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */ -#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) -#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) -#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */ -#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) -#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) -#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */ -#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) -#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) -#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */ -#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) -#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) -#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */ -#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) -#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) -#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */ -#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) -#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) -#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */ -#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) -#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) -#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */ -#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) -#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) -#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */ -#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) -#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) -#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */ -#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) -#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) -#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */ -#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) -#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) -#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */ -#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) -#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) -#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */ -#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) -#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) -#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */ -#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) -#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) -#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */ -#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) -#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) -#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */ -#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) -#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) -#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */ -#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) -#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) -#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */ -#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) -#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) -#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */ -#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) -#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) -#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */ -#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) -#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) -#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */ -#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) -#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) -#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */ -#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) -#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) -#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */ -#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) -#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) -#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */ -#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) -#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) -#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */ -#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) -#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) -#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */ -#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) -#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) -#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */ -#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) -#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) -#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */ -#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) -#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) -#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */ -#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) -#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) -#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */ -#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) -#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) -#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */ -#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) -#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) -#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */ -#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) -#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) -#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */ -#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) -#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) -#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */ -#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) -#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) -#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */ -#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) -#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) -#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */ -#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) -#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) -#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */ -#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) -#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) -#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */ -#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) -#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) -#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */ -#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) -#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) -#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */ -#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) -#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) -#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */ -#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) -#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) -#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */ -#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) -#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) -#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */ -#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) -#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) -#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */ -#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) -#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) -#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */ -#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) -#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) -#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */ -#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) -#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) -#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */ -#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) -#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) -#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */ -#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) -#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) -#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */ -#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) -#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) -#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */ -#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) -#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) -#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */ -#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) -#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) -#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */ -#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) -#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) -#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */ -#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) -#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) -#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */ -#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) -#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) -#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */ -#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) -#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) -#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */ -#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) -#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) -#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */ -#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) -#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) -#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */ -#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) -#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) -#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */ -#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) -#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) -#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */ -#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) -#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) -#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */ -#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) -#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) -#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */ -#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) -#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) -#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */ -#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) -#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) -#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */ -#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) -#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) -#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */ -#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) -#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) -#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */ -#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) -#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) -#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */ -#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) -#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) -#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */ -#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) -#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) -#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */ -#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) -#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) -#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */ -#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) -#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) -#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */ -#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) -#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) -#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */ -#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) -#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) -#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */ -#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) -#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) -#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */ -#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) -#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) -#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */ -#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) -#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) -#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */ -#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) -#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) -#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */ -#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) -#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) -#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */ -#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) -#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) -#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */ -#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) -#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) -#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */ -#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) -#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) -#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */ -#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) -#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) -#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */ -#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) -#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) -#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */ -#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) -#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) -#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */ -#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) -#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) -#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */ -#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) -#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) -#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */ -#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) -#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) -#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */ -#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) -#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) -#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */ -#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) -#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) -#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */ -#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) -#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) -#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */ -#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) -#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) -#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */ -#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) -#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) -#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */ -#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) -#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) -#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */ -#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) -#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) -#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */ -#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) -#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) -#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */ -#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) -#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) -#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */ -#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) -#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) -#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */ -#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) -#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) -#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */ -#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) -#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) -#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */ -#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) -#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) -#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */ -#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) -#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) -#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */ -#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) -#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) -#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */ -#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) -#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) -#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */ -#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) -#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) -#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */ -#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) -#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) -#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */ -#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) -#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */ -#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) -#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */ -#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) -#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */ -#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) -#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */ -#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) -#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */ -#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) -#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) -#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */ -#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) -#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */ -#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) -#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */ -#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) -#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */ -#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) -#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */ -#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) -#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */ -#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) -#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) -#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */ -#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */ -#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL) -#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val) -#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */ -#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */ -#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */ -#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) -#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */ -#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */ -#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */ -#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */ -#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) -#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */ -#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */ -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */ -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */ -#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) -#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */ -#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) -#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) -#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) -#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ -#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) -#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */ -#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) -#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) -#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) -#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */ -#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) -#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */ -#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) -#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) -#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) -#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */ -#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) -#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) -#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) -#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) -#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) -#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) -#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) -#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) -#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) -#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */ -#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) -#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */ -#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) -#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) -#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) -#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ -#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) -#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */ -#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) -#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) -#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) -#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */ -#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) -#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */ -#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) -#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) -#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) -#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */ -#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) -#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) -#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) -#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) -#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) -#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) -#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) -#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) -#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) -#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */ -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) -#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) -#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */ -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */ -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) -#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) -#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */ -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) -#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) -#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */ -#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) -#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */ -#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) -#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */ -#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) -#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */ -#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) -#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */ -#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) -#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */ -#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) -#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) -#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) -#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */ -#define bfin_read_UART3_THR() bfin_read16(UART3_THR) -#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */ -#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) -#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_BF542_extended__ */ diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_def.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_def.h deleted file mode 100644 index f294a85..0000000 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_def.h +++ /dev/null @@ -1,1467 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_BF542_extended__ -#define __BFIN_DEF_ADSP_EDN_BF542_extended__ - -#define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */ -#define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */ -#define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */ -#define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */ -#define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */ -#define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */ -#define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */ -#define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */ -#define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */ -#define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */ -#define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */ -#define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */ -#define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */ -#define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */ -#define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */ -#define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */ -#define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */ -#define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */ -#define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ -#define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */ -#define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ -#define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */ -#define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ -#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */ -#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */ -#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */ -#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */ -#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */ -#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */ -#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */ -#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */ -#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */ -#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */ -#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */ -#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */ -#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */ -#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */ -#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */ -#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */ -#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */ -#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */ -#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */ -#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */ -#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */ -#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */ -#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */ -#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */ -#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */ -#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */ -#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */ -#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */ -#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */ -#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */ -#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */ -#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */ -#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */ -#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */ -#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */ -#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */ -#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */ -#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */ -#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */ -#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */ -#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */ -#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */ -#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */ -#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */ -#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */ -#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */ -#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */ -#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */ -#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */ -#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */ -#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */ -#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */ -#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */ -#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */ -#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */ -#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */ -#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */ -#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */ -#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */ -#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */ -#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */ -#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */ -#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */ -#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */ -#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */ -#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */ -#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */ -#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */ -#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */ -#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */ -#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */ -#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */ -#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */ -#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */ -#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */ -#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */ -#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */ -#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */ -#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */ -#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */ -#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */ -#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */ -#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */ -#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */ -#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */ -#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */ -#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */ -#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */ -#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */ -#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */ -#define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */ -#define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */ -#define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */ -#define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */ -#define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */ -#define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */ -#define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */ -#define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */ -#define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */ -#define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */ -#define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */ -#define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */ -#define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */ -#define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */ -#define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */ -#define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */ -#define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */ -#define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */ -#define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */ -#define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */ -#define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */ -#define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */ -#define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */ -#define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */ -#define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */ -#define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */ -#define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */ -#define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */ -#define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */ -#define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */ -#define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */ -#define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */ -#define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */ -#define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */ -#define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */ -#define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */ -#define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */ -#define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */ -#define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */ -#define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */ -#define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */ -#define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */ -#define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */ -#define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */ -#define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */ -#define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */ -#define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */ -#define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */ -#define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */ -#define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */ -#define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */ -#define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */ -#define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */ -#define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */ -#define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */ -#define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */ -#define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */ -#define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */ -#define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */ -#define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */ -#define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */ -#define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */ -#define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */ -#define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */ -#define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */ -#define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */ -#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */ -#define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */ -#define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */ -#define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */ -#define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */ -#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */ -#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */ -#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */ -#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */ -#define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */ -#define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */ -#define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */ -#define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */ -#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */ -#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */ -#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */ -#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */ -#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */ -#define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */ -#define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */ -#define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */ -#define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */ -#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */ -#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */ -#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */ -#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */ -#define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */ -#define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */ -#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */ -#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */ -#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */ -#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */ -#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */ -#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */ -#define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */ -#define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */ -#define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */ -#define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */ -#define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */ -#define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */ -#define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */ -#define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */ -#define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */ -#define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */ -#define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */ -#define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */ -#define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */ -#define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ -#define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */ -#define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */ -#define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */ -#define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */ -#define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */ -#define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */ -#define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */ -#define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */ -#define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */ -#define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */ -#define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */ -#define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */ -#define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */ -#define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */ -#define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */ -#define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */ -#define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */ -#define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */ -#define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */ -#define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */ -#define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */ -#define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */ -#define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */ -#define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */ -#define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */ -#define PORTA_FER 0xFFC014C0 /* Function Enable Register */ -#define PORTA 0xFFC014C4 /* GPIO Data Register */ -#define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */ -#define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */ -#define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */ -#define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */ -#define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */ -#define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */ -#define PORTB_FER 0xFFC014E0 /* Function Enable Register */ -#define PORTB 0xFFC014E4 /* GPIO Data Register */ -#define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */ -#define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */ -#define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */ -#define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */ -#define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */ -#define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */ -#define PORTC_FER 0xFFC01500 /* Function Enable Register */ -#define PORTC 0xFFC01504 /* GPIO Data Register */ -#define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */ -#define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */ -#define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */ -#define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */ -#define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */ -#define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */ -#define PORTD_FER 0xFFC01520 /* Function Enable Register */ -#define PORTD 0xFFC01524 /* GPIO Data Register */ -#define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */ -#define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */ -#define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */ -#define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */ -#define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */ -#define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */ -#define PORTE_FER 0xFFC01540 /* Function Enable Register */ -#define PORTE 0xFFC01544 /* GPIO Data Register */ -#define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */ -#define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */ -#define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */ -#define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */ -#define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */ -#define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */ -#define PORTF_FER 0xFFC01560 /* Function Enable Register */ -#define PORTF 0xFFC01564 /* GPIO Data Register */ -#define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */ -#define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */ -#define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */ -#define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */ -#define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */ -#define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */ -#define PORTG_FER 0xFFC01580 /* Function Enable Register */ -#define PORTG 0xFFC01584 /* GPIO Data Register */ -#define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */ -#define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */ -#define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */ -#define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */ -#define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */ -#define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */ -#define PORTH_FER 0xFFC015A0 /* Function Enable Register */ -#define PORTH 0xFFC015A4 /* GPIO Data Register */ -#define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */ -#define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */ -#define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */ -#define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */ -#define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */ -#define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */ -#define PORTI_FER 0xFFC015C0 /* Function Enable Register */ -#define PORTI 0xFFC015C4 /* GPIO Data Register */ -#define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */ -#define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */ -#define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */ -#define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */ -#define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */ -#define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */ -#define PORTJ_FER 0xFFC015E0 /* Function Enable Register */ -#define PORTJ 0xFFC015E4 /* GPIO Data Register */ -#define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */ -#define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */ -#define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */ -#define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */ -#define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */ -#define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */ -#define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */ -#define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */ -#define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */ -#define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */ -#define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */ -#define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */ -#define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */ -#define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */ -#define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */ -#define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */ -#define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */ -#define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */ -#define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */ -#define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */ -#define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */ -#define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */ -#define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */ -#define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */ -#define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */ -#define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */ -#define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */ -#define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */ -#define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */ -#define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */ -#define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */ -#define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */ -#define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */ -#define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */ -#define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */ -#define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */ -#define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */ -#define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */ -#define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */ -#define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */ -#define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */ -#define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */ -#define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */ -#define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */ -#define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */ -#define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */ -#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */ -#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */ -#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define CNT_CONFIG 0xFFC04200 /* Configuration Register */ -#define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */ -#define CNT_STATUS 0xFFC04208 /* Status Register */ -#define CNT_COMMAND 0xFFC0420C /* Command Register */ -#define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */ -#define CNT_COUNTER 0xFFC04214 /* Counter Register */ -#define CNT_MAX 0xFFC04218 /* Maximal Count Register */ -#define CNT_MIN 0xFFC0421C /* Minimal Count Register */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ -#define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */ -#define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */ -#define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */ -#define SECURE_CONTROL 0xFFC04324 /* Secure Control */ -#define SECURE_STATUS 0xFFC04328 /* Secure Status */ -#define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divisor Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define KPAD_CTL 0xFFC04100 /* Controls keypad module enable and disable */ -#define KPAD_PRESCALE 0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */ -#define KPAD_MSEL 0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */ -#define KPAD_ROWCOL 0xFFC0410C /* Captures the row and column output values of the keys pressed */ -#define KPAD_STAT 0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */ -#define KPAD_SOFTEVAL 0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */ -#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ -#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ -#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ -#define SDH_COMMAND 0xFFC0390C /* SDH Command */ -#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ -#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ -#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ -#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ -#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ -#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ -#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ -#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ -#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ -#define SDH_STATUS 0xFFC03934 /* SDH Status */ -#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ -#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ -#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ -#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ -#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ -#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ -#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ -#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ -#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ -#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ -#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ -#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ -#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ -#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ -#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ -#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ -#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ -#define ATAPI_CONTROL 0xFFC03800 /* ATAPI Control Register */ -#define ATAPI_STATUS 0xFFC03804 /* ATAPI Status Register */ -#define ATAPI_DEV_ADDR 0xFFC03808 /* ATAPI Device Register Address */ -#define ATAPI_DEV_TXBUF 0xFFC0380C /* ATAPI Device Register Write Data */ -#define ATAPI_DEV_RXBUF 0xFFC03810 /* ATAPI Device Register Read Data */ -#define ATAPI_INT_MASK 0xFFC03814 /* ATAPI Interrupt Mask Register */ -#define ATAPI_INT_STATUS 0xFFC03818 /* ATAPI Interrupt Status Register */ -#define ATAPI_XFER_LEN 0xFFC0381C /* ATAPI Length of Transfer */ -#define ATAPI_LINE_STATUS 0xFFC03820 /* ATAPI Line Status */ -#define ATAPI_SM_STATE 0xFFC03824 /* ATAPI State Machine Status */ -#define ATAPI_TERMINATE 0xFFC03828 /* ATAPI Host Terminate */ -#define ATAPI_PIO_TFRCNT 0xFFC0382C /* ATAPI PIO mode transfer count */ -#define ATAPI_DMA_TFRCNT 0xFFC03830 /* ATAPI DMA mode transfer count */ -#define ATAPI_UMAIN_TFRCNT 0xFFC03834 /* ATAPI UDMAIN transfer count */ -#define ATAPI_UDMAOUT_TFRCNT 0xFFC03838 /* ATAPI UDMAOUT transfer count */ -#define ATAPI_REG_TIM_0 0xFFC03840 /* ATAPI Register Transfer Timing 0 */ -#define ATAPI_PIO_TIM_0 0xFFC03844 /* ATAPI PIO Timing 0 Register */ -#define ATAPI_PIO_TIM_1 0xFFC03848 /* ATAPI PIO Timing 1 Register */ -#define ATAPI_MULTI_TIM_0 0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */ -#define ATAPI_MULTI_TIM_1 0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */ -#define ATAPI_MULTI_TIM_2 0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_0 0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */ -#define ATAPI_ULTRA_TIM_1 0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */ -#define ATAPI_ULTRA_TIM_2 0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_3 0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */ -#define NFC_CTL 0xFFC03B00 /* NAND Control Register */ -#define NFC_STAT 0xFFC03B04 /* NAND Status Register */ -#define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */ -#define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */ -#define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */ -#define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */ -#define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */ -#define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */ -#define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */ -#define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */ -#define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */ -#define NFC_READ 0xFFC03B2C /* NAND Read Data Register */ -#define NFC_ADDR 0xFFC03B40 /* NAND Address Register */ -#define NFC_CMD 0xFFC03B44 /* NAND Command Register */ -#define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */ -#define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */ -#define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */ -#define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */ -#define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */ -#define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */ -#define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */ -#define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */ -#define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */ -#define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */ -#define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */ -#define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */ -#define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */ -#define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */ -#define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */ -#define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */ -#define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */ -#define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */ -#define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */ -#define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */ -#define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */ -#define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */ -#define CAN0_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */ -#define CAN0_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */ -#define CAN0_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */ -#define CAN0_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */ -#define CAN0_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ -#define CAN0_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */ -#define CAN0_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */ -#define CAN0_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */ -#define CAN0_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN0_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN0_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ -#define CAN0_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ -#define CAN0_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ -#define CAN0_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */ -#define CAN0_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */ -#define CAN0_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */ -#define CAN0_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */ -#define CAN0_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ -#define CAN0_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */ -#define CAN0_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */ -#define CAN0_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */ -#define CAN0_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN0_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN0_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ -#define CAN0_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ -#define CAN0_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ -#define CAN0_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */ -#define CAN0_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */ -#define CAN0_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */ -#define CAN0_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */ -#define CAN0_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */ -#define CAN0_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */ -#define CAN0_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */ -#define CAN0_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */ -#define CAN0_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */ -#define CAN0_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */ -#define CAN0_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */ -#define CAN0_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */ -#define CAN0_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */ -#define CAN0_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */ -#define CAN0_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */ -#define CAN0_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */ -#define CAN0_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ -#define CAN0_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ -#define CAN0_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ -#define CAN0_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ -#define CAN0_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ -#define CAN0_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ -#define CAN0_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ -#define CAN0_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ -#define CAN0_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ -#define CAN0_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ -#define CAN0_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ -#define CAN0_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ -#define CAN0_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ -#define CAN0_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ -#define CAN0_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ -#define CAN0_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ -#define CAN0_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ -#define CAN0_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ -#define CAN0_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ -#define CAN0_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ -#define CAN0_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ -#define CAN0_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ -#define CAN0_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ -#define CAN0_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ -#define CAN0_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ -#define CAN0_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ -#define CAN0_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ -#define CAN0_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ -#define CAN0_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ -#define CAN0_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ -#define CAN0_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ -#define CAN0_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ -#define CAN0_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ -#define CAN0_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ -#define CAN0_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ -#define CAN0_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ -#define CAN0_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ -#define CAN0_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ -#define CAN0_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ -#define CAN0_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ -#define CAN0_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ -#define CAN0_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ -#define CAN0_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ -#define CAN0_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ -#define CAN0_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ -#define CAN0_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ -#define CAN0_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ -#define CAN0_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ -#define CAN0_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ -#define CAN0_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ -#define CAN0_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ -#define CAN0_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ -#define CAN0_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ -#define CAN0_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ -#define CAN0_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ -#define CAN0_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ -#define CAN0_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ -#define CAN0_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ -#define CAN0_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ -#define CAN0_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ -#define CAN0_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ -#define CAN0_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ -#define CAN0_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ -#define CAN0_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ -#define CAN0_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ -#define CAN0_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ -#define CAN0_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ -#define CAN0_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */ -#define CAN0_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */ -#define CAN0_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ -#define CAN0_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */ -#define CAN0_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */ -#define CAN0_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ -#define CAN0_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ -#define CAN0_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ -#define CAN0_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */ -#define CAN0_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */ -#define CAN0_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ -#define CAN0_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */ -#define CAN0_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */ -#define CAN0_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ -#define CAN0_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ -#define CAN0_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ -#define CAN0_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */ -#define CAN0_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */ -#define CAN0_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ -#define CAN0_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */ -#define CAN0_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */ -#define CAN0_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ -#define CAN0_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ -#define CAN0_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ -#define CAN0_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */ -#define CAN0_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */ -#define CAN0_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ -#define CAN0_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */ -#define CAN0_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */ -#define CAN0_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ -#define CAN0_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ -#define CAN0_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ -#define CAN0_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */ -#define CAN0_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */ -#define CAN0_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ -#define CAN0_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */ -#define CAN0_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */ -#define CAN0_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ -#define CAN0_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ -#define CAN0_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ -#define CAN0_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */ -#define CAN0_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */ -#define CAN0_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ -#define CAN0_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */ -#define CAN0_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */ -#define CAN0_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ -#define CAN0_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ -#define CAN0_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ -#define CAN0_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */ -#define CAN0_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */ -#define CAN0_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ -#define CAN0_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */ -#define CAN0_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */ -#define CAN0_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ -#define CAN0_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ -#define CAN0_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ -#define CAN0_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */ -#define CAN0_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */ -#define CAN0_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ -#define CAN0_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */ -#define CAN0_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */ -#define CAN0_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ -#define CAN0_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ -#define CAN0_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ -#define CAN0_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */ -#define CAN0_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */ -#define CAN0_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ -#define CAN0_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */ -#define CAN0_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */ -#define CAN0_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ -#define CAN0_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ -#define CAN0_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ -#define CAN0_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */ -#define CAN0_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */ -#define CAN0_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ -#define CAN0_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */ -#define CAN0_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */ -#define CAN0_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ -#define CAN0_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ -#define CAN0_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ -#define CAN0_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */ -#define CAN0_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */ -#define CAN0_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ -#define CAN0_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */ -#define CAN0_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */ -#define CAN0_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ -#define CAN0_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ -#define CAN0_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ -#define CAN0_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */ -#define CAN0_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */ -#define CAN0_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ -#define CAN0_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */ -#define CAN0_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */ -#define CAN0_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ -#define CAN0_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ -#define CAN0_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ -#define CAN0_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */ -#define CAN0_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */ -#define CAN0_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ -#define CAN0_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */ -#define CAN0_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */ -#define CAN0_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ -#define CAN0_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ -#define CAN0_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ -#define CAN0_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */ -#define CAN0_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */ -#define CAN0_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ -#define CAN0_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */ -#define CAN0_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */ -#define CAN0_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ -#define CAN0_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ -#define CAN0_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ -#define CAN0_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */ -#define CAN0_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */ -#define CAN0_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ -#define CAN0_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */ -#define CAN0_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */ -#define CAN0_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ -#define CAN0_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ -#define CAN0_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ -#define CAN0_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */ -#define CAN0_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */ -#define CAN0_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ -#define CAN0_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */ -#define CAN0_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */ -#define CAN0_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ -#define CAN0_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ -#define CAN0_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ -#define CAN0_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */ -#define CAN0_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */ -#define CAN0_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ -#define CAN0_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */ -#define CAN0_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */ -#define CAN0_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ -#define CAN0_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ -#define CAN0_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ -#define CAN0_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */ -#define CAN0_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */ -#define CAN0_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ -#define CAN0_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */ -#define CAN0_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */ -#define CAN0_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ -#define CAN0_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ -#define CAN0_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ -#define CAN0_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */ -#define CAN0_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */ -#define CAN0_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ -#define CAN0_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */ -#define CAN0_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */ -#define CAN0_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ -#define CAN0_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ -#define CAN0_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ -#define CAN0_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */ -#define CAN0_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */ -#define CAN0_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ -#define CAN0_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */ -#define CAN0_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */ -#define CAN0_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ -#define CAN0_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ -#define CAN0_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ -#define CAN0_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */ -#define CAN0_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */ -#define CAN0_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ -#define CAN0_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */ -#define CAN0_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */ -#define CAN0_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ -#define CAN0_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ -#define CAN0_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ -#define CAN0_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */ -#define CAN0_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */ -#define CAN0_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ -#define CAN0_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */ -#define CAN0_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */ -#define CAN0_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ -#define CAN0_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ -#define CAN0_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ -#define CAN0_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */ -#define CAN0_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */ -#define CAN0_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ -#define CAN0_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */ -#define CAN0_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */ -#define CAN0_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ -#define CAN0_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ -#define CAN0_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ -#define CAN0_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */ -#define CAN0_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */ -#define CAN0_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ -#define CAN0_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */ -#define CAN0_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */ -#define CAN0_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ -#define CAN0_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ -#define CAN0_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ -#define CAN0_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */ -#define CAN0_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */ -#define CAN0_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ -#define CAN0_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */ -#define CAN0_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */ -#define CAN0_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ -#define CAN0_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ -#define CAN0_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ -#define CAN0_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */ -#define CAN0_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */ -#define CAN0_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ -#define CAN0_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */ -#define CAN0_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */ -#define CAN0_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ -#define CAN0_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ -#define CAN0_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ -#define CAN0_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */ -#define CAN0_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */ -#define CAN0_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ -#define CAN0_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */ -#define CAN0_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */ -#define CAN0_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ -#define CAN0_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ -#define CAN0_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ -#define CAN0_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */ -#define CAN0_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */ -#define CAN0_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ -#define CAN0_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */ -#define CAN0_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */ -#define CAN0_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ -#define CAN0_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ -#define CAN0_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ -#define CAN0_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */ -#define CAN0_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */ -#define CAN0_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ -#define CAN0_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */ -#define CAN0_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */ -#define CAN0_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ -#define CAN0_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ -#define CAN0_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ -#define CAN0_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */ -#define CAN0_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */ -#define CAN0_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ -#define CAN0_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */ -#define CAN0_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */ -#define CAN0_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ -#define CAN0_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ -#define CAN0_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ -#define CAN0_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */ -#define CAN0_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */ -#define CAN0_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ -#define CAN0_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */ -#define CAN0_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */ -#define CAN0_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ -#define CAN0_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ -#define CAN0_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ -#define CAN0_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */ -#define CAN0_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */ -#define CAN0_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ -#define CAN0_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */ -#define CAN0_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */ -#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ -#define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */ -#define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */ -#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ -#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ -#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */ -#define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */ -#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ -#define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */ -#define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */ -#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ -#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ -#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */ -#define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */ -#define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */ -#define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */ -#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ -#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ -#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */ -#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */ -#define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */ -#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */ -#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */ -#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */ -#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */ -#define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */ -#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ -#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */ -#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */ -#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ -#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */ -#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */ -#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */ -#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */ -#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */ -#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */ -#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */ -#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */ -#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ -#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ -#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */ -#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */ -#define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */ -#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */ -#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */ -#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */ -#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */ -#define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */ -#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ -#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */ -#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */ -#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ -#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */ -#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */ -#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */ -#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */ -#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */ -#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */ -#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */ -#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */ -#define UART0_GCTL 0xFFC00408 /* Global Control Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* Scratch Register */ -#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */ -#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */ -#define UART0_THR 0xFFC00428 /* Transmit Hold Register */ -#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */ -#define UART1_GCTL 0xFFC02008 /* Global Control Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* Scratch Register */ -#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */ -#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */ -#define UART1_THR 0xFFC02028 /* Transmit Hold Register */ -#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */ -#define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */ -#define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */ -#define UART3_GCTL 0xFFC03108 /* Global Control Register */ -#define UART3_LCR 0xFFC0310C /* Line Control Register */ -#define UART3_MCR 0xFFC03110 /* Modem Control Register */ -#define UART3_LSR 0xFFC03114 /* Line Status Register */ -#define UART3_MSR 0xFFC03118 /* Modem Status Register */ -#define UART3_SCR 0xFFC0311C /* Scratch Register */ -#define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */ -#define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */ -#define UART3_THR 0xFFC03128 /* Transmit Hold Register */ -#define UART3_RBR 0xFFC0312C /* Receive Buffer Register */ -#define USB_FADDR 0xFFC03C00 /* Function address register */ -#define USB_POWER 0xFFC03C04 /* Power management register */ -#define USB_INTRTX 0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03C10 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03C14 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03C18 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC03C1C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03C20 /* USB frame number */ -#define USB_INDEX 0xFFC03C24 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03C28 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03C30 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03C40 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03C48 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC03C4C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03C80 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03C88 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03C90 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03C98 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC03CA0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC03CA8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC03CB0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC03CB8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03D00 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03D04 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03D08 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03D48 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03D50 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03D54 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03D58 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC03DE0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC03DE4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03E04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03E0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03E44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03E4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03E84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03E8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03EC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ECC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03F04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03F0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03F44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03F4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03F84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03F8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03FC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03FCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC04000 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC04004 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC04024 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC04044 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC04064 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC04084 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC040A4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC040C4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC040E4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -#endif /* __BFIN_DEF_ADSP_EDN_BF542_extended__ */ diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h deleted file mode 100644 index 4c0fdf5..0000000 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h +++ /dev/null @@ -1,4972 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_BF544_extended__ -#define __BFIN_CDEF_ADSP_EDN_BF544_extended__ - -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */ -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */ -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */ -#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) -#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */ -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */ -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */ -#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) -#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */ -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */ -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */ -#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) -#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */ -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */ -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */ -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */ -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */ -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */ -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */ -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */ -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */ -#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) -#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */ -#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) -#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */ -#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) -#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */ -#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) -#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) -#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */ -#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) -#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) -#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */ -#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) -#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) -#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */ -#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) -#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) -#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */ -#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) -#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) -#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */ -#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) -#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ -#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ -#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ -#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ -#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ -#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ -#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ -#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ -#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ -#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ -#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ -#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ -#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ -#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ -#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ -#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ -#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ -#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ -#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ -#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ -#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ -#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ -#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ -#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ -#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */ -#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) -#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */ -#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) -#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */ -#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) -#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */ -#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) -#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */ -#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) -#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */ -#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) -#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */ -#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) -#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */ -#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) -#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */ -#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) -#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */ -#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) -#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */ -#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) -#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */ -#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) -#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */ -#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) -#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */ -#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) -#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */ -#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) -#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */ -#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) -#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */ -#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) -#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */ -#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) -#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */ -#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) -#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */ -#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) -#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */ -#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) -#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */ -#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) -#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */ -#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) -#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */ -#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) -#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */ -#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) -#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */ -#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) -#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */ -#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) -#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */ -#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) -#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */ -#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) -#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */ -#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) -#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */ -#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) -#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */ -#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) -#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */ -#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) -#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */ -#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) -#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */ -#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) -#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */ -#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) -#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */ -#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) -#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */ -#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) -#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */ -#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) -#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */ -#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) -#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */ -#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) -#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */ -#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) -#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */ -#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) -#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */ -#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) -#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */ -#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) -#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */ -#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) -#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */ -#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) -#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */ -#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) -#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */ -#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) -#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */ -#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) -#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */ -#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) -#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */ -#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) -#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */ -#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) -#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */ -#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) -#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */ -#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) -#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */ -#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) -#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */ -#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) -#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */ -#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) -#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */ -#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) -#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */ -#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) -#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */ -#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) -#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */ -#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) -#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */ -#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) -#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */ -#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) -#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */ -#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) -#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */ -#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) -#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */ -#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) -#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */ -#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) -#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */ -#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) -#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */ -#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) -#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */ -#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) -#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */ -#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) -#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */ -#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) -#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */ -#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) -#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */ -#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) -#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */ -#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) -#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */ -#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) -#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */ -#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) -#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */ -#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) -#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */ -#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) -#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */ -#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) -#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */ -#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) -#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */ -#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) -#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */ -#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) -#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */ -#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) -#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */ -#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) -#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */ -#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) -#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */ -#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) -#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */ -#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) -#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */ -#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) -#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */ -#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) -#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */ -#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) -#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */ -#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) -#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */ -#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) -#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */ -#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) -#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */ -#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) -#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */ -#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) -#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */ -#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) -#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */ -#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) -#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */ -#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) -#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */ -#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) -#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */ -#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) -#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */ -#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) -#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */ -#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) -#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */ -#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR) -#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val) -#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */ -#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR) -#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val) -#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */ -#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) -#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */ -#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) -#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */ -#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) -#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */ -#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) -#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */ -#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) -#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */ -#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR) -#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val) -#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */ -#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR) -#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val) -#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */ -#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) -#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */ -#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) -#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */ -#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) -#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */ -#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) -#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) -#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */ -#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR) -#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val) -#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */ -#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR) -#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val) -#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */ -#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) -#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */ -#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) -#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */ -#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) -#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */ -#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) -#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */ -#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) -#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */ -#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR) -#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val) -#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */ -#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR) -#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val) -#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */ -#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) -#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */ -#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) -#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */ -#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) -#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */ -#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) -#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) -#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */ -#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR) -#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val) -#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */ -#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR) -#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val) -#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */ -#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) -#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */ -#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) -#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */ -#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) -#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */ -#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) -#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */ -#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) -#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */ -#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR) -#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val) -#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */ -#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR) -#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val) -#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */ -#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) -#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */ -#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) -#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */ -#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) -#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */ -#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) -#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) -#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */ -#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR) -#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val) -#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */ -#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR) -#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val) -#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */ -#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) -#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */ -#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) -#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */ -#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) -#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */ -#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) -#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */ -#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) -#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */ -#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR) -#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val) -#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */ -#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR) -#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val) -#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */ -#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) -#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */ -#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) -#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */ -#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) -#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */ -#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) -#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */ -#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */ -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */ -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */ -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */ -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */ -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */ -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */ -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */ -#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */ -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */ -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */ -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */ -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */ -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */ -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */ -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */ -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */ -#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */ -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */ -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */ -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */ -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */ -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */ -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */ -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */ -#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */ -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */ -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */ -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */ -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */ -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */ -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */ -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */ -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) -#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */ -#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) -#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */ -#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) -#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */ -#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) -#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */ -#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) -#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */ -#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) -#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */ -#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) -#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) -#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */ -#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) -#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) -#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) -#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */ -#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) -#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) -#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) -#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */ -#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) -#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */ -#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) -#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */ -#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) -#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */ -#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) -#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */ -#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) -#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */ -#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) -#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) -#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */ -#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) -#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) -#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) -#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */ -#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) -#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */ -#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) -#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) -#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */ -#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) -#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */ -#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) -#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */ -#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) -#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */ -#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) -#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */ -#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) -#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */ -#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) -#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) -#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */ -#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) -#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) -#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) -#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */ -#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) -#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) -#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) -#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */ -#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) -#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */ -#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) -#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */ -#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) -#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */ -#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) -#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */ -#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) -#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */ -#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) -#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) -#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */ -#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) -#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) -#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) -#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */ -#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) -#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */ -#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) -#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */ -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */ -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */ -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */ -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */ -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */ -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */ -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */ -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */ -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */ -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */ -#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL) -#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val) -#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */ -#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) -#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */ -#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) -#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */ -#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL) -#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val) -#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */ -#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) -#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */ -#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) -#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */ -#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) -#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */ -#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) -#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */ -#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) -#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */ -#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD) -#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val) -#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */ -#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) -#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */ -#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) -#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) -#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */ -#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) -#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */ -#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) -#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */ -#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) -#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */ -#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) -#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */ -#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) -#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */ -#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) -#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */ -#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) -#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */ -#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) -#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */ -#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) -#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */ -#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) -#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */ -#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) -#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */ -#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) -#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */ -#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) -#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */ -#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) -#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */ -#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) -#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */ -#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) -#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */ -#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) -#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */ -#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) -#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */ -#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) -#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */ -#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) -#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */ -#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) -#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */ -#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) -#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */ -#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) -#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */ -#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) -#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */ -#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) -#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) -#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) -#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) -#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */ -#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) -#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) -#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */ -#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) -#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) -#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) -#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) -#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) -#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) -#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) -#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) -#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) -#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) -#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */ -#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) -#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) -#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) -#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) -#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) -#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) -#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) -#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) -#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) -#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) -#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */ -#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) -#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) -#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */ -#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) -#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) -#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) -#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) -#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) -#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) -#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) -#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) -#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */ -#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) -#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) -#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */ -#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) -#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) -#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */ -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */ -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */ -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */ -#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) -#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */ -#define bfin_read_PORTA() bfin_read16(PORTA) -#define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) -#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) -#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) -#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) -#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) -#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) -#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */ -#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) -#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */ -#define bfin_read_PORTB() bfin_read16(PORTB) -#define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) -#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) -#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) -#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) -#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) -#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) -#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */ -#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) -#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */ -#define bfin_read_PORTC() bfin_read16(PORTC) -#define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) -#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) -#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) -#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) -#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) -#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) -#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */ -#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) -#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */ -#define bfin_read_PORTD() bfin_read16(PORTD) -#define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) -#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) -#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) -#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) -#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) -#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) -#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */ -#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) -#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */ -#define bfin_read_PORTE() bfin_read16(PORTE) -#define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) -#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) -#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) -#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) -#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) -#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) -#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */ -#define bfin_read_PORTF() bfin_read16(PORTF) -#define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) -#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) -#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) -#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) -#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) -#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */ -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */ -#define bfin_read_PORTG() bfin_read16(PORTG) -#define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) -#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) -#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) -#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) -#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) -#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */ -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */ -#define bfin_read_PORTH() bfin_read16(PORTH) -#define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) -#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) -#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) -#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) -#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) -#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) -#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */ -#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) -#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */ -#define bfin_read_PORTI() bfin_read16(PORTI) -#define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) -#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) -#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) -#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) -#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) -#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) -#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) -#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */ -#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) -#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */ -#define bfin_read_PORTJ() bfin_read16(PORTJ) -#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) -#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) -#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) -#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) -#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) -#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) -#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) -#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */ -#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) -#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */ -#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) -#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */ -#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ) -#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val) -#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */ -#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) -#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) -#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) -#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */ -#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) -#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */ -#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) -#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */ -#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) -#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */ -#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) -#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) -#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */ -#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) -#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */ -#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) -#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */ -#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ) -#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val) -#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */ -#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) -#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) -#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) -#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */ -#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) -#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */ -#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) -#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */ -#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) -#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */ -#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) -#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) -#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */ -#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) -#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */ -#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) -#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */ -#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ) -#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val) -#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */ -#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) -#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) -#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) -#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */ -#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) -#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */ -#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) -#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */ -#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) -#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */ -#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) -#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) -#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */ -#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) -#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */ -#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) -#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */ -#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ) -#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val) -#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */ -#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) -#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) -#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) -#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */ -#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) -#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */ -#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) -#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */ -#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) -#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */ -#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) -#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */ -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */ -#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) -#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */ -#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) -#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */ -#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) -#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */ -#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) -#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */ -#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) -#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */ -#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) -#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */ -#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) -#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */ -#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) -#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */ -#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) -#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */ -#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) -#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */ -#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) -#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */ -#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) -#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) -#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */ -#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) -#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */ -#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) -#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */ -#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) -#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) -#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */ -#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) -#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) -#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */ -#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) -#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) -#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */ -#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) -#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */ -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */ -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */ -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */ -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */ -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ -#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) -#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ -#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) -#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ -#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) -#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ -#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) -#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) -#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) -#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) -#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) -#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ -#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) -#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ -#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) -#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ -#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) -#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ -#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) -#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ -#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) -#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ -#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) -#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ -#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) -#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ -#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) -#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ -#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) -#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ -#define bfin_read_NFC_RST() bfin_read16(NFC_RST) -#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ -#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) -#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ -#define bfin_read_NFC_READ() bfin_read16(NFC_READ) -#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ -#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) -#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ -#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) -#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ -#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) -#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ -#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) -#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */ -#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) -#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) -#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */ -#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) -#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) -#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */ -#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) -#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) -#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */ -#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) -#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) -#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */ -#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) -#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) -#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */ -#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) -#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) -#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */ -#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) -#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) -#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */ -#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) -#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) -#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */ -#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) -#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) -#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) -#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) -#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) -#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) -#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) -#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) -#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) -#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) -#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */ -#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) -#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) -#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */ -#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) -#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */ -#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) -#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */ -#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) -#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */ -#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) -#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */ -#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) -#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */ -#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) -#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */ -#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) -#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */ -#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) -#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */ -#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) -#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) -#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) -#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) -#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) -#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */ -#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) -#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) -#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */ -#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) -#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */ -#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) -#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */ -#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) -#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */ -#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) -#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */ -#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) -#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */ -#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) -#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */ -#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) -#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */ -#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) -#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */ -#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) -#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) -#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) -#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) -#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) -#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */ -#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) -#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) -#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */ -#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) -#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) -#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */ -#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) -#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) -#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */ -#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) -#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) -#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */ -#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) -#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) -#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */ -#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) -#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) -#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */ -#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) -#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) -#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */ -#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) -#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) -#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */ -#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) -#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) -#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ -#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) -#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) -#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ -#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) -#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) -#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ -#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) -#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) -#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ -#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) -#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) -#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ -#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) -#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) -#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */ -#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) -#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) -#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */ -#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) -#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) -#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */ -#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) -#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) -#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */ -#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) -#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) -#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */ -#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) -#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) -#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */ -#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) -#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) -#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */ -#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) -#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) -#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */ -#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) -#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) -#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ -#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) -#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) -#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ -#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) -#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) -#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ -#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) -#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) -#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ -#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) -#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) -#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ -#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) -#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) -#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */ -#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) -#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) -#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */ -#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) -#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) -#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */ -#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) -#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) -#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */ -#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) -#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) -#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */ -#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) -#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) -#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */ -#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) -#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) -#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */ -#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) -#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) -#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */ -#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) -#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) -#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */ -#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) -#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) -#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */ -#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) -#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) -#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */ -#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) -#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) -#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */ -#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) -#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) -#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */ -#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) -#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) -#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */ -#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) -#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) -#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */ -#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) -#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) -#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */ -#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) -#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) -#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) -#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) -#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) -#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) -#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) -#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) -#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) -#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) -#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) -#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) -#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) -#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) -#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) -#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) -#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) -#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) -#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) -#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) -#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) -#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) -#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) -#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) -#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) -#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) -#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) -#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) -#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) -#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) -#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) -#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) -#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) -#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) -#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) -#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) -#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) -#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) -#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) -#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) -#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) -#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) -#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) -#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) -#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) -#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) -#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) -#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) -#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) -#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) -#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) -#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) -#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) -#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) -#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) -#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) -#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) -#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) -#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) -#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) -#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) -#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) -#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) -#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) -#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) -#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) -#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) -#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) -#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) -#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) -#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) -#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) -#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) -#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) -#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) -#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) -#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) -#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) -#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) -#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) -#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) -#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) -#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) -#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) -#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) -#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) -#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) -#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) -#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) -#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) -#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) -#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) -#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) -#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) -#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) -#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) -#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) -#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) -#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) -#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) -#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) -#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) -#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) -#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) -#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) -#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) -#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) -#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) -#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) -#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) -#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) -#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) -#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) -#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) -#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) -#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) -#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) -#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) -#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) -#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) -#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) -#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) -#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) -#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) -#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) -#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) -#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) -#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) -#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) -#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) -#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */ -#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) -#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) -#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */ -#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) -#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) -#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */ -#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) -#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) -#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */ -#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) -#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) -#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */ -#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) -#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) -#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */ -#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) -#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) -#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */ -#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) -#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) -#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */ -#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) -#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) -#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */ -#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) -#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) -#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */ -#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) -#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) -#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */ -#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) -#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) -#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */ -#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) -#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) -#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */ -#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) -#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) -#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */ -#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) -#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) -#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */ -#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) -#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) -#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */ -#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) -#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) -#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */ -#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) -#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) -#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */ -#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) -#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) -#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */ -#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) -#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) -#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */ -#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) -#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) -#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */ -#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) -#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) -#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */ -#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) -#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) -#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */ -#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) -#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) -#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */ -#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) -#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) -#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */ -#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) -#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) -#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */ -#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) -#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) -#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */ -#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) -#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) -#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */ -#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) -#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) -#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */ -#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) -#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) -#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */ -#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) -#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) -#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */ -#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) -#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) -#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */ -#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) -#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) -#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */ -#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) -#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) -#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */ -#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) -#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) -#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */ -#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) -#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) -#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */ -#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) -#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) -#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */ -#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) -#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) -#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */ -#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) -#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) -#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */ -#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) -#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) -#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */ -#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) -#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) -#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */ -#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) -#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) -#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */ -#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) -#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) -#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */ -#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) -#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) -#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */ -#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) -#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) -#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */ -#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) -#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) -#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */ -#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) -#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) -#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */ -#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) -#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) -#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */ -#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) -#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) -#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */ -#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) -#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) -#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */ -#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) -#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) -#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */ -#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) -#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) -#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */ -#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) -#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) -#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */ -#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) -#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) -#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */ -#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) -#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) -#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */ -#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) -#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) -#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */ -#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) -#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) -#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */ -#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) -#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) -#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */ -#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) -#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) -#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */ -#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) -#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) -#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */ -#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) -#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) -#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */ -#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) -#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) -#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */ -#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) -#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) -#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */ -#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) -#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) -#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */ -#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) -#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) -#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */ -#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) -#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) -#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */ -#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) -#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) -#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */ -#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) -#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) -#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */ -#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) -#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) -#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */ -#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) -#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) -#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */ -#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) -#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) -#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */ -#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) -#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) -#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */ -#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) -#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) -#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */ -#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) -#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) -#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */ -#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) -#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) -#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */ -#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) -#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) -#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */ -#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) -#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) -#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */ -#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) -#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) -#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */ -#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) -#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) -#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */ -#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) -#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) -#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */ -#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) -#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) -#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */ -#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) -#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) -#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */ -#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) -#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) -#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */ -#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) -#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) -#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */ -#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) -#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) -#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */ -#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) -#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) -#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */ -#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) -#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) -#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */ -#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) -#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) -#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */ -#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) -#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) -#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */ -#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) -#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) -#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */ -#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) -#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) -#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */ -#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) -#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) -#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */ -#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) -#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) -#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */ -#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) -#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) -#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */ -#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) -#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) -#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */ -#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) -#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) -#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */ -#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) -#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) -#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */ -#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) -#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) -#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */ -#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) -#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) -#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */ -#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) -#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) -#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */ -#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) -#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) -#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */ -#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) -#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) -#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */ -#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) -#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) -#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */ -#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) -#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) -#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */ -#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) -#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) -#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */ -#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) -#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) -#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */ -#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) -#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) -#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */ -#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) -#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) -#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */ -#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) -#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) -#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */ -#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) -#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) -#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */ -#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) -#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) -#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */ -#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) -#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) -#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */ -#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) -#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) -#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */ -#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) -#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) -#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */ -#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) -#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) -#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */ -#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) -#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) -#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */ -#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) -#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) -#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */ -#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) -#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) -#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */ -#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) -#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) -#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */ -#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) -#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) -#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */ -#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) -#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) -#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */ -#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) -#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) -#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */ -#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) -#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) -#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */ -#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) -#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) -#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */ -#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) -#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) -#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */ -#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) -#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) -#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */ -#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) -#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) -#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */ -#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) -#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) -#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */ -#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) -#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) -#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */ -#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) -#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) -#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */ -#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) -#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) -#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */ -#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) -#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) -#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */ -#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) -#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) -#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */ -#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) -#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) -#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */ -#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) -#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) -#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */ -#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) -#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) -#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */ -#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) -#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) -#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */ -#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) -#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) -#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */ -#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) -#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) -#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */ -#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) -#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) -#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */ -#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) -#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) -#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */ -#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) -#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) -#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */ -#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) -#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) -#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */ -#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) -#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) -#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */ -#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) -#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) -#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */ -#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) -#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) -#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */ -#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) -#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) -#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */ -#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) -#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) -#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */ -#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) -#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) -#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */ -#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) -#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) -#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */ -#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) -#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) -#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */ -#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) -#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) -#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */ -#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) -#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) -#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */ -#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) -#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) -#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */ -#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) -#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) -#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */ -#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) -#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) -#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */ -#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) -#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) -#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */ -#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) -#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) -#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */ -#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) -#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) -#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */ -#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) -#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) -#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */ -#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) -#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) -#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */ -#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) -#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) -#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */ -#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) -#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) -#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */ -#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) -#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) -#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */ -#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) -#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) -#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */ -#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) -#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) -#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */ -#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) -#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) -#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */ -#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) -#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) -#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */ -#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) -#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) -#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */ -#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) -#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) -#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */ -#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) -#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) -#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */ -#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) -#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) -#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */ -#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) -#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) -#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */ -#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) -#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) -#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */ -#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) -#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) -#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */ -#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) -#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) -#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */ -#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) -#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) -#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */ -#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) -#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) -#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */ -#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) -#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) -#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */ -#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) -#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) -#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */ -#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) -#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) -#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */ -#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) -#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) -#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */ -#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) -#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) -#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */ -#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) -#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) -#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */ -#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) -#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) -#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */ -#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) -#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) -#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */ -#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) -#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) -#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */ -#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) -#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) -#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */ -#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) -#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) -#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */ -#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) -#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) -#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */ -#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) -#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) -#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */ -#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) -#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) -#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */ -#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) -#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) -#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */ -#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) -#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) -#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */ -#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) -#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) -#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */ -#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) -#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) -#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */ -#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) -#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) -#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */ -#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) -#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) -#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */ -#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) -#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) -#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */ -#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) -#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) -#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */ -#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) -#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) -#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */ -#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) -#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) -#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */ -#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) -#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) -#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */ -#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) -#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) -#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */ -#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) -#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) -#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */ -#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) -#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) -#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */ -#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) -#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) -#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */ -#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) -#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) -#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */ -#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) -#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) -#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */ -#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) -#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) -#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */ -#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) -#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) -#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */ -#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) -#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) -#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */ -#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) -#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) -#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */ -#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) -#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) -#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */ -#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) -#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) -#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */ -#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) -#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) -#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */ -#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) -#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) -#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */ -#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) -#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) -#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */ -#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) -#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) -#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */ -#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) -#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) -#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */ -#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) -#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) -#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */ -#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) -#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) -#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */ -#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) -#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) -#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */ -#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) -#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) -#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */ -#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) -#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) -#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */ -#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) -#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) -#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */ -#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) -#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) -#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */ -#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) -#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) -#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */ -#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) -#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) -#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */ -#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) -#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) -#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */ -#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) -#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) -#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */ -#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) -#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) -#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */ -#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) -#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) -#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */ -#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) -#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) -#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */ -#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) -#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) -#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */ -#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) -#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) -#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */ -#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) -#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) -#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */ -#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) -#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) -#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */ -#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) -#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) -#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */ -#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) -#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) -#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */ -#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) -#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) -#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */ -#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) -#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) -#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */ -#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) -#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) -#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */ -#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) -#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) -#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */ -#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) -#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) -#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */ -#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) -#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) -#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */ -#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) -#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) -#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */ -#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) -#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) -#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */ -#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) -#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) -#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */ -#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) -#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) -#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */ -#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) -#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) -#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */ -#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) -#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) -#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */ -#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) -#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) -#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */ -#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) -#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) -#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */ -#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) -#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) -#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */ -#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) -#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) -#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */ -#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) -#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) -#define pCAN1_MC1 ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */ -#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) -#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) -#define pCAN1_MD1 ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */ -#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) -#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) -#define pCAN1_TRS1 ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */ -#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) -#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) -#define pCAN1_TRR1 ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */ -#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) -#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) -#define pCAN1_TA1 ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */ -#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) -#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) -#define pCAN1_AA1 ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */ -#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) -#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) -#define pCAN1_RMP1 ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */ -#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) -#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) -#define pCAN1_RML1 ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */ -#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) -#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) -#define pCAN1_MBTIF1 ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ -#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) -#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) -#define pCAN1_MBRIF1 ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ -#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) -#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) -#define pCAN1_MBIM1 ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ -#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) -#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) -#define pCAN1_RFH1 ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ -#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) -#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) -#define pCAN1_OPSS1 ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ -#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) -#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) -#define pCAN1_MC2 ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */ -#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) -#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) -#define pCAN1_MD2 ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */ -#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) -#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) -#define pCAN1_TRS2 ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */ -#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) -#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) -#define pCAN1_TRR2 ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */ -#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) -#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) -#define pCAN1_TA2 ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */ -#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) -#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) -#define pCAN1_AA2 ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */ -#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) -#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) -#define pCAN1_RMP2 ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */ -#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) -#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) -#define pCAN1_RML2 ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */ -#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) -#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) -#define pCAN1_MBTIF2 ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ -#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) -#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) -#define pCAN1_MBRIF2 ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ -#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) -#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) -#define pCAN1_MBIM2 ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ -#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) -#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) -#define pCAN1_RFH2 ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ -#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) -#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) -#define pCAN1_OPSS2 ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ -#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) -#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) -#define pCAN1_CLOCK ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */ -#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) -#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) -#define pCAN1_TIMING ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */ -#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) -#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) -#define pCAN1_DEBUG ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */ -#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) -#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) -#define pCAN1_STATUS ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */ -#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) -#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) -#define pCAN1_CEC ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */ -#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) -#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) -#define pCAN1_GIS ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */ -#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) -#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) -#define pCAN1_GIM ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */ -#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) -#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) -#define pCAN1_GIF ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */ -#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) -#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) -#define pCAN1_CONTROL ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */ -#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) -#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) -#define pCAN1_INTR ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */ -#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) -#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) -#define pCAN1_MBTD ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */ -#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) -#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) -#define pCAN1_EWR ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */ -#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) -#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) -#define pCAN1_ESR ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */ -#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) -#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) -#define pCAN1_UCCNT ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */ -#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) -#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) -#define pCAN1_UCRC ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */ -#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) -#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) -#define pCAN1_UCCNF ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */ -#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) -#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) -#define pCAN1_AM00L ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) -#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) -#define pCAN1_AM00H ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) -#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) -#define pCAN1_AM01L ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) -#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) -#define pCAN1_AM01H ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) -#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) -#define pCAN1_AM02L ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) -#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) -#define pCAN1_AM02H ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) -#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) -#define pCAN1_AM03L ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) -#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) -#define pCAN1_AM03H ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) -#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) -#define pCAN1_AM04L ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) -#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) -#define pCAN1_AM04H ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) -#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) -#define pCAN1_AM05L ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) -#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) -#define pCAN1_AM05H ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) -#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) -#define pCAN1_AM06L ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) -#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) -#define pCAN1_AM06H ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) -#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) -#define pCAN1_AM07L ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) -#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) -#define pCAN1_AM07H ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) -#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) -#define pCAN1_AM08L ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) -#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) -#define pCAN1_AM08H ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) -#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) -#define pCAN1_AM09L ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) -#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) -#define pCAN1_AM09H ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) -#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) -#define pCAN1_AM10L ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) -#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) -#define pCAN1_AM10H ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) -#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) -#define pCAN1_AM11L ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) -#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) -#define pCAN1_AM11H ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) -#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) -#define pCAN1_AM12L ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) -#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) -#define pCAN1_AM12H ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) -#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) -#define pCAN1_AM13L ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) -#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) -#define pCAN1_AM13H ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) -#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) -#define pCAN1_AM14L ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) -#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) -#define pCAN1_AM14H ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) -#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) -#define pCAN1_AM15L ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) -#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) -#define pCAN1_AM15H ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) -#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) -#define pCAN1_AM16L ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) -#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) -#define pCAN1_AM16H ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) -#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) -#define pCAN1_AM17L ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) -#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) -#define pCAN1_AM17H ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) -#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) -#define pCAN1_AM18L ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) -#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) -#define pCAN1_AM18H ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) -#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) -#define pCAN1_AM19L ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) -#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) -#define pCAN1_AM19H ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) -#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) -#define pCAN1_AM20L ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) -#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) -#define pCAN1_AM20H ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) -#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) -#define pCAN1_AM21L ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) -#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) -#define pCAN1_AM21H ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) -#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) -#define pCAN1_AM22L ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) -#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) -#define pCAN1_AM22H ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) -#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) -#define pCAN1_AM23L ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) -#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) -#define pCAN1_AM23H ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) -#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) -#define pCAN1_AM24L ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) -#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) -#define pCAN1_AM24H ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) -#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) -#define pCAN1_AM25L ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) -#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) -#define pCAN1_AM25H ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) -#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) -#define pCAN1_AM26L ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) -#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) -#define pCAN1_AM26H ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) -#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) -#define pCAN1_AM27L ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) -#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) -#define pCAN1_AM27H ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) -#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) -#define pCAN1_AM28L ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) -#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) -#define pCAN1_AM28H ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) -#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) -#define pCAN1_AM29L ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) -#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) -#define pCAN1_AM29H ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) -#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) -#define pCAN1_AM30L ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) -#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) -#define pCAN1_AM30H ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) -#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) -#define pCAN1_AM31L ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) -#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) -#define pCAN1_AM31H ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) -#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) -#define pCAN1_MB00_DATA0 ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */ -#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) -#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) -#define pCAN1_MB00_DATA1 ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */ -#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) -#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) -#define pCAN1_MB00_DATA2 ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */ -#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) -#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) -#define pCAN1_MB00_DATA3 ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */ -#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) -#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) -#define pCAN1_MB00_LENGTH ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */ -#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) -#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) -#define pCAN1_MB00_TIMESTAMP ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */ -#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) -#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) -#define pCAN1_MB00_ID0 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */ -#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) -#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) -#define pCAN1_MB00_ID1 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */ -#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) -#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) -#define pCAN1_MB01_DATA0 ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */ -#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) -#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) -#define pCAN1_MB01_DATA1 ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */ -#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) -#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) -#define pCAN1_MB01_DATA2 ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */ -#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) -#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) -#define pCAN1_MB01_DATA3 ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */ -#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) -#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) -#define pCAN1_MB01_LENGTH ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */ -#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) -#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) -#define pCAN1_MB01_TIMESTAMP ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */ -#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) -#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) -#define pCAN1_MB01_ID0 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */ -#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) -#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) -#define pCAN1_MB01_ID1 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */ -#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) -#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) -#define pCAN1_MB02_DATA0 ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */ -#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) -#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) -#define pCAN1_MB02_DATA1 ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */ -#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) -#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) -#define pCAN1_MB02_DATA2 ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */ -#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) -#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) -#define pCAN1_MB02_DATA3 ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */ -#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) -#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) -#define pCAN1_MB02_LENGTH ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */ -#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) -#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) -#define pCAN1_MB02_TIMESTAMP ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */ -#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) -#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) -#define pCAN1_MB02_ID0 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */ -#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) -#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) -#define pCAN1_MB02_ID1 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */ -#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) -#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) -#define pCAN1_MB03_DATA0 ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */ -#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) -#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) -#define pCAN1_MB03_DATA1 ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */ -#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) -#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) -#define pCAN1_MB03_DATA2 ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */ -#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) -#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) -#define pCAN1_MB03_DATA3 ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */ -#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) -#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) -#define pCAN1_MB03_LENGTH ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */ -#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) -#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) -#define pCAN1_MB03_TIMESTAMP ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */ -#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) -#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) -#define pCAN1_MB03_ID0 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */ -#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) -#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) -#define pCAN1_MB03_ID1 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */ -#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) -#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) -#define pCAN1_MB04_DATA0 ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */ -#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) -#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) -#define pCAN1_MB04_DATA1 ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */ -#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) -#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) -#define pCAN1_MB04_DATA2 ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */ -#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) -#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) -#define pCAN1_MB04_DATA3 ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */ -#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) -#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) -#define pCAN1_MB04_LENGTH ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */ -#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) -#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) -#define pCAN1_MB04_TIMESTAMP ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */ -#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) -#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) -#define pCAN1_MB04_ID0 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */ -#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) -#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) -#define pCAN1_MB04_ID1 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */ -#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) -#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) -#define pCAN1_MB05_DATA0 ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */ -#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) -#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) -#define pCAN1_MB05_DATA1 ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */ -#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) -#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) -#define pCAN1_MB05_DATA2 ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */ -#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) -#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) -#define pCAN1_MB05_DATA3 ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */ -#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) -#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) -#define pCAN1_MB05_LENGTH ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */ -#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) -#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) -#define pCAN1_MB05_TIMESTAMP ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */ -#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) -#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) -#define pCAN1_MB05_ID0 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */ -#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) -#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) -#define pCAN1_MB05_ID1 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */ -#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) -#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) -#define pCAN1_MB06_DATA0 ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */ -#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) -#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) -#define pCAN1_MB06_DATA1 ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */ -#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) -#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) -#define pCAN1_MB06_DATA2 ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */ -#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) -#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) -#define pCAN1_MB06_DATA3 ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */ -#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) -#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) -#define pCAN1_MB06_LENGTH ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */ -#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) -#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) -#define pCAN1_MB06_TIMESTAMP ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */ -#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) -#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) -#define pCAN1_MB06_ID0 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */ -#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) -#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) -#define pCAN1_MB06_ID1 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */ -#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) -#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) -#define pCAN1_MB07_DATA0 ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */ -#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) -#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) -#define pCAN1_MB07_DATA1 ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */ -#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) -#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) -#define pCAN1_MB07_DATA2 ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */ -#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) -#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) -#define pCAN1_MB07_DATA3 ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */ -#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) -#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) -#define pCAN1_MB07_LENGTH ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */ -#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) -#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) -#define pCAN1_MB07_TIMESTAMP ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */ -#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) -#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) -#define pCAN1_MB07_ID0 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */ -#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) -#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) -#define pCAN1_MB07_ID1 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */ -#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) -#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) -#define pCAN1_MB08_DATA0 ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */ -#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) -#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) -#define pCAN1_MB08_DATA1 ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */ -#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) -#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) -#define pCAN1_MB08_DATA2 ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */ -#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) -#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) -#define pCAN1_MB08_DATA3 ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */ -#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) -#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) -#define pCAN1_MB08_LENGTH ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */ -#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) -#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) -#define pCAN1_MB08_TIMESTAMP ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */ -#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) -#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) -#define pCAN1_MB08_ID0 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */ -#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) -#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) -#define pCAN1_MB08_ID1 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */ -#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) -#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) -#define pCAN1_MB09_DATA0 ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */ -#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) -#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) -#define pCAN1_MB09_DATA1 ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */ -#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) -#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) -#define pCAN1_MB09_DATA2 ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */ -#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) -#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) -#define pCAN1_MB09_DATA3 ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */ -#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) -#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) -#define pCAN1_MB09_LENGTH ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */ -#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) -#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) -#define pCAN1_MB09_TIMESTAMP ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */ -#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) -#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) -#define pCAN1_MB09_ID0 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */ -#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) -#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) -#define pCAN1_MB09_ID1 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */ -#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) -#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) -#define pCAN1_MB10_DATA0 ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */ -#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) -#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) -#define pCAN1_MB10_DATA1 ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */ -#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) -#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) -#define pCAN1_MB10_DATA2 ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */ -#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) -#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) -#define pCAN1_MB10_DATA3 ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */ -#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) -#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) -#define pCAN1_MB10_LENGTH ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */ -#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) -#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) -#define pCAN1_MB10_TIMESTAMP ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */ -#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) -#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) -#define pCAN1_MB10_ID0 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */ -#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) -#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) -#define pCAN1_MB10_ID1 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */ -#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) -#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) -#define pCAN1_MB11_DATA0 ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */ -#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) -#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) -#define pCAN1_MB11_DATA1 ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */ -#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) -#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) -#define pCAN1_MB11_DATA2 ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */ -#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) -#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) -#define pCAN1_MB11_DATA3 ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */ -#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) -#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) -#define pCAN1_MB11_LENGTH ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */ -#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) -#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) -#define pCAN1_MB11_TIMESTAMP ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */ -#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) -#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) -#define pCAN1_MB11_ID0 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */ -#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) -#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) -#define pCAN1_MB11_ID1 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */ -#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) -#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) -#define pCAN1_MB12_DATA0 ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */ -#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) -#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) -#define pCAN1_MB12_DATA1 ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */ -#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) -#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) -#define pCAN1_MB12_DATA2 ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */ -#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) -#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) -#define pCAN1_MB12_DATA3 ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */ -#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) -#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) -#define pCAN1_MB12_LENGTH ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */ -#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) -#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) -#define pCAN1_MB12_TIMESTAMP ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */ -#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) -#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) -#define pCAN1_MB12_ID0 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */ -#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) -#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) -#define pCAN1_MB12_ID1 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */ -#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) -#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) -#define pCAN1_MB13_DATA0 ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */ -#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) -#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) -#define pCAN1_MB13_DATA1 ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */ -#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) -#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) -#define pCAN1_MB13_DATA2 ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */ -#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) -#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) -#define pCAN1_MB13_DATA3 ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */ -#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) -#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) -#define pCAN1_MB13_LENGTH ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */ -#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) -#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) -#define pCAN1_MB13_TIMESTAMP ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */ -#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) -#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) -#define pCAN1_MB13_ID0 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */ -#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) -#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) -#define pCAN1_MB13_ID1 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */ -#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) -#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) -#define pCAN1_MB14_DATA0 ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */ -#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) -#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) -#define pCAN1_MB14_DATA1 ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */ -#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) -#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) -#define pCAN1_MB14_DATA2 ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */ -#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) -#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) -#define pCAN1_MB14_DATA3 ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */ -#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) -#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) -#define pCAN1_MB14_LENGTH ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */ -#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) -#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) -#define pCAN1_MB14_TIMESTAMP ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */ -#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) -#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) -#define pCAN1_MB14_ID0 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */ -#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) -#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) -#define pCAN1_MB14_ID1 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */ -#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) -#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) -#define pCAN1_MB15_DATA0 ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */ -#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) -#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) -#define pCAN1_MB15_DATA1 ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */ -#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) -#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) -#define pCAN1_MB15_DATA2 ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */ -#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) -#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) -#define pCAN1_MB15_DATA3 ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */ -#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) -#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) -#define pCAN1_MB15_LENGTH ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */ -#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) -#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) -#define pCAN1_MB15_TIMESTAMP ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */ -#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) -#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) -#define pCAN1_MB15_ID0 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */ -#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) -#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) -#define pCAN1_MB15_ID1 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */ -#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) -#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) -#define pCAN1_MB16_DATA0 ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */ -#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) -#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) -#define pCAN1_MB16_DATA1 ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */ -#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) -#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) -#define pCAN1_MB16_DATA2 ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */ -#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) -#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) -#define pCAN1_MB16_DATA3 ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */ -#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) -#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) -#define pCAN1_MB16_LENGTH ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */ -#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) -#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) -#define pCAN1_MB16_TIMESTAMP ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */ -#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) -#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) -#define pCAN1_MB16_ID0 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */ -#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) -#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) -#define pCAN1_MB16_ID1 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */ -#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) -#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) -#define pCAN1_MB17_DATA0 ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */ -#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) -#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) -#define pCAN1_MB17_DATA1 ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */ -#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) -#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) -#define pCAN1_MB17_DATA2 ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */ -#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) -#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) -#define pCAN1_MB17_DATA3 ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */ -#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) -#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) -#define pCAN1_MB17_LENGTH ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */ -#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) -#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) -#define pCAN1_MB17_TIMESTAMP ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */ -#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) -#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) -#define pCAN1_MB17_ID0 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */ -#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) -#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) -#define pCAN1_MB17_ID1 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */ -#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) -#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) -#define pCAN1_MB18_DATA0 ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */ -#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) -#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) -#define pCAN1_MB18_DATA1 ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */ -#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) -#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) -#define pCAN1_MB18_DATA2 ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */ -#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) -#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) -#define pCAN1_MB18_DATA3 ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */ -#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) -#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) -#define pCAN1_MB18_LENGTH ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */ -#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) -#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) -#define pCAN1_MB18_TIMESTAMP ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */ -#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) -#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) -#define pCAN1_MB18_ID0 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */ -#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) -#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) -#define pCAN1_MB18_ID1 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */ -#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) -#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) -#define pCAN1_MB19_DATA0 ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */ -#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) -#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) -#define pCAN1_MB19_DATA1 ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */ -#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) -#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) -#define pCAN1_MB19_DATA2 ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */ -#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) -#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) -#define pCAN1_MB19_DATA3 ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */ -#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) -#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) -#define pCAN1_MB19_LENGTH ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */ -#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) -#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) -#define pCAN1_MB19_TIMESTAMP ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */ -#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) -#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) -#define pCAN1_MB19_ID0 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */ -#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) -#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) -#define pCAN1_MB19_ID1 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */ -#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) -#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) -#define pCAN1_MB20_DATA0 ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */ -#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) -#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) -#define pCAN1_MB20_DATA1 ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */ -#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) -#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) -#define pCAN1_MB20_DATA2 ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */ -#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) -#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) -#define pCAN1_MB20_DATA3 ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */ -#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) -#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) -#define pCAN1_MB20_LENGTH ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */ -#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) -#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) -#define pCAN1_MB20_TIMESTAMP ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */ -#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) -#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) -#define pCAN1_MB20_ID0 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */ -#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) -#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) -#define pCAN1_MB20_ID1 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */ -#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) -#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) -#define pCAN1_MB21_DATA0 ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */ -#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) -#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) -#define pCAN1_MB21_DATA1 ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */ -#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) -#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) -#define pCAN1_MB21_DATA2 ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */ -#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) -#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) -#define pCAN1_MB21_DATA3 ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */ -#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) -#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) -#define pCAN1_MB21_LENGTH ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */ -#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) -#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) -#define pCAN1_MB21_TIMESTAMP ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */ -#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) -#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) -#define pCAN1_MB21_ID0 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */ -#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) -#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) -#define pCAN1_MB21_ID1 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */ -#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) -#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) -#define pCAN1_MB22_DATA0 ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */ -#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) -#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) -#define pCAN1_MB22_DATA1 ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */ -#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) -#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) -#define pCAN1_MB22_DATA2 ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */ -#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) -#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) -#define pCAN1_MB22_DATA3 ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */ -#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) -#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) -#define pCAN1_MB22_LENGTH ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */ -#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) -#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) -#define pCAN1_MB22_TIMESTAMP ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */ -#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) -#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) -#define pCAN1_MB22_ID0 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */ -#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) -#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) -#define pCAN1_MB22_ID1 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */ -#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) -#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) -#define pCAN1_MB23_DATA0 ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */ -#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) -#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) -#define pCAN1_MB23_DATA1 ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */ -#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) -#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) -#define pCAN1_MB23_DATA2 ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */ -#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) -#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) -#define pCAN1_MB23_DATA3 ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */ -#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) -#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) -#define pCAN1_MB23_LENGTH ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */ -#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) -#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) -#define pCAN1_MB23_TIMESTAMP ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */ -#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) -#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) -#define pCAN1_MB23_ID0 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */ -#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) -#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) -#define pCAN1_MB23_ID1 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */ -#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) -#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) -#define pCAN1_MB24_DATA0 ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */ -#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) -#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) -#define pCAN1_MB24_DATA1 ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */ -#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) -#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) -#define pCAN1_MB24_DATA2 ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */ -#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) -#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) -#define pCAN1_MB24_DATA3 ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */ -#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) -#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) -#define pCAN1_MB24_LENGTH ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */ -#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) -#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) -#define pCAN1_MB24_TIMESTAMP ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */ -#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) -#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) -#define pCAN1_MB24_ID0 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */ -#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) -#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) -#define pCAN1_MB24_ID1 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */ -#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) -#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) -#define pCAN1_MB25_DATA0 ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */ -#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) -#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) -#define pCAN1_MB25_DATA1 ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */ -#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) -#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) -#define pCAN1_MB25_DATA2 ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */ -#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) -#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) -#define pCAN1_MB25_DATA3 ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */ -#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) -#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) -#define pCAN1_MB25_LENGTH ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */ -#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) -#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) -#define pCAN1_MB25_TIMESTAMP ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */ -#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) -#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) -#define pCAN1_MB25_ID0 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */ -#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) -#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) -#define pCAN1_MB25_ID1 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */ -#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) -#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) -#define pCAN1_MB26_DATA0 ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */ -#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) -#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) -#define pCAN1_MB26_DATA1 ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */ -#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) -#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) -#define pCAN1_MB26_DATA2 ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */ -#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) -#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) -#define pCAN1_MB26_DATA3 ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */ -#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) -#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) -#define pCAN1_MB26_LENGTH ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */ -#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) -#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) -#define pCAN1_MB26_TIMESTAMP ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */ -#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) -#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) -#define pCAN1_MB26_ID0 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */ -#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) -#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) -#define pCAN1_MB26_ID1 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */ -#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) -#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) -#define pCAN1_MB27_DATA0 ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */ -#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) -#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) -#define pCAN1_MB27_DATA1 ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */ -#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) -#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) -#define pCAN1_MB27_DATA2 ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */ -#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) -#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) -#define pCAN1_MB27_DATA3 ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */ -#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) -#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) -#define pCAN1_MB27_LENGTH ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */ -#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) -#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) -#define pCAN1_MB27_TIMESTAMP ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */ -#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) -#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) -#define pCAN1_MB27_ID0 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */ -#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) -#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) -#define pCAN1_MB27_ID1 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */ -#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) -#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) -#define pCAN1_MB28_DATA0 ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */ -#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) -#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) -#define pCAN1_MB28_DATA1 ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */ -#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) -#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) -#define pCAN1_MB28_DATA2 ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */ -#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) -#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) -#define pCAN1_MB28_DATA3 ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */ -#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) -#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) -#define pCAN1_MB28_LENGTH ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */ -#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) -#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) -#define pCAN1_MB28_TIMESTAMP ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */ -#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) -#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) -#define pCAN1_MB28_ID0 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */ -#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) -#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) -#define pCAN1_MB28_ID1 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */ -#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) -#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) -#define pCAN1_MB29_DATA0 ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */ -#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) -#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) -#define pCAN1_MB29_DATA1 ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */ -#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) -#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) -#define pCAN1_MB29_DATA2 ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */ -#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) -#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) -#define pCAN1_MB29_DATA3 ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */ -#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) -#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) -#define pCAN1_MB29_LENGTH ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */ -#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) -#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) -#define pCAN1_MB29_TIMESTAMP ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */ -#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) -#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) -#define pCAN1_MB29_ID0 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */ -#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) -#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) -#define pCAN1_MB29_ID1 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */ -#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) -#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) -#define pCAN1_MB30_DATA0 ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */ -#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) -#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) -#define pCAN1_MB30_DATA1 ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */ -#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) -#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) -#define pCAN1_MB30_DATA2 ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */ -#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) -#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) -#define pCAN1_MB30_DATA3 ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */ -#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) -#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) -#define pCAN1_MB30_LENGTH ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */ -#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) -#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) -#define pCAN1_MB30_TIMESTAMP ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */ -#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) -#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) -#define pCAN1_MB30_ID0 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */ -#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) -#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) -#define pCAN1_MB30_ID1 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */ -#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) -#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) -#define pCAN1_MB31_DATA0 ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */ -#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) -#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) -#define pCAN1_MB31_DATA1 ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */ -#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) -#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) -#define pCAN1_MB31_DATA2 ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */ -#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) -#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) -#define pCAN1_MB31_DATA3 ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */ -#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) -#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) -#define pCAN1_MB31_LENGTH ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */ -#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) -#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) -#define pCAN1_MB31_TIMESTAMP ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */ -#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) -#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) -#define pCAN1_MB31_ID0 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */ -#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) -#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) -#define pCAN1_MB31_ID1 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */ -#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) -#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) -#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */ -#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) -#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */ -#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) -#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */ -#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) -#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */ -#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) -#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */ -#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) -#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */ -#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) -#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) -#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */ -#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) -#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */ -#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) -#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */ -#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) -#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */ -#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) -#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */ -#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) -#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */ -#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) -#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) -#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */ -#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */ -#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL) -#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val) -#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */ -#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */ -#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */ -#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) -#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */ -#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */ -#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */ -#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */ -#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) -#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */ -#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */ -#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL) -#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val) -#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */ -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */ -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */ -#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) -#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) -#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */ -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */ -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */ -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */ -#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) -#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) -#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */ -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */ -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */ -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */ -#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) -#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */ -#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) -#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) -#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) -#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ -#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) -#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */ -#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) -#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) -#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) -#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */ -#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) -#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */ -#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) -#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) -#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) -#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */ -#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) -#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) -#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) -#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) -#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) -#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) -#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) -#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) -#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) -#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */ -#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) -#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */ -#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) -#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) -#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) -#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ -#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) -#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */ -#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) -#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) -#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) -#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */ -#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) -#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */ -#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) -#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) -#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) -#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */ -#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) -#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) -#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) -#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) -#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) -#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) -#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) -#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) -#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) -#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */ -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) -#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) -#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */ -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */ -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) -#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) -#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */ -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) -#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) -#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */ -#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) -#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */ -#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) -#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */ -#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) -#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */ -#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) -#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */ -#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) -#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */ -#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) -#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) -#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) -#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */ -#define bfin_read_UART3_THR() bfin_read16(UART3_THR) -#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */ -#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) -#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_BF544_extended__ */ diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_def.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_def.h deleted file mode 100644 index 3c14d22..0000000 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_def.h +++ /dev/null @@ -1,1665 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_BF544_extended__ -#define __BFIN_DEF_ADSP_EDN_BF544_extended__ - -#define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */ -#define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */ -#define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */ -#define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */ -#define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */ -#define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */ -#define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */ -#define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */ -#define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */ -#define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */ -#define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */ -#define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */ -#define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */ -#define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */ -#define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */ -#define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */ -#define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */ -#define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */ -#define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ -#define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */ -#define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ -#define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */ -#define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ -#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */ -#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */ -#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */ -#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */ -#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */ -#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */ -#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */ -#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */ -#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */ -#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */ -#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */ -#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */ -#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */ -#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */ -#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */ -#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */ -#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */ -#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */ -#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */ -#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */ -#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */ -#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */ -#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */ -#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */ -#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */ -#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */ -#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */ -#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */ -#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */ -#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */ -#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */ -#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */ -#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */ -#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */ -#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */ -#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */ -#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */ -#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */ -#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */ -#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */ -#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */ -#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */ -#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */ -#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */ -#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */ -#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */ -#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */ -#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */ -#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */ -#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */ -#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */ -#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */ -#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */ -#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */ -#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */ -#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */ -#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */ -#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */ -#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */ -#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */ -#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */ -#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */ -#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */ -#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */ -#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */ -#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */ -#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */ -#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */ -#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */ -#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */ -#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */ -#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */ -#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */ -#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */ -#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */ -#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */ -#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */ -#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */ -#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */ -#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */ -#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */ -#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */ -#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */ -#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */ -#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */ -#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */ -#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */ -#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */ -#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */ -#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */ -#define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */ -#define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */ -#define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */ -#define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */ -#define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */ -#define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */ -#define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */ -#define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */ -#define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */ -#define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */ -#define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */ -#define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */ -#define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */ -#define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */ -#define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */ -#define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */ -#define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */ -#define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */ -#define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */ -#define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */ -#define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */ -#define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */ -#define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */ -#define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */ -#define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */ -#define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */ -#define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */ -#define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */ -#define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */ -#define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */ -#define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */ -#define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */ -#define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */ -#define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */ -#define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */ -#define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */ -#define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */ -#define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */ -#define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */ -#define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */ -#define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */ -#define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */ -#define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */ -#define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */ -#define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */ -#define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */ -#define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */ -#define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */ -#define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */ -#define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */ -#define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */ -#define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */ -#define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */ -#define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */ -#define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */ -#define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */ -#define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */ -#define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */ -#define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */ -#define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */ -#define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */ -#define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */ -#define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */ -#define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */ -#define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */ -#define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */ -#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */ -#define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */ -#define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */ -#define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */ -#define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */ -#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */ -#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */ -#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */ -#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */ -#define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */ -#define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */ -#define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */ -#define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */ -#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */ -#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */ -#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */ -#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */ -#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */ -#define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */ -#define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */ -#define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */ -#define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */ -#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */ -#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */ -#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */ -#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */ -#define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */ -#define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */ -#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */ -#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */ -#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */ -#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */ -#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */ -#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */ -#define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */ -#define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */ -#define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */ -#define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */ -#define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */ -#define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */ -#define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */ -#define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */ -#define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */ -#define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */ -#define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */ -#define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */ -#define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */ -#define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ -#define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */ -#define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */ -#define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */ -#define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */ -#define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */ -#define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */ -#define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */ -#define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */ -#define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */ -#define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */ -#define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */ -#define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */ -#define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */ -#define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */ -#define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */ -#define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */ -#define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */ -#define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */ -#define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */ -#define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */ -#define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */ -#define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */ -#define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */ -#define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */ -#define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */ -#define PIXC_CTL 0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define PIXC_PPL 0xFFC04404 /* Holds the number of pixels per line of the display */ -#define PIXC_LPF 0xFFC04408 /* Holds the number of lines per frame of the display */ -#define PIXC_AHSTART 0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */ -#define PIXC_AHEND 0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */ -#define PIXC_AVSTART 0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */ -#define PIXC_AVEND 0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */ -#define PIXC_ATRANSP 0xFFC0441C /* Contains the transparency ratio (set A) */ -#define PIXC_BHSTART 0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */ -#define PIXC_BHEND 0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */ -#define PIXC_BVSTART 0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */ -#define PIXC_BVEND 0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */ -#define PIXC_BTRANSP 0xFFC04430 /* Contains the transparency ratio (set B) */ -#define PIXC_INTRSTAT 0xFFC0443C /* Overlay interrupt configuration/status */ -#define PIXC_RYCON 0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define PIXC_GUCON 0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define PIXC_BVCON 0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define PIXC_CCBIAS 0xFFC0444C /* Bias values for the color space conversion matrix */ -#define PIXC_TC 0xFFC04450 /* Holds the transparent color value */ -#define HOST_CONTROL 0xFFC03A00 /* HOSTDP Control Register */ -#define HOST_STATUS 0xFFC03A04 /* HOSTDP Status Register */ -#define HOST_TIMEOUT 0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */ -#define PORTA_FER 0xFFC014C0 /* Function Enable Register */ -#define PORTA 0xFFC014C4 /* GPIO Data Register */ -#define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */ -#define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */ -#define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */ -#define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */ -#define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */ -#define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */ -#define PORTB_FER 0xFFC014E0 /* Function Enable Register */ -#define PORTB 0xFFC014E4 /* GPIO Data Register */ -#define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */ -#define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */ -#define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */ -#define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */ -#define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */ -#define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */ -#define PORTC_FER 0xFFC01500 /* Function Enable Register */ -#define PORTC 0xFFC01504 /* GPIO Data Register */ -#define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */ -#define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */ -#define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */ -#define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */ -#define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */ -#define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */ -#define PORTD_FER 0xFFC01520 /* Function Enable Register */ -#define PORTD 0xFFC01524 /* GPIO Data Register */ -#define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */ -#define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */ -#define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */ -#define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */ -#define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */ -#define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */ -#define PORTE_FER 0xFFC01540 /* Function Enable Register */ -#define PORTE 0xFFC01544 /* GPIO Data Register */ -#define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */ -#define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */ -#define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */ -#define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */ -#define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */ -#define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */ -#define PORTF_FER 0xFFC01560 /* Function Enable Register */ -#define PORTF 0xFFC01564 /* GPIO Data Register */ -#define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */ -#define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */ -#define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */ -#define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */ -#define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */ -#define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */ -#define PORTG_FER 0xFFC01580 /* Function Enable Register */ -#define PORTG 0xFFC01584 /* GPIO Data Register */ -#define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */ -#define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */ -#define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */ -#define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */ -#define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */ -#define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */ -#define PORTH_FER 0xFFC015A0 /* Function Enable Register */ -#define PORTH 0xFFC015A4 /* GPIO Data Register */ -#define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */ -#define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */ -#define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */ -#define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */ -#define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */ -#define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */ -#define PORTI_FER 0xFFC015C0 /* Function Enable Register */ -#define PORTI 0xFFC015C4 /* GPIO Data Register */ -#define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */ -#define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */ -#define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */ -#define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */ -#define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */ -#define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */ -#define PORTJ_FER 0xFFC015E0 /* Function Enable Register */ -#define PORTJ 0xFFC015E4 /* GPIO Data Register */ -#define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */ -#define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */ -#define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */ -#define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */ -#define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */ -#define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */ -#define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */ -#define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */ -#define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */ -#define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */ -#define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */ -#define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */ -#define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */ -#define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */ -#define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */ -#define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */ -#define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */ -#define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */ -#define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */ -#define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */ -#define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */ -#define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */ -#define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */ -#define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */ -#define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */ -#define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */ -#define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */ -#define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */ -#define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */ -#define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */ -#define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */ -#define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */ -#define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */ -#define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */ -#define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */ -#define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */ -#define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */ -#define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */ -#define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */ -#define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */ -#define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */ -#define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */ -#define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */ -#define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */ -#define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */ -#define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */ -#define TIMER8_CONFIG 0xFFC00600 /* Timer 8 Configuration Register */ -#define TIMER8_COUNTER 0xFFC00604 /* Timer 8 Counter Register */ -#define TIMER8_PERIOD 0xFFC00608 /* Timer 8 Period Register */ -#define TIMER8_WIDTH 0xFFC0060C /* Timer 8 Width Register */ -#define TIMER9_CONFIG 0xFFC00610 /* Timer 9 Configuration Register */ -#define TIMER9_COUNTER 0xFFC00614 /* Timer 9 Counter Register */ -#define TIMER9_PERIOD 0xFFC00618 /* Timer 9 Period Register */ -#define TIMER9_WIDTH 0xFFC0061C /* Timer 9 Width Register */ -#define TIMER10_CONFIG 0xFFC00620 /* Timer 10 Configuration Register */ -#define TIMER10_COUNTER 0xFFC00624 /* Timer 10 Counter Register */ -#define TIMER10_PERIOD 0xFFC00628 /* Timer 10 Period Register */ -#define TIMER10_WIDTH 0xFFC0062C /* Timer 10 Width Register */ -#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */ -#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */ -#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */ -#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */ -#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */ -#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define CNT_CONFIG 0xFFC04200 /* Configuration Register */ -#define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */ -#define CNT_STATUS 0xFFC04208 /* Status Register */ -#define CNT_COMMAND 0xFFC0420C /* Command Register */ -#define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */ -#define CNT_COUNTER 0xFFC04214 /* Counter Register */ -#define CNT_MAX 0xFFC04218 /* Maximal Count Register */ -#define CNT_MIN 0xFFC0421C /* Minimal Count Register */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ -#define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */ -#define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */ -#define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */ -#define SECURE_CONTROL 0xFFC04324 /* Secure Control */ -#define SECURE_STATUS 0xFFC04328 /* Secure Status */ -#define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divisor Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define NFC_CTL 0xFFC03B00 /* NAND Control Register */ -#define NFC_STAT 0xFFC03B04 /* NAND Status Register */ -#define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */ -#define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */ -#define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */ -#define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */ -#define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */ -#define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */ -#define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */ -#define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */ -#define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */ -#define NFC_READ 0xFFC03B2C /* NAND Read Data Register */ -#define NFC_ADDR 0xFFC03B40 /* NAND Address Register */ -#define NFC_CMD 0xFFC03B44 /* NAND Command Register */ -#define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */ -#define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */ -#define EPPI0_STATUS 0xFFC01000 /* EPPI0 Status Register */ -#define EPPI0_HCOUNT 0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */ -#define EPPI0_HDELAY 0xFFC01008 /* EPPI0 Horizontal Delay Count Register */ -#define EPPI0_VCOUNT 0xFFC0100C /* EPPI0 Vertical Transfer Count Register */ -#define EPPI0_VDELAY 0xFFC01010 /* EPPI0 Vertical Delay Count Register */ -#define EPPI0_FRAME 0xFFC01014 /* EPPI0 Lines per Frame Register */ -#define EPPI0_LINE 0xFFC01018 /* EPPI0 Samples per Line Register */ -#define EPPI0_CLKDIV 0xFFC0101C /* EPPI0 Clock Divide Register */ -#define EPPI0_CONTROL 0xFFC01020 /* EPPI0 Control Register */ -#define EPPI0_FS1W_HBL 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define EPPI0_FS1P_AVPL 0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define EPPI0_FS2W_LVB 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define EPPI0_FS2P_LAVF 0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define EPPI0_CLIP 0xFFC01034 /* EPPI0 Clipping Register */ -#define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */ -#define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */ -#define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */ -#define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */ -#define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */ -#define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */ -#define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */ -#define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */ -#define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */ -#define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */ -#define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */ -#define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */ -#define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */ -#define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */ -#define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */ -#define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */ -#define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */ -#define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */ -#define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */ -#define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */ -#define CAN0_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */ -#define CAN0_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */ -#define CAN0_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */ -#define CAN0_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */ -#define CAN0_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ -#define CAN0_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */ -#define CAN0_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */ -#define CAN0_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */ -#define CAN0_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN0_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN0_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ -#define CAN0_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ -#define CAN0_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ -#define CAN0_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */ -#define CAN0_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */ -#define CAN0_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */ -#define CAN0_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */ -#define CAN0_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ -#define CAN0_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */ -#define CAN0_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */ -#define CAN0_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */ -#define CAN0_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN0_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN0_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ -#define CAN0_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ -#define CAN0_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ -#define CAN0_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */ -#define CAN0_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */ -#define CAN0_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */ -#define CAN0_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */ -#define CAN0_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */ -#define CAN0_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */ -#define CAN0_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */ -#define CAN0_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */ -#define CAN0_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */ -#define CAN0_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */ -#define CAN0_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */ -#define CAN0_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */ -#define CAN0_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */ -#define CAN0_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */ -#define CAN0_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */ -#define CAN0_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */ -#define CAN0_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ -#define CAN0_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ -#define CAN0_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ -#define CAN0_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ -#define CAN0_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ -#define CAN0_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ -#define CAN0_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ -#define CAN0_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ -#define CAN0_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ -#define CAN0_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ -#define CAN0_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ -#define CAN0_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ -#define CAN0_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ -#define CAN0_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ -#define CAN0_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ -#define CAN0_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ -#define CAN0_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ -#define CAN0_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ -#define CAN0_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ -#define CAN0_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ -#define CAN0_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ -#define CAN0_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ -#define CAN0_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ -#define CAN0_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ -#define CAN0_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ -#define CAN0_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ -#define CAN0_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ -#define CAN0_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ -#define CAN0_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ -#define CAN0_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ -#define CAN0_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ -#define CAN0_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ -#define CAN0_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ -#define CAN0_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ -#define CAN0_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ -#define CAN0_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ -#define CAN0_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ -#define CAN0_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ -#define CAN0_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ -#define CAN0_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ -#define CAN0_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ -#define CAN0_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ -#define CAN0_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ -#define CAN0_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ -#define CAN0_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ -#define CAN0_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ -#define CAN0_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ -#define CAN0_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ -#define CAN0_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ -#define CAN0_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ -#define CAN0_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ -#define CAN0_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ -#define CAN0_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ -#define CAN0_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ -#define CAN0_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ -#define CAN0_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ -#define CAN0_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ -#define CAN0_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ -#define CAN0_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ -#define CAN0_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ -#define CAN0_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ -#define CAN0_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ -#define CAN0_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ -#define CAN0_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ -#define CAN0_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ -#define CAN0_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ -#define CAN0_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ -#define CAN0_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */ -#define CAN0_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */ -#define CAN0_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ -#define CAN0_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */ -#define CAN0_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */ -#define CAN0_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ -#define CAN0_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ -#define CAN0_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ -#define CAN0_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */ -#define CAN0_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */ -#define CAN0_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ -#define CAN0_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */ -#define CAN0_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */ -#define CAN0_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ -#define CAN0_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ -#define CAN0_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ -#define CAN0_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */ -#define CAN0_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */ -#define CAN0_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ -#define CAN0_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */ -#define CAN0_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */ -#define CAN0_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ -#define CAN0_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ -#define CAN0_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ -#define CAN0_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */ -#define CAN0_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */ -#define CAN0_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ -#define CAN0_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */ -#define CAN0_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */ -#define CAN0_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ -#define CAN0_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ -#define CAN0_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ -#define CAN0_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */ -#define CAN0_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */ -#define CAN0_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ -#define CAN0_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */ -#define CAN0_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */ -#define CAN0_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ -#define CAN0_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ -#define CAN0_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ -#define CAN0_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */ -#define CAN0_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */ -#define CAN0_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ -#define CAN0_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */ -#define CAN0_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */ -#define CAN0_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ -#define CAN0_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ -#define CAN0_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ -#define CAN0_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */ -#define CAN0_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */ -#define CAN0_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ -#define CAN0_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */ -#define CAN0_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */ -#define CAN0_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ -#define CAN0_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ -#define CAN0_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ -#define CAN0_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */ -#define CAN0_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */ -#define CAN0_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ -#define CAN0_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */ -#define CAN0_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */ -#define CAN0_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ -#define CAN0_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ -#define CAN0_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ -#define CAN0_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */ -#define CAN0_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */ -#define CAN0_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ -#define CAN0_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */ -#define CAN0_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */ -#define CAN0_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ -#define CAN0_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ -#define CAN0_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ -#define CAN0_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */ -#define CAN0_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */ -#define CAN0_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ -#define CAN0_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */ -#define CAN0_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */ -#define CAN0_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ -#define CAN0_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ -#define CAN0_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ -#define CAN0_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */ -#define CAN0_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */ -#define CAN0_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ -#define CAN0_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */ -#define CAN0_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */ -#define CAN0_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ -#define CAN0_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ -#define CAN0_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ -#define CAN0_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */ -#define CAN0_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */ -#define CAN0_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ -#define CAN0_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */ -#define CAN0_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */ -#define CAN0_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ -#define CAN0_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ -#define CAN0_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ -#define CAN0_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */ -#define CAN0_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */ -#define CAN0_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ -#define CAN0_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */ -#define CAN0_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */ -#define CAN0_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ -#define CAN0_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ -#define CAN0_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ -#define CAN0_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */ -#define CAN0_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */ -#define CAN0_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ -#define CAN0_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */ -#define CAN0_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */ -#define CAN0_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ -#define CAN0_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ -#define CAN0_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ -#define CAN0_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */ -#define CAN0_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */ -#define CAN0_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ -#define CAN0_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */ -#define CAN0_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */ -#define CAN0_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ -#define CAN0_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ -#define CAN0_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ -#define CAN0_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */ -#define CAN0_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */ -#define CAN0_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ -#define CAN0_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */ -#define CAN0_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */ -#define CAN0_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ -#define CAN0_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ -#define CAN0_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ -#define CAN0_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */ -#define CAN0_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */ -#define CAN0_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ -#define CAN0_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */ -#define CAN0_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */ -#define CAN0_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ -#define CAN0_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ -#define CAN0_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ -#define CAN0_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */ -#define CAN0_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */ -#define CAN0_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ -#define CAN0_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */ -#define CAN0_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */ -#define CAN0_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ -#define CAN0_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ -#define CAN0_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ -#define CAN0_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */ -#define CAN0_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */ -#define CAN0_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ -#define CAN0_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */ -#define CAN0_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */ -#define CAN0_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ -#define CAN0_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ -#define CAN0_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ -#define CAN0_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */ -#define CAN0_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */ -#define CAN0_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ -#define CAN0_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */ -#define CAN0_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */ -#define CAN0_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ -#define CAN0_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ -#define CAN0_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ -#define CAN0_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */ -#define CAN0_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */ -#define CAN0_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ -#define CAN0_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */ -#define CAN0_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */ -#define CAN0_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ -#define CAN0_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ -#define CAN0_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ -#define CAN0_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */ -#define CAN0_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */ -#define CAN0_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ -#define CAN0_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */ -#define CAN0_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */ -#define CAN0_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ -#define CAN0_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ -#define CAN0_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ -#define CAN0_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */ -#define CAN0_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */ -#define CAN0_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ -#define CAN0_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */ -#define CAN0_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */ -#define CAN0_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ -#define CAN0_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ -#define CAN0_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ -#define CAN0_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */ -#define CAN0_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */ -#define CAN0_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ -#define CAN0_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */ -#define CAN0_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */ -#define CAN0_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ -#define CAN0_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ -#define CAN0_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ -#define CAN0_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */ -#define CAN0_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */ -#define CAN0_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ -#define CAN0_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */ -#define CAN0_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */ -#define CAN0_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ -#define CAN0_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ -#define CAN0_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ -#define CAN0_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */ -#define CAN0_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */ -#define CAN0_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ -#define CAN0_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */ -#define CAN0_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */ -#define CAN0_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ -#define CAN0_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ -#define CAN0_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ -#define CAN0_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */ -#define CAN0_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */ -#define CAN0_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ -#define CAN0_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */ -#define CAN0_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */ -#define CAN0_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ -#define CAN0_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ -#define CAN0_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ -#define CAN0_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */ -#define CAN0_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */ -#define CAN0_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ -#define CAN0_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */ -#define CAN0_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */ -#define CAN0_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ -#define CAN0_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ -#define CAN0_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ -#define CAN0_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */ -#define CAN0_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */ -#define CAN0_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ -#define CAN0_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */ -#define CAN0_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */ -#define CAN0_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ -#define CAN0_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ -#define CAN0_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ -#define CAN0_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */ -#define CAN0_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */ -#define CAN0_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ -#define CAN0_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */ -#define CAN0_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */ -#define CAN0_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ -#define CAN0_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ -#define CAN0_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ -#define CAN0_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */ -#define CAN0_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */ -#define CAN0_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ -#define CAN0_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */ -#define CAN0_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */ -#define CAN0_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ -#define CAN0_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ -#define CAN0_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ -#define CAN0_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */ -#define CAN0_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */ -#define CAN0_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ -#define CAN0_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */ -#define CAN0_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */ -#define CAN1_MC1 0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ -#define CAN1_MD1 0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */ -#define CAN1_TRS1 0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */ -#define CAN1_TRR1 0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */ -#define CAN1_TA1 0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ -#define CAN1_AA1 0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ -#define CAN1_RMP1 0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */ -#define CAN1_RML1 0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */ -#define CAN1_MBTIF1 0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN1_MBRIF1 0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN1_MBIM1 0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ -#define CAN1_RFH1 0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ -#define CAN1_OPSS1 0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ -#define CAN1_MC2 0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ -#define CAN1_MD2 0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */ -#define CAN1_TRS2 0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */ -#define CAN1_TRR2 0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */ -#define CAN1_TA2 0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ -#define CAN1_AA2 0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ -#define CAN1_RMP2 0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */ -#define CAN1_RML2 0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */ -#define CAN1_MBTIF2 0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN1_MBRIF2 0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN1_MBIM2 0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ -#define CAN1_RFH2 0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ -#define CAN1_OPSS2 0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ -#define CAN1_CLOCK 0xFFC03280 /* CAN Controller 1 Clock Register */ -#define CAN1_TIMING 0xFFC03284 /* CAN Controller 1 Timing Register */ -#define CAN1_DEBUG 0xFFC03288 /* CAN Controller 1 Debug Register */ -#define CAN1_STATUS 0xFFC0328C /* CAN Controller 1 Global Status Register */ -#define CAN1_CEC 0xFFC03290 /* CAN Controller 1 Error Counter Register */ -#define CAN1_GIS 0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */ -#define CAN1_GIM 0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */ -#define CAN1_GIF 0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */ -#define CAN1_CONTROL 0xFFC032A0 /* CAN Controller 1 Master Control Register */ -#define CAN1_INTR 0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */ -#define CAN1_MBTD 0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */ -#define CAN1_EWR 0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */ -#define CAN1_ESR 0xFFC032B4 /* CAN Controller 1 Error Status Register */ -#define CAN1_UCCNT 0xFFC032C4 /* CAN Controller 1 Universal Counter Register */ -#define CAN1_UCRC 0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */ -#define CAN1_UCCNF 0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */ -#define CAN1_AM00L 0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ -#define CAN1_AM00H 0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ -#define CAN1_AM01L 0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ -#define CAN1_AM01H 0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ -#define CAN1_AM02L 0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ -#define CAN1_AM02H 0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ -#define CAN1_AM03L 0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ -#define CAN1_AM03H 0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ -#define CAN1_AM04L 0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ -#define CAN1_AM04H 0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ -#define CAN1_AM05L 0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ -#define CAN1_AM05H 0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ -#define CAN1_AM06L 0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ -#define CAN1_AM06H 0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ -#define CAN1_AM07L 0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ -#define CAN1_AM07H 0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ -#define CAN1_AM08L 0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ -#define CAN1_AM08H 0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ -#define CAN1_AM09L 0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ -#define CAN1_AM09H 0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ -#define CAN1_AM10L 0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ -#define CAN1_AM10H 0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ -#define CAN1_AM11L 0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ -#define CAN1_AM11H 0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ -#define CAN1_AM12L 0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ -#define CAN1_AM12H 0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ -#define CAN1_AM13L 0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ -#define CAN1_AM13H 0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ -#define CAN1_AM14L 0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ -#define CAN1_AM14H 0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ -#define CAN1_AM15L 0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ -#define CAN1_AM15H 0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ -#define CAN1_AM16L 0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ -#define CAN1_AM16H 0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ -#define CAN1_AM17L 0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ -#define CAN1_AM17H 0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ -#define CAN1_AM18L 0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ -#define CAN1_AM18H 0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ -#define CAN1_AM19L 0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ -#define CAN1_AM19H 0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ -#define CAN1_AM20L 0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ -#define CAN1_AM20H 0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ -#define CAN1_AM21L 0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ -#define CAN1_AM21H 0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ -#define CAN1_AM22L 0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ -#define CAN1_AM22H 0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ -#define CAN1_AM23L 0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ -#define CAN1_AM23H 0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ -#define CAN1_AM24L 0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ -#define CAN1_AM24H 0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ -#define CAN1_AM25L 0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ -#define CAN1_AM25H 0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ -#define CAN1_AM26L 0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ -#define CAN1_AM26H 0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ -#define CAN1_AM27L 0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ -#define CAN1_AM27H 0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ -#define CAN1_AM28L 0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ -#define CAN1_AM28H 0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ -#define CAN1_AM29L 0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ -#define CAN1_AM29H 0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ -#define CAN1_AM30L 0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ -#define CAN1_AM30H 0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ -#define CAN1_AM31L 0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ -#define CAN1_AM31H 0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ -#define CAN1_MB00_DATA0 0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ -#define CAN1_MB00_DATA1 0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ -#define CAN1_MB00_DATA2 0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ -#define CAN1_MB00_DATA3 0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */ -#define CAN1_MB00_LENGTH 0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */ -#define CAN1_MB00_TIMESTAMP 0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ -#define CAN1_MB00_ID0 0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ -#define CAN1_MB00_ID1 0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */ -#define CAN1_MB01_DATA0 0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ -#define CAN1_MB01_DATA1 0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ -#define CAN1_MB01_DATA2 0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ -#define CAN1_MB01_DATA3 0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */ -#define CAN1_MB01_LENGTH 0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */ -#define CAN1_MB01_TIMESTAMP 0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ -#define CAN1_MB01_ID0 0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ -#define CAN1_MB01_ID1 0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */ -#define CAN1_MB02_DATA0 0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ -#define CAN1_MB02_DATA1 0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ -#define CAN1_MB02_DATA2 0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ -#define CAN1_MB02_DATA3 0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */ -#define CAN1_MB02_LENGTH 0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */ -#define CAN1_MB02_TIMESTAMP 0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ -#define CAN1_MB02_ID0 0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ -#define CAN1_MB02_ID1 0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */ -#define CAN1_MB03_DATA0 0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ -#define CAN1_MB03_DATA1 0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ -#define CAN1_MB03_DATA2 0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ -#define CAN1_MB03_DATA3 0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */ -#define CAN1_MB03_LENGTH 0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */ -#define CAN1_MB03_TIMESTAMP 0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ -#define CAN1_MB03_ID0 0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ -#define CAN1_MB03_ID1 0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */ -#define CAN1_MB04_DATA0 0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ -#define CAN1_MB04_DATA1 0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ -#define CAN1_MB04_DATA2 0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ -#define CAN1_MB04_DATA3 0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */ -#define CAN1_MB04_LENGTH 0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */ -#define CAN1_MB04_TIMESTAMP 0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ -#define CAN1_MB04_ID0 0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ -#define CAN1_MB04_ID1 0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */ -#define CAN1_MB05_DATA0 0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ -#define CAN1_MB05_DATA1 0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ -#define CAN1_MB05_DATA2 0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ -#define CAN1_MB05_DATA3 0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */ -#define CAN1_MB05_LENGTH 0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */ -#define CAN1_MB05_TIMESTAMP 0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ -#define CAN1_MB05_ID0 0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */ -#define CAN1_MB05_ID1 0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */ -#define CAN1_MB06_DATA0 0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ -#define CAN1_MB06_DATA1 0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ -#define CAN1_MB06_DATA2 0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ -#define CAN1_MB06_DATA3 0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */ -#define CAN1_MB06_LENGTH 0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */ -#define CAN1_MB06_TIMESTAMP 0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ -#define CAN1_MB06_ID0 0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */ -#define CAN1_MB06_ID1 0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */ -#define CAN1_MB07_DATA0 0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ -#define CAN1_MB07_DATA1 0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ -#define CAN1_MB07_DATA2 0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ -#define CAN1_MB07_DATA3 0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */ -#define CAN1_MB07_LENGTH 0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */ -#define CAN1_MB07_TIMESTAMP 0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ -#define CAN1_MB07_ID0 0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */ -#define CAN1_MB07_ID1 0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */ -#define CAN1_MB08_DATA0 0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ -#define CAN1_MB08_DATA1 0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ -#define CAN1_MB08_DATA2 0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ -#define CAN1_MB08_DATA3 0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */ -#define CAN1_MB08_LENGTH 0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */ -#define CAN1_MB08_TIMESTAMP 0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ -#define CAN1_MB08_ID0 0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ -#define CAN1_MB08_ID1 0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */ -#define CAN1_MB09_DATA0 0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ -#define CAN1_MB09_DATA1 0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ -#define CAN1_MB09_DATA2 0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ -#define CAN1_MB09_DATA3 0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */ -#define CAN1_MB09_LENGTH 0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */ -#define CAN1_MB09_TIMESTAMP 0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ -#define CAN1_MB09_ID0 0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ -#define CAN1_MB09_ID1 0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */ -#define CAN1_MB10_DATA0 0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ -#define CAN1_MB10_DATA1 0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ -#define CAN1_MB10_DATA2 0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ -#define CAN1_MB10_DATA3 0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */ -#define CAN1_MB10_LENGTH 0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */ -#define CAN1_MB10_TIMESTAMP 0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ -#define CAN1_MB10_ID0 0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ -#define CAN1_MB10_ID1 0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */ -#define CAN1_MB11_DATA0 0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ -#define CAN1_MB11_DATA1 0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ -#define CAN1_MB11_DATA2 0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ -#define CAN1_MB11_DATA3 0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */ -#define CAN1_MB11_LENGTH 0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */ -#define CAN1_MB11_TIMESTAMP 0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ -#define CAN1_MB11_ID0 0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ -#define CAN1_MB11_ID1 0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */ -#define CAN1_MB12_DATA0 0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ -#define CAN1_MB12_DATA1 0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ -#define CAN1_MB12_DATA2 0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ -#define CAN1_MB12_DATA3 0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */ -#define CAN1_MB12_LENGTH 0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */ -#define CAN1_MB12_TIMESTAMP 0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ -#define CAN1_MB12_ID0 0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ -#define CAN1_MB12_ID1 0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */ -#define CAN1_MB13_DATA0 0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ -#define CAN1_MB13_DATA1 0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ -#define CAN1_MB13_DATA2 0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ -#define CAN1_MB13_DATA3 0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */ -#define CAN1_MB13_LENGTH 0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */ -#define CAN1_MB13_TIMESTAMP 0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ -#define CAN1_MB13_ID0 0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */ -#define CAN1_MB13_ID1 0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */ -#define CAN1_MB14_DATA0 0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ -#define CAN1_MB14_DATA1 0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ -#define CAN1_MB14_DATA2 0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ -#define CAN1_MB14_DATA3 0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */ -#define CAN1_MB14_LENGTH 0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */ -#define CAN1_MB14_TIMESTAMP 0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ -#define CAN1_MB14_ID0 0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */ -#define CAN1_MB14_ID1 0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */ -#define CAN1_MB15_DATA0 0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ -#define CAN1_MB15_DATA1 0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ -#define CAN1_MB15_DATA2 0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ -#define CAN1_MB15_DATA3 0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */ -#define CAN1_MB15_LENGTH 0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */ -#define CAN1_MB15_TIMESTAMP 0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ -#define CAN1_MB15_ID0 0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */ -#define CAN1_MB15_ID1 0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */ -#define CAN1_MB16_DATA0 0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ -#define CAN1_MB16_DATA1 0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ -#define CAN1_MB16_DATA2 0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ -#define CAN1_MB16_DATA3 0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */ -#define CAN1_MB16_LENGTH 0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */ -#define CAN1_MB16_TIMESTAMP 0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ -#define CAN1_MB16_ID0 0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ -#define CAN1_MB16_ID1 0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */ -#define CAN1_MB17_DATA0 0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ -#define CAN1_MB17_DATA1 0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ -#define CAN1_MB17_DATA2 0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ -#define CAN1_MB17_DATA3 0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */ -#define CAN1_MB17_LENGTH 0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */ -#define CAN1_MB17_TIMESTAMP 0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ -#define CAN1_MB17_ID0 0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ -#define CAN1_MB17_ID1 0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */ -#define CAN1_MB18_DATA0 0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ -#define CAN1_MB18_DATA1 0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ -#define CAN1_MB18_DATA2 0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ -#define CAN1_MB18_DATA3 0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */ -#define CAN1_MB18_LENGTH 0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */ -#define CAN1_MB18_TIMESTAMP 0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ -#define CAN1_MB18_ID0 0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ -#define CAN1_MB18_ID1 0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */ -#define CAN1_MB19_DATA0 0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ -#define CAN1_MB19_DATA1 0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ -#define CAN1_MB19_DATA2 0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ -#define CAN1_MB19_DATA3 0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */ -#define CAN1_MB19_LENGTH 0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */ -#define CAN1_MB19_TIMESTAMP 0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ -#define CAN1_MB19_ID0 0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ -#define CAN1_MB19_ID1 0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */ -#define CAN1_MB20_DATA0 0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ -#define CAN1_MB20_DATA1 0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ -#define CAN1_MB20_DATA2 0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ -#define CAN1_MB20_DATA3 0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */ -#define CAN1_MB20_LENGTH 0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */ -#define CAN1_MB20_TIMESTAMP 0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ -#define CAN1_MB20_ID0 0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ -#define CAN1_MB20_ID1 0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */ -#define CAN1_MB21_DATA0 0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ -#define CAN1_MB21_DATA1 0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ -#define CAN1_MB21_DATA2 0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ -#define CAN1_MB21_DATA3 0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */ -#define CAN1_MB21_LENGTH 0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */ -#define CAN1_MB21_TIMESTAMP 0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ -#define CAN1_MB21_ID0 0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */ -#define CAN1_MB21_ID1 0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */ -#define CAN1_MB22_DATA0 0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ -#define CAN1_MB22_DATA1 0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ -#define CAN1_MB22_DATA2 0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ -#define CAN1_MB22_DATA3 0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */ -#define CAN1_MB22_LENGTH 0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */ -#define CAN1_MB22_TIMESTAMP 0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ -#define CAN1_MB22_ID0 0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */ -#define CAN1_MB22_ID1 0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */ -#define CAN1_MB23_DATA0 0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ -#define CAN1_MB23_DATA1 0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ -#define CAN1_MB23_DATA2 0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ -#define CAN1_MB23_DATA3 0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */ -#define CAN1_MB23_LENGTH 0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */ -#define CAN1_MB23_TIMESTAMP 0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ -#define CAN1_MB23_ID0 0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */ -#define CAN1_MB23_ID1 0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */ -#define CAN1_MB24_DATA0 0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ -#define CAN1_MB24_DATA1 0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ -#define CAN1_MB24_DATA2 0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ -#define CAN1_MB24_DATA3 0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */ -#define CAN1_MB24_LENGTH 0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */ -#define CAN1_MB24_TIMESTAMP 0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ -#define CAN1_MB24_ID0 0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ -#define CAN1_MB24_ID1 0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */ -#define CAN1_MB25_DATA0 0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ -#define CAN1_MB25_DATA1 0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ -#define CAN1_MB25_DATA2 0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ -#define CAN1_MB25_DATA3 0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */ -#define CAN1_MB25_LENGTH 0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */ -#define CAN1_MB25_TIMESTAMP 0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ -#define CAN1_MB25_ID0 0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ -#define CAN1_MB25_ID1 0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */ -#define CAN1_MB26_DATA0 0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ -#define CAN1_MB26_DATA1 0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ -#define CAN1_MB26_DATA2 0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ -#define CAN1_MB26_DATA3 0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */ -#define CAN1_MB26_LENGTH 0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */ -#define CAN1_MB26_TIMESTAMP 0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ -#define CAN1_MB26_ID0 0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ -#define CAN1_MB26_ID1 0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */ -#define CAN1_MB27_DATA0 0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ -#define CAN1_MB27_DATA1 0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ -#define CAN1_MB27_DATA2 0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ -#define CAN1_MB27_DATA3 0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */ -#define CAN1_MB27_LENGTH 0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */ -#define CAN1_MB27_TIMESTAMP 0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ -#define CAN1_MB27_ID0 0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ -#define CAN1_MB27_ID1 0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */ -#define CAN1_MB28_DATA0 0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ -#define CAN1_MB28_DATA1 0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ -#define CAN1_MB28_DATA2 0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ -#define CAN1_MB28_DATA3 0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */ -#define CAN1_MB28_LENGTH 0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */ -#define CAN1_MB28_TIMESTAMP 0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ -#define CAN1_MB28_ID0 0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ -#define CAN1_MB28_ID1 0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */ -#define CAN1_MB29_DATA0 0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ -#define CAN1_MB29_DATA1 0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ -#define CAN1_MB29_DATA2 0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ -#define CAN1_MB29_DATA3 0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */ -#define CAN1_MB29_LENGTH 0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */ -#define CAN1_MB29_TIMESTAMP 0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ -#define CAN1_MB29_ID0 0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */ -#define CAN1_MB29_ID1 0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */ -#define CAN1_MB30_DATA0 0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ -#define CAN1_MB30_DATA1 0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ -#define CAN1_MB30_DATA2 0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ -#define CAN1_MB30_DATA3 0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */ -#define CAN1_MB30_LENGTH 0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */ -#define CAN1_MB30_TIMESTAMP 0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ -#define CAN1_MB30_ID0 0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */ -#define CAN1_MB30_ID1 0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */ -#define CAN1_MB31_DATA0 0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ -#define CAN1_MB31_DATA1 0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ -#define CAN1_MB31_DATA2 0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ -#define CAN1_MB31_DATA3 0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */ -#define CAN1_MB31_LENGTH 0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */ -#define CAN1_MB31_TIMESTAMP 0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ -#define CAN1_MB31_ID0 0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */ -#define CAN1_MB31_ID1 0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */ -#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ -#define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */ -#define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */ -#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ -#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ -#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */ -#define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */ -#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ -#define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */ -#define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */ -#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ -#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ -#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */ -#define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */ -#define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */ -#define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */ -#define TWI1_CLKDIV 0xFFC02200 /* Clock Divider Register */ -#define TWI1_CONTROL 0xFFC02204 /* TWI Control Register */ -#define TWI1_SLAVE_CTL 0xFFC02208 /* TWI Slave Mode Control Register */ -#define TWI1_SLAVE_STAT 0xFFC0220C /* TWI Slave Mode Status Register */ -#define TWI1_SLAVE_ADDR 0xFFC02210 /* TWI Slave Mode Address Register */ -#define TWI1_MASTER_CTL 0xFFC02214 /* TWI Master Mode Control Register */ -#define TWI1_MASTER_STAT 0xFFC02218 /* TWI Master Mode Status Register */ -#define TWI1_MASTER_ADDR 0xFFC0221C /* TWI Master Mode Address Register */ -#define TWI1_INT_STAT 0xFFC02220 /* TWI Interrupt Status Register */ -#define TWI1_INT_MASK 0xFFC02224 /* TWI Interrupt Mask Register */ -#define TWI1_FIFO_CTL 0xFFC02228 /* TWI FIFO Control Register */ -#define TWI1_FIFO_STAT 0xFFC0222C /* TWI FIFO Status Register */ -#define TWI1_XMT_DATA8 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI1_XMT_DATA16 0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI1_RCV_DATA8 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI1_RCV_DATA16 0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */ -#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ -#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ -#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */ -#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */ -#define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */ -#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */ -#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */ -#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */ -#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */ -#define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */ -#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ -#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */ -#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */ -#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ -#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */ -#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */ -#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */ -#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */ -#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */ -#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */ -#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */ -#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */ -#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ -#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ -#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */ -#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */ -#define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */ -#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */ -#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */ -#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */ -#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */ -#define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */ -#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ -#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */ -#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */ -#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ -#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */ -#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */ -#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */ -#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */ -#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */ -#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */ -#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */ -#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */ -#define UART0_GCTL 0xFFC00408 /* Global Control Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* Scratch Register */ -#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */ -#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */ -#define UART0_THR 0xFFC00428 /* Transmit Hold Register */ -#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */ -#define UART1_GCTL 0xFFC02008 /* Global Control Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* Scratch Register */ -#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */ -#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */ -#define UART1_THR 0xFFC02028 /* Transmit Hold Register */ -#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */ -#define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */ -#define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */ -#define UART3_GCTL 0xFFC03108 /* Global Control Register */ -#define UART3_LCR 0xFFC0310C /* Line Control Register */ -#define UART3_MCR 0xFFC03110 /* Modem Control Register */ -#define UART3_LSR 0xFFC03114 /* Line Status Register */ -#define UART3_MSR 0xFFC03118 /* Modem Status Register */ -#define UART3_SCR 0xFFC0311C /* Scratch Register */ -#define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */ -#define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */ -#define UART3_THR 0xFFC03128 /* Transmit Hold Register */ -#define UART3_RBR 0xFFC0312C /* Receive Buffer Register */ - -#endif /* __BFIN_DEF_ADSP_EDN_BF544_extended__ */ diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h deleted file mode 100644 index e0f76ae..0000000 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h +++ /dev/null @@ -1,3615 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_BF547_extended__ -#define __BFIN_CDEF_ADSP_EDN_BF547_extended__ - -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */ -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */ -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */ -#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) -#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */ -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */ -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */ -#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) -#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */ -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */ -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */ -#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) -#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */ -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */ -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */ -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */ -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */ -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */ -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */ -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */ -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */ -#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) -#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */ -#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) -#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */ -#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) -#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */ -#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) -#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) -#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */ -#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) -#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) -#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */ -#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) -#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) -#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */ -#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) -#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) -#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */ -#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) -#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) -#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */ -#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) -#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ -#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ -#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ -#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ -#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ -#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ -#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ -#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ -#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ -#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ -#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ -#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ -#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ -#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ -#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ -#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ -#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ -#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ -#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ -#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ -#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ -#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ -#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ -#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ -#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */ -#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) -#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */ -#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) -#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */ -#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) -#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */ -#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) -#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */ -#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) -#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */ -#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) -#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */ -#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) -#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */ -#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) -#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */ -#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) -#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */ -#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) -#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */ -#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) -#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */ -#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) -#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */ -#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) -#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */ -#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) -#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */ -#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) -#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */ -#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) -#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */ -#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) -#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */ -#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) -#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */ -#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) -#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */ -#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) -#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */ -#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) -#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */ -#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) -#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */ -#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) -#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */ -#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) -#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */ -#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) -#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */ -#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) -#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */ -#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) -#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */ -#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) -#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */ -#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) -#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */ -#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) -#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */ -#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) -#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */ -#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) -#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */ -#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) -#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */ -#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) -#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */ -#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) -#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */ -#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) -#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */ -#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) -#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */ -#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) -#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */ -#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) -#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */ -#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) -#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */ -#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) -#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */ -#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) -#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */ -#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) -#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */ -#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) -#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */ -#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) -#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */ -#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) -#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */ -#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) -#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */ -#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) -#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */ -#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) -#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */ -#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) -#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */ -#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) -#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */ -#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) -#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */ -#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) -#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */ -#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) -#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */ -#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) -#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */ -#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) -#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */ -#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) -#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */ -#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) -#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */ -#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) -#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */ -#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) -#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */ -#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) -#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */ -#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) -#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */ -#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) -#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */ -#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) -#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */ -#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) -#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */ -#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) -#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */ -#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) -#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */ -#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) -#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */ -#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) -#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */ -#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) -#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */ -#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) -#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */ -#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) -#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */ -#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) -#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */ -#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) -#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */ -#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) -#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */ -#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) -#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */ -#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) -#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */ -#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) -#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */ -#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) -#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */ -#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) -#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */ -#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) -#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */ -#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) -#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */ -#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) -#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */ -#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) -#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */ -#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) -#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */ -#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) -#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */ -#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) -#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */ -#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) -#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */ -#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) -#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */ -#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) -#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */ -#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) -#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */ -#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) -#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */ -#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) -#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */ -#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) -#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */ -#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) -#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */ -#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) -#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */ -#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) -#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */ -#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) -#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */ -#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) -#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */ -#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) -#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */ -#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) -#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */ -#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) -#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */ -#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) -#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */ -#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) -#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */ -#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR) -#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val) -#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */ -#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR) -#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val) -#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */ -#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) -#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */ -#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) -#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */ -#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) -#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */ -#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) -#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */ -#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) -#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */ -#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR) -#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val) -#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */ -#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR) -#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val) -#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */ -#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) -#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */ -#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) -#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */ -#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) -#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */ -#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) -#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) -#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */ -#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR) -#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val) -#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */ -#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR) -#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val) -#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */ -#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) -#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */ -#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) -#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */ -#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) -#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */ -#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) -#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */ -#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) -#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */ -#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR) -#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val) -#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */ -#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR) -#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val) -#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */ -#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) -#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */ -#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) -#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */ -#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) -#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */ -#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) -#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) -#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */ -#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR) -#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val) -#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */ -#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR) -#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val) -#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */ -#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) -#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */ -#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) -#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */ -#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) -#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */ -#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) -#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */ -#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) -#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */ -#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR) -#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val) -#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */ -#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR) -#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val) -#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */ -#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) -#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */ -#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) -#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */ -#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) -#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */ -#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) -#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) -#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */ -#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR) -#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val) -#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */ -#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR) -#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val) -#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */ -#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) -#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */ -#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) -#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */ -#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) -#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */ -#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) -#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */ -#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) -#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */ -#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR) -#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val) -#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */ -#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR) -#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val) -#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */ -#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) -#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */ -#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) -#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */ -#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) -#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */ -#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) -#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */ -#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */ -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */ -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */ -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */ -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */ -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */ -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */ -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */ -#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */ -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */ -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */ -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */ -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */ -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */ -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */ -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */ -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */ -#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */ -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */ -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */ -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */ -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */ -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */ -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */ -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */ -#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */ -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */ -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */ -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */ -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */ -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */ -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */ -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */ -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) -#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */ -#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) -#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */ -#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) -#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */ -#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) -#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */ -#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) -#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */ -#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) -#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */ -#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) -#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) -#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */ -#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) -#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) -#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) -#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */ -#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) -#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) -#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) -#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */ -#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) -#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */ -#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) -#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */ -#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) -#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */ -#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) -#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */ -#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) -#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */ -#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) -#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) -#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */ -#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) -#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) -#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) -#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */ -#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) -#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */ -#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) -#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) -#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */ -#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) -#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */ -#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) -#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */ -#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) -#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */ -#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) -#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */ -#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) -#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */ -#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) -#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) -#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */ -#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) -#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) -#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) -#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */ -#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) -#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) -#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) -#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */ -#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) -#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */ -#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) -#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */ -#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) -#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */ -#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) -#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */ -#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) -#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */ -#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) -#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) -#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */ -#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) -#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) -#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) -#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */ -#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) -#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */ -#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) -#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */ -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */ -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */ -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */ -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */ -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */ -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */ -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */ -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */ -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */ -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */ -#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL) -#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val) -#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */ -#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) -#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */ -#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) -#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */ -#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL) -#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val) -#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */ -#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) -#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */ -#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) -#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */ -#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) -#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */ -#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) -#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */ -#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) -#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */ -#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD) -#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val) -#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */ -#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) -#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */ -#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) -#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) -#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */ -#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) -#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */ -#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) -#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */ -#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) -#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */ -#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) -#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */ -#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) -#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */ -#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) -#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */ -#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) -#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */ -#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) -#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */ -#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) -#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */ -#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) -#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */ -#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) -#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */ -#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) -#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */ -#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) -#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */ -#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) -#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */ -#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) -#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */ -#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) -#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */ -#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) -#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */ -#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) -#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */ -#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) -#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */ -#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) -#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */ -#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) -#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */ -#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) -#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */ -#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) -#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */ -#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) -#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */ -#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) -#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) -#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) -#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) -#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */ -#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) -#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) -#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */ -#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) -#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) -#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) -#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) -#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) -#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) -#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) -#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) -#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) -#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) -#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */ -#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) -#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) -#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) -#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) -#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) -#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) -#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) -#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) -#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) -#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) -#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */ -#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) -#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) -#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */ -#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) -#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) -#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) -#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) -#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) -#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) -#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) -#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) -#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */ -#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) -#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) -#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */ -#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) -#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) -#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */ -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */ -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */ -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */ -#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) -#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */ -#define bfin_read_PORTA() bfin_read16(PORTA) -#define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) -#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) -#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) -#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) -#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) -#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) -#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */ -#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) -#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */ -#define bfin_read_PORTB() bfin_read16(PORTB) -#define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) -#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) -#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) -#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) -#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) -#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) -#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */ -#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) -#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */ -#define bfin_read_PORTC() bfin_read16(PORTC) -#define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) -#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) -#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) -#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) -#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) -#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) -#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */ -#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) -#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */ -#define bfin_read_PORTD() bfin_read16(PORTD) -#define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) -#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) -#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) -#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) -#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) -#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) -#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */ -#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) -#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */ -#define bfin_read_PORTE() bfin_read16(PORTE) -#define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) -#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) -#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) -#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) -#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) -#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) -#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */ -#define bfin_read_PORTF() bfin_read16(PORTF) -#define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) -#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) -#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) -#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) -#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) -#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */ -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */ -#define bfin_read_PORTG() bfin_read16(PORTG) -#define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) -#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) -#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) -#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) -#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) -#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */ -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */ -#define bfin_read_PORTH() bfin_read16(PORTH) -#define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) -#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) -#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) -#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) -#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) -#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) -#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */ -#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) -#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */ -#define bfin_read_PORTI() bfin_read16(PORTI) -#define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) -#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) -#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) -#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) -#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) -#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) -#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) -#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */ -#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) -#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */ -#define bfin_read_PORTJ() bfin_read16(PORTJ) -#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) -#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) -#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) -#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) -#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) -#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) -#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) -#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */ -#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) -#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */ -#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) -#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */ -#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ) -#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val) -#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */ -#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) -#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) -#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) -#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */ -#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) -#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */ -#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) -#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */ -#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) -#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */ -#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) -#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) -#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */ -#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) -#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */ -#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) -#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */ -#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ) -#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val) -#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */ -#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) -#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) -#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) -#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */ -#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) -#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */ -#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) -#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */ -#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) -#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */ -#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) -#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) -#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */ -#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) -#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */ -#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) -#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */ -#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ) -#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val) -#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */ -#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) -#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) -#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) -#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */ -#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) -#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */ -#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) -#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */ -#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) -#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */ -#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) -#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) -#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */ -#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) -#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */ -#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) -#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */ -#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ) -#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val) -#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */ -#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) -#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) -#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) -#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */ -#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) -#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */ -#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) -#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */ -#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) -#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */ -#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) -#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */ -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */ -#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) -#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */ -#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) -#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */ -#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) -#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */ -#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) -#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */ -#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) -#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */ -#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) -#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */ -#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) -#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */ -#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) -#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */ -#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) -#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */ -#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) -#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */ -#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) -#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */ -#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) -#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) -#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */ -#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) -#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */ -#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) -#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */ -#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) -#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) -#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */ -#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) -#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) -#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */ -#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) -#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) -#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */ -#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) -#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */ -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */ -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */ -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */ -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */ -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ -#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) -#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ -#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) -#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ -#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) -#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ -#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) -#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) -#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) -#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) -#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) -#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */ -#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) -#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) -#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */ -#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) -#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) -#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */ -#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) -#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) -#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */ -#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) -#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) -#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */ -#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) -#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) -#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */ -#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) -#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) -#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */ -#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) -#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) -#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */ -#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) -#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) -#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */ -#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) -#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) -#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */ -#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) -#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) -#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */ -#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) -#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) -#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */ -#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) -#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) -#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */ -#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) -#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) -#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */ -#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) -#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) -#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */ -#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) -#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) -#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */ -#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) -#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) -#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */ -#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) -#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) -#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */ -#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) -#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */ -#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) -#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) -#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */ -#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) -#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */ -#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) -#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) -#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */ -#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) -#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) -#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */ -#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) -#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) -#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */ -#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) -#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) -#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */ -#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) -#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) -#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */ -#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) -#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) -#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */ -#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) -#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) -#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */ -#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) -#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) -#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */ -#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) -#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) -#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */ -#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) -#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) -#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */ -#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) -#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) -#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */ -#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) -#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) -#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */ -#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) -#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) -#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */ -#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) -#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) -#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */ -#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) -#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) -#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */ -#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) -#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) -#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */ -#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) -#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) -#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */ -#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) -#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) -#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */ -#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) -#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) -#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */ -#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) -#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) -#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */ -#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) -#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) -#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */ -#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) -#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) -#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */ -#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) -#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) -#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */ -#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) -#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) -#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */ -#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) -#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) -#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */ -#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) -#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) -#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */ -#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) -#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) -#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */ -#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) -#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) -#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */ -#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) -#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) -#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */ -#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) -#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) -#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */ -#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) -#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) -#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */ -#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) -#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) -#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */ -#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) -#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) -#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */ -#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) -#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) -#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */ -#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) -#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) -#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */ -#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) -#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) -#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */ -#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) -#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) -#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */ -#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) -#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) -#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) -#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) -#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) -#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) -#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) -#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) -#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) -#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ -#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) -#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ -#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) -#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ -#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) -#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ -#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) -#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ -#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) -#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ -#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) -#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ -#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) -#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ -#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) -#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ -#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) -#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ -#define bfin_read_NFC_RST() bfin_read16(NFC_RST) -#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ -#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) -#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ -#define bfin_read_NFC_READ() bfin_read16(NFC_READ) -#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ -#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) -#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ -#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) -#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ -#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) -#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ -#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) -#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */ -#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) -#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) -#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */ -#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) -#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) -#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */ -#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) -#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) -#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */ -#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) -#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) -#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */ -#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) -#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) -#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */ -#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) -#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) -#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */ -#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) -#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) -#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */ -#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) -#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) -#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */ -#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) -#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) -#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) -#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) -#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) -#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) -#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) -#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) -#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) -#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) -#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */ -#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) -#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) -#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */ -#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) -#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */ -#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) -#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */ -#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) -#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */ -#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) -#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */ -#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) -#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */ -#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) -#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */ -#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) -#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */ -#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) -#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */ -#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) -#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) -#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) -#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) -#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) -#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */ -#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) -#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) -#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */ -#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) -#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */ -#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) -#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */ -#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) -#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */ -#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) -#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */ -#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) -#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */ -#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) -#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */ -#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) -#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */ -#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) -#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */ -#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) -#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) -#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) -#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) -#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) -#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */ -#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) -#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) -#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */ -#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) -#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */ -#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) -#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */ -#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) -#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */ -#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) -#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */ -#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) -#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */ -#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) -#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) -#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */ -#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) -#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */ -#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) -#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */ -#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) -#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */ -#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) -#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */ -#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) -#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */ -#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) -#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) -#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define pSPI2_CTL ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */ -#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) -#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) -#define pSPI2_FLG ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */ -#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) -#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) -#define pSPI2_STAT ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */ -#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) -#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) -#define pSPI2_TDBR ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */ -#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) -#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) -#define pSPI2_RDBR ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */ -#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) -#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) -#define pSPI2_BAUD ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */ -#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) -#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) -#define pSPI2_SHADOW ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) -#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) -#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */ -#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */ -#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL) -#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val) -#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */ -#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */ -#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */ -#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) -#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */ -#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */ -#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */ -#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */ -#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) -#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */ -#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */ -#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL) -#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val) -#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */ -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */ -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */ -#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) -#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) -#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */ -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */ -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */ -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */ -#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) -#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) -#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */ -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */ -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */ -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */ -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */ -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */ -#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) -#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */ -#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) -#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) -#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) -#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ -#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) -#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */ -#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) -#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) -#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) -#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */ -#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) -#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */ -#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) -#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) -#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) -#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */ -#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) -#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) -#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) -#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) -#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) -#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) -#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) -#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) -#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) -#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */ -#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) -#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */ -#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) -#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) -#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) -#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ -#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) -#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */ -#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) -#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) -#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) -#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */ -#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) -#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */ -#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) -#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) -#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) -#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */ -#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) -#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) -#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) -#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) -#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) -#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) -#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) -#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) -#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) -#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */ -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) -#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) -#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */ -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */ -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) -#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) -#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */ -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART2_DLL ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) -#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) -#define pUART2_DLH ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) -#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) -#define pUART2_GCTL ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */ -#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) -#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) -#define pUART2_LCR ((uint16_t volatile *)UART2_LCR) /* Line Control Register */ -#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) -#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) -#define pUART2_MCR ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */ -#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) -#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) -#define pUART2_LSR ((uint16_t volatile *)UART2_LSR) /* Line Status Register */ -#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) -#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) -#define pUART2_MSR ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */ -#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) -#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) -#define pUART2_SCR ((uint16_t volatile *)UART2_SCR) /* Scratch Register */ -#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) -#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) -#define pUART2_IER_SET ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) -#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) -#define pUART2_IER_CLEAR ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) -#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) -#define pUART2_THR ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */ -#define bfin_read_UART2_THR() bfin_read16(UART2_THR) -#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val) -#define pUART2_RBR ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */ -#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) -#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) -#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) -#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) -#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */ -#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) -#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */ -#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) -#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */ -#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) -#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */ -#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) -#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */ -#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) -#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */ -#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) -#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) -#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) -#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */ -#define bfin_read_UART3_THR() bfin_read16(UART3_THR) -#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */ -#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) -#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_BF547_extended__ */ diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_def.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_def.h deleted file mode 100644 index 0e48279..0000000 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_def.h +++ /dev/null @@ -1,1213 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_BF547_extended__ -#define __BFIN_DEF_ADSP_EDN_BF547_extended__ - -#define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */ -#define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */ -#define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */ -#define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */ -#define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */ -#define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */ -#define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */ -#define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */ -#define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */ -#define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */ -#define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */ -#define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */ -#define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */ -#define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */ -#define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */ -#define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */ -#define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */ -#define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */ -#define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ -#define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */ -#define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ -#define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */ -#define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ -#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */ -#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */ -#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */ -#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */ -#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */ -#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */ -#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */ -#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */ -#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */ -#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */ -#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */ -#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */ -#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */ -#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */ -#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */ -#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */ -#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */ -#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */ -#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */ -#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */ -#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */ -#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */ -#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */ -#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */ -#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */ -#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */ -#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */ -#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */ -#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */ -#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */ -#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */ -#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */ -#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */ -#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */ -#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */ -#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */ -#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */ -#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */ -#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */ -#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */ -#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */ -#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */ -#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */ -#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */ -#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */ -#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */ -#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */ -#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */ -#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */ -#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */ -#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */ -#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */ -#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */ -#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */ -#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */ -#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */ -#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */ -#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */ -#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */ -#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */ -#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */ -#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */ -#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */ -#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */ -#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */ -#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */ -#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */ -#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */ -#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */ -#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */ -#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */ -#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */ -#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */ -#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */ -#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */ -#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */ -#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */ -#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */ -#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */ -#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */ -#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */ -#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */ -#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */ -#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */ -#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */ -#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */ -#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */ -#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */ -#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */ -#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */ -#define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */ -#define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */ -#define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */ -#define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */ -#define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */ -#define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */ -#define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */ -#define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */ -#define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */ -#define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */ -#define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */ -#define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */ -#define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */ -#define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */ -#define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */ -#define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */ -#define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */ -#define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */ -#define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */ -#define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */ -#define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */ -#define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */ -#define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */ -#define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */ -#define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */ -#define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */ -#define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */ -#define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */ -#define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */ -#define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */ -#define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */ -#define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */ -#define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */ -#define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */ -#define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */ -#define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */ -#define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */ -#define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */ -#define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */ -#define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */ -#define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */ -#define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */ -#define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */ -#define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */ -#define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */ -#define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */ -#define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */ -#define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */ -#define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */ -#define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */ -#define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */ -#define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */ -#define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */ -#define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */ -#define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */ -#define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */ -#define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */ -#define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */ -#define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */ -#define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */ -#define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */ -#define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */ -#define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */ -#define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */ -#define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */ -#define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */ -#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */ -#define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */ -#define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */ -#define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */ -#define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */ -#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */ -#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */ -#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */ -#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */ -#define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */ -#define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */ -#define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */ -#define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */ -#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */ -#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */ -#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */ -#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */ -#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */ -#define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */ -#define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */ -#define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */ -#define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */ -#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */ -#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */ -#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */ -#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */ -#define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */ -#define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */ -#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */ -#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */ -#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */ -#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */ -#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */ -#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */ -#define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */ -#define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */ -#define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */ -#define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */ -#define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */ -#define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */ -#define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */ -#define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */ -#define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */ -#define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */ -#define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */ -#define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */ -#define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */ -#define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ -#define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */ -#define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */ -#define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */ -#define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */ -#define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */ -#define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */ -#define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */ -#define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */ -#define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */ -#define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */ -#define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */ -#define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */ -#define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */ -#define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */ -#define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */ -#define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */ -#define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */ -#define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */ -#define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */ -#define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */ -#define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */ -#define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */ -#define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */ -#define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */ -#define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */ -#define PIXC_CTL 0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define PIXC_PPL 0xFFC04404 /* Holds the number of pixels per line of the display */ -#define PIXC_LPF 0xFFC04408 /* Holds the number of lines per frame of the display */ -#define PIXC_AHSTART 0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */ -#define PIXC_AHEND 0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */ -#define PIXC_AVSTART 0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */ -#define PIXC_AVEND 0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */ -#define PIXC_ATRANSP 0xFFC0441C /* Contains the transparency ratio (set A) */ -#define PIXC_BHSTART 0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */ -#define PIXC_BHEND 0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */ -#define PIXC_BVSTART 0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */ -#define PIXC_BVEND 0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */ -#define PIXC_BTRANSP 0xFFC04430 /* Contains the transparency ratio (set B) */ -#define PIXC_INTRSTAT 0xFFC0443C /* Overlay interrupt configuration/status */ -#define PIXC_RYCON 0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define PIXC_GUCON 0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define PIXC_BVCON 0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define PIXC_CCBIAS 0xFFC0444C /* Bias values for the color space conversion matrix */ -#define PIXC_TC 0xFFC04450 /* Holds the transparent color value */ -#define HOST_CONTROL 0xFFC03A00 /* HOSTDP Control Register */ -#define HOST_STATUS 0xFFC03A04 /* HOSTDP Status Register */ -#define HOST_TIMEOUT 0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */ -#define PORTA_FER 0xFFC014C0 /* Function Enable Register */ -#define PORTA 0xFFC014C4 /* GPIO Data Register */ -#define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */ -#define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */ -#define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */ -#define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */ -#define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */ -#define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */ -#define PORTB_FER 0xFFC014E0 /* Function Enable Register */ -#define PORTB 0xFFC014E4 /* GPIO Data Register */ -#define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */ -#define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */ -#define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */ -#define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */ -#define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */ -#define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */ -#define PORTC_FER 0xFFC01500 /* Function Enable Register */ -#define PORTC 0xFFC01504 /* GPIO Data Register */ -#define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */ -#define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */ -#define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */ -#define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */ -#define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */ -#define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */ -#define PORTD_FER 0xFFC01520 /* Function Enable Register */ -#define PORTD 0xFFC01524 /* GPIO Data Register */ -#define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */ -#define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */ -#define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */ -#define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */ -#define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */ -#define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */ -#define PORTE_FER 0xFFC01540 /* Function Enable Register */ -#define PORTE 0xFFC01544 /* GPIO Data Register */ -#define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */ -#define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */ -#define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */ -#define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */ -#define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */ -#define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */ -#define PORTF_FER 0xFFC01560 /* Function Enable Register */ -#define PORTF 0xFFC01564 /* GPIO Data Register */ -#define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */ -#define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */ -#define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */ -#define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */ -#define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */ -#define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */ -#define PORTG_FER 0xFFC01580 /* Function Enable Register */ -#define PORTG 0xFFC01584 /* GPIO Data Register */ -#define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */ -#define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */ -#define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */ -#define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */ -#define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */ -#define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */ -#define PORTH_FER 0xFFC015A0 /* Function Enable Register */ -#define PORTH 0xFFC015A4 /* GPIO Data Register */ -#define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */ -#define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */ -#define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */ -#define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */ -#define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */ -#define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */ -#define PORTI_FER 0xFFC015C0 /* Function Enable Register */ -#define PORTI 0xFFC015C4 /* GPIO Data Register */ -#define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */ -#define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */ -#define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */ -#define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */ -#define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */ -#define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */ -#define PORTJ_FER 0xFFC015E0 /* Function Enable Register */ -#define PORTJ 0xFFC015E4 /* GPIO Data Register */ -#define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */ -#define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */ -#define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */ -#define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */ -#define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */ -#define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */ -#define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */ -#define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */ -#define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */ -#define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */ -#define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */ -#define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */ -#define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */ -#define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */ -#define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */ -#define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */ -#define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */ -#define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */ -#define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */ -#define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */ -#define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */ -#define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */ -#define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */ -#define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */ -#define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */ -#define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */ -#define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */ -#define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */ -#define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */ -#define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */ -#define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */ -#define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */ -#define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */ -#define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */ -#define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */ -#define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */ -#define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */ -#define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */ -#define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */ -#define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */ -#define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */ -#define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */ -#define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */ -#define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */ -#define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */ -#define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */ -#define TIMER8_CONFIG 0xFFC00600 /* Timer 8 Configuration Register */ -#define TIMER8_COUNTER 0xFFC00604 /* Timer 8 Counter Register */ -#define TIMER8_PERIOD 0xFFC00608 /* Timer 8 Period Register */ -#define TIMER8_WIDTH 0xFFC0060C /* Timer 8 Width Register */ -#define TIMER9_CONFIG 0xFFC00610 /* Timer 9 Configuration Register */ -#define TIMER9_COUNTER 0xFFC00614 /* Timer 9 Counter Register */ -#define TIMER9_PERIOD 0xFFC00618 /* Timer 9 Period Register */ -#define TIMER9_WIDTH 0xFFC0061C /* Timer 9 Width Register */ -#define TIMER10_CONFIG 0xFFC00620 /* Timer 10 Configuration Register */ -#define TIMER10_COUNTER 0xFFC00624 /* Timer 10 Counter Register */ -#define TIMER10_PERIOD 0xFFC00628 /* Timer 10 Period Register */ -#define TIMER10_WIDTH 0xFFC0062C /* Timer 10 Width Register */ -#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */ -#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */ -#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */ -#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */ -#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */ -#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define CNT_CONFIG 0xFFC04200 /* Configuration Register */ -#define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */ -#define CNT_STATUS 0xFFC04208 /* Status Register */ -#define CNT_COMMAND 0xFFC0420C /* Command Register */ -#define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */ -#define CNT_COUNTER 0xFFC04214 /* Counter Register */ -#define CNT_MAX 0xFFC04218 /* Maximal Count Register */ -#define CNT_MIN 0xFFC0421C /* Minimal Count Register */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ -#define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */ -#define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */ -#define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */ -#define SECURE_CONTROL 0xFFC04324 /* Secure Control */ -#define SECURE_STATUS 0xFFC04328 /* Secure Status */ -#define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divisor Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define KPAD_CTL 0xFFC04100 /* Controls keypad module enable and disable */ -#define KPAD_PRESCALE 0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */ -#define KPAD_MSEL 0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */ -#define KPAD_ROWCOL 0xFFC0410C /* Captures the row and column output values of the keys pressed */ -#define KPAD_STAT 0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */ -#define KPAD_SOFTEVAL 0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */ -#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ -#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ -#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ -#define SDH_COMMAND 0xFFC0390C /* SDH Command */ -#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ -#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ -#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ -#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ -#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ -#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ -#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ -#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ -#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ -#define SDH_STATUS 0xFFC03934 /* SDH Status */ -#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ -#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ -#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ -#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ -#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ -#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ -#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ -#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ -#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ -#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ -#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ -#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ -#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ -#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ -#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ -#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ -#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ -#define ATAPI_CONTROL 0xFFC03800 /* ATAPI Control Register */ -#define ATAPI_STATUS 0xFFC03804 /* ATAPI Status Register */ -#define ATAPI_DEV_ADDR 0xFFC03808 /* ATAPI Device Register Address */ -#define ATAPI_DEV_TXBUF 0xFFC0380C /* ATAPI Device Register Write Data */ -#define ATAPI_DEV_RXBUF 0xFFC03810 /* ATAPI Device Register Read Data */ -#define ATAPI_INT_MASK 0xFFC03814 /* ATAPI Interrupt Mask Register */ -#define ATAPI_INT_STATUS 0xFFC03818 /* ATAPI Interrupt Status Register */ -#define ATAPI_XFER_LEN 0xFFC0381C /* ATAPI Length of Transfer */ -#define ATAPI_LINE_STATUS 0xFFC03820 /* ATAPI Line Status */ -#define ATAPI_SM_STATE 0xFFC03824 /* ATAPI State Machine Status */ -#define ATAPI_TERMINATE 0xFFC03828 /* ATAPI Host Terminate */ -#define ATAPI_PIO_TFRCNT 0xFFC0382C /* ATAPI PIO mode transfer count */ -#define ATAPI_DMA_TFRCNT 0xFFC03830 /* ATAPI DMA mode transfer count */ -#define ATAPI_UMAIN_TFRCNT 0xFFC03834 /* ATAPI UDMAIN transfer count */ -#define ATAPI_UDMAOUT_TFRCNT 0xFFC03838 /* ATAPI UDMAOUT transfer count */ -#define ATAPI_REG_TIM_0 0xFFC03840 /* ATAPI Register Transfer Timing 0 */ -#define ATAPI_PIO_TIM_0 0xFFC03844 /* ATAPI PIO Timing 0 Register */ -#define ATAPI_PIO_TIM_1 0xFFC03848 /* ATAPI PIO Timing 1 Register */ -#define ATAPI_MULTI_TIM_0 0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */ -#define ATAPI_MULTI_TIM_1 0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */ -#define ATAPI_MULTI_TIM_2 0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_0 0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */ -#define ATAPI_ULTRA_TIM_1 0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */ -#define ATAPI_ULTRA_TIM_2 0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_3 0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */ -#define NFC_CTL 0xFFC03B00 /* NAND Control Register */ -#define NFC_STAT 0xFFC03B04 /* NAND Status Register */ -#define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */ -#define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */ -#define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */ -#define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */ -#define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */ -#define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */ -#define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */ -#define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */ -#define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */ -#define NFC_READ 0xFFC03B2C /* NAND Read Data Register */ -#define NFC_ADDR 0xFFC03B40 /* NAND Address Register */ -#define NFC_CMD 0xFFC03B44 /* NAND Command Register */ -#define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */ -#define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */ -#define EPPI0_STATUS 0xFFC01000 /* EPPI0 Status Register */ -#define EPPI0_HCOUNT 0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */ -#define EPPI0_HDELAY 0xFFC01008 /* EPPI0 Horizontal Delay Count Register */ -#define EPPI0_VCOUNT 0xFFC0100C /* EPPI0 Vertical Transfer Count Register */ -#define EPPI0_VDELAY 0xFFC01010 /* EPPI0 Vertical Delay Count Register */ -#define EPPI0_FRAME 0xFFC01014 /* EPPI0 Lines per Frame Register */ -#define EPPI0_LINE 0xFFC01018 /* EPPI0 Samples per Line Register */ -#define EPPI0_CLKDIV 0xFFC0101C /* EPPI0 Clock Divide Register */ -#define EPPI0_CONTROL 0xFFC01020 /* EPPI0 Control Register */ -#define EPPI0_FS1W_HBL 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define EPPI0_FS1P_AVPL 0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define EPPI0_FS2W_LVB 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define EPPI0_FS2P_LAVF 0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define EPPI0_CLIP 0xFFC01034 /* EPPI0 Clipping Register */ -#define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */ -#define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */ -#define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */ -#define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */ -#define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */ -#define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */ -#define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */ -#define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */ -#define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */ -#define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */ -#define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */ -#define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */ -#define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */ -#define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */ -#define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */ -#define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */ -#define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */ -#define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */ -#define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */ -#define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */ -#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ -#define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */ -#define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */ -#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ -#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ -#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */ -#define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */ -#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ -#define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */ -#define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */ -#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ -#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ -#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */ -#define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */ -#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ -#define SPI2_FLG 0xFFC02404 /* SPI2 Flag Register */ -#define SPI2_STAT 0xFFC02408 /* SPI2 Status Register */ -#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ -#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ -#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud Rate Register */ -#define SPI2_SHADOW 0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */ -#define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */ -#define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */ -#define TWI1_CLKDIV 0xFFC02200 /* Clock Divider Register */ -#define TWI1_CONTROL 0xFFC02204 /* TWI Control Register */ -#define TWI1_SLAVE_CTL 0xFFC02208 /* TWI Slave Mode Control Register */ -#define TWI1_SLAVE_STAT 0xFFC0220C /* TWI Slave Mode Status Register */ -#define TWI1_SLAVE_ADDR 0xFFC02210 /* TWI Slave Mode Address Register */ -#define TWI1_MASTER_CTL 0xFFC02214 /* TWI Master Mode Control Register */ -#define TWI1_MASTER_STAT 0xFFC02218 /* TWI Master Mode Status Register */ -#define TWI1_MASTER_ADDR 0xFFC0221C /* TWI Master Mode Address Register */ -#define TWI1_INT_STAT 0xFFC02220 /* TWI Interrupt Status Register */ -#define TWI1_INT_MASK 0xFFC02224 /* TWI Interrupt Mask Register */ -#define TWI1_FIFO_CTL 0xFFC02228 /* TWI FIFO Control Register */ -#define TWI1_FIFO_STAT 0xFFC0222C /* TWI FIFO Status Register */ -#define TWI1_XMT_DATA8 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI1_XMT_DATA16 0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI1_RCV_DATA8 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI1_RCV_DATA16 0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 Transmit Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Receive Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Receive Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 Receive Data Register */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */ -#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ -#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ -#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */ -#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */ -#define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */ -#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */ -#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */ -#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */ -#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */ -#define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */ -#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ -#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */ -#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */ -#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ -#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */ -#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */ -#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */ -#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */ -#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */ -#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */ -#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */ -#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */ -#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ -#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ -#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */ -#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */ -#define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */ -#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */ -#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */ -#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */ -#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */ -#define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */ -#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ -#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */ -#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */ -#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ -#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */ -#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */ -#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */ -#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */ -#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */ -#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */ -#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */ -#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */ -#define UART0_GCTL 0xFFC00408 /* Global Control Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* Scratch Register */ -#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */ -#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */ -#define UART0_THR 0xFFC00428 /* Transmit Hold Register */ -#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */ -#define UART1_GCTL 0xFFC02008 /* Global Control Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* Scratch Register */ -#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */ -#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */ -#define UART1_THR 0xFFC02028 /* Transmit Hold Register */ -#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */ -#define UART2_DLL 0xFFC02100 /* Divisor Latch Low Byte */ -#define UART2_DLH 0xFFC02104 /* Divisor Latch High Byte */ -#define UART2_GCTL 0xFFC02108 /* Global Control Register */ -#define UART2_LCR 0xFFC0210C /* Line Control Register */ -#define UART2_MCR 0xFFC02110 /* Modem Control Register */ -#define UART2_LSR 0xFFC02114 /* Line Status Register */ -#define UART2_MSR 0xFFC02118 /* Modem Status Register */ -#define UART2_SCR 0xFFC0211C /* Scratch Register */ -#define UART2_IER_SET 0xFFC02120 /* Interrupt Enable Register Set */ -#define UART2_IER_CLEAR 0xFFC02124 /* Interrupt Enable Register Clear */ -#define UART2_THR 0xFFC02128 /* Transmit Hold Register */ -#define UART2_RBR 0xFFC0212C /* Receive Buffer Register */ -#define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */ -#define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */ -#define UART3_GCTL 0xFFC03108 /* Global Control Register */ -#define UART3_LCR 0xFFC0310C /* Line Control Register */ -#define UART3_MCR 0xFFC03110 /* Modem Control Register */ -#define UART3_LSR 0xFFC03114 /* Line Status Register */ -#define UART3_MSR 0xFFC03118 /* Modem Status Register */ -#define UART3_SCR 0xFFC0311C /* Scratch Register */ -#define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */ -#define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */ -#define UART3_THR 0xFFC03128 /* Transmit Hold Register */ -#define UART3_RBR 0xFFC0312C /* Receive Buffer Register */ -#define USB_FADDR 0xFFC03C00 /* Function address register */ -#define USB_POWER 0xFFC03C04 /* Power management register */ -#define USB_INTRTX 0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03C10 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03C14 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03C18 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC03C1C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03C20 /* USB frame number */ -#define USB_INDEX 0xFFC03C24 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03C28 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03C30 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03C40 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03C48 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC03C4C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03C80 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03C88 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03C90 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03C98 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC03CA0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC03CA8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC03CB0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC03CB8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03D00 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03D04 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03D08 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03D48 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03D50 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03D54 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03D58 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC03DE0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC03DE4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03E04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03E0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03E44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03E4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03E84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03E8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03EC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ECC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03F04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03F0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03F44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03F4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03F84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03F8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03FC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03FCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC04000 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC04004 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC04024 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC04044 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC04064 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC04084 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC040A4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC040C4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC040E4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -#endif /* __BFIN_DEF_ADSP_EDN_BF547_extended__ */ diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h deleted file mode 100644 index caf2f6f..0000000 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h +++ /dev/null @@ -1,5787 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_BF548_extended__ -#define __BFIN_CDEF_ADSP_EDN_BF548_extended__ - -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */ -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */ -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */ -#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) -#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */ -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */ -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */ -#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) -#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */ -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */ -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */ -#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) -#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */ -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */ -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */ -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */ -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */ -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */ -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */ -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */ -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */ -#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) -#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */ -#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) -#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */ -#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) -#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */ -#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) -#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) -#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */ -#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) -#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) -#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */ -#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) -#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) -#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */ -#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) -#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) -#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */ -#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) -#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) -#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */ -#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) -#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ -#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ -#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ -#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ -#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ -#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ -#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ -#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ -#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ -#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ -#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ -#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ -#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ -#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ -#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ -#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ -#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ -#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ -#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ -#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ -#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ -#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ -#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ -#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ -#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */ -#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) -#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */ -#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) -#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */ -#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) -#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */ -#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) -#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */ -#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) -#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */ -#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) -#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */ -#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) -#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */ -#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) -#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */ -#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) -#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */ -#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) -#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */ -#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) -#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */ -#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) -#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */ -#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) -#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */ -#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) -#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */ -#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) -#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */ -#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) -#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */ -#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) -#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */ -#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) -#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */ -#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) -#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */ -#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) -#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */ -#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) -#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */ -#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) -#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */ -#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) -#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */ -#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) -#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */ -#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) -#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */ -#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) -#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */ -#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) -#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */ -#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) -#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */ -#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) -#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */ -#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) -#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */ -#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) -#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */ -#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) -#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */ -#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) -#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */ -#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) -#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */ -#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) -#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */ -#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) -#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */ -#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) -#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */ -#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) -#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */ -#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) -#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */ -#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) -#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */ -#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) -#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */ -#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) -#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */ -#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) -#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */ -#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) -#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */ -#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) -#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */ -#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) -#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */ -#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) -#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */ -#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) -#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */ -#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) -#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */ -#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) -#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */ -#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) -#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */ -#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) -#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */ -#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) -#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */ -#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) -#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */ -#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) -#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */ -#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) -#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */ -#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) -#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */ -#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) -#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */ -#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) -#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */ -#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) -#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */ -#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) -#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */ -#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) -#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */ -#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) -#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */ -#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) -#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */ -#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) -#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */ -#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) -#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */ -#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) -#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */ -#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) -#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */ -#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) -#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */ -#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) -#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */ -#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) -#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */ -#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) -#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */ -#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) -#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */ -#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) -#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */ -#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) -#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */ -#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) -#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */ -#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) -#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */ -#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) -#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */ -#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) -#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */ -#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) -#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */ -#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) -#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */ -#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) -#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */ -#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) -#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */ -#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) -#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */ -#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) -#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */ -#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) -#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */ -#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) -#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */ -#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) -#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */ -#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) -#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */ -#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) -#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */ -#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) -#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */ -#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) -#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */ -#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) -#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */ -#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) -#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */ -#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) -#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */ -#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) -#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */ -#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) -#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */ -#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) -#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */ -#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) -#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */ -#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) -#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */ -#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) -#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */ -#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) -#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */ -#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) -#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */ -#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) -#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */ -#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR) -#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val) -#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */ -#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR) -#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val) -#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */ -#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) -#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */ -#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) -#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */ -#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) -#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */ -#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) -#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */ -#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) -#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */ -#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR) -#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val) -#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */ -#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR) -#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val) -#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */ -#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) -#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */ -#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) -#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */ -#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) -#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */ -#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) -#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) -#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */ -#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR) -#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val) -#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */ -#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR) -#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val) -#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */ -#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) -#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */ -#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) -#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */ -#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) -#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */ -#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) -#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */ -#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) -#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */ -#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR) -#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val) -#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */ -#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR) -#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val) -#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */ -#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) -#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */ -#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) -#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */ -#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) -#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */ -#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) -#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) -#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */ -#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR) -#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val) -#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */ -#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR) -#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val) -#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */ -#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) -#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */ -#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) -#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */ -#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) -#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */ -#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) -#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */ -#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) -#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */ -#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR) -#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val) -#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */ -#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR) -#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val) -#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */ -#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) -#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */ -#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) -#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */ -#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) -#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */ -#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) -#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) -#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */ -#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR) -#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val) -#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */ -#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR) -#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val) -#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */ -#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) -#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */ -#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) -#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */ -#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) -#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */ -#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) -#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */ -#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) -#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */ -#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR) -#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val) -#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */ -#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR) -#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val) -#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */ -#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) -#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */ -#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) -#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */ -#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) -#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */ -#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) -#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */ -#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */ -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */ -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */ -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */ -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */ -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */ -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */ -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */ -#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */ -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */ -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */ -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */ -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */ -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */ -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */ -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */ -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */ -#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */ -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */ -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */ -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */ -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */ -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */ -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */ -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */ -#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */ -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */ -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */ -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */ -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */ -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */ -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */ -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */ -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) -#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */ -#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) -#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */ -#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) -#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */ -#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) -#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */ -#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) -#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */ -#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) -#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */ -#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) -#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) -#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */ -#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) -#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) -#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) -#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */ -#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) -#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) -#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) -#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */ -#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) -#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */ -#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) -#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */ -#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) -#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */ -#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) -#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */ -#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) -#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */ -#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) -#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) -#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */ -#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) -#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) -#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) -#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */ -#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) -#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */ -#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) -#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) -#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */ -#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) -#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */ -#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) -#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */ -#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) -#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */ -#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) -#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */ -#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) -#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */ -#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) -#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) -#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */ -#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) -#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) -#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) -#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */ -#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) -#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) -#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) -#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */ -#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) -#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */ -#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) -#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */ -#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) -#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */ -#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) -#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */ -#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) -#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */ -#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) -#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) -#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */ -#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) -#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) -#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) -#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */ -#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) -#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */ -#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) -#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */ -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */ -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */ -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */ -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */ -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */ -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */ -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */ -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */ -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */ -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */ -#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL) -#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val) -#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */ -#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) -#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */ -#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) -#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */ -#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL) -#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val) -#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */ -#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) -#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */ -#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) -#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */ -#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) -#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */ -#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) -#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */ -#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) -#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */ -#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD) -#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val) -#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */ -#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) -#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */ -#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) -#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) -#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */ -#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) -#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */ -#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) -#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */ -#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) -#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */ -#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) -#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */ -#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) -#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */ -#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) -#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */ -#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) -#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */ -#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) -#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */ -#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) -#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */ -#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) -#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */ -#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) -#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */ -#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) -#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */ -#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) -#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */ -#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) -#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */ -#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) -#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */ -#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) -#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */ -#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) -#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */ -#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) -#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */ -#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) -#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */ -#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) -#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */ -#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) -#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */ -#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) -#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */ -#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) -#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */ -#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) -#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */ -#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) -#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) -#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) -#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) -#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */ -#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) -#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) -#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */ -#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) -#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) -#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) -#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) -#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) -#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) -#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) -#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) -#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) -#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) -#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */ -#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) -#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) -#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) -#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) -#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) -#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) -#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) -#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) -#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) -#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) -#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */ -#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) -#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) -#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */ -#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) -#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) -#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) -#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) -#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) -#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) -#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) -#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) -#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */ -#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) -#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) -#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */ -#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) -#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) -#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */ -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */ -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */ -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */ -#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) -#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */ -#define bfin_read_PORTA() bfin_read16(PORTA) -#define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) -#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) -#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) -#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) -#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) -#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) -#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */ -#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) -#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */ -#define bfin_read_PORTB() bfin_read16(PORTB) -#define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) -#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) -#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) -#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) -#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) -#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) -#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */ -#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) -#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */ -#define bfin_read_PORTC() bfin_read16(PORTC) -#define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) -#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) -#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) -#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) -#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) -#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) -#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */ -#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) -#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */ -#define bfin_read_PORTD() bfin_read16(PORTD) -#define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) -#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) -#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) -#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) -#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) -#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) -#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */ -#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) -#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */ -#define bfin_read_PORTE() bfin_read16(PORTE) -#define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) -#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) -#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) -#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) -#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) -#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) -#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */ -#define bfin_read_PORTF() bfin_read16(PORTF) -#define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) -#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) -#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) -#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) -#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) -#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */ -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */ -#define bfin_read_PORTG() bfin_read16(PORTG) -#define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) -#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) -#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) -#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) -#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) -#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */ -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */ -#define bfin_read_PORTH() bfin_read16(PORTH) -#define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) -#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) -#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) -#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) -#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) -#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) -#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */ -#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) -#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */ -#define bfin_read_PORTI() bfin_read16(PORTI) -#define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) -#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) -#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) -#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) -#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) -#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) -#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) -#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */ -#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) -#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */ -#define bfin_read_PORTJ() bfin_read16(PORTJ) -#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) -#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) -#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) -#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) -#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) -#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) -#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) -#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */ -#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) -#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */ -#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) -#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */ -#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ) -#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val) -#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */ -#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) -#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) -#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) -#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */ -#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) -#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */ -#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) -#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */ -#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) -#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */ -#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) -#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) -#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */ -#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) -#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */ -#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) -#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */ -#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ) -#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val) -#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */ -#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) -#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) -#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) -#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */ -#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) -#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */ -#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) -#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */ -#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) -#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */ -#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) -#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) -#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */ -#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) -#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */ -#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) -#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */ -#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ) -#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val) -#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */ -#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) -#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) -#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) -#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */ -#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) -#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */ -#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) -#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */ -#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) -#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */ -#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) -#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) -#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */ -#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) -#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */ -#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) -#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */ -#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ) -#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val) -#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */ -#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) -#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) -#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) -#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */ -#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) -#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */ -#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) -#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */ -#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) -#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */ -#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) -#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */ -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */ -#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) -#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */ -#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) -#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */ -#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) -#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */ -#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) -#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */ -#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) -#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */ -#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) -#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */ -#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) -#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */ -#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) -#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */ -#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) -#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */ -#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) -#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */ -#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) -#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */ -#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) -#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) -#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */ -#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) -#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */ -#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) -#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */ -#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) -#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) -#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */ -#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) -#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) -#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */ -#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) -#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) -#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */ -#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) -#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */ -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */ -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */ -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */ -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */ -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ -#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) -#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ -#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) -#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ -#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) -#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ -#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) -#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) -#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) -#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) -#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) -#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */ -#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) -#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) -#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */ -#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) -#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) -#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */ -#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) -#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) -#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */ -#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) -#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) -#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */ -#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) -#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) -#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */ -#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) -#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) -#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */ -#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) -#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) -#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */ -#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) -#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) -#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */ -#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) -#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) -#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */ -#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) -#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) -#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */ -#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) -#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) -#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */ -#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) -#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) -#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */ -#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) -#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) -#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */ -#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) -#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) -#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */ -#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) -#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) -#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */ -#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) -#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) -#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */ -#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) -#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) -#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */ -#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) -#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */ -#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) -#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) -#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */ -#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) -#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */ -#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) -#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) -#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */ -#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) -#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) -#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */ -#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) -#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) -#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */ -#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) -#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) -#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */ -#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) -#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) -#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */ -#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) -#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) -#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */ -#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) -#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) -#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */ -#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) -#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) -#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */ -#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) -#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) -#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */ -#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) -#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) -#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */ -#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) -#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) -#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */ -#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) -#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) -#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */ -#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) -#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) -#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */ -#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) -#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) -#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */ -#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) -#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) -#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */ -#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) -#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) -#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */ -#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) -#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) -#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */ -#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) -#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) -#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */ -#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) -#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) -#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */ -#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) -#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) -#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */ -#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) -#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) -#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */ -#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) -#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) -#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */ -#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) -#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) -#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */ -#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) -#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) -#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */ -#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) -#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) -#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */ -#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) -#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) -#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */ -#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) -#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) -#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */ -#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) -#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) -#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */ -#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) -#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) -#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */ -#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) -#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) -#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */ -#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) -#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) -#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */ -#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) -#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) -#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */ -#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) -#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) -#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */ -#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) -#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) -#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */ -#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) -#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) -#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */ -#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) -#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) -#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */ -#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) -#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) -#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */ -#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) -#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) -#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) -#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) -#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) -#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) -#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) -#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) -#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) -#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ -#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) -#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ -#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) -#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ -#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) -#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ -#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) -#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ -#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) -#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ -#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) -#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ -#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) -#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ -#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) -#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ -#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) -#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ -#define bfin_read_NFC_RST() bfin_read16(NFC_RST) -#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ -#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) -#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ -#define bfin_read_NFC_READ() bfin_read16(NFC_READ) -#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ -#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) -#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ -#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) -#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ -#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) -#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ -#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) -#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */ -#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) -#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) -#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */ -#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) -#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) -#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */ -#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) -#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) -#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */ -#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) -#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) -#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */ -#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) -#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) -#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */ -#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) -#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) -#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */ -#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) -#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) -#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */ -#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) -#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) -#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */ -#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) -#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) -#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) -#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) -#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) -#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) -#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) -#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) -#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) -#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) -#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */ -#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) -#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) -#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */ -#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) -#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */ -#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) -#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */ -#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) -#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */ -#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) -#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */ -#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) -#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */ -#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) -#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */ -#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) -#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */ -#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) -#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */ -#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) -#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) -#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) -#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) -#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) -#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */ -#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) -#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) -#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */ -#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) -#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */ -#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) -#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */ -#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) -#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */ -#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) -#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */ -#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) -#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */ -#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) -#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */ -#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) -#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */ -#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) -#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */ -#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) -#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) -#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) -#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) -#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) -#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */ -#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) -#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) -#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */ -#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) -#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) -#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */ -#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) -#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) -#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */ -#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) -#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) -#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */ -#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) -#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) -#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */ -#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) -#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) -#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */ -#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) -#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) -#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */ -#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) -#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) -#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */ -#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) -#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) -#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ -#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) -#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) -#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ -#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) -#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) -#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ -#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) -#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) -#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ -#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) -#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) -#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ -#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) -#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) -#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */ -#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) -#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) -#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */ -#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) -#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) -#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */ -#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) -#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) -#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */ -#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) -#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) -#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */ -#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) -#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) -#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */ -#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) -#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) -#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */ -#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) -#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) -#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */ -#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) -#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) -#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ -#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) -#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) -#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ -#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) -#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) -#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ -#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) -#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) -#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ -#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) -#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) -#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ -#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) -#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) -#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */ -#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) -#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) -#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */ -#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) -#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) -#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */ -#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) -#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) -#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */ -#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) -#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) -#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */ -#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) -#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) -#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */ -#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) -#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) -#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */ -#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) -#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) -#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */ -#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) -#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) -#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */ -#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) -#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) -#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */ -#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) -#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) -#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */ -#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) -#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) -#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */ -#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) -#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) -#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */ -#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) -#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) -#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */ -#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) -#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) -#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */ -#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) -#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) -#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */ -#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) -#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) -#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) -#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) -#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) -#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) -#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) -#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) -#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) -#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) -#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) -#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) -#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) -#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) -#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) -#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) -#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) -#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) -#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) -#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) -#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) -#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) -#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) -#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) -#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) -#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) -#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) -#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) -#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) -#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) -#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) -#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) -#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) -#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) -#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) -#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) -#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) -#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) -#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) -#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) -#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) -#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) -#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) -#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) -#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) -#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) -#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) -#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) -#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) -#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) -#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) -#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) -#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) -#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) -#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) -#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) -#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) -#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) -#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) -#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) -#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) -#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) -#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) -#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) -#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) -#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) -#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) -#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) -#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) -#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) -#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) -#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) -#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) -#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) -#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) -#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) -#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) -#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) -#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) -#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) -#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) -#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) -#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) -#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) -#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) -#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) -#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) -#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) -#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) -#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) -#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) -#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) -#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) -#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) -#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) -#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) -#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) -#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) -#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) -#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) -#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) -#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) -#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) -#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) -#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) -#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) -#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) -#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) -#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) -#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) -#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) -#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) -#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) -#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) -#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) -#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) -#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) -#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) -#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) -#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) -#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) -#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) -#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) -#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) -#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) -#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) -#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) -#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) -#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) -#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) -#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */ -#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) -#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) -#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */ -#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) -#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) -#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */ -#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) -#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) -#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */ -#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) -#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) -#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */ -#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) -#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) -#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */ -#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) -#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) -#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */ -#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) -#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) -#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */ -#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) -#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) -#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */ -#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) -#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) -#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */ -#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) -#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) -#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */ -#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) -#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) -#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */ -#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) -#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) -#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */ -#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) -#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) -#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */ -#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) -#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) -#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */ -#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) -#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) -#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */ -#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) -#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) -#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */ -#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) -#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) -#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */ -#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) -#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) -#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */ -#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) -#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) -#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */ -#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) -#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) -#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */ -#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) -#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) -#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */ -#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) -#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) -#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */ -#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) -#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) -#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */ -#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) -#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) -#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */ -#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) -#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) -#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */ -#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) -#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) -#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */ -#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) -#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) -#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */ -#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) -#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) -#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */ -#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) -#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) -#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */ -#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) -#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) -#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */ -#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) -#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) -#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */ -#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) -#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) -#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */ -#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) -#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) -#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */ -#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) -#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) -#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */ -#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) -#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) -#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */ -#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) -#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) -#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */ -#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) -#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) -#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */ -#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) -#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) -#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */ -#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) -#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) -#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */ -#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) -#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) -#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */ -#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) -#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) -#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */ -#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) -#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) -#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */ -#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) -#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) -#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */ -#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) -#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) -#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */ -#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) -#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) -#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */ -#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) -#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) -#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */ -#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) -#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) -#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */ -#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) -#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) -#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */ -#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) -#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) -#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */ -#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) -#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) -#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */ -#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) -#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) -#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */ -#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) -#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) -#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */ -#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) -#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) -#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */ -#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) -#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) -#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */ -#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) -#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) -#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */ -#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) -#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) -#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */ -#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) -#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) -#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */ -#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) -#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) -#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */ -#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) -#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) -#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */ -#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) -#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) -#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */ -#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) -#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) -#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */ -#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) -#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) -#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */ -#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) -#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) -#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */ -#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) -#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) -#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */ -#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) -#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) -#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */ -#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) -#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) -#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */ -#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) -#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) -#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */ -#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) -#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) -#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */ -#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) -#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) -#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */ -#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) -#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) -#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */ -#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) -#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) -#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */ -#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) -#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) -#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */ -#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) -#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) -#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */ -#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) -#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) -#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */ -#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) -#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) -#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */ -#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) -#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) -#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */ -#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) -#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) -#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */ -#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) -#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) -#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */ -#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) -#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) -#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */ -#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) -#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) -#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */ -#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) -#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) -#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */ -#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) -#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) -#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */ -#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) -#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) -#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */ -#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) -#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) -#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */ -#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) -#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) -#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */ -#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) -#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) -#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */ -#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) -#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) -#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */ -#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) -#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) -#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */ -#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) -#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) -#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */ -#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) -#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) -#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */ -#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) -#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) -#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */ -#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) -#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) -#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */ -#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) -#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) -#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */ -#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) -#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) -#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */ -#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) -#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) -#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */ -#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) -#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) -#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */ -#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) -#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) -#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */ -#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) -#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) -#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */ -#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) -#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) -#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */ -#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) -#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) -#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */ -#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) -#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) -#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */ -#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) -#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) -#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */ -#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) -#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) -#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */ -#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) -#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) -#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */ -#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) -#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) -#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */ -#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) -#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) -#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */ -#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) -#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) -#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */ -#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) -#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) -#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */ -#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) -#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) -#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */ -#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) -#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) -#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */ -#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) -#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) -#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */ -#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) -#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) -#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */ -#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) -#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) -#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */ -#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) -#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) -#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */ -#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) -#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) -#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */ -#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) -#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) -#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */ -#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) -#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) -#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */ -#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) -#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) -#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */ -#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) -#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) -#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */ -#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) -#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) -#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */ -#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) -#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) -#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */ -#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) -#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) -#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */ -#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) -#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) -#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */ -#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) -#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) -#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */ -#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) -#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) -#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */ -#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) -#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) -#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */ -#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) -#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) -#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */ -#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) -#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) -#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */ -#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) -#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) -#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */ -#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) -#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) -#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */ -#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) -#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) -#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */ -#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) -#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) -#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */ -#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) -#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) -#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */ -#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) -#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) -#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */ -#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) -#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) -#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */ -#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) -#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) -#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */ -#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) -#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) -#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */ -#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) -#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) -#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */ -#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) -#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) -#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */ -#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) -#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) -#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */ -#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) -#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) -#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */ -#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) -#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) -#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */ -#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) -#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) -#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */ -#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) -#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) -#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */ -#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) -#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) -#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */ -#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) -#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) -#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */ -#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) -#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) -#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */ -#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) -#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) -#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */ -#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) -#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) -#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */ -#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) -#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) -#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */ -#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) -#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) -#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */ -#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) -#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) -#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */ -#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) -#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) -#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */ -#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) -#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) -#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */ -#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) -#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) -#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */ -#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) -#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) -#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */ -#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) -#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) -#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */ -#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) -#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) -#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */ -#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) -#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) -#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */ -#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) -#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) -#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */ -#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) -#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) -#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */ -#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) -#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) -#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */ -#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) -#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) -#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */ -#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) -#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) -#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */ -#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) -#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) -#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */ -#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) -#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) -#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */ -#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) -#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) -#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */ -#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) -#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) -#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */ -#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) -#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) -#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */ -#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) -#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) -#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */ -#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) -#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) -#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */ -#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) -#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) -#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */ -#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) -#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) -#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */ -#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) -#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) -#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */ -#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) -#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) -#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */ -#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) -#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) -#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */ -#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) -#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) -#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */ -#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) -#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) -#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */ -#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) -#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) -#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */ -#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) -#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) -#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */ -#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) -#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) -#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */ -#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) -#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) -#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */ -#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) -#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) -#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */ -#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) -#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) -#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */ -#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) -#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) -#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */ -#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) -#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) -#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */ -#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) -#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) -#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */ -#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) -#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) -#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */ -#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) -#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) -#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */ -#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) -#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) -#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */ -#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) -#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) -#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */ -#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) -#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) -#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */ -#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) -#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) -#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */ -#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) -#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) -#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */ -#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) -#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) -#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */ -#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) -#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) -#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */ -#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) -#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) -#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */ -#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) -#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) -#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */ -#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) -#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) -#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */ -#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) -#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) -#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */ -#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) -#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) -#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */ -#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) -#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) -#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */ -#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) -#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) -#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */ -#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) -#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) -#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */ -#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) -#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) -#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */ -#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) -#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) -#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */ -#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) -#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) -#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */ -#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) -#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) -#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */ -#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) -#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) -#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */ -#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) -#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) -#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */ -#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) -#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) -#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */ -#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) -#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) -#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */ -#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) -#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) -#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */ -#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) -#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) -#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */ -#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) -#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) -#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */ -#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) -#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) -#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */ -#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) -#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) -#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */ -#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) -#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) -#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */ -#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) -#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) -#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */ -#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) -#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) -#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */ -#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) -#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) -#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */ -#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) -#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) -#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */ -#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) -#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) -#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */ -#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) -#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) -#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */ -#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) -#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) -#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */ -#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) -#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) -#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */ -#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) -#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) -#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */ -#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) -#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) -#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */ -#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) -#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) -#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */ -#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) -#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) -#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */ -#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) -#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) -#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */ -#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) -#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) -#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */ -#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) -#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) -#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */ -#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) -#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) -#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */ -#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) -#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) -#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */ -#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) -#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) -#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */ -#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) -#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) -#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */ -#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) -#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) -#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */ -#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) -#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) -#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */ -#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) -#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) -#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */ -#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) -#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) -#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */ -#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) -#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) -#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */ -#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) -#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) -#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */ -#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) -#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) -#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */ -#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) -#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) -#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */ -#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) -#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) -#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */ -#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) -#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) -#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */ -#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) -#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) -#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */ -#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) -#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) -#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */ -#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) -#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) -#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */ -#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) -#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) -#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */ -#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) -#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) -#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */ -#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) -#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) -#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */ -#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) -#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) -#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */ -#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) -#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) -#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */ -#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) -#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) -#define pCAN1_MC1 ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */ -#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) -#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) -#define pCAN1_MD1 ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */ -#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) -#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) -#define pCAN1_TRS1 ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */ -#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) -#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) -#define pCAN1_TRR1 ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */ -#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) -#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) -#define pCAN1_TA1 ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */ -#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) -#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) -#define pCAN1_AA1 ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */ -#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) -#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) -#define pCAN1_RMP1 ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */ -#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) -#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) -#define pCAN1_RML1 ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */ -#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) -#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) -#define pCAN1_MBTIF1 ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ -#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) -#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) -#define pCAN1_MBRIF1 ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ -#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) -#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) -#define pCAN1_MBIM1 ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ -#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) -#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) -#define pCAN1_RFH1 ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ -#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) -#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) -#define pCAN1_OPSS1 ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ -#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) -#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) -#define pCAN1_MC2 ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */ -#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) -#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) -#define pCAN1_MD2 ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */ -#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) -#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) -#define pCAN1_TRS2 ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */ -#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) -#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) -#define pCAN1_TRR2 ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */ -#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) -#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) -#define pCAN1_TA2 ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */ -#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) -#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) -#define pCAN1_AA2 ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */ -#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) -#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) -#define pCAN1_RMP2 ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */ -#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) -#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) -#define pCAN1_RML2 ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */ -#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) -#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) -#define pCAN1_MBTIF2 ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ -#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) -#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) -#define pCAN1_MBRIF2 ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ -#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) -#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) -#define pCAN1_MBIM2 ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ -#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) -#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) -#define pCAN1_RFH2 ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ -#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) -#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) -#define pCAN1_OPSS2 ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ -#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) -#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) -#define pCAN1_CLOCK ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */ -#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) -#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) -#define pCAN1_TIMING ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */ -#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) -#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) -#define pCAN1_DEBUG ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */ -#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) -#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) -#define pCAN1_STATUS ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */ -#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) -#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) -#define pCAN1_CEC ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */ -#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) -#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) -#define pCAN1_GIS ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */ -#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) -#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) -#define pCAN1_GIM ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */ -#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) -#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) -#define pCAN1_GIF ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */ -#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) -#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) -#define pCAN1_CONTROL ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */ -#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) -#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) -#define pCAN1_INTR ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */ -#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) -#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) -#define pCAN1_MBTD ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */ -#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) -#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) -#define pCAN1_EWR ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */ -#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) -#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) -#define pCAN1_ESR ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */ -#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) -#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) -#define pCAN1_UCCNT ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */ -#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) -#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) -#define pCAN1_UCRC ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */ -#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) -#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) -#define pCAN1_UCCNF ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */ -#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) -#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) -#define pCAN1_AM00L ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) -#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) -#define pCAN1_AM00H ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) -#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) -#define pCAN1_AM01L ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) -#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) -#define pCAN1_AM01H ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) -#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) -#define pCAN1_AM02L ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) -#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) -#define pCAN1_AM02H ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) -#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) -#define pCAN1_AM03L ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) -#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) -#define pCAN1_AM03H ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) -#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) -#define pCAN1_AM04L ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) -#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) -#define pCAN1_AM04H ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) -#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) -#define pCAN1_AM05L ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) -#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) -#define pCAN1_AM05H ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) -#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) -#define pCAN1_AM06L ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) -#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) -#define pCAN1_AM06H ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) -#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) -#define pCAN1_AM07L ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) -#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) -#define pCAN1_AM07H ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) -#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) -#define pCAN1_AM08L ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) -#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) -#define pCAN1_AM08H ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) -#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) -#define pCAN1_AM09L ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) -#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) -#define pCAN1_AM09H ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) -#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) -#define pCAN1_AM10L ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) -#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) -#define pCAN1_AM10H ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) -#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) -#define pCAN1_AM11L ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) -#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) -#define pCAN1_AM11H ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) -#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) -#define pCAN1_AM12L ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) -#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) -#define pCAN1_AM12H ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) -#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) -#define pCAN1_AM13L ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) -#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) -#define pCAN1_AM13H ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) -#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) -#define pCAN1_AM14L ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) -#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) -#define pCAN1_AM14H ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) -#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) -#define pCAN1_AM15L ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) -#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) -#define pCAN1_AM15H ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) -#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) -#define pCAN1_AM16L ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) -#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) -#define pCAN1_AM16H ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) -#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) -#define pCAN1_AM17L ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) -#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) -#define pCAN1_AM17H ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) -#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) -#define pCAN1_AM18L ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) -#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) -#define pCAN1_AM18H ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) -#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) -#define pCAN1_AM19L ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) -#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) -#define pCAN1_AM19H ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) -#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) -#define pCAN1_AM20L ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) -#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) -#define pCAN1_AM20H ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) -#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) -#define pCAN1_AM21L ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) -#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) -#define pCAN1_AM21H ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) -#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) -#define pCAN1_AM22L ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) -#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) -#define pCAN1_AM22H ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) -#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) -#define pCAN1_AM23L ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) -#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) -#define pCAN1_AM23H ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) -#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) -#define pCAN1_AM24L ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) -#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) -#define pCAN1_AM24H ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) -#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) -#define pCAN1_AM25L ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) -#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) -#define pCAN1_AM25H ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) -#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) -#define pCAN1_AM26L ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) -#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) -#define pCAN1_AM26H ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) -#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) -#define pCAN1_AM27L ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) -#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) -#define pCAN1_AM27H ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) -#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) -#define pCAN1_AM28L ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) -#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) -#define pCAN1_AM28H ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) -#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) -#define pCAN1_AM29L ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) -#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) -#define pCAN1_AM29H ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) -#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) -#define pCAN1_AM30L ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) -#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) -#define pCAN1_AM30H ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) -#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) -#define pCAN1_AM31L ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) -#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) -#define pCAN1_AM31H ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) -#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) -#define pCAN1_MB00_DATA0 ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */ -#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) -#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) -#define pCAN1_MB00_DATA1 ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */ -#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) -#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) -#define pCAN1_MB00_DATA2 ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */ -#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) -#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) -#define pCAN1_MB00_DATA3 ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */ -#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) -#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) -#define pCAN1_MB00_LENGTH ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */ -#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) -#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) -#define pCAN1_MB00_TIMESTAMP ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */ -#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) -#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) -#define pCAN1_MB00_ID0 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */ -#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) -#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) -#define pCAN1_MB00_ID1 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */ -#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) -#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) -#define pCAN1_MB01_DATA0 ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */ -#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) -#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) -#define pCAN1_MB01_DATA1 ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */ -#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) -#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) -#define pCAN1_MB01_DATA2 ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */ -#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) -#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) -#define pCAN1_MB01_DATA3 ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */ -#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) -#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) -#define pCAN1_MB01_LENGTH ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */ -#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) -#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) -#define pCAN1_MB01_TIMESTAMP ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */ -#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) -#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) -#define pCAN1_MB01_ID0 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */ -#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) -#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) -#define pCAN1_MB01_ID1 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */ -#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) -#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) -#define pCAN1_MB02_DATA0 ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */ -#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) -#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) -#define pCAN1_MB02_DATA1 ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */ -#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) -#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) -#define pCAN1_MB02_DATA2 ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */ -#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) -#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) -#define pCAN1_MB02_DATA3 ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */ -#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) -#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) -#define pCAN1_MB02_LENGTH ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */ -#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) -#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) -#define pCAN1_MB02_TIMESTAMP ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */ -#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) -#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) -#define pCAN1_MB02_ID0 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */ -#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) -#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) -#define pCAN1_MB02_ID1 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */ -#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) -#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) -#define pCAN1_MB03_DATA0 ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */ -#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) -#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) -#define pCAN1_MB03_DATA1 ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */ -#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) -#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) -#define pCAN1_MB03_DATA2 ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */ -#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) -#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) -#define pCAN1_MB03_DATA3 ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */ -#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) -#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) -#define pCAN1_MB03_LENGTH ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */ -#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) -#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) -#define pCAN1_MB03_TIMESTAMP ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */ -#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) -#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) -#define pCAN1_MB03_ID0 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */ -#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) -#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) -#define pCAN1_MB03_ID1 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */ -#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) -#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) -#define pCAN1_MB04_DATA0 ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */ -#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) -#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) -#define pCAN1_MB04_DATA1 ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */ -#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) -#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) -#define pCAN1_MB04_DATA2 ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */ -#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) -#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) -#define pCAN1_MB04_DATA3 ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */ -#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) -#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) -#define pCAN1_MB04_LENGTH ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */ -#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) -#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) -#define pCAN1_MB04_TIMESTAMP ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */ -#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) -#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) -#define pCAN1_MB04_ID0 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */ -#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) -#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) -#define pCAN1_MB04_ID1 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */ -#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) -#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) -#define pCAN1_MB05_DATA0 ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */ -#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) -#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) -#define pCAN1_MB05_DATA1 ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */ -#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) -#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) -#define pCAN1_MB05_DATA2 ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */ -#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) -#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) -#define pCAN1_MB05_DATA3 ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */ -#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) -#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) -#define pCAN1_MB05_LENGTH ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */ -#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) -#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) -#define pCAN1_MB05_TIMESTAMP ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */ -#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) -#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) -#define pCAN1_MB05_ID0 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */ -#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) -#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) -#define pCAN1_MB05_ID1 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */ -#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) -#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) -#define pCAN1_MB06_DATA0 ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */ -#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) -#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) -#define pCAN1_MB06_DATA1 ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */ -#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) -#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) -#define pCAN1_MB06_DATA2 ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */ -#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) -#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) -#define pCAN1_MB06_DATA3 ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */ -#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) -#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) -#define pCAN1_MB06_LENGTH ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */ -#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) -#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) -#define pCAN1_MB06_TIMESTAMP ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */ -#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) -#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) -#define pCAN1_MB06_ID0 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */ -#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) -#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) -#define pCAN1_MB06_ID1 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */ -#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) -#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) -#define pCAN1_MB07_DATA0 ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */ -#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) -#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) -#define pCAN1_MB07_DATA1 ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */ -#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) -#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) -#define pCAN1_MB07_DATA2 ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */ -#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) -#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) -#define pCAN1_MB07_DATA3 ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */ -#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) -#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) -#define pCAN1_MB07_LENGTH ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */ -#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) -#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) -#define pCAN1_MB07_TIMESTAMP ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */ -#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) -#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) -#define pCAN1_MB07_ID0 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */ -#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) -#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) -#define pCAN1_MB07_ID1 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */ -#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) -#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) -#define pCAN1_MB08_DATA0 ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */ -#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) -#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) -#define pCAN1_MB08_DATA1 ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */ -#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) -#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) -#define pCAN1_MB08_DATA2 ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */ -#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) -#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) -#define pCAN1_MB08_DATA3 ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */ -#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) -#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) -#define pCAN1_MB08_LENGTH ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */ -#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) -#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) -#define pCAN1_MB08_TIMESTAMP ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */ -#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) -#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) -#define pCAN1_MB08_ID0 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */ -#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) -#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) -#define pCAN1_MB08_ID1 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */ -#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) -#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) -#define pCAN1_MB09_DATA0 ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */ -#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) -#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) -#define pCAN1_MB09_DATA1 ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */ -#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) -#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) -#define pCAN1_MB09_DATA2 ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */ -#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) -#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) -#define pCAN1_MB09_DATA3 ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */ -#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) -#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) -#define pCAN1_MB09_LENGTH ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */ -#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) -#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) -#define pCAN1_MB09_TIMESTAMP ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */ -#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) -#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) -#define pCAN1_MB09_ID0 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */ -#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) -#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) -#define pCAN1_MB09_ID1 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */ -#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) -#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) -#define pCAN1_MB10_DATA0 ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */ -#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) -#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) -#define pCAN1_MB10_DATA1 ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */ -#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) -#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) -#define pCAN1_MB10_DATA2 ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */ -#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) -#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) -#define pCAN1_MB10_DATA3 ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */ -#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) -#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) -#define pCAN1_MB10_LENGTH ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */ -#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) -#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) -#define pCAN1_MB10_TIMESTAMP ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */ -#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) -#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) -#define pCAN1_MB10_ID0 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */ -#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) -#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) -#define pCAN1_MB10_ID1 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */ -#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) -#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) -#define pCAN1_MB11_DATA0 ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */ -#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) -#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) -#define pCAN1_MB11_DATA1 ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */ -#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) -#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) -#define pCAN1_MB11_DATA2 ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */ -#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) -#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) -#define pCAN1_MB11_DATA3 ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */ -#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) -#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) -#define pCAN1_MB11_LENGTH ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */ -#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) -#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) -#define pCAN1_MB11_TIMESTAMP ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */ -#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) -#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) -#define pCAN1_MB11_ID0 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */ -#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) -#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) -#define pCAN1_MB11_ID1 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */ -#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) -#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) -#define pCAN1_MB12_DATA0 ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */ -#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) -#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) -#define pCAN1_MB12_DATA1 ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */ -#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) -#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) -#define pCAN1_MB12_DATA2 ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */ -#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) -#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) -#define pCAN1_MB12_DATA3 ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */ -#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) -#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) -#define pCAN1_MB12_LENGTH ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */ -#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) -#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) -#define pCAN1_MB12_TIMESTAMP ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */ -#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) -#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) -#define pCAN1_MB12_ID0 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */ -#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) -#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) -#define pCAN1_MB12_ID1 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */ -#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) -#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) -#define pCAN1_MB13_DATA0 ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */ -#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) -#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) -#define pCAN1_MB13_DATA1 ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */ -#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) -#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) -#define pCAN1_MB13_DATA2 ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */ -#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) -#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) -#define pCAN1_MB13_DATA3 ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */ -#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) -#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) -#define pCAN1_MB13_LENGTH ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */ -#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) -#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) -#define pCAN1_MB13_TIMESTAMP ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */ -#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) -#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) -#define pCAN1_MB13_ID0 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */ -#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) -#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) -#define pCAN1_MB13_ID1 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */ -#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) -#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) -#define pCAN1_MB14_DATA0 ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */ -#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) -#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) -#define pCAN1_MB14_DATA1 ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */ -#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) -#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) -#define pCAN1_MB14_DATA2 ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */ -#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) -#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) -#define pCAN1_MB14_DATA3 ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */ -#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) -#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) -#define pCAN1_MB14_LENGTH ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */ -#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) -#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) -#define pCAN1_MB14_TIMESTAMP ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */ -#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) -#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) -#define pCAN1_MB14_ID0 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */ -#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) -#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) -#define pCAN1_MB14_ID1 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */ -#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) -#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) -#define pCAN1_MB15_DATA0 ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */ -#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) -#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) -#define pCAN1_MB15_DATA1 ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */ -#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) -#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) -#define pCAN1_MB15_DATA2 ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */ -#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) -#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) -#define pCAN1_MB15_DATA3 ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */ -#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) -#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) -#define pCAN1_MB15_LENGTH ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */ -#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) -#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) -#define pCAN1_MB15_TIMESTAMP ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */ -#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) -#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) -#define pCAN1_MB15_ID0 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */ -#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) -#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) -#define pCAN1_MB15_ID1 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */ -#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) -#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) -#define pCAN1_MB16_DATA0 ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */ -#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) -#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) -#define pCAN1_MB16_DATA1 ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */ -#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) -#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) -#define pCAN1_MB16_DATA2 ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */ -#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) -#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) -#define pCAN1_MB16_DATA3 ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */ -#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) -#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) -#define pCAN1_MB16_LENGTH ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */ -#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) -#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) -#define pCAN1_MB16_TIMESTAMP ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */ -#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) -#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) -#define pCAN1_MB16_ID0 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */ -#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) -#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) -#define pCAN1_MB16_ID1 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */ -#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) -#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) -#define pCAN1_MB17_DATA0 ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */ -#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) -#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) -#define pCAN1_MB17_DATA1 ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */ -#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) -#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) -#define pCAN1_MB17_DATA2 ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */ -#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) -#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) -#define pCAN1_MB17_DATA3 ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */ -#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) -#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) -#define pCAN1_MB17_LENGTH ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */ -#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) -#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) -#define pCAN1_MB17_TIMESTAMP ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */ -#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) -#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) -#define pCAN1_MB17_ID0 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */ -#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) -#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) -#define pCAN1_MB17_ID1 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */ -#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) -#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) -#define pCAN1_MB18_DATA0 ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */ -#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) -#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) -#define pCAN1_MB18_DATA1 ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */ -#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) -#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) -#define pCAN1_MB18_DATA2 ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */ -#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) -#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) -#define pCAN1_MB18_DATA3 ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */ -#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) -#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) -#define pCAN1_MB18_LENGTH ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */ -#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) -#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) -#define pCAN1_MB18_TIMESTAMP ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */ -#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) -#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) -#define pCAN1_MB18_ID0 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */ -#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) -#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) -#define pCAN1_MB18_ID1 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */ -#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) -#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) -#define pCAN1_MB19_DATA0 ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */ -#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) -#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) -#define pCAN1_MB19_DATA1 ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */ -#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) -#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) -#define pCAN1_MB19_DATA2 ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */ -#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) -#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) -#define pCAN1_MB19_DATA3 ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */ -#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) -#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) -#define pCAN1_MB19_LENGTH ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */ -#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) -#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) -#define pCAN1_MB19_TIMESTAMP ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */ -#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) -#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) -#define pCAN1_MB19_ID0 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */ -#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) -#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) -#define pCAN1_MB19_ID1 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */ -#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) -#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) -#define pCAN1_MB20_DATA0 ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */ -#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) -#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) -#define pCAN1_MB20_DATA1 ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */ -#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) -#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) -#define pCAN1_MB20_DATA2 ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */ -#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) -#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) -#define pCAN1_MB20_DATA3 ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */ -#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) -#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) -#define pCAN1_MB20_LENGTH ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */ -#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) -#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) -#define pCAN1_MB20_TIMESTAMP ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */ -#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) -#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) -#define pCAN1_MB20_ID0 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */ -#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) -#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) -#define pCAN1_MB20_ID1 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */ -#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) -#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) -#define pCAN1_MB21_DATA0 ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */ -#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) -#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) -#define pCAN1_MB21_DATA1 ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */ -#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) -#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) -#define pCAN1_MB21_DATA2 ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */ -#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) -#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) -#define pCAN1_MB21_DATA3 ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */ -#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) -#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) -#define pCAN1_MB21_LENGTH ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */ -#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) -#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) -#define pCAN1_MB21_TIMESTAMP ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */ -#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) -#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) -#define pCAN1_MB21_ID0 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */ -#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) -#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) -#define pCAN1_MB21_ID1 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */ -#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) -#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) -#define pCAN1_MB22_DATA0 ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */ -#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) -#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) -#define pCAN1_MB22_DATA1 ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */ -#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) -#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) -#define pCAN1_MB22_DATA2 ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */ -#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) -#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) -#define pCAN1_MB22_DATA3 ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */ -#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) -#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) -#define pCAN1_MB22_LENGTH ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */ -#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) -#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) -#define pCAN1_MB22_TIMESTAMP ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */ -#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) -#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) -#define pCAN1_MB22_ID0 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */ -#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) -#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) -#define pCAN1_MB22_ID1 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */ -#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) -#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) -#define pCAN1_MB23_DATA0 ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */ -#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) -#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) -#define pCAN1_MB23_DATA1 ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */ -#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) -#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) -#define pCAN1_MB23_DATA2 ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */ -#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) -#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) -#define pCAN1_MB23_DATA3 ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */ -#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) -#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) -#define pCAN1_MB23_LENGTH ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */ -#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) -#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) -#define pCAN1_MB23_TIMESTAMP ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */ -#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) -#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) -#define pCAN1_MB23_ID0 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */ -#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) -#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) -#define pCAN1_MB23_ID1 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */ -#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) -#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) -#define pCAN1_MB24_DATA0 ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */ -#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) -#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) -#define pCAN1_MB24_DATA1 ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */ -#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) -#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) -#define pCAN1_MB24_DATA2 ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */ -#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) -#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) -#define pCAN1_MB24_DATA3 ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */ -#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) -#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) -#define pCAN1_MB24_LENGTH ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */ -#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) -#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) -#define pCAN1_MB24_TIMESTAMP ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */ -#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) -#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) -#define pCAN1_MB24_ID0 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */ -#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) -#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) -#define pCAN1_MB24_ID1 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */ -#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) -#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) -#define pCAN1_MB25_DATA0 ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */ -#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) -#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) -#define pCAN1_MB25_DATA1 ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */ -#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) -#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) -#define pCAN1_MB25_DATA2 ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */ -#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) -#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) -#define pCAN1_MB25_DATA3 ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */ -#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) -#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) -#define pCAN1_MB25_LENGTH ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */ -#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) -#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) -#define pCAN1_MB25_TIMESTAMP ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */ -#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) -#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) -#define pCAN1_MB25_ID0 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */ -#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) -#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) -#define pCAN1_MB25_ID1 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */ -#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) -#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) -#define pCAN1_MB26_DATA0 ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */ -#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) -#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) -#define pCAN1_MB26_DATA1 ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */ -#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) -#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) -#define pCAN1_MB26_DATA2 ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */ -#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) -#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) -#define pCAN1_MB26_DATA3 ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */ -#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) -#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) -#define pCAN1_MB26_LENGTH ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */ -#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) -#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) -#define pCAN1_MB26_TIMESTAMP ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */ -#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) -#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) -#define pCAN1_MB26_ID0 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */ -#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) -#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) -#define pCAN1_MB26_ID1 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */ -#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) -#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) -#define pCAN1_MB27_DATA0 ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */ -#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) -#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) -#define pCAN1_MB27_DATA1 ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */ -#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) -#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) -#define pCAN1_MB27_DATA2 ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */ -#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) -#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) -#define pCAN1_MB27_DATA3 ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */ -#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) -#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) -#define pCAN1_MB27_LENGTH ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */ -#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) -#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) -#define pCAN1_MB27_TIMESTAMP ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */ -#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) -#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) -#define pCAN1_MB27_ID0 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */ -#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) -#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) -#define pCAN1_MB27_ID1 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */ -#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) -#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) -#define pCAN1_MB28_DATA0 ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */ -#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) -#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) -#define pCAN1_MB28_DATA1 ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */ -#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) -#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) -#define pCAN1_MB28_DATA2 ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */ -#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) -#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) -#define pCAN1_MB28_DATA3 ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */ -#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) -#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) -#define pCAN1_MB28_LENGTH ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */ -#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) -#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) -#define pCAN1_MB28_TIMESTAMP ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */ -#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) -#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) -#define pCAN1_MB28_ID0 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */ -#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) -#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) -#define pCAN1_MB28_ID1 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */ -#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) -#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) -#define pCAN1_MB29_DATA0 ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */ -#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) -#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) -#define pCAN1_MB29_DATA1 ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */ -#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) -#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) -#define pCAN1_MB29_DATA2 ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */ -#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) -#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) -#define pCAN1_MB29_DATA3 ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */ -#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) -#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) -#define pCAN1_MB29_LENGTH ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */ -#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) -#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) -#define pCAN1_MB29_TIMESTAMP ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */ -#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) -#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) -#define pCAN1_MB29_ID0 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */ -#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) -#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) -#define pCAN1_MB29_ID1 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */ -#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) -#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) -#define pCAN1_MB30_DATA0 ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */ -#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) -#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) -#define pCAN1_MB30_DATA1 ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */ -#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) -#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) -#define pCAN1_MB30_DATA2 ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */ -#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) -#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) -#define pCAN1_MB30_DATA3 ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */ -#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) -#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) -#define pCAN1_MB30_LENGTH ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */ -#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) -#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) -#define pCAN1_MB30_TIMESTAMP ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */ -#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) -#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) -#define pCAN1_MB30_ID0 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */ -#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) -#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) -#define pCAN1_MB30_ID1 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */ -#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) -#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) -#define pCAN1_MB31_DATA0 ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */ -#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) -#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) -#define pCAN1_MB31_DATA1 ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */ -#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) -#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) -#define pCAN1_MB31_DATA2 ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */ -#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) -#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) -#define pCAN1_MB31_DATA3 ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */ -#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) -#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) -#define pCAN1_MB31_LENGTH ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */ -#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) -#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) -#define pCAN1_MB31_TIMESTAMP ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */ -#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) -#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) -#define pCAN1_MB31_ID0 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */ -#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) -#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) -#define pCAN1_MB31_ID1 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */ -#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) -#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) -#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */ -#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) -#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */ -#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) -#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */ -#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) -#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */ -#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) -#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */ -#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) -#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */ -#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) -#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) -#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */ -#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) -#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */ -#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) -#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */ -#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) -#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */ -#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) -#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */ -#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) -#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */ -#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) -#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) -#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define pSPI2_CTL ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */ -#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) -#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) -#define pSPI2_FLG ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */ -#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) -#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) -#define pSPI2_STAT ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */ -#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) -#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) -#define pSPI2_TDBR ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */ -#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) -#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) -#define pSPI2_RDBR ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */ -#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) -#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) -#define pSPI2_BAUD ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */ -#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) -#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) -#define pSPI2_SHADOW ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) -#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) -#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */ -#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */ -#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL) -#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val) -#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */ -#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */ -#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */ -#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) -#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */ -#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */ -#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */ -#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */ -#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) -#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */ -#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */ -#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL) -#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val) -#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */ -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */ -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */ -#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) -#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) -#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */ -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */ -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */ -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */ -#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) -#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) -#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */ -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */ -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */ -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */ -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */ -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */ -#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) -#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */ -#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) -#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) -#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) -#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ -#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) -#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */ -#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) -#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) -#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) -#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */ -#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) -#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */ -#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) -#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) -#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) -#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */ -#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) -#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) -#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) -#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) -#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) -#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) -#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) -#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) -#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) -#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */ -#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) -#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */ -#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) -#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) -#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) -#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ -#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) -#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */ -#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) -#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) -#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) -#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */ -#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) -#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */ -#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) -#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) -#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) -#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */ -#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) -#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) -#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) -#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) -#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) -#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) -#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) -#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) -#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) -#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */ -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) -#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) -#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */ -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */ -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) -#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) -#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */ -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART2_DLL ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) -#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) -#define pUART2_DLH ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) -#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) -#define pUART2_GCTL ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */ -#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) -#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) -#define pUART2_LCR ((uint16_t volatile *)UART2_LCR) /* Line Control Register */ -#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) -#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) -#define pUART2_MCR ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */ -#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) -#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) -#define pUART2_LSR ((uint16_t volatile *)UART2_LSR) /* Line Status Register */ -#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) -#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) -#define pUART2_MSR ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */ -#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) -#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) -#define pUART2_SCR ((uint16_t volatile *)UART2_SCR) /* Scratch Register */ -#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) -#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) -#define pUART2_IER_SET ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) -#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) -#define pUART2_IER_CLEAR ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) -#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) -#define pUART2_THR ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */ -#define bfin_read_UART2_THR() bfin_read16(UART2_THR) -#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val) -#define pUART2_RBR ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */ -#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) -#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) -#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) -#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) -#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */ -#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) -#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */ -#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) -#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */ -#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) -#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */ -#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) -#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */ -#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) -#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */ -#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) -#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) -#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) -#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */ -#define bfin_read_UART3_THR() bfin_read16(UART3_THR) -#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */ -#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) -#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_BF548_extended__ */ diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_def.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_def.h deleted file mode 100644 index a92479b..0000000 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_def.h +++ /dev/null @@ -1,1937 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_BF548_extended__ -#define __BFIN_DEF_ADSP_EDN_BF548_extended__ - -#define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */ -#define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */ -#define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */ -#define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */ -#define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */ -#define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */ -#define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */ -#define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */ -#define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */ -#define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */ -#define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */ -#define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */ -#define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */ -#define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */ -#define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */ -#define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */ -#define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */ -#define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */ -#define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ -#define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */ -#define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ -#define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */ -#define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ -#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */ -#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */ -#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */ -#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */ -#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */ -#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */ -#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */ -#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */ -#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */ -#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */ -#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */ -#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */ -#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */ -#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */ -#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */ -#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */ -#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */ -#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */ -#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */ -#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */ -#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */ -#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */ -#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */ -#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */ -#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */ -#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */ -#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */ -#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */ -#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */ -#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */ -#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */ -#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */ -#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */ -#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */ -#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */ -#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */ -#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */ -#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */ -#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */ -#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */ -#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */ -#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */ -#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */ -#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */ -#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */ -#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */ -#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */ -#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */ -#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */ -#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */ -#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */ -#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */ -#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */ -#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */ -#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */ -#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */ -#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */ -#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */ -#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */ -#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */ -#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */ -#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */ -#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */ -#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */ -#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */ -#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */ -#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */ -#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */ -#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */ -#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */ -#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */ -#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */ -#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */ -#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */ -#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */ -#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */ -#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */ -#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */ -#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */ -#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */ -#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */ -#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */ -#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */ -#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */ -#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */ -#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */ -#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */ -#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */ -#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */ -#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */ -#define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */ -#define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */ -#define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */ -#define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */ -#define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */ -#define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */ -#define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */ -#define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */ -#define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */ -#define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */ -#define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */ -#define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */ -#define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */ -#define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */ -#define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */ -#define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */ -#define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */ -#define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */ -#define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */ -#define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */ -#define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */ -#define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */ -#define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */ -#define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */ -#define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */ -#define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */ -#define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */ -#define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */ -#define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */ -#define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */ -#define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */ -#define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */ -#define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */ -#define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */ -#define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */ -#define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */ -#define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */ -#define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */ -#define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */ -#define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */ -#define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */ -#define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */ -#define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */ -#define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */ -#define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */ -#define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */ -#define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */ -#define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */ -#define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */ -#define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */ -#define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */ -#define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */ -#define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */ -#define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */ -#define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */ -#define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */ -#define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */ -#define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */ -#define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */ -#define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */ -#define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */ -#define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */ -#define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */ -#define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */ -#define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */ -#define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */ -#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */ -#define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */ -#define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */ -#define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */ -#define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */ -#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */ -#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */ -#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */ -#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */ -#define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */ -#define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */ -#define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */ -#define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */ -#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */ -#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */ -#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */ -#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */ -#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */ -#define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */ -#define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */ -#define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */ -#define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */ -#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */ -#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */ -#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */ -#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */ -#define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */ -#define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */ -#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */ -#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */ -#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */ -#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */ -#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */ -#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */ -#define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */ -#define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */ -#define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */ -#define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */ -#define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */ -#define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */ -#define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */ -#define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */ -#define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */ -#define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */ -#define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */ -#define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */ -#define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */ -#define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ -#define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */ -#define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */ -#define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */ -#define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */ -#define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */ -#define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */ -#define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */ -#define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */ -#define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */ -#define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */ -#define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */ -#define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */ -#define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */ -#define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */ -#define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */ -#define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */ -#define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */ -#define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */ -#define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */ -#define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */ -#define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */ -#define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */ -#define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */ -#define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */ -#define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */ -#define PIXC_CTL 0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define PIXC_PPL 0xFFC04404 /* Holds the number of pixels per line of the display */ -#define PIXC_LPF 0xFFC04408 /* Holds the number of lines per frame of the display */ -#define PIXC_AHSTART 0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */ -#define PIXC_AHEND 0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */ -#define PIXC_AVSTART 0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */ -#define PIXC_AVEND 0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */ -#define PIXC_ATRANSP 0xFFC0441C /* Contains the transparency ratio (set A) */ -#define PIXC_BHSTART 0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */ -#define PIXC_BHEND 0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */ -#define PIXC_BVSTART 0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */ -#define PIXC_BVEND 0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */ -#define PIXC_BTRANSP 0xFFC04430 /* Contains the transparency ratio (set B) */ -#define PIXC_INTRSTAT 0xFFC0443C /* Overlay interrupt configuration/status */ -#define PIXC_RYCON 0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define PIXC_GUCON 0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define PIXC_BVCON 0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define PIXC_CCBIAS 0xFFC0444C /* Bias values for the color space conversion matrix */ -#define PIXC_TC 0xFFC04450 /* Holds the transparent color value */ -#define HOST_CONTROL 0xFFC03A00 /* HOSTDP Control Register */ -#define HOST_STATUS 0xFFC03A04 /* HOSTDP Status Register */ -#define HOST_TIMEOUT 0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */ -#define PORTA_FER 0xFFC014C0 /* Function Enable Register */ -#define PORTA 0xFFC014C4 /* GPIO Data Register */ -#define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */ -#define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */ -#define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */ -#define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */ -#define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */ -#define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */ -#define PORTB_FER 0xFFC014E0 /* Function Enable Register */ -#define PORTB 0xFFC014E4 /* GPIO Data Register */ -#define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */ -#define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */ -#define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */ -#define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */ -#define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */ -#define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */ -#define PORTC_FER 0xFFC01500 /* Function Enable Register */ -#define PORTC 0xFFC01504 /* GPIO Data Register */ -#define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */ -#define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */ -#define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */ -#define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */ -#define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */ -#define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */ -#define PORTD_FER 0xFFC01520 /* Function Enable Register */ -#define PORTD 0xFFC01524 /* GPIO Data Register */ -#define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */ -#define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */ -#define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */ -#define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */ -#define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */ -#define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */ -#define PORTE_FER 0xFFC01540 /* Function Enable Register */ -#define PORTE 0xFFC01544 /* GPIO Data Register */ -#define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */ -#define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */ -#define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */ -#define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */ -#define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */ -#define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */ -#define PORTF_FER 0xFFC01560 /* Function Enable Register */ -#define PORTF 0xFFC01564 /* GPIO Data Register */ -#define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */ -#define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */ -#define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */ -#define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */ -#define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */ -#define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */ -#define PORTG_FER 0xFFC01580 /* Function Enable Register */ -#define PORTG 0xFFC01584 /* GPIO Data Register */ -#define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */ -#define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */ -#define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */ -#define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */ -#define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */ -#define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */ -#define PORTH_FER 0xFFC015A0 /* Function Enable Register */ -#define PORTH 0xFFC015A4 /* GPIO Data Register */ -#define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */ -#define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */ -#define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */ -#define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */ -#define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */ -#define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */ -#define PORTI_FER 0xFFC015C0 /* Function Enable Register */ -#define PORTI 0xFFC015C4 /* GPIO Data Register */ -#define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */ -#define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */ -#define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */ -#define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */ -#define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */ -#define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */ -#define PORTJ_FER 0xFFC015E0 /* Function Enable Register */ -#define PORTJ 0xFFC015E4 /* GPIO Data Register */ -#define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */ -#define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */ -#define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */ -#define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */ -#define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */ -#define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */ -#define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */ -#define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */ -#define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */ -#define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */ -#define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */ -#define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */ -#define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */ -#define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */ -#define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */ -#define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */ -#define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */ -#define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */ -#define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */ -#define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */ -#define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */ -#define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */ -#define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */ -#define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */ -#define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */ -#define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */ -#define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */ -#define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */ -#define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */ -#define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */ -#define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */ -#define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */ -#define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */ -#define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */ -#define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */ -#define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */ -#define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */ -#define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */ -#define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */ -#define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */ -#define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */ -#define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */ -#define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */ -#define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */ -#define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */ -#define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */ -#define TIMER8_CONFIG 0xFFC00600 /* Timer 8 Configuration Register */ -#define TIMER8_COUNTER 0xFFC00604 /* Timer 8 Counter Register */ -#define TIMER8_PERIOD 0xFFC00608 /* Timer 8 Period Register */ -#define TIMER8_WIDTH 0xFFC0060C /* Timer 8 Width Register */ -#define TIMER9_CONFIG 0xFFC00610 /* Timer 9 Configuration Register */ -#define TIMER9_COUNTER 0xFFC00614 /* Timer 9 Counter Register */ -#define TIMER9_PERIOD 0xFFC00618 /* Timer 9 Period Register */ -#define TIMER9_WIDTH 0xFFC0061C /* Timer 9 Width Register */ -#define TIMER10_CONFIG 0xFFC00620 /* Timer 10 Configuration Register */ -#define TIMER10_COUNTER 0xFFC00624 /* Timer 10 Counter Register */ -#define TIMER10_PERIOD 0xFFC00628 /* Timer 10 Period Register */ -#define TIMER10_WIDTH 0xFFC0062C /* Timer 10 Width Register */ -#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */ -#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */ -#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */ -#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */ -#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */ -#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define CNT_CONFIG 0xFFC04200 /* Configuration Register */ -#define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */ -#define CNT_STATUS 0xFFC04208 /* Status Register */ -#define CNT_COMMAND 0xFFC0420C /* Command Register */ -#define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */ -#define CNT_COUNTER 0xFFC04214 /* Counter Register */ -#define CNT_MAX 0xFFC04218 /* Maximal Count Register */ -#define CNT_MIN 0xFFC0421C /* Minimal Count Register */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ -#define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */ -#define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */ -#define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */ -#define SECURE_CONTROL 0xFFC04324 /* Secure Control */ -#define SECURE_STATUS 0xFFC04328 /* Secure Status */ -#define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divisor Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define KPAD_CTL 0xFFC04100 /* Controls keypad module enable and disable */ -#define KPAD_PRESCALE 0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */ -#define KPAD_MSEL 0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */ -#define KPAD_ROWCOL 0xFFC0410C /* Captures the row and column output values of the keys pressed */ -#define KPAD_STAT 0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */ -#define KPAD_SOFTEVAL 0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */ -#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ -#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ -#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ -#define SDH_COMMAND 0xFFC0390C /* SDH Command */ -#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ -#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ -#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ -#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ -#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ -#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ -#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ -#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ -#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ -#define SDH_STATUS 0xFFC03934 /* SDH Status */ -#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ -#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ -#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ -#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ -#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ -#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ -#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ -#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ -#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ -#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ -#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ -#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ -#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ -#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ -#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ -#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ -#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ -#define ATAPI_CONTROL 0xFFC03800 /* ATAPI Control Register */ -#define ATAPI_STATUS 0xFFC03804 /* ATAPI Status Register */ -#define ATAPI_DEV_ADDR 0xFFC03808 /* ATAPI Device Register Address */ -#define ATAPI_DEV_TXBUF 0xFFC0380C /* ATAPI Device Register Write Data */ -#define ATAPI_DEV_RXBUF 0xFFC03810 /* ATAPI Device Register Read Data */ -#define ATAPI_INT_MASK 0xFFC03814 /* ATAPI Interrupt Mask Register */ -#define ATAPI_INT_STATUS 0xFFC03818 /* ATAPI Interrupt Status Register */ -#define ATAPI_XFER_LEN 0xFFC0381C /* ATAPI Length of Transfer */ -#define ATAPI_LINE_STATUS 0xFFC03820 /* ATAPI Line Status */ -#define ATAPI_SM_STATE 0xFFC03824 /* ATAPI State Machine Status */ -#define ATAPI_TERMINATE 0xFFC03828 /* ATAPI Host Terminate */ -#define ATAPI_PIO_TFRCNT 0xFFC0382C /* ATAPI PIO mode transfer count */ -#define ATAPI_DMA_TFRCNT 0xFFC03830 /* ATAPI DMA mode transfer count */ -#define ATAPI_UMAIN_TFRCNT 0xFFC03834 /* ATAPI UDMAIN transfer count */ -#define ATAPI_UDMAOUT_TFRCNT 0xFFC03838 /* ATAPI UDMAOUT transfer count */ -#define ATAPI_REG_TIM_0 0xFFC03840 /* ATAPI Register Transfer Timing 0 */ -#define ATAPI_PIO_TIM_0 0xFFC03844 /* ATAPI PIO Timing 0 Register */ -#define ATAPI_PIO_TIM_1 0xFFC03848 /* ATAPI PIO Timing 1 Register */ -#define ATAPI_MULTI_TIM_0 0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */ -#define ATAPI_MULTI_TIM_1 0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */ -#define ATAPI_MULTI_TIM_2 0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_0 0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */ -#define ATAPI_ULTRA_TIM_1 0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */ -#define ATAPI_ULTRA_TIM_2 0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_3 0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */ -#define NFC_CTL 0xFFC03B00 /* NAND Control Register */ -#define NFC_STAT 0xFFC03B04 /* NAND Status Register */ -#define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */ -#define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */ -#define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */ -#define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */ -#define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */ -#define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */ -#define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */ -#define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */ -#define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */ -#define NFC_READ 0xFFC03B2C /* NAND Read Data Register */ -#define NFC_ADDR 0xFFC03B40 /* NAND Address Register */ -#define NFC_CMD 0xFFC03B44 /* NAND Command Register */ -#define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */ -#define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */ -#define EPPI0_STATUS 0xFFC01000 /* EPPI0 Status Register */ -#define EPPI0_HCOUNT 0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */ -#define EPPI0_HDELAY 0xFFC01008 /* EPPI0 Horizontal Delay Count Register */ -#define EPPI0_VCOUNT 0xFFC0100C /* EPPI0 Vertical Transfer Count Register */ -#define EPPI0_VDELAY 0xFFC01010 /* EPPI0 Vertical Delay Count Register */ -#define EPPI0_FRAME 0xFFC01014 /* EPPI0 Lines per Frame Register */ -#define EPPI0_LINE 0xFFC01018 /* EPPI0 Samples per Line Register */ -#define EPPI0_CLKDIV 0xFFC0101C /* EPPI0 Clock Divide Register */ -#define EPPI0_CONTROL 0xFFC01020 /* EPPI0 Control Register */ -#define EPPI0_FS1W_HBL 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define EPPI0_FS1P_AVPL 0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define EPPI0_FS2W_LVB 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define EPPI0_FS2P_LAVF 0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define EPPI0_CLIP 0xFFC01034 /* EPPI0 Clipping Register */ -#define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */ -#define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */ -#define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */ -#define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */ -#define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */ -#define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */ -#define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */ -#define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */ -#define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */ -#define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */ -#define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */ -#define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */ -#define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */ -#define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */ -#define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */ -#define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */ -#define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */ -#define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */ -#define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */ -#define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */ -#define CAN0_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */ -#define CAN0_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */ -#define CAN0_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */ -#define CAN0_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */ -#define CAN0_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ -#define CAN0_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */ -#define CAN0_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */ -#define CAN0_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */ -#define CAN0_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN0_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN0_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ -#define CAN0_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ -#define CAN0_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ -#define CAN0_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */ -#define CAN0_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */ -#define CAN0_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */ -#define CAN0_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */ -#define CAN0_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ -#define CAN0_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */ -#define CAN0_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */ -#define CAN0_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */ -#define CAN0_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN0_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN0_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ -#define CAN0_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ -#define CAN0_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ -#define CAN0_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */ -#define CAN0_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */ -#define CAN0_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */ -#define CAN0_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */ -#define CAN0_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */ -#define CAN0_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */ -#define CAN0_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */ -#define CAN0_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */ -#define CAN0_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */ -#define CAN0_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */ -#define CAN0_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */ -#define CAN0_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */ -#define CAN0_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */ -#define CAN0_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */ -#define CAN0_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */ -#define CAN0_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */ -#define CAN0_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ -#define CAN0_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ -#define CAN0_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ -#define CAN0_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ -#define CAN0_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ -#define CAN0_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ -#define CAN0_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ -#define CAN0_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ -#define CAN0_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ -#define CAN0_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ -#define CAN0_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ -#define CAN0_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ -#define CAN0_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ -#define CAN0_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ -#define CAN0_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ -#define CAN0_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ -#define CAN0_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ -#define CAN0_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ -#define CAN0_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ -#define CAN0_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ -#define CAN0_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ -#define CAN0_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ -#define CAN0_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ -#define CAN0_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ -#define CAN0_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ -#define CAN0_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ -#define CAN0_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ -#define CAN0_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ -#define CAN0_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ -#define CAN0_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ -#define CAN0_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ -#define CAN0_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ -#define CAN0_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ -#define CAN0_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ -#define CAN0_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ -#define CAN0_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ -#define CAN0_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ -#define CAN0_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ -#define CAN0_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ -#define CAN0_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ -#define CAN0_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ -#define CAN0_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ -#define CAN0_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ -#define CAN0_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ -#define CAN0_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ -#define CAN0_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ -#define CAN0_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ -#define CAN0_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ -#define CAN0_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ -#define CAN0_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ -#define CAN0_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ -#define CAN0_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ -#define CAN0_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ -#define CAN0_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ -#define CAN0_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ -#define CAN0_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ -#define CAN0_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ -#define CAN0_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ -#define CAN0_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ -#define CAN0_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ -#define CAN0_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ -#define CAN0_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ -#define CAN0_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ -#define CAN0_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ -#define CAN0_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ -#define CAN0_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ -#define CAN0_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ -#define CAN0_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */ -#define CAN0_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */ -#define CAN0_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ -#define CAN0_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */ -#define CAN0_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */ -#define CAN0_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ -#define CAN0_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ -#define CAN0_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ -#define CAN0_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */ -#define CAN0_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */ -#define CAN0_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ -#define CAN0_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */ -#define CAN0_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */ -#define CAN0_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ -#define CAN0_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ -#define CAN0_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ -#define CAN0_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */ -#define CAN0_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */ -#define CAN0_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ -#define CAN0_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */ -#define CAN0_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */ -#define CAN0_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ -#define CAN0_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ -#define CAN0_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ -#define CAN0_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */ -#define CAN0_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */ -#define CAN0_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ -#define CAN0_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */ -#define CAN0_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */ -#define CAN0_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ -#define CAN0_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ -#define CAN0_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ -#define CAN0_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */ -#define CAN0_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */ -#define CAN0_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ -#define CAN0_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */ -#define CAN0_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */ -#define CAN0_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ -#define CAN0_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ -#define CAN0_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ -#define CAN0_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */ -#define CAN0_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */ -#define CAN0_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ -#define CAN0_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */ -#define CAN0_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */ -#define CAN0_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ -#define CAN0_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ -#define CAN0_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ -#define CAN0_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */ -#define CAN0_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */ -#define CAN0_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ -#define CAN0_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */ -#define CAN0_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */ -#define CAN0_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ -#define CAN0_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ -#define CAN0_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ -#define CAN0_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */ -#define CAN0_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */ -#define CAN0_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ -#define CAN0_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */ -#define CAN0_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */ -#define CAN0_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ -#define CAN0_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ -#define CAN0_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ -#define CAN0_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */ -#define CAN0_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */ -#define CAN0_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ -#define CAN0_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */ -#define CAN0_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */ -#define CAN0_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ -#define CAN0_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ -#define CAN0_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ -#define CAN0_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */ -#define CAN0_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */ -#define CAN0_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ -#define CAN0_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */ -#define CAN0_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */ -#define CAN0_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ -#define CAN0_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ -#define CAN0_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ -#define CAN0_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */ -#define CAN0_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */ -#define CAN0_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ -#define CAN0_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */ -#define CAN0_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */ -#define CAN0_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ -#define CAN0_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ -#define CAN0_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ -#define CAN0_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */ -#define CAN0_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */ -#define CAN0_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ -#define CAN0_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */ -#define CAN0_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */ -#define CAN0_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ -#define CAN0_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ -#define CAN0_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ -#define CAN0_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */ -#define CAN0_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */ -#define CAN0_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ -#define CAN0_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */ -#define CAN0_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */ -#define CAN0_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ -#define CAN0_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ -#define CAN0_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ -#define CAN0_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */ -#define CAN0_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */ -#define CAN0_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ -#define CAN0_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */ -#define CAN0_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */ -#define CAN0_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ -#define CAN0_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ -#define CAN0_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ -#define CAN0_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */ -#define CAN0_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */ -#define CAN0_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ -#define CAN0_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */ -#define CAN0_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */ -#define CAN0_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ -#define CAN0_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ -#define CAN0_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ -#define CAN0_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */ -#define CAN0_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */ -#define CAN0_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ -#define CAN0_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */ -#define CAN0_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */ -#define CAN0_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ -#define CAN0_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ -#define CAN0_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ -#define CAN0_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */ -#define CAN0_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */ -#define CAN0_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ -#define CAN0_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */ -#define CAN0_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */ -#define CAN0_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ -#define CAN0_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ -#define CAN0_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ -#define CAN0_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */ -#define CAN0_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */ -#define CAN0_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ -#define CAN0_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */ -#define CAN0_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */ -#define CAN0_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ -#define CAN0_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ -#define CAN0_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ -#define CAN0_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */ -#define CAN0_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */ -#define CAN0_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ -#define CAN0_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */ -#define CAN0_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */ -#define CAN0_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ -#define CAN0_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ -#define CAN0_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ -#define CAN0_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */ -#define CAN0_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */ -#define CAN0_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ -#define CAN0_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */ -#define CAN0_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */ -#define CAN0_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ -#define CAN0_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ -#define CAN0_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ -#define CAN0_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */ -#define CAN0_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */ -#define CAN0_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ -#define CAN0_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */ -#define CAN0_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */ -#define CAN0_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ -#define CAN0_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ -#define CAN0_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ -#define CAN0_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */ -#define CAN0_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */ -#define CAN0_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ -#define CAN0_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */ -#define CAN0_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */ -#define CAN0_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ -#define CAN0_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ -#define CAN0_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ -#define CAN0_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */ -#define CAN0_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */ -#define CAN0_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ -#define CAN0_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */ -#define CAN0_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */ -#define CAN0_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ -#define CAN0_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ -#define CAN0_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ -#define CAN0_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */ -#define CAN0_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */ -#define CAN0_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ -#define CAN0_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */ -#define CAN0_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */ -#define CAN0_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ -#define CAN0_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ -#define CAN0_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ -#define CAN0_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */ -#define CAN0_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */ -#define CAN0_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ -#define CAN0_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */ -#define CAN0_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */ -#define CAN0_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ -#define CAN0_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ -#define CAN0_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ -#define CAN0_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */ -#define CAN0_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */ -#define CAN0_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ -#define CAN0_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */ -#define CAN0_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */ -#define CAN0_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ -#define CAN0_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ -#define CAN0_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ -#define CAN0_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */ -#define CAN0_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */ -#define CAN0_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ -#define CAN0_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */ -#define CAN0_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */ -#define CAN0_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ -#define CAN0_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ -#define CAN0_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ -#define CAN0_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */ -#define CAN0_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */ -#define CAN0_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ -#define CAN0_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */ -#define CAN0_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */ -#define CAN0_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ -#define CAN0_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ -#define CAN0_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ -#define CAN0_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */ -#define CAN0_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */ -#define CAN0_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ -#define CAN0_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */ -#define CAN0_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */ -#define CAN0_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ -#define CAN0_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ -#define CAN0_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ -#define CAN0_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */ -#define CAN0_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */ -#define CAN0_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ -#define CAN0_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */ -#define CAN0_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */ -#define CAN0_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ -#define CAN0_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ -#define CAN0_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ -#define CAN0_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */ -#define CAN0_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */ -#define CAN0_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ -#define CAN0_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */ -#define CAN0_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */ -#define CAN0_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ -#define CAN0_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ -#define CAN0_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ -#define CAN0_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */ -#define CAN0_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */ -#define CAN0_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ -#define CAN0_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */ -#define CAN0_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */ -#define CAN1_MC1 0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ -#define CAN1_MD1 0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */ -#define CAN1_TRS1 0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */ -#define CAN1_TRR1 0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */ -#define CAN1_TA1 0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ -#define CAN1_AA1 0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ -#define CAN1_RMP1 0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */ -#define CAN1_RML1 0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */ -#define CAN1_MBTIF1 0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN1_MBRIF1 0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN1_MBIM1 0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ -#define CAN1_RFH1 0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ -#define CAN1_OPSS1 0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ -#define CAN1_MC2 0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ -#define CAN1_MD2 0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */ -#define CAN1_TRS2 0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */ -#define CAN1_TRR2 0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */ -#define CAN1_TA2 0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ -#define CAN1_AA2 0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ -#define CAN1_RMP2 0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */ -#define CAN1_RML2 0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */ -#define CAN1_MBTIF2 0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN1_MBRIF2 0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN1_MBIM2 0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ -#define CAN1_RFH2 0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ -#define CAN1_OPSS2 0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ -#define CAN1_CLOCK 0xFFC03280 /* CAN Controller 1 Clock Register */ -#define CAN1_TIMING 0xFFC03284 /* CAN Controller 1 Timing Register */ -#define CAN1_DEBUG 0xFFC03288 /* CAN Controller 1 Debug Register */ -#define CAN1_STATUS 0xFFC0328C /* CAN Controller 1 Global Status Register */ -#define CAN1_CEC 0xFFC03290 /* CAN Controller 1 Error Counter Register */ -#define CAN1_GIS 0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */ -#define CAN1_GIM 0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */ -#define CAN1_GIF 0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */ -#define CAN1_CONTROL 0xFFC032A0 /* CAN Controller 1 Master Control Register */ -#define CAN1_INTR 0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */ -#define CAN1_MBTD 0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */ -#define CAN1_EWR 0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */ -#define CAN1_ESR 0xFFC032B4 /* CAN Controller 1 Error Status Register */ -#define CAN1_UCCNT 0xFFC032C4 /* CAN Controller 1 Universal Counter Register */ -#define CAN1_UCRC 0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */ -#define CAN1_UCCNF 0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */ -#define CAN1_AM00L 0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ -#define CAN1_AM00H 0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ -#define CAN1_AM01L 0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ -#define CAN1_AM01H 0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ -#define CAN1_AM02L 0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ -#define CAN1_AM02H 0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ -#define CAN1_AM03L 0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ -#define CAN1_AM03H 0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ -#define CAN1_AM04L 0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ -#define CAN1_AM04H 0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ -#define CAN1_AM05L 0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ -#define CAN1_AM05H 0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ -#define CAN1_AM06L 0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ -#define CAN1_AM06H 0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ -#define CAN1_AM07L 0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ -#define CAN1_AM07H 0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ -#define CAN1_AM08L 0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ -#define CAN1_AM08H 0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ -#define CAN1_AM09L 0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ -#define CAN1_AM09H 0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ -#define CAN1_AM10L 0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ -#define CAN1_AM10H 0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ -#define CAN1_AM11L 0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ -#define CAN1_AM11H 0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ -#define CAN1_AM12L 0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ -#define CAN1_AM12H 0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ -#define CAN1_AM13L 0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ -#define CAN1_AM13H 0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ -#define CAN1_AM14L 0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ -#define CAN1_AM14H 0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ -#define CAN1_AM15L 0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ -#define CAN1_AM15H 0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ -#define CAN1_AM16L 0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ -#define CAN1_AM16H 0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ -#define CAN1_AM17L 0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ -#define CAN1_AM17H 0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ -#define CAN1_AM18L 0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ -#define CAN1_AM18H 0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ -#define CAN1_AM19L 0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ -#define CAN1_AM19H 0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ -#define CAN1_AM20L 0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ -#define CAN1_AM20H 0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ -#define CAN1_AM21L 0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ -#define CAN1_AM21H 0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ -#define CAN1_AM22L 0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ -#define CAN1_AM22H 0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ -#define CAN1_AM23L 0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ -#define CAN1_AM23H 0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ -#define CAN1_AM24L 0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ -#define CAN1_AM24H 0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ -#define CAN1_AM25L 0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ -#define CAN1_AM25H 0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ -#define CAN1_AM26L 0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ -#define CAN1_AM26H 0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ -#define CAN1_AM27L 0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ -#define CAN1_AM27H 0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ -#define CAN1_AM28L 0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ -#define CAN1_AM28H 0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ -#define CAN1_AM29L 0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ -#define CAN1_AM29H 0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ -#define CAN1_AM30L 0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ -#define CAN1_AM30H 0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ -#define CAN1_AM31L 0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ -#define CAN1_AM31H 0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ -#define CAN1_MB00_DATA0 0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ -#define CAN1_MB00_DATA1 0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ -#define CAN1_MB00_DATA2 0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ -#define CAN1_MB00_DATA3 0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */ -#define CAN1_MB00_LENGTH 0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */ -#define CAN1_MB00_TIMESTAMP 0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ -#define CAN1_MB00_ID0 0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ -#define CAN1_MB00_ID1 0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */ -#define CAN1_MB01_DATA0 0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ -#define CAN1_MB01_DATA1 0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ -#define CAN1_MB01_DATA2 0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ -#define CAN1_MB01_DATA3 0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */ -#define CAN1_MB01_LENGTH 0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */ -#define CAN1_MB01_TIMESTAMP 0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ -#define CAN1_MB01_ID0 0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ -#define CAN1_MB01_ID1 0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */ -#define CAN1_MB02_DATA0 0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ -#define CAN1_MB02_DATA1 0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ -#define CAN1_MB02_DATA2 0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ -#define CAN1_MB02_DATA3 0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */ -#define CAN1_MB02_LENGTH 0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */ -#define CAN1_MB02_TIMESTAMP 0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ -#define CAN1_MB02_ID0 0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ -#define CAN1_MB02_ID1 0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */ -#define CAN1_MB03_DATA0 0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ -#define CAN1_MB03_DATA1 0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ -#define CAN1_MB03_DATA2 0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ -#define CAN1_MB03_DATA3 0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */ -#define CAN1_MB03_LENGTH 0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */ -#define CAN1_MB03_TIMESTAMP 0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ -#define CAN1_MB03_ID0 0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ -#define CAN1_MB03_ID1 0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */ -#define CAN1_MB04_DATA0 0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ -#define CAN1_MB04_DATA1 0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ -#define CAN1_MB04_DATA2 0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ -#define CAN1_MB04_DATA3 0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */ -#define CAN1_MB04_LENGTH 0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */ -#define CAN1_MB04_TIMESTAMP 0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ -#define CAN1_MB04_ID0 0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ -#define CAN1_MB04_ID1 0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */ -#define CAN1_MB05_DATA0 0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ -#define CAN1_MB05_DATA1 0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ -#define CAN1_MB05_DATA2 0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ -#define CAN1_MB05_DATA3 0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */ -#define CAN1_MB05_LENGTH 0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */ -#define CAN1_MB05_TIMESTAMP 0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ -#define CAN1_MB05_ID0 0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */ -#define CAN1_MB05_ID1 0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */ -#define CAN1_MB06_DATA0 0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ -#define CAN1_MB06_DATA1 0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ -#define CAN1_MB06_DATA2 0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ -#define CAN1_MB06_DATA3 0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */ -#define CAN1_MB06_LENGTH 0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */ -#define CAN1_MB06_TIMESTAMP 0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ -#define CAN1_MB06_ID0 0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */ -#define CAN1_MB06_ID1 0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */ -#define CAN1_MB07_DATA0 0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ -#define CAN1_MB07_DATA1 0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ -#define CAN1_MB07_DATA2 0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ -#define CAN1_MB07_DATA3 0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */ -#define CAN1_MB07_LENGTH 0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */ -#define CAN1_MB07_TIMESTAMP 0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ -#define CAN1_MB07_ID0 0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */ -#define CAN1_MB07_ID1 0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */ -#define CAN1_MB08_DATA0 0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ -#define CAN1_MB08_DATA1 0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ -#define CAN1_MB08_DATA2 0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ -#define CAN1_MB08_DATA3 0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */ -#define CAN1_MB08_LENGTH 0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */ -#define CAN1_MB08_TIMESTAMP 0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ -#define CAN1_MB08_ID0 0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ -#define CAN1_MB08_ID1 0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */ -#define CAN1_MB09_DATA0 0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ -#define CAN1_MB09_DATA1 0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ -#define CAN1_MB09_DATA2 0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ -#define CAN1_MB09_DATA3 0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */ -#define CAN1_MB09_LENGTH 0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */ -#define CAN1_MB09_TIMESTAMP 0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ -#define CAN1_MB09_ID0 0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ -#define CAN1_MB09_ID1 0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */ -#define CAN1_MB10_DATA0 0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ -#define CAN1_MB10_DATA1 0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ -#define CAN1_MB10_DATA2 0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ -#define CAN1_MB10_DATA3 0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */ -#define CAN1_MB10_LENGTH 0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */ -#define CAN1_MB10_TIMESTAMP 0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ -#define CAN1_MB10_ID0 0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ -#define CAN1_MB10_ID1 0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */ -#define CAN1_MB11_DATA0 0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ -#define CAN1_MB11_DATA1 0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ -#define CAN1_MB11_DATA2 0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ -#define CAN1_MB11_DATA3 0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */ -#define CAN1_MB11_LENGTH 0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */ -#define CAN1_MB11_TIMESTAMP 0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ -#define CAN1_MB11_ID0 0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ -#define CAN1_MB11_ID1 0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */ -#define CAN1_MB12_DATA0 0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ -#define CAN1_MB12_DATA1 0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ -#define CAN1_MB12_DATA2 0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ -#define CAN1_MB12_DATA3 0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */ -#define CAN1_MB12_LENGTH 0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */ -#define CAN1_MB12_TIMESTAMP 0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ -#define CAN1_MB12_ID0 0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ -#define CAN1_MB12_ID1 0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */ -#define CAN1_MB13_DATA0 0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ -#define CAN1_MB13_DATA1 0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ -#define CAN1_MB13_DATA2 0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ -#define CAN1_MB13_DATA3 0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */ -#define CAN1_MB13_LENGTH 0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */ -#define CAN1_MB13_TIMESTAMP 0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ -#define CAN1_MB13_ID0 0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */ -#define CAN1_MB13_ID1 0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */ -#define CAN1_MB14_DATA0 0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ -#define CAN1_MB14_DATA1 0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ -#define CAN1_MB14_DATA2 0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ -#define CAN1_MB14_DATA3 0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */ -#define CAN1_MB14_LENGTH 0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */ -#define CAN1_MB14_TIMESTAMP 0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ -#define CAN1_MB14_ID0 0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */ -#define CAN1_MB14_ID1 0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */ -#define CAN1_MB15_DATA0 0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ -#define CAN1_MB15_DATA1 0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ -#define CAN1_MB15_DATA2 0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ -#define CAN1_MB15_DATA3 0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */ -#define CAN1_MB15_LENGTH 0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */ -#define CAN1_MB15_TIMESTAMP 0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ -#define CAN1_MB15_ID0 0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */ -#define CAN1_MB15_ID1 0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */ -#define CAN1_MB16_DATA0 0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ -#define CAN1_MB16_DATA1 0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ -#define CAN1_MB16_DATA2 0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ -#define CAN1_MB16_DATA3 0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */ -#define CAN1_MB16_LENGTH 0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */ -#define CAN1_MB16_TIMESTAMP 0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ -#define CAN1_MB16_ID0 0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ -#define CAN1_MB16_ID1 0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */ -#define CAN1_MB17_DATA0 0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ -#define CAN1_MB17_DATA1 0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ -#define CAN1_MB17_DATA2 0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ -#define CAN1_MB17_DATA3 0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */ -#define CAN1_MB17_LENGTH 0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */ -#define CAN1_MB17_TIMESTAMP 0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ -#define CAN1_MB17_ID0 0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ -#define CAN1_MB17_ID1 0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */ -#define CAN1_MB18_DATA0 0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ -#define CAN1_MB18_DATA1 0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ -#define CAN1_MB18_DATA2 0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ -#define CAN1_MB18_DATA3 0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */ -#define CAN1_MB18_LENGTH 0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */ -#define CAN1_MB18_TIMESTAMP 0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ -#define CAN1_MB18_ID0 0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ -#define CAN1_MB18_ID1 0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */ -#define CAN1_MB19_DATA0 0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ -#define CAN1_MB19_DATA1 0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ -#define CAN1_MB19_DATA2 0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ -#define CAN1_MB19_DATA3 0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */ -#define CAN1_MB19_LENGTH 0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */ -#define CAN1_MB19_TIMESTAMP 0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ -#define CAN1_MB19_ID0 0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ -#define CAN1_MB19_ID1 0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */ -#define CAN1_MB20_DATA0 0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ -#define CAN1_MB20_DATA1 0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ -#define CAN1_MB20_DATA2 0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ -#define CAN1_MB20_DATA3 0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */ -#define CAN1_MB20_LENGTH 0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */ -#define CAN1_MB20_TIMESTAMP 0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ -#define CAN1_MB20_ID0 0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ -#define CAN1_MB20_ID1 0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */ -#define CAN1_MB21_DATA0 0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ -#define CAN1_MB21_DATA1 0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ -#define CAN1_MB21_DATA2 0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ -#define CAN1_MB21_DATA3 0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */ -#define CAN1_MB21_LENGTH 0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */ -#define CAN1_MB21_TIMESTAMP 0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ -#define CAN1_MB21_ID0 0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */ -#define CAN1_MB21_ID1 0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */ -#define CAN1_MB22_DATA0 0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ -#define CAN1_MB22_DATA1 0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ -#define CAN1_MB22_DATA2 0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ -#define CAN1_MB22_DATA3 0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */ -#define CAN1_MB22_LENGTH 0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */ -#define CAN1_MB22_TIMESTAMP 0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ -#define CAN1_MB22_ID0 0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */ -#define CAN1_MB22_ID1 0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */ -#define CAN1_MB23_DATA0 0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ -#define CAN1_MB23_DATA1 0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ -#define CAN1_MB23_DATA2 0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ -#define CAN1_MB23_DATA3 0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */ -#define CAN1_MB23_LENGTH 0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */ -#define CAN1_MB23_TIMESTAMP 0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ -#define CAN1_MB23_ID0 0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */ -#define CAN1_MB23_ID1 0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */ -#define CAN1_MB24_DATA0 0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ -#define CAN1_MB24_DATA1 0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ -#define CAN1_MB24_DATA2 0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ -#define CAN1_MB24_DATA3 0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */ -#define CAN1_MB24_LENGTH 0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */ -#define CAN1_MB24_TIMESTAMP 0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ -#define CAN1_MB24_ID0 0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ -#define CAN1_MB24_ID1 0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */ -#define CAN1_MB25_DATA0 0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ -#define CAN1_MB25_DATA1 0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ -#define CAN1_MB25_DATA2 0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ -#define CAN1_MB25_DATA3 0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */ -#define CAN1_MB25_LENGTH 0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */ -#define CAN1_MB25_TIMESTAMP 0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ -#define CAN1_MB25_ID0 0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ -#define CAN1_MB25_ID1 0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */ -#define CAN1_MB26_DATA0 0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ -#define CAN1_MB26_DATA1 0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ -#define CAN1_MB26_DATA2 0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ -#define CAN1_MB26_DATA3 0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */ -#define CAN1_MB26_LENGTH 0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */ -#define CAN1_MB26_TIMESTAMP 0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ -#define CAN1_MB26_ID0 0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ -#define CAN1_MB26_ID1 0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */ -#define CAN1_MB27_DATA0 0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ -#define CAN1_MB27_DATA1 0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ -#define CAN1_MB27_DATA2 0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ -#define CAN1_MB27_DATA3 0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */ -#define CAN1_MB27_LENGTH 0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */ -#define CAN1_MB27_TIMESTAMP 0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ -#define CAN1_MB27_ID0 0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ -#define CAN1_MB27_ID1 0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */ -#define CAN1_MB28_DATA0 0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ -#define CAN1_MB28_DATA1 0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ -#define CAN1_MB28_DATA2 0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ -#define CAN1_MB28_DATA3 0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */ -#define CAN1_MB28_LENGTH 0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */ -#define CAN1_MB28_TIMESTAMP 0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ -#define CAN1_MB28_ID0 0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ -#define CAN1_MB28_ID1 0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */ -#define CAN1_MB29_DATA0 0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ -#define CAN1_MB29_DATA1 0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ -#define CAN1_MB29_DATA2 0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ -#define CAN1_MB29_DATA3 0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */ -#define CAN1_MB29_LENGTH 0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */ -#define CAN1_MB29_TIMESTAMP 0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ -#define CAN1_MB29_ID0 0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */ -#define CAN1_MB29_ID1 0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */ -#define CAN1_MB30_DATA0 0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ -#define CAN1_MB30_DATA1 0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ -#define CAN1_MB30_DATA2 0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ -#define CAN1_MB30_DATA3 0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */ -#define CAN1_MB30_LENGTH 0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */ -#define CAN1_MB30_TIMESTAMP 0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ -#define CAN1_MB30_ID0 0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */ -#define CAN1_MB30_ID1 0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */ -#define CAN1_MB31_DATA0 0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ -#define CAN1_MB31_DATA1 0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ -#define CAN1_MB31_DATA2 0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ -#define CAN1_MB31_DATA3 0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */ -#define CAN1_MB31_LENGTH 0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */ -#define CAN1_MB31_TIMESTAMP 0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ -#define CAN1_MB31_ID0 0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */ -#define CAN1_MB31_ID1 0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */ -#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ -#define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */ -#define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */ -#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ -#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ -#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */ -#define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */ -#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ -#define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */ -#define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */ -#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ -#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ -#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */ -#define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */ -#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ -#define SPI2_FLG 0xFFC02404 /* SPI2 Flag Register */ -#define SPI2_STAT 0xFFC02408 /* SPI2 Status Register */ -#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ -#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ -#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud Rate Register */ -#define SPI2_SHADOW 0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */ -#define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */ -#define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */ -#define TWI1_CLKDIV 0xFFC02200 /* Clock Divider Register */ -#define TWI1_CONTROL 0xFFC02204 /* TWI Control Register */ -#define TWI1_SLAVE_CTL 0xFFC02208 /* TWI Slave Mode Control Register */ -#define TWI1_SLAVE_STAT 0xFFC0220C /* TWI Slave Mode Status Register */ -#define TWI1_SLAVE_ADDR 0xFFC02210 /* TWI Slave Mode Address Register */ -#define TWI1_MASTER_CTL 0xFFC02214 /* TWI Master Mode Control Register */ -#define TWI1_MASTER_STAT 0xFFC02218 /* TWI Master Mode Status Register */ -#define TWI1_MASTER_ADDR 0xFFC0221C /* TWI Master Mode Address Register */ -#define TWI1_INT_STAT 0xFFC02220 /* TWI Interrupt Status Register */ -#define TWI1_INT_MASK 0xFFC02224 /* TWI Interrupt Mask Register */ -#define TWI1_FIFO_CTL 0xFFC02228 /* TWI FIFO Control Register */ -#define TWI1_FIFO_STAT 0xFFC0222C /* TWI FIFO Status Register */ -#define TWI1_XMT_DATA8 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI1_XMT_DATA16 0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI1_RCV_DATA8 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI1_RCV_DATA16 0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 Transmit Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Receive Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Receive Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 Receive Data Register */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */ -#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ -#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ -#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */ -#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */ -#define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */ -#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */ -#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */ -#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */ -#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */ -#define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */ -#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ -#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */ -#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */ -#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ -#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */ -#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */ -#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */ -#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */ -#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */ -#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */ -#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */ -#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */ -#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ -#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ -#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */ -#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */ -#define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */ -#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */ -#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */ -#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */ -#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */ -#define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */ -#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ -#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */ -#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */ -#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ -#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */ -#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */ -#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */ -#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */ -#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */ -#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */ -#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */ -#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */ -#define UART0_GCTL 0xFFC00408 /* Global Control Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* Scratch Register */ -#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */ -#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */ -#define UART0_THR 0xFFC00428 /* Transmit Hold Register */ -#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */ -#define UART1_GCTL 0xFFC02008 /* Global Control Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* Scratch Register */ -#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */ -#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */ -#define UART1_THR 0xFFC02028 /* Transmit Hold Register */ -#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */ -#define UART2_DLL 0xFFC02100 /* Divisor Latch Low Byte */ -#define UART2_DLH 0xFFC02104 /* Divisor Latch High Byte */ -#define UART2_GCTL 0xFFC02108 /* Global Control Register */ -#define UART2_LCR 0xFFC0210C /* Line Control Register */ -#define UART2_MCR 0xFFC02110 /* Modem Control Register */ -#define UART2_LSR 0xFFC02114 /* Line Status Register */ -#define UART2_MSR 0xFFC02118 /* Modem Status Register */ -#define UART2_SCR 0xFFC0211C /* Scratch Register */ -#define UART2_IER_SET 0xFFC02120 /* Interrupt Enable Register Set */ -#define UART2_IER_CLEAR 0xFFC02124 /* Interrupt Enable Register Clear */ -#define UART2_THR 0xFFC02128 /* Transmit Hold Register */ -#define UART2_RBR 0xFFC0212C /* Receive Buffer Register */ -#define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */ -#define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */ -#define UART3_GCTL 0xFFC03108 /* Global Control Register */ -#define UART3_LCR 0xFFC0310C /* Line Control Register */ -#define UART3_MCR 0xFFC03110 /* Modem Control Register */ -#define UART3_LSR 0xFFC03114 /* Line Status Register */ -#define UART3_MSR 0xFFC03118 /* Modem Status Register */ -#define UART3_SCR 0xFFC0311C /* Scratch Register */ -#define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */ -#define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */ -#define UART3_THR 0xFFC03128 /* Transmit Hold Register */ -#define UART3_RBR 0xFFC0312C /* Receive Buffer Register */ -#define USB_FADDR 0xFFC03C00 /* Function address register */ -#define USB_POWER 0xFFC03C04 /* Power management register */ -#define USB_INTRTX 0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03C10 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03C14 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03C18 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC03C1C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03C20 /* USB frame number */ -#define USB_INDEX 0xFFC03C24 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03C28 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03C30 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03C40 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03C48 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC03C4C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03C80 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03C88 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03C90 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03C98 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC03CA0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC03CA8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC03CB0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC03CB8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03D00 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03D04 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03D08 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03D48 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03D50 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03D54 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03D58 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC03DE0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC03DE4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03E04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03E0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03E44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03E4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03E84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03E8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03EC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ECC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03F04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03F0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03F44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03F4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03F84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03F8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03FC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03FCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC04000 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC04004 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC04024 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC04044 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC04064 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC04084 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC040A4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC040C4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC040E4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -#endif /* __BFIN_DEF_ADSP_EDN_BF548_extended__ */ diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h deleted file mode 100644 index af90e4c..0000000 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h +++ /dev/null @@ -1,6135 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_BF549_extended__ -#define __BFIN_CDEF_ADSP_EDN_BF549_extended__ - -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */ -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */ -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */ -#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) -#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */ -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */ -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */ -#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) -#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */ -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */ -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */ -#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) -#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */ -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */ -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */ -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */ -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */ -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */ -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */ -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */ -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */ -#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) -#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */ -#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) -#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */ -#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) -#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */ -#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) -#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) -#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */ -#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) -#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) -#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */ -#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) -#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) -#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */ -#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) -#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) -#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */ -#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) -#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) -#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */ -#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) -#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ -#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ -#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ -#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ -#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ -#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ -#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ -#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ -#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ -#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ -#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ -#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ -#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ -#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ -#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ -#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ -#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ -#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ -#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ -#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ -#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ -#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ -#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ -#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ -#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */ -#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) -#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */ -#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) -#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */ -#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) -#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */ -#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) -#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */ -#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) -#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */ -#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) -#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */ -#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) -#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */ -#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) -#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */ -#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) -#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */ -#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) -#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */ -#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) -#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */ -#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) -#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */ -#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) -#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */ -#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) -#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */ -#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) -#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */ -#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) -#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */ -#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) -#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */ -#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) -#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */ -#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) -#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */ -#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) -#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */ -#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) -#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */ -#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) -#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */ -#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) -#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */ -#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) -#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */ -#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) -#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */ -#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) -#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */ -#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) -#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */ -#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) -#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */ -#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) -#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */ -#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) -#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */ -#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) -#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */ -#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) -#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */ -#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) -#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */ -#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) -#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */ -#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) -#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */ -#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) -#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */ -#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) -#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */ -#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) -#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */ -#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) -#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */ -#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) -#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */ -#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) -#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */ -#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) -#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */ -#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) -#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */ -#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) -#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */ -#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) -#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */ -#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) -#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */ -#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) -#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */ -#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) -#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */ -#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) -#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */ -#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) -#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */ -#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) -#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */ -#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) -#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */ -#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) -#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */ -#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) -#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */ -#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) -#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */ -#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) -#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */ -#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) -#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */ -#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) -#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */ -#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) -#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */ -#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) -#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */ -#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) -#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */ -#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) -#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */ -#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) -#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */ -#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) -#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */ -#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) -#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */ -#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) -#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */ -#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) -#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */ -#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) -#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */ -#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) -#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */ -#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) -#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */ -#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) -#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */ -#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) -#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */ -#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) -#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */ -#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) -#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */ -#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) -#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */ -#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) -#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */ -#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) -#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */ -#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) -#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */ -#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) -#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */ -#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) -#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */ -#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) -#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */ -#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) -#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */ -#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) -#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */ -#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) -#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */ -#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) -#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */ -#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) -#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */ -#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) -#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */ -#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) -#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */ -#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) -#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */ -#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) -#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */ -#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) -#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */ -#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) -#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */ -#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) -#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */ -#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) -#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */ -#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) -#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */ -#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) -#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */ -#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) -#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */ -#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) -#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */ -#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) -#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */ -#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) -#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */ -#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) -#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */ -#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) -#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */ -#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) -#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */ -#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) -#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */ -#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR) -#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val) -#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */ -#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR) -#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val) -#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */ -#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) -#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */ -#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) -#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */ -#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) -#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */ -#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) -#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */ -#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) -#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */ -#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR) -#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val) -#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */ -#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR) -#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val) -#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */ -#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) -#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */ -#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) -#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */ -#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) -#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */ -#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) -#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) -#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */ -#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR) -#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val) -#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */ -#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR) -#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val) -#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */ -#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) -#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */ -#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) -#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */ -#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) -#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */ -#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) -#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */ -#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) -#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */ -#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR) -#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val) -#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */ -#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR) -#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val) -#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */ -#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) -#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */ -#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) -#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */ -#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) -#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */ -#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) -#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) -#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */ -#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR) -#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val) -#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */ -#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR) -#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val) -#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */ -#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) -#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */ -#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) -#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */ -#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) -#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */ -#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) -#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */ -#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) -#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */ -#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR) -#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val) -#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */ -#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR) -#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val) -#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */ -#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) -#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */ -#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) -#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */ -#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) -#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */ -#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) -#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) -#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */ -#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR) -#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val) -#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */ -#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR) -#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val) -#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */ -#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) -#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */ -#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) -#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */ -#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) -#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */ -#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) -#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */ -#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) -#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */ -#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR) -#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val) -#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */ -#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR) -#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val) -#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */ -#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) -#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */ -#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) -#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */ -#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) -#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */ -#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) -#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */ -#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */ -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */ -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */ -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */ -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */ -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */ -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */ -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */ -#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */ -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */ -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */ -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */ -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */ -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */ -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */ -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */ -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */ -#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */ -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */ -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */ -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */ -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */ -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */ -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */ -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */ -#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */ -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */ -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */ -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */ -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */ -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */ -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */ -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */ -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) -#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */ -#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) -#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */ -#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) -#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */ -#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) -#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */ -#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) -#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */ -#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) -#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */ -#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) -#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) -#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */ -#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) -#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) -#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) -#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */ -#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) -#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) -#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) -#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */ -#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) -#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */ -#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) -#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */ -#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) -#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */ -#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) -#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */ -#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) -#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */ -#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) -#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) -#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */ -#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) -#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) -#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) -#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */ -#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) -#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */ -#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) -#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) -#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */ -#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) -#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */ -#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) -#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */ -#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) -#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */ -#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) -#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */ -#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) -#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */ -#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) -#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) -#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */ -#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) -#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) -#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) -#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */ -#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) -#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) -#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) -#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */ -#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) -#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */ -#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) -#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */ -#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) -#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */ -#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) -#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */ -#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) -#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */ -#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) -#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) -#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */ -#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) -#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) -#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) -#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */ -#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) -#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */ -#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) -#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */ -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */ -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */ -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */ -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */ -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */ -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */ -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */ -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */ -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */ -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */ -#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL) -#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val) -#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */ -#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) -#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */ -#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) -#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */ -#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL) -#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val) -#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */ -#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) -#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */ -#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) -#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */ -#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) -#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */ -#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) -#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */ -#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) -#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */ -#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD) -#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val) -#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */ -#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) -#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */ -#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) -#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) -#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */ -#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) -#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */ -#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) -#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */ -#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) -#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */ -#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) -#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */ -#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) -#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */ -#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) -#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */ -#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) -#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */ -#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) -#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */ -#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) -#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */ -#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) -#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */ -#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) -#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */ -#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) -#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */ -#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) -#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */ -#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) -#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */ -#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) -#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */ -#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) -#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */ -#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) -#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */ -#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) -#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */ -#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) -#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */ -#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) -#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */ -#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) -#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */ -#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) -#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */ -#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) -#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */ -#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) -#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */ -#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) -#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) -#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) -#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) -#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */ -#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) -#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) -#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */ -#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) -#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) -#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) -#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) -#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) -#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) -#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) -#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) -#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */ -#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) -#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) -#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */ -#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) -#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) -#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) -#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) -#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) -#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) -#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) -#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) -#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */ -#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) -#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) -#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */ -#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) -#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) -#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */ -#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) -#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) -#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) -#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) -#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) -#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) -#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) -#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) -#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */ -#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) -#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) -#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */ -#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) -#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) -#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */ -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */ -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */ -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */ -#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) -#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */ -#define bfin_read_PORTA() bfin_read16(PORTA) -#define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) -#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) -#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) -#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) -#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) -#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) -#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */ -#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) -#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */ -#define bfin_read_PORTB() bfin_read16(PORTB) -#define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) -#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) -#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) -#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) -#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) -#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) -#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */ -#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) -#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */ -#define bfin_read_PORTC() bfin_read16(PORTC) -#define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) -#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) -#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) -#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) -#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) -#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) -#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */ -#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) -#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */ -#define bfin_read_PORTD() bfin_read16(PORTD) -#define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) -#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) -#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) -#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) -#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) -#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) -#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */ -#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) -#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */ -#define bfin_read_PORTE() bfin_read16(PORTE) -#define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) -#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) -#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) -#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) -#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) -#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) -#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */ -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */ -#define bfin_read_PORTF() bfin_read16(PORTF) -#define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) -#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) -#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) -#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) -#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) -#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */ -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */ -#define bfin_read_PORTG() bfin_read16(PORTG) -#define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) -#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) -#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) -#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) -#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) -#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */ -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */ -#define bfin_read_PORTH() bfin_read16(PORTH) -#define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) -#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) -#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) -#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) -#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) -#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) -#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */ -#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) -#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */ -#define bfin_read_PORTI() bfin_read16(PORTI) -#define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) -#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) -#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) -#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) -#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) -#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) -#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) -#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */ -#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) -#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */ -#define bfin_read_PORTJ() bfin_read16(PORTJ) -#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */ -#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) -#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */ -#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) -#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */ -#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) -#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */ -#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) -#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */ -#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) -#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */ -#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) -#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) -#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */ -#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) -#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */ -#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) -#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */ -#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ) -#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val) -#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */ -#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) -#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) -#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) -#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */ -#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) -#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */ -#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) -#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */ -#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) -#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */ -#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) -#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) -#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */ -#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) -#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */ -#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) -#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */ -#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ) -#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val) -#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */ -#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) -#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) -#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) -#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */ -#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) -#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */ -#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) -#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */ -#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) -#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */ -#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) -#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) -#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */ -#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) -#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */ -#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) -#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */ -#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ) -#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val) -#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */ -#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) -#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) -#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) -#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */ -#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) -#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */ -#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) -#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */ -#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) -#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */ -#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) -#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) -#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */ -#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) -#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */ -#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) -#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */ -#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ) -#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val) -#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */ -#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) -#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) -#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) -#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */ -#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) -#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */ -#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) -#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */ -#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) -#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */ -#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) -#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */ -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */ -#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) -#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */ -#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) -#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */ -#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) -#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */ -#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) -#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */ -#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) -#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */ -#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) -#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */ -#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) -#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */ -#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) -#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */ -#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) -#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */ -#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) -#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */ -#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) -#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */ -#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) -#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) -#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */ -#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) -#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */ -#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) -#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */ -#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) -#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) -#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */ -#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) -#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) -#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */ -#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) -#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) -#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */ -#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) -#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */ -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */ -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */ -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */ -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */ -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ -#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) -#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ -#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) -#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ -#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) -#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ -#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) -#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) -#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) -#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) -#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) -#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pMXVR_CONFIG ((uint16_t volatile *)MXVR_CONFIG) /* MXVR Configuration Register */ -#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG) -#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val) -#define pMXVR_STATE_0 ((uint32_t volatile *)MXVR_STATE_0) /* MXVR State Register 0 */ -#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0) -#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val) -#define pMXVR_STATE_1 ((uint32_t volatile *)MXVR_STATE_1) /* MXVR State Register 1 */ -#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1) -#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val) -#define pMXVR_INT_STAT_0 ((uint32_t volatile *)MXVR_INT_STAT_0) /* MXVR Interrupt Status Register 0 */ -#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0) -#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val) -#define pMXVR_INT_STAT_1 ((uint32_t volatile *)MXVR_INT_STAT_1) /* MXVR Interrupt Status Register 1 */ -#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1) -#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val) -#define pMXVR_INT_EN_0 ((uint32_t volatile *)MXVR_INT_EN_0) /* MXVR Interrupt Enable Register 0 */ -#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0) -#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val) -#define pMXVR_INT_EN_1 ((uint32_t volatile *)MXVR_INT_EN_1) /* MXVR Interrupt Enable Register 1 */ -#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1) -#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val) -#define pMXVR_POSITION ((uint16_t volatile *)MXVR_POSITION) /* MXVR Node Position Register */ -#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION) -#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val) -#define pMXVR_MAX_POSITION ((uint16_t volatile *)MXVR_MAX_POSITION) /* MXVR Maximum Node Position Register */ -#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION) -#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val) -#define pMXVR_DELAY ((uint16_t volatile *)MXVR_DELAY) /* MXVR Node Frame Delay Register */ -#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY) -#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val) -#define pMXVR_MAX_DELAY ((uint16_t volatile *)MXVR_MAX_DELAY) /* MXVR Maximum Node Frame Delay Register */ -#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY) -#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val) -#define pMXVR_LADDR ((uint32_t volatile *)MXVR_LADDR) /* MXVR Logical Address Register */ -#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR) -#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val) -#define pMXVR_GADDR ((uint16_t volatile *)MXVR_GADDR) /* MXVR Group Address Register */ -#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR) -#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val) -#define pMXVR_AADDR ((uint32_t volatile *)MXVR_AADDR) /* MXVR Alternate Address Register */ -#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR) -#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val) -#define pMXVR_ALLOC_0 ((uint32_t volatile *)MXVR_ALLOC_0) /* MXVR Allocation Table Register 0 */ -#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0) -#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val) -#define pMXVR_ALLOC_1 ((uint32_t volatile *)MXVR_ALLOC_1) /* MXVR Allocation Table Register 1 */ -#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1) -#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val) -#define pMXVR_ALLOC_2 ((uint32_t volatile *)MXVR_ALLOC_2) /* MXVR Allocation Table Register 2 */ -#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2) -#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val) -#define pMXVR_ALLOC_3 ((uint32_t volatile *)MXVR_ALLOC_3) /* MXVR Allocation Table Register 3 */ -#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3) -#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val) -#define pMXVR_ALLOC_4 ((uint32_t volatile *)MXVR_ALLOC_4) /* MXVR Allocation Table Register 4 */ -#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4) -#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val) -#define pMXVR_ALLOC_5 ((uint32_t volatile *)MXVR_ALLOC_5) /* MXVR Allocation Table Register 5 */ -#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5) -#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val) -#define pMXVR_ALLOC_6 ((uint32_t volatile *)MXVR_ALLOC_6) /* MXVR Allocation Table Register 6 */ -#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6) -#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val) -#define pMXVR_ALLOC_7 ((uint32_t volatile *)MXVR_ALLOC_7) /* MXVR Allocation Table Register 7 */ -#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7) -#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val) -#define pMXVR_ALLOC_8 ((uint32_t volatile *)MXVR_ALLOC_8) /* MXVR Allocation Table Register 8 */ -#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8) -#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val) -#define pMXVR_ALLOC_9 ((uint32_t volatile *)MXVR_ALLOC_9) /* MXVR Allocation Table Register 9 */ -#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9) -#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val) -#define pMXVR_ALLOC_10 ((uint32_t volatile *)MXVR_ALLOC_10) /* MXVR Allocation Table Register 10 */ -#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10) -#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val) -#define pMXVR_ALLOC_11 ((uint32_t volatile *)MXVR_ALLOC_11) /* MXVR Allocation Table Register 11 */ -#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11) -#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val) -#define pMXVR_ALLOC_12 ((uint32_t volatile *)MXVR_ALLOC_12) /* MXVR Allocation Table Register 12 */ -#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12) -#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val) -#define pMXVR_ALLOC_13 ((uint32_t volatile *)MXVR_ALLOC_13) /* MXVR Allocation Table Register 13 */ -#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13) -#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val) -#define pMXVR_ALLOC_14 ((uint32_t volatile *)MXVR_ALLOC_14) /* MXVR Allocation Table Register 14 */ -#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14) -#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val) -#define pMXVR_SYNC_LCHAN_0 ((uint32_t volatile *)MXVR_SYNC_LCHAN_0) /* MXVR Sync Data Logical Channel Assign Register 0 */ -#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0) -#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val) -#define pMXVR_SYNC_LCHAN_1 ((uint32_t volatile *)MXVR_SYNC_LCHAN_1) /* MXVR Sync Data Logical Channel Assign Register 1 */ -#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1) -#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val) -#define pMXVR_SYNC_LCHAN_2 ((uint32_t volatile *)MXVR_SYNC_LCHAN_2) /* MXVR Sync Data Logical Channel Assign Register 2 */ -#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2) -#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val) -#define pMXVR_SYNC_LCHAN_3 ((uint32_t volatile *)MXVR_SYNC_LCHAN_3) /* MXVR Sync Data Logical Channel Assign Register 3 */ -#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3) -#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val) -#define pMXVR_SYNC_LCHAN_4 ((uint32_t volatile *)MXVR_SYNC_LCHAN_4) /* MXVR Sync Data Logical Channel Assign Register 4 */ -#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4) -#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val) -#define pMXVR_SYNC_LCHAN_5 ((uint32_t volatile *)MXVR_SYNC_LCHAN_5) /* MXVR Sync Data Logical Channel Assign Register 5 */ -#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5) -#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val) -#define pMXVR_SYNC_LCHAN_6 ((uint32_t volatile *)MXVR_SYNC_LCHAN_6) /* MXVR Sync Data Logical Channel Assign Register 6 */ -#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6) -#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val) -#define pMXVR_SYNC_LCHAN_7 ((uint32_t volatile *)MXVR_SYNC_LCHAN_7) /* MXVR Sync Data Logical Channel Assign Register 7 */ -#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7) -#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val) -#define pMXVR_DMA0_CONFIG ((uint32_t volatile *)MXVR_DMA0_CONFIG) /* MXVR Sync Data DMA0 Config Register */ -#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG) -#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val) -#define pMXVR_DMA0_START_ADDR ((void * volatile *)MXVR_DMA0_START_ADDR) /* MXVR Sync Data DMA0 Start Address */ -#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR) -#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val) -#define pMXVR_DMA0_COUNT ((uint16_t volatile *)MXVR_DMA0_COUNT) /* MXVR Sync Data DMA0 Loop Count Register */ -#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT) -#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val) -#define pMXVR_DMA0_CURR_ADDR ((void * volatile *)MXVR_DMA0_CURR_ADDR) /* MXVR Sync Data DMA0 Current Address */ -#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR) -#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val) -#define pMXVR_DMA0_CURR_COUNT ((uint16_t volatile *)MXVR_DMA0_CURR_COUNT) /* MXVR Sync Data DMA0 Current Loop Count */ -#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT) -#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val) -#define pMXVR_DMA1_CONFIG ((uint32_t volatile *)MXVR_DMA1_CONFIG) /* MXVR Sync Data DMA1 Config Register */ -#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG) -#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val) -#define pMXVR_DMA1_START_ADDR ((void * volatile *)MXVR_DMA1_START_ADDR) /* MXVR Sync Data DMA1 Start Address */ -#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR) -#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val) -#define pMXVR_DMA1_COUNT ((uint16_t volatile *)MXVR_DMA1_COUNT) /* MXVR Sync Data DMA1 Loop Count Register */ -#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT) -#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val) -#define pMXVR_DMA1_CURR_ADDR ((void * volatile *)MXVR_DMA1_CURR_ADDR) /* MXVR Sync Data DMA1 Current Address */ -#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR) -#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val) -#define pMXVR_DMA1_CURR_COUNT ((uint16_t volatile *)MXVR_DMA1_CURR_COUNT) /* MXVR Sync Data DMA1 Current Loop Count */ -#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT) -#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val) -#define pMXVR_DMA2_CONFIG ((uint32_t volatile *)MXVR_DMA2_CONFIG) /* MXVR Sync Data DMA2 Config Register */ -#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG) -#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val) -#define pMXVR_DMA2_START_ADDR ((void * volatile *)MXVR_DMA2_START_ADDR) /* MXVR Sync Data DMA2 Start Address */ -#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR) -#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val) -#define pMXVR_DMA2_COUNT ((uint16_t volatile *)MXVR_DMA2_COUNT) /* MXVR Sync Data DMA2 Loop Count Register */ -#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT) -#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val) -#define pMXVR_DMA2_CURR_ADDR ((void * volatile *)MXVR_DMA2_CURR_ADDR) /* MXVR Sync Data DMA2 Current Address */ -#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR) -#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val) -#define pMXVR_DMA2_CURR_COUNT ((uint16_t volatile *)MXVR_DMA2_CURR_COUNT) /* MXVR Sync Data DMA2 Current Loop Count */ -#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT) -#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val) -#define pMXVR_DMA3_CONFIG ((uint32_t volatile *)MXVR_DMA3_CONFIG) /* MXVR Sync Data DMA3 Config Register */ -#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG) -#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val) -#define pMXVR_DMA3_START_ADDR ((void * volatile *)MXVR_DMA3_START_ADDR) /* MXVR Sync Data DMA3 Start Address */ -#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR) -#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val) -#define pMXVR_DMA3_COUNT ((uint16_t volatile *)MXVR_DMA3_COUNT) /* MXVR Sync Data DMA3 Loop Count Register */ -#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT) -#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val) -#define pMXVR_DMA3_CURR_ADDR ((void * volatile *)MXVR_DMA3_CURR_ADDR) /* MXVR Sync Data DMA3 Current Address */ -#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR) -#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val) -#define pMXVR_DMA3_CURR_COUNT ((uint16_t volatile *)MXVR_DMA3_CURR_COUNT) /* MXVR Sync Data DMA3 Current Loop Count */ -#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT) -#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val) -#define pMXVR_DMA4_CONFIG ((uint32_t volatile *)MXVR_DMA4_CONFIG) /* MXVR Sync Data DMA4 Config Register */ -#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG) -#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val) -#define pMXVR_DMA4_START_ADDR ((void * volatile *)MXVR_DMA4_START_ADDR) /* MXVR Sync Data DMA4 Start Address */ -#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR) -#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val) -#define pMXVR_DMA4_COUNT ((uint16_t volatile *)MXVR_DMA4_COUNT) /* MXVR Sync Data DMA4 Loop Count Register */ -#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT) -#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val) -#define pMXVR_DMA4_CURR_ADDR ((void * volatile *)MXVR_DMA4_CURR_ADDR) /* MXVR Sync Data DMA4 Current Address */ -#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR) -#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val) -#define pMXVR_DMA4_CURR_COUNT ((uint16_t volatile *)MXVR_DMA4_CURR_COUNT) /* MXVR Sync Data DMA4 Current Loop Count */ -#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT) -#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val) -#define pMXVR_DMA5_CONFIG ((uint32_t volatile *)MXVR_DMA5_CONFIG) /* MXVR Sync Data DMA5 Config Register */ -#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG) -#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val) -#define pMXVR_DMA5_START_ADDR ((void * volatile *)MXVR_DMA5_START_ADDR) /* MXVR Sync Data DMA5 Start Address */ -#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR) -#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val) -#define pMXVR_DMA5_COUNT ((uint16_t volatile *)MXVR_DMA5_COUNT) /* MXVR Sync Data DMA5 Loop Count Register */ -#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT) -#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val) -#define pMXVR_DMA5_CURR_ADDR ((void * volatile *)MXVR_DMA5_CURR_ADDR) /* MXVR Sync Data DMA5 Current Address */ -#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR) -#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val) -#define pMXVR_DMA5_CURR_COUNT ((uint16_t volatile *)MXVR_DMA5_CURR_COUNT) /* MXVR Sync Data DMA5 Current Loop Count */ -#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT) -#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val) -#define pMXVR_DMA6_CONFIG ((uint32_t volatile *)MXVR_DMA6_CONFIG) /* MXVR Sync Data DMA6 Config Register */ -#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG) -#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val) -#define pMXVR_DMA6_START_ADDR ((void * volatile *)MXVR_DMA6_START_ADDR) /* MXVR Sync Data DMA6 Start Address */ -#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR) -#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val) -#define pMXVR_DMA6_COUNT ((uint16_t volatile *)MXVR_DMA6_COUNT) /* MXVR Sync Data DMA6 Loop Count Register */ -#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT) -#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val) -#define pMXVR_DMA6_CURR_ADDR ((void * volatile *)MXVR_DMA6_CURR_ADDR) /* MXVR Sync Data DMA6 Current Address */ -#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR) -#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val) -#define pMXVR_DMA6_CURR_COUNT ((uint16_t volatile *)MXVR_DMA6_CURR_COUNT) /* MXVR Sync Data DMA6 Current Loop Count */ -#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT) -#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val) -#define pMXVR_DMA7_CONFIG ((uint32_t volatile *)MXVR_DMA7_CONFIG) /* MXVR Sync Data DMA7 Config Register */ -#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG) -#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val) -#define pMXVR_DMA7_START_ADDR ((void * volatile *)MXVR_DMA7_START_ADDR) /* MXVR Sync Data DMA7 Start Address */ -#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR) -#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val) -#define pMXVR_DMA7_COUNT ((uint16_t volatile *)MXVR_DMA7_COUNT) /* MXVR Sync Data DMA7 Loop Count Register */ -#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT) -#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val) -#define pMXVR_DMA7_CURR_ADDR ((void * volatile *)MXVR_DMA7_CURR_ADDR) /* MXVR Sync Data DMA7 Current Address */ -#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR) -#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val) -#define pMXVR_DMA7_CURR_COUNT ((uint16_t volatile *)MXVR_DMA7_CURR_COUNT) /* MXVR Sync Data DMA7 Current Loop Count */ -#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT) -#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val) -#define pMXVR_AP_CTL ((uint16_t volatile *)MXVR_AP_CTL) /* MXVR Async Packet Control Register */ -#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL) -#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val) -#define pMXVR_APRB_START_ADDR ((void * volatile *)MXVR_APRB_START_ADDR) /* MXVR Async Packet RX Buffer Start Addr Register */ -#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR) -#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val) -#define pMXVR_APRB_CURR_ADDR ((void * volatile *)MXVR_APRB_CURR_ADDR) /* MXVR Async Packet RX Buffer Current Addr Register */ -#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR) -#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val) -#define pMXVR_APTB_START_ADDR ((void * volatile *)MXVR_APTB_START_ADDR) /* MXVR Async Packet TX Buffer Start Addr Register */ -#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR) -#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val) -#define pMXVR_APTB_CURR_ADDR ((void * volatile *)MXVR_APTB_CURR_ADDR) /* MXVR Async Packet TX Buffer Current Addr Register */ -#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR) -#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val) -#define pMXVR_CM_CTL ((uint32_t volatile *)MXVR_CM_CTL) /* MXVR Control Message Control Register */ -#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL) -#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val) -#define pMXVR_CMRB_START_ADDR ((void * volatile *)MXVR_CMRB_START_ADDR) /* MXVR Control Message RX Buffer Start Addr Register */ -#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR) -#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val) -#define pMXVR_CMRB_CURR_ADDR ((void * volatile *)MXVR_CMRB_CURR_ADDR) /* MXVR Control Message RX Buffer Current Address */ -#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR) -#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val) -#define pMXVR_CMTB_START_ADDR ((void * volatile *)MXVR_CMTB_START_ADDR) /* MXVR Control Message TX Buffer Start Addr Register */ -#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR) -#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val) -#define pMXVR_CMTB_CURR_ADDR ((void * volatile *)MXVR_CMTB_CURR_ADDR) /* MXVR Control Message TX Buffer Current Address */ -#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR) -#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val) -#define pMXVR_RRDB_START_ADDR ((void * volatile *)MXVR_RRDB_START_ADDR) /* MXVR Remote Read Buffer Start Addr Register */ -#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR) -#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val) -#define pMXVR_RRDB_CURR_ADDR ((void * volatile *)MXVR_RRDB_CURR_ADDR) /* MXVR Remote Read Buffer Current Addr Register */ -#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR) -#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val) -#define pMXVR_PAT_DATA_0 ((uint32_t volatile *)MXVR_PAT_DATA_0) /* MXVR Pattern Data Register 0 */ -#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0) -#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val) -#define pMXVR_PAT_EN_0 ((uint32_t volatile *)MXVR_PAT_EN_0) /* MXVR Pattern Enable Register 0 */ -#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0) -#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val) -#define pMXVR_PAT_DATA_1 ((uint32_t volatile *)MXVR_PAT_DATA_1) /* MXVR Pattern Data Register 1 */ -#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1) -#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val) -#define pMXVR_PAT_EN_1 ((uint32_t volatile *)MXVR_PAT_EN_1) /* MXVR Pattern Enable Register 1 */ -#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1) -#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val) -#define pMXVR_FRAME_CNT_0 ((uint16_t volatile *)MXVR_FRAME_CNT_0) /* MXVR Frame Counter 0 */ -#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0) -#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val) -#define pMXVR_FRAME_CNT_1 ((uint16_t volatile *)MXVR_FRAME_CNT_1) /* MXVR Frame Counter 1 */ -#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1) -#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val) -#define pMXVR_ROUTING_0 ((uint32_t volatile *)MXVR_ROUTING_0) /* MXVR Routing Table Register 0 */ -#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0) -#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val) -#define pMXVR_ROUTING_1 ((uint32_t volatile *)MXVR_ROUTING_1) /* MXVR Routing Table Register 1 */ -#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1) -#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val) -#define pMXVR_ROUTING_2 ((uint32_t volatile *)MXVR_ROUTING_2) /* MXVR Routing Table Register 2 */ -#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2) -#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val) -#define pMXVR_ROUTING_3 ((uint32_t volatile *)MXVR_ROUTING_3) /* MXVR Routing Table Register 3 */ -#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3) -#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val) -#define pMXVR_ROUTING_4 ((uint32_t volatile *)MXVR_ROUTING_4) /* MXVR Routing Table Register 4 */ -#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4) -#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val) -#define pMXVR_ROUTING_5 ((uint32_t volatile *)MXVR_ROUTING_5) /* MXVR Routing Table Register 5 */ -#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5) -#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val) -#define pMXVR_ROUTING_6 ((uint32_t volatile *)MXVR_ROUTING_6) /* MXVR Routing Table Register 6 */ -#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6) -#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val) -#define pMXVR_ROUTING_7 ((uint32_t volatile *)MXVR_ROUTING_7) /* MXVR Routing Table Register 7 */ -#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7) -#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val) -#define pMXVR_ROUTING_8 ((uint32_t volatile *)MXVR_ROUTING_8) /* MXVR Routing Table Register 8 */ -#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8) -#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val) -#define pMXVR_ROUTING_9 ((uint32_t volatile *)MXVR_ROUTING_9) /* MXVR Routing Table Register 9 */ -#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9) -#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val) -#define pMXVR_ROUTING_10 ((uint32_t volatile *)MXVR_ROUTING_10) /* MXVR Routing Table Register 10 */ -#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10) -#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val) -#define pMXVR_ROUTING_11 ((uint32_t volatile *)MXVR_ROUTING_11) /* MXVR Routing Table Register 11 */ -#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11) -#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val) -#define pMXVR_ROUTING_12 ((uint32_t volatile *)MXVR_ROUTING_12) /* MXVR Routing Table Register 12 */ -#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12) -#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val) -#define pMXVR_ROUTING_13 ((uint32_t volatile *)MXVR_ROUTING_13) /* MXVR Routing Table Register 13 */ -#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13) -#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val) -#define pMXVR_ROUTING_14 ((uint32_t volatile *)MXVR_ROUTING_14) /* MXVR Routing Table Register 14 */ -#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14) -#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val) -#define pMXVR_BLOCK_CNT ((uint16_t volatile *)MXVR_BLOCK_CNT) /* MXVR Block Counter */ -#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT) -#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val) -#define pMXVR_CLK_CTL ((uint32_t volatile *)MXVR_CLK_CTL) /* MXVR Clock Control Register */ -#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL) -#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val) -#define pMXVR_CDRPLL_CTL ((uint32_t volatile *)MXVR_CDRPLL_CTL) /* MXVR Clock/Data Recovery PLL Control Register */ -#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL) -#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val) -#define pMXVR_FMPLL_CTL ((uint32_t volatile *)MXVR_FMPLL_CTL) /* MXVR Frequency Multiply PLL Control Register */ -#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL) -#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val) -#define pMXVR_PIN_CTL ((uint16_t volatile *)MXVR_PIN_CTL) /* MXVR Pin Control Register */ -#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL) -#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val) -#define pMXVR_SCLK_CNT ((uint16_t volatile *)MXVR_SCLK_CNT) /* MXVR System Clock Counter Register */ -#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT) -#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val) -#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */ -#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) -#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) -#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */ -#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) -#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) -#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */ -#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) -#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) -#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */ -#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) -#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) -#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */ -#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) -#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) -#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */ -#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) -#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) -#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */ -#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) -#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) -#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */ -#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) -#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) -#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */ -#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) -#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) -#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */ -#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) -#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) -#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */ -#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) -#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) -#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */ -#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) -#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) -#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */ -#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) -#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) -#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */ -#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) -#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) -#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */ -#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) -#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) -#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */ -#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) -#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) -#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */ -#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) -#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) -#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */ -#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) -#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */ -#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) -#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) -#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */ -#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) -#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */ -#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) -#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) -#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */ -#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) -#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) -#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */ -#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) -#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) -#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */ -#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) -#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) -#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */ -#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) -#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) -#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */ -#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) -#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) -#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */ -#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) -#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) -#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */ -#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) -#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) -#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */ -#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) -#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) -#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */ -#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) -#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) -#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */ -#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) -#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) -#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */ -#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) -#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) -#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */ -#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) -#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) -#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */ -#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) -#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) -#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */ -#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) -#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) -#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */ -#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) -#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) -#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */ -#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) -#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) -#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */ -#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) -#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) -#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */ -#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) -#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) -#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */ -#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) -#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) -#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */ -#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) -#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) -#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */ -#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) -#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) -#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */ -#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) -#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) -#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */ -#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) -#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) -#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */ -#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) -#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) -#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */ -#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) -#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) -#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */ -#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) -#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) -#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */ -#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) -#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) -#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */ -#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) -#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) -#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */ -#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) -#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) -#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */ -#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) -#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) -#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */ -#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) -#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) -#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */ -#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) -#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) -#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */ -#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) -#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) -#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */ -#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) -#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) -#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */ -#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) -#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) -#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */ -#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) -#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) -#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */ -#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) -#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) -#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) -#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) -#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) -#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) -#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) -#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) -#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */ -#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) -#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ -#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) -#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ -#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) -#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ -#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) -#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ -#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) -#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ -#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) -#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ -#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) -#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ -#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) -#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ -#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) -#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ -#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) -#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ -#define bfin_read_NFC_RST() bfin_read16(NFC_RST) -#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ -#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) -#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ -#define bfin_read_NFC_READ() bfin_read16(NFC_READ) -#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ -#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) -#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ -#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) -#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ -#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) -#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ -#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) -#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */ -#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) -#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) -#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */ -#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) -#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) -#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */ -#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) -#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) -#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */ -#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) -#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) -#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */ -#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) -#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) -#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */ -#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) -#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) -#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */ -#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) -#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) -#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */ -#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) -#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) -#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */ -#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) -#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) -#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) -#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) -#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) -#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) -#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) -#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) -#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) -#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) -#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */ -#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) -#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) -#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */ -#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) -#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */ -#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) -#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */ -#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) -#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */ -#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) -#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */ -#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) -#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */ -#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) -#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */ -#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) -#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */ -#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) -#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */ -#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) -#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) -#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) -#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) -#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) -#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */ -#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) -#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) -#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */ -#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) -#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */ -#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) -#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */ -#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) -#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */ -#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) -#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */ -#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) -#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */ -#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) -#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */ -#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) -#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */ -#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) -#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */ -#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) -#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) -#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) -#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) -#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) -#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */ -#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) -#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) -#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */ -#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) -#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) -#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */ -#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) -#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) -#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */ -#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) -#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) -#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */ -#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) -#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) -#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */ -#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) -#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) -#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */ -#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) -#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) -#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */ -#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) -#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) -#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */ -#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) -#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) -#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ -#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) -#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) -#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ -#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) -#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) -#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ -#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) -#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) -#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ -#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) -#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) -#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ -#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) -#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) -#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */ -#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) -#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) -#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */ -#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) -#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) -#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */ -#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) -#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) -#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */ -#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) -#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) -#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */ -#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) -#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) -#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */ -#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) -#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) -#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */ -#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) -#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) -#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */ -#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) -#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) -#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ -#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) -#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) -#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ -#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) -#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) -#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ -#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) -#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) -#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ -#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) -#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) -#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ -#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) -#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) -#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */ -#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) -#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) -#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */ -#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) -#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) -#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */ -#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) -#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) -#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */ -#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) -#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) -#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */ -#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) -#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) -#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */ -#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) -#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) -#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */ -#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) -#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) -#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */ -#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) -#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) -#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */ -#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) -#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) -#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */ -#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) -#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) -#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */ -#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) -#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) -#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */ -#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) -#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) -#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */ -#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) -#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) -#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */ -#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) -#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) -#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */ -#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) -#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) -#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */ -#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) -#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) -#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) -#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) -#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) -#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) -#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) -#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) -#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) -#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) -#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) -#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) -#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) -#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) -#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) -#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) -#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) -#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) -#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) -#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) -#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) -#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) -#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) -#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) -#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) -#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) -#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) -#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) -#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) -#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) -#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) -#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) -#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) -#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) -#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) -#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) -#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) -#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) -#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) -#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) -#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) -#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) -#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) -#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) -#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) -#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) -#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) -#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) -#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) -#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) -#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) -#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) -#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) -#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) -#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) -#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) -#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) -#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) -#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) -#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) -#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) -#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) -#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) -#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) -#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) -#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) -#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) -#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) -#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) -#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) -#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) -#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) -#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) -#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) -#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) -#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) -#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) -#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) -#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) -#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) -#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) -#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) -#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) -#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) -#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) -#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) -#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) -#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) -#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) -#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) -#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) -#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) -#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) -#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) -#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) -#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) -#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) -#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) -#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) -#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) -#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) -#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) -#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) -#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) -#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) -#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) -#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) -#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) -#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) -#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) -#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) -#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) -#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) -#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) -#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) -#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) -#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) -#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) -#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) -#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) -#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) -#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) -#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) -#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) -#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) -#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) -#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ -#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) -#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) -#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ -#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) -#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) -#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */ -#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) -#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) -#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */ -#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) -#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) -#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */ -#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) -#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) -#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */ -#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) -#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) -#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */ -#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) -#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) -#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */ -#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) -#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) -#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */ -#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) -#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) -#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */ -#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) -#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) -#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */ -#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) -#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) -#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */ -#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) -#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) -#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */ -#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) -#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) -#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */ -#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) -#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) -#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */ -#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) -#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) -#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */ -#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) -#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) -#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */ -#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) -#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) -#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */ -#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) -#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) -#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */ -#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) -#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) -#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */ -#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) -#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) -#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */ -#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) -#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) -#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */ -#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) -#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) -#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */ -#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) -#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) -#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */ -#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) -#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) -#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */ -#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) -#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) -#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */ -#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) -#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) -#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */ -#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) -#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) -#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */ -#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) -#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) -#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */ -#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) -#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) -#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */ -#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) -#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) -#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */ -#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) -#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) -#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */ -#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) -#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) -#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */ -#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) -#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) -#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */ -#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) -#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) -#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */ -#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) -#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) -#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */ -#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) -#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) -#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */ -#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) -#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) -#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */ -#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) -#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) -#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */ -#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) -#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) -#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */ -#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) -#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) -#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */ -#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) -#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) -#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */ -#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) -#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) -#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */ -#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) -#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) -#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */ -#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) -#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) -#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */ -#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) -#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) -#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */ -#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) -#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) -#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */ -#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) -#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) -#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */ -#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) -#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) -#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */ -#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) -#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) -#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */ -#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) -#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) -#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */ -#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) -#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) -#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */ -#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) -#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) -#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */ -#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) -#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) -#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */ -#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) -#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) -#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */ -#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) -#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) -#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */ -#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) -#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) -#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */ -#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) -#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) -#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */ -#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) -#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) -#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */ -#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) -#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) -#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */ -#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) -#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) -#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */ -#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) -#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) -#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */ -#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) -#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) -#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */ -#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) -#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) -#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */ -#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) -#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) -#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */ -#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) -#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) -#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */ -#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) -#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) -#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */ -#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) -#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) -#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */ -#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) -#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) -#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */ -#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) -#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) -#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */ -#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) -#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) -#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */ -#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) -#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) -#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */ -#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) -#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) -#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */ -#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) -#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) -#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */ -#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) -#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) -#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */ -#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) -#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) -#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */ -#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) -#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) -#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */ -#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) -#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) -#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */ -#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) -#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) -#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */ -#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) -#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) -#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */ -#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) -#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) -#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */ -#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) -#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) -#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */ -#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) -#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) -#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */ -#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) -#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) -#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */ -#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) -#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) -#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */ -#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) -#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) -#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */ -#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) -#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) -#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */ -#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) -#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) -#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */ -#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) -#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) -#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */ -#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) -#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) -#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */ -#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) -#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) -#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */ -#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) -#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) -#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */ -#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) -#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) -#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */ -#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) -#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) -#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */ -#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) -#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) -#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */ -#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) -#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) -#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */ -#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) -#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) -#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */ -#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) -#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) -#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */ -#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) -#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) -#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */ -#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) -#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) -#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */ -#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) -#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) -#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */ -#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) -#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) -#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */ -#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) -#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) -#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */ -#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) -#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) -#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */ -#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) -#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) -#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */ -#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) -#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) -#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */ -#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) -#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) -#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */ -#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) -#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) -#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */ -#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) -#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) -#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */ -#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) -#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) -#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */ -#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) -#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) -#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */ -#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) -#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) -#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */ -#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) -#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) -#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */ -#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) -#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) -#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */ -#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) -#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) -#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */ -#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) -#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) -#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */ -#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) -#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) -#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */ -#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) -#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) -#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */ -#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) -#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) -#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */ -#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) -#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) -#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */ -#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) -#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) -#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */ -#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) -#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) -#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */ -#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) -#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) -#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */ -#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) -#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) -#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */ -#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) -#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) -#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */ -#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) -#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) -#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */ -#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) -#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) -#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */ -#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) -#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) -#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */ -#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) -#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) -#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */ -#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) -#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) -#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */ -#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) -#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) -#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */ -#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) -#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) -#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */ -#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) -#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) -#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */ -#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) -#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) -#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */ -#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) -#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) -#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */ -#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) -#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) -#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */ -#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) -#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) -#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */ -#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) -#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) -#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */ -#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) -#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) -#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */ -#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) -#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) -#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */ -#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) -#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) -#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */ -#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) -#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) -#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */ -#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) -#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) -#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */ -#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) -#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) -#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */ -#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) -#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) -#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */ -#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) -#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) -#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */ -#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) -#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) -#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */ -#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) -#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) -#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */ -#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) -#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) -#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */ -#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) -#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) -#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */ -#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) -#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) -#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */ -#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) -#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) -#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */ -#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) -#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) -#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */ -#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) -#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) -#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */ -#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) -#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) -#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */ -#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) -#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) -#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */ -#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) -#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) -#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */ -#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) -#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) -#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */ -#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) -#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) -#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */ -#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) -#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) -#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */ -#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) -#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) -#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */ -#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) -#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) -#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */ -#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) -#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) -#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */ -#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) -#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) -#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */ -#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) -#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) -#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */ -#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) -#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) -#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */ -#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) -#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) -#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */ -#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) -#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) -#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */ -#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) -#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) -#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */ -#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) -#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) -#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */ -#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) -#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) -#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */ -#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) -#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) -#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */ -#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) -#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) -#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */ -#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) -#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) -#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */ -#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) -#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) -#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */ -#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) -#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) -#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */ -#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) -#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) -#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */ -#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) -#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) -#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */ -#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) -#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) -#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */ -#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) -#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) -#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */ -#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) -#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) -#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */ -#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) -#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) -#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */ -#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) -#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) -#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */ -#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) -#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) -#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */ -#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) -#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) -#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */ -#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) -#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) -#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */ -#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) -#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) -#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */ -#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) -#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) -#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */ -#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) -#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) -#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */ -#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) -#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) -#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */ -#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) -#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) -#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */ -#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) -#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) -#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */ -#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) -#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) -#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */ -#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) -#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) -#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */ -#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) -#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) -#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */ -#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) -#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) -#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */ -#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) -#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) -#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */ -#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) -#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) -#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */ -#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) -#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) -#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */ -#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) -#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) -#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */ -#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) -#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) -#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */ -#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) -#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) -#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */ -#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) -#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) -#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */ -#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) -#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) -#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */ -#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) -#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) -#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */ -#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) -#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) -#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */ -#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) -#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) -#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */ -#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) -#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) -#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */ -#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) -#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) -#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */ -#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) -#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) -#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */ -#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) -#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) -#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */ -#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) -#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) -#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */ -#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) -#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) -#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */ -#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) -#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) -#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */ -#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) -#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) -#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */ -#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) -#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) -#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */ -#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) -#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) -#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */ -#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) -#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) -#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */ -#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) -#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) -#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */ -#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) -#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) -#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */ -#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) -#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) -#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */ -#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) -#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) -#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */ -#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) -#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) -#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */ -#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) -#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) -#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */ -#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) -#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) -#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */ -#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) -#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) -#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */ -#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) -#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) -#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */ -#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) -#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) -#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */ -#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) -#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) -#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */ -#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) -#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) -#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */ -#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) -#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) -#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */ -#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) -#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) -#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */ -#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) -#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) -#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */ -#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) -#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) -#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */ -#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) -#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) -#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */ -#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) -#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) -#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */ -#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) -#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) -#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */ -#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) -#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) -#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */ -#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) -#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) -#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */ -#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) -#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) -#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */ -#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) -#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) -#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */ -#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) -#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) -#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */ -#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) -#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) -#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */ -#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) -#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) -#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */ -#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) -#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) -#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */ -#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) -#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) -#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */ -#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) -#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) -#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */ -#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) -#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) -#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */ -#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) -#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) -#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */ -#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) -#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) -#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */ -#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) -#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) -#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */ -#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) -#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) -#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */ -#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) -#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) -#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */ -#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) -#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) -#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */ -#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) -#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) -#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */ -#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) -#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) -#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */ -#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) -#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) -#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */ -#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) -#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) -#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */ -#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) -#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) -#define pCAN1_MC1 ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */ -#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) -#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) -#define pCAN1_MD1 ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */ -#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) -#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) -#define pCAN1_TRS1 ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */ -#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) -#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) -#define pCAN1_TRR1 ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */ -#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) -#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) -#define pCAN1_TA1 ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */ -#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) -#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) -#define pCAN1_AA1 ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */ -#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) -#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) -#define pCAN1_RMP1 ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */ -#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) -#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) -#define pCAN1_RML1 ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */ -#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) -#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) -#define pCAN1_MBTIF1 ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ -#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) -#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) -#define pCAN1_MBRIF1 ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ -#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) -#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) -#define pCAN1_MBIM1 ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ -#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) -#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) -#define pCAN1_RFH1 ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ -#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) -#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) -#define pCAN1_OPSS1 ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ -#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) -#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) -#define pCAN1_MC2 ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */ -#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) -#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) -#define pCAN1_MD2 ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */ -#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) -#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) -#define pCAN1_TRS2 ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */ -#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) -#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) -#define pCAN1_TRR2 ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */ -#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) -#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) -#define pCAN1_TA2 ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */ -#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) -#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) -#define pCAN1_AA2 ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */ -#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) -#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) -#define pCAN1_RMP2 ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */ -#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) -#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) -#define pCAN1_RML2 ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */ -#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) -#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) -#define pCAN1_MBTIF2 ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ -#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) -#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) -#define pCAN1_MBRIF2 ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ -#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) -#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) -#define pCAN1_MBIM2 ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ -#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) -#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) -#define pCAN1_RFH2 ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ -#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) -#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) -#define pCAN1_OPSS2 ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ -#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) -#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) -#define pCAN1_CLOCK ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */ -#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) -#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) -#define pCAN1_TIMING ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */ -#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) -#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) -#define pCAN1_DEBUG ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */ -#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) -#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) -#define pCAN1_STATUS ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */ -#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) -#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) -#define pCAN1_CEC ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */ -#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) -#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) -#define pCAN1_GIS ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */ -#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) -#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) -#define pCAN1_GIM ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */ -#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) -#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) -#define pCAN1_GIF ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */ -#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) -#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) -#define pCAN1_CONTROL ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */ -#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) -#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) -#define pCAN1_INTR ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */ -#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) -#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) -#define pCAN1_MBTD ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */ -#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) -#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) -#define pCAN1_EWR ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */ -#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) -#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) -#define pCAN1_ESR ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */ -#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) -#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) -#define pCAN1_UCCNT ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */ -#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) -#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) -#define pCAN1_UCRC ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */ -#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) -#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) -#define pCAN1_UCCNF ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */ -#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) -#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) -#define pCAN1_AM00L ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) -#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) -#define pCAN1_AM00H ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) -#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) -#define pCAN1_AM01L ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) -#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) -#define pCAN1_AM01H ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) -#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) -#define pCAN1_AM02L ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) -#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) -#define pCAN1_AM02H ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) -#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) -#define pCAN1_AM03L ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) -#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) -#define pCAN1_AM03H ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) -#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) -#define pCAN1_AM04L ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) -#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) -#define pCAN1_AM04H ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) -#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) -#define pCAN1_AM05L ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) -#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) -#define pCAN1_AM05H ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) -#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) -#define pCAN1_AM06L ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) -#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) -#define pCAN1_AM06H ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) -#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) -#define pCAN1_AM07L ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) -#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) -#define pCAN1_AM07H ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) -#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) -#define pCAN1_AM08L ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) -#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) -#define pCAN1_AM08H ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) -#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) -#define pCAN1_AM09L ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) -#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) -#define pCAN1_AM09H ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) -#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) -#define pCAN1_AM10L ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) -#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) -#define pCAN1_AM10H ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) -#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) -#define pCAN1_AM11L ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) -#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) -#define pCAN1_AM11H ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) -#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) -#define pCAN1_AM12L ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) -#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) -#define pCAN1_AM12H ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) -#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) -#define pCAN1_AM13L ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) -#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) -#define pCAN1_AM13H ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) -#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) -#define pCAN1_AM14L ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) -#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) -#define pCAN1_AM14H ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) -#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) -#define pCAN1_AM15L ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) -#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) -#define pCAN1_AM15H ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) -#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) -#define pCAN1_AM16L ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) -#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) -#define pCAN1_AM16H ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) -#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) -#define pCAN1_AM17L ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) -#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) -#define pCAN1_AM17H ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) -#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) -#define pCAN1_AM18L ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) -#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) -#define pCAN1_AM18H ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) -#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) -#define pCAN1_AM19L ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) -#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) -#define pCAN1_AM19H ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) -#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) -#define pCAN1_AM20L ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) -#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) -#define pCAN1_AM20H ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) -#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) -#define pCAN1_AM21L ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) -#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) -#define pCAN1_AM21H ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) -#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) -#define pCAN1_AM22L ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) -#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) -#define pCAN1_AM22H ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) -#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) -#define pCAN1_AM23L ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) -#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) -#define pCAN1_AM23H ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) -#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) -#define pCAN1_AM24L ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) -#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) -#define pCAN1_AM24H ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) -#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) -#define pCAN1_AM25L ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) -#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) -#define pCAN1_AM25H ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) -#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) -#define pCAN1_AM26L ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) -#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) -#define pCAN1_AM26H ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) -#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) -#define pCAN1_AM27L ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) -#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) -#define pCAN1_AM27H ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) -#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) -#define pCAN1_AM28L ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) -#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) -#define pCAN1_AM28H ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) -#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) -#define pCAN1_AM29L ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) -#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) -#define pCAN1_AM29H ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) -#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) -#define pCAN1_AM30L ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) -#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) -#define pCAN1_AM30H ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) -#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) -#define pCAN1_AM31L ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ -#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) -#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) -#define pCAN1_AM31H ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ -#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) -#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) -#define pCAN1_MB00_DATA0 ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */ -#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) -#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) -#define pCAN1_MB00_DATA1 ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */ -#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) -#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) -#define pCAN1_MB00_DATA2 ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */ -#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) -#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) -#define pCAN1_MB00_DATA3 ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */ -#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) -#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) -#define pCAN1_MB00_LENGTH ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */ -#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) -#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) -#define pCAN1_MB00_TIMESTAMP ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */ -#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) -#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) -#define pCAN1_MB00_ID0 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */ -#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) -#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) -#define pCAN1_MB00_ID1 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */ -#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) -#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) -#define pCAN1_MB01_DATA0 ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */ -#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) -#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) -#define pCAN1_MB01_DATA1 ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */ -#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) -#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) -#define pCAN1_MB01_DATA2 ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */ -#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) -#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) -#define pCAN1_MB01_DATA3 ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */ -#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) -#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) -#define pCAN1_MB01_LENGTH ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */ -#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) -#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) -#define pCAN1_MB01_TIMESTAMP ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */ -#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) -#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) -#define pCAN1_MB01_ID0 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */ -#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) -#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) -#define pCAN1_MB01_ID1 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */ -#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) -#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) -#define pCAN1_MB02_DATA0 ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */ -#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) -#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) -#define pCAN1_MB02_DATA1 ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */ -#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) -#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) -#define pCAN1_MB02_DATA2 ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */ -#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) -#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) -#define pCAN1_MB02_DATA3 ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */ -#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) -#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) -#define pCAN1_MB02_LENGTH ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */ -#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) -#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) -#define pCAN1_MB02_TIMESTAMP ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */ -#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) -#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) -#define pCAN1_MB02_ID0 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */ -#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) -#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) -#define pCAN1_MB02_ID1 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */ -#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) -#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) -#define pCAN1_MB03_DATA0 ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */ -#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) -#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) -#define pCAN1_MB03_DATA1 ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */ -#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) -#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) -#define pCAN1_MB03_DATA2 ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */ -#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) -#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) -#define pCAN1_MB03_DATA3 ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */ -#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) -#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) -#define pCAN1_MB03_LENGTH ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */ -#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) -#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) -#define pCAN1_MB03_TIMESTAMP ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */ -#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) -#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) -#define pCAN1_MB03_ID0 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */ -#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) -#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) -#define pCAN1_MB03_ID1 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */ -#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) -#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) -#define pCAN1_MB04_DATA0 ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */ -#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) -#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) -#define pCAN1_MB04_DATA1 ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */ -#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) -#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) -#define pCAN1_MB04_DATA2 ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */ -#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) -#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) -#define pCAN1_MB04_DATA3 ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */ -#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) -#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) -#define pCAN1_MB04_LENGTH ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */ -#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) -#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) -#define pCAN1_MB04_TIMESTAMP ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */ -#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) -#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) -#define pCAN1_MB04_ID0 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */ -#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) -#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) -#define pCAN1_MB04_ID1 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */ -#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) -#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) -#define pCAN1_MB05_DATA0 ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */ -#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) -#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) -#define pCAN1_MB05_DATA1 ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */ -#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) -#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) -#define pCAN1_MB05_DATA2 ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */ -#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) -#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) -#define pCAN1_MB05_DATA3 ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */ -#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) -#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) -#define pCAN1_MB05_LENGTH ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */ -#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) -#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) -#define pCAN1_MB05_TIMESTAMP ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */ -#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) -#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) -#define pCAN1_MB05_ID0 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */ -#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) -#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) -#define pCAN1_MB05_ID1 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */ -#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) -#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) -#define pCAN1_MB06_DATA0 ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */ -#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) -#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) -#define pCAN1_MB06_DATA1 ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */ -#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) -#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) -#define pCAN1_MB06_DATA2 ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */ -#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) -#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) -#define pCAN1_MB06_DATA3 ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */ -#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) -#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) -#define pCAN1_MB06_LENGTH ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */ -#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) -#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) -#define pCAN1_MB06_TIMESTAMP ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */ -#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) -#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) -#define pCAN1_MB06_ID0 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */ -#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) -#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) -#define pCAN1_MB06_ID1 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */ -#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) -#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) -#define pCAN1_MB07_DATA0 ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */ -#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) -#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) -#define pCAN1_MB07_DATA1 ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */ -#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) -#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) -#define pCAN1_MB07_DATA2 ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */ -#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) -#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) -#define pCAN1_MB07_DATA3 ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */ -#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) -#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) -#define pCAN1_MB07_LENGTH ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */ -#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) -#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) -#define pCAN1_MB07_TIMESTAMP ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */ -#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) -#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) -#define pCAN1_MB07_ID0 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */ -#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) -#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) -#define pCAN1_MB07_ID1 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */ -#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) -#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) -#define pCAN1_MB08_DATA0 ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */ -#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) -#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) -#define pCAN1_MB08_DATA1 ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */ -#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) -#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) -#define pCAN1_MB08_DATA2 ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */ -#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) -#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) -#define pCAN1_MB08_DATA3 ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */ -#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) -#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) -#define pCAN1_MB08_LENGTH ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */ -#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) -#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) -#define pCAN1_MB08_TIMESTAMP ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */ -#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) -#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) -#define pCAN1_MB08_ID0 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */ -#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) -#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) -#define pCAN1_MB08_ID1 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */ -#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) -#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) -#define pCAN1_MB09_DATA0 ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */ -#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) -#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) -#define pCAN1_MB09_DATA1 ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */ -#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) -#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) -#define pCAN1_MB09_DATA2 ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */ -#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) -#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) -#define pCAN1_MB09_DATA3 ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */ -#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) -#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) -#define pCAN1_MB09_LENGTH ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */ -#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) -#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) -#define pCAN1_MB09_TIMESTAMP ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */ -#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) -#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) -#define pCAN1_MB09_ID0 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */ -#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) -#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) -#define pCAN1_MB09_ID1 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */ -#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) -#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) -#define pCAN1_MB10_DATA0 ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */ -#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) -#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) -#define pCAN1_MB10_DATA1 ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */ -#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) -#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) -#define pCAN1_MB10_DATA2 ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */ -#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) -#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) -#define pCAN1_MB10_DATA3 ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */ -#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) -#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) -#define pCAN1_MB10_LENGTH ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */ -#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) -#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) -#define pCAN1_MB10_TIMESTAMP ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */ -#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) -#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) -#define pCAN1_MB10_ID0 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */ -#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) -#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) -#define pCAN1_MB10_ID1 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */ -#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) -#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) -#define pCAN1_MB11_DATA0 ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */ -#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) -#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) -#define pCAN1_MB11_DATA1 ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */ -#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) -#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) -#define pCAN1_MB11_DATA2 ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */ -#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) -#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) -#define pCAN1_MB11_DATA3 ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */ -#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) -#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) -#define pCAN1_MB11_LENGTH ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */ -#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) -#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) -#define pCAN1_MB11_TIMESTAMP ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */ -#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) -#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) -#define pCAN1_MB11_ID0 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */ -#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) -#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) -#define pCAN1_MB11_ID1 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */ -#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) -#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) -#define pCAN1_MB12_DATA0 ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */ -#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) -#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) -#define pCAN1_MB12_DATA1 ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */ -#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) -#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) -#define pCAN1_MB12_DATA2 ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */ -#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) -#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) -#define pCAN1_MB12_DATA3 ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */ -#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) -#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) -#define pCAN1_MB12_LENGTH ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */ -#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) -#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) -#define pCAN1_MB12_TIMESTAMP ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */ -#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) -#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) -#define pCAN1_MB12_ID0 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */ -#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) -#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) -#define pCAN1_MB12_ID1 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */ -#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) -#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) -#define pCAN1_MB13_DATA0 ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */ -#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) -#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) -#define pCAN1_MB13_DATA1 ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */ -#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) -#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) -#define pCAN1_MB13_DATA2 ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */ -#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) -#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) -#define pCAN1_MB13_DATA3 ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */ -#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) -#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) -#define pCAN1_MB13_LENGTH ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */ -#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) -#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) -#define pCAN1_MB13_TIMESTAMP ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */ -#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) -#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) -#define pCAN1_MB13_ID0 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */ -#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) -#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) -#define pCAN1_MB13_ID1 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */ -#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) -#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) -#define pCAN1_MB14_DATA0 ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */ -#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) -#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) -#define pCAN1_MB14_DATA1 ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */ -#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) -#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) -#define pCAN1_MB14_DATA2 ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */ -#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) -#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) -#define pCAN1_MB14_DATA3 ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */ -#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) -#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) -#define pCAN1_MB14_LENGTH ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */ -#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) -#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) -#define pCAN1_MB14_TIMESTAMP ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */ -#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) -#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) -#define pCAN1_MB14_ID0 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */ -#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) -#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) -#define pCAN1_MB14_ID1 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */ -#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) -#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) -#define pCAN1_MB15_DATA0 ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */ -#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) -#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) -#define pCAN1_MB15_DATA1 ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */ -#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) -#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) -#define pCAN1_MB15_DATA2 ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */ -#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) -#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) -#define pCAN1_MB15_DATA3 ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */ -#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) -#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) -#define pCAN1_MB15_LENGTH ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */ -#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) -#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) -#define pCAN1_MB15_TIMESTAMP ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */ -#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) -#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) -#define pCAN1_MB15_ID0 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */ -#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) -#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) -#define pCAN1_MB15_ID1 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */ -#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) -#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) -#define pCAN1_MB16_DATA0 ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */ -#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) -#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) -#define pCAN1_MB16_DATA1 ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */ -#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) -#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) -#define pCAN1_MB16_DATA2 ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */ -#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) -#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) -#define pCAN1_MB16_DATA3 ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */ -#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) -#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) -#define pCAN1_MB16_LENGTH ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */ -#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) -#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) -#define pCAN1_MB16_TIMESTAMP ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */ -#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) -#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) -#define pCAN1_MB16_ID0 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */ -#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) -#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) -#define pCAN1_MB16_ID1 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */ -#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) -#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) -#define pCAN1_MB17_DATA0 ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */ -#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) -#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) -#define pCAN1_MB17_DATA1 ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */ -#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) -#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) -#define pCAN1_MB17_DATA2 ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */ -#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) -#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) -#define pCAN1_MB17_DATA3 ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */ -#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) -#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) -#define pCAN1_MB17_LENGTH ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */ -#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) -#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) -#define pCAN1_MB17_TIMESTAMP ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */ -#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) -#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) -#define pCAN1_MB17_ID0 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */ -#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) -#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) -#define pCAN1_MB17_ID1 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */ -#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) -#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) -#define pCAN1_MB18_DATA0 ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */ -#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) -#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) -#define pCAN1_MB18_DATA1 ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */ -#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) -#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) -#define pCAN1_MB18_DATA2 ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */ -#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) -#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) -#define pCAN1_MB18_DATA3 ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */ -#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) -#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) -#define pCAN1_MB18_LENGTH ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */ -#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) -#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) -#define pCAN1_MB18_TIMESTAMP ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */ -#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) -#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) -#define pCAN1_MB18_ID0 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */ -#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) -#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) -#define pCAN1_MB18_ID1 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */ -#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) -#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) -#define pCAN1_MB19_DATA0 ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */ -#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) -#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) -#define pCAN1_MB19_DATA1 ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */ -#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) -#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) -#define pCAN1_MB19_DATA2 ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */ -#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) -#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) -#define pCAN1_MB19_DATA3 ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */ -#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) -#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) -#define pCAN1_MB19_LENGTH ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */ -#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) -#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) -#define pCAN1_MB19_TIMESTAMP ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */ -#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) -#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) -#define pCAN1_MB19_ID0 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */ -#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) -#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) -#define pCAN1_MB19_ID1 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */ -#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) -#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) -#define pCAN1_MB20_DATA0 ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */ -#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) -#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) -#define pCAN1_MB20_DATA1 ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */ -#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) -#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) -#define pCAN1_MB20_DATA2 ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */ -#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) -#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) -#define pCAN1_MB20_DATA3 ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */ -#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) -#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) -#define pCAN1_MB20_LENGTH ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */ -#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) -#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) -#define pCAN1_MB20_TIMESTAMP ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */ -#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) -#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) -#define pCAN1_MB20_ID0 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */ -#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) -#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) -#define pCAN1_MB20_ID1 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */ -#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) -#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) -#define pCAN1_MB21_DATA0 ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */ -#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) -#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) -#define pCAN1_MB21_DATA1 ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */ -#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) -#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) -#define pCAN1_MB21_DATA2 ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */ -#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) -#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) -#define pCAN1_MB21_DATA3 ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */ -#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) -#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) -#define pCAN1_MB21_LENGTH ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */ -#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) -#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) -#define pCAN1_MB21_TIMESTAMP ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */ -#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) -#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) -#define pCAN1_MB21_ID0 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */ -#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) -#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) -#define pCAN1_MB21_ID1 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */ -#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) -#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) -#define pCAN1_MB22_DATA0 ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */ -#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) -#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) -#define pCAN1_MB22_DATA1 ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */ -#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) -#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) -#define pCAN1_MB22_DATA2 ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */ -#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) -#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) -#define pCAN1_MB22_DATA3 ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */ -#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) -#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) -#define pCAN1_MB22_LENGTH ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */ -#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) -#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) -#define pCAN1_MB22_TIMESTAMP ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */ -#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) -#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) -#define pCAN1_MB22_ID0 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */ -#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) -#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) -#define pCAN1_MB22_ID1 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */ -#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) -#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) -#define pCAN1_MB23_DATA0 ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */ -#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) -#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) -#define pCAN1_MB23_DATA1 ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */ -#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) -#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) -#define pCAN1_MB23_DATA2 ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */ -#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) -#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) -#define pCAN1_MB23_DATA3 ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */ -#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) -#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) -#define pCAN1_MB23_LENGTH ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */ -#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) -#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) -#define pCAN1_MB23_TIMESTAMP ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */ -#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) -#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) -#define pCAN1_MB23_ID0 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */ -#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) -#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) -#define pCAN1_MB23_ID1 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */ -#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) -#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) -#define pCAN1_MB24_DATA0 ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */ -#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) -#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) -#define pCAN1_MB24_DATA1 ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */ -#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) -#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) -#define pCAN1_MB24_DATA2 ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */ -#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) -#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) -#define pCAN1_MB24_DATA3 ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */ -#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) -#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) -#define pCAN1_MB24_LENGTH ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */ -#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) -#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) -#define pCAN1_MB24_TIMESTAMP ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */ -#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) -#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) -#define pCAN1_MB24_ID0 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */ -#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) -#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) -#define pCAN1_MB24_ID1 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */ -#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) -#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) -#define pCAN1_MB25_DATA0 ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */ -#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) -#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) -#define pCAN1_MB25_DATA1 ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */ -#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) -#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) -#define pCAN1_MB25_DATA2 ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */ -#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) -#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) -#define pCAN1_MB25_DATA3 ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */ -#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) -#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) -#define pCAN1_MB25_LENGTH ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */ -#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) -#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) -#define pCAN1_MB25_TIMESTAMP ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */ -#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) -#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) -#define pCAN1_MB25_ID0 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */ -#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) -#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) -#define pCAN1_MB25_ID1 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */ -#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) -#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) -#define pCAN1_MB26_DATA0 ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */ -#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) -#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) -#define pCAN1_MB26_DATA1 ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */ -#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) -#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) -#define pCAN1_MB26_DATA2 ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */ -#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) -#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) -#define pCAN1_MB26_DATA3 ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */ -#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) -#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) -#define pCAN1_MB26_LENGTH ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */ -#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) -#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) -#define pCAN1_MB26_TIMESTAMP ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */ -#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) -#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) -#define pCAN1_MB26_ID0 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */ -#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) -#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) -#define pCAN1_MB26_ID1 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */ -#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) -#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) -#define pCAN1_MB27_DATA0 ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */ -#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) -#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) -#define pCAN1_MB27_DATA1 ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */ -#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) -#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) -#define pCAN1_MB27_DATA2 ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */ -#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) -#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) -#define pCAN1_MB27_DATA3 ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */ -#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) -#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) -#define pCAN1_MB27_LENGTH ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */ -#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) -#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) -#define pCAN1_MB27_TIMESTAMP ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */ -#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) -#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) -#define pCAN1_MB27_ID0 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */ -#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) -#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) -#define pCAN1_MB27_ID1 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */ -#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) -#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) -#define pCAN1_MB28_DATA0 ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */ -#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) -#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) -#define pCAN1_MB28_DATA1 ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */ -#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) -#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) -#define pCAN1_MB28_DATA2 ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */ -#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) -#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) -#define pCAN1_MB28_DATA3 ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */ -#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) -#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) -#define pCAN1_MB28_LENGTH ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */ -#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) -#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) -#define pCAN1_MB28_TIMESTAMP ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */ -#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) -#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) -#define pCAN1_MB28_ID0 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */ -#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) -#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) -#define pCAN1_MB28_ID1 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */ -#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) -#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) -#define pCAN1_MB29_DATA0 ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */ -#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) -#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) -#define pCAN1_MB29_DATA1 ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */ -#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) -#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) -#define pCAN1_MB29_DATA2 ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */ -#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) -#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) -#define pCAN1_MB29_DATA3 ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */ -#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) -#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) -#define pCAN1_MB29_LENGTH ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */ -#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) -#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) -#define pCAN1_MB29_TIMESTAMP ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */ -#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) -#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) -#define pCAN1_MB29_ID0 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */ -#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) -#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) -#define pCAN1_MB29_ID1 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */ -#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) -#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) -#define pCAN1_MB30_DATA0 ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */ -#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) -#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) -#define pCAN1_MB30_DATA1 ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */ -#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) -#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) -#define pCAN1_MB30_DATA2 ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */ -#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) -#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) -#define pCAN1_MB30_DATA3 ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */ -#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) -#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) -#define pCAN1_MB30_LENGTH ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */ -#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) -#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) -#define pCAN1_MB30_TIMESTAMP ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */ -#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) -#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) -#define pCAN1_MB30_ID0 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */ -#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) -#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) -#define pCAN1_MB30_ID1 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */ -#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) -#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) -#define pCAN1_MB31_DATA0 ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */ -#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) -#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) -#define pCAN1_MB31_DATA1 ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */ -#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) -#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) -#define pCAN1_MB31_DATA2 ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */ -#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) -#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) -#define pCAN1_MB31_DATA3 ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */ -#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) -#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) -#define pCAN1_MB31_LENGTH ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */ -#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) -#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) -#define pCAN1_MB31_TIMESTAMP ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */ -#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) -#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) -#define pCAN1_MB31_ID0 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */ -#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) -#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) -#define pCAN1_MB31_ID1 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */ -#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) -#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) -#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */ -#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) -#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */ -#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) -#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */ -#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) -#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */ -#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) -#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */ -#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) -#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */ -#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) -#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) -#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */ -#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) -#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */ -#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) -#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */ -#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) -#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */ -#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) -#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */ -#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) -#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */ -#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) -#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) -#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define pSPI2_CTL ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */ -#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) -#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) -#define pSPI2_FLG ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */ -#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) -#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) -#define pSPI2_STAT ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */ -#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) -#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) -#define pSPI2_TDBR ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */ -#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) -#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) -#define pSPI2_RDBR ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */ -#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) -#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) -#define pSPI2_BAUD ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */ -#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) -#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) -#define pSPI2_SHADOW ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */ -#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) -#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) -#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */ -#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */ -#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL) -#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val) -#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */ -#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */ -#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */ -#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) -#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */ -#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */ -#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */ -#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */ -#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) -#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */ -#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */ -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */ -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */ -#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL) -#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val) -#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */ -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */ -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */ -#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) -#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) -#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */ -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */ -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */ -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */ -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */ -#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) -#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) -#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */ -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */ -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */ -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */ -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */ -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */ -#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) -#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */ -#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) -#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) -#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) -#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ -#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) -#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */ -#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) -#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) -#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) -#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */ -#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) -#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */ -#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) -#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) -#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) -#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */ -#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) -#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) -#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) -#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) -#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) -#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) -#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) -#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) -#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) -#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */ -#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) -#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */ -#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) -#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */ -#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) -#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */ -#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) -#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ -#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) -#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */ -#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) -#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */ -#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) -#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */ -#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) -#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */ -#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) -#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */ -#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) -#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */ -#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) -#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */ -#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) -#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */ -#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) -#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */ -#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) -#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */ -#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) -#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */ -#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) -#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */ -#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) -#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */ -#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) -#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */ -#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) -#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */ -#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) -#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */ -#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) -#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */ -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) -#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) -#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */ -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */ -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */ -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) -#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) -#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */ -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */ -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART2_DLL ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) -#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) -#define pUART2_DLH ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) -#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) -#define pUART2_GCTL ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */ -#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) -#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) -#define pUART2_LCR ((uint16_t volatile *)UART2_LCR) /* Line Control Register */ -#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) -#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) -#define pUART2_MCR ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */ -#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) -#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) -#define pUART2_LSR ((uint16_t volatile *)UART2_LSR) /* Line Status Register */ -#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) -#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) -#define pUART2_MSR ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */ -#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) -#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) -#define pUART2_SCR ((uint16_t volatile *)UART2_SCR) /* Scratch Register */ -#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) -#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) -#define pUART2_IER_SET ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) -#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) -#define pUART2_IER_CLEAR ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) -#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) -#define pUART2_THR ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */ -#define bfin_read_UART2_THR() bfin_read16(UART2_THR) -#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val) -#define pUART2_RBR ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */ -#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) -#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) -#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) -#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) -#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */ -#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) -#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */ -#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) -#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */ -#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) -#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */ -#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) -#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */ -#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) -#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */ -#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) -#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */ -#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) -#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */ -#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) -#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */ -#define bfin_read_UART3_THR() bfin_read16(UART3_THR) -#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */ -#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) -#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_BF549_extended__ */ diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_def.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_def.h deleted file mode 100644 index 6163eb2..0000000 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_def.h +++ /dev/null @@ -1,2053 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_BF549_extended__ -#define __BFIN_DEF_ADSP_EDN_BF549_extended__ - -#define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */ -#define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */ -#define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */ -#define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */ -#define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */ -#define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */ -#define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */ -#define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */ -#define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */ -#define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */ -#define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */ -#define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */ -#define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */ -#define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */ -#define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */ -#define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */ -#define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */ -#define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */ -#define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ -#define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */ -#define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ -#define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */ -#define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ -#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */ -#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */ -#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */ -#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */ -#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */ -#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */ -#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */ -#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */ -#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */ -#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */ -#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */ -#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */ -#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */ -#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */ -#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */ -#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */ -#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */ -#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */ -#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */ -#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */ -#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */ -#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */ -#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */ -#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */ -#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */ -#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */ -#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */ -#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */ -#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */ -#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */ -#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */ -#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */ -#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */ -#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */ -#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */ -#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */ -#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */ -#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */ -#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */ -#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */ -#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */ -#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */ -#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */ -#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */ -#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */ -#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */ -#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */ -#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */ -#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */ -#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */ -#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */ -#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */ -#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */ -#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */ -#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */ -#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */ -#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */ -#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */ -#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */ -#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */ -#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */ -#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */ -#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */ -#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */ -#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */ -#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */ -#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */ -#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */ -#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */ -#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */ -#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */ -#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */ -#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */ -#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */ -#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */ -#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */ -#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */ -#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */ -#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */ -#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */ -#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */ -#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */ -#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */ -#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */ -#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */ -#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */ -#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */ -#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */ -#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */ -#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */ -#define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */ -#define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */ -#define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */ -#define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */ -#define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */ -#define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */ -#define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */ -#define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */ -#define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */ -#define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */ -#define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */ -#define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */ -#define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */ -#define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */ -#define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */ -#define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */ -#define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */ -#define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */ -#define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */ -#define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */ -#define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */ -#define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */ -#define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */ -#define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */ -#define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */ -#define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */ -#define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */ -#define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */ -#define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */ -#define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */ -#define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */ -#define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */ -#define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */ -#define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */ -#define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */ -#define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */ -#define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */ -#define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */ -#define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */ -#define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */ -#define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */ -#define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */ -#define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */ -#define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */ -#define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */ -#define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */ -#define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */ -#define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */ -#define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */ -#define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */ -#define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */ -#define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */ -#define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */ -#define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */ -#define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */ -#define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */ -#define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */ -#define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */ -#define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */ -#define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */ -#define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */ -#define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */ -#define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */ -#define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */ -#define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */ -#define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */ -#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ -#define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */ -#define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */ -#define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */ -#define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */ -#define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */ -#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */ -#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ -#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */ -#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ -#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */ -#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */ -#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */ -#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ -#define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */ -#define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */ -#define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */ -#define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */ -#define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */ -#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */ -#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ -#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */ -#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */ -#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */ -#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */ -#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */ -#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ -#define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */ -#define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */ -#define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */ -#define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */ -#define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */ -#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */ -#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ -#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */ -#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */ -#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */ -#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */ -#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */ -#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ -#define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */ -#define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */ -#define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */ -#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */ -#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */ -#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */ -#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ -#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */ -#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */ -#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */ -#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */ -#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */ -#define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */ -#define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */ -#define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */ -#define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */ -#define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */ -#define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */ -#define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */ -#define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */ -#define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */ -#define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */ -#define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */ -#define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */ -#define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */ -#define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ -#define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */ -#define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */ -#define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */ -#define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */ -#define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */ -#define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */ -#define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */ -#define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */ -#define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */ -#define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */ -#define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */ -#define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */ -#define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */ -#define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */ -#define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */ -#define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */ -#define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */ -#define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */ -#define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */ -#define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */ -#define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */ -#define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */ -#define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */ -#define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */ -#define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */ -#define PIXC_CTL 0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ -#define PIXC_PPL 0xFFC04404 /* Holds the number of pixels per line of the display */ -#define PIXC_LPF 0xFFC04408 /* Holds the number of lines per frame of the display */ -#define PIXC_AHSTART 0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */ -#define PIXC_AHEND 0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */ -#define PIXC_AVSTART 0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */ -#define PIXC_AVEND 0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */ -#define PIXC_ATRANSP 0xFFC0441C /* Contains the transparency ratio (set A) */ -#define PIXC_BHSTART 0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */ -#define PIXC_BHEND 0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */ -#define PIXC_BVSTART 0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */ -#define PIXC_BVEND 0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */ -#define PIXC_BTRANSP 0xFFC04430 /* Contains the transparency ratio (set B) */ -#define PIXC_INTRSTAT 0xFFC0443C /* Overlay interrupt configuration/status */ -#define PIXC_RYCON 0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ -#define PIXC_GUCON 0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ -#define PIXC_BVCON 0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ -#define PIXC_CCBIAS 0xFFC0444C /* Bias values for the color space conversion matrix */ -#define PIXC_TC 0xFFC04450 /* Holds the transparent color value */ -#define HOST_CONTROL 0xFFC03A00 /* HOSTDP Control Register */ -#define HOST_STATUS 0xFFC03A04 /* HOSTDP Status Register */ -#define HOST_TIMEOUT 0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */ -#define PORTA_FER 0xFFC014C0 /* Function Enable Register */ -#define PORTA 0xFFC014C4 /* GPIO Data Register */ -#define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */ -#define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */ -#define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */ -#define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */ -#define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */ -#define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */ -#define PORTB_FER 0xFFC014E0 /* Function Enable Register */ -#define PORTB 0xFFC014E4 /* GPIO Data Register */ -#define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */ -#define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */ -#define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */ -#define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */ -#define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */ -#define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */ -#define PORTC_FER 0xFFC01500 /* Function Enable Register */ -#define PORTC 0xFFC01504 /* GPIO Data Register */ -#define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */ -#define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */ -#define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */ -#define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */ -#define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */ -#define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */ -#define PORTD_FER 0xFFC01520 /* Function Enable Register */ -#define PORTD 0xFFC01524 /* GPIO Data Register */ -#define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */ -#define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */ -#define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */ -#define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */ -#define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */ -#define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */ -#define PORTE_FER 0xFFC01540 /* Function Enable Register */ -#define PORTE 0xFFC01544 /* GPIO Data Register */ -#define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */ -#define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */ -#define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */ -#define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */ -#define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */ -#define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */ -#define PORTF_FER 0xFFC01560 /* Function Enable Register */ -#define PORTF 0xFFC01564 /* GPIO Data Register */ -#define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */ -#define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */ -#define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */ -#define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */ -#define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */ -#define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */ -#define PORTG_FER 0xFFC01580 /* Function Enable Register */ -#define PORTG 0xFFC01584 /* GPIO Data Register */ -#define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */ -#define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */ -#define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */ -#define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */ -#define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */ -#define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */ -#define PORTH_FER 0xFFC015A0 /* Function Enable Register */ -#define PORTH 0xFFC015A4 /* GPIO Data Register */ -#define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */ -#define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */ -#define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */ -#define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */ -#define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */ -#define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */ -#define PORTI_FER 0xFFC015C0 /* Function Enable Register */ -#define PORTI 0xFFC015C4 /* GPIO Data Register */ -#define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */ -#define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */ -#define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */ -#define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */ -#define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */ -#define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */ -#define PORTJ_FER 0xFFC015E0 /* Function Enable Register */ -#define PORTJ 0xFFC015E4 /* GPIO Data Register */ -#define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */ -#define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */ -#define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */ -#define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */ -#define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */ -#define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */ -#define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */ -#define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */ -#define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */ -#define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */ -#define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */ -#define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */ -#define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */ -#define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */ -#define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */ -#define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */ -#define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */ -#define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */ -#define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */ -#define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */ -#define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */ -#define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */ -#define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */ -#define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */ -#define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */ -#define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */ -#define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */ -#define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */ -#define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */ -#define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */ -#define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */ -#define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */ -#define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */ -#define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */ -#define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */ -#define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */ -#define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */ -#define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */ -#define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */ -#define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */ -#define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */ -#define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */ -#define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */ -#define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */ -#define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */ -#define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */ -#define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */ -#define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */ -#define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */ -#define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */ -#define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */ -#define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */ -#define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */ -#define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */ -#define TIMER8_CONFIG 0xFFC00600 /* Timer 8 Configuration Register */ -#define TIMER8_COUNTER 0xFFC00604 /* Timer 8 Counter Register */ -#define TIMER8_PERIOD 0xFFC00608 /* Timer 8 Period Register */ -#define TIMER8_WIDTH 0xFFC0060C /* Timer 8 Width Register */ -#define TIMER9_CONFIG 0xFFC00610 /* Timer 9 Configuration Register */ -#define TIMER9_COUNTER 0xFFC00614 /* Timer 9 Counter Register */ -#define TIMER9_PERIOD 0xFFC00618 /* Timer 9 Period Register */ -#define TIMER9_WIDTH 0xFFC0061C /* Timer 9 Width Register */ -#define TIMER10_CONFIG 0xFFC00620 /* Timer 10 Configuration Register */ -#define TIMER10_COUNTER 0xFFC00624 /* Timer 10 Counter Register */ -#define TIMER10_PERIOD 0xFFC00628 /* Timer 10 Period Register */ -#define TIMER10_WIDTH 0xFFC0062C /* Timer 10 Width Register */ -#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */ -#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */ -#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */ -#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */ -#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */ -#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define CNT_CONFIG 0xFFC04200 /* Configuration Register */ -#define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */ -#define CNT_STATUS 0xFFC04208 /* Status Register */ -#define CNT_COMMAND 0xFFC0420C /* Command Register */ -#define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */ -#define CNT_COUNTER 0xFFC04214 /* Counter Register */ -#define CNT_MAX 0xFFC04218 /* Maximal Count Register */ -#define CNT_MIN 0xFFC0421C /* Minimal Count Register */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ -#define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */ -#define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */ -#define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */ -#define SECURE_CONTROL 0xFFC04324 /* Secure Control */ -#define SECURE_STATUS 0xFFC04328 /* Secure Status */ -#define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divisor Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */ -#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */ -#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */ -#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */ -#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */ -#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */ -#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */ -#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */ -#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */ -#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */ -#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */ -#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */ -#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */ -#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */ -#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */ -#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */ -#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */ -#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */ -#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */ -#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */ -#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */ -#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */ -#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */ -#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */ -#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */ -#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */ -#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */ -#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */ -#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */ -#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */ -#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */ -#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */ -#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */ -#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */ -#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */ -#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */ -#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */ -#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */ -#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address */ -#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */ -#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address */ -#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count */ -#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */ -#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address */ -#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */ -#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address */ -#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count */ -#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */ -#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address */ -#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */ -#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address */ -#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count */ -#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */ -#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address */ -#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */ -#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address */ -#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count */ -#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */ -#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address */ -#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */ -#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address */ -#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count */ -#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */ -#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address */ -#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */ -#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address */ -#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count */ -#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */ -#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address */ -#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */ -#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address */ -#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count */ -#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */ -#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address */ -#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */ -#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address */ -#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count */ -#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */ -#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */ -#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */ -#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */ -#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */ -#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */ -#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */ -#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */ -#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */ -#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */ -#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */ -#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */ -#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */ -#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */ -#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */ -#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */ -#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */ -#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */ -#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */ -#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */ -#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */ -#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */ -#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */ -#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */ -#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */ -#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */ -#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */ -#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */ -#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */ -#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */ -#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */ -#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */ -#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */ -#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */ -#define MXVR_CLK_CTL 0xFFC028D0 /* MXVR Clock Control Register */ -#define MXVR_CDRPLL_CTL 0xFFC028D4 /* MXVR Clock/Data Recovery PLL Control Register */ -#define MXVR_FMPLL_CTL 0xFFC028D8 /* MXVR Frequency Multiply PLL Control Register */ -#define MXVR_PIN_CTL 0xFFC028DC /* MXVR Pin Control Register */ -#define MXVR_SCLK_CNT 0xFFC028E0 /* MXVR System Clock Counter Register */ -#define KPAD_CTL 0xFFC04100 /* Controls keypad module enable and disable */ -#define KPAD_PRESCALE 0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */ -#define KPAD_MSEL 0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */ -#define KPAD_ROWCOL 0xFFC0410C /* Captures the row and column output values of the keys pressed */ -#define KPAD_STAT 0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */ -#define KPAD_SOFTEVAL 0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */ -#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ -#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ -#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ -#define SDH_COMMAND 0xFFC0390C /* SDH Command */ -#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ -#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ -#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ -#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ -#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ -#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ -#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ -#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ -#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ -#define SDH_STATUS 0xFFC03934 /* SDH Status */ -#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ -#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ -#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ -#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ -#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ -#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ -#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ -#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ -#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ -#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ -#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ -#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ -#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ -#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ -#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ -#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ -#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ -#define ATAPI_CONTROL 0xFFC03800 /* ATAPI Control Register */ -#define ATAPI_STATUS 0xFFC03804 /* ATAPI Status Register */ -#define ATAPI_DEV_ADDR 0xFFC03808 /* ATAPI Device Register Address */ -#define ATAPI_DEV_TXBUF 0xFFC0380C /* ATAPI Device Register Write Data */ -#define ATAPI_DEV_RXBUF 0xFFC03810 /* ATAPI Device Register Read Data */ -#define ATAPI_INT_MASK 0xFFC03814 /* ATAPI Interrupt Mask Register */ -#define ATAPI_INT_STATUS 0xFFC03818 /* ATAPI Interrupt Status Register */ -#define ATAPI_XFER_LEN 0xFFC0381C /* ATAPI Length of Transfer */ -#define ATAPI_LINE_STATUS 0xFFC03820 /* ATAPI Line Status */ -#define ATAPI_SM_STATE 0xFFC03824 /* ATAPI State Machine Status */ -#define ATAPI_TERMINATE 0xFFC03828 /* ATAPI Host Terminate */ -#define ATAPI_PIO_TFRCNT 0xFFC0382C /* ATAPI PIO mode transfer count */ -#define ATAPI_DMA_TFRCNT 0xFFC03830 /* ATAPI DMA mode transfer count */ -#define ATAPI_UMAIN_TFRCNT 0xFFC03834 /* ATAPI UDMAIN transfer count */ -#define ATAPI_UDMAOUT_TFRCNT 0xFFC03838 /* ATAPI UDMAOUT transfer count */ -#define ATAPI_REG_TIM_0 0xFFC03840 /* ATAPI Register Transfer Timing 0 */ -#define ATAPI_PIO_TIM_0 0xFFC03844 /* ATAPI PIO Timing 0 Register */ -#define ATAPI_PIO_TIM_1 0xFFC03848 /* ATAPI PIO Timing 1 Register */ -#define ATAPI_MULTI_TIM_0 0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */ -#define ATAPI_MULTI_TIM_1 0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */ -#define ATAPI_MULTI_TIM_2 0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_0 0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */ -#define ATAPI_ULTRA_TIM_1 0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */ -#define ATAPI_ULTRA_TIM_2 0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */ -#define ATAPI_ULTRA_TIM_3 0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */ -#define NFC_CTL 0xFFC03B00 /* NAND Control Register */ -#define NFC_STAT 0xFFC03B04 /* NAND Status Register */ -#define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */ -#define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */ -#define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */ -#define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */ -#define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */ -#define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */ -#define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */ -#define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */ -#define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */ -#define NFC_READ 0xFFC03B2C /* NAND Read Data Register */ -#define NFC_ADDR 0xFFC03B40 /* NAND Address Register */ -#define NFC_CMD 0xFFC03B44 /* NAND Command Register */ -#define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */ -#define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */ -#define EPPI0_STATUS 0xFFC01000 /* EPPI0 Status Register */ -#define EPPI0_HCOUNT 0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */ -#define EPPI0_HDELAY 0xFFC01008 /* EPPI0 Horizontal Delay Count Register */ -#define EPPI0_VCOUNT 0xFFC0100C /* EPPI0 Vertical Transfer Count Register */ -#define EPPI0_VDELAY 0xFFC01010 /* EPPI0 Vertical Delay Count Register */ -#define EPPI0_FRAME 0xFFC01014 /* EPPI0 Lines per Frame Register */ -#define EPPI0_LINE 0xFFC01018 /* EPPI0 Samples per Line Register */ -#define EPPI0_CLKDIV 0xFFC0101C /* EPPI0 Clock Divide Register */ -#define EPPI0_CONTROL 0xFFC01020 /* EPPI0 Control Register */ -#define EPPI0_FS1W_HBL 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ -#define EPPI0_FS1P_AVPL 0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ -#define EPPI0_FS2W_LVB 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ -#define EPPI0_FS2P_LAVF 0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ -#define EPPI0_CLIP 0xFFC01034 /* EPPI0 Clipping Register */ -#define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */ -#define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */ -#define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */ -#define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */ -#define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */ -#define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */ -#define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */ -#define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */ -#define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */ -#define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ -#define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ -#define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ -#define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ -#define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */ -#define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */ -#define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */ -#define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */ -#define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */ -#define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */ -#define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */ -#define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */ -#define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */ -#define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */ -#define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ -#define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ -#define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ -#define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ -#define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */ -#define CAN0_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */ -#define CAN0_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */ -#define CAN0_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */ -#define CAN0_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */ -#define CAN0_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ -#define CAN0_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */ -#define CAN0_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */ -#define CAN0_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */ -#define CAN0_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN0_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN0_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ -#define CAN0_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ -#define CAN0_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ -#define CAN0_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */ -#define CAN0_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */ -#define CAN0_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */ -#define CAN0_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */ -#define CAN0_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ -#define CAN0_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */ -#define CAN0_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */ -#define CAN0_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */ -#define CAN0_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN0_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN0_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ -#define CAN0_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ -#define CAN0_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ -#define CAN0_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */ -#define CAN0_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */ -#define CAN0_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */ -#define CAN0_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */ -#define CAN0_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */ -#define CAN0_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */ -#define CAN0_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */ -#define CAN0_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */ -#define CAN0_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */ -#define CAN0_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */ -#define CAN0_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */ -#define CAN0_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */ -#define CAN0_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */ -#define CAN0_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */ -#define CAN0_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */ -#define CAN0_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */ -#define CAN0_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ -#define CAN0_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ -#define CAN0_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ -#define CAN0_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ -#define CAN0_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ -#define CAN0_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ -#define CAN0_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ -#define CAN0_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ -#define CAN0_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ -#define CAN0_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ -#define CAN0_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ -#define CAN0_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ -#define CAN0_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ -#define CAN0_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ -#define CAN0_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ -#define CAN0_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ -#define CAN0_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ -#define CAN0_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ -#define CAN0_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ -#define CAN0_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ -#define CAN0_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ -#define CAN0_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ -#define CAN0_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ -#define CAN0_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ -#define CAN0_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ -#define CAN0_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ -#define CAN0_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ -#define CAN0_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ -#define CAN0_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ -#define CAN0_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ -#define CAN0_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ -#define CAN0_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ -#define CAN0_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ -#define CAN0_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ -#define CAN0_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ -#define CAN0_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ -#define CAN0_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ -#define CAN0_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ -#define CAN0_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ -#define CAN0_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ -#define CAN0_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ -#define CAN0_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ -#define CAN0_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ -#define CAN0_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ -#define CAN0_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ -#define CAN0_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ -#define CAN0_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ -#define CAN0_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ -#define CAN0_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ -#define CAN0_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ -#define CAN0_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ -#define CAN0_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ -#define CAN0_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ -#define CAN0_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ -#define CAN0_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ -#define CAN0_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ -#define CAN0_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ -#define CAN0_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ -#define CAN0_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ -#define CAN0_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ -#define CAN0_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ -#define CAN0_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ -#define CAN0_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ -#define CAN0_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ -#define CAN0_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ -#define CAN0_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ -#define CAN0_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ -#define CAN0_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */ -#define CAN0_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */ -#define CAN0_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ -#define CAN0_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */ -#define CAN0_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */ -#define CAN0_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ -#define CAN0_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ -#define CAN0_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ -#define CAN0_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */ -#define CAN0_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */ -#define CAN0_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ -#define CAN0_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */ -#define CAN0_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */ -#define CAN0_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ -#define CAN0_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ -#define CAN0_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ -#define CAN0_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */ -#define CAN0_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */ -#define CAN0_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ -#define CAN0_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */ -#define CAN0_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */ -#define CAN0_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ -#define CAN0_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ -#define CAN0_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ -#define CAN0_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */ -#define CAN0_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */ -#define CAN0_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ -#define CAN0_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */ -#define CAN0_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */ -#define CAN0_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ -#define CAN0_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ -#define CAN0_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ -#define CAN0_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */ -#define CAN0_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */ -#define CAN0_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ -#define CAN0_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */ -#define CAN0_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */ -#define CAN0_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ -#define CAN0_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ -#define CAN0_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ -#define CAN0_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */ -#define CAN0_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */ -#define CAN0_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ -#define CAN0_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */ -#define CAN0_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */ -#define CAN0_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ -#define CAN0_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ -#define CAN0_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ -#define CAN0_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */ -#define CAN0_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */ -#define CAN0_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ -#define CAN0_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */ -#define CAN0_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */ -#define CAN0_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ -#define CAN0_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ -#define CAN0_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ -#define CAN0_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */ -#define CAN0_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */ -#define CAN0_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ -#define CAN0_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */ -#define CAN0_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */ -#define CAN0_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ -#define CAN0_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ -#define CAN0_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ -#define CAN0_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */ -#define CAN0_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */ -#define CAN0_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ -#define CAN0_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */ -#define CAN0_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */ -#define CAN0_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ -#define CAN0_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ -#define CAN0_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ -#define CAN0_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */ -#define CAN0_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */ -#define CAN0_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ -#define CAN0_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */ -#define CAN0_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */ -#define CAN0_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ -#define CAN0_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ -#define CAN0_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ -#define CAN0_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */ -#define CAN0_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */ -#define CAN0_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ -#define CAN0_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */ -#define CAN0_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */ -#define CAN0_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ -#define CAN0_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ -#define CAN0_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ -#define CAN0_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */ -#define CAN0_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */ -#define CAN0_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ -#define CAN0_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */ -#define CAN0_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */ -#define CAN0_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ -#define CAN0_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ -#define CAN0_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ -#define CAN0_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */ -#define CAN0_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */ -#define CAN0_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ -#define CAN0_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */ -#define CAN0_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */ -#define CAN0_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ -#define CAN0_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ -#define CAN0_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ -#define CAN0_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */ -#define CAN0_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */ -#define CAN0_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ -#define CAN0_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */ -#define CAN0_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */ -#define CAN0_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ -#define CAN0_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ -#define CAN0_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ -#define CAN0_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */ -#define CAN0_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */ -#define CAN0_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ -#define CAN0_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */ -#define CAN0_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */ -#define CAN0_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ -#define CAN0_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ -#define CAN0_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ -#define CAN0_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */ -#define CAN0_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */ -#define CAN0_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ -#define CAN0_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */ -#define CAN0_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */ -#define CAN0_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ -#define CAN0_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ -#define CAN0_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ -#define CAN0_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */ -#define CAN0_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */ -#define CAN0_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ -#define CAN0_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */ -#define CAN0_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */ -#define CAN0_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ -#define CAN0_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ -#define CAN0_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ -#define CAN0_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */ -#define CAN0_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */ -#define CAN0_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ -#define CAN0_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */ -#define CAN0_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */ -#define CAN0_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ -#define CAN0_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ -#define CAN0_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ -#define CAN0_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */ -#define CAN0_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */ -#define CAN0_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ -#define CAN0_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */ -#define CAN0_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */ -#define CAN0_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ -#define CAN0_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ -#define CAN0_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ -#define CAN0_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */ -#define CAN0_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */ -#define CAN0_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ -#define CAN0_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */ -#define CAN0_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */ -#define CAN0_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ -#define CAN0_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ -#define CAN0_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ -#define CAN0_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */ -#define CAN0_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */ -#define CAN0_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ -#define CAN0_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */ -#define CAN0_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */ -#define CAN0_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ -#define CAN0_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ -#define CAN0_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ -#define CAN0_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */ -#define CAN0_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */ -#define CAN0_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ -#define CAN0_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */ -#define CAN0_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */ -#define CAN0_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ -#define CAN0_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ -#define CAN0_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ -#define CAN0_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */ -#define CAN0_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */ -#define CAN0_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ -#define CAN0_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */ -#define CAN0_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */ -#define CAN0_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ -#define CAN0_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ -#define CAN0_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ -#define CAN0_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */ -#define CAN0_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */ -#define CAN0_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ -#define CAN0_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */ -#define CAN0_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */ -#define CAN0_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ -#define CAN0_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ -#define CAN0_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ -#define CAN0_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */ -#define CAN0_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */ -#define CAN0_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ -#define CAN0_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */ -#define CAN0_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */ -#define CAN0_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ -#define CAN0_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ -#define CAN0_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ -#define CAN0_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */ -#define CAN0_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */ -#define CAN0_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ -#define CAN0_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */ -#define CAN0_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */ -#define CAN0_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ -#define CAN0_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ -#define CAN0_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ -#define CAN0_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */ -#define CAN0_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */ -#define CAN0_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ -#define CAN0_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */ -#define CAN0_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */ -#define CAN0_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ -#define CAN0_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ -#define CAN0_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ -#define CAN0_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */ -#define CAN0_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */ -#define CAN0_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ -#define CAN0_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */ -#define CAN0_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */ -#define CAN0_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ -#define CAN0_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ -#define CAN0_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ -#define CAN0_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */ -#define CAN0_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */ -#define CAN0_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ -#define CAN0_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */ -#define CAN0_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */ -#define CAN0_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ -#define CAN0_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ -#define CAN0_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ -#define CAN0_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */ -#define CAN0_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */ -#define CAN0_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ -#define CAN0_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */ -#define CAN0_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */ -#define CAN0_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ -#define CAN0_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ -#define CAN0_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ -#define CAN0_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */ -#define CAN0_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */ -#define CAN0_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ -#define CAN0_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */ -#define CAN0_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */ -#define CAN0_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ -#define CAN0_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ -#define CAN0_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ -#define CAN0_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */ -#define CAN0_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */ -#define CAN0_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ -#define CAN0_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */ -#define CAN0_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */ -#define CAN1_MC1 0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ -#define CAN1_MD1 0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */ -#define CAN1_TRS1 0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */ -#define CAN1_TRR1 0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */ -#define CAN1_TA1 0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ -#define CAN1_AA1 0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ -#define CAN1_RMP1 0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */ -#define CAN1_RML1 0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */ -#define CAN1_MBTIF1 0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ -#define CAN1_MBRIF1 0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ -#define CAN1_MBIM1 0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ -#define CAN1_RFH1 0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ -#define CAN1_OPSS1 0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ -#define CAN1_MC2 0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ -#define CAN1_MD2 0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */ -#define CAN1_TRS2 0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */ -#define CAN1_TRR2 0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */ -#define CAN1_TA2 0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ -#define CAN1_AA2 0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ -#define CAN1_RMP2 0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */ -#define CAN1_RML2 0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */ -#define CAN1_MBTIF2 0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ -#define CAN1_MBRIF2 0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ -#define CAN1_MBIM2 0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ -#define CAN1_RFH2 0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ -#define CAN1_OPSS2 0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ -#define CAN1_CLOCK 0xFFC03280 /* CAN Controller 1 Clock Register */ -#define CAN1_TIMING 0xFFC03284 /* CAN Controller 1 Timing Register */ -#define CAN1_DEBUG 0xFFC03288 /* CAN Controller 1 Debug Register */ -#define CAN1_STATUS 0xFFC0328C /* CAN Controller 1 Global Status Register */ -#define CAN1_CEC 0xFFC03290 /* CAN Controller 1 Error Counter Register */ -#define CAN1_GIS 0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */ -#define CAN1_GIM 0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */ -#define CAN1_GIF 0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */ -#define CAN1_CONTROL 0xFFC032A0 /* CAN Controller 1 Master Control Register */ -#define CAN1_INTR 0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */ -#define CAN1_MBTD 0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */ -#define CAN1_EWR 0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */ -#define CAN1_ESR 0xFFC032B4 /* CAN Controller 1 Error Status Register */ -#define CAN1_UCCNT 0xFFC032C4 /* CAN Controller 1 Universal Counter Register */ -#define CAN1_UCRC 0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */ -#define CAN1_UCCNF 0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */ -#define CAN1_AM00L 0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ -#define CAN1_AM00H 0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ -#define CAN1_AM01L 0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ -#define CAN1_AM01H 0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ -#define CAN1_AM02L 0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ -#define CAN1_AM02H 0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ -#define CAN1_AM03L 0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ -#define CAN1_AM03H 0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ -#define CAN1_AM04L 0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ -#define CAN1_AM04H 0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ -#define CAN1_AM05L 0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ -#define CAN1_AM05H 0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ -#define CAN1_AM06L 0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ -#define CAN1_AM06H 0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ -#define CAN1_AM07L 0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ -#define CAN1_AM07H 0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ -#define CAN1_AM08L 0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ -#define CAN1_AM08H 0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ -#define CAN1_AM09L 0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ -#define CAN1_AM09H 0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ -#define CAN1_AM10L 0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ -#define CAN1_AM10H 0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ -#define CAN1_AM11L 0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ -#define CAN1_AM11H 0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ -#define CAN1_AM12L 0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ -#define CAN1_AM12H 0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ -#define CAN1_AM13L 0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ -#define CAN1_AM13H 0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ -#define CAN1_AM14L 0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ -#define CAN1_AM14H 0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ -#define CAN1_AM15L 0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ -#define CAN1_AM15H 0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ -#define CAN1_AM16L 0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ -#define CAN1_AM16H 0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ -#define CAN1_AM17L 0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ -#define CAN1_AM17H 0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ -#define CAN1_AM18L 0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ -#define CAN1_AM18H 0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ -#define CAN1_AM19L 0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ -#define CAN1_AM19H 0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ -#define CAN1_AM20L 0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ -#define CAN1_AM20H 0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ -#define CAN1_AM21L 0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ -#define CAN1_AM21H 0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ -#define CAN1_AM22L 0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ -#define CAN1_AM22H 0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ -#define CAN1_AM23L 0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ -#define CAN1_AM23H 0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ -#define CAN1_AM24L 0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ -#define CAN1_AM24H 0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ -#define CAN1_AM25L 0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ -#define CAN1_AM25H 0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ -#define CAN1_AM26L 0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ -#define CAN1_AM26H 0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ -#define CAN1_AM27L 0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ -#define CAN1_AM27H 0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ -#define CAN1_AM28L 0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ -#define CAN1_AM28H 0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ -#define CAN1_AM29L 0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ -#define CAN1_AM29H 0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ -#define CAN1_AM30L 0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ -#define CAN1_AM30H 0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ -#define CAN1_AM31L 0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ -#define CAN1_AM31H 0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ -#define CAN1_MB00_DATA0 0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ -#define CAN1_MB00_DATA1 0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ -#define CAN1_MB00_DATA2 0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ -#define CAN1_MB00_DATA3 0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */ -#define CAN1_MB00_LENGTH 0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */ -#define CAN1_MB00_TIMESTAMP 0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ -#define CAN1_MB00_ID0 0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ -#define CAN1_MB00_ID1 0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */ -#define CAN1_MB01_DATA0 0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ -#define CAN1_MB01_DATA1 0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ -#define CAN1_MB01_DATA2 0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ -#define CAN1_MB01_DATA3 0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */ -#define CAN1_MB01_LENGTH 0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */ -#define CAN1_MB01_TIMESTAMP 0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ -#define CAN1_MB01_ID0 0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ -#define CAN1_MB01_ID1 0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */ -#define CAN1_MB02_DATA0 0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ -#define CAN1_MB02_DATA1 0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ -#define CAN1_MB02_DATA2 0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ -#define CAN1_MB02_DATA3 0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */ -#define CAN1_MB02_LENGTH 0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */ -#define CAN1_MB02_TIMESTAMP 0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ -#define CAN1_MB02_ID0 0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ -#define CAN1_MB02_ID1 0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */ -#define CAN1_MB03_DATA0 0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ -#define CAN1_MB03_DATA1 0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ -#define CAN1_MB03_DATA2 0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ -#define CAN1_MB03_DATA3 0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */ -#define CAN1_MB03_LENGTH 0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */ -#define CAN1_MB03_TIMESTAMP 0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ -#define CAN1_MB03_ID0 0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ -#define CAN1_MB03_ID1 0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */ -#define CAN1_MB04_DATA0 0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ -#define CAN1_MB04_DATA1 0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ -#define CAN1_MB04_DATA2 0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ -#define CAN1_MB04_DATA3 0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */ -#define CAN1_MB04_LENGTH 0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */ -#define CAN1_MB04_TIMESTAMP 0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ -#define CAN1_MB04_ID0 0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ -#define CAN1_MB04_ID1 0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */ -#define CAN1_MB05_DATA0 0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ -#define CAN1_MB05_DATA1 0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ -#define CAN1_MB05_DATA2 0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ -#define CAN1_MB05_DATA3 0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */ -#define CAN1_MB05_LENGTH 0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */ -#define CAN1_MB05_TIMESTAMP 0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ -#define CAN1_MB05_ID0 0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */ -#define CAN1_MB05_ID1 0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */ -#define CAN1_MB06_DATA0 0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ -#define CAN1_MB06_DATA1 0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ -#define CAN1_MB06_DATA2 0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ -#define CAN1_MB06_DATA3 0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */ -#define CAN1_MB06_LENGTH 0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */ -#define CAN1_MB06_TIMESTAMP 0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ -#define CAN1_MB06_ID0 0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */ -#define CAN1_MB06_ID1 0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */ -#define CAN1_MB07_DATA0 0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ -#define CAN1_MB07_DATA1 0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ -#define CAN1_MB07_DATA2 0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ -#define CAN1_MB07_DATA3 0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */ -#define CAN1_MB07_LENGTH 0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */ -#define CAN1_MB07_TIMESTAMP 0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ -#define CAN1_MB07_ID0 0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */ -#define CAN1_MB07_ID1 0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */ -#define CAN1_MB08_DATA0 0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ -#define CAN1_MB08_DATA1 0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ -#define CAN1_MB08_DATA2 0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ -#define CAN1_MB08_DATA3 0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */ -#define CAN1_MB08_LENGTH 0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */ -#define CAN1_MB08_TIMESTAMP 0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ -#define CAN1_MB08_ID0 0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ -#define CAN1_MB08_ID1 0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */ -#define CAN1_MB09_DATA0 0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ -#define CAN1_MB09_DATA1 0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ -#define CAN1_MB09_DATA2 0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ -#define CAN1_MB09_DATA3 0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */ -#define CAN1_MB09_LENGTH 0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */ -#define CAN1_MB09_TIMESTAMP 0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ -#define CAN1_MB09_ID0 0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ -#define CAN1_MB09_ID1 0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */ -#define CAN1_MB10_DATA0 0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ -#define CAN1_MB10_DATA1 0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ -#define CAN1_MB10_DATA2 0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ -#define CAN1_MB10_DATA3 0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */ -#define CAN1_MB10_LENGTH 0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */ -#define CAN1_MB10_TIMESTAMP 0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ -#define CAN1_MB10_ID0 0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ -#define CAN1_MB10_ID1 0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */ -#define CAN1_MB11_DATA0 0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ -#define CAN1_MB11_DATA1 0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ -#define CAN1_MB11_DATA2 0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ -#define CAN1_MB11_DATA3 0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */ -#define CAN1_MB11_LENGTH 0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */ -#define CAN1_MB11_TIMESTAMP 0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ -#define CAN1_MB11_ID0 0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ -#define CAN1_MB11_ID1 0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */ -#define CAN1_MB12_DATA0 0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ -#define CAN1_MB12_DATA1 0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ -#define CAN1_MB12_DATA2 0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ -#define CAN1_MB12_DATA3 0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */ -#define CAN1_MB12_LENGTH 0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */ -#define CAN1_MB12_TIMESTAMP 0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ -#define CAN1_MB12_ID0 0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ -#define CAN1_MB12_ID1 0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */ -#define CAN1_MB13_DATA0 0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ -#define CAN1_MB13_DATA1 0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ -#define CAN1_MB13_DATA2 0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ -#define CAN1_MB13_DATA3 0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */ -#define CAN1_MB13_LENGTH 0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */ -#define CAN1_MB13_TIMESTAMP 0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ -#define CAN1_MB13_ID0 0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */ -#define CAN1_MB13_ID1 0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */ -#define CAN1_MB14_DATA0 0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ -#define CAN1_MB14_DATA1 0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ -#define CAN1_MB14_DATA2 0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ -#define CAN1_MB14_DATA3 0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */ -#define CAN1_MB14_LENGTH 0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */ -#define CAN1_MB14_TIMESTAMP 0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ -#define CAN1_MB14_ID0 0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */ -#define CAN1_MB14_ID1 0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */ -#define CAN1_MB15_DATA0 0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ -#define CAN1_MB15_DATA1 0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ -#define CAN1_MB15_DATA2 0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ -#define CAN1_MB15_DATA3 0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */ -#define CAN1_MB15_LENGTH 0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */ -#define CAN1_MB15_TIMESTAMP 0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ -#define CAN1_MB15_ID0 0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */ -#define CAN1_MB15_ID1 0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */ -#define CAN1_MB16_DATA0 0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ -#define CAN1_MB16_DATA1 0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ -#define CAN1_MB16_DATA2 0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ -#define CAN1_MB16_DATA3 0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */ -#define CAN1_MB16_LENGTH 0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */ -#define CAN1_MB16_TIMESTAMP 0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ -#define CAN1_MB16_ID0 0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ -#define CAN1_MB16_ID1 0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */ -#define CAN1_MB17_DATA0 0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ -#define CAN1_MB17_DATA1 0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ -#define CAN1_MB17_DATA2 0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ -#define CAN1_MB17_DATA3 0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */ -#define CAN1_MB17_LENGTH 0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */ -#define CAN1_MB17_TIMESTAMP 0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ -#define CAN1_MB17_ID0 0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ -#define CAN1_MB17_ID1 0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */ -#define CAN1_MB18_DATA0 0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ -#define CAN1_MB18_DATA1 0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ -#define CAN1_MB18_DATA2 0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ -#define CAN1_MB18_DATA3 0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */ -#define CAN1_MB18_LENGTH 0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */ -#define CAN1_MB18_TIMESTAMP 0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ -#define CAN1_MB18_ID0 0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ -#define CAN1_MB18_ID1 0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */ -#define CAN1_MB19_DATA0 0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ -#define CAN1_MB19_DATA1 0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ -#define CAN1_MB19_DATA2 0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ -#define CAN1_MB19_DATA3 0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */ -#define CAN1_MB19_LENGTH 0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */ -#define CAN1_MB19_TIMESTAMP 0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ -#define CAN1_MB19_ID0 0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ -#define CAN1_MB19_ID1 0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */ -#define CAN1_MB20_DATA0 0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ -#define CAN1_MB20_DATA1 0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ -#define CAN1_MB20_DATA2 0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ -#define CAN1_MB20_DATA3 0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */ -#define CAN1_MB20_LENGTH 0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */ -#define CAN1_MB20_TIMESTAMP 0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ -#define CAN1_MB20_ID0 0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ -#define CAN1_MB20_ID1 0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */ -#define CAN1_MB21_DATA0 0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ -#define CAN1_MB21_DATA1 0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ -#define CAN1_MB21_DATA2 0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ -#define CAN1_MB21_DATA3 0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */ -#define CAN1_MB21_LENGTH 0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */ -#define CAN1_MB21_TIMESTAMP 0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ -#define CAN1_MB21_ID0 0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */ -#define CAN1_MB21_ID1 0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */ -#define CAN1_MB22_DATA0 0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ -#define CAN1_MB22_DATA1 0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ -#define CAN1_MB22_DATA2 0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ -#define CAN1_MB22_DATA3 0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */ -#define CAN1_MB22_LENGTH 0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */ -#define CAN1_MB22_TIMESTAMP 0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ -#define CAN1_MB22_ID0 0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */ -#define CAN1_MB22_ID1 0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */ -#define CAN1_MB23_DATA0 0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ -#define CAN1_MB23_DATA1 0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ -#define CAN1_MB23_DATA2 0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ -#define CAN1_MB23_DATA3 0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */ -#define CAN1_MB23_LENGTH 0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */ -#define CAN1_MB23_TIMESTAMP 0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ -#define CAN1_MB23_ID0 0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */ -#define CAN1_MB23_ID1 0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */ -#define CAN1_MB24_DATA0 0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ -#define CAN1_MB24_DATA1 0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ -#define CAN1_MB24_DATA2 0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ -#define CAN1_MB24_DATA3 0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */ -#define CAN1_MB24_LENGTH 0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */ -#define CAN1_MB24_TIMESTAMP 0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ -#define CAN1_MB24_ID0 0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ -#define CAN1_MB24_ID1 0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */ -#define CAN1_MB25_DATA0 0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ -#define CAN1_MB25_DATA1 0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ -#define CAN1_MB25_DATA2 0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ -#define CAN1_MB25_DATA3 0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */ -#define CAN1_MB25_LENGTH 0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */ -#define CAN1_MB25_TIMESTAMP 0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ -#define CAN1_MB25_ID0 0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ -#define CAN1_MB25_ID1 0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */ -#define CAN1_MB26_DATA0 0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ -#define CAN1_MB26_DATA1 0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ -#define CAN1_MB26_DATA2 0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ -#define CAN1_MB26_DATA3 0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */ -#define CAN1_MB26_LENGTH 0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */ -#define CAN1_MB26_TIMESTAMP 0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ -#define CAN1_MB26_ID0 0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ -#define CAN1_MB26_ID1 0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */ -#define CAN1_MB27_DATA0 0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ -#define CAN1_MB27_DATA1 0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ -#define CAN1_MB27_DATA2 0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ -#define CAN1_MB27_DATA3 0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */ -#define CAN1_MB27_LENGTH 0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */ -#define CAN1_MB27_TIMESTAMP 0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ -#define CAN1_MB27_ID0 0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ -#define CAN1_MB27_ID1 0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */ -#define CAN1_MB28_DATA0 0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ -#define CAN1_MB28_DATA1 0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ -#define CAN1_MB28_DATA2 0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ -#define CAN1_MB28_DATA3 0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */ -#define CAN1_MB28_LENGTH 0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */ -#define CAN1_MB28_TIMESTAMP 0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ -#define CAN1_MB28_ID0 0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ -#define CAN1_MB28_ID1 0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */ -#define CAN1_MB29_DATA0 0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ -#define CAN1_MB29_DATA1 0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ -#define CAN1_MB29_DATA2 0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ -#define CAN1_MB29_DATA3 0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */ -#define CAN1_MB29_LENGTH 0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */ -#define CAN1_MB29_TIMESTAMP 0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ -#define CAN1_MB29_ID0 0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */ -#define CAN1_MB29_ID1 0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */ -#define CAN1_MB30_DATA0 0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ -#define CAN1_MB30_DATA1 0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ -#define CAN1_MB30_DATA2 0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ -#define CAN1_MB30_DATA3 0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */ -#define CAN1_MB30_LENGTH 0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */ -#define CAN1_MB30_TIMESTAMP 0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ -#define CAN1_MB30_ID0 0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */ -#define CAN1_MB30_ID1 0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */ -#define CAN1_MB31_DATA0 0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ -#define CAN1_MB31_DATA1 0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ -#define CAN1_MB31_DATA2 0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ -#define CAN1_MB31_DATA3 0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */ -#define CAN1_MB31_LENGTH 0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */ -#define CAN1_MB31_TIMESTAMP 0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ -#define CAN1_MB31_ID0 0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */ -#define CAN1_MB31_ID1 0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */ -#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ -#define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */ -#define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */ -#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ -#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ -#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */ -#define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */ -#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ -#define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */ -#define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */ -#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ -#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ -#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */ -#define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */ -#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ -#define SPI2_FLG 0xFFC02404 /* SPI2 Flag Register */ -#define SPI2_STAT 0xFFC02408 /* SPI2 Status Register */ -#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ -#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ -#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud Rate Register */ -#define SPI2_SHADOW 0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */ -#define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */ -#define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */ -#define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */ -#define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */ -#define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */ -#define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */ -#define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */ -#define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */ -#define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */ -#define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */ -#define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */ -#define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */ -#define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */ -#define TWI1_CLKDIV 0xFFC02200 /* Clock Divider Register */ -#define TWI1_CONTROL 0xFFC02204 /* TWI Control Register */ -#define TWI1_SLAVE_CTL 0xFFC02208 /* TWI Slave Mode Control Register */ -#define TWI1_SLAVE_STAT 0xFFC0220C /* TWI Slave Mode Status Register */ -#define TWI1_SLAVE_ADDR 0xFFC02210 /* TWI Slave Mode Address Register */ -#define TWI1_MASTER_CTL 0xFFC02214 /* TWI Master Mode Control Register */ -#define TWI1_MASTER_STAT 0xFFC02218 /* TWI Master Mode Status Register */ -#define TWI1_MASTER_ADDR 0xFFC0221C /* TWI Master Mode Address Register */ -#define TWI1_INT_STAT 0xFFC02220 /* TWI Interrupt Status Register */ -#define TWI1_INT_MASK 0xFFC02224 /* TWI Interrupt Mask Register */ -#define TWI1_FIFO_CTL 0xFFC02228 /* TWI FIFO Control Register */ -#define TWI1_FIFO_STAT 0xFFC0222C /* TWI FIFO Status Register */ -#define TWI1_XMT_DATA8 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */ -#define TWI1_XMT_DATA16 0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */ -#define TWI1_RCV_DATA8 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */ -#define TWI1_RCV_DATA16 0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 Transmit Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Receive Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Receive Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 Receive Data Register */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */ -#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ -#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ -#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */ -#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */ -#define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */ -#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */ -#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */ -#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */ -#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */ -#define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */ -#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ -#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */ -#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */ -#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ -#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */ -#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */ -#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */ -#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */ -#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */ -#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */ -#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */ -#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */ -#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ -#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ -#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */ -#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */ -#define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */ -#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */ -#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */ -#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */ -#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */ -#define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */ -#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ -#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */ -#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */ -#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ -#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */ -#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */ -#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */ -#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */ -#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */ -#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */ -#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */ -#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */ -#define UART0_GCTL 0xFFC00408 /* Global Control Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* Scratch Register */ -#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */ -#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */ -#define UART0_THR 0xFFC00428 /* Transmit Hold Register */ -#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */ -#define UART1_GCTL 0xFFC02008 /* Global Control Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* Scratch Register */ -#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */ -#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */ -#define UART1_THR 0xFFC02028 /* Transmit Hold Register */ -#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */ -#define UART2_DLL 0xFFC02100 /* Divisor Latch Low Byte */ -#define UART2_DLH 0xFFC02104 /* Divisor Latch High Byte */ -#define UART2_GCTL 0xFFC02108 /* Global Control Register */ -#define UART2_LCR 0xFFC0210C /* Line Control Register */ -#define UART2_MCR 0xFFC02110 /* Modem Control Register */ -#define UART2_LSR 0xFFC02114 /* Line Status Register */ -#define UART2_MSR 0xFFC02118 /* Modem Status Register */ -#define UART2_SCR 0xFFC0211C /* Scratch Register */ -#define UART2_IER_SET 0xFFC02120 /* Interrupt Enable Register Set */ -#define UART2_IER_CLEAR 0xFFC02124 /* Interrupt Enable Register Clear */ -#define UART2_THR 0xFFC02128 /* Transmit Hold Register */ -#define UART2_RBR 0xFFC0212C /* Receive Buffer Register */ -#define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */ -#define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */ -#define UART3_GCTL 0xFFC03108 /* Global Control Register */ -#define UART3_LCR 0xFFC0310C /* Line Control Register */ -#define UART3_MCR 0xFFC03110 /* Modem Control Register */ -#define UART3_LSR 0xFFC03114 /* Line Status Register */ -#define UART3_MSR 0xFFC03118 /* Modem Status Register */ -#define UART3_SCR 0xFFC0311C /* Scratch Register */ -#define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */ -#define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */ -#define UART3_THR 0xFFC03128 /* Transmit Hold Register */ -#define UART3_RBR 0xFFC0312C /* Receive Buffer Register */ -#define USB_FADDR 0xFFC03C00 /* Function address register */ -#define USB_POWER 0xFFC03C04 /* Power management register */ -#define USB_INTRTX 0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03C10 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03C14 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03C18 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC03C1C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03C20 /* USB frame number */ -#define USB_INDEX 0xFFC03C24 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03C28 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03C30 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03C40 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03C48 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC03C4C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03C80 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03C88 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03C90 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03C98 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC03CA0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC03CA8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC03CB0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC03CB8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03D00 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03D04 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03D08 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03D48 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03D50 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03D54 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03D58 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC03DE0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC03DE4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03E04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03E0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03E44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03E4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03E84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03E8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03EC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ECC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03F04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03F0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03F44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03F4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03F84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03F8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03FC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03FCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC04000 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC04004 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC04024 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC04044 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC04064 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC04084 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC040A4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC040C4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC040E4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -#endif /* __BFIN_DEF_ADSP_EDN_BF549_extended__ */ diff --git a/include/asm-blackfin/mach-bf548/BF541_cdef.h b/include/asm-blackfin/mach-bf548/BF541_cdef.h deleted file mode 100644 index 1b8c79b..0000000 --- a/include/asm-blackfin/mach-bf548/BF541_cdef.h +++ /dev/null @@ -1,323 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF541_proc__ -#define __BFIN_CDEF_ADSP_BF541_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF542-extended_cdef.h" - -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) - -#endif /* __BFIN_CDEF_ADSP_BF541_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF541_def.h b/include/asm-blackfin/mach-bf548/BF541_def.h deleted file mode 100644 index 1469ac2..0000000 --- a/include/asm-blackfin/mach-bf548/BF541_def.h +++ /dev/null @@ -1,117 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF541_proc__ -#define __BFIN_DEF_ADSP_BF541_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF542-extended_def.h" - -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ - -#endif /* __BFIN_DEF_ADSP_BF541_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF542_cdef.h b/include/asm-blackfin/mach-bf548/BF542_cdef.h deleted file mode 100644 index 306b5f1..0000000 --- a/include/asm-blackfin/mach-bf548/BF542_cdef.h +++ /dev/null @@ -1,323 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF542_proc__ -#define __BFIN_CDEF_ADSP_BF542_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF542-extended_cdef.h" - -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) - -#endif /* __BFIN_CDEF_ADSP_BF542_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF542_def.h b/include/asm-blackfin/mach-bf548/BF542_def.h deleted file mode 100644 index 1324a13..0000000 --- a/include/asm-blackfin/mach-bf548/BF542_def.h +++ /dev/null @@ -1,117 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF542_proc__ -#define __BFIN_DEF_ADSP_BF542_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF542-extended_def.h" - -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ - -#endif /* __BFIN_DEF_ADSP_BF542_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF544_cdef.h b/include/asm-blackfin/mach-bf548/BF544_cdef.h deleted file mode 100644 index 47ef6e1..0000000 --- a/include/asm-blackfin/mach-bf548/BF544_cdef.h +++ /dev/null @@ -1,323 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF544_proc__ -#define __BFIN_CDEF_ADSP_BF544_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF544-extended_cdef.h" - -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) - -#endif /* __BFIN_CDEF_ADSP_BF544_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF544_def.h b/include/asm-blackfin/mach-bf548/BF544_def.h deleted file mode 100644 index aef6e48..0000000 --- a/include/asm-blackfin/mach-bf548/BF544_def.h +++ /dev/null @@ -1,117 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF544_proc__ -#define __BFIN_DEF_ADSP_BF544_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF544-extended_def.h" - -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ - -#endif /* __BFIN_DEF_ADSP_BF544_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF547_cdef.h b/include/asm-blackfin/mach-bf548/BF547_cdef.h deleted file mode 100644 index 42d041a..0000000 --- a/include/asm-blackfin/mach-bf548/BF547_cdef.h +++ /dev/null @@ -1,323 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF547_proc__ -#define __BFIN_CDEF_ADSP_BF547_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF547-extended_cdef.h" - -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) - -#endif /* __BFIN_CDEF_ADSP_BF547_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF547_def.h b/include/asm-blackfin/mach-bf548/BF547_def.h deleted file mode 100644 index ce7c880..0000000 --- a/include/asm-blackfin/mach-bf548/BF547_def.h +++ /dev/null @@ -1,117 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF547_proc__ -#define __BFIN_DEF_ADSP_BF547_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF547-extended_def.h" - -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ - -#endif /* __BFIN_DEF_ADSP_BF547_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF548_cdef.h b/include/asm-blackfin/mach-bf548/BF548_cdef.h deleted file mode 100644 index cf02834..0000000 --- a/include/asm-blackfin/mach-bf548/BF548_cdef.h +++ /dev/null @@ -1,323 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF548_proc__ -#define __BFIN_CDEF_ADSP_BF548_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF548-extended_cdef.h" - -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) - -#endif /* __BFIN_CDEF_ADSP_BF548_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF548_def.h b/include/asm-blackfin/mach-bf548/BF548_def.h deleted file mode 100644 index e02e843..0000000 --- a/include/asm-blackfin/mach-bf548/BF548_def.h +++ /dev/null @@ -1,117 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF548_proc__ -#define __BFIN_DEF_ADSP_BF548_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF548-extended_def.h" - -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ - -#endif /* __BFIN_DEF_ADSP_BF548_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF549_cdef.h b/include/asm-blackfin/mach-bf548/BF549_cdef.h deleted file mode 100644 index 3514cef..0000000 --- a/include/asm-blackfin/mach-bf548/BF549_cdef.h +++ /dev/null @@ -1,323 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF549_proc__ -#define __BFIN_CDEF_ADSP_BF549_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF549-extended_cdef.h" - -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) - -#endif /* __BFIN_CDEF_ADSP_BF549_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/BF549_def.h b/include/asm-blackfin/mach-bf548/BF549_def.h deleted file mode 100644 index a16ff5a..0000000 --- a/include/asm-blackfin/mach-bf548/BF549_def.h +++ /dev/null @@ -1,117 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF549_proc__ -#define __BFIN_DEF_ADSP_BF549_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF549-extended_def.h" - -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ - -#endif /* __BFIN_DEF_ADSP_BF549_proc__ */ diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h deleted file mode 100644 index 192dd67..0000000 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * File: include/asm-blackfin/mach-bf548/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -/* This file should be up to date with: - * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ -#define ANOMALY_05000074 (1) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (1) -/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) -/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) -/* TWI Slave Boot Mode Is Not Functional */ -#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) -/* External FIFO Boot Mode Is Not Functional */ -#define ANOMALY_05000325 (__SILICON_REVISION__ < 2) -/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ -#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) -/* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) -/* Synchronous Burst Flash Boot Mode Is Not Functional */ -#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) -/* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) -/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ -#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) -/* Inadequate Rotary Debounce Logic Duration */ -#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) -/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ -#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) -/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) -/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ -#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) -/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ -#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) -/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ -#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) -/* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) -/* USB Calibration Value to use */ -#define ANOMALY_05000346_value 0x5411 -/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) -/* Data Lost when Core Reads SDH Data FIFO */ -#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) -/* PLL Status Register Is Inaccurate */ -#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) -/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -#define ANOMALY_05000353 (__SILICON_REVISION__ < 2) -/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (__SILICON_REVISION__ < 1) -/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ -#define ANOMALY_05000356 (__SILICON_REVISION__ < 1) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) -/* External Memory Read Access Hangs Core With PLL Bypass */ -#define ANOMALY_05000360 (1) -/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ -#define ANOMALY_05000365 (1) -/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ -#define ANOMALY_05000367 (__SILICON_REVISION__ < 1) -/* Addressing Conflict between Boot ROM and Asynchronous Memory */ -#define ANOMALY_05000369 (1) -/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ -#define ANOMALY_05000370 (__SILICON_REVISION__ < 1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) -/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ -#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) -/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ -#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) -/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ -#define ANOMALY_05000379 (1) -/* 8-Bit NAND Flash Boot Mode Not Functional */ -#define ANOMALY_05000382 (__SILICON_REVISION__ < 1) -/* Some ATAPI Modes Are Not Functional */ -#define ANOMALY_05000383 (1) -/* Boot from OTP Memory Not Functional */ -#define ANOMALY_05000385 (__SILICON_REVISION__ < 1) -/* bfrom_SysControl() Firmware Routine Not Functional */ -#define ANOMALY_05000386 (__SILICON_REVISION__ < 1) -/* Programmable Preboot Settings Not Functional */ -#define ANOMALY_05000387 (__SILICON_REVISION__ < 1) -/* CRC32 Checksum Support Not Functional */ -#define ANOMALY_05000388 (__SILICON_REVISION__ < 1) -/* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (__SILICON_REVISION__ < 1) -/* Changed Meaning of BCODE Field in SYSCR Register */ -#define ANOMALY_05000390 (__SILICON_REVISION__ < 1) -/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ -#define ANOMALY_05000391 (__SILICON_REVISION__ < 1) -/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (__SILICON_REVISION__ < 1) -/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (__SILICON_REVISION__ < 1) -/* Log Buffer Not Functional */ -#define ANOMALY_05000394 (__SILICON_REVISION__ < 1) -/* Hook Routine Not Functional */ -#define ANOMALY_05000395 (__SILICON_REVISION__ < 1) -/* Header Indirect Bit Not Functional */ -#define ANOMALY_05000396 (__SILICON_REVISION__ < 1) -/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ -#define ANOMALY_05000397 (__SILICON_REVISION__ < 1) -/* Lockbox SESR Disallows Certain User Interrupts */ -#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) -/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ -#define ANOMALY_05000405 (1) -/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */ -#define ANOMALY_05000406 (__SILICON_REVISION__ < 2) -/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ -#define ANOMALY_05000407 (__SILICON_REVISION__ < 2) -/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ -#define ANOMALY_05000408 (1) -/* Lockbox firmware leaves MDMA0 channel enabled */ -#define ANOMALY_05000409 (__SILICON_REVISION__ < 2) -/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (__SILICON_REVISION__ < 2) -/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */ -#define ANOMALY_05000413 (__SILICON_REVISION__ < 2) -/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ -#define ANOMALY_05000414 (__SILICON_REVISION__ < 2) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ -#define ANOMALY_05000427 (__SILICON_REVISION__ < 2) -/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ -#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) -/* Software System Reset Corrupts PLL_LOCKCNT Register */ -#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) -/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ -#define ANOMALY_05000431 (__SILICON_REVISION__ < 3) -/* OTP Write Accesses Not Supported */ -#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) -/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ -#define ANOMALY_05000446 (1) -/* UART IrDA Receiver Fails on Extended Bit Pulses */ -#define ANOMALY_05000447 (1) -/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */ -#define ANOMALY_05000448 (__SILICON_REVISION__ == 1) -/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ -#define ANOMALY_05000449 (__SILICON_REVISION__ == 1) -/* USB DMA Mode 1 Short Packet Data Corruption */ -#define ANOMALY_05000450 (1 - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000125 (0) -#define ANOMALY_05000158 (0) -#define ANOMALY_05000171 (0) -#define ANOMALY_05000183 (0) -#define ANOMALY_05000198 (0) -#define ANOMALY_05000227 (0) -#define ANOMALY_05000230 (0) -#define ANOMALY_05000242 (0) -#define ANOMALY_05000244 (0) -#define ANOMALY_05000261 (0) -#define ANOMALY_05000263 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000273 (0) -#define ANOMALY_05000278 (0) -#define ANOMALY_05000305 (0) -#define ANOMALY_05000307 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000363 (0) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000435 (0) - -#endif diff --git a/include/asm-blackfin/mach-bf548/def_local.h b/include/asm-blackfin/mach-bf548/def_local.h deleted file mode 100644 index 81eca83..0000000 --- a/include/asm-blackfin/mach-bf548/def_local.h +++ /dev/null @@ -1,2 +0,0 @@ -#include "mem_map.h" -#include "ports.h" diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h deleted file mode 100644 index 4f94397..0000000 --- a/include/asm-blackfin/mach-bf548/mem_map.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Common Blackfin memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BF54X_MEM_MAP_H__ -#define __BF54X_MEM_MAP_H__ - -#define L1_DATA_A_SRAM (0xFF800000) -#define L1_DATA_A_SRAM_SIZE (0x4000) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM (0xFF900000) -#define L1_DATA_B_SRAM_SIZE (0x4000) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM (0xFFA00000) -#define L1_INST_SRAM_SIZE (0xC000) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) - -#endif diff --git a/include/asm-blackfin/mach-bf548/ports.h b/include/asm-blackfin/mach-bf548/ports.h deleted file mode 100644 index 50054f3..0000000 --- a/include/asm-blackfin/mach-bf548/ports.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Port Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT__ -#define __BFIN_PERIPHERAL_PORT__ - -/* PORTx_MUX Masks */ -#define PORT_x_MUX_0_MASK 0x00000003 -#define PORT_x_MUX_1_MASK 0x0000000C -#define PORT_x_MUX_2_MASK 0x00000030 -#define PORT_x_MUX_3_MASK 0x000000C0 -#define PORT_x_MUX_4_MASK 0x00000300 -#define PORT_x_MUX_5_MASK 0x00000C00 -#define PORT_x_MUX_6_MASK 0x00003000 -#define PORT_x_MUX_7_MASK 0x0000C000 -#define PORT_x_MUX_8_MASK 0x00030000 -#define PORT_x_MUX_9_MASK 0x000C0000 -#define PORT_x_MUX_10_MASK 0x00300000 -#define PORT_x_MUX_11_MASK 0x00C00000 -#define PORT_x_MUX_12_MASK 0x03000000 -#define PORT_x_MUX_13_MASK 0x0C000000 -#define PORT_x_MUX_14_MASK 0x30000000 -#define PORT_x_MUX_15_MASK 0xC0000000 - -#define PORT_x_MUX_FUNC_1 (0x0) -#define PORT_x_MUX_FUNC_2 (0x1) -#define PORT_x_MUX_FUNC_3 (0x2) -#define PORT_x_MUX_FUNC_4 (0x3) -#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0) -#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0) -#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0) -#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0) -#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2) -#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2) -#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2) -#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2) -#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4) -#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4) -#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4) -#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4) -#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6) -#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6) -#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6) -#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6) -#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8) -#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8) -#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8) -#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8) -#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10) -#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10) -#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10) -#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10) -#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12) -#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12) -#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12) -#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12) -#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) -#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) -#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) -#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) -#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16) -#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16) -#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16) -#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16) -#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18) -#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18) -#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18) -#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18) -#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20) -#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20) -#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20) -#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20) -#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22) -#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22) -#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22) -#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22) -#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24) -#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24) -#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24) -#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24) -#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26) -#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26) -#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26) -#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26) -#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28) -#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28) -#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28) -#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28) -#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30) -#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30) -#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30) -#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30) - -#include "../mach-common/bits/ports-a.h" -#include "../mach-common/bits/ports-b.h" -#include "../mach-common/bits/ports-c.h" -#include "../mach-common/bits/ports-d.h" -#include "../mach-common/bits/ports-e.h" -#include "../mach-common/bits/ports-f.h" -#include "../mach-common/bits/ports-g.h" -#include "../mach-common/bits/ports-h.h" -#include "../mach-common/bits/ports-i.h" -#include "../mach-common/bits/ports-j.h" - -#endif diff --git a/include/asm-blackfin/mach-bf561/BF561_cdef.h b/include/asm-blackfin/mach-bf561/BF561_cdef.h deleted file mode 100644 index e2c165a..0000000 --- a/include/asm-blackfin/mach-bf561/BF561_cdef.h +++ /dev/null @@ -1,464 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF561_proc__ -#define __BFIN_CDEF_ADSP_BF561_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h" - -#define pSRAM_BASE_ADDR ((uint32_t volatile *)SRAM_BASE_ADDR) -#define bfin_read_SRAM_BASE_ADDR() bfin_read32(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((uint32_t volatile *)DCPLB_ADDR0) -#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((uint32_t volatile *)DCPLB_ADDR1) -#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((uint32_t volatile *)DCPLB_ADDR2) -#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((uint32_t volatile *)DCPLB_ADDR3) -#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((uint32_t volatile *)DCPLB_ADDR4) -#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((uint32_t volatile *)DCPLB_ADDR5) -#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((uint32_t volatile *)DCPLB_ADDR6) -#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((uint32_t volatile *)DCPLB_ADDR7) -#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((uint32_t volatile *)DCPLB_ADDR8) -#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((uint32_t volatile *)DCPLB_ADDR9) -#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((uint32_t volatile *)DCPLB_ADDR10) -#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((uint32_t volatile *)DCPLB_ADDR11) -#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((uint32_t volatile *)DCPLB_ADDR12) -#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((uint32_t volatile *)DCPLB_ADDR13) -#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((uint32_t volatile *)DCPLB_ADDR14) -#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((uint32_t volatile *)DCPLB_ADDR15) -#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR) -#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((uint32_t volatile *)ICPLB_ADDR0) -#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((uint32_t volatile *)ICPLB_ADDR1) -#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((uint32_t volatile *)ICPLB_ADDR2) -#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((uint32_t volatile *)ICPLB_ADDR3) -#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((uint32_t volatile *)ICPLB_ADDR4) -#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((uint32_t volatile *)ICPLB_ADDR5) -#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((uint32_t volatile *)ICPLB_ADDR6) -#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((uint32_t volatile *)ICPLB_ADDR7) -#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((uint32_t volatile *)ICPLB_ADDR8) -#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((uint32_t volatile *)ICPLB_ADDR9) -#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((uint32_t volatile *)ICPLB_ADDR10) -#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((uint32_t volatile *)ICPLB_ADDR11) -#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((uint32_t volatile *)ICPLB_ADDR12) -#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((uint32_t volatile *)ICPLB_ADDR13) -#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((uint32_t volatile *)ICPLB_ADDR14) -#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((uint32_t volatile *)ICPLB_ADDR15) -#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pSICA_SWRST ((uint16_t volatile *)SICA_SWRST) -#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) -#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val) -#define pSICA_SYSCR ((uint16_t volatile *)SICA_SYSCR) -#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) -#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR, val) -#define pSICA_RVECT ((uint16_t volatile *)SICA_RVECT) -#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) -#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT, val) -#define pSICA_IMASK0 ((uint32_t volatile *)SICA_IMASK0) -#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) -#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0, val) -#define pSICA_IMASK1 ((uint32_t volatile *)SICA_IMASK1) -#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) -#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1, val) -#define pSICA_ISR0 ((uint32_t volatile *)SICA_ISR0) -#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) -#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0, val) -#define pSICA_ISR1 ((uint32_t volatile *)SICA_ISR1) -#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) -#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1, val) -#define pSICA_IWR0 ((uint32_t volatile *)SICA_IWR0) -#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) -#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0, val) -#define pSICA_IWR1 ((uint32_t volatile *)SICA_IWR1) -#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1) -#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1, val) -#define pSICA_IAR0 ((uint32_t volatile *)SICA_IAR0) -#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) -#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0, val) -#define pSICA_IAR1 ((uint32_t volatile *)SICA_IAR1) -#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) -#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1, val) -#define pSICA_IAR2 ((uint32_t volatile *)SICA_IAR2) -#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) -#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2, val) -#define pSICA_IAR3 ((uint32_t volatile *)SICA_IAR3) -#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) -#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3, val) -#define pSICA_IAR4 ((uint32_t volatile *)SICA_IAR4) -#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) -#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4, val) -#define pSICA_IAR5 ((uint32_t volatile *)SICA_IAR5) -#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) -#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5, val) -#define pSICA_IAR6 ((uint32_t volatile *)SICA_IAR6) -#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) -#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6, val) -#define pSICA_IAR7 ((uint32_t volatile *)SICA_IAR7) -#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) -#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7, val) -#define pSICB_SWRST ((uint16_t volatile *)SICB_SWRST) -#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) -#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST, val) -#define pSICB_SYSCR ((uint16_t volatile *)SICB_SYSCR) -#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR) -#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR, val) -#define pSICB_RVECT ((uint16_t volatile *)SICB_RVECT) -#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT) -#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT, val) -#define pSICB_IMASK0 ((uint32_t volatile *)SICB_IMASK0) -#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0) -#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0, val) -#define pSICB_IMASK1 ((uint32_t volatile *)SICB_IMASK1) -#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1) -#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1, val) -#define pSICB_ISR0 ((uint32_t volatile *)SICB_ISR0) -#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0) -#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0, val) -#define pSICB_ISR1 ((uint32_t volatile *)SICB_ISR1) -#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1) -#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1, val) -#define pSICB_IWR0 ((uint32_t volatile *)SICB_IWR0) -#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0) -#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0, val) -#define pSICB_IWR1 ((uint32_t volatile *)SICB_IWR1) -#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1) -#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1, val) -#define pSICB_IAR0 ((uint32_t volatile *)SICB_IAR0) -#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0) -#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0, val) -#define pSICB_IAR1 ((uint32_t volatile *)SICB_IAR1) -#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1) -#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1, val) -#define pSICB_IAR2 ((uint32_t volatile *)SICB_IAR2) -#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2) -#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2, val) -#define pSICB_IAR3 ((uint32_t volatile *)SICB_IAR3) -#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3) -#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3, val) -#define pSICB_IAR4 ((uint32_t volatile *)SICB_IAR4) -#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4) -#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4, val) -#define pSICB_IAR5 ((uint32_t volatile *)SICB_IAR5) -#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5) -#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5, val) -#define pSICB_IAR6 ((uint32_t volatile *)SICB_IAR6) -#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6) -#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6, val) -#define pSICB_IAR7 ((uint32_t volatile *)SICB_IAR7) -#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7) -#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7, val) -#define pPPI0_CONTROL ((uint16_t volatile *)PPI0_CONTROL) -#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL) -#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL, val) -#define pPPI0_STATUS ((uint16_t volatile *)PPI0_STATUS) -#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS) -#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS, val) -#define pPPI0_DELAY ((uint16_t volatile *)PPI0_DELAY) -#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY) -#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY, val) -#define pPPI0_COUNT ((uint16_t volatile *)PPI0_COUNT) -#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT) -#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT, val) -#define pPPI0_FRAME ((uint16_t volatile *)PPI0_FRAME) -#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME) -#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME, val) -#define pPPI1_CONTROL ((uint16_t volatile *)PPI1_CONTROL) -#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL) -#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL, val) -#define pPPI1_STATUS ((uint16_t volatile *)PPI1_STATUS) -#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS) -#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS, val) -#define pPPI1_DELAY ((uint16_t volatile *)PPI1_DELAY) -#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY) -#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY, val) -#define pPPI1_COUNT ((uint16_t volatile *)PPI1_COUNT) -#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT) -#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT, val) -#define pPPI1_FRAME ((uint16_t volatile *)PPI1_FRAME) -#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME) -#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((uint32_t volatile *)TBUF) -#define bfin_read_TBUF() bfin_read32(TBUF) -#define bfin_write_TBUF(val) bfin_write32(TBUF, val) -#define pPFCTL ((uint32_t volatile *)PFCTL) -#define bfin_read_PFCTL() bfin_read32(PFCTL) -#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) -#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) -#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) -#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) -#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) -#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) -#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) -#define pSRAM_BASE_ADDR_CORE_A ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_A) -#define bfin_read_SRAM_BASE_ADDR_CORE_A() bfin_read32(SRAM_BASE_ADDR_CORE_A) -#define bfin_write_SRAM_BASE_ADDR_CORE_A(val) bfin_write32(SRAM_BASE_ADDR_CORE_A, val) -#define pSRAM_BASE_ADDR_CORE_B ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_B) -#define bfin_read_SRAM_BASE_ADDR_CORE_B() bfin_read32(SRAM_BASE_ADDR_CORE_B) -#define bfin_write_SRAM_BASE_ADDR_CORE_B(val) bfin_write32(SRAM_BASE_ADDR_CORE_B, val) -#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE) -#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) -#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val) -#define pUART_THR ((uint16_t volatile *)UART_THR) -#define bfin_read_UART_THR() bfin_read16(UART_THR) -#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val) -#define pUART_RBR ((uint16_t volatile *)UART_RBR) -#define bfin_read_UART_RBR() bfin_read16(UART_RBR) -#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val) -#define pUART_DLL ((uint16_t volatile *)UART_DLL) -#define bfin_read_UART_DLL() bfin_read16(UART_DLL) -#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val) -#define pUART_DLH ((uint16_t volatile *)UART_DLH) -#define bfin_read_UART_DLH() bfin_read16(UART_DLH) -#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val) -#define pUART_IER ((uint16_t volatile *)UART_IER) -#define bfin_read_UART_IER() bfin_read16(UART_IER) -#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val) -#define pUART_IIR ((uint16_t volatile *)UART_IIR) -#define bfin_read_UART_IIR() bfin_read16(UART_IIR) -#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val) -#define pUART_LCR ((uint16_t volatile *)UART_LCR) -#define bfin_read_UART_LCR() bfin_read16(UART_LCR) -#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val) -#define pUART_MCR ((uint16_t volatile *)UART_MCR) -#define bfin_read_UART_MCR() bfin_read16(UART_MCR) -#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val) -#define pUART_LSR ((uint16_t volatile *)UART_LSR) -#define bfin_read_UART_LSR() bfin_read16(UART_LSR) -#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val) -#define pUART_MSR ((uint16_t volatile *)UART_MSR) -#define bfin_read_UART_MSR() bfin_read16(UART_MSR) -#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR, val) -#define pUART_SCR ((uint16_t volatile *)UART_SCR) -#define bfin_read_UART_SCR() bfin_read16(UART_SCR) -#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val) -#define pUART_GCTL ((uint16_t volatile *)UART_GCTL) -#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) -#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val) -#define pUART_GBL ((uint16_t volatile *)UART_GBL) -#define bfin_read_UART_GBL() bfin_read16(UART_GBL) -#define bfin_write_UART_GBL(val) bfin_write16(UART_GBL, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define pEBIU_SDBCTL ((uint32_t volatile *)EBIU_SDBCTL) -#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL, val) -#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) - -#endif /* __BFIN_CDEF_ADSP_BF561_proc__ */ diff --git a/include/asm-blackfin/mach-bf561/BF561_def.h b/include/asm-blackfin/mach-bf561/BF561_def.h deleted file mode 100644 index 8534962..0000000 --- a/include/asm-blackfin/mach-bf561/BF561_def.h +++ /dev/null @@ -1,173 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF561_proc__ -#define __BFIN_DEF_ADSP_BF561_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h" - -#define SRAM_BASE_ADDR 0xFFE00000 -#define DMEM_CONTROL 0xFFE00004 -#define DCPLB_STATUS 0xFFE00008 -#define DCPLB_FAULT_ADDR 0xFFE0000C -#define DCPLB_ADDR0 0xFFE00100 -#define DCPLB_ADDR1 0xFFE00104 -#define DCPLB_ADDR2 0xFFE00108 -#define DCPLB_ADDR3 0xFFE0010C -#define DCPLB_ADDR4 0xFFE00110 -#define DCPLB_ADDR5 0xFFE00114 -#define DCPLB_ADDR6 0xFFE00118 -#define DCPLB_ADDR7 0xFFE0011C -#define DCPLB_ADDR8 0xFFE00120 -#define DCPLB_ADDR9 0xFFE00124 -#define DCPLB_ADDR10 0xFFE00128 -#define DCPLB_ADDR11 0xFFE0012C -#define DCPLB_ADDR12 0xFFE00130 -#define DCPLB_ADDR13 0xFFE00134 -#define DCPLB_ADDR14 0xFFE00138 -#define DCPLB_ADDR15 0xFFE0013C -#define DCPLB_DATA0 0xFFE00200 -#define DCPLB_DATA1 0xFFE00204 -#define DCPLB_DATA2 0xFFE00208 -#define DCPLB_DATA3 0xFFE0020C -#define DCPLB_DATA4 0xFFE00210 -#define DCPLB_DATA5 0xFFE00214 -#define DCPLB_DATA6 0xFFE00218 -#define DCPLB_DATA7 0xFFE0021C -#define DCPLB_DATA8 0xFFE00220 -#define DCPLB_DATA9 0xFFE00224 -#define DCPLB_DATA10 0xFFE00228 -#define DCPLB_DATA11 0xFFE0022C -#define DCPLB_DATA12 0xFFE00230 -#define DCPLB_DATA13 0xFFE00234 -#define DCPLB_DATA14 0xFFE00238 -#define DCPLB_DATA15 0xFFE0023C -#define DTEST_COMMAND 0xFFE00300 -#define DTEST_DATA0 0xFFE00400 -#define DTEST_DATA1 0xFFE00404 -#define IMEM_CONTROL 0xFFE01004 -#define ICPLB_STATUS 0xFFE01008 -#define ICPLB_FAULT_ADDR 0xFFE0100C -#define ICPLB_ADDR0 0xFFE01100 -#define ICPLB_ADDR1 0xFFE01104 -#define ICPLB_ADDR2 0xFFE01108 -#define ICPLB_ADDR3 0xFFE0110C -#define ICPLB_ADDR4 0xFFE01110 -#define ICPLB_ADDR5 0xFFE01114 -#define ICPLB_ADDR6 0xFFE01118 -#define ICPLB_ADDR7 0xFFE0111C -#define ICPLB_ADDR8 0xFFE01120 -#define ICPLB_ADDR9 0xFFE01124 -#define ICPLB_ADDR10 0xFFE01128 -#define ICPLB_ADDR11 0xFFE0112C -#define ICPLB_ADDR12 0xFFE01130 -#define ICPLB_ADDR13 0xFFE01134 -#define ICPLB_ADDR14 0xFFE01138 -#define ICPLB_ADDR15 0xFFE0113C -#define ICPLB_DATA0 0xFFE01200 -#define ICPLB_DATA1 0xFFE01204 -#define ICPLB_DATA2 0xFFE01208 -#define ICPLB_DATA3 0xFFE0120C -#define ICPLB_DATA4 0xFFE01210 -#define ICPLB_DATA5 0xFFE01214 -#define ICPLB_DATA6 0xFFE01218 -#define ICPLB_DATA7 0xFFE0121C -#define ICPLB_DATA8 0xFFE01220 -#define ICPLB_DATA9 0xFFE01224 -#define ICPLB_DATA10 0xFFE01228 -#define ICPLB_DATA11 0xFFE0122C -#define ICPLB_DATA12 0xFFE01230 -#define ICPLB_DATA13 0xFFE01234 -#define ICPLB_DATA14 0xFFE01238 -#define ICPLB_DATA15 0xFFE0123C -#define ITEST_COMMAND 0xFFE01300 -#define ITEST_DATA0 0xFFE01400 -#define ITEST_DATA1 0xFFE01404 -#define SICA_SWRST 0xFFC00100 -#define SICA_SYSCR 0xFFC00104 -#define SICA_RVECT 0xFFC00108 -#define SICA_IMASK0 0xFFC0010C -#define SICA_IMASK1 0xFFC00110 -#define SICA_ISR0 0xFFC00114 -#define SICA_ISR1 0xFFC00118 -#define SICA_IWR0 0xFFC0011C -#define SICA_IWR1 0xFFC00120 -#define SICA_IAR0 0xFFC00124 -#define SICA_IAR1 0xFFC00128 -#define SICA_IAR2 0xFFC0012C -#define SICA_IAR3 0xFFC00130 -#define SICA_IAR4 0xFFC00134 -#define SICA_IAR5 0xFFC00138 -#define SICA_IAR6 0xFFC0013C -#define SICA_IAR7 0xFFC00140 -#define SICB_SWRST 0xFFC01100 -#define SICB_SYSCR 0xFFC01104 -#define SICB_RVECT 0xFFC01108 -#define SICB_IMASK0 0xFFC0110C -#define SICB_IMASK1 0xFFC01110 -#define SICB_ISR0 0xFFC01114 -#define SICB_ISR1 0xFFC01118 -#define SICB_IWR0 0xFFC0111C -#define SICB_IWR1 0xFFC01120 -#define SICB_IAR0 0xFFC01124 -#define SICB_IAR1 0xFFC01128 -#define SICB_IAR2 0xFFC0112C -#define SICB_IAR3 0xFFC01130 -#define SICB_IAR4 0xFFC01134 -#define SICB_IAR5 0xFFC01138 -#define SICB_IAR6 0xFFC0113C -#define SICB_IAR7 0xFFC01140 -#define PPI0_CONTROL 0xFFC01000 -#define PPI0_STATUS 0xFFC01004 -#define PPI0_DELAY 0xFFC0100C -#define PPI0_COUNT 0xFFC01008 -#define PPI0_FRAME 0xFFC01010 -#define PPI1_CONTROL 0xFFC01300 -#define PPI1_STATUS 0xFFC01304 -#define PPI1_DELAY 0xFFC0130C -#define PPI1_COUNT 0xFFC01308 -#define PPI1_FRAME 0xFFC01310 -#define TBUFCTL 0xFFE06000 -#define TBUFSTAT 0xFFE06004 -#define TBUF 0xFFE06100 -#define PFCTL 0xFFE08000 -#define PFCNTR0 0xFFE08100 -#define PFCNTR1 0xFFE08104 -#define SRAM_BASE_ADDR_CORE_A 0xFFE00000 -#define SRAM_BASE_ADDR_CORE_B 0xFFE00000 -#define EVT_OVERRIDE 0xFFE02100 -#define UART_THR 0xFFC00400 -#define UART_RBR 0xFFC00400 -#define UART_DLL 0xFFC00400 -#define UART_DLH 0xFFC00404 -#define UART_IER 0xFFC00404 -#define UART_IIR 0xFFC00408 -#define UART_LCR 0xFFC0040C -#define UART_MCR 0xFFC00410 -#define UART_LSR 0xFFC00414 -#define UART_MSR 0xFFC00418 -#define UART_SCR 0xFFC0041C -#define UART_GCTL 0xFFC00424 -#define UART_GBL 0xFFC00424 -#define EBIU_AMGCTL 0xFFC00A00 -#define EBIU_AMBCTL0 0xFFC00A04 -#define EBIU_AMBCTL1 0xFFC00A08 -#define EBIU_SDGCTL 0xFFC00A10 -#define EBIU_SDBCTL 0xFFC00A14 -#define EBIU_SDRRC 0xFFC00A18 -#define EBIU_SDSTAT 0xFFC00A1C -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) - -#endif /* __BFIN_DEF_ADSP_BF561_proc__ */ diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h deleted file mode 100644 index e4aa20c..0000000 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * File: include/asm-blackfin/mach-bf561/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -/* This file should be up to date with: - * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ -#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 -# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 -#endif - -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ -#define ANOMALY_05000074 (1) -/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ -#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ -#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* Testset instructions restricted to 32-bit aligned memory locations */ -#define ANOMALY_05000120 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* Erroneous exception when enabling cache */ -#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* Signbits instruction not functional under certain conditions */ -#define ANOMALY_05000127 (1) -/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ -#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) -/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ -#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) -/* Stall in multi-unit DMA operations */ -#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) -/* Allowing the SPORT RX FIFO to fill will cause an overflow */ -#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ -#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) -/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ -#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) -/* DMA and TESTSET conflict when both are accessing external memory */ -#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) -/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ -#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) -/* MDMA may lose the first few words of a descriptor chain */ -#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ -#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* IMDMA S1/D1 channel may stall */ -#define ANOMALY_05000149 (1) -/* DMA engine may lose data due to incorrect handshaking */ -#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) -/* DMA stalls when all three controllers read data from the same source */ -#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) -/* Execution stall when executing in L2 and doing external accesses */ -#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) -/* Frame Delay in SPORT Multichannel Mode */ -#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ -#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) -/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ -#define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ -#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) -/* A read from external memory may return a wrong value with data cache enabled */ -#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) -/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ -#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL<12> is not set on Reset */ -#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ -#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ -#define ANOMALY_05000166 (1) -/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ -#define ANOMALY_05000167 (1) -/* SDRAM auto-refresh and subsequent Power Ups */ -#define ANOMALY_05000168 (__SILICON_REVISION__ < 5) -/* DATA CPLB page miss can result in lost write-through cache data writes */ -#define ANOMALY_05000169 (__SILICON_REVISION__ < 5) -/* Boot-ROM code modifies SICA_IWRx wakeup registers */ -#define ANOMALY_05000171 (__SILICON_REVISION__ < 5) -/* DSPID register values incorrect */ -#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) -/* DMA vs Core accesses to external memory */ -#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) -/* Cache Fill Buffer Data lost */ -#define ANOMALY_05000174 (__SILICON_REVISION__ < 5) -/* Overlapping Sequencer and Memory Stalls */ -#define ANOMALY_05000175 (__SILICON_REVISION__ < 5) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ -#define ANOMALY_05000176 (__SILICON_REVISION__ < 5) -/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ -#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) -/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ -#define ANOMALY_05000180 (1) -/* Disabling the PPI resets the PPI configuration registers */ -#define ANOMALY_05000181 (__SILICON_REVISION__ < 5) -/* IMDMA does not operate to full speed for 600MHz and higher devices */ -#define ANOMALY_05000182 (1) -/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ -#define ANOMALY_05000184 (__SILICON_REVISION__ < 5) -/* PPI TX Mode with 2 External Frame Syncs */ -#define ANOMALY_05000185 (__SILICON_REVISION__ < 5) -/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ -#define ANOMALY_05000186 (__SILICON_REVISION__ < 5) -/* IMDMA Corrupted Data after a Halt */ -#define ANOMALY_05000187 (1) -/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ -#define ANOMALY_05000188 (__SILICON_REVISION__ < 5) -/* False Protection Exceptions */ -#define ANOMALY_05000189 (__SILICON_REVISION__ < 5) -/* PPI not functional at core voltage < 1Volt */ -#define ANOMALY_05000190 (1) -/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ -#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) -/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ -#define ANOMALY_05000193 (__SILICON_REVISION__ < 5) -/* Restarting SPORT in Specific Modes May Cause Data Corruption */ -#define ANOMALY_05000194 (__SILICON_REVISION__ < 5) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ -#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) -/* Current DMA Address Shows Wrong Value During Carry Fix */ -#define ANOMALY_05000199 (__SILICON_REVISION__ < 5) -/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ -#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) -/* Possible Infinite Stall with Specific Dual-DAG Situation */ -#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ -#define ANOMALY_05000204 (__SILICON_REVISION__ < 5) -/* Specific sequence that can cause DMA error or DMA stopping */ -#define ANOMALY_05000205 (__SILICON_REVISION__ < 5) -/* Recovery from "Brown-Out" Condition */ -#define ANOMALY_05000207 (__SILICON_REVISION__ < 5) -/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ -#define ANOMALY_05000208 (1) -/* Speed Path in Computational Unit Affects Certain Instructions */ -#define ANOMALY_05000209 (__SILICON_REVISION__ < 5) -/* UART TX Interrupt Masked Erroneously */ -#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) -/* NMI Event at Boot Time Results in Unpredictable State */ -#define ANOMALY_05000219 (__SILICON_REVISION__ < 5) -/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ -#define ANOMALY_05000220 (__SILICON_REVISION__ < 5) -/* Incorrect Pulse-Width of UART Start Bit */ -#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) -/* Scratchpad Memory Bank Reads May Return Incorrect Data */ -#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) -/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ -#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) -/* UART STB Bit Incorrectly Affects Receiver Setting */ -#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* SPORT data transmit lines are incorrectly driven in multichannel mode */ -#define ANOMALY_05000232 (__SILICON_REVISION__ < 5) -/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ -#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (__SILICON_REVISION__ < 5) -/* TESTSET operation forces stall on the other core */ -#define ANOMALY_05000248 (__SILICON_REVISION__ < 5) -/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ -#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) -/* Exception Not Generated for MMR Accesses in Reserved Region */ -#define ANOMALY_05000251 (__SILICON_REVISION__ < 5) -/* Maximum External Clock Speed for Timers */ -#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ -#define ANOMALY_05000254 (__SILICON_REVISION__ > 3) -/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ -#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) -/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ -#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) -/* ICPLB_STATUS MMR Register May Be Corrupted */ -#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) -/* Stores To Data Cache May Be Lost */ -#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) -/* Hardware Loop Corrupted When Taking an ICPLB Exception */ -#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) -/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ -#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) -/* IMDMA destination IRQ status must be read prior to using IMDMA */ -#define ANOMALY_05000266 (__SILICON_REVISION__ > 3) -/* IMDMA may corrupt data under certain conditions */ -#define ANOMALY_05000267 (1) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ -#define ANOMALY_05000269 (1) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ -#define ANOMALY_05000270 (1) -/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) -/* Data cache write back to external synchronous memory may be lost */ -#define ANOMALY_05000274 (1) -/* PPI Timing and Sampling Information Updates */ -#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) -/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ -#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) -/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) -/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error Exception When ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 5) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ -#define ANOMALY_05000283 (1) -/* A read will receive incorrect data under certain conditions */ -#define ANOMALY_05000287 (__SILICON_REVISION__ < 5) -/* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (__SILICON_REVISION__ < 5) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ -#define ANOMALY_05000302 (1) -/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ -#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) -/* SCKELOW Bit Does Not Maintain State Through Hibernate */ -#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) -/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ -#define ANOMALY_05000315 (1) -/* PF2 Output Remains Asserted After SPI Master Boot */ -#define ANOMALY_05000320 (__SILICON_REVISION__ > 3) -/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ -#define ANOMALY_05000323 (1) -/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ -#define ANOMALY_05000326 (__SILICON_REVISION__ > 3) -/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ -#define ANOMALY_05000331 (__SILICON_REVISION__ < 5) -/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ -#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) -/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ -#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ -#define ANOMALY_05000339 (__SILICON_REVISION__ < 5) -/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ -#define ANOMALY_05000343 (__SILICON_REVISION__ < 5) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) -/* Conflicting Column Address Widths Causes SDRAM Errors */ -#define ANOMALY_05000362 (1) -/* UART Break Signal Issues */ -#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (1) -/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ -#define ANOMALY_05000412 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */ -#define ANOMALY_05000428 (__SILICON_REVISION__ > 3) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000158 (0) -#define ANOMALY_05000183 (0) -#define ANOMALY_05000273 (0) -#define ANOMALY_05000311 (0) -#define ANOMALY_05000353 (1) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000386 (1) -#define ANOMALY_05000430 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000435 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) - -#endif diff --git a/include/asm-blackfin/mach-bf561/def_local.h b/include/asm-blackfin/mach-bf561/def_local.h deleted file mode 100644 index 597dcec..0000000 --- a/include/asm-blackfin/mach-bf561/def_local.h +++ /dev/null @@ -1,12 +0,0 @@ -#define SWRST SICA_SWRST -#define SYSCR SICA_SYSCR -#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) -#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) - -#define WDOG_CNT WDOGA_CNT -#define WDOG_CTL WDOGA_CTL -#define bfin_write_WDOG_CNT(val) bfin_write_WDOGA_CNT(val) -#define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val) -#define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val) - -#include "ports.h" diff --git a/include/asm-blackfin/mach-bf561/ports.h b/include/asm-blackfin/mach-bf561/ports.h deleted file mode 100644 index 194d4a3..0000000 --- a/include/asm-blackfin/mach-bf561/ports.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Port Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT__ -#define __BFIN_PERIPHERAL_PORT__ - -#include "../mach-common/bits/ports-f.h" - -/* The non-standard PF16+ */ -#define PF16 (1 << 0) -#define PF17 (1 << 1) -#define PF18 (1 << 2) -#define PF19 (1 << 3) -#define PF20 (1 << 4) -#define PF21 (1 << 5) -#define PF22 (1 << 6) -#define PF23 (1 << 7) -#define PF24 (1 << 8) -#define PF25 (1 << 9) -#define PF26 (1 << 10) -#define PF27 (1 << 11) -#define PF28 (1 << 12) -#define PF29 (1 << 13) -#define PF30 (1 << 14) -#define PF31 (1 << 15) -#define PF32 (1 << 0) -#define PF33 (1 << 1) -#define PF34 (1 << 2) -#define PF35 (1 << 3) -#define PF36 (1 << 4) -#define PF37 (1 << 5) -#define PF38 (1 << 6) -#define PF39 (1 << 7) -#define PF40 (1 << 8) -#define PF41 (1 << 9) -#define PF42 (1 << 10) -#define PF43 (1 << 11) -#define PF44 (1 << 12) -#define PF45 (1 << 13) -#define PF46 (1 << 14) -#define PF47 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h deleted file mode 100644 index 43f3850..0000000 --- a/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h +++ /dev/null @@ -1,1988 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ -#define __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSPI_CTL ((uint16_t volatile *)SPI_CTL) -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define pSPI_FLG ((uint16_t volatile *)SPI_FLG) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define pSPI_STAT ((uint16_t volatile *)SPI_STAT) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) -#define pWDOGA_CTL ((uint16_t volatile *)WDOGA_CTL) -#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL) -#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL, val) -#define pWDOGA_CNT ((uint32_t volatile *)WDOGA_CNT) -#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT) -#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT, val) -#define pWDOGA_STAT ((uint32_t volatile *)WDOGA_STAT) -#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT) -#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT, val) -#define pWDOGB_CTL ((uint16_t volatile *)WDOGB_CTL) -#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL) -#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL, val) -#define pWDOGB_CNT ((uint32_t volatile *)WDOGB_CNT) -#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT) -#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT, val) -#define pWDOGB_STAT ((uint32_t volatile *)WDOGB_STAT) -#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT) -#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT, val) -#define pDMA1_TC_PER ((uint16_t volatile *)DMA1_TC_PER) /* Traffic Control Periods */ -#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) -#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val) -#define pDMA1_TC_CNT ((uint16_t volatile *)DMA1_TC_CNT) /* Traffic Control Current Counts */ -#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) -#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val) -#define pDMA1_0_CONFIG ((uint16_t volatile *)DMA1_0_CONFIG) -#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) -#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG, val) -#define pDMA1_0_NEXT_DESC_PTR ((void * volatile *)DMA1_0_NEXT_DESC_PTR) -#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR) -#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val) -#define pDMA1_0_START_ADDR ((void * volatile *)DMA1_0_START_ADDR) -#define bfin_read_DMA1_0_START_ADDR() bfin_readPTR(DMA1_0_START_ADDR) -#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val) -#define pDMA1_0_X_COUNT ((uint16_t volatile *)DMA1_0_X_COUNT) -#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT) -#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val) -#define pDMA1_0_Y_COUNT ((uint16_t volatile *)DMA1_0_Y_COUNT) -#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT) -#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val) -#define pDMA1_0_X_MODIFY ((uint16_t volatile *)DMA1_0_X_MODIFY) -#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY) -#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val) -#define pDMA1_0_Y_MODIFY ((uint16_t volatile *)DMA1_0_Y_MODIFY) -#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY) -#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val) -#define pDMA1_0_CURR_DESC_PTR ((void * volatile *)DMA1_0_CURR_DESC_PTR) -#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR) -#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val) -#define pDMA1_0_CURR_ADDR ((void * volatile *)DMA1_0_CURR_ADDR) -#define bfin_read_DMA1_0_CURR_ADDR() bfin_readPTR(DMA1_0_CURR_ADDR) -#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val) -#define pDMA1_0_CURR_X_COUNT ((uint16_t volatile *)DMA1_0_CURR_X_COUNT) -#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT) -#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val) -#define pDMA1_0_CURR_Y_COUNT ((uint16_t volatile *)DMA1_0_CURR_Y_COUNT) -#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT) -#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val) -#define pDMA1_0_IRQ_STATUS ((uint16_t volatile *)DMA1_0_IRQ_STATUS) -#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS) -#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val) -#define pDMA1_0_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_0_PERIPHERAL_MAP) -#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP) -#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val) -#define pDMA1_1_CONFIG ((uint16_t volatile *)DMA1_1_CONFIG) -#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG) -#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG, val) -#define pDMA1_1_NEXT_DESC_PTR ((void * volatile *)DMA1_1_NEXT_DESC_PTR) -#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR) -#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val) -#define pDMA1_1_START_ADDR ((void * volatile *)DMA1_1_START_ADDR) -#define bfin_read_DMA1_1_START_ADDR() bfin_readPTR(DMA1_1_START_ADDR) -#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val) -#define pDMA1_1_X_COUNT ((uint16_t volatile *)DMA1_1_X_COUNT) -#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT) -#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val) -#define pDMA1_1_Y_COUNT ((uint16_t volatile *)DMA1_1_Y_COUNT) -#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT) -#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val) -#define pDMA1_1_X_MODIFY ((uint16_t volatile *)DMA1_1_X_MODIFY) -#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY) -#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val) -#define pDMA1_1_Y_MODIFY ((uint16_t volatile *)DMA1_1_Y_MODIFY) -#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY) -#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val) -#define pDMA1_1_CURR_DESC_PTR ((void * volatile *)DMA1_1_CURR_DESC_PTR) -#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR) -#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val) -#define pDMA1_1_CURR_ADDR ((void * volatile *)DMA1_1_CURR_ADDR) -#define bfin_read_DMA1_1_CURR_ADDR() bfin_readPTR(DMA1_1_CURR_ADDR) -#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val) -#define pDMA1_1_CURR_X_COUNT ((uint16_t volatile *)DMA1_1_CURR_X_COUNT) -#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT) -#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val) -#define pDMA1_1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_1_CURR_Y_COUNT) -#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT) -#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val) -#define pDMA1_1_IRQ_STATUS ((uint16_t volatile *)DMA1_1_IRQ_STATUS) -#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS) -#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val) -#define pDMA1_1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_1_PERIPHERAL_MAP) -#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP) -#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val) -#define pDMA1_2_CONFIG ((uint16_t volatile *)DMA1_2_CONFIG) -#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG) -#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG, val) -#define pDMA1_2_NEXT_DESC_PTR ((void * volatile *)DMA1_2_NEXT_DESC_PTR) -#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR) -#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val) -#define pDMA1_2_START_ADDR ((void * volatile *)DMA1_2_START_ADDR) -#define bfin_read_DMA1_2_START_ADDR() bfin_readPTR(DMA1_2_START_ADDR) -#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val) -#define pDMA1_2_X_COUNT ((uint16_t volatile *)DMA1_2_X_COUNT) -#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT) -#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val) -#define pDMA1_2_Y_COUNT ((uint16_t volatile *)DMA1_2_Y_COUNT) -#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT) -#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val) -#define pDMA1_2_X_MODIFY ((uint16_t volatile *)DMA1_2_X_MODIFY) -#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY) -#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val) -#define pDMA1_2_Y_MODIFY ((uint16_t volatile *)DMA1_2_Y_MODIFY) -#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY) -#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val) -#define pDMA1_2_CURR_DESC_PTR ((void * volatile *)DMA1_2_CURR_DESC_PTR) -#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR) -#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val) -#define pDMA1_2_CURR_ADDR ((void * volatile *)DMA1_2_CURR_ADDR) -#define bfin_read_DMA1_2_CURR_ADDR() bfin_readPTR(DMA1_2_CURR_ADDR) -#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val) -#define pDMA1_2_CURR_X_COUNT ((uint16_t volatile *)DMA1_2_CURR_X_COUNT) -#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT) -#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val) -#define pDMA1_2_CURR_Y_COUNT ((uint16_t volatile *)DMA1_2_CURR_Y_COUNT) -#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT) -#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val) -#define pDMA1_2_IRQ_STATUS ((uint16_t volatile *)DMA1_2_IRQ_STATUS) -#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS) -#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val) -#define pDMA1_2_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_2_PERIPHERAL_MAP) -#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP) -#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val) -#define pDMA1_3_CONFIG ((uint16_t volatile *)DMA1_3_CONFIG) -#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG) -#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG, val) -#define pDMA1_3_NEXT_DESC_PTR ((void * volatile *)DMA1_3_NEXT_DESC_PTR) -#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR) -#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val) -#define pDMA1_3_START_ADDR ((void * volatile *)DMA1_3_START_ADDR) -#define bfin_read_DMA1_3_START_ADDR() bfin_readPTR(DMA1_3_START_ADDR) -#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val) -#define pDMA1_3_X_COUNT ((uint16_t volatile *)DMA1_3_X_COUNT) -#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT) -#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val) -#define pDMA1_3_Y_COUNT ((uint16_t volatile *)DMA1_3_Y_COUNT) -#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT) -#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val) -#define pDMA1_3_X_MODIFY ((uint16_t volatile *)DMA1_3_X_MODIFY) -#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY) -#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val) -#define pDMA1_3_Y_MODIFY ((uint16_t volatile *)DMA1_3_Y_MODIFY) -#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY) -#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val) -#define pDMA1_3_CURR_DESC_PTR ((void * volatile *)DMA1_3_CURR_DESC_PTR) -#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR) -#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val) -#define pDMA1_3_CURR_ADDR ((void * volatile *)DMA1_3_CURR_ADDR) -#define bfin_read_DMA1_3_CURR_ADDR() bfin_readPTR(DMA1_3_CURR_ADDR) -#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val) -#define pDMA1_3_CURR_X_COUNT ((uint16_t volatile *)DMA1_3_CURR_X_COUNT) -#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT) -#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val) -#define pDMA1_3_CURR_Y_COUNT ((uint16_t volatile *)DMA1_3_CURR_Y_COUNT) -#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT) -#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val) -#define pDMA1_3_IRQ_STATUS ((uint16_t volatile *)DMA1_3_IRQ_STATUS) -#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS) -#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val) -#define pDMA1_3_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_3_PERIPHERAL_MAP) -#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP) -#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val) -#define pDMA1_4_CONFIG ((uint16_t volatile *)DMA1_4_CONFIG) -#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG) -#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG, val) -#define pDMA1_4_NEXT_DESC_PTR ((void * volatile *)DMA1_4_NEXT_DESC_PTR) -#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR) -#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val) -#define pDMA1_4_START_ADDR ((void * volatile *)DMA1_4_START_ADDR) -#define bfin_read_DMA1_4_START_ADDR() bfin_readPTR(DMA1_4_START_ADDR) -#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val) -#define pDMA1_4_X_COUNT ((uint16_t volatile *)DMA1_4_X_COUNT) -#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT) -#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val) -#define pDMA1_4_Y_COUNT ((uint16_t volatile *)DMA1_4_Y_COUNT) -#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT) -#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val) -#define pDMA1_4_X_MODIFY ((uint16_t volatile *)DMA1_4_X_MODIFY) -#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY) -#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val) -#define pDMA1_4_Y_MODIFY ((uint16_t volatile *)DMA1_4_Y_MODIFY) -#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY) -#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val) -#define pDMA1_4_CURR_DESC_PTR ((void * volatile *)DMA1_4_CURR_DESC_PTR) -#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR) -#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val) -#define pDMA1_4_CURR_ADDR ((void * volatile *)DMA1_4_CURR_ADDR) -#define bfin_read_DMA1_4_CURR_ADDR() bfin_readPTR(DMA1_4_CURR_ADDR) -#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val) -#define pDMA1_4_CURR_X_COUNT ((uint16_t volatile *)DMA1_4_CURR_X_COUNT) -#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT) -#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val) -#define pDMA1_4_CURR_Y_COUNT ((uint16_t volatile *)DMA1_4_CURR_Y_COUNT) -#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT) -#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val) -#define pDMA1_4_IRQ_STATUS ((uint16_t volatile *)DMA1_4_IRQ_STATUS) -#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS) -#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val) -#define pDMA1_4_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_4_PERIPHERAL_MAP) -#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP) -#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val) -#define pDMA1_5_CONFIG ((uint16_t volatile *)DMA1_5_CONFIG) -#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG) -#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG, val) -#define pDMA1_5_NEXT_DESC_PTR ((void * volatile *)DMA1_5_NEXT_DESC_PTR) -#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR) -#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val) -#define pDMA1_5_START_ADDR ((void * volatile *)DMA1_5_START_ADDR) -#define bfin_read_DMA1_5_START_ADDR() bfin_readPTR(DMA1_5_START_ADDR) -#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val) -#define pDMA1_5_X_COUNT ((uint16_t volatile *)DMA1_5_X_COUNT) -#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT) -#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val) -#define pDMA1_5_Y_COUNT ((uint16_t volatile *)DMA1_5_Y_COUNT) -#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT) -#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val) -#define pDMA1_5_X_MODIFY ((uint16_t volatile *)DMA1_5_X_MODIFY) -#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY) -#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val) -#define pDMA1_5_Y_MODIFY ((uint16_t volatile *)DMA1_5_Y_MODIFY) -#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY) -#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val) -#define pDMA1_5_CURR_DESC_PTR ((void * volatile *)DMA1_5_CURR_DESC_PTR) -#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR) -#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val) -#define pDMA1_5_CURR_ADDR ((void * volatile *)DMA1_5_CURR_ADDR) -#define bfin_read_DMA1_5_CURR_ADDR() bfin_readPTR(DMA1_5_CURR_ADDR) -#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val) -#define pDMA1_5_CURR_X_COUNT ((uint16_t volatile *)DMA1_5_CURR_X_COUNT) -#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT) -#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val) -#define pDMA1_5_CURR_Y_COUNT ((uint16_t volatile *)DMA1_5_CURR_Y_COUNT) -#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT) -#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val) -#define pDMA1_5_IRQ_STATUS ((uint16_t volatile *)DMA1_5_IRQ_STATUS) -#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS) -#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val) -#define pDMA1_5_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_5_PERIPHERAL_MAP) -#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP) -#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val) -#define pDMA1_6_CONFIG ((uint16_t volatile *)DMA1_6_CONFIG) -#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG) -#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG, val) -#define pDMA1_6_NEXT_DESC_PTR ((void * volatile *)DMA1_6_NEXT_DESC_PTR) -#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR) -#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val) -#define pDMA1_6_START_ADDR ((void * volatile *)DMA1_6_START_ADDR) -#define bfin_read_DMA1_6_START_ADDR() bfin_readPTR(DMA1_6_START_ADDR) -#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val) -#define pDMA1_6_X_COUNT ((uint16_t volatile *)DMA1_6_X_COUNT) -#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT) -#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val) -#define pDMA1_6_Y_COUNT ((uint16_t volatile *)DMA1_6_Y_COUNT) -#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT) -#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val) -#define pDMA1_6_X_MODIFY ((uint16_t volatile *)DMA1_6_X_MODIFY) -#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY) -#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val) -#define pDMA1_6_Y_MODIFY ((uint16_t volatile *)DMA1_6_Y_MODIFY) -#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY) -#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val) -#define pDMA1_6_CURR_DESC_PTR ((void * volatile *)DMA1_6_CURR_DESC_PTR) -#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR) -#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val) -#define pDMA1_6_CURR_ADDR ((void * volatile *)DMA1_6_CURR_ADDR) -#define bfin_read_DMA1_6_CURR_ADDR() bfin_readPTR(DMA1_6_CURR_ADDR) -#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val) -#define pDMA1_6_CURR_X_COUNT ((uint16_t volatile *)DMA1_6_CURR_X_COUNT) -#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT) -#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val) -#define pDMA1_6_CURR_Y_COUNT ((uint16_t volatile *)DMA1_6_CURR_Y_COUNT) -#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT) -#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val) -#define pDMA1_6_IRQ_STATUS ((uint16_t volatile *)DMA1_6_IRQ_STATUS) -#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS) -#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val) -#define pDMA1_6_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_6_PERIPHERAL_MAP) -#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP) -#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val) -#define pDMA1_7_CONFIG ((uint16_t volatile *)DMA1_7_CONFIG) -#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG) -#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG, val) -#define pDMA1_7_NEXT_DESC_PTR ((void * volatile *)DMA1_7_NEXT_DESC_PTR) -#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR) -#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val) -#define pDMA1_7_START_ADDR ((void * volatile *)DMA1_7_START_ADDR) -#define bfin_read_DMA1_7_START_ADDR() bfin_readPTR(DMA1_7_START_ADDR) -#define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val) -#define pDMA1_7_X_COUNT ((uint16_t volatile *)DMA1_7_X_COUNT) -#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT) -#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val) -#define pDMA1_7_Y_COUNT ((uint16_t volatile *)DMA1_7_Y_COUNT) -#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT) -#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val) -#define pDMA1_7_X_MODIFY ((uint16_t volatile *)DMA1_7_X_MODIFY) -#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY) -#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val) -#define pDMA1_7_Y_MODIFY ((uint16_t volatile *)DMA1_7_Y_MODIFY) -#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY) -#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val) -#define pDMA1_7_CURR_DESC_PTR ((void * volatile *)DMA1_7_CURR_DESC_PTR) -#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR) -#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val) -#define pDMA1_7_CURR_ADDR ((void * volatile *)DMA1_7_CURR_ADDR) -#define bfin_read_DMA1_7_CURR_ADDR() bfin_readPTR(DMA1_7_CURR_ADDR) -#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val) -#define pDMA1_7_CURR_X_COUNT ((uint16_t volatile *)DMA1_7_CURR_X_COUNT) -#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT) -#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val) -#define pDMA1_7_CURR_Y_COUNT ((uint16_t volatile *)DMA1_7_CURR_Y_COUNT) -#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT) -#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val) -#define pDMA1_7_IRQ_STATUS ((uint16_t volatile *)DMA1_7_IRQ_STATUS) -#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS) -#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val) -#define pDMA1_7_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_7_PERIPHERAL_MAP) -#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP) -#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val) -#define pDMA1_8_CONFIG ((uint16_t volatile *)DMA1_8_CONFIG) -#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG) -#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG, val) -#define pDMA1_8_NEXT_DESC_PTR ((void * volatile *)DMA1_8_NEXT_DESC_PTR) -#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR) -#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val) -#define pDMA1_8_START_ADDR ((void * volatile *)DMA1_8_START_ADDR) -#define bfin_read_DMA1_8_START_ADDR() bfin_readPTR(DMA1_8_START_ADDR) -#define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val) -#define pDMA1_8_X_COUNT ((uint16_t volatile *)DMA1_8_X_COUNT) -#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT) -#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val) -#define pDMA1_8_Y_COUNT ((uint16_t volatile *)DMA1_8_Y_COUNT) -#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT) -#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val) -#define pDMA1_8_X_MODIFY ((uint16_t volatile *)DMA1_8_X_MODIFY) -#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY) -#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val) -#define pDMA1_8_Y_MODIFY ((uint16_t volatile *)DMA1_8_Y_MODIFY) -#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY) -#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val) -#define pDMA1_8_CURR_DESC_PTR ((void * volatile *)DMA1_8_CURR_DESC_PTR) -#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR) -#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val) -#define pDMA1_8_CURR_ADDR ((void * volatile *)DMA1_8_CURR_ADDR) -#define bfin_read_DMA1_8_CURR_ADDR() bfin_readPTR(DMA1_8_CURR_ADDR) -#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val) -#define pDMA1_8_CURR_X_COUNT ((uint16_t volatile *)DMA1_8_CURR_X_COUNT) -#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT) -#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val) -#define pDMA1_8_CURR_Y_COUNT ((uint16_t volatile *)DMA1_8_CURR_Y_COUNT) -#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT) -#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val) -#define pDMA1_8_IRQ_STATUS ((uint16_t volatile *)DMA1_8_IRQ_STATUS) -#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS) -#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val) -#define pDMA1_8_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_8_PERIPHERAL_MAP) -#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP) -#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val) -#define pDMA1_9_CONFIG ((uint16_t volatile *)DMA1_9_CONFIG) -#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG) -#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG, val) -#define pDMA1_9_NEXT_DESC_PTR ((void * volatile *)DMA1_9_NEXT_DESC_PTR) -#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR) -#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val) -#define pDMA1_9_START_ADDR ((void * volatile *)DMA1_9_START_ADDR) -#define bfin_read_DMA1_9_START_ADDR() bfin_readPTR(DMA1_9_START_ADDR) -#define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val) -#define pDMA1_9_X_COUNT ((uint16_t volatile *)DMA1_9_X_COUNT) -#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT) -#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val) -#define pDMA1_9_Y_COUNT ((uint16_t volatile *)DMA1_9_Y_COUNT) -#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT) -#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val) -#define pDMA1_9_X_MODIFY ((uint16_t volatile *)DMA1_9_X_MODIFY) -#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY) -#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val) -#define pDMA1_9_Y_MODIFY ((uint16_t volatile *)DMA1_9_Y_MODIFY) -#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY) -#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val) -#define pDMA1_9_CURR_DESC_PTR ((void * volatile *)DMA1_9_CURR_DESC_PTR) -#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR) -#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val) -#define pDMA1_9_CURR_ADDR ((void * volatile *)DMA1_9_CURR_ADDR) -#define bfin_read_DMA1_9_CURR_ADDR() bfin_readPTR(DMA1_9_CURR_ADDR) -#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val) -#define pDMA1_9_CURR_X_COUNT ((uint16_t volatile *)DMA1_9_CURR_X_COUNT) -#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT) -#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val) -#define pDMA1_9_CURR_Y_COUNT ((uint16_t volatile *)DMA1_9_CURR_Y_COUNT) -#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT) -#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val) -#define pDMA1_9_IRQ_STATUS ((uint16_t volatile *)DMA1_9_IRQ_STATUS) -#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS) -#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val) -#define pDMA1_9_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_9_PERIPHERAL_MAP) -#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP) -#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val) -#define pDMA1_10_CONFIG ((uint16_t volatile *)DMA1_10_CONFIG) -#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG) -#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val) -#define pDMA1_10_NEXT_DESC_PTR ((void * volatile *)DMA1_10_NEXT_DESC_PTR) -#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR) -#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val) -#define pDMA1_10_START_ADDR ((void * volatile *)DMA1_10_START_ADDR) -#define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR) -#define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val) -#define pDMA1_10_X_COUNT ((uint16_t volatile *)DMA1_10_X_COUNT) -#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT) -#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val) -#define pDMA1_10_Y_COUNT ((uint16_t volatile *)DMA1_10_Y_COUNT) -#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT) -#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val) -#define pDMA1_10_X_MODIFY ((uint16_t volatile *)DMA1_10_X_MODIFY) -#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY) -#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val) -#define pDMA1_10_Y_MODIFY ((uint16_t volatile *)DMA1_10_Y_MODIFY) -#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY) -#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val) -#define pDMA1_10_CURR_DESC_PTR ((void * volatile *)DMA1_10_CURR_DESC_PTR) -#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR) -#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val) -#define pDMA1_10_CURR_ADDR ((void * volatile *)DMA1_10_CURR_ADDR) -#define bfin_read_DMA1_10_CURR_ADDR() bfin_readPTR(DMA1_10_CURR_ADDR) -#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val) -#define pDMA1_10_CURR_X_COUNT ((uint16_t volatile *)DMA1_10_CURR_X_COUNT) -#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT) -#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val) -#define pDMA1_10_CURR_Y_COUNT ((uint16_t volatile *)DMA1_10_CURR_Y_COUNT) -#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT) -#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val) -#define pDMA1_10_IRQ_STATUS ((uint16_t volatile *)DMA1_10_IRQ_STATUS) -#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS) -#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val) -#define pDMA1_10_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_10_PERIPHERAL_MAP) -#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP) -#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val) -#define pDMA1_11_CONFIG ((uint16_t volatile *)DMA1_11_CONFIG) -#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG) -#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val) -#define pDMA1_11_NEXT_DESC_PTR ((void * volatile *)DMA1_11_NEXT_DESC_PTR) -#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR) -#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val) -#define pDMA1_11_START_ADDR ((void * volatile *)DMA1_11_START_ADDR) -#define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR) -#define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val) -#define pDMA1_11_X_COUNT ((uint16_t volatile *)DMA1_11_X_COUNT) -#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT) -#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val) -#define pDMA1_11_Y_COUNT ((uint16_t volatile *)DMA1_11_Y_COUNT) -#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT) -#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val) -#define pDMA1_11_X_MODIFY ((uint16_t volatile *)DMA1_11_X_MODIFY) -#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY) -#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val) -#define pDMA1_11_Y_MODIFY ((uint16_t volatile *)DMA1_11_Y_MODIFY) -#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY) -#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val) -#define pDMA1_11_CURR_DESC_PTR ((void * volatile *)DMA1_11_CURR_DESC_PTR) -#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR) -#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val) -#define pDMA1_11_CURR_ADDR ((void * volatile *)DMA1_11_CURR_ADDR) -#define bfin_read_DMA1_11_CURR_ADDR() bfin_readPTR(DMA1_11_CURR_ADDR) -#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val) -#define pDMA1_11_CURR_X_COUNT ((uint16_t volatile *)DMA1_11_CURR_X_COUNT) -#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT) -#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val) -#define pDMA1_11_CURR_Y_COUNT ((uint16_t volatile *)DMA1_11_CURR_Y_COUNT) -#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT) -#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val) -#define pDMA1_11_IRQ_STATUS ((uint16_t volatile *)DMA1_11_IRQ_STATUS) -#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS) -#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val) -#define pDMA1_11_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_11_PERIPHERAL_MAP) -#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) -#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val) -#define pDMA2_TC_PER ((uint16_t volatile *)DMA2_TC_PER) -#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER) -#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER, val) -#define pDMA2_TC_CNT ((uint16_t volatile *)DMA2_TC_CNT) /* Traffic Control Current Counts */ -#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT) -#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT, val) -#define pDMA2_0_CONFIG ((uint16_t volatile *)DMA2_0_CONFIG) -#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) -#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG, val) -#define pDMA2_0_NEXT_DESC_PTR ((void * volatile *)DMA2_0_NEXT_DESC_PTR) -#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR) -#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val) -#define pDMA2_0_START_ADDR ((void * volatile *)DMA2_0_START_ADDR) -#define bfin_read_DMA2_0_START_ADDR() bfin_readPTR(DMA2_0_START_ADDR) -#define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val) -#define pDMA2_0_X_COUNT ((uint16_t volatile *)DMA2_0_X_COUNT) -#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT) -#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val) -#define pDMA2_0_Y_COUNT ((uint16_t volatile *)DMA2_0_Y_COUNT) -#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT) -#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val) -#define pDMA2_0_X_MODIFY ((uint16_t volatile *)DMA2_0_X_MODIFY) -#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY) -#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val) -#define pDMA2_0_Y_MODIFY ((uint16_t volatile *)DMA2_0_Y_MODIFY) -#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY) -#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val) -#define pDMA2_0_CURR_DESC_PTR ((void * volatile *)DMA2_0_CURR_DESC_PTR) -#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR) -#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val) -#define pDMA2_0_CURR_ADDR ((void * volatile *)DMA2_0_CURR_ADDR) -#define bfin_read_DMA2_0_CURR_ADDR() bfin_readPTR(DMA2_0_CURR_ADDR) -#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val) -#define pDMA2_0_CURR_X_COUNT ((uint16_t volatile *)DMA2_0_CURR_X_COUNT) -#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT) -#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val) -#define pDMA2_0_CURR_Y_COUNT ((uint16_t volatile *)DMA2_0_CURR_Y_COUNT) -#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT) -#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val) -#define pDMA2_0_IRQ_STATUS ((uint16_t volatile *)DMA2_0_IRQ_STATUS) -#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS) -#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val) -#define pDMA2_0_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_0_PERIPHERAL_MAP) -#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP) -#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val) -#define pDMA2_1_CONFIG ((uint16_t volatile *)DMA2_1_CONFIG) -#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG) -#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG, val) -#define pDMA2_1_NEXT_DESC_PTR ((void * volatile *)DMA2_1_NEXT_DESC_PTR) -#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR) -#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val) -#define pDMA2_1_START_ADDR ((void * volatile *)DMA2_1_START_ADDR) -#define bfin_read_DMA2_1_START_ADDR() bfin_readPTR(DMA2_1_START_ADDR) -#define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val) -#define pDMA2_1_X_COUNT ((uint16_t volatile *)DMA2_1_X_COUNT) -#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT) -#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val) -#define pDMA2_1_Y_COUNT ((uint16_t volatile *)DMA2_1_Y_COUNT) -#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT) -#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val) -#define pDMA2_1_X_MODIFY ((uint16_t volatile *)DMA2_1_X_MODIFY) -#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY) -#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val) -#define pDMA2_1_Y_MODIFY ((uint16_t volatile *)DMA2_1_Y_MODIFY) -#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY) -#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val) -#define pDMA2_1_CURR_DESC_PTR ((void * volatile *)DMA2_1_CURR_DESC_PTR) -#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR) -#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val) -#define pDMA2_1_CURR_ADDR ((void * volatile *)DMA2_1_CURR_ADDR) -#define bfin_read_DMA2_1_CURR_ADDR() bfin_readPTR(DMA2_1_CURR_ADDR) -#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val) -#define pDMA2_1_CURR_X_COUNT ((uint16_t volatile *)DMA2_1_CURR_X_COUNT) -#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT) -#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val) -#define pDMA2_1_CURR_Y_COUNT ((uint16_t volatile *)DMA2_1_CURR_Y_COUNT) -#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT) -#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val) -#define pDMA2_1_IRQ_STATUS ((uint16_t volatile *)DMA2_1_IRQ_STATUS) -#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS) -#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val) -#define pDMA2_1_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_1_PERIPHERAL_MAP) -#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP) -#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val) -#define pDMA2_2_CONFIG ((uint16_t volatile *)DMA2_2_CONFIG) -#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG) -#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG, val) -#define pDMA2_2_NEXT_DESC_PTR ((void * volatile *)DMA2_2_NEXT_DESC_PTR) -#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR) -#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val) -#define pDMA2_2_START_ADDR ((void * volatile *)DMA2_2_START_ADDR) -#define bfin_read_DMA2_2_START_ADDR() bfin_readPTR(DMA2_2_START_ADDR) -#define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val) -#define pDMA2_2_X_COUNT ((uint16_t volatile *)DMA2_2_X_COUNT) -#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT) -#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val) -#define pDMA2_2_Y_COUNT ((uint16_t volatile *)DMA2_2_Y_COUNT) -#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT) -#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val) -#define pDMA2_2_X_MODIFY ((uint16_t volatile *)DMA2_2_X_MODIFY) -#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY) -#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val) -#define pDMA2_2_Y_MODIFY ((uint16_t volatile *)DMA2_2_Y_MODIFY) -#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY) -#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val) -#define pDMA2_2_CURR_DESC_PTR ((void * volatile *)DMA2_2_CURR_DESC_PTR) -#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR) -#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val) -#define pDMA2_2_CURR_ADDR ((void * volatile *)DMA2_2_CURR_ADDR) -#define bfin_read_DMA2_2_CURR_ADDR() bfin_readPTR(DMA2_2_CURR_ADDR) -#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val) -#define pDMA2_2_CURR_X_COUNT ((uint16_t volatile *)DMA2_2_CURR_X_COUNT) -#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT) -#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val) -#define pDMA2_2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_2_CURR_Y_COUNT) -#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT) -#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val) -#define pDMA2_2_IRQ_STATUS ((uint16_t volatile *)DMA2_2_IRQ_STATUS) -#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS) -#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val) -#define pDMA2_2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_2_PERIPHERAL_MAP) -#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP) -#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val) -#define pDMA2_3_CONFIG ((uint16_t volatile *)DMA2_3_CONFIG) -#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG) -#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG, val) -#define pDMA2_3_NEXT_DESC_PTR ((void * volatile *)DMA2_3_NEXT_DESC_PTR) -#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR) -#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val) -#define pDMA2_3_START_ADDR ((void * volatile *)DMA2_3_START_ADDR) -#define bfin_read_DMA2_3_START_ADDR() bfin_readPTR(DMA2_3_START_ADDR) -#define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val) -#define pDMA2_3_X_COUNT ((uint16_t volatile *)DMA2_3_X_COUNT) -#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT) -#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val) -#define pDMA2_3_Y_COUNT ((uint16_t volatile *)DMA2_3_Y_COUNT) -#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT) -#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val) -#define pDMA2_3_X_MODIFY ((uint16_t volatile *)DMA2_3_X_MODIFY) -#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY) -#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val) -#define pDMA2_3_Y_MODIFY ((uint16_t volatile *)DMA2_3_Y_MODIFY) -#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY) -#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val) -#define pDMA2_3_CURR_DESC_PTR ((void * volatile *)DMA2_3_CURR_DESC_PTR) -#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR) -#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val) -#define pDMA2_3_CURR_ADDR ((void * volatile *)DMA2_3_CURR_ADDR) -#define bfin_read_DMA2_3_CURR_ADDR() bfin_readPTR(DMA2_3_CURR_ADDR) -#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val) -#define pDMA2_3_CURR_X_COUNT ((uint16_t volatile *)DMA2_3_CURR_X_COUNT) -#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT) -#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val) -#define pDMA2_3_CURR_Y_COUNT ((uint16_t volatile *)DMA2_3_CURR_Y_COUNT) -#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT) -#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val) -#define pDMA2_3_IRQ_STATUS ((uint16_t volatile *)DMA2_3_IRQ_STATUS) -#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS) -#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val) -#define pDMA2_3_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_3_PERIPHERAL_MAP) -#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP) -#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val) -#define pDMA2_4_CONFIG ((uint16_t volatile *)DMA2_4_CONFIG) -#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG) -#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG, val) -#define pDMA2_4_NEXT_DESC_PTR ((void * volatile *)DMA2_4_NEXT_DESC_PTR) -#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR) -#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val) -#define pDMA2_4_START_ADDR ((void * volatile *)DMA2_4_START_ADDR) -#define bfin_read_DMA2_4_START_ADDR() bfin_readPTR(DMA2_4_START_ADDR) -#define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val) -#define pDMA2_4_X_COUNT ((uint16_t volatile *)DMA2_4_X_COUNT) -#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT) -#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val) -#define pDMA2_4_Y_COUNT ((uint16_t volatile *)DMA2_4_Y_COUNT) -#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT) -#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val) -#define pDMA2_4_X_MODIFY ((uint16_t volatile *)DMA2_4_X_MODIFY) -#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY) -#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val) -#define pDMA2_4_Y_MODIFY ((uint16_t volatile *)DMA2_4_Y_MODIFY) -#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY) -#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val) -#define pDMA2_4_CURR_DESC_PTR ((void * volatile *)DMA2_4_CURR_DESC_PTR) -#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR) -#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val) -#define pDMA2_4_CURR_ADDR ((void * volatile *)DMA2_4_CURR_ADDR) -#define bfin_read_DMA2_4_CURR_ADDR() bfin_readPTR(DMA2_4_CURR_ADDR) -#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val) -#define pDMA2_4_CURR_X_COUNT ((uint16_t volatile *)DMA2_4_CURR_X_COUNT) -#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT) -#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val) -#define pDMA2_4_CURR_Y_COUNT ((uint16_t volatile *)DMA2_4_CURR_Y_COUNT) -#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT) -#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val) -#define pDMA2_4_IRQ_STATUS ((uint16_t volatile *)DMA2_4_IRQ_STATUS) -#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS) -#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val) -#define pDMA2_4_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_4_PERIPHERAL_MAP) -#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP) -#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val) -#define pDMA2_5_CONFIG ((uint16_t volatile *)DMA2_5_CONFIG) -#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG) -#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG, val) -#define pDMA2_5_NEXT_DESC_PTR ((void * volatile *)DMA2_5_NEXT_DESC_PTR) -#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR) -#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val) -#define pDMA2_5_START_ADDR ((void * volatile *)DMA2_5_START_ADDR) -#define bfin_read_DMA2_5_START_ADDR() bfin_readPTR(DMA2_5_START_ADDR) -#define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val) -#define pDMA2_5_X_COUNT ((uint16_t volatile *)DMA2_5_X_COUNT) -#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT) -#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val) -#define pDMA2_5_Y_COUNT ((uint16_t volatile *)DMA2_5_Y_COUNT) -#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT) -#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val) -#define pDMA2_5_X_MODIFY ((uint16_t volatile *)DMA2_5_X_MODIFY) -#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY) -#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val) -#define pDMA2_5_Y_MODIFY ((uint16_t volatile *)DMA2_5_Y_MODIFY) -#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY) -#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val) -#define pDMA2_5_CURR_DESC_PTR ((void * volatile *)DMA2_5_CURR_DESC_PTR) -#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR) -#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val) -#define pDMA2_5_CURR_ADDR ((void * volatile *)DMA2_5_CURR_ADDR) -#define bfin_read_DMA2_5_CURR_ADDR() bfin_readPTR(DMA2_5_CURR_ADDR) -#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val) -#define pDMA2_5_CURR_X_COUNT ((uint16_t volatile *)DMA2_5_CURR_X_COUNT) -#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT) -#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val) -#define pDMA2_5_CURR_Y_COUNT ((uint16_t volatile *)DMA2_5_CURR_Y_COUNT) -#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT) -#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val) -#define pDMA2_5_IRQ_STATUS ((uint16_t volatile *)DMA2_5_IRQ_STATUS) -#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS) -#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val) -#define pDMA2_5_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_5_PERIPHERAL_MAP) -#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP) -#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val) -#define pDMA2_6_CONFIG ((uint16_t volatile *)DMA2_6_CONFIG) -#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG) -#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG, val) -#define pDMA2_6_NEXT_DESC_PTR ((void * volatile *)DMA2_6_NEXT_DESC_PTR) -#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR) -#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val) -#define pDMA2_6_START_ADDR ((void * volatile *)DMA2_6_START_ADDR) -#define bfin_read_DMA2_6_START_ADDR() bfin_readPTR(DMA2_6_START_ADDR) -#define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val) -#define pDMA2_6_X_COUNT ((uint16_t volatile *)DMA2_6_X_COUNT) -#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT) -#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val) -#define pDMA2_6_Y_COUNT ((uint16_t volatile *)DMA2_6_Y_COUNT) -#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT) -#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val) -#define pDMA2_6_X_MODIFY ((uint16_t volatile *)DMA2_6_X_MODIFY) -#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY) -#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val) -#define pDMA2_6_Y_MODIFY ((uint16_t volatile *)DMA2_6_Y_MODIFY) -#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY) -#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val) -#define pDMA2_6_CURR_DESC_PTR ((void * volatile *)DMA2_6_CURR_DESC_PTR) -#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR) -#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val) -#define pDMA2_6_CURR_ADDR ((void * volatile *)DMA2_6_CURR_ADDR) -#define bfin_read_DMA2_6_CURR_ADDR() bfin_readPTR(DMA2_6_CURR_ADDR) -#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val) -#define pDMA2_6_CURR_X_COUNT ((uint16_t volatile *)DMA2_6_CURR_X_COUNT) -#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT) -#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val) -#define pDMA2_6_CURR_Y_COUNT ((uint16_t volatile *)DMA2_6_CURR_Y_COUNT) -#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT) -#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val) -#define pDMA2_6_IRQ_STATUS ((uint16_t volatile *)DMA2_6_IRQ_STATUS) -#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS) -#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val) -#define pDMA2_6_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_6_PERIPHERAL_MAP) -#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP) -#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val) -#define pDMA2_7_CONFIG ((uint16_t volatile *)DMA2_7_CONFIG) -#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG) -#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG, val) -#define pDMA2_7_NEXT_DESC_PTR ((void * volatile *)DMA2_7_NEXT_DESC_PTR) -#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR) -#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val) -#define pDMA2_7_START_ADDR ((void * volatile *)DMA2_7_START_ADDR) -#define bfin_read_DMA2_7_START_ADDR() bfin_readPTR(DMA2_7_START_ADDR) -#define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val) -#define pDMA2_7_X_COUNT ((uint16_t volatile *)DMA2_7_X_COUNT) -#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT) -#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val) -#define pDMA2_7_Y_COUNT ((uint16_t volatile *)DMA2_7_Y_COUNT) -#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT) -#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val) -#define pDMA2_7_X_MODIFY ((uint16_t volatile *)DMA2_7_X_MODIFY) -#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY) -#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val) -#define pDMA2_7_Y_MODIFY ((uint16_t volatile *)DMA2_7_Y_MODIFY) -#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY) -#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val) -#define pDMA2_7_CURR_DESC_PTR ((void * volatile *)DMA2_7_CURR_DESC_PTR) -#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR) -#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val) -#define pDMA2_7_CURR_ADDR ((void * volatile *)DMA2_7_CURR_ADDR) -#define bfin_read_DMA2_7_CURR_ADDR() bfin_readPTR(DMA2_7_CURR_ADDR) -#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val) -#define pDMA2_7_CURR_X_COUNT ((uint16_t volatile *)DMA2_7_CURR_X_COUNT) -#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT) -#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val) -#define pDMA2_7_CURR_Y_COUNT ((uint16_t volatile *)DMA2_7_CURR_Y_COUNT) -#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT) -#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val) -#define pDMA2_7_IRQ_STATUS ((uint16_t volatile *)DMA2_7_IRQ_STATUS) -#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS) -#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val) -#define pDMA2_7_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_7_PERIPHERAL_MAP) -#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP) -#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val) -#define pDMA2_8_CONFIG ((uint16_t volatile *)DMA2_8_CONFIG) -#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG) -#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG, val) -#define pDMA2_8_NEXT_DESC_PTR ((void * volatile *)DMA2_8_NEXT_DESC_PTR) -#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR) -#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val) -#define pDMA2_8_START_ADDR ((void * volatile *)DMA2_8_START_ADDR) -#define bfin_read_DMA2_8_START_ADDR() bfin_readPTR(DMA2_8_START_ADDR) -#define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val) -#define pDMA2_8_X_COUNT ((uint16_t volatile *)DMA2_8_X_COUNT) -#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT) -#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val) -#define pDMA2_8_Y_COUNT ((uint16_t volatile *)DMA2_8_Y_COUNT) -#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT) -#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val) -#define pDMA2_8_X_MODIFY ((uint16_t volatile *)DMA2_8_X_MODIFY) -#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY) -#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val) -#define pDMA2_8_Y_MODIFY ((uint16_t volatile *)DMA2_8_Y_MODIFY) -#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY) -#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val) -#define pDMA2_8_CURR_DESC_PTR ((void * volatile *)DMA2_8_CURR_DESC_PTR) -#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR) -#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val) -#define pDMA2_8_CURR_ADDR ((void * volatile *)DMA2_8_CURR_ADDR) -#define bfin_read_DMA2_8_CURR_ADDR() bfin_readPTR(DMA2_8_CURR_ADDR) -#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val) -#define pDMA2_8_CURR_X_COUNT ((uint16_t volatile *)DMA2_8_CURR_X_COUNT) -#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT) -#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val) -#define pDMA2_8_CURR_Y_COUNT ((uint16_t volatile *)DMA2_8_CURR_Y_COUNT) -#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT) -#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val) -#define pDMA2_8_IRQ_STATUS ((uint16_t volatile *)DMA2_8_IRQ_STATUS) -#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS) -#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val) -#define pDMA2_8_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_8_PERIPHERAL_MAP) -#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP) -#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val) -#define pDMA2_9_CONFIG ((uint16_t volatile *)DMA2_9_CONFIG) -#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG) -#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG, val) -#define pDMA2_9_NEXT_DESC_PTR ((void * volatile *)DMA2_9_NEXT_DESC_PTR) -#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR) -#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val) -#define pDMA2_9_START_ADDR ((void * volatile *)DMA2_9_START_ADDR) -#define bfin_read_DMA2_9_START_ADDR() bfin_readPTR(DMA2_9_START_ADDR) -#define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val) -#define pDMA2_9_X_COUNT ((uint16_t volatile *)DMA2_9_X_COUNT) -#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT) -#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val) -#define pDMA2_9_Y_COUNT ((uint16_t volatile *)DMA2_9_Y_COUNT) -#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT) -#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val) -#define pDMA2_9_X_MODIFY ((uint16_t volatile *)DMA2_9_X_MODIFY) -#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY) -#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val) -#define pDMA2_9_Y_MODIFY ((uint16_t volatile *)DMA2_9_Y_MODIFY) -#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY) -#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val) -#define pDMA2_9_CURR_DESC_PTR ((void * volatile *)DMA2_9_CURR_DESC_PTR) -#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR) -#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val) -#define pDMA2_9_CURR_ADDR ((void * volatile *)DMA2_9_CURR_ADDR) -#define bfin_read_DMA2_9_CURR_ADDR() bfin_readPTR(DMA2_9_CURR_ADDR) -#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val) -#define pDMA2_9_CURR_X_COUNT ((uint16_t volatile *)DMA2_9_CURR_X_COUNT) -#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT) -#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val) -#define pDMA2_9_CURR_Y_COUNT ((uint16_t volatile *)DMA2_9_CURR_Y_COUNT) -#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT) -#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val) -#define pDMA2_9_IRQ_STATUS ((uint16_t volatile *)DMA2_9_IRQ_STATUS) -#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS) -#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val) -#define pDMA2_9_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_9_PERIPHERAL_MAP) -#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP) -#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val) -#define pDMA2_10_CONFIG ((uint16_t volatile *)DMA2_10_CONFIG) -#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG) -#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val) -#define pDMA2_10_NEXT_DESC_PTR ((void * volatile *)DMA2_10_NEXT_DESC_PTR) -#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR) -#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val) -#define pDMA2_10_START_ADDR ((void * volatile *)DMA2_10_START_ADDR) -#define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR) -#define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val) -#define pDMA2_10_X_COUNT ((uint16_t volatile *)DMA2_10_X_COUNT) -#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT) -#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val) -#define pDMA2_10_Y_COUNT ((uint16_t volatile *)DMA2_10_Y_COUNT) -#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT) -#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val) -#define pDMA2_10_X_MODIFY ((uint16_t volatile *)DMA2_10_X_MODIFY) -#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY) -#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val) -#define pDMA2_10_Y_MODIFY ((uint16_t volatile *)DMA2_10_Y_MODIFY) -#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY) -#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val) -#define pDMA2_10_CURR_DESC_PTR ((void * volatile *)DMA2_10_CURR_DESC_PTR) -#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR) -#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val) -#define pDMA2_10_CURR_ADDR ((void * volatile *)DMA2_10_CURR_ADDR) -#define bfin_read_DMA2_10_CURR_ADDR() bfin_readPTR(DMA2_10_CURR_ADDR) -#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val) -#define pDMA2_10_CURR_X_COUNT ((uint16_t volatile *)DMA2_10_CURR_X_COUNT) -#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT) -#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val) -#define pDMA2_10_CURR_Y_COUNT ((uint16_t volatile *)DMA2_10_CURR_Y_COUNT) -#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT) -#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val) -#define pDMA2_10_IRQ_STATUS ((uint16_t volatile *)DMA2_10_IRQ_STATUS) -#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS) -#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val) -#define pDMA2_10_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_10_PERIPHERAL_MAP) -#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP) -#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val) -#define pDMA2_11_CONFIG ((uint16_t volatile *)DMA2_11_CONFIG) -#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG) -#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val) -#define pDMA2_11_NEXT_DESC_PTR ((void * volatile *)DMA2_11_NEXT_DESC_PTR) -#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR) -#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val) -#define pDMA2_11_START_ADDR ((void * volatile *)DMA2_11_START_ADDR) -#define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR) -#define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val) -#define pDMA2_11_X_COUNT ((uint16_t volatile *)DMA2_11_X_COUNT) -#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT) -#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val) -#define pDMA2_11_Y_COUNT ((uint16_t volatile *)DMA2_11_Y_COUNT) -#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT) -#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val) -#define pDMA2_11_X_MODIFY ((uint16_t volatile *)DMA2_11_X_MODIFY) -#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY) -#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val) -#define pDMA2_11_Y_MODIFY ((uint16_t volatile *)DMA2_11_Y_MODIFY) -#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY) -#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val) -#define pDMA2_11_CURR_DESC_PTR ((void * volatile *)DMA2_11_CURR_DESC_PTR) -#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR) -#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val) -#define pDMA2_11_CURR_ADDR ((void * volatile *)DMA2_11_CURR_ADDR) -#define bfin_read_DMA2_11_CURR_ADDR() bfin_readPTR(DMA2_11_CURR_ADDR) -#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val) -#define pDMA2_11_CURR_X_COUNT ((uint16_t volatile *)DMA2_11_CURR_X_COUNT) -#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT) -#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val) -#define pDMA2_11_CURR_Y_COUNT ((uint16_t volatile *)DMA2_11_CURR_Y_COUNT) -#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT) -#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val) -#define pDMA2_11_IRQ_STATUS ((uint16_t volatile *)DMA2_11_IRQ_STATUS) -#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS) -#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val) -#define pDMA2_11_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_11_PERIPHERAL_MAP) -#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) -#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val) -#define pIMDMA_S0_CONFIG ((uint16_t volatile *)IMDMA_S0_CONFIG) -#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG) -#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val) -#define pIMDMA_S0_NEXT_DESC_PTR ((void * volatile *)IMDMA_S0_NEXT_DESC_PTR) -#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR) -#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val) -#define pIMDMA_S0_START_ADDR ((void * volatile *)IMDMA_S0_START_ADDR) -#define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR) -#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val) -#define pIMDMA_S0_X_COUNT ((uint16_t volatile *)IMDMA_S0_X_COUNT) -#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT) -#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val) -#define pIMDMA_S0_Y_COUNT ((uint16_t volatile *)IMDMA_S0_Y_COUNT) -#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT) -#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val) -#define pIMDMA_S0_X_MODIFY ((uint16_t volatile *)IMDMA_S0_X_MODIFY) -#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY) -#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val) -#define pIMDMA_S0_Y_MODIFY ((uint16_t volatile *)IMDMA_S0_Y_MODIFY) -#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY) -#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val) -#define pIMDMA_S0_CURR_DESC_PTR ((void * volatile *)IMDMA_S0_CURR_DESC_PTR) -#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR) -#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val) -#define pIMDMA_S0_CURR_ADDR ((void * volatile *)IMDMA_S0_CURR_ADDR) -#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR) -#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val) -#define pIMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_X_COUNT) -#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT) -#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val) -#define pIMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_Y_COUNT) -#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT) -#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val) -#define pIMDMA_S0_IRQ_STATUS ((uint16_t volatile *)IMDMA_S0_IRQ_STATUS) -#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS) -#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val) -#define pIMDMA_D0_CONFIG ((uint16_t volatile *)IMDMA_D0_CONFIG) -#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) -#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val) -#define pIMDMA_D0_NEXT_DESC_PTR ((void * volatile *)IMDMA_D0_NEXT_DESC_PTR) -#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR) -#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val) -#define pIMDMA_D0_START_ADDR ((void * volatile *)IMDMA_D0_START_ADDR) -#define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR) -#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val) -#define pIMDMA_D0_X_COUNT ((uint16_t volatile *)IMDMA_D0_X_COUNT) -#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT) -#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val) -#define pIMDMA_D0_Y_COUNT ((uint16_t volatile *)IMDMA_D0_Y_COUNT) -#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT) -#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val) -#define pIMDMA_D0_X_MODIFY ((uint16_t volatile *)IMDMA_D0_X_MODIFY) -#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY) -#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val) -#define pIMDMA_D0_Y_MODIFY ((uint16_t volatile *)IMDMA_D0_Y_MODIFY) -#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY) -#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val) -#define pIMDMA_D0_CURR_DESC_PTR ((void * volatile *)IMDMA_D0_CURR_DESC_PTR) -#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR) -#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val) -#define pIMDMA_D0_CURR_ADDR ((void * volatile *)IMDMA_D0_CURR_ADDR) -#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR) -#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val) -#define pIMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_X_COUNT) -#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT) -#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val) -#define pIMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_Y_COUNT) -#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT) -#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val) -#define pIMDMA_D0_IRQ_STATUS ((uint16_t volatile *)IMDMA_D0_IRQ_STATUS) -#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS) -#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val) -#define pIMDMA_S1_CONFIG ((uint16_t volatile *)IMDMA_S1_CONFIG) -#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG) -#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val) -#define pIMDMA_S1_NEXT_DESC_PTR ((void * volatile *)IMDMA_S1_NEXT_DESC_PTR) -#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR) -#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val) -#define pIMDMA_S1_START_ADDR ((void * volatile *)IMDMA_S1_START_ADDR) -#define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR) -#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val) -#define pIMDMA_S1_X_COUNT ((uint16_t volatile *)IMDMA_S1_X_COUNT) -#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT) -#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val) -#define pIMDMA_S1_Y_COUNT ((uint16_t volatile *)IMDMA_S1_Y_COUNT) -#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT) -#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val) -#define pIMDMA_S1_X_MODIFY ((uint16_t volatile *)IMDMA_S1_X_MODIFY) -#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY) -#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val) -#define pIMDMA_S1_Y_MODIFY ((uint16_t volatile *)IMDMA_S1_Y_MODIFY) -#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY) -#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val) -#define pIMDMA_S1_CURR_DESC_PTR ((void * volatile *)IMDMA_S1_CURR_DESC_PTR) -#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR) -#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val) -#define pIMDMA_S1_CURR_ADDR ((void * volatile *)IMDMA_S1_CURR_ADDR) -#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR) -#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val) -#define pIMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_X_COUNT) -#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT) -#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val) -#define pIMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_Y_COUNT) -#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT) -#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val) -#define pIMDMA_S1_IRQ_STATUS ((uint16_t volatile *)IMDMA_S1_IRQ_STATUS) -#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) -#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val) -#define pIMDMA_D1_CONFIG ((uint16_t volatile *)IMDMA_D1_CONFIG) -#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG) -#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val) -#define pIMDMA_D1_NEXT_DESC_PTR ((void * volatile *)IMDMA_D1_NEXT_DESC_PTR) -#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR) -#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val) -#define pIMDMA_D1_START_ADDR ((void * volatile *)IMDMA_D1_START_ADDR) -#define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR) -#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val) -#define pIMDMA_D1_X_COUNT ((uint16_t volatile *)IMDMA_D1_X_COUNT) -#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT) -#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val) -#define pIMDMA_D1_Y_COUNT ((uint16_t volatile *)IMDMA_D1_Y_COUNT) -#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT) -#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val) -#define pIMDMA_D1_X_MODIFY ((uint16_t volatile *)IMDMA_D1_X_MODIFY) -#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY) -#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val) -#define pIMDMA_D1_Y_MODIFY ((uint16_t volatile *)IMDMA_D1_Y_MODIFY) -#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY) -#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val) -#define pIMDMA_D1_CURR_DESC_PTR ((void * volatile *)IMDMA_D1_CURR_DESC_PTR) -#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR) -#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val) -#define pIMDMA_D1_CURR_ADDR ((void * volatile *)IMDMA_D1_CURR_ADDR) -#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR) -#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val) -#define pIMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_X_COUNT) -#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT) -#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val) -#define pIMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_Y_COUNT) -#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT) -#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val) -#define pIMDMA_D1_IRQ_STATUS ((uint16_t volatile *)IMDMA_D1_IRQ_STATUS) -#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS) -#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val) -#define pMDMA1_S0_CONFIG ((uint16_t volatile *)MDMA1_S0_CONFIG) -#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) -#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val) -#define pMDMA1_S0_NEXT_DESC_PTR ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR) -#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val) -#define pMDMA1_S0_START_ADDR ((void * volatile *)MDMA1_S0_START_ADDR) -#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR) -#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val) -#define pMDMA1_S0_X_COUNT ((uint16_t volatile *)MDMA1_S0_X_COUNT) -#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) -#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val) -#define pMDMA1_S0_Y_COUNT ((uint16_t volatile *)MDMA1_S0_Y_COUNT) -#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) -#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val) -#define pMDMA1_S0_X_MODIFY ((uint16_t volatile *)MDMA1_S0_X_MODIFY) -#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) -#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val) -#define pMDMA1_S0_Y_MODIFY ((uint16_t volatile *)MDMA1_S0_Y_MODIFY) -#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) -#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val) -#define pMDMA1_S0_CURR_DESC_PTR ((void * volatile *)MDMA1_S0_CURR_DESC_PTR) -#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR) -#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val) -#define pMDMA1_S0_CURR_ADDR ((void * volatile *)MDMA1_S0_CURR_ADDR) -#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR) -#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val) -#define pMDMA1_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_X_COUNT) -#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) -#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val) -#define pMDMA1_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_Y_COUNT) -#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) -#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val) -#define pMDMA1_S0_IRQ_STATUS ((uint16_t volatile *)MDMA1_S0_IRQ_STATUS) -#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) -#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val) -#define pMDMA1_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_S0_PERIPHERAL_MAP) -#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val) -#define pMDMA1_D0_CONFIG ((uint16_t volatile *)MDMA1_D0_CONFIG) -#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) -#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val) -#define pMDMA1_D0_NEXT_DESC_PTR ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR) -#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val) -#define pMDMA1_D0_START_ADDR ((void * volatile *)MDMA1_D0_START_ADDR) -#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR) -#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val) -#define pMDMA1_D0_X_COUNT ((uint16_t volatile *)MDMA1_D0_X_COUNT) -#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) -#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val) -#define pMDMA1_D0_Y_COUNT ((uint16_t volatile *)MDMA1_D0_Y_COUNT) -#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) -#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val) -#define pMDMA1_D0_X_MODIFY ((uint16_t volatile *)MDMA1_D0_X_MODIFY) -#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) -#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val) -#define pMDMA1_D0_Y_MODIFY ((uint16_t volatile *)MDMA1_D0_Y_MODIFY) -#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) -#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val) -#define pMDMA1_D0_CURR_DESC_PTR ((void * volatile *)MDMA1_D0_CURR_DESC_PTR) -#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR) -#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val) -#define pMDMA1_D0_CURR_ADDR ((void * volatile *)MDMA1_D0_CURR_ADDR) -#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR) -#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val) -#define pMDMA1_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_X_COUNT) -#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) -#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val) -#define pMDMA1_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_Y_COUNT) -#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) -#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val) -#define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS) -#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) -#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val) -#define pMDMA1_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_D0_PERIPHERAL_MAP) -#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val) -#define pMDMA1_S1_CONFIG ((uint16_t volatile *)MDMA1_S1_CONFIG) -#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) -#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val) -#define pMDMA1_S1_NEXT_DESC_PTR ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR) -#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val) -#define pMDMA1_S1_START_ADDR ((void * volatile *)MDMA1_S1_START_ADDR) -#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR) -#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val) -#define pMDMA1_S1_X_COUNT ((uint16_t volatile *)MDMA1_S1_X_COUNT) -#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) -#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val) -#define pMDMA1_S1_Y_COUNT ((uint16_t volatile *)MDMA1_S1_Y_COUNT) -#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) -#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val) -#define pMDMA1_S1_X_MODIFY ((uint16_t volatile *)MDMA1_S1_X_MODIFY) -#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) -#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val) -#define pMDMA1_S1_Y_MODIFY ((uint16_t volatile *)MDMA1_S1_Y_MODIFY) -#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) -#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val) -#define pMDMA1_S1_CURR_DESC_PTR ((void * volatile *)MDMA1_S1_CURR_DESC_PTR) -#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR) -#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val) -#define pMDMA1_S1_CURR_ADDR ((void * volatile *)MDMA1_S1_CURR_ADDR) -#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR) -#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val) -#define pMDMA1_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_X_COUNT) -#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) -#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) -#define pMDMA1_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_Y_COUNT) -#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) -#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) -#define pMDMA1_S1_IRQ_STATUS ((uint16_t volatile *)MDMA1_S1_IRQ_STATUS) -#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) -#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val) -#define pMDMA1_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_S1_PERIPHERAL_MAP) -#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val) -#define pMDMA1_D1_CONFIG ((uint16_t volatile *)MDMA1_D1_CONFIG) -#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) -#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val) -#define pMDMA1_D1_NEXT_DESC_PTR ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR) -#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val) -#define pMDMA1_D1_START_ADDR ((void * volatile *)MDMA1_D1_START_ADDR) -#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR) -#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val) -#define pMDMA1_D1_X_COUNT ((uint16_t volatile *)MDMA1_D1_X_COUNT) -#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) -#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val) -#define pMDMA1_D1_Y_COUNT ((uint16_t volatile *)MDMA1_D1_Y_COUNT) -#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) -#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val) -#define pMDMA1_D1_X_MODIFY ((uint16_t volatile *)MDMA1_D1_X_MODIFY) -#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) -#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val) -#define pMDMA1_D1_Y_MODIFY ((uint16_t volatile *)MDMA1_D1_Y_MODIFY) -#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) -#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val) -#define pMDMA1_D1_CURR_DESC_PTR ((void * volatile *)MDMA1_D1_CURR_DESC_PTR) -#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR) -#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val) -#define pMDMA1_D1_CURR_ADDR ((void * volatile *)MDMA1_D1_CURR_ADDR) -#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR) -#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val) -#define pMDMA1_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_X_COUNT) -#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) -#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val) -#define pMDMA1_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_Y_COUNT) -#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) -#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val) -#define pMDMA1_D1_IRQ_STATUS ((uint16_t volatile *)MDMA1_D1_IRQ_STATUS) -#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) -#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val) -#define pMDMA1_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_D1_PERIPHERAL_MAP) -#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val) -#define pMDMA2_S0_CONFIG ((uint16_t volatile *)MDMA2_S0_CONFIG) -#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG) -#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val) -#define pMDMA2_S0_NEXT_DESC_PTR ((void * volatile *)MDMA2_S0_NEXT_DESC_PTR) -#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val) -#define pMDMA2_S0_START_ADDR ((void * volatile *)MDMA2_S0_START_ADDR) -#define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR) -#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val) -#define pMDMA2_S0_X_COUNT ((uint16_t volatile *)MDMA2_S0_X_COUNT) -#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT) -#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val) -#define pMDMA2_S0_Y_COUNT ((uint16_t volatile *)MDMA2_S0_Y_COUNT) -#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT) -#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val) -#define pMDMA2_S0_X_MODIFY ((uint16_t volatile *)MDMA2_S0_X_MODIFY) -#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY) -#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val) -#define pMDMA2_S0_Y_MODIFY ((uint16_t volatile *)MDMA2_S0_Y_MODIFY) -#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY) -#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val) -#define pMDMA2_S0_CURR_DESC_PTR ((void * volatile *)MDMA2_S0_CURR_DESC_PTR) -#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR) -#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val) -#define pMDMA2_S0_CURR_ADDR ((void * volatile *)MDMA2_S0_CURR_ADDR) -#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR) -#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val) -#define pMDMA2_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_X_COUNT) -#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT) -#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val) -#define pMDMA2_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_Y_COUNT) -#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT) -#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val) -#define pMDMA2_S0_IRQ_STATUS ((uint16_t volatile *)MDMA2_S0_IRQ_STATUS) -#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS) -#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val) -#define pMDMA2_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_S0_PERIPHERAL_MAP) -#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val) -#define pMDMA2_D0_CONFIG ((uint16_t volatile *)MDMA2_D0_CONFIG) -#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG) -#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val) -#define pMDMA2_D0_NEXT_DESC_PTR ((void * volatile *)MDMA2_D0_NEXT_DESC_PTR) -#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val) -#define pMDMA2_D0_START_ADDR ((void * volatile *)MDMA2_D0_START_ADDR) -#define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR) -#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val) -#define pMDMA2_D0_X_COUNT ((uint16_t volatile *)MDMA2_D0_X_COUNT) -#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT) -#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val) -#define pMDMA2_D0_Y_COUNT ((uint16_t volatile *)MDMA2_D0_Y_COUNT) -#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT) -#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val) -#define pMDMA2_D0_X_MODIFY ((uint16_t volatile *)MDMA2_D0_X_MODIFY) -#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY) -#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val) -#define pMDMA2_D0_Y_MODIFY ((uint16_t volatile *)MDMA2_D0_Y_MODIFY) -#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY) -#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val) -#define pMDMA2_D0_CURR_DESC_PTR ((void * volatile *)MDMA2_D0_CURR_DESC_PTR) -#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR) -#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val) -#define pMDMA2_D0_CURR_ADDR ((void * volatile *)MDMA2_D0_CURR_ADDR) -#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR) -#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val) -#define pMDMA2_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_X_COUNT) -#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT) -#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val) -#define pMDMA2_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_Y_COUNT) -#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT) -#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val) -#define pMDMA2_D0_IRQ_STATUS ((uint16_t volatile *)MDMA2_D0_IRQ_STATUS) -#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS) -#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val) -#define pMDMA2_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_D0_PERIPHERAL_MAP) -#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val) -#define pMDMA2_S1_CONFIG ((uint16_t volatile *)MDMA2_S1_CONFIG) -#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG) -#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val) -#define pMDMA2_S1_NEXT_DESC_PTR ((void * volatile *)MDMA2_S1_NEXT_DESC_PTR) -#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val) -#define pMDMA2_S1_START_ADDR ((void * volatile *)MDMA2_S1_START_ADDR) -#define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR) -#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val) -#define pMDMA2_S1_X_COUNT ((uint16_t volatile *)MDMA2_S1_X_COUNT) -#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT) -#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val) -#define pMDMA2_S1_Y_COUNT ((uint16_t volatile *)MDMA2_S1_Y_COUNT) -#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT) -#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val) -#define pMDMA2_S1_X_MODIFY ((uint16_t volatile *)MDMA2_S1_X_MODIFY) -#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY) -#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val) -#define pMDMA2_S1_Y_MODIFY ((uint16_t volatile *)MDMA2_S1_Y_MODIFY) -#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY) -#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val) -#define pMDMA2_S1_CURR_DESC_PTR ((void * volatile *)MDMA2_S1_CURR_DESC_PTR) -#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR) -#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val) -#define pMDMA2_S1_CURR_ADDR ((void * volatile *)MDMA2_S1_CURR_ADDR) -#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR) -#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val) -#define pMDMA2_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_X_COUNT) -#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT) -#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val) -#define pMDMA2_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_Y_COUNT) -#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT) -#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val) -#define pMDMA2_S1_IRQ_STATUS ((uint16_t volatile *)MDMA2_S1_IRQ_STATUS) -#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS) -#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val) -#define pMDMA2_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_S1_PERIPHERAL_MAP) -#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val) -#define pMDMA2_D1_CONFIG ((uint16_t volatile *)MDMA2_D1_CONFIG) -#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG) -#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val) -#define pMDMA2_D1_NEXT_DESC_PTR ((void * volatile *)MDMA2_D1_NEXT_DESC_PTR) -#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val) -#define pMDMA2_D1_START_ADDR ((void * volatile *)MDMA2_D1_START_ADDR) -#define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR) -#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val) -#define pMDMA2_D1_X_COUNT ((uint16_t volatile *)MDMA2_D1_X_COUNT) -#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT) -#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val) -#define pMDMA2_D1_Y_COUNT ((uint16_t volatile *)MDMA2_D1_Y_COUNT) -#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT) -#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val) -#define pMDMA2_D1_X_MODIFY ((uint16_t volatile *)MDMA2_D1_X_MODIFY) -#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY) -#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val) -#define pMDMA2_D1_Y_MODIFY ((uint16_t volatile *)MDMA2_D1_Y_MODIFY) -#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY) -#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val) -#define pMDMA2_D1_CURR_DESC_PTR ((void * volatile *)MDMA2_D1_CURR_DESC_PTR) -#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR) -#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val) -#define pMDMA2_D1_CURR_ADDR ((void * volatile *)MDMA2_D1_CURR_ADDR) -#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR) -#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val) -#define pMDMA2_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_X_COUNT) -#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT) -#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val) -#define pMDMA2_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_Y_COUNT) -#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT) -#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val) -#define pMDMA2_D1_IRQ_STATUS ((uint16_t volatile *)MDMA2_D1_IRQ_STATUS) -#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS) -#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val) -#define pMDMA2_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_D1_PERIPHERAL_MAP) -#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) -#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) -#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) -#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) -#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) -#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) -#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) -#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) -#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) -#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) -#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) -#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) -#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) -#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) -#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) -#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) -#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) -#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) -#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) -#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) -#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) -#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) -#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) -#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) -#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) -#define pTIMER11_CONFIG ((uint16_t volatile *)TIMER11_CONFIG) -#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG) -#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val) -#define pTIMER11_COUNTER ((uint32_t volatile *)TIMER11_COUNTER) -#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER) -#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val) -#define pTIMER11_PERIOD ((uint32_t volatile *)TIMER11_PERIOD) -#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD) -#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val) -#define pTIMER11_WIDTH ((uint32_t volatile *)TIMER11_WIDTH) -#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH) -#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH, val) -#define pTMRS4_ENABLE ((uint32_t volatile *)TMRS4_ENABLE) -#define bfin_read_TMRS4_ENABLE() bfin_read32(TMRS4_ENABLE) -#define bfin_write_TMRS4_ENABLE(val) bfin_write32(TMRS4_ENABLE, val) -#define pTMRS4_DISABLE ((uint32_t volatile *)TMRS4_DISABLE) -#define bfin_read_TMRS4_DISABLE() bfin_read32(TMRS4_DISABLE) -#define bfin_write_TMRS4_DISABLE(val) bfin_write32(TMRS4_DISABLE, val) -#define pTMRS4_STATUS ((uint32_t volatile *)TMRS4_STATUS) -#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS) -#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS, val) -#define pTMRS8_ENABLE ((uint32_t volatile *)TMRS8_ENABLE) -#define bfin_read_TMRS8_ENABLE() bfin_read32(TMRS8_ENABLE) -#define bfin_write_TMRS8_ENABLE(val) bfin_write32(TMRS8_ENABLE, val) -#define pTMRS8_DISABLE ((uint32_t volatile *)TMRS8_DISABLE) -#define bfin_read_TMRS8_DISABLE() bfin_read32(TMRS8_DISABLE) -#define bfin_write_TMRS8_DISABLE(val) bfin_write32(TMRS8_DISABLE, val) -#define pTMRS8_STATUS ((uint32_t volatile *)TMRS8_STATUS) -#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS) -#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS, val) -#define pFIO0_FLAG_D ((uint16_t volatile *)FIO0_FLAG_D) -#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D) -#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D, val) -#define pFIO0_FLAG_C ((uint16_t volatile *)FIO0_FLAG_C) -#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C) -#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C, val) -#define pFIO0_FLAG_S ((uint16_t volatile *)FIO0_FLAG_S) -#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S) -#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S, val) -#define pFIO0_FLAG_T ((uint16_t volatile *)FIO0_FLAG_T) -#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T) -#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T, val) -#define pFIO0_MASKA_D ((uint16_t volatile *)FIO0_MASKA_D) -#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D) -#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D, val) -#define pFIO0_MASKA_C ((uint16_t volatile *)FIO0_MASKA_C) -#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C) -#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C, val) -#define pFIO0_MASKA_S ((uint16_t volatile *)FIO0_MASKA_S) -#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S) -#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S, val) -#define pFIO0_MASKA_T ((uint16_t volatile *)FIO0_MASKA_T) -#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T) -#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T, val) -#define pFIO0_MASKB_D ((uint16_t volatile *)FIO0_MASKB_D) -#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D) -#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D, val) -#define pFIO0_MASKB_C ((uint16_t volatile *)FIO0_MASKB_C) -#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C) -#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C, val) -#define pFIO0_MASKB_S ((uint16_t volatile *)FIO0_MASKB_S) -#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S) -#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S, val) -#define pFIO0_MASKB_T ((uint16_t volatile *)FIO0_MASKB_T) -#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T) -#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T, val) -#define pFIO0_DIR ((uint16_t volatile *)FIO0_DIR) -#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR) -#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR, val) -#define pFIO0_POLAR ((uint16_t volatile *)FIO0_POLAR) -#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR) -#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR, val) -#define pFIO0_EDGE ((uint16_t volatile *)FIO0_EDGE) -#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE) -#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE, val) -#define pFIO0_BOTH ((uint16_t volatile *)FIO0_BOTH) -#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH) -#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH, val) -#define pFIO0_INEN ((uint16_t volatile *)FIO0_INEN) -#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN) -#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN, val) -#define pFIO1_FLAG_D ((uint16_t volatile *)FIO1_FLAG_D) -#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D) -#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D, val) -#define pFIO1_FLAG_C ((uint16_t volatile *)FIO1_FLAG_C) -#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C) -#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C, val) -#define pFIO1_FLAG_S ((uint16_t volatile *)FIO1_FLAG_S) -#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S) -#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S, val) -#define pFIO1_FLAG_T ((uint16_t volatile *)FIO1_FLAG_T) -#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T) -#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T, val) -#define pFIO1_MASKA_D ((uint16_t volatile *)FIO1_MASKA_D) -#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D) -#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D, val) -#define pFIO1_MASKA_C ((uint16_t volatile *)FIO1_MASKA_C) -#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C) -#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C, val) -#define pFIO1_MASKA_S ((uint16_t volatile *)FIO1_MASKA_S) -#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S) -#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S, val) -#define pFIO1_MASKA_T ((uint16_t volatile *)FIO1_MASKA_T) -#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T) -#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T, val) -#define pFIO1_MASKB_D ((uint16_t volatile *)FIO1_MASKB_D) -#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D) -#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D, val) -#define pFIO1_MASKB_C ((uint16_t volatile *)FIO1_MASKB_C) -#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C) -#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C, val) -#define pFIO1_MASKB_S ((uint16_t volatile *)FIO1_MASKB_S) -#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S) -#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S, val) -#define pFIO1_MASKB_T ((uint16_t volatile *)FIO1_MASKB_T) -#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T) -#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T, val) -#define pFIO1_DIR ((uint16_t volatile *)FIO1_DIR) -#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR) -#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR, val) -#define pFIO1_POLAR ((uint16_t volatile *)FIO1_POLAR) -#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR) -#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR, val) -#define pFIO1_EDGE ((uint16_t volatile *)FIO1_EDGE) -#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE) -#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE, val) -#define pFIO1_BOTH ((uint16_t volatile *)FIO1_BOTH) -#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH) -#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH, val) -#define pFIO1_INEN ((uint16_t volatile *)FIO1_INEN) -#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN) -#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN, val) -#define pFIO2_FLAG_D ((uint16_t volatile *)FIO2_FLAG_D) -#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D) -#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D, val) -#define pFIO2_FLAG_C ((uint16_t volatile *)FIO2_FLAG_C) -#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C) -#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C, val) -#define pFIO2_FLAG_S ((uint16_t volatile *)FIO2_FLAG_S) -#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S) -#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S, val) -#define pFIO2_FLAG_T ((uint16_t volatile *)FIO2_FLAG_T) -#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T) -#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T, val) -#define pFIO2_MASKA_D ((uint16_t volatile *)FIO2_MASKA_D) -#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D) -#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D, val) -#define pFIO2_MASKA_C ((uint16_t volatile *)FIO2_MASKA_C) -#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C) -#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C, val) -#define pFIO2_MASKA_S ((uint16_t volatile *)FIO2_MASKA_S) -#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S) -#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S, val) -#define pFIO2_MASKA_T ((uint16_t volatile *)FIO2_MASKA_T) -#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T) -#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T, val) -#define pFIO2_MASKB_D ((uint16_t volatile *)FIO2_MASKB_D) -#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D) -#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D, val) -#define pFIO2_MASKB_C ((uint16_t volatile *)FIO2_MASKB_C) -#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C) -#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C, val) -#define pFIO2_MASKB_S ((uint16_t volatile *)FIO2_MASKB_S) -#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S) -#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S, val) -#define pFIO2_MASKB_T ((uint16_t volatile *)FIO2_MASKB_T) -#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T) -#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T, val) -#define pFIO2_DIR ((uint16_t volatile *)FIO2_DIR) -#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR) -#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR, val) -#define pFIO2_POLAR ((uint16_t volatile *)FIO2_POLAR) -#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR) -#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR, val) -#define pFIO2_EDGE ((uint16_t volatile *)FIO2_EDGE) -#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE) -#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE, val) -#define pFIO2_BOTH ((uint16_t volatile *)FIO2_BOTH) -#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH) -#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH, val) -#define pFIO2_INEN ((uint16_t volatile *)FIO2_INEN) -#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN) -#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pEVT0 ((void * volatile *)EVT0) -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ */ diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h b/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h deleted file mode 100644 index b4857c3..0000000 --- a/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h +++ /dev/null @@ -1,670 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ -#define __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ - -#define PLL_CTL 0xFFC00000 -#define PLL_DIV 0xFFC00004 -#define VR_CTL 0xFFC00008 -#define PLL_STAT 0xFFC0000C -#define PLL_LOCKCNT 0xFFC00010 -#define CHIPID 0xFFC00014 -#define SPI_CTL 0xFFC00500 -#define SPI_FLG 0xFFC00504 -#define SPI_STAT 0xFFC00508 -#define SPI_TDBR 0xFFC0050C -#define SPI_RDBR 0xFFC00510 -#define SPI_BAUD 0xFFC00514 -#define SPI_SHADOW 0xFFC00518 -#define WDOGA_CTL 0xFFC00200 -#define WDOGA_CNT 0xFFC00204 -#define WDOGA_STAT 0xFFC00208 -#define WDOGB_CTL 0xFFC01200 -#define WDOGB_CNT 0xFFC01204 -#define WDOGB_STAT 0xFFC01208 -#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */ -#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */ -#define DMA1_0_CONFIG 0xFFC01C08 -#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 -#define DMA1_0_START_ADDR 0xFFC01C04 -#define DMA1_0_X_COUNT 0xFFC01C10 -#define DMA1_0_Y_COUNT 0xFFC01C18 -#define DMA1_0_X_MODIFY 0xFFC01C14 -#define DMA1_0_Y_MODIFY 0xFFC01C1C -#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 -#define DMA1_0_CURR_ADDR 0xFFC01C24 -#define DMA1_0_CURR_X_COUNT 0xFFC01C30 -#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 -#define DMA1_0_IRQ_STATUS 0xFFC01C28 -#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C -#define DMA1_1_CONFIG 0xFFC01C48 -#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 -#define DMA1_1_START_ADDR 0xFFC01C44 -#define DMA1_1_X_COUNT 0xFFC01C50 -#define DMA1_1_Y_COUNT 0xFFC01C58 -#define DMA1_1_X_MODIFY 0xFFC01C54 -#define DMA1_1_Y_MODIFY 0xFFC01C5C -#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 -#define DMA1_1_CURR_ADDR 0xFFC01C64 -#define DMA1_1_CURR_X_COUNT 0xFFC01C70 -#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 -#define DMA1_1_IRQ_STATUS 0xFFC01C68 -#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C -#define DMA1_2_CONFIG 0xFFC01C88 -#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 -#define DMA1_2_START_ADDR 0xFFC01C84 -#define DMA1_2_X_COUNT 0xFFC01C90 -#define DMA1_2_Y_COUNT 0xFFC01C98 -#define DMA1_2_X_MODIFY 0xFFC01C94 -#define DMA1_2_Y_MODIFY 0xFFC01C9C -#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 -#define DMA1_2_CURR_ADDR 0xFFC01CA4 -#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 -#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 -#define DMA1_2_IRQ_STATUS 0xFFC01CA8 -#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC -#define DMA1_3_CONFIG 0xFFC01CC8 -#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 -#define DMA1_3_START_ADDR 0xFFC01CC4 -#define DMA1_3_X_COUNT 0xFFC01CD0 -#define DMA1_3_Y_COUNT 0xFFC01CD8 -#define DMA1_3_X_MODIFY 0xFFC01CD4 -#define DMA1_3_Y_MODIFY 0xFFC01CDC -#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 -#define DMA1_3_CURR_ADDR 0xFFC01CE4 -#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 -#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 -#define DMA1_3_IRQ_STATUS 0xFFC01CE8 -#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC -#define DMA1_4_CONFIG 0xFFC01D08 -#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 -#define DMA1_4_START_ADDR 0xFFC01D04 -#define DMA1_4_X_COUNT 0xFFC01D10 -#define DMA1_4_Y_COUNT 0xFFC01D18 -#define DMA1_4_X_MODIFY 0xFFC01D14 -#define DMA1_4_Y_MODIFY 0xFFC01D1C -#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 -#define DMA1_4_CURR_ADDR 0xFFC01D24 -#define DMA1_4_CURR_X_COUNT 0xFFC01D30 -#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 -#define DMA1_4_IRQ_STATUS 0xFFC01D28 -#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C -#define DMA1_5_CONFIG 0xFFC01D48 -#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 -#define DMA1_5_START_ADDR 0xFFC01D44 -#define DMA1_5_X_COUNT 0xFFC01D50 -#define DMA1_5_Y_COUNT 0xFFC01D58 -#define DMA1_5_X_MODIFY 0xFFC01D54 -#define DMA1_5_Y_MODIFY 0xFFC01D5C -#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 -#define DMA1_5_CURR_ADDR 0xFFC01D64 -#define DMA1_5_CURR_X_COUNT 0xFFC01D70 -#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 -#define DMA1_5_IRQ_STATUS 0xFFC01D68 -#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C -#define DMA1_6_CONFIG 0xFFC01D88 -#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 -#define DMA1_6_START_ADDR 0xFFC01D84 -#define DMA1_6_X_COUNT 0xFFC01D90 -#define DMA1_6_Y_COUNT 0xFFC01D98 -#define DMA1_6_X_MODIFY 0xFFC01D94 -#define DMA1_6_Y_MODIFY 0xFFC01D9C -#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 -#define DMA1_6_CURR_ADDR 0xFFC01DA4 -#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 -#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 -#define DMA1_6_IRQ_STATUS 0xFFC01DA8 -#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC -#define DMA1_7_CONFIG 0xFFC01DC8 -#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 -#define DMA1_7_START_ADDR 0xFFC01DC4 -#define DMA1_7_X_COUNT 0xFFC01DD0 -#define DMA1_7_Y_COUNT 0xFFC01DD8 -#define DMA1_7_X_MODIFY 0xFFC01DD4 -#define DMA1_7_Y_MODIFY 0xFFC01DDC -#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 -#define DMA1_7_CURR_ADDR 0xFFC01DE4 -#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 -#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 -#define DMA1_7_IRQ_STATUS 0xFFC01DE8 -#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC -#define DMA1_8_CONFIG 0xFFC01E08 -#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 -#define DMA1_8_START_ADDR 0xFFC01E04 -#define DMA1_8_X_COUNT 0xFFC01E10 -#define DMA1_8_Y_COUNT 0xFFC01E18 -#define DMA1_8_X_MODIFY 0xFFC01E14 -#define DMA1_8_Y_MODIFY 0xFFC01E1C -#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 -#define DMA1_8_CURR_ADDR 0xFFC01E24 -#define DMA1_8_CURR_X_COUNT 0xFFC01E30 -#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 -#define DMA1_8_IRQ_STATUS 0xFFC01E28 -#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C -#define DMA1_9_CONFIG 0xFFC01E48 -#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 -#define DMA1_9_START_ADDR 0xFFC01E44 -#define DMA1_9_X_COUNT 0xFFC01E50 -#define DMA1_9_Y_COUNT 0xFFC01E58 -#define DMA1_9_X_MODIFY 0xFFC01E54 -#define DMA1_9_Y_MODIFY 0xFFC01E5C -#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 -#define DMA1_9_CURR_ADDR 0xFFC01E64 -#define DMA1_9_CURR_X_COUNT 0xFFC01E70 -#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 -#define DMA1_9_IRQ_STATUS 0xFFC01E68 -#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C -#define DMA1_10_CONFIG 0xFFC01E88 -#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 -#define DMA1_10_START_ADDR 0xFFC01E84 -#define DMA1_10_X_COUNT 0xFFC01E90 -#define DMA1_10_Y_COUNT 0xFFC01E98 -#define DMA1_10_X_MODIFY 0xFFC01E94 -#define DMA1_10_Y_MODIFY 0xFFC01E9C -#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 -#define DMA1_10_CURR_ADDR 0xFFC01EA4 -#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 -#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 -#define DMA1_10_IRQ_STATUS 0xFFC01EA8 -#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC -#define DMA1_11_CONFIG 0xFFC01EC8 -#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 -#define DMA1_11_START_ADDR 0xFFC01EC4 -#define DMA1_11_X_COUNT 0xFFC01ED0 -#define DMA1_11_Y_COUNT 0xFFC01ED8 -#define DMA1_11_X_MODIFY 0xFFC01ED4 -#define DMA1_11_Y_MODIFY 0xFFC01EDC -#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 -#define DMA1_11_CURR_ADDR 0xFFC01EE4 -#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 -#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 -#define DMA1_11_IRQ_STATUS 0xFFC01EE8 -#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC -#define DMA2_TC_PER 0xFFC00B0C -#define DMA2_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */ -#define DMA2_0_CONFIG 0xFFC00C08 -#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 -#define DMA2_0_START_ADDR 0xFFC00C04 -#define DMA2_0_X_COUNT 0xFFC00C10 -#define DMA2_0_Y_COUNT 0xFFC00C18 -#define DMA2_0_X_MODIFY 0xFFC00C14 -#define DMA2_0_Y_MODIFY 0xFFC00C1C -#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 -#define DMA2_0_CURR_ADDR 0xFFC00C24 -#define DMA2_0_CURR_X_COUNT 0xFFC00C30 -#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 -#define DMA2_0_IRQ_STATUS 0xFFC00C28 -#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C -#define DMA2_1_CONFIG 0xFFC00C48 -#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 -#define DMA2_1_START_ADDR 0xFFC00C44 -#define DMA2_1_X_COUNT 0xFFC00C50 -#define DMA2_1_Y_COUNT 0xFFC00C58 -#define DMA2_1_X_MODIFY 0xFFC00C54 -#define DMA2_1_Y_MODIFY 0xFFC00C5C -#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 -#define DMA2_1_CURR_ADDR 0xFFC00C64 -#define DMA2_1_CURR_X_COUNT 0xFFC00C70 -#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 -#define DMA2_1_IRQ_STATUS 0xFFC00C68 -#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C -#define DMA2_2_CONFIG 0xFFC00C88 -#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 -#define DMA2_2_START_ADDR 0xFFC00C84 -#define DMA2_2_X_COUNT 0xFFC00C90 -#define DMA2_2_Y_COUNT 0xFFC00C98 -#define DMA2_2_X_MODIFY 0xFFC00C94 -#define DMA2_2_Y_MODIFY 0xFFC00C9C -#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 -#define DMA2_2_CURR_ADDR 0xFFC00CA4 -#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 -#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 -#define DMA2_2_IRQ_STATUS 0xFFC00CA8 -#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC -#define DMA2_3_CONFIG 0xFFC00CC8 -#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 -#define DMA2_3_START_ADDR 0xFFC00CC4 -#define DMA2_3_X_COUNT 0xFFC00CD0 -#define DMA2_3_Y_COUNT 0xFFC00CD8 -#define DMA2_3_X_MODIFY 0xFFC00CD4 -#define DMA2_3_Y_MODIFY 0xFFC00CDC -#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 -#define DMA2_3_CURR_ADDR 0xFFC00CE4 -#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 -#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 -#define DMA2_3_IRQ_STATUS 0xFFC00CE8 -#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC -#define DMA2_4_CONFIG 0xFFC00D08 -#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 -#define DMA2_4_START_ADDR 0xFFC00D04 -#define DMA2_4_X_COUNT 0xFFC00D10 -#define DMA2_4_Y_COUNT 0xFFC00D18 -#define DMA2_4_X_MODIFY 0xFFC00D14 -#define DMA2_4_Y_MODIFY 0xFFC00D1C -#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 -#define DMA2_4_CURR_ADDR 0xFFC00D24 -#define DMA2_4_CURR_X_COUNT 0xFFC00D30 -#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 -#define DMA2_4_IRQ_STATUS 0xFFC00D28 -#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C -#define DMA2_5_CONFIG 0xFFC00D48 -#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 -#define DMA2_5_START_ADDR 0xFFC00D44 -#define DMA2_5_X_COUNT 0xFFC00D50 -#define DMA2_5_Y_COUNT 0xFFC00D58 -#define DMA2_5_X_MODIFY 0xFFC00D54 -#define DMA2_5_Y_MODIFY 0xFFC00D5C -#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 -#define DMA2_5_CURR_ADDR 0xFFC00D64 -#define DMA2_5_CURR_X_COUNT 0xFFC00D70 -#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 -#define DMA2_5_IRQ_STATUS 0xFFC00D68 -#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C -#define DMA2_6_CONFIG 0xFFC00D88 -#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 -#define DMA2_6_START_ADDR 0xFFC00D84 -#define DMA2_6_X_COUNT 0xFFC00D90 -#define DMA2_6_Y_COUNT 0xFFC00D98 -#define DMA2_6_X_MODIFY 0xFFC00D94 -#define DMA2_6_Y_MODIFY 0xFFC00D9C -#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 -#define DMA2_6_CURR_ADDR 0xFFC00DA4 -#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 -#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 -#define DMA2_6_IRQ_STATUS 0xFFC00DA8 -#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC -#define DMA2_7_CONFIG 0xFFC00DC8 -#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 -#define DMA2_7_START_ADDR 0xFFC00DC4 -#define DMA2_7_X_COUNT 0xFFC00DD0 -#define DMA2_7_Y_COUNT 0xFFC00DD8 -#define DMA2_7_X_MODIFY 0xFFC00DD4 -#define DMA2_7_Y_MODIFY 0xFFC00DDC -#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 -#define DMA2_7_CURR_ADDR 0xFFC00DE4 -#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 -#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 -#define DMA2_7_IRQ_STATUS 0xFFC00DE8 -#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC -#define DMA2_8_CONFIG 0xFFC00E08 -#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 -#define DMA2_8_START_ADDR 0xFFC00E04 -#define DMA2_8_X_COUNT 0xFFC00E10 -#define DMA2_8_Y_COUNT 0xFFC00E18 -#define DMA2_8_X_MODIFY 0xFFC00E14 -#define DMA2_8_Y_MODIFY 0xFFC00E1C -#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 -#define DMA2_8_CURR_ADDR 0xFFC00E24 -#define DMA2_8_CURR_X_COUNT 0xFFC00E30 -#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 -#define DMA2_8_IRQ_STATUS 0xFFC00E28 -#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C -#define DMA2_9_CONFIG 0xFFC00E48 -#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 -#define DMA2_9_START_ADDR 0xFFC00E44 -#define DMA2_9_X_COUNT 0xFFC00E50 -#define DMA2_9_Y_COUNT 0xFFC00E58 -#define DMA2_9_X_MODIFY 0xFFC00E54 -#define DMA2_9_Y_MODIFY 0xFFC00E5C -#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 -#define DMA2_9_CURR_ADDR 0xFFC00E64 -#define DMA2_9_CURR_X_COUNT 0xFFC00E70 -#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 -#define DMA2_9_IRQ_STATUS 0xFFC00E68 -#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C -#define DMA2_10_CONFIG 0xFFC00E88 -#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 -#define DMA2_10_START_ADDR 0xFFC00E84 -#define DMA2_10_X_COUNT 0xFFC00E90 -#define DMA2_10_Y_COUNT 0xFFC00E98 -#define DMA2_10_X_MODIFY 0xFFC00E94 -#define DMA2_10_Y_MODIFY 0xFFC00E9C -#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 -#define DMA2_10_CURR_ADDR 0xFFC00EA4 -#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 -#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 -#define DMA2_10_IRQ_STATUS 0xFFC00EA8 -#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC -#define DMA2_11_CONFIG 0xFFC00EC8 -#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 -#define DMA2_11_START_ADDR 0xFFC00EC4 -#define DMA2_11_X_COUNT 0xFFC00ED0 -#define DMA2_11_Y_COUNT 0xFFC00ED8 -#define DMA2_11_X_MODIFY 0xFFC00ED4 -#define DMA2_11_Y_MODIFY 0xFFC00EDC -#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 -#define DMA2_11_CURR_ADDR 0xFFC00EE4 -#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 -#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 -#define DMA2_11_IRQ_STATUS 0xFFC00EE8 -#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC -#define IMDMA_S0_CONFIG 0xFFC01848 -#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 -#define IMDMA_S0_START_ADDR 0xFFC01844 -#define IMDMA_S0_X_COUNT 0xFFC01850 -#define IMDMA_S0_Y_COUNT 0xFFC01858 -#define IMDMA_S0_X_MODIFY 0xFFC01854 -#define IMDMA_S0_Y_MODIFY 0xFFC0185C -#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 -#define IMDMA_S0_CURR_ADDR 0xFFC01864 -#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 -#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 -#define IMDMA_S0_IRQ_STATUS 0xFFC01868 -#define IMDMA_D0_CONFIG 0xFFC01808 -#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 -#define IMDMA_D0_START_ADDR 0xFFC01804 -#define IMDMA_D0_X_COUNT 0xFFC01810 -#define IMDMA_D0_Y_COUNT 0xFFC01818 -#define IMDMA_D0_X_MODIFY 0xFFC01814 -#define IMDMA_D0_Y_MODIFY 0xFFC0181C -#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 -#define IMDMA_D0_CURR_ADDR 0xFFC01824 -#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 -#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 -#define IMDMA_D0_IRQ_STATUS 0xFFC01828 -#define IMDMA_S1_CONFIG 0xFFC018C8 -#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 -#define IMDMA_S1_START_ADDR 0xFFC018C4 -#define IMDMA_S1_X_COUNT 0xFFC018D0 -#define IMDMA_S1_Y_COUNT 0xFFC018D8 -#define IMDMA_S1_X_MODIFY 0xFFC018D4 -#define IMDMA_S1_Y_MODIFY 0xFFC018DC -#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 -#define IMDMA_S1_CURR_ADDR 0xFFC018E4 -#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 -#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 -#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 -#define IMDMA_D1_CONFIG 0xFFC01888 -#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 -#define IMDMA_D1_START_ADDR 0xFFC01884 -#define IMDMA_D1_X_COUNT 0xFFC01890 -#define IMDMA_D1_Y_COUNT 0xFFC01898 -#define IMDMA_D1_X_MODIFY 0xFFC01894 -#define IMDMA_D1_Y_MODIFY 0xFFC0189C -#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 -#define IMDMA_D1_CURR_ADDR 0xFFC018A4 -#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 -#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 -#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 -#define MDMA1_S0_CONFIG 0xFFC01F48 -#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 -#define MDMA1_S0_START_ADDR 0xFFC01F44 -#define MDMA1_S0_X_COUNT 0xFFC01F50 -#define MDMA1_S0_Y_COUNT 0xFFC01F58 -#define MDMA1_S0_X_MODIFY 0xFFC01F54 -#define MDMA1_S0_Y_MODIFY 0xFFC01F5C -#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 -#define MDMA1_S0_CURR_ADDR 0xFFC01F64 -#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 -#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 -#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 -#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C -#define MDMA1_D0_CONFIG 0xFFC01F08 -#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 -#define MDMA1_D0_START_ADDR 0xFFC01F04 -#define MDMA1_D0_X_COUNT 0xFFC01F10 -#define MDMA1_D0_Y_COUNT 0xFFC01F18 -#define MDMA1_D0_X_MODIFY 0xFFC01F14 -#define MDMA1_D0_Y_MODIFY 0xFFC01F1C -#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 -#define MDMA1_D0_CURR_ADDR 0xFFC01F24 -#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 -#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 -#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 -#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C -#define MDMA1_S1_CONFIG 0xFFC01FC8 -#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 -#define MDMA1_S1_START_ADDR 0xFFC01FC4 -#define MDMA1_S1_X_COUNT 0xFFC01FD0 -#define MDMA1_S1_Y_COUNT 0xFFC01FD8 -#define MDMA1_S1_X_MODIFY 0xFFC01FD4 -#define MDMA1_S1_Y_MODIFY 0xFFC01FDC -#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 -#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 -#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 -#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 -#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 -#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC -#define MDMA1_D1_CONFIG 0xFFC01F88 -#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 -#define MDMA1_D1_START_ADDR 0xFFC01F84 -#define MDMA1_D1_X_COUNT 0xFFC01F90 -#define MDMA1_D1_Y_COUNT 0xFFC01F98 -#define MDMA1_D1_X_MODIFY 0xFFC01F94 -#define MDMA1_D1_Y_MODIFY 0xFFC01F9C -#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 -#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 -#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 -#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 -#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 -#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC -#define MDMA2_S0_CONFIG 0xFFC00F48 -#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 -#define MDMA2_S0_START_ADDR 0xFFC00F44 -#define MDMA2_S0_X_COUNT 0xFFC00F50 -#define MDMA2_S0_Y_COUNT 0xFFC00F58 -#define MDMA2_S0_X_MODIFY 0xFFC00F54 -#define MDMA2_S0_Y_MODIFY 0xFFC00F5C -#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 -#define MDMA2_S0_CURR_ADDR 0xFFC00F64 -#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 -#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 -#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 -#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C -#define MDMA2_D0_CONFIG 0xFFC00F08 -#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 -#define MDMA2_D0_START_ADDR 0xFFC00F04 -#define MDMA2_D0_X_COUNT 0xFFC00F10 -#define MDMA2_D0_Y_COUNT 0xFFC00F18 -#define MDMA2_D0_X_MODIFY 0xFFC00F14 -#define MDMA2_D0_Y_MODIFY 0xFFC00F1C -#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 -#define MDMA2_D0_CURR_ADDR 0xFFC00F24 -#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 -#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 -#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 -#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C -#define MDMA2_S1_CONFIG 0xFFC00FC8 -#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 -#define MDMA2_S1_START_ADDR 0xFFC00FC4 -#define MDMA2_S1_X_COUNT 0xFFC00FD0 -#define MDMA2_S1_Y_COUNT 0xFFC00FD8 -#define MDMA2_S1_X_MODIFY 0xFFC00FD4 -#define MDMA2_S1_Y_MODIFY 0xFFC00FDC -#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 -#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 -#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 -#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 -#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 -#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC -#define MDMA2_D1_CONFIG 0xFFC00F88 -#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 -#define MDMA2_D1_START_ADDR 0xFFC00F84 -#define MDMA2_D1_X_COUNT 0xFFC00F90 -#define MDMA2_D1_Y_COUNT 0xFFC00F98 -#define MDMA2_D1_X_MODIFY 0xFFC00F94 -#define MDMA2_D1_Y_MODIFY 0xFFC00F9C -#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 -#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 -#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 -#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 -#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 -#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC -#define TIMER0_CONFIG 0xFFC00600 -#define TIMER0_COUNTER 0xFFC00604 -#define TIMER0_PERIOD 0xFFC00608 -#define TIMER0_WIDTH 0xFFC0060C -#define TIMER1_CONFIG 0xFFC00610 -#define TIMER1_COUNTER 0xFFC00614 -#define TIMER1_PERIOD 0xFFC00618 -#define TIMER1_WIDTH 0xFFC0061C -#define TIMER2_CONFIG 0xFFC00620 -#define TIMER2_COUNTER 0xFFC00624 -#define TIMER2_PERIOD 0xFFC00628 -#define TIMER2_WIDTH 0xFFC0062C -#define TIMER3_CONFIG 0xFFC00630 -#define TIMER3_COUNTER 0xFFC00634 -#define TIMER3_PERIOD 0xFFC00638 -#define TIMER3_WIDTH 0xFFC0063C -#define TIMER4_CONFIG 0xFFC00640 -#define TIMER4_COUNTER 0xFFC00644 -#define TIMER4_PERIOD 0xFFC00648 -#define TIMER4_WIDTH 0xFFC0064C -#define TIMER5_CONFIG 0xFFC00650 -#define TIMER5_COUNTER 0xFFC00654 -#define TIMER5_PERIOD 0xFFC00658 -#define TIMER5_WIDTH 0xFFC0065C -#define TIMER6_CONFIG 0xFFC00660 -#define TIMER6_COUNTER 0xFFC00664 -#define TIMER6_PERIOD 0xFFC00668 -#define TIMER6_WIDTH 0xFFC0066C -#define TIMER7_CONFIG 0xFFC00670 -#define TIMER7_COUNTER 0xFFC00674 -#define TIMER7_PERIOD 0xFFC00678 -#define TIMER7_WIDTH 0xFFC0067C -#define TIMER8_CONFIG 0xFFC01600 -#define TIMER8_COUNTER 0xFFC01604 -#define TIMER8_PERIOD 0xFFC01608 -#define TIMER8_WIDTH 0xFFC0160C -#define TIMER9_CONFIG 0xFFC01610 -#define TIMER9_COUNTER 0xFFC01614 -#define TIMER9_PERIOD 0xFFC01618 -#define TIMER9_WIDTH 0xFFC0161C -#define TIMER10_CONFIG 0xFFC01620 -#define TIMER10_COUNTER 0xFFC01624 -#define TIMER10_PERIOD 0xFFC01628 -#define TIMER10_WIDTH 0xFFC0162C -#define TIMER11_CONFIG 0xFFC01630 -#define TIMER11_COUNTER 0xFFC01634 -#define TIMER11_PERIOD 0xFFC01638 -#define TIMER11_WIDTH 0xFFC0163C -#define TMRS4_ENABLE 0xFFC01640 -#define TMRS4_DISABLE 0xFFC01644 -#define TMRS4_STATUS 0xFFC01648 -#define TMRS8_ENABLE 0xFFC00680 -#define TMRS8_DISABLE 0xFFC00684 -#define TMRS8_STATUS 0xFFC00688 -#define FIO0_FLAG_D 0xFFC00700 -#define FIO0_FLAG_C 0xFFC00704 -#define FIO0_FLAG_S 0xFFC00708 -#define FIO0_FLAG_T 0xFFC0070C -#define FIO0_MASKA_D 0xFFC00710 -#define FIO0_MASKA_C 0xFFC00714 -#define FIO0_MASKA_S 0xFFC00718 -#define FIO0_MASKA_T 0xFFC0071C -#define FIO0_MASKB_D 0xFFC00720 -#define FIO0_MASKB_C 0xFFC00724 -#define FIO0_MASKB_S 0xFFC00728 -#define FIO0_MASKB_T 0xFFC0072C -#define FIO0_DIR 0xFFC00730 -#define FIO0_POLAR 0xFFC00734 -#define FIO0_EDGE 0xFFC00738 -#define FIO0_BOTH 0xFFC0073C -#define FIO0_INEN 0xFFC00740 -#define FIO1_FLAG_D 0xFFC01500 -#define FIO1_FLAG_C 0xFFC01504 -#define FIO1_FLAG_S 0xFFC01508 -#define FIO1_FLAG_T 0xFFC0150C -#define FIO1_MASKA_D 0xFFC01510 -#define FIO1_MASKA_C 0xFFC01514 -#define FIO1_MASKA_S 0xFFC01518 -#define FIO1_MASKA_T 0xFFC0151C -#define FIO1_MASKB_D 0xFFC01520 -#define FIO1_MASKB_C 0xFFC01524 -#define FIO1_MASKB_S 0xFFC01528 -#define FIO1_MASKB_T 0xFFC0152C -#define FIO1_DIR 0xFFC01530 -#define FIO1_POLAR 0xFFC01534 -#define FIO1_EDGE 0xFFC01538 -#define FIO1_BOTH 0xFFC0153C -#define FIO1_INEN 0xFFC01540 -#define FIO2_FLAG_D 0xFFC01700 -#define FIO2_FLAG_C 0xFFC01704 -#define FIO2_FLAG_S 0xFFC01708 -#define FIO2_FLAG_T 0xFFC0170C -#define FIO2_MASKA_D 0xFFC01710 -#define FIO2_MASKA_C 0xFFC01714 -#define FIO2_MASKA_S 0xFFC01718 -#define FIO2_MASKA_T 0xFFC0171C -#define FIO2_MASKB_D 0xFFC01720 -#define FIO2_MASKB_C 0xFFC01724 -#define FIO2_MASKB_S 0xFFC01728 -#define FIO2_MASKB_T 0xFFC0172C -#define FIO2_DIR 0xFFC01730 -#define FIO2_POLAR 0xFFC01734 -#define FIO2_EDGE 0xFFC01738 -#define FIO2_BOTH 0xFFC0173C -#define FIO2_INEN 0xFFC01740 -#define SPORT0_TCR1 0xFFC00800 -#define SPORT0_TCR2 0xFFC00804 -#define SPORT0_TCLKDIV 0xFFC00808 -#define SPORT0_TFSDIV 0xFFC0080C -#define SPORT0_TX 0xFFC00810 -#define SPORT0_RX 0xFFC00818 -#define SPORT0_RCR1 0xFFC00820 -#define SPORT0_RCR2 0xFFC00824 -#define SPORT0_RCLKDIV 0xFFC00828 -#define SPORT0_RFSDIV 0xFFC0082C -#define SPORT0_STAT 0xFFC00830 -#define SPORT0_CHNL 0xFFC00834 -#define SPORT0_MCMC1 0xFFC00838 -#define SPORT0_MCMC2 0xFFC0083C -#define SPORT0_MTCS0 0xFFC00840 -#define SPORT0_MTCS1 0xFFC00844 -#define SPORT0_MTCS2 0xFFC00848 -#define SPORT0_MTCS3 0xFFC0084C -#define SPORT0_MRCS0 0xFFC00850 -#define SPORT0_MRCS1 0xFFC00854 -#define SPORT0_MRCS2 0xFFC00858 -#define SPORT0_MRCS3 0xFFC0085C -#define SPORT1_TCR1 0xFFC00900 -#define SPORT1_TCR2 0xFFC00904 -#define SPORT1_TCLKDIV 0xFFC00908 -#define SPORT1_TFSDIV 0xFFC0090C -#define SPORT1_TX 0xFFC00910 -#define SPORT1_RX 0xFFC00918 -#define SPORT1_RCR1 0xFFC00920 -#define SPORT1_RCR2 0xFFC00924 -#define SPORT1_RCLKDIV 0xFFC00928 -#define SPORT1_RFSDIV 0xFFC0092C -#define SPORT1_STAT 0xFFC00930 -#define SPORT1_CHNL 0xFFC00934 -#define SPORT1_MCMC1 0xFFC00938 -#define SPORT1_MCMC2 0xFFC0093C -#define SPORT1_MTCS0 0xFFC00940 -#define SPORT1_MTCS1 0xFFC00944 -#define SPORT1_MTCS2 0xFFC00948 -#define SPORT1_MTCS3 0xFFC0094C -#define SPORT1_MRCS0 0xFFC00950 -#define SPORT1_MRCS1 0xFFC00954 -#define SPORT1_MRCS2 0xFFC00958 -#define SPORT1_MRCS3 0xFFC0095C -#define EVT0 0xFFE02000 -#define EVT1 0xFFE02004 -#define EVT2 0xFFE02008 -#define EVT3 0xFFE0200C -#define EVT4 0xFFE02010 -#define EVT5 0xFFE02014 -#define EVT6 0xFFE02018 -#define EVT7 0xFFE0201C -#define EVT8 0xFFE02020 -#define EVT9 0xFFE02024 -#define EVT10 0xFFE02028 -#define EVT11 0xFFE0202C -#define EVT12 0xFFE02030 -#define EVT13 0xFFE02034 -#define EVT14 0xFFE02038 -#define EVT15 0xFFE0203C -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 -#define TPERIOD 0xFFE03004 -#define TSCALE 0xFFE03008 -#define TCOUNT 0xFFE0300C - -#endif /* __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ */ diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h deleted file mode 100644 index af17813..0000000 --- a/include/asm-blackfin/mach-common/ADSP-EDN-core_cdef.h +++ /dev/null @@ -1,73 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_core__ -#define __BFIN_CDEF_ADSP_EDN_core__ - -#define pWPIACTL ((uint32_t volatile *)WPIACTL) -#define bfin_read_WPIACTL() bfin_read32(WPIACTL) -#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL, val) -#define pWPIA0 ((void * volatile *)WPIA0) -#define bfin_read_WPIA0() bfin_readPTR(WPIA0) -#define bfin_write_WPIA0(val) bfin_writePTR(WPIA0, val) -#define pWPIA1 ((void * volatile *)WPIA1) -#define bfin_read_WPIA1() bfin_readPTR(WPIA1) -#define bfin_write_WPIA1(val) bfin_writePTR(WPIA1, val) -#define pWPIA2 ((void * volatile *)WPIA2) -#define bfin_read_WPIA2() bfin_readPTR(WPIA2) -#define bfin_write_WPIA2(val) bfin_writePTR(WPIA2, val) -#define pWPIA3 ((void * volatile *)WPIA3) -#define bfin_read_WPIA3() bfin_readPTR(WPIA3) -#define bfin_write_WPIA3(val) bfin_writePTR(WPIA3, val) -#define pWPIA4 ((void * volatile *)WPIA4) -#define bfin_read_WPIA4() bfin_readPTR(WPIA4) -#define bfin_write_WPIA4(val) bfin_writePTR(WPIA4, val) -#define pWPIA5 ((void * volatile *)WPIA5) -#define bfin_read_WPIA5() bfin_readPTR(WPIA5) -#define bfin_write_WPIA5(val) bfin_writePTR(WPIA5, val) -#define pWPIACNT0 ((uint32_t volatile *)WPIACNT0) -#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0) -#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0, val) -#define pWPIACNT1 ((uint32_t volatile *)WPIACNT1) -#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1) -#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1, val) -#define pWPIACNT2 ((uint32_t volatile *)WPIACNT2) -#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2) -#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2, val) -#define pWPIACNT3 ((uint32_t volatile *)WPIACNT3) -#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3) -#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3, val) -#define pWPIACNT4 ((uint32_t volatile *)WPIACNT4) -#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4) -#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4, val) -#define pWPIACNT5 ((uint32_t volatile *)WPIACNT5) -#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5) -#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5, val) -#define pWPDACTL ((uint32_t volatile *)WPDACTL) -#define bfin_read_WPDACTL() bfin_read32(WPDACTL) -#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL, val) -#define pWPDA0 ((void * volatile *)WPDA0) -#define bfin_read_WPDA0() bfin_readPTR(WPDA0) -#define bfin_write_WPDA0(val) bfin_writePTR(WPDA0, val) -#define pWPDA1 ((void * volatile *)WPDA1) -#define bfin_read_WPDA1() bfin_readPTR(WPDA1) -#define bfin_write_WPDA1(val) bfin_writePTR(WPDA1, val) -#define pWPDACNT0 ((uint32_t volatile *)WPDACNT0) -#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0) -#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0, val) -#define pWPDACNT1 ((uint32_t volatile *)WPDACNT1) -#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1) -#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1, val) -#define pWPSTAT ((uint32_t volatile *)WPSTAT) -#define bfin_read_WPSTAT() bfin_read32(WPSTAT) -#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) -#define pDBGSTAT ((uint32_t volatile *)DBGSTAT) -#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT) -#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_core__ */ diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h b/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h deleted file mode 100644 index 74f5d30..0000000 --- a/include/asm-blackfin/mach-common/ADSP-EDN-core_def.h +++ /dev/null @@ -1,31 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_core__ -#define __BFIN_DEF_ADSP_EDN_core__ - -#define WPIACTL 0xFFE07000 -#define WPIA0 0xFFE07040 -#define WPIA1 0xFFE07044 -#define WPIA2 0xFFE07048 -#define WPIA3 0xFFE0704C -#define WPIA4 0xFFE07050 -#define WPIA5 0xFFE07054 -#define WPIACNT0 0xFFE07080 -#define WPIACNT1 0xFFE07084 -#define WPIACNT2 0xFFE07088 -#define WPIACNT3 0xFFE0708C -#define WPIACNT4 0xFFE07090 -#define WPIACNT5 0xFFE07094 -#define WPDACTL 0xFFE07100 -#define WPDA0 0xFFE07140 -#define WPDA1 0xFFE07144 -#define WPDACNT0 0xFFE07180 -#define WPDACNT1 0xFFE07184 -#define WPSTAT 0xFFE07200 -#define DSPID 0xFFE05000 -#define DBGSTAT 0xFFE05008 - -#endif /* __BFIN_DEF_ADSP_EDN_core__ */ diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h deleted file mode 100644 index 2e61b5f..0000000 --- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h +++ /dev/null @@ -1,1607 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_extended__ -#define __BFIN_CDEF_ADSP_EDN_extended__ - -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_FAULT_STATUS ((uint32_t volatile *)DCPLB_FAULT_STATUS) /* L1 Data Memory Controller Register */ -#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS) -#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val) -#define pDCPLB_FAULT_ADDR ((uint32_t volatile *)DCPLB_FAULT_ADDR) -#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_FAULT_STATUS ((uint32_t volatile *)ICPLB_FAULT_STATUS) -#define bfin_read_ICPLB_FAULT_STATUS() bfin_read32(ICPLB_FAULT_STATUS) -#define bfin_write_ICPLB_FAULT_STATUS(val) bfin_write32(ICPLB_FAULT_STATUS, val) -#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR) -#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pMDMAFLX0_DMACNFG_D ((uint16_t volatile *)MDMAFLX0_DMACNFG_D) -#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D) -#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val) -#define pMDMAFLX0_XCOUNT_D ((uint16_t volatile *)MDMAFLX0_XCOUNT_D) -#define bfin_read_MDMAFLX0_XCOUNT_D() bfin_read16(MDMAFLX0_XCOUNT_D) -#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val) -#define pMDMAFLX0_XMODIFY_D ((uint16_t volatile *)MDMAFLX0_XMODIFY_D) -#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D) -#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val) -#define pMDMAFLX0_YCOUNT_D ((uint16_t volatile *)MDMAFLX0_YCOUNT_D) -#define bfin_read_MDMAFLX0_YCOUNT_D() bfin_read16(MDMAFLX0_YCOUNT_D) -#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val) -#define pMDMAFLX0_YMODIFY_D ((uint16_t volatile *)MDMAFLX0_YMODIFY_D) -#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D) -#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val) -#define pMDMAFLX0_IRQSTAT_D ((uint16_t volatile *)MDMAFLX0_IRQSTAT_D) -#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D) -#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val) -#define pMDMAFLX0_PMAP_D ((uint16_t volatile *)MDMAFLX0_PMAP_D) -#define bfin_read_MDMAFLX0_PMAP_D() bfin_read16(MDMAFLX0_PMAP_D) -#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val) -#define pMDMAFLX0_CURXCOUNT_D ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_D) -#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D) -#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val) -#define pMDMAFLX0_CURYCOUNT_D ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_D) -#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D) -#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val) -#define pMDMAFLX0_DMACNFG_S ((uint16_t volatile *)MDMAFLX0_DMACNFG_S) -#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S) -#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val) -#define pMDMAFLX0_XCOUNT_S ((uint16_t volatile *)MDMAFLX0_XCOUNT_S) -#define bfin_read_MDMAFLX0_XCOUNT_S() bfin_read16(MDMAFLX0_XCOUNT_S) -#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val) -#define pMDMAFLX0_XMODIFY_S ((uint16_t volatile *)MDMAFLX0_XMODIFY_S) -#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S) -#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val) -#define pMDMAFLX0_YCOUNT_S ((uint16_t volatile *)MDMAFLX0_YCOUNT_S) -#define bfin_read_MDMAFLX0_YCOUNT_S() bfin_read16(MDMAFLX0_YCOUNT_S) -#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val) -#define pMDMAFLX0_YMODIFY_S ((uint16_t volatile *)MDMAFLX0_YMODIFY_S) -#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S) -#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val) -#define pMDMAFLX0_IRQSTAT_S ((uint16_t volatile *)MDMAFLX0_IRQSTAT_S) -#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S) -#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val) -#define pMDMAFLX0_PMAP_S ((uint16_t volatile *)MDMAFLX0_PMAP_S) -#define bfin_read_MDMAFLX0_PMAP_S() bfin_read16(MDMAFLX0_PMAP_S) -#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val) -#define pMDMAFLX0_CURXCOUNT_S ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_S) -#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S) -#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val) -#define pMDMAFLX0_CURYCOUNT_S ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_S) -#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S) -#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val) -#define pMDMAFLX1_DMACNFG_D ((uint16_t volatile *)MDMAFLX1_DMACNFG_D) -#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D) -#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val) -#define pMDMAFLX1_XCOUNT_D ((uint16_t volatile *)MDMAFLX1_XCOUNT_D) -#define bfin_read_MDMAFLX1_XCOUNT_D() bfin_read16(MDMAFLX1_XCOUNT_D) -#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val) -#define pMDMAFLX1_XMODIFY_D ((uint16_t volatile *)MDMAFLX1_XMODIFY_D) -#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D) -#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val) -#define pMDMAFLX1_YCOUNT_D ((uint16_t volatile *)MDMAFLX1_YCOUNT_D) -#define bfin_read_MDMAFLX1_YCOUNT_D() bfin_read16(MDMAFLX1_YCOUNT_D) -#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val) -#define pMDMAFLX1_YMODIFY_D ((uint16_t volatile *)MDMAFLX1_YMODIFY_D) -#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D) -#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val) -#define pMDMAFLX1_IRQSTAT_D ((uint16_t volatile *)MDMAFLX1_IRQSTAT_D) -#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D) -#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val) -#define pMDMAFLX1_PMAP_D ((uint16_t volatile *)MDMAFLX1_PMAP_D) -#define bfin_read_MDMAFLX1_PMAP_D() bfin_read16(MDMAFLX1_PMAP_D) -#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val) -#define pMDMAFLX1_CURXCOUNT_D ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_D) -#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D) -#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val) -#define pMDMAFLX1_CURYCOUNT_D ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_D) -#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D) -#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val) -#define pMDMAFLX1_DMACNFG_S ((uint16_t volatile *)MDMAFLX1_DMACNFG_S) -#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S) -#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val) -#define pMDMAFLX1_XCOUNT_S ((uint16_t volatile *)MDMAFLX1_XCOUNT_S) -#define bfin_read_MDMAFLX1_XCOUNT_S() bfin_read16(MDMAFLX1_XCOUNT_S) -#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val) -#define pMDMAFLX1_XMODIFY_S ((uint16_t volatile *)MDMAFLX1_XMODIFY_S) -#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S) -#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val) -#define pMDMAFLX1_YCOUNT_S ((uint16_t volatile *)MDMAFLX1_YCOUNT_S) -#define bfin_read_MDMAFLX1_YCOUNT_S() bfin_read16(MDMAFLX1_YCOUNT_S) -#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val) -#define pMDMAFLX1_YMODIFY_S ((uint16_t volatile *)MDMAFLX1_YMODIFY_S) -#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S) -#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val) -#define pMDMAFLX1_IRQSTAT_S ((uint16_t volatile *)MDMAFLX1_IRQSTAT_S) -#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S) -#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val) -#define pMDMAFLX1_PMAP_S ((uint16_t volatile *)MDMAFLX1_PMAP_S) -#define bfin_read_MDMAFLX1_PMAP_S() bfin_read16(MDMAFLX1_PMAP_S) -#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val) -#define pMDMAFLX1_CURXCOUNT_S ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_S) -#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S) -#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val) -#define pMDMAFLX1_CURYCOUNT_S ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_S) -#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S) -#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val) -#define pDMAFLX0_DMACNFG ((uint16_t volatile *)DMAFLX0_DMACNFG) -#define bfin_read_DMAFLX0_DMACNFG() bfin_read16(DMAFLX0_DMACNFG) -#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val) -#define pDMAFLX0_XCOUNT ((uint16_t volatile *)DMAFLX0_XCOUNT) -#define bfin_read_DMAFLX0_XCOUNT() bfin_read16(DMAFLX0_XCOUNT) -#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val) -#define pDMAFLX0_XMODIFY ((uint16_t volatile *)DMAFLX0_XMODIFY) -#define bfin_read_DMAFLX0_XMODIFY() bfin_read16(DMAFLX0_XMODIFY) -#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val) -#define pDMAFLX0_YCOUNT ((uint16_t volatile *)DMAFLX0_YCOUNT) -#define bfin_read_DMAFLX0_YCOUNT() bfin_read16(DMAFLX0_YCOUNT) -#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val) -#define pDMAFLX0_YMODIFY ((uint16_t volatile *)DMAFLX0_YMODIFY) -#define bfin_read_DMAFLX0_YMODIFY() bfin_read16(DMAFLX0_YMODIFY) -#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val) -#define pDMAFLX0_IRQSTAT ((uint16_t volatile *)DMAFLX0_IRQSTAT) -#define bfin_read_DMAFLX0_IRQSTAT() bfin_read16(DMAFLX0_IRQSTAT) -#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val) -#define pDMAFLX0_PMAP ((uint16_t volatile *)DMAFLX0_PMAP) -#define bfin_read_DMAFLX0_PMAP() bfin_read16(DMAFLX0_PMAP) -#define bfin_write_DMAFLX0_PMAP(val) bfin_write16(DMAFLX0_PMAP, val) -#define pDMAFLX0_CURXCOUNT ((uint16_t volatile *)DMAFLX0_CURXCOUNT) -#define bfin_read_DMAFLX0_CURXCOUNT() bfin_read16(DMAFLX0_CURXCOUNT) -#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val) -#define pDMAFLX0_CURYCOUNT ((uint16_t volatile *)DMAFLX0_CURYCOUNT) -#define bfin_read_DMAFLX0_CURYCOUNT() bfin_read16(DMAFLX0_CURYCOUNT) -#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val) -#define pDMAFLX1_DMACNFG ((uint16_t volatile *)DMAFLX1_DMACNFG) -#define bfin_read_DMAFLX1_DMACNFG() bfin_read16(DMAFLX1_DMACNFG) -#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val) -#define pDMAFLX1_XCOUNT ((uint16_t volatile *)DMAFLX1_XCOUNT) -#define bfin_read_DMAFLX1_XCOUNT() bfin_read16(DMAFLX1_XCOUNT) -#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val) -#define pDMAFLX1_XMODIFY ((uint16_t volatile *)DMAFLX1_XMODIFY) -#define bfin_read_DMAFLX1_XMODIFY() bfin_read16(DMAFLX1_XMODIFY) -#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val) -#define pDMAFLX1_YCOUNT ((uint16_t volatile *)DMAFLX1_YCOUNT) -#define bfin_read_DMAFLX1_YCOUNT() bfin_read16(DMAFLX1_YCOUNT) -#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val) -#define pDMAFLX1_YMODIFY ((uint16_t volatile *)DMAFLX1_YMODIFY) -#define bfin_read_DMAFLX1_YMODIFY() bfin_read16(DMAFLX1_YMODIFY) -#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val) -#define pDMAFLX1_IRQSTAT ((uint16_t volatile *)DMAFLX1_IRQSTAT) -#define bfin_read_DMAFLX1_IRQSTAT() bfin_read16(DMAFLX1_IRQSTAT) -#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val) -#define pDMAFLX1_PMAP ((uint16_t volatile *)DMAFLX1_PMAP) -#define bfin_read_DMAFLX1_PMAP() bfin_read16(DMAFLX1_PMAP) -#define bfin_write_DMAFLX1_PMAP(val) bfin_write16(DMAFLX1_PMAP, val) -#define pDMAFLX1_CURXCOUNT ((uint16_t volatile *)DMAFLX1_CURXCOUNT) -#define bfin_read_DMAFLX1_CURXCOUNT() bfin_read16(DMAFLX1_CURXCOUNT) -#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val) -#define pDMAFLX1_CURYCOUNT ((uint16_t volatile *)DMAFLX1_CURYCOUNT) -#define bfin_read_DMAFLX1_CURYCOUNT() bfin_read16(DMAFLX1_CURYCOUNT) -#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val) -#define pDMAFLX2_DMACNFG ((uint16_t volatile *)DMAFLX2_DMACNFG) -#define bfin_read_DMAFLX2_DMACNFG() bfin_read16(DMAFLX2_DMACNFG) -#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val) -#define pDMAFLX2_XCOUNT ((uint16_t volatile *)DMAFLX2_XCOUNT) -#define bfin_read_DMAFLX2_XCOUNT() bfin_read16(DMAFLX2_XCOUNT) -#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val) -#define pDMAFLX2_XMODIFY ((uint16_t volatile *)DMAFLX2_XMODIFY) -#define bfin_read_DMAFLX2_XMODIFY() bfin_read16(DMAFLX2_XMODIFY) -#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val) -#define pDMAFLX2_YCOUNT ((uint16_t volatile *)DMAFLX2_YCOUNT) -#define bfin_read_DMAFLX2_YCOUNT() bfin_read16(DMAFLX2_YCOUNT) -#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val) -#define pDMAFLX2_YMODIFY ((uint16_t volatile *)DMAFLX2_YMODIFY) -#define bfin_read_DMAFLX2_YMODIFY() bfin_read16(DMAFLX2_YMODIFY) -#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val) -#define pDMAFLX2_IRQSTAT ((uint16_t volatile *)DMAFLX2_IRQSTAT) -#define bfin_read_DMAFLX2_IRQSTAT() bfin_read16(DMAFLX2_IRQSTAT) -#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val) -#define pDMAFLX2_PMAP ((uint16_t volatile *)DMAFLX2_PMAP) -#define bfin_read_DMAFLX2_PMAP() bfin_read16(DMAFLX2_PMAP) -#define bfin_write_DMAFLX2_PMAP(val) bfin_write16(DMAFLX2_PMAP, val) -#define pDMAFLX2_CURXCOUNT ((uint16_t volatile *)DMAFLX2_CURXCOUNT) -#define bfin_read_DMAFLX2_CURXCOUNT() bfin_read16(DMAFLX2_CURXCOUNT) -#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val) -#define pDMAFLX2_CURYCOUNT ((uint16_t volatile *)DMAFLX2_CURYCOUNT) -#define bfin_read_DMAFLX2_CURYCOUNT() bfin_read16(DMAFLX2_CURYCOUNT) -#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val) -#define pDMAFLX3_DMACNFG ((uint16_t volatile *)DMAFLX3_DMACNFG) -#define bfin_read_DMAFLX3_DMACNFG() bfin_read16(DMAFLX3_DMACNFG) -#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val) -#define pDMAFLX3_XCOUNT ((uint16_t volatile *)DMAFLX3_XCOUNT) -#define bfin_read_DMAFLX3_XCOUNT() bfin_read16(DMAFLX3_XCOUNT) -#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val) -#define pDMAFLX3_XMODIFY ((uint16_t volatile *)DMAFLX3_XMODIFY) -#define bfin_read_DMAFLX3_XMODIFY() bfin_read16(DMAFLX3_XMODIFY) -#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val) -#define pDMAFLX3_YCOUNT ((uint16_t volatile *)DMAFLX3_YCOUNT) -#define bfin_read_DMAFLX3_YCOUNT() bfin_read16(DMAFLX3_YCOUNT) -#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val) -#define pDMAFLX3_YMODIFY ((uint16_t volatile *)DMAFLX3_YMODIFY) -#define bfin_read_DMAFLX3_YMODIFY() bfin_read16(DMAFLX3_YMODIFY) -#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val) -#define pDMAFLX3_IRQSTAT ((uint16_t volatile *)DMAFLX3_IRQSTAT) -#define bfin_read_DMAFLX3_IRQSTAT() bfin_read16(DMAFLX3_IRQSTAT) -#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val) -#define pDMAFLX3_PMAP ((uint16_t volatile *)DMAFLX3_PMAP) -#define bfin_read_DMAFLX3_PMAP() bfin_read16(DMAFLX3_PMAP) -#define bfin_write_DMAFLX3_PMAP(val) bfin_write16(DMAFLX3_PMAP, val) -#define pDMAFLX3_CURXCOUNT ((uint16_t volatile *)DMAFLX3_CURXCOUNT) -#define bfin_read_DMAFLX3_CURXCOUNT() bfin_read16(DMAFLX3_CURXCOUNT) -#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val) -#define pDMAFLX3_CURYCOUNT ((uint16_t volatile *)DMAFLX3_CURYCOUNT) -#define bfin_read_DMAFLX3_CURYCOUNT() bfin_read16(DMAFLX3_CURYCOUNT) -#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val) -#define pDMAFLX4_DMACNFG ((uint16_t volatile *)DMAFLX4_DMACNFG) -#define bfin_read_DMAFLX4_DMACNFG() bfin_read16(DMAFLX4_DMACNFG) -#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val) -#define pDMAFLX4_XCOUNT ((uint16_t volatile *)DMAFLX4_XCOUNT) -#define bfin_read_DMAFLX4_XCOUNT() bfin_read16(DMAFLX4_XCOUNT) -#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val) -#define pDMAFLX4_XMODIFY ((uint16_t volatile *)DMAFLX4_XMODIFY) -#define bfin_read_DMAFLX4_XMODIFY() bfin_read16(DMAFLX4_XMODIFY) -#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val) -#define pDMAFLX4_YCOUNT ((uint16_t volatile *)DMAFLX4_YCOUNT) -#define bfin_read_DMAFLX4_YCOUNT() bfin_read16(DMAFLX4_YCOUNT) -#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val) -#define pDMAFLX4_YMODIFY ((uint16_t volatile *)DMAFLX4_YMODIFY) -#define bfin_read_DMAFLX4_YMODIFY() bfin_read16(DMAFLX4_YMODIFY) -#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val) -#define pDMAFLX4_IRQSTAT ((uint16_t volatile *)DMAFLX4_IRQSTAT) -#define bfin_read_DMAFLX4_IRQSTAT() bfin_read16(DMAFLX4_IRQSTAT) -#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val) -#define pDMAFLX4_PMAP ((uint16_t volatile *)DMAFLX4_PMAP) -#define bfin_read_DMAFLX4_PMAP() bfin_read16(DMAFLX4_PMAP) -#define bfin_write_DMAFLX4_PMAP(val) bfin_write16(DMAFLX4_PMAP, val) -#define pDMAFLX4_CURXCOUNT ((uint16_t volatile *)DMAFLX4_CURXCOUNT) -#define bfin_read_DMAFLX4_CURXCOUNT() bfin_read16(DMAFLX4_CURXCOUNT) -#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val) -#define pDMAFLX4_CURYCOUNT ((uint16_t volatile *)DMAFLX4_CURYCOUNT) -#define bfin_read_DMAFLX4_CURYCOUNT() bfin_read16(DMAFLX4_CURYCOUNT) -#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val) -#define pDMAFLX5_DMACNFG ((uint16_t volatile *)DMAFLX5_DMACNFG) -#define bfin_read_DMAFLX5_DMACNFG() bfin_read16(DMAFLX5_DMACNFG) -#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val) -#define pDMAFLX5_XCOUNT ((uint16_t volatile *)DMAFLX5_XCOUNT) -#define bfin_read_DMAFLX5_XCOUNT() bfin_read16(DMAFLX5_XCOUNT) -#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val) -#define pDMAFLX5_XMODIFY ((uint16_t volatile *)DMAFLX5_XMODIFY) -#define bfin_read_DMAFLX5_XMODIFY() bfin_read16(DMAFLX5_XMODIFY) -#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val) -#define pDMAFLX5_YCOUNT ((uint16_t volatile *)DMAFLX5_YCOUNT) -#define bfin_read_DMAFLX5_YCOUNT() bfin_read16(DMAFLX5_YCOUNT) -#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val) -#define pDMAFLX5_YMODIFY ((uint16_t volatile *)DMAFLX5_YMODIFY) -#define bfin_read_DMAFLX5_YMODIFY() bfin_read16(DMAFLX5_YMODIFY) -#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val) -#define pDMAFLX5_IRQSTAT ((uint16_t volatile *)DMAFLX5_IRQSTAT) -#define bfin_read_DMAFLX5_IRQSTAT() bfin_read16(DMAFLX5_IRQSTAT) -#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val) -#define pDMAFLX5_PMAP ((uint16_t volatile *)DMAFLX5_PMAP) -#define bfin_read_DMAFLX5_PMAP() bfin_read16(DMAFLX5_PMAP) -#define bfin_write_DMAFLX5_PMAP(val) bfin_write16(DMAFLX5_PMAP, val) -#define pDMAFLX5_CURXCOUNT ((uint16_t volatile *)DMAFLX5_CURXCOUNT) -#define bfin_read_DMAFLX5_CURXCOUNT() bfin_read16(DMAFLX5_CURXCOUNT) -#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val) -#define pDMAFLX5_CURYCOUNT ((uint16_t volatile *)DMAFLX5_CURYCOUNT) -#define bfin_read_DMAFLX5_CURYCOUNT() bfin_read16(DMAFLX5_CURYCOUNT) -#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val) -#define pDMAFLX6_DMACNFG ((uint16_t volatile *)DMAFLX6_DMACNFG) -#define bfin_read_DMAFLX6_DMACNFG() bfin_read16(DMAFLX6_DMACNFG) -#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val) -#define pDMAFLX6_XCOUNT ((uint16_t volatile *)DMAFLX6_XCOUNT) -#define bfin_read_DMAFLX6_XCOUNT() bfin_read16(DMAFLX6_XCOUNT) -#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val) -#define pDMAFLX6_XMODIFY ((uint16_t volatile *)DMAFLX6_XMODIFY) -#define bfin_read_DMAFLX6_XMODIFY() bfin_read16(DMAFLX6_XMODIFY) -#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val) -#define pDMAFLX6_YCOUNT ((uint16_t volatile *)DMAFLX6_YCOUNT) -#define bfin_read_DMAFLX6_YCOUNT() bfin_read16(DMAFLX6_YCOUNT) -#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val) -#define pDMAFLX6_YMODIFY ((uint16_t volatile *)DMAFLX6_YMODIFY) -#define bfin_read_DMAFLX6_YMODIFY() bfin_read16(DMAFLX6_YMODIFY) -#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val) -#define pDMAFLX6_IRQSTAT ((uint16_t volatile *)DMAFLX6_IRQSTAT) -#define bfin_read_DMAFLX6_IRQSTAT() bfin_read16(DMAFLX6_IRQSTAT) -#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val) -#define pDMAFLX6_PMAP ((uint16_t volatile *)DMAFLX6_PMAP) -#define bfin_read_DMAFLX6_PMAP() bfin_read16(DMAFLX6_PMAP) -#define bfin_write_DMAFLX6_PMAP(val) bfin_write16(DMAFLX6_PMAP, val) -#define pDMAFLX6_CURXCOUNT ((uint16_t volatile *)DMAFLX6_CURXCOUNT) -#define bfin_read_DMAFLX6_CURXCOUNT() bfin_read16(DMAFLX6_CURXCOUNT) -#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val) -#define pDMAFLX6_CURYCOUNT ((uint16_t volatile *)DMAFLX6_CURYCOUNT) -#define bfin_read_DMAFLX6_CURYCOUNT() bfin_read16(DMAFLX6_CURYCOUNT) -#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val) -#define pDMAFLX7_DMACNFG ((uint16_t volatile *)DMAFLX7_DMACNFG) -#define bfin_read_DMAFLX7_DMACNFG() bfin_read16(DMAFLX7_DMACNFG) -#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val) -#define pDMAFLX7_XCOUNT ((uint16_t volatile *)DMAFLX7_XCOUNT) -#define bfin_read_DMAFLX7_XCOUNT() bfin_read16(DMAFLX7_XCOUNT) -#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val) -#define pDMAFLX7_XMODIFY ((uint16_t volatile *)DMAFLX7_XMODIFY) -#define bfin_read_DMAFLX7_XMODIFY() bfin_read16(DMAFLX7_XMODIFY) -#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val) -#define pDMAFLX7_YCOUNT ((uint16_t volatile *)DMAFLX7_YCOUNT) -#define bfin_read_DMAFLX7_YCOUNT() bfin_read16(DMAFLX7_YCOUNT) -#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val) -#define pDMAFLX7_YMODIFY ((uint16_t volatile *)DMAFLX7_YMODIFY) -#define bfin_read_DMAFLX7_YMODIFY() bfin_read16(DMAFLX7_YMODIFY) -#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val) -#define pDMAFLX7_IRQSTAT ((uint16_t volatile *)DMAFLX7_IRQSTAT) -#define bfin_read_DMAFLX7_IRQSTAT() bfin_read16(DMAFLX7_IRQSTAT) -#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val) -#define pDMAFLX7_PMAP ((uint16_t volatile *)DMAFLX7_PMAP) -#define bfin_read_DMAFLX7_PMAP() bfin_read16(DMAFLX7_PMAP) -#define bfin_write_DMAFLX7_PMAP(val) bfin_write16(DMAFLX7_PMAP, val) -#define pDMAFLX7_CURXCOUNT ((uint16_t volatile *)DMAFLX7_CURXCOUNT) -#define bfin_read_DMAFLX7_CURXCOUNT() bfin_read16(DMAFLX7_CURXCOUNT) -#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val) -#define pDMAFLX7_CURYCOUNT ((uint16_t volatile *)DMAFLX7_CURYCOUNT) -#define bfin_read_DMAFLX7_CURYCOUNT() bfin_read16(DMAFLX7_CURYCOUNT) -#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE) -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define pTIMER_STATUS ((uint16_t volatile *)TIMER_STATUS) -#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val) -#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ -#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) -#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */ -#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) -#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */ -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */ -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */ -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */ -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_ISR ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */ -#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) -#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) -#define pSIC_IWR ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */ -#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) -#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) -#define pUART_THR ((uint16_t volatile *)UART_THR) /* Transmit Holding */ -#define bfin_read_UART_THR() bfin_read16(UART_THR) -#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val) -#define pUART_DLL ((uint16_t volatile *)UART_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART_DLL() bfin_read16(UART_DLL) -#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val) -#define pUART_DLH ((uint16_t volatile *)UART_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART_DLH() bfin_read16(UART_DLH) -#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val) -#define pUART_IER ((uint16_t volatile *)UART_IER) -#define bfin_read_UART_IER() bfin_read16(UART_IER) -#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val) -#define pUART_IIR ((uint16_t volatile *)UART_IIR) -#define bfin_read_UART_IIR() bfin_read16(UART_IIR) -#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val) -#define pUART_LCR ((uint16_t volatile *)UART_LCR) -#define bfin_read_UART_LCR() bfin_read16(UART_LCR) -#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val) -#define pUART_MCR ((uint16_t volatile *)UART_MCR) -#define bfin_read_UART_MCR() bfin_read16(UART_MCR) -#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val) -#define pUART_LSR ((uint16_t volatile *)UART_LSR) -#define bfin_read_UART_LSR() bfin_read16(UART_LSR) -#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val) -#define pUART_SCR ((uint16_t volatile *)UART_SCR) -#define bfin_read_UART_SCR() bfin_read16(UART_SCR) -#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val) -#define pUART_RBR ((uint16_t volatile *)UART_RBR) /* Receive Buffer */ -#define bfin_read_UART_RBR() bfin_read16(UART_RBR) -#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val) -#define pUART_GCTL ((uint16_t volatile *)UART_GCTL) -#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) -#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val) -#define pSPT0_TX_CONFIG0 ((uint16_t volatile *)SPT0_TX_CONFIG0) -#define bfin_read_SPT0_TX_CONFIG0() bfin_read16(SPT0_TX_CONFIG0) -#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val) -#define pSPT0_TX_CONFIG1 ((uint16_t volatile *)SPT0_TX_CONFIG1) -#define bfin_read_SPT0_TX_CONFIG1() bfin_read16(SPT0_TX_CONFIG1) -#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val) -#define pSPT0_RX_CONFIG0 ((uint16_t volatile *)SPT0_RX_CONFIG0) -#define bfin_read_SPT0_RX_CONFIG0() bfin_read16(SPT0_RX_CONFIG0) -#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val) -#define pSPT0_RX_CONFIG1 ((uint16_t volatile *)SPT0_RX_CONFIG1) -#define bfin_read_SPT0_RX_CONFIG1() bfin_read16(SPT0_RX_CONFIG1) -#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val) -#define pSPT0_TX ((uint32_t volatile *)SPT0_TX) -#define bfin_read_SPT0_TX() bfin_read32(SPT0_TX) -#define bfin_write_SPT0_TX(val) bfin_write32(SPT0_TX, val) -#define pSPT0_RX ((uint32_t volatile *)SPT0_RX) -#define bfin_read_SPT0_RX() bfin_read32(SPT0_RX) -#define bfin_write_SPT0_RX(val) bfin_write32(SPT0_RX, val) -#define pSPT0_TSCLKDIV ((uint16_t volatile *)SPT0_TSCLKDIV) -#define bfin_read_SPT0_TSCLKDIV() bfin_read16(SPT0_TSCLKDIV) -#define bfin_write_SPT0_TSCLKDIV(val) bfin_write16(SPT0_TSCLKDIV, val) -#define pSPT0_RSCLKDIV ((uint16_t volatile *)SPT0_RSCLKDIV) -#define bfin_read_SPT0_RSCLKDIV() bfin_read16(SPT0_RSCLKDIV) -#define bfin_write_SPT0_RSCLKDIV(val) bfin_write16(SPT0_RSCLKDIV, val) -#define pSPT0_TFSDIV ((uint16_t volatile *)SPT0_TFSDIV) -#define bfin_read_SPT0_TFSDIV() bfin_read16(SPT0_TFSDIV) -#define bfin_write_SPT0_TFSDIV(val) bfin_write16(SPT0_TFSDIV, val) -#define pSPT0_RFSDIV ((uint16_t volatile *)SPT0_RFSDIV) -#define bfin_read_SPT0_RFSDIV() bfin_read16(SPT0_RFSDIV) -#define bfin_write_SPT0_RFSDIV(val) bfin_write16(SPT0_RFSDIV, val) -#define pSPT0_STAT ((uint16_t volatile *)SPT0_STAT) -#define bfin_read_SPT0_STAT() bfin_read16(SPT0_STAT) -#define bfin_write_SPT0_STAT(val) bfin_write16(SPT0_STAT, val) -#define pSPT0_MTCS0 ((uint32_t volatile *)SPT0_MTCS0) -#define bfin_read_SPT0_MTCS0() bfin_read32(SPT0_MTCS0) -#define bfin_write_SPT0_MTCS0(val) bfin_write32(SPT0_MTCS0, val) -#define pSPT0_MTCS1 ((uint32_t volatile *)SPT0_MTCS1) -#define bfin_read_SPT0_MTCS1() bfin_read32(SPT0_MTCS1) -#define bfin_write_SPT0_MTCS1(val) bfin_write32(SPT0_MTCS1, val) -#define pSPT0_MTCS2 ((uint32_t volatile *)SPT0_MTCS2) -#define bfin_read_SPT0_MTCS2() bfin_read32(SPT0_MTCS2) -#define bfin_write_SPT0_MTCS2(val) bfin_write32(SPT0_MTCS2, val) -#define pSPT0_MTCS3 ((uint32_t volatile *)SPT0_MTCS3) -#define bfin_read_SPT0_MTCS3() bfin_read32(SPT0_MTCS3) -#define bfin_write_SPT0_MTCS3(val) bfin_write32(SPT0_MTCS3, val) -#define pSPT0_MRCS0 ((uint32_t volatile *)SPT0_MRCS0) -#define bfin_read_SPT0_MRCS0() bfin_read32(SPT0_MRCS0) -#define bfin_write_SPT0_MRCS0(val) bfin_write32(SPT0_MRCS0, val) -#define pSPT0_MRCS1 ((uint32_t volatile *)SPT0_MRCS1) -#define bfin_read_SPT0_MRCS1() bfin_read32(SPT0_MRCS1) -#define bfin_write_SPT0_MRCS1(val) bfin_write32(SPT0_MRCS1, val) -#define pSPT0_MRCS2 ((uint32_t volatile *)SPT0_MRCS2) -#define bfin_read_SPT0_MRCS2() bfin_read32(SPT0_MRCS2) -#define bfin_write_SPT0_MRCS2(val) bfin_write32(SPT0_MRCS2, val) -#define pSPT0_MRCS3 ((uint32_t volatile *)SPT0_MRCS3) -#define bfin_read_SPT0_MRCS3() bfin_read32(SPT0_MRCS3) -#define bfin_write_SPT0_MRCS3(val) bfin_write32(SPT0_MRCS3, val) -#define pSPT0_MCMC1 ((uint16_t volatile *)SPT0_MCMC1) -#define bfin_read_SPT0_MCMC1() bfin_read16(SPT0_MCMC1) -#define bfin_write_SPT0_MCMC1(val) bfin_write16(SPT0_MCMC1, val) -#define pSPT0_MCMC2 ((uint16_t volatile *)SPT0_MCMC2) -#define bfin_read_SPT0_MCMC2() bfin_read16(SPT0_MCMC2) -#define bfin_write_SPT0_MCMC2(val) bfin_write16(SPT0_MCMC2, val) -#define pSPT0_CHNL ((uint16_t volatile *)SPT0_CHNL) -#define bfin_read_SPT0_CHNL() bfin_read16(SPT0_CHNL) -#define bfin_write_SPT0_CHNL(val) bfin_write16(SPT0_CHNL, val) -#define pSPT1_TX_CONFIG0 ((uint16_t volatile *)SPT1_TX_CONFIG0) -#define bfin_read_SPT1_TX_CONFIG0() bfin_read16(SPT1_TX_CONFIG0) -#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val) -#define pSPT1_TX_CONFIG1 ((uint16_t volatile *)SPT1_TX_CONFIG1) -#define bfin_read_SPT1_TX_CONFIG1() bfin_read16(SPT1_TX_CONFIG1) -#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val) -#define pSPT1_RX_CONFIG0 ((uint16_t volatile *)SPT1_RX_CONFIG0) -#define bfin_read_SPT1_RX_CONFIG0() bfin_read16(SPT1_RX_CONFIG0) -#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val) -#define pSPT1_RX_CONFIG1 ((uint16_t volatile *)SPT1_RX_CONFIG1) -#define bfin_read_SPT1_RX_CONFIG1() bfin_read16(SPT1_RX_CONFIG1) -#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val) -#define pSPT1_TX ((uint16_t volatile *)SPT1_TX) -#define bfin_read_SPT1_TX() bfin_read16(SPT1_TX) -#define bfin_write_SPT1_TX(val) bfin_write16(SPT1_TX, val) -#define pSPT1_RX ((uint16_t volatile *)SPT1_RX) -#define bfin_read_SPT1_RX() bfin_read16(SPT1_RX) -#define bfin_write_SPT1_RX(val) bfin_write16(SPT1_RX, val) -#define pSPT1_TSCLKDIV ((uint16_t volatile *)SPT1_TSCLKDIV) -#define bfin_read_SPT1_TSCLKDIV() bfin_read16(SPT1_TSCLKDIV) -#define bfin_write_SPT1_TSCLKDIV(val) bfin_write16(SPT1_TSCLKDIV, val) -#define pSPT1_RSCLKDIV ((uint16_t volatile *)SPT1_RSCLKDIV) -#define bfin_read_SPT1_RSCLKDIV() bfin_read16(SPT1_RSCLKDIV) -#define bfin_write_SPT1_RSCLKDIV(val) bfin_write16(SPT1_RSCLKDIV, val) -#define pSPT1_TFSDIV ((uint16_t volatile *)SPT1_TFSDIV) -#define bfin_read_SPT1_TFSDIV() bfin_read16(SPT1_TFSDIV) -#define bfin_write_SPT1_TFSDIV(val) bfin_write16(SPT1_TFSDIV, val) -#define pSPT1_RFSDIV ((uint16_t volatile *)SPT1_RFSDIV) -#define bfin_read_SPT1_RFSDIV() bfin_read16(SPT1_RFSDIV) -#define bfin_write_SPT1_RFSDIV(val) bfin_write16(SPT1_RFSDIV, val) -#define pSPT1_STAT ((uint16_t volatile *)SPT1_STAT) -#define bfin_read_SPT1_STAT() bfin_read16(SPT1_STAT) -#define bfin_write_SPT1_STAT(val) bfin_write16(SPT1_STAT, val) -#define pSPT1_MTCS0 ((uint32_t volatile *)SPT1_MTCS0) -#define bfin_read_SPT1_MTCS0() bfin_read32(SPT1_MTCS0) -#define bfin_write_SPT1_MTCS0(val) bfin_write32(SPT1_MTCS0, val) -#define pSPT1_MTCS1 ((uint32_t volatile *)SPT1_MTCS1) -#define bfin_read_SPT1_MTCS1() bfin_read32(SPT1_MTCS1) -#define bfin_write_SPT1_MTCS1(val) bfin_write32(SPT1_MTCS1, val) -#define pSPT1_MTCS2 ((uint32_t volatile *)SPT1_MTCS2) -#define bfin_read_SPT1_MTCS2() bfin_read32(SPT1_MTCS2) -#define bfin_write_SPT1_MTCS2(val) bfin_write32(SPT1_MTCS2, val) -#define pSPT1_MTCS3 ((uint32_t volatile *)SPT1_MTCS3) -#define bfin_read_SPT1_MTCS3() bfin_read32(SPT1_MTCS3) -#define bfin_write_SPT1_MTCS3(val) bfin_write32(SPT1_MTCS3, val) -#define pSPT1_MRCS0 ((uint32_t volatile *)SPT1_MRCS0) -#define bfin_read_SPT1_MRCS0() bfin_read32(SPT1_MRCS0) -#define bfin_write_SPT1_MRCS0(val) bfin_write32(SPT1_MRCS0, val) -#define pSPT1_MRCS1 ((uint32_t volatile *)SPT1_MRCS1) -#define bfin_read_SPT1_MRCS1() bfin_read32(SPT1_MRCS1) -#define bfin_write_SPT1_MRCS1(val) bfin_write32(SPT1_MRCS1, val) -#define pSPT1_MRCS2 ((uint32_t volatile *)SPT1_MRCS2) -#define bfin_read_SPT1_MRCS2() bfin_read32(SPT1_MRCS2) -#define bfin_write_SPT1_MRCS2(val) bfin_write32(SPT1_MRCS2, val) -#define pSPT1_MRCS3 ((uint32_t volatile *)SPT1_MRCS3) -#define bfin_read_SPT1_MRCS3() bfin_read32(SPT1_MRCS3) -#define bfin_write_SPT1_MRCS3(val) bfin_write32(SPT1_MRCS3, val) -#define pSPT1_MCMC1 ((uint16_t volatile *)SPT1_MCMC1) -#define bfin_read_SPT1_MCMC1() bfin_read16(SPT1_MCMC1) -#define bfin_write_SPT1_MCMC1(val) bfin_write16(SPT1_MCMC1, val) -#define pSPT1_MCMC2 ((uint16_t volatile *)SPT1_MCMC2) -#define bfin_read_SPT1_MCMC2() bfin_read16(SPT1_MCMC2) -#define bfin_write_SPT1_MCMC2(val) bfin_write16(SPT1_MCMC2, val) -#define pSPT1_CHNL ((uint16_t volatile *)SPT1_CHNL) -#define bfin_read_SPT1_CHNL() bfin_read16(SPT1_CHNL) -#define bfin_write_SPT1_CHNL(val) bfin_write16(SPT1_CHNL, val) -#define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL) -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY) -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control register (16-bit) */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register (16-bit) */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register (16-bit) */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status register (16-bit) */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE) -#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) -#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) -#define pPFCTL ((uint32_t volatile *)PFCTL) -#define bfin_read_PFCTL() bfin_read32(PFCTL) -#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) -#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) -#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) -#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) -#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) -#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) -#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pSPI_CTL ((uint16_t volatile *)SPI_CTL) -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define pSPI_FLG ((uint16_t volatile *)SPI_FLG) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define pSPI_STAT ((uint16_t volatile *)SPI_STAT) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) -#define pFIO_FLAG_D ((uint16_t volatile *)FIO_FLAG_D) -#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) -#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) -#define pFIO_FLAG_C ((uint16_t volatile *)FIO_FLAG_C) -#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) -#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) -#define pFIO_FLAG_S ((uint16_t volatile *)FIO_FLAG_S) -#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) -#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) -#define pFIO_FLAG_T ((uint16_t volatile *)FIO_FLAG_T) -#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) -#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) -#define pFIO_MASKA_D ((uint16_t volatile *)FIO_MASKA_D) -#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) -#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D, val) -#define pFIO_MASKA_C ((uint16_t volatile *)FIO_MASKA_C) -#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) -#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C, val) -#define pFIO_MASKA_S ((uint16_t volatile *)FIO_MASKA_S) -#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) -#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S, val) -#define pFIO_MASKA_T ((uint16_t volatile *)FIO_MASKA_T) -#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) -#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T, val) -#define pFIO_MASKB_D ((uint16_t volatile *)FIO_MASKB_D) -#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) -#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D, val) -#define pFIO_MASKB_C ((uint16_t volatile *)FIO_MASKB_C) -#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) -#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C, val) -#define pFIO_MASKB_S ((uint16_t volatile *)FIO_MASKB_S) -#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) -#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S, val) -#define pFIO_MASKB_T ((uint16_t volatile *)FIO_MASKB_T) -#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) -#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T, val) -#define pFIO_DIR ((uint16_t volatile *)FIO_DIR) -#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) -#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR, val) -#define pFIO_POLAR ((uint16_t volatile *)FIO_POLAR) -#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) -#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR, val) -#define pFIO_EDGE ((uint16_t volatile *)FIO_EDGE) -#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) -#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE, val) -#define pFIO_BOTH ((uint16_t volatile *)FIO_BOTH) -#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) -#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH, val) -#define pFIO_INEN ((uint16_t volatile *)FIO_INEN) -#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) -#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */ -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */ -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */ -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */ -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */ -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */ -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */ -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */ -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */ -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */ -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */ -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */ -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pDMA0_NEXT_DESC_PTR ((uint32_t volatile *)DMA0_NEXT_DESC_PTR) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((uint32_t volatile *)DMA0_START_ADDR) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((uint32_t volatile *)DMA0_CURR_DESC_PTR) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((uint32_t volatile *)DMA0_CURR_ADDR) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((uint32_t volatile *)DMA1_NEXT_DESC_PTR) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((uint32_t volatile *)DMA1_START_ADDR) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((uint32_t volatile *)DMA1_CURR_DESC_PTR) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((uint32_t volatile *)DMA1_CURR_ADDR) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((uint32_t volatile *)DMA2_NEXT_DESC_PTR) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((uint32_t volatile *)DMA2_START_ADDR) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((uint32_t volatile *)DMA2_CURR_DESC_PTR) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((uint32_t volatile *)DMA2_CURR_ADDR) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((uint32_t volatile *)DMA3_NEXT_DESC_PTR) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((uint32_t volatile *)DMA3_START_ADDR) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((uint32_t volatile *)DMA3_CURR_DESC_PTR) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((uint32_t volatile *)DMA3_CURR_ADDR) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((uint32_t volatile *)DMA4_NEXT_DESC_PTR) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((uint32_t volatile *)DMA4_START_ADDR) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((uint32_t volatile *)DMA4_CURR_DESC_PTR) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((uint32_t volatile *)DMA4_CURR_ADDR) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((uint32_t volatile *)DMA5_NEXT_DESC_PTR) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((uint32_t volatile *)DMA5_START_ADDR) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((uint32_t volatile *)DMA5_CURR_DESC_PTR) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((uint32_t volatile *)DMA5_CURR_ADDR) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((uint32_t volatile *)DMA6_START_ADDR) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((uint32_t volatile *)DMA6_CURR_DESC_PTR) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((uint32_t volatile *)DMA6_CURR_ADDR) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((uint32_t volatile *)DMA7_NEXT_DESC_PTR) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((uint32_t volatile *)DMA7_START_ADDR) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((uint32_t volatile *)DMA7_CURR_DESC_PTR) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((uint32_t volatile *)DMA7_CURR_ADDR) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_D0_NEXT_DESC_PTR) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((uint32_t volatile *)MDMA_D0_START_ADDR) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((uint32_t volatile *)MDMA_D0_CURR_DESC_PTR) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((uint32_t volatile *)MDMA_D0_CURR_ADDR) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_S0_NEXT_DESC_PTR) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((uint32_t volatile *)MDMA_S0_START_ADDR) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((uint32_t volatile *)MDMA_S0_CURR_DESC_PTR) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((uint32_t volatile *)MDMA_S0_CURR_ADDR) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_D1_NEXT_DESC_PTR) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((uint32_t volatile *)MDMA_D1_START_ADDR) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */ -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((uint32_t volatile *)MDMA_D1_CURR_DESC_PTR) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((uint32_t volatile *)MDMA_D1_CURR_ADDR) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_S1_NEXT_DESC_PTR) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((uint32_t volatile *)MDMA_S1_START_ADDR) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((uint32_t volatile *)MDMA_S1_CURR_DESC_PTR) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((uint32_t volatile *)MDMA_S1_CURR_ADDR) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) -#define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) -#define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER) -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_extended__ */ diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h deleted file mode 100644 index 24b56b3..0000000 --- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_def.h +++ /dev/null @@ -1,543 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_extended__ -#define __BFIN_DEF_ADSP_EDN_extended__ - -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_FAULT_STATUS 0xFFE00008 /* L1 Data Memory Controller Register */ -#define DCPLB_FAULT_ADDR 0xFFE0000C -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_FAULT_STATUS 0xFFE01008 -#define ICPLB_FAULT_ADDR 0xFFE0100C -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define MDMAFLX0_DMACNFG_D 0xFFC00E08 -#define MDMAFLX0_XCOUNT_D 0xFFC00E10 -#define MDMAFLX0_XMODIFY_D 0xFFC00E14 -#define MDMAFLX0_YCOUNT_D 0xFFC00E18 -#define MDMAFLX0_YMODIFY_D 0xFFC00E1C -#define MDMAFLX0_IRQSTAT_D 0xFFC00E28 -#define MDMAFLX0_PMAP_D 0xFFC00E2C -#define MDMAFLX0_CURXCOUNT_D 0xFFC00E30 -#define MDMAFLX0_CURYCOUNT_D 0xFFC00E38 -#define MDMAFLX0_DMACNFG_S 0xFFC00E48 -#define MDMAFLX0_XCOUNT_S 0xFFC00E50 -#define MDMAFLX0_XMODIFY_S 0xFFC00E54 -#define MDMAFLX0_YCOUNT_S 0xFFC00E58 -#define MDMAFLX0_YMODIFY_S 0xFFC00E5C -#define MDMAFLX0_IRQSTAT_S 0xFFC00E68 -#define MDMAFLX0_PMAP_S 0xFFC00E6C -#define MDMAFLX0_CURXCOUNT_S 0xFFC00E70 -#define MDMAFLX0_CURYCOUNT_S 0xFFC00E78 -#define MDMAFLX1_DMACNFG_D 0xFFC00E88 -#define MDMAFLX1_XCOUNT_D 0xFFC00E90 -#define MDMAFLX1_XMODIFY_D 0xFFC00E94 -#define MDMAFLX1_YCOUNT_D 0xFFC00E98 -#define MDMAFLX1_YMODIFY_D 0xFFC00E9C -#define MDMAFLX1_IRQSTAT_D 0xFFC00EA8 -#define MDMAFLX1_PMAP_D 0xFFC00EAC -#define MDMAFLX1_CURXCOUNT_D 0xFFC00EB0 -#define MDMAFLX1_CURYCOUNT_D 0xFFC00EB8 -#define MDMAFLX1_DMACNFG_S 0xFFC00EC8 -#define MDMAFLX1_XCOUNT_S 0xFFC00ED0 -#define MDMAFLX1_XMODIFY_S 0xFFC00ED4 -#define MDMAFLX1_YCOUNT_S 0xFFC00ED8 -#define MDMAFLX1_YMODIFY_S 0xFFC00EDC -#define MDMAFLX1_IRQSTAT_S 0xFFC00EE8 -#define MDMAFLX1_PMAP_S 0xFFC00EEC -#define MDMAFLX1_CURXCOUNT_S 0xFFC00EF0 -#define MDMAFLX1_CURYCOUNT_S 0xFFC00EF8 -#define DMAFLX0_DMACNFG 0xFFC00C08 -#define DMAFLX0_XCOUNT 0xFFC00C10 -#define DMAFLX0_XMODIFY 0xFFC00C14 -#define DMAFLX0_YCOUNT 0xFFC00C18 -#define DMAFLX0_YMODIFY 0xFFC00C1C -#define DMAFLX0_IRQSTAT 0xFFC00C28 -#define DMAFLX0_PMAP 0xFFC00C2C -#define DMAFLX0_CURXCOUNT 0xFFC00C30 -#define DMAFLX0_CURYCOUNT 0xFFC00C38 -#define DMAFLX1_DMACNFG 0xFFC00C48 -#define DMAFLX1_XCOUNT 0xFFC00C50 -#define DMAFLX1_XMODIFY 0xFFC00C54 -#define DMAFLX1_YCOUNT 0xFFC00C58 -#define DMAFLX1_YMODIFY 0xFFC00C5C -#define DMAFLX1_IRQSTAT 0xFFC00C68 -#define DMAFLX1_PMAP 0xFFC00C6C -#define DMAFLX1_CURXCOUNT 0xFFC00C70 -#define DMAFLX1_CURYCOUNT 0xFFC00C78 -#define DMAFLX2_DMACNFG 0xFFC00C88 -#define DMAFLX2_XCOUNT 0xFFC00C90 -#define DMAFLX2_XMODIFY 0xFFC00C94 -#define DMAFLX2_YCOUNT 0xFFC00C98 -#define DMAFLX2_YMODIFY 0xFFC00C9C -#define DMAFLX2_IRQSTAT 0xFFC00CA8 -#define DMAFLX2_PMAP 0xFFC00CAC -#define DMAFLX2_CURXCOUNT 0xFFC00CB0 -#define DMAFLX2_CURYCOUNT 0xFFC00CB8 -#define DMAFLX3_DMACNFG 0xFFC00CC8 -#define DMAFLX3_XCOUNT 0xFFC00CD0 -#define DMAFLX3_XMODIFY 0xFFC00CD4 -#define DMAFLX3_YCOUNT 0xFFC00CD8 -#define DMAFLX3_YMODIFY 0xFFC00CDC -#define DMAFLX3_IRQSTAT 0xFFC00CE8 -#define DMAFLX3_PMAP 0xFFC00CEC -#define DMAFLX3_CURXCOUNT 0xFFC00CF0 -#define DMAFLX3_CURYCOUNT 0xFFC00CF8 -#define DMAFLX4_DMACNFG 0xFFC00D08 -#define DMAFLX4_XCOUNT 0xFFC00D10 -#define DMAFLX4_XMODIFY 0xFFC00D14 -#define DMAFLX4_YCOUNT 0xFFC00D18 -#define DMAFLX4_YMODIFY 0xFFC00D1C -#define DMAFLX4_IRQSTAT 0xFFC00D28 -#define DMAFLX4_PMAP 0xFFC00D2C -#define DMAFLX4_CURXCOUNT 0xFFC00D30 -#define DMAFLX4_CURYCOUNT 0xFFC00D38 -#define DMAFLX5_DMACNFG 0xFFC00D48 -#define DMAFLX5_XCOUNT 0xFFC00D50 -#define DMAFLX5_XMODIFY 0xFFC00D54 -#define DMAFLX5_YCOUNT 0xFFC00D58 -#define DMAFLX5_YMODIFY 0xFFC00D5C -#define DMAFLX5_IRQSTAT 0xFFC00D68 -#define DMAFLX5_PMAP 0xFFC00D6C -#define DMAFLX5_CURXCOUNT 0xFFC00D70 -#define DMAFLX5_CURYCOUNT 0xFFC00D78 -#define DMAFLX6_DMACNFG 0xFFC00D88 -#define DMAFLX6_XCOUNT 0xFFC00D90 -#define DMAFLX6_XMODIFY 0xFFC00D94 -#define DMAFLX6_YCOUNT 0xFFC00D98 -#define DMAFLX6_YMODIFY 0xFFC00D9C -#define DMAFLX6_IRQSTAT 0xFFC00DA8 -#define DMAFLX6_PMAP 0xFFC00DAC -#define DMAFLX6_CURXCOUNT 0xFFC00DB0 -#define DMAFLX6_CURYCOUNT 0xFFC00DB8 -#define DMAFLX7_DMACNFG 0xFFC00DC8 -#define DMAFLX7_XCOUNT 0xFFC00DD0 -#define DMAFLX7_XMODIFY 0xFFC00DD4 -#define DMAFLX7_YCOUNT 0xFFC00DD8 -#define DMAFLX7_YMODIFY 0xFFC00DDC -#define DMAFLX7_IRQSTAT 0xFFC00DE8 -#define DMAFLX7_PMAP 0xFFC00DEC -#define DMAFLX7_CURXCOUNT 0xFFC00DF0 -#define DMAFLX7_CURYCOUNT 0xFFC00DF8 -#define TIMER0_CONFIG 0xFFC00600 -#define TIMER0_COUNTER 0xFFC00604 -#define TIMER0_PERIOD 0xFFC00608 -#define TIMER0_WIDTH 0xFFC0060C -#define TIMER1_CONFIG 0xFFC00610 -#define TIMER1_COUNTER 0xFFC00614 -#define TIMER1_PERIOD 0xFFC00618 -#define TIMER1_WIDTH 0xFFC0061C -#define TIMER2_CONFIG 0xFFC00620 -#define TIMER2_COUNTER 0xFFC00624 -#define TIMER2_PERIOD 0xFFC00628 -#define TIMER2_WIDTH 0xFFC0062C -#define TIMER_ENABLE 0xFFC00640 -#define TIMER_DISABLE 0xFFC00644 -#define TIMER_STATUS 0xFFC00648 -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ -#define UART_THR 0xFFC00400 /* Transmit Holding */ -#define UART_DLL 0xFFC00400 /* Divisor Latch Low Byte */ -#define UART_DLH 0xFFC00404 /* Divisor Latch High Byte */ -#define UART_IER 0xFFC00404 -#define UART_IIR 0xFFC00408 -#define UART_LCR 0xFFC0040C -#define UART_MCR 0xFFC00410 -#define UART_LSR 0xFFC00414 -#define UART_SCR 0xFFC0041C -#define UART_RBR 0xFFC00400 /* Receive Buffer */ -#define UART_GCTL 0xFFC00424 -#define SPT0_TX_CONFIG0 0xFFC00800 -#define SPT0_TX_CONFIG1 0xFFC00804 -#define SPT0_RX_CONFIG0 0xFFC00820 -#define SPT0_RX_CONFIG1 0xFFC00824 -#define SPT0_TX 0xFFC00810 -#define SPT0_RX 0xFFC00818 -#define SPT0_TSCLKDIV 0xFFC00808 -#define SPT0_RSCLKDIV 0xFFC00828 -#define SPT0_TFSDIV 0xFFC0080C -#define SPT0_RFSDIV 0xFFC0082C -#define SPT0_STAT 0xFFC00830 -#define SPT0_MTCS0 0xFFC00840 -#define SPT0_MTCS1 0xFFC00844 -#define SPT0_MTCS2 0xFFC00848 -#define SPT0_MTCS3 0xFFC0084C -#define SPT0_MRCS0 0xFFC00850 -#define SPT0_MRCS1 0xFFC00854 -#define SPT0_MRCS2 0xFFC00858 -#define SPT0_MRCS3 0xFFC0085C -#define SPT0_MCMC1 0xFFC00838 -#define SPT0_MCMC2 0xFFC0083C -#define SPT0_CHNL 0xFFC00834 -#define SPT1_TX_CONFIG0 0xFFC00900 -#define SPT1_TX_CONFIG1 0xFFC00904 -#define SPT1_RX_CONFIG0 0xFFC00920 -#define SPT1_RX_CONFIG1 0xFFC00924 -#define SPT1_TX 0xFFC00910 -#define SPT1_RX 0xFFC00918 -#define SPT1_TSCLKDIV 0xFFC00908 -#define SPT1_RSCLKDIV 0xFFC00928 -#define SPT1_TFSDIV 0xFFC0090C -#define SPT1_RFSDIV 0xFFC0092C -#define SPT1_STAT 0xFFC00930 -#define SPT1_MTCS0 0xFFC00940 -#define SPT1_MTCS1 0xFFC00944 -#define SPT1_MTCS2 0xFFC00948 -#define SPT1_MTCS3 0xFFC0094C -#define SPT1_MRCS0 0xFFC00950 -#define SPT1_MRCS1 0xFFC00954 -#define SPT1_MRCS2 0xFFC00958 -#define SPT1_MRCS3 0xFFC0095C -#define SPT1_MCMC1 0xFFC00938 -#define SPT1_MCMC2 0xFFC0093C -#define SPT1_CHNL 0xFFC00934 -#define PPI_CONTROL 0xFFC01000 -#define PPI_STATUS 0xFFC01004 -#define PPI_DELAY 0xFFC0100C -#define PPI_COUNT 0xFFC01008 -#define PPI_FRAME 0xFFC01010 -#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ -#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define EVT_OVERRIDE 0xFFE02100 -#define CHIPID 0xFFC00014 -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ -#define PFCTL 0xFFE08000 -#define PFCNTR0 0xFFE08100 -#define PFCNTR1 0xFFE08104 -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define RTC_STAT 0xFFC00300 -#define RTC_ICTL 0xFFC00304 -#define RTC_ISTAT 0xFFC00308 -#define RTC_SWCNT 0xFFC0030C -#define RTC_ALARM 0xFFC00310 -#define RTC_PREN 0xFFC00314 -#define SPI_CTL 0xFFC00500 -#define SPI_FLG 0xFFC00504 -#define SPI_STAT 0xFFC00508 -#define SPI_TDBR 0xFFC0050C -#define SPI_RDBR 0xFFC00510 -#define SPI_BAUD 0xFFC00514 -#define SPI_SHADOW 0xFFC00518 -#define FIO_FLAG_D 0xFFC00700 -#define FIO_FLAG_C 0xFFC00704 -#define FIO_FLAG_S 0xFFC00708 -#define FIO_FLAG_T 0xFFC0070C -#define FIO_MASKA_D 0xFFC00710 -#define FIO_MASKA_C 0xFFC00714 -#define FIO_MASKA_S 0xFFC00718 -#define FIO_MASKA_T 0xFFC0071C -#define FIO_MASKB_D 0xFFC00720 -#define FIO_MASKB_C 0xFFC00724 -#define FIO_MASKB_S 0xFFC00728 -#define FIO_MASKB_T 0xFFC0072C -#define FIO_DIR 0xFFC00730 -#define FIO_POLAR 0xFFC00734 -#define FIO_EDGE 0xFFC00738 -#define FIO_BOTH 0xFFC0073C -#define FIO_INEN 0xFFC00740 -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 -#define DMA0_START_ADDR 0xFFC00C04 -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 -#define DMA0_X_MODIFY 0xFFC00C14 -#define DMA0_Y_COUNT 0xFFC00C18 -#define DMA0_Y_MODIFY 0xFFC00C1C -#define DMA0_CURR_DESC_PTR 0xFFC00C20 -#define DMA0_CURR_ADDR 0xFFC00C24 -#define DMA0_IRQ_STATUS 0xFFC00C28 -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C -#define DMA0_CURR_X_COUNT 0xFFC00C30 -#define DMA0_CURR_Y_COUNT 0xFFC00C38 -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 -#define DMA1_START_ADDR 0xFFC00C44 -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 -#define DMA1_X_MODIFY 0xFFC00C54 -#define DMA1_Y_COUNT 0xFFC00C58 -#define DMA1_Y_MODIFY 0xFFC00C5C -#define DMA1_CURR_DESC_PTR 0xFFC00C60 -#define DMA1_CURR_ADDR 0xFFC00C64 -#define DMA1_IRQ_STATUS 0xFFC00C68 -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C -#define DMA1_CURR_X_COUNT 0xFFC00C70 -#define DMA1_CURR_Y_COUNT 0xFFC00C78 -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 -#define DMA2_START_ADDR 0xFFC00C84 -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 -#define DMA2_X_MODIFY 0xFFC00C94 -#define DMA2_Y_COUNT 0xFFC00C98 -#define DMA2_Y_MODIFY 0xFFC00C9C -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 -#define DMA2_CURR_ADDR 0xFFC00CA4 -#define DMA2_IRQ_STATUS 0xFFC00CA8 -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC -#define DMA2_CURR_X_COUNT 0xFFC00CB0 -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 -#define DMA3_START_ADDR 0xFFC00CC4 -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 -#define DMA3_X_MODIFY 0xFFC00CD4 -#define DMA3_Y_COUNT 0xFFC00CD8 -#define DMA3_Y_MODIFY 0xFFC00CDC -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 -#define DMA3_CURR_ADDR 0xFFC00CE4 -#define DMA3_IRQ_STATUS 0xFFC00CE8 -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC -#define DMA3_CURR_X_COUNT 0xFFC00CF0 -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 -#define DMA4_START_ADDR 0xFFC00D04 -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 -#define DMA4_X_MODIFY 0xFFC00D14 -#define DMA4_Y_COUNT 0xFFC00D18 -#define DMA4_Y_MODIFY 0xFFC00D1C -#define DMA4_CURR_DESC_PTR 0xFFC00D20 -#define DMA4_CURR_ADDR 0xFFC00D24 -#define DMA4_IRQ_STATUS 0xFFC00D28 -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C -#define DMA4_CURR_X_COUNT 0xFFC00D30 -#define DMA4_CURR_Y_COUNT 0xFFC00D38 -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 -#define DMA5_START_ADDR 0xFFC00D44 -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 -#define DMA5_X_MODIFY 0xFFC00D54 -#define DMA5_Y_COUNT 0xFFC00D58 -#define DMA5_Y_MODIFY 0xFFC00D5C -#define DMA5_CURR_DESC_PTR 0xFFC00D60 -#define DMA5_CURR_ADDR 0xFFC00D64 -#define DMA5_IRQ_STATUS 0xFFC00D68 -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C -#define DMA5_CURR_X_COUNT 0xFFC00D70 -#define DMA5_CURR_Y_COUNT 0xFFC00D78 -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 -#define DMA6_START_ADDR 0xFFC00D84 -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 -#define DMA6_X_MODIFY 0xFFC00D94 -#define DMA6_Y_COUNT 0xFFC00D98 -#define DMA6_Y_MODIFY 0xFFC00D9C -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 -#define DMA6_CURR_ADDR 0xFFC00DA4 -#define DMA6_IRQ_STATUS 0xFFC00DA8 -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC -#define DMA6_CURR_X_COUNT 0xFFC00DB0 -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 -#define DMA7_START_ADDR 0xFFC00DC4 -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 -#define DMA7_X_MODIFY 0xFFC00DD4 -#define DMA7_Y_COUNT 0xFFC00DD8 -#define DMA7_Y_MODIFY 0xFFC00DDC -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 -#define DMA7_CURR_ADDR 0xFFC00DE4 -#define DMA7_IRQ_STATUS 0xFFC00DE8 -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC -#define DMA7_CURR_X_COUNT 0xFFC00DF0 -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 -#define MDMA_D0_START_ADDR 0xFFC00E04 -#define MDMA_D0_CONFIG 0xFFC00E08 -#define MDMA_D0_X_COUNT 0xFFC00E10 -#define MDMA_D0_X_MODIFY 0xFFC00E14 -#define MDMA_D0_Y_COUNT 0xFFC00E18 -#define MDMA_D0_Y_MODIFY 0xFFC00E1C -#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 -#define MDMA_D0_CURR_ADDR 0xFFC00E24 -#define MDMA_D0_IRQ_STATUS 0xFFC00E28 -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C -#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 -#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 -#define MDMA_S0_START_ADDR 0xFFC00E44 -#define MDMA_S0_CONFIG 0xFFC00E48 -#define MDMA_S0_X_COUNT 0xFFC00E50 -#define MDMA_S0_X_MODIFY 0xFFC00E54 -#define MDMA_S0_Y_COUNT 0xFFC00E58 -#define MDMA_S0_Y_MODIFY 0xFFC00E5C -#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 -#define MDMA_S0_CURR_ADDR 0xFFC00E64 -#define MDMA_S0_IRQ_STATUS 0xFFC00E68 -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C -#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 -#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 -#define MDMA_D1_START_ADDR 0xFFC00E84 -#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00E90 -#define MDMA_D1_X_MODIFY 0xFFC00E94 -#define MDMA_D1_Y_COUNT 0xFFC00E98 -#define MDMA_D1_Y_MODIFY 0xFFC00E9C -#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 -#define MDMA_D1_CURR_ADDR 0xFFC00EA4 -#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC -#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 -#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 -#define MDMA_S1_START_ADDR 0xFFC00EC4 -#define MDMA_S1_CONFIG 0xFFC00EC8 -#define MDMA_S1_X_COUNT 0xFFC00ED0 -#define MDMA_S1_X_MODIFY 0xFFC00ED4 -#define MDMA_S1_Y_COUNT 0xFFC00ED8 -#define MDMA_S1_Y_MODIFY 0xFFC00EDC -#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 -#define MDMA_S1_CURR_ADDR 0xFFC00EE4 -#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC -#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 -#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 -#define EBIU_AMGCTL 0xFFC00A00 -#define EBIU_AMBCTL0 0xFFC00A04 -#define EBIU_AMBCTL1 0xFFC00A08 -#define EBIU_SDGCTL 0xFFC00A10 -#define EBIU_SDBCTL 0xFFC00A14 -#define EBIU_SDRRC 0xFFC00A18 -#define EBIU_SDSTAT 0xFFC00A1C -#define DMA_TC_CNT 0xFFC00B0C -#define DMA_TC_PER 0xFFC00B10 - -#endif /* __BFIN_DEF_ADSP_EDN_extended__ */ diff --git a/include/asm-blackfin/mach-common/bits/bootrom.h b/include/asm-blackfin/mach-common/bits/bootrom.h deleted file mode 100644 index f537e93..0000000 --- a/include/asm-blackfin/mach-common/bits/bootrom.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Boot ROM Entry Points and such - */ - -/* These Blackfins all have a Boot ROM that is not reusable (at all): - * BF531 / BF532 / BF533 - * BF538 / BF539 - * BF561 - * So there is nothing for us to export ;( - * - * These Blackfins started to roll with the idea that the Boot ROM can - * provide useful functions, but still only a few (and not really useful): - * BF534 / BF536 / BF537 - * - * Looking forward, Boot ROM's on newer Blackfins have quite a few - * nice entry points that are usable at runtime and beyond. We'll - * only define known legacy parts (listed above) and otherwise just - * assume it's a newer part. - * - * These entry points are accomplished by placing a small jump table at - * the start of the Boot ROM. This way the addresses are fixed forever. - */ - -#ifndef __BFIN_PERIPHERAL_BOOTROM__ -#define __BFIN_PERIPHERAL_BOOTROM__ - -/* All Blackfin's have the Boot ROM entry point at the same address */ -#define _BOOTROM_RESET 0xEF000000 - -#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ - defined(__ADSPBF538__) || defined(__ADSPBF539__) || \ - defined(__ADSPBF561__) - - /* Nothing to export */ - -#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) - - /* The BF537 family */ - -#define _BOOTROM_FINAL_INIT 0xEF000002 -/* reserved 0xEF000004 */ -#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 -#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 -#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A -#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C -/* reserved 0xEF00000E */ -#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 -#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 -#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 -/* reserved 0xEF000016 */ -/* reserved 0xEF000018 */ - - /* Glue to newer Boot ROMs */ -#define _BOOTROM_MDMA _BOOTROM_DO_MEMORY_DMA -#define _BOOTROM_MEMBOOT _BOOTROM_BOOT_DXE_FLASH -#define _BOOTROM_SPIBOOT _BOOTROM_BOOT_DXE_FLASH -#define _BOOTROM_TWIBOOT _BOOTROM_BOOT_DXE_TWI - -#else - - /* All the newer Boot ROMs */ - -#define _BOOTROM_FINAL_INIT 0xEF000002 -#define _BOOTROM_PDMA 0xEF000004 -#define _BOOTROM_MDMA 0xEF000006 -#define _BOOTROM_MEMBOOT 0xEF000008 -#define _BOOTROM_SPIBOOT 0xEF00000A -#define _BOOTROM_TWIBOOT 0xEF00000C -/* reserved 0xEF00000E */ -/* reserved 0xEF000010 */ -/* reserved 0xEF000012 */ -/* reserved 0xEF000014 */ -/* reserved 0xEF000016 */ -#define _BOOTROM_OTP_COMMAND 0xEF000018 -#define _BOOTROM_OTP_READ 0xEF00001A -#define _BOOTROM_OTP_WRITE 0xEF00001C -#define _BOOTROM_ECC_TABLE 0xEF00001E -#define _BOOTROM_BOOTKERNEL 0xEF000020 -#define _BOOTROM_GETPORT 0xEF000022 -#define _BOOTROM_NMI 0xEF000024 -#define _BOOTROM_HWERROR 0xEF000026 -#define _BOOTROM_EXCEPTION 0xEF000028 -#define _BOOTROM_CRC32 0xEF000030 -#define _BOOTROM_CRC32POLY 0xEF000032 -#define _BOOTROM_CRC32CALLBACK 0xEF000034 -#define _BOOTROM_CRC32INITCODE 0xEF000036 -#define _BOOTROM_SYSCONTROL 0xEF000038 -#define _BOOTROM_REV 0xEF000040 -#define _BOOTROM_SESR 0xEF001000 - -#define BOOTROM_FOLLOWS_C_ABI 1 - -#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 1 - -#endif - -#ifndef BOOTROM_FOLLOWS_C_ABI -#define BOOTROM_FOLLOWS_C_ABI 0 -#endif -#ifndef BOOTROM_CAPS_ADI_BOOT_STRUCTS -#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 0 -#endif - -/* Possible syscontrol action flags */ -#define SYSCTRL_READ 0x00000000 /* read registers */ -#define SYSCTRL_WRITE 0x00000001 /* write registers */ -#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */ -#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */ -#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */ -#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */ -#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */ -#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */ -#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */ -#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */ -#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */ -#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */ -#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */ - -#ifndef __ASSEMBLY__ - -#if BOOTROM_FOLLOWS_C_ABI -# define BOOTROM_CALLED_FUNC_ATTR -#else -# define BOOTROM_CALLED_FUNC_ATTR __attribute__((saveall)) -#endif - -/* Structures for the syscontrol() function */ -typedef struct ADI_SYSCTRL_VALUES { - uint16_t uwVrCtl; - uint16_t uwPllCtl; - uint16_t uwPllDiv; - uint16_t uwPllLockCnt; - uint16_t uwPllStat; -} ADI_SYSCTRL_VALUES; - -#ifndef _BOOTROM_SYSCONTROL -#define _BOOTROM_SYSCONTROL 0 -#endif -static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL; - -/* We need a dedicated function since we need to screw with the stack pointer - * when resetting. The on-chip ROM will save/restore registers on the stack - * when doing a system reset, so the stack cannot be outside of the chip. - */ -__attribute__((__noreturn__)) -static inline void bfrom_SoftReset(void *new_stack) -{ - while (1) - __asm__ __volatile__( - "sp = %[stack];" - "jump (%[bfrom_syscontrol]);" - : : [bfrom_syscontrol] "p"(bfrom_SysControl), - "q0"(SYSCTRL_SOFTRESET), - "q1"(0), - "q2"(NULL), - [stack] "p"(new_stack) - ); -} - -/* Structures for working with LDRs and boot rom callbacks */ -typedef struct ADI_BOOT_HEADER { - int32_t dBlockCode; - void *pTargetAddress; - int32_t dByteCount; - int32_t dArgument; -} ADI_BOOT_HEADER; - -typedef struct ADI_BOOT_BUFFER { - void *pSource; - int32_t dByteCount; -} ADI_BOOT_BUFFER; - -typedef struct ADI_BOOT_DATA { - void *pSource; - void *pDestination; - int16_t *pControlRegister; - int16_t *pDmaControlRegister; - int32_t dControlValue; - int32_t dByteCount; - int32_t dFlags; - int16_t uwDataWidth; - int16_t uwSrcModifyMult; - int16_t uwDstModifyMult; - int16_t uwHwait; - int16_t uwSsel; - int16_t uwUserShort; - int32_t dUserLong; - int32_t dReserved2; - void *pErrorFunction; - void *pLoadFunction; - void *pCallBackFunction; - ADI_BOOT_HEADER *pHeader; - void *pTempBuffer; - void *pTempCurrent; - int32_t dTempByteCount; - int32_t dBlockCount; - int32_t dClock; - void *pLogBuffer; - void *pLogCurrent; - int32_t dLogByteCount; -} ADI_BOOT_DATA; - -typedef void ADI_BOOT_HOOK_FUNC (ADI_BOOT_DATA *); - -#ifndef _BOOTROM_MEMBOOT -#define _BOOTROM_MEMBOOT 0 -#endif -static uint32_t (* const bfrom_MemBoot)(void *pBootStream, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_MEMBOOT; - -#ifndef _BOOTROM_TWIBOOT -#define _BOOTROM_TWIBOOT 0 -#endif -static uint32_t (* const bfrom_TwiBoot)(int32_t dTwiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_TWIBOOT; - -#ifndef _BOOTROM_SPIBOOT -#define _BOOTROM_SPIBOOT 0 -#endif -static uint32_t (* const bfrom_SpiBoot)(int32_t dSpiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_SPIBOOT; - -#ifndef _BOOTROM_OTPBOOT -#define _BOOTROM_OTPBOOT 0 -#endif -static uint32_t (* const bfrom_OtpBoot)(int32_t dOtpAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_OTPBOOT; - -#ifndef _BOOTROM_NANDBOOT -#define _BOOTROM_NANDBOOT 0 -#endif -static uint32_t (* const bfrom_NandBoot)(int32_t dNandAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_NANDBOOT; - -#endif /* __ASSEMBLY__ */ - -/* Bit defines for ADI_BOOT_DATA->dFlags */ -#define BFLAG_DMACODE_MASK 0x0000000F -#define BFLAG_SAFE 0x00000010 -#define BFLAG_AUX 0x00000020 -#define BFLAG_FILL 0x00000100 -#define BFLAG_QUICKBOOT 0x00000200 -#define BFLAG_CALLBACK 0x00000400 -#define BFLAG_INIT 0x00000800 -#define BFLAG_IGNORE 0x00001000 -#define BFLAG_INDIRECT 0x00002000 -#define BFLAG_FIRST 0x00004000 -#define BFLAG_FINAL 0x00008000 -#define BFLAG_HOOK 0x00400000 -#define BFLAG_HDRINDIRECT 0x00800000 -#define BFLAG_TYPE_MASK 0x00300000 -#define BFLAG_TYPE_1 0x00000000 -#define BFLAG_TYPE_2 0x00100000 -#define BFLAG_TYPE_3 0x00200000 -#define BFLAG_TYPE_4 0x00300000 -#define BFLAG_FASTREAD 0x00400000 -#define BFLAG_NOAUTO 0x01000000 -#define BFLAG_PERIPHERAL 0x02000000 -#define BFLAG_SLAVE 0x04000000 -#define BFLAG_WAKEUP 0x08000000 -#define BFLAG_NEXTDXE 0x10000000 -#define BFLAG_RETURN 0x20000000 -#define BFLAG_RESET 0x40000000 -#define BFLAG_NONRESTORE 0x80000000 - -#endif diff --git a/include/asm-blackfin/mach-common/bits/core.h b/include/asm-blackfin/mach-common/bits/core.h deleted file mode 100644 index 6db4f81..0000000 --- a/include/asm-blackfin/mach-common/bits/core.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Misc Core Masks - */ - -#ifndef __BFIN_PERIPHERAL_CORE__ -#define __BFIN_PERIPHERAL_CORE__ - -/* - * EVT registers (ILAT, IMASK, and IPEND). - */ - -#define EVT_EMU_P 0 /* Emulator interrupt bit position */ -#define EVT_RST_P 1 /* Reset interrupt bit position */ -#define EVT_NMI_P 2 /* Non Maskable interrupt bit position */ -#define EVT_EVX_P 3 /* Exception bit position */ -#define EVT_IRPTEN_P 4 /* Global interrupt enable bit position */ -#define EVT_IVHW_P 5 /* Hardware Error interrupt bit position */ -#define EVT_IVTMR_P 6 /* Timer interrupt bit position */ -#define EVT_IVG7_P 7 /* IVG7 interrupt bit position */ -#define EVT_IVG8_P 8 /* IVG8 interrupt bit position */ -#define EVT_IVG9_P 9 /* IVG9 interrupt bit position */ -#define EVT_IVG10_P 10 /* IVG10 interrupt bit position */ -#define EVT_IVG11_P 11 /* IVG11 interrupt bit position */ -#define EVT_IVG12_P 12 /* IVG12 interrupt bit position */ -#define EVT_IVG13_P 13 /* IVG13 interrupt bit position */ -#define EVT_IVG14_P 14 /* IVG14 interrupt bit position */ -#define EVT_IVG15_P 15 /* IVG15 interrupt bit position */ - -#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */ -#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */ -#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */ -#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */ -#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */ -#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */ -#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */ -#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */ -#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */ -#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */ -#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */ -#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */ -#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */ -#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */ -#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */ -#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */ - -/* - * SEQSTAT register - */ - -#define EXCAUSE_P 0 /* Last exception cause bit positions */ -#define EXCAUSE0_P 0 /* Last exception cause bit 0 */ -#define EXCAUSE1_P 1 /* Last exception cause bit 1 */ -#define EXCAUSE2_P 2 /* Last exception cause bit 2 */ -#define EXCAUSE3_P 3 /* Last exception cause bit 3 */ -#define EXCAUSE4_P 4 /* Last exception cause bit 4 */ -#define EXCAUSE5_P 5 /* Last exception cause bit 5 */ -#define IDLE_REQ_P 12 /* Pending idle mode request, set by IDLE instruction */ -#define SFTRESET_P 13 /* Indicates whether the last reset was a software reset (=1) */ -#define HWERRCAUSE_P 14 /* Last hw error cause bit positions */ -#define HWERRCAUSE0_P 14 /* Last hw error cause bit 0 */ -#define HWERRCAUSE1_P 15 /* Last hw error cause bit 1 */ -#define HWERRCAUSE2_P 16 /* Last hw error cause bit 2 */ -#define HWERRCAUSE3_P 17 /* Last hw error cause bit 3 */ -#define HWERRCAUSE4_P 18 /* Last hw error cause bit 4 */ -#define HWERRCAUSE5_P 19 /* Last hw error cause bit 5 */ -#define HWERRCAUSE6_P 20 /* Last hw error cause bit 6 */ -#define HWERRCAUSE7_P 21 /* Last hw error cause bit 7 */ - -#define EXCAUSE \ - ( MK_BMSK_(EXCAUSE0_P) | \ - MK_BMSK_(EXCAUSE1_P) | \ - MK_BMSK_(EXCAUSE2_P) | \ - MK_BMSK_(EXCAUSE3_P) | \ - MK_BMSK_(EXCAUSE4_P) | \ - MK_BMSK_(EXCAUSE5_P) ) -#define SFTRESET \ - ( MK_BMSK_(SFTRESET_P) ) -#define HWERRCAUSE \ - ( MK_BMSK_(HWERRCAUSE0_P) | \ - MK_BMSK_(HWERRCAUSE1_P) | \ - MK_BMSK_(HWERRCAUSE2_P) | \ - MK_BMSK_(HWERRCAUSE3_P) | \ - MK_BMSK_(HWERRCAUSE4_P) ) - -/* SWRST Masks */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#ifdef __ADSPBF561__ -# define DOUBLE_FAULT_A 0x0008 -# define DOUBLE_FAULT_B 0x0010 -# define DOUBLE_FAULT 0x0018 /* Core [A|B] Double Fault Causes Reset */ -# define RESET_DOUBLE_A 0x0800 -# define RESET_DOUBLE_B 0x1000 -# define RESET_DOUBLE 0x1800 /* SW Reset Generated By Core [A|B] Double-Fault */ -# define RESET_WDOG_B 0x2000 -# define RESET_WDOG_A 0x4000 -# define RESET_WDOG 0x6000 /* SW Reset Generated By Watchdog [A|B] Timer */ -#else -# define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -# define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -# define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#endif -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCFG Masks */ -#define SSSTEP 0x00000001 /* Supervisor Single Step */ -#define CCEN 0x00000002 /* Cycle Counter Enable */ -#define SNEN 0x00000004 /* Self-Nesting Interrupt Enable */ -#define SYSCFG_SSSTEP_P 0 -#define SYSCFG_CCEN_P 1 -#define SYSCFG_SCEN_P 2 - -#endif diff --git a/include/asm-blackfin/mach-common/bits/dma.h b/include/asm-blackfin/mach-common/bits/dma.h deleted file mode 100644 index 136313e..0000000 --- a/include/asm-blackfin/mach-common/bits/dma.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * DMA Masks - */ - -#ifndef __BFIN_PERIPHERAL_DMA__ -#define __BFIN_PERIPHERAL_DMA__ - -/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ -#define DMAEN 0x0001 /* DMA Channel Enable */ -#define WNR 0x0002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ -#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ -#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ -#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ -#define RESTART 0x0020 /* DMA Buffer Clear */ -#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ -#define DI_EN 0x0080 /* Data Interrupt Enable */ -#define NDSIZE 0x0F00 /* Next Descriptor bitmask */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ -#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ -#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ -#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ -#define FLOW_STOP 0x0000 /* Stop Mode */ -#define FLOW_AUTO 0x1000 /* Autobuffer Mode */ -#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */ -#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ -#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ - -#define DMAEN_P 0 /* Channel Enable */ -#define WNR_P 1 /* Channel Direction (W/R*) */ -#define DMA2D_P 4 /* 2D/1D* Mode */ -#define RESTART_P 5 /* Restart */ -#define DI_SEL_P 6 /* Data Interrupt Select */ -#define DI_EN_P 7 /* Data Interrupt Enable */ - -/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ -#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ -#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ -#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ -#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ - -#define DMA_DONE_P 0 /* DMA Done Indicator */ -#define DMA_ERR_P 1 /* DMA Error Indicator */ -#define DFETCH_P 2 /* Descriptor Fetch Indicator */ -#define DMA_RUN_P 3 /* DMA Running Indicator */ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ -#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ -#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ -#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ebiu.h b/include/asm-blackfin/mach-common/bits/ebiu.h deleted file mode 100644 index 7c0c569..0000000 --- a/include/asm-blackfin/mach-common/bits/ebiu.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * EBIU Masks - */ - -#ifndef __BFIN_PERIPHERAL_EBIU__ -#define __BFIN_PERIPHERAL_EBIU__ - -/* EBIU_AMGCTL Masks */ -#define AMCKEN 0x0001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x0000 /* All Banks Disabled */ -#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ -#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0,/ 1, and 2 */ -#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ -#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */ -#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */ -#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */ -#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */ -#define CDPRIO 0x0100 /* Core has priority over DMA for external accesses */ - -/* EBIU_AMGCTL Bit Positions */ -#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ -#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ -#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ -#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ -#define B0_PEN_P 0x00000004 /* Enable 16-bit packing Bank 0 */ -#define B1_PEN_P 0x00000005 /* Enable 16-bit packing Bank 1 */ -#define B2_PEN_P 0x00000006 /* Enable 16-bit packing Bank 2 */ -#define B3_PEN_P 0x00000007 /* Enable 16-bit packing Bank 3 */ -#define CDPRIO_P 0x00000008 /* Core has priority over DMA for external accesses */ - -/* EBIU_AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ -#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ -#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ -#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ -#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ -#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ -#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ -#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ -#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ -#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ -#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ -#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ -#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ -#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ -#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ -#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ -#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ -#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ -#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ -#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ -#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ -#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ - -/* EBIU_AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ -#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ -#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ -#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ -#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ -#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ -#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ -#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ -#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ -#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ -#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ -#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ -#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ -#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ - -/* Only available on newer parts */ -#ifdef EBIU_MODE - -/* EBIU_MBSCTL Bit Positions */ -#define AMSB0CTL_P 0 -#define AMSB1CTL_P 2 -#define AMSB2CTL_P 4 -#define AMSB3CTL_P 6 - -/* EBIU_MBSCTL Masks */ -#define AMSB0CTL_MASK (0x3 << AMSB0CTL_P) /* Async Memory Bank 0 Control Modes */ -#define AMSB0CTL_NONE (0x0 << AMSB0CTL_P) /* Control Mode - 00 - No logic */ -#define AMSB0CTL_ARE (0x1 << AMSB0CTL_P) /* Control Mode - 01 - OR-ed with /ARE */ -#define AMSB0CTL_AOE (0x2 << AMSB0CTL_P) /* Control Mode - 02 - OR-ed with /AOE */ -#define AMSB0CTL_AWE (0x3 << AMSB0CTL_P) /* Control Mode - 03 - OR-ed with /AWE */ -#define AMSB1CTL_MASK (0x3 << AMSB1CTL_P) /* Async Memory Bank 1 Control Modes */ -#define AMSB1CTL_NONE (0x0 << AMSB1CTL_P) /* Control Mode - 00 - No logic */ -#define AMSB1CTL_ARE (0x1 << AMSB1CTL_P) /* Control Mode - 01 - OR-ed with /ARE */ -#define AMSB1CTL_AOE (0x2 << AMSB1CTL_P) /* Control Mode - 02 - OR-ed with /AOE */ -#define AMSB1CTL_AWE (0x3 << AMSB1CTL_P) /* Control Mode - 03 - OR-ed with /AWE */ -#define AMSB2CTL_MASK (0x3 << AMSB2CTL_P) /* Async Memory Bank 2 Control Modes */ -#define AMSB2CTL_NONE (0x0 << AMSB2CTL_P) /* Control Mode - 00 - No logic */ -#define AMSB2CTL_ARE (0x1 << AMSB2CTL_P) /* Control Mode - 01 - OR-ed with /ARE */ -#define AMSB2CTL_AOE (0x2 << AMSB2CTL_P) /* Control Mode - 02 - OR-ed with /AOE */ -#define AMSB2CTL_AWE (0x3 << AMSB2CTL_P) /* Control Mode - 03 - OR-ed with /AWE */ -#define AMSB3CTL_MASK (0x3 << AMSB3CTL_P) /* Async Memory Bank 3 Control Modes */ -#define AMSB3CTL_NONE (0x0 << AMSB3CTL_P) /* Control Mode - 00 - No logic */ -#define AMSB3CTL_ARE (0x1 << AMSB3CTL_P) /* Control Mode - 01 - OR-ed with /ARE */ -#define AMSB3CTL_AOE (0x2 << AMSB3CTL_P) /* Control Mode - 02 - OR-ed with /AOE */ -#define AMSB3CTL_AWE (0x3 << AMSB3CTL_P) /* Control Mode - 03 - OR-ed with /AWE */ - -/* EBIU_MODE Bit Positions */ -#define B0MODE_P 0 -#define B1MODE_P 2 -#define B2MODE_P 4 -#define B3MODE_P 6 - -/* EBIU_MODE Masks */ -#define B0MODE_MASK (0x3 << B0MODE_P) /* Async Memory Bank 0 Access Mode */ -#define B0MODE_ASYNC (0x0 << B0MODE_P) /* Access Mode - 00 - Asynchronous Mode */ -#define B0MODE_FLASH (0x1 << B0MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */ -#define B0MODE_PAGE (0x2 << B0MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */ -#define B0MODE_BURST (0x3 << B0MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */ -#define B1MODE_MASK (0x3 << B1MODE_P) /* Async Memory Bank 1 Access Mode */ -#define B1MODE_ASYNC (0x0 << B1MODE_P) /* Access Mode - 00 - Asynchronous Mode */ -#define B1MODE_FLASH (0x1 << B1MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */ -#define B1MODE_PAGE (0x2 << B1MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */ -#define B1MODE_BURST (0x3 << B1MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */ -#define B2MODE_MASK (0x3 << B2MODE_P) /* Async Memory Bank 2 Access Mode */ -#define B2MODE_ASYNC (0x0 << B2MODE_P) /* Access Mode - 00 - Asynchronous Mode */ -#define B2MODE_FLASH (0x1 << B2MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */ -#define B2MODE_PAGE (0x2 << B2MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */ -#define B2MODE_BURST (0x3 << B2MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */ -#define B3MODE_MASK (0x3 << B3MODE_P) /* Async Memory Bank 3 Access Mode */ -#define B3MODE_ASYNC (0x0 << B3MODE_P) /* Access Mode - 00 - Asynchronous Mode */ -#define B3MODE_FLASH (0x1 << B3MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */ -#define B3MODE_PAGE (0x2 << B3MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */ -#define B3MODE_BURST (0x3 << B3MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */ - -/* EBIU_FCTL Bit Positions */ -#define TESTSETLOCK_P 0 -#define BCLK_P 1 -#define PGWS_P 3 -#define PGSZ_P 6 -#define RDDL_P 7 - -/* EBIU_FCTL Masks */ -#define TESTSETLOCK (0x1 << TESTSETLOCK_P) /* Test set lock */ -#define BCLK_MASK (0x3 << BCLK_P) /* Burst clock frequency */ -#define BCLK_2 (0x1 << BCLK_P) /* Burst clock frequency - SCLK/2 */ -#define BCLK_3 (0x2 << BCLK_P) /* Burst clock frequency - SCLK/3 */ -#define BCLK_4 (0x3 << BCLK_P) /* Burst clock frequency - SCLK/4 */ -#define PGWS_MASK (0x7 << PGWS_P) /* Page wait states */ -#define PGWS_0 (0x0 << PGWS_P) /* Page wait states - 0 cycles */ -#define PGWS_1 (0x1 << PGWS_P) /* Page wait states - 1 cycles */ -#define PGWS_2 (0x2 << PGWS_P) /* Page wait states - 2 cycles */ -#define PGWS_3 (0x3 << PGWS_P) /* Page wait states - 3 cycles */ -#define PGWS_4 (0x4 << PGWS_P) /* Page wait states - 4 cycles */ -#define PGSZ (0x1 << PGSZ_P) /* Page size */ -#define PGSZ_4 (0x0 << PGSZ_P) /* Page size - 4 words */ -#define PGSZ_8 (0x1 << PGSZ_P) /* Page size - 8 words */ -#define RDDL (0x38 << RDDL_P) /* Read data delay */ - -/* EBIU_ARBSTAT Masks */ -#define ARBSTAT 0x00000001 /* Arbitration status */ -#define BGSTAT 0x00000002 /* External Bus grant status */ - -#endif /* EBIU_MODE */ - -/* Only available on SDRAM based-parts */ -#ifdef EBIU_SDGCTL - -/* EBIU_SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ -#define SCK1E 0x00000002 /* Enable CLKOUT, /SCLK1 */ -#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /* Power-up start delay */ -#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ -#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ -#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ -#define EBUFE 0x02000000 /* Enable external buffering timing */ -#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ -#define EMREN 0x10000000 /* Extended mode register enable */ -#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ -#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x0001 /* Enable SDRAM External Bank */ -#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ -#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ -#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ -#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ -#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ -#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ -#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ -#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ -#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ -#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ - -#ifdef __ADSPBF561__ - -#define EB0E (EBE<<0) /* Enable SDRAM external bank 0 */ -#define EB0SZ_16 (EBSZ_16<<0) /* SDRAM external bank size = 16MB */ -#define EB0SZ_32 (EBSZ_32<<0) /* SDRAM external bank size = 32MB */ -#define EB0SZ_64 (EBSZ_64<<0) /* SDRAM external bank size = 64MB */ -#define EB0SZ_128 (EBSZ_128<<0) /* SDRAM external bank size = 128MB */ -#define EB0CAW_8 (EBCAW_8<<0) /* SDRAM external bank column address width = 8 bits */ -#define EB0CAW_9 (EBCAW_9<<0) /* SDRAM external bank column address width = 9 bits */ -#define EB0CAW_10 (EBCAW_10<<0) /* SDRAM external bank column address width = 9 bits */ -#define EB0CAW_11 (EBCAW_11<<0) /* SDRAM external bank column address width = 9 bits */ - -#define EB1E (EBE<<8) /* Enable SDRAM external bank 0 */ -#define EB1SZ_16 (EBSZ_16<<8) /* SDRAM external bank size = 16MB */ -#define EB1SZ_32 (EBSZ_32<<8) /* SDRAM external bank size = 32MB */ -#define EB1SZ_64 (EBSZ_64<<8) /* SDRAM external bank size = 64MB */ -#define EB1SZ_128 (EBSZ_128<<8) /* SDRAM external bank size = 128MB */ -#define EB1CAW_8 (EBCAW_8<<8) /* SDRAM external bank column address width = 8 bits */ -#define EB1CAW_9 (EBCAW_9<<8) /* SDRAM external bank column address width = 9 bits */ -#define EB1CAW_10 (EBCAW_10<<8) /* SDRAM external bank column address width = 9 bits */ -#define EB1CAW_11 (EBCAW_11<<8) /* SDRAM external bank column address width = 9 bits */ - -#define EB2E (EBE<<16) /* Enable SDRAM external bank 0 */ -#define EB2SZ_16 (EBSZ_16<<16) /* SDRAM external bank size = 16MB */ -#define EB2SZ_32 (EBSZ_32<<16) /* SDRAM external bank size = 32MB */ -#define EB2SZ_64 (EBSZ_64<<16) /* SDRAM external bank size = 64MB */ -#define EB2SZ_128 (EBSZ_128<<16) /* SDRAM external bank size = 128MB */ -#define EB2CAW_8 (EBCAW_8<<16) /* SDRAM external bank column address width = 8 bits */ -#define EB2CAW_9 (EBCAW_9<<16) /* SDRAM external bank column address width = 9 bits */ -#define EB2CAW_10 (EBCAW_10<<16) /* SDRAM external bank column address width = 9 bits */ -#define EB2CAW_11 (EBCAW_11<<16) /* SDRAM external bank column address width = 9 bits */ - -#define EB3E (EBE<<24) /* Enable SDRAM external bank 0 */ -#define EB3SZ_16 (EBSZ_16<<24) /* SDRAM external bank size = 16MB */ -#define EB3SZ_32 (EBSZ_32<<24) /* SDRAM external bank size = 32MB */ -#define EB3SZ_64 (EBSZ_64<<24) /* SDRAM external bank size = 64MB */ -#define EB3SZ_128 (EBSZ_128<<24) /* SDRAM external bank size = 128MB */ -#define EB3CAW_8 (EBCAW_8<<24) /* SDRAM external bank column address width = 8 bits */ -#define EB3CAW_9 (EBCAW_9<<24) /* SDRAM external bank column address width = 9 bits */ -#define EB3CAW_10 (EBCAW_10<<24) /* SDRAM external bank column address width = 9 bits */ -#define EB3CAW_11 (EBCAW_11<<24) /* SDRAM external bank column address width = 9 bits */ - -#endif /* BF561 */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x0001 /* SDRAM controller is idle */ -#define SDSRA 0x0002 /* SDRAM self refresh is active */ -#define SDPUA 0x0004 /* SDRAM power up active */ -#define SDRS 0x0008 /* SDRAM is in reset state */ -#define SDEASE 0x0010 /* SDRAM EAB sticky error status - W1C */ -#define BGSTAT 0x0020 /* Bus granted */ - -/* Only available on DDR based-parts */ -#else - -/* EBIU_ERRMST Masks */ -#define DEB0_ERROR 0x0001 /* DEB0 access on reserved memory */ -#define DEB1_ERROR 0x0002 /* DEB1 access on reserved memory */ -#define DEB2_ERROR 0x0004 /* DEB2 (USB) access on reserved memory */ -#define CORE_ERROR 0x0008 /* Core access on reserved memory */ -#define DEB0_MERROR 0x0010 /* DEB0 access on reserved memory and DEB0_ERROR is set */ -#define DEB1_MERROR 0x0020 /* DEB1 access on reserved memory and DEB1_ERROR is set */ -#define DEB2_MERROR 0x0040 /* DEB2 access on reserved memory and DEB2_ERROR is set */ -#define CORE_MERROR 0x0080 /* Core access on reserved memory and CORE_ERROR is set */ - -/* EBIU_RSTCTL Masks */ -#define DDR_SRESET 0x0001 /* Reset Control to DDR Controller */ -#define SRREQ 0x0008 /* Self Refresh Request */ -#define SRACK 0x0010 /* Self Refresh Request Acknowledgement */ -#define MDDRENABLE 0x0020 /* Mobile DDR Enable */ - -#endif /* EBIU_SDGCTL */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/emac.h b/include/asm-blackfin/mach-common/bits/emac.h deleted file mode 100644 index 7a43bbb..0000000 --- a/include/asm-blackfin/mach-common/bits/emac.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Ethernet MAC Masks - */ - -#ifndef __BFIN_PERIPHERAL_EMAC__ -#define __BFIN_PERIPHERAL_EMAC__ - -/* EMAC_OPMODE Masks */ -#define RE 0x00000001 /* Receiver Enable */ -#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ -#define HU 0x00000010 /* Hash Filter Unicast Address */ -#define HM 0x00000020 /* Hash Filter Multicast Address */ -#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ -#define PR 0x00000080 /* Promiscuous Mode Enable */ -#define IFE 0x00000100 /* Inverse Filtering Enable */ -#define DBF 0x00000200 /* Disable Broadcast Frame Reception */ -#define PBF 0x00000400 /* Pass Bad Frames Enable */ -#define PSF 0x00000800 /* Pass Short Frames Enable */ -#define RAF 0x00001000 /* Receive-All Mode */ -#define TE 0x00010000 /* Transmitter Enable */ -#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ -#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ -#define DC 0x00080000 /* Deferral Check */ -#define BOLMT 0x00300000 /* Back-Off Limit */ -#define BOLMT_10 0x00000000 /* 10-bit range */ -#define BOLMT_8 0x00100000 /* 8-bit range */ -#define BOLMT_4 0x00200000 /* 4-bit range */ -#define BOLMT_1 0x00300000 /* 1-bit range */ -#define DRTY 0x00400000 /* Disable TX Retry On Collision */ -#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ -#define RMII 0x01000000 /* RMII/MII* Mode */ -#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ -#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ -#define LB 0x08000000 /* Internal Loopback Enable */ -#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ - -/* EMAC_STAADD Masks */ -#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ -#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ -#define STADISPRE 0x00000004 /* Disable Preamble Generation */ -#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ -#define REGAD 0x000007C0 /* STA Register Address */ -#define PHYAD 0x0000F800 /* PHY Device Address */ - -#define SET_REGAD(x) (((x) & 0x1F) << 6) /* Set STA Register Address */ -#define SET_PHYAD(x) (((x) & 0x1F) << 11) /* Set PHY Device Address */ - -/* EMAC_STADAT Mask */ -#define STADATA 0x0000FFFF /* Station Management Data */ - -/* EMAC_FLC Masks */ -#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ -#define FLCE 0x00000002 /* Flow Control Enable */ -#define PCF 0x00000004 /* Pass Control Frames */ -#define BKPRSEN 0x00000008 /* Enable Backpressure */ -#define FLCPAUSE 0xFFFF0000 /* Pause Time */ - -#define SET_FLCPAUSE(x) (((x) & 0xFFFF) << 16) /* Set Pause Time */ - -/* EMAC_WKUP_CTL Masks */ -#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ -#define MPKE 0x00000002 /* Magic Packet Enable */ -#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ -#define GUWKE 0x00000008 /* Global Unicast Wake Enable */ -#define MPKS 0x00000020 /* Magic Packet Received Status */ -#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ - -/* EMAC_WKUP_FFCMD Masks */ -#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ -#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ -#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ -#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ -#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ -#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ -#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ -#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ - -/* EMAC_WKUP_FFOFF Masks */ -#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ -#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ -#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ -#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ - -#define SET_WF0_OFF(x) (((x) & 0xFF) << 0) /* Set Wake-Up Filter 0 Byte Offset */ -#define SET_WF1_OFF(x) (((x) & 0xFF) << 8) /* Set Wake-Up Filter 1 Byte Offset */ -#define SET_WF2_OFF(x) (((x) & 0xFF) << 16) /* Set Wake-Up Filter 2 Byte Offset */ -#define SET_WF3_OFF(x) (((x) & 0xFF) << 24) /* Set Wake-Up Filter 3 Byte Offset */ -/* Set ALL Offsets */ -#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) - -/* EMAC_WKUP_FFCRC0 Masks */ -#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ -#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ - -#define SET_WF0_CRC(x) (((x) & 0xFFFF) << 0) /* Set Wake-Up Filter 0 Target CRC */ -#define SET_WF1_CRC(x) (((x) & 0xFFFF) << 16) /* Set Wake-Up Filter 1 Target CRC */ - -/* EMAC_WKUP_FFCRC1 Masks */ -#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ -#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ - -#define SET_WF2_CRC(x) (((x) & 0xFFFF) << 0) /* Set Wake-Up Filter 2 Target CRC */ -#define SET_WF3_CRC(x) (((x) & 0xFFFF) << 16) /* Set Wake-Up Filter 3 Target CRC */ - -/* EMAC_SYSCTL Masks */ -#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ -#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ -#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ -#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ - -#define SET_MDCDIV(x) (((x) & 0x3F) << 8) /* Set MDC Clock Divisor */ - -/* EMAC_SYSTAT Masks */ -#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ -#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ -#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ -#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ -#define WAKEDET 0x00000010 /* Wake-Up Detected Status */ -#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ -#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ -#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ - -/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ -#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ -#define RX_COMP 0x00001000 /* RX Frame Complete */ -#define RX_OK 0x00002000 /* RX Frame Received With No Errors */ -#define RX_LONG 0x00004000 /* RX Frame Too Long Error */ -#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ -#define RX_CRC 0x00010000 /* RX Frame CRC Error */ -#define RX_LEN 0x00020000 /* RX Frame Length Error */ -#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ -#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ -#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ -#define RX_PHY 0x00200000 /* RX Frame PHY Error */ -#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ -#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ -#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ -#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ -#define RX_CTL 0x04000000 /* RX Control Frame Indicator */ -#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ -#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ -#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ -#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ -#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ - -/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ -#define TX_COMP 0x00000001 /* TX Frame Complete */ -#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ -#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ -#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ -#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ -#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ -#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ -#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ -#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ -#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ -#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ -#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ -#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ -#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ -#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ - -/* EMAC_MMC_CTL Masks */ -#define RSTC 0x00000001 /* Reset All Counters */ -#define CROLL 0x00000002 /* Counter Roll-Over Enable */ -#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ -#define MMCE 0x00000008 /* Enable MMC Counter Operation */ - -/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ -#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ -#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ -#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ -#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ -#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ -#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ -#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ -#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ -#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ -#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ -#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ -#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ -#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ -#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ -#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ -#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ -#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ -#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ -#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ -#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ -#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ -#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ -#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ -#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ - -/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ -#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ -#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ -#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ -#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ -#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ -#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ -#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ -#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ -#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ -#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ -#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ -#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ -#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ -#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ -#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ -#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ -#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ -#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ -#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ -#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ -#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ -#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ -#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/eppi.h b/include/asm-blackfin/mach-common/bits/eppi.h deleted file mode 100644 index fb1456f..0000000 --- a/include/asm-blackfin/mach-common/bits/eppi.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Enhanced PPI (EPPI) - */ - -#ifndef __BFIN_PERIPHERAL_EPPI__ -#define __BFIN_PERIPHERAL_EPPI__ - -/* Bit masks for EPPIx_STATUS */ -#define CFIFO_ERR 0x0001 /* Chroma FIFO Error */ -#define YFIFO_ERR 0x0002 /* Luma FIFO Error */ -#define LTERR_OVR 0x0004 /* Line Track Overflow */ -#define LTERR_UNDR 0x0008 /* Line Track Underflow */ -#define FTERR_OVR 0x0010 /* Frame Track Overflow */ -#define FTERR_UNDR 0x0020 /* Frame Track Underflow */ -#define ERR_NCOR 0x0040 /* Preamble Error Not Corrected */ -#define DMA1URQ 0x0080 /* DMA1 Urgent Request */ -#define DMA0URQ 0x0100 /* DMA0 Urgent Request */ -#define ERR_DET 0x4000 /* Preamble Error Detected */ -#define FLD 0x8000 /* Field */ - -/* Bit masks for EPPIx_CONTROL */ -#define EPPI_EN 0x00000001 /* Enable */ -#define EPPI_DIR 0x00000002 /* Direction */ -#define XFR_TYPE 0x0000000c /* Operating Mode */ -#define FS_CFG 0x00000030 /* Frame Sync Configuration */ -#define FLD_SEL 0x00000040 /* Field Select/Trigger */ -#define ITU_TYPE 0x00000080 /* ITU Interlaced or Progressive */ -#define BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */ -#define ICLKGEN 0x00000200 /* Internal Clock Generation */ -#define IFSGEN 0x00000400 /* Internal Frame Sync Generation */ -#define POLC 0x00001800 /* Frame Sync and Data Driving/Sampling Edges */ -#define POLS 0x00006000 /* Frame Sync Polarity */ -#define DLENGTH 0x00038000 /* Data Length */ -#define SKIP_EN 0x00040000 /* Skip Enable */ -#define SKIP_EO 0x00080000 /* Skip Even or Odd */ -#define PACKEN 0x00100000 /* Packing/Unpacking Enable */ -#define SWAPEN 0x00200000 /* Swap Enable */ -#define SIGN_EXT 0x00400000 /* Sign Extension or Zero-filled / Data Split Format */ -#define SPLT_EVEN_ODD 0x00800000 /* Split Even and Odd Data Samples */ -#define SUBSPLT_ODD 0x01000000 /* Sub-split Odd Samples */ -#define DMACFG 0x02000000 /* One or Two DMA Channels Mode */ -#define RGB_FMT_EN 0x04000000 /* RGB Formatting Enable */ -#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ -#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ - -#define DLEN_8 (0 << 15) /* 000 - 8 bits */ -#define DLEN_10 (1 << 15) /* 001 - 10 bits */ -#define DLEN_12 (2 << 15) /* 010 - 12 bits */ -#define DLEN_14 (3 << 15) /* 011 - 14 bits */ -#define DLEN_16 (4 << 15) /* 100 - 16 bits */ -#define DLEN_18 (5 << 15) /* 101 - 18 bits */ -#define DLEN_24 (6 << 15) /* 110 - 24 bits */ - -/* Bit masks for EPPIx_FS2W_LVB */ -#define F1VB_BD 0x000000ff /* Vertical Blanking before Field 1 Active Data */ -#define F1VB_AD 0x0000ff00 /* Vertical Blanking after Field 1 Active Data */ -#define F2VB_BD 0x00ff0000 /* Vertical Blanking before Field 2 Active Data */ -#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */ - -/* Bit masks for EPPIx_FS2W_LAVF */ -#define F1_ACT 0x0000ffff /* Number of Lines of Active Data in Field 1 */ -#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */ - -/* Bit masks for EPPIx_CLIP */ -#define LOW_ODD 0x000000ff /* Lower Limit for Odd Bytes (Chroma) */ -#define HIGH_ODD 0x0000ff00 /* Upper Limit for Odd Bytes (Chroma) */ -#define LOW_EVEN 0x00ff0000 /* Lower Limit for Even Bytes (Luma) */ -#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/lockbox.h b/include/asm-blackfin/mach-common/bits/lockbox.h deleted file mode 100644 index 77f849e..0000000 --- a/include/asm-blackfin/mach-common/bits/lockbox.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Lockbox/Security Masks - */ - -#ifndef __BFIN_PERIPHERAL_LOCKBOX__ -#define __BFIN_PERIPHERAL_LOCKBOX__ - -#ifndef __ASSEMBLY__ - -#include "bootrom.h" - -/* SESR argument structure. Expected to reside at 0xFF900018. */ -typedef struct SESR_args { - unsigned short usFlags; /* security firmware flags */ - unsigned short usIRQMask; /* interrupt mask */ - unsigned long ulMessageSize; /* message length in bytes */ - unsigned long ulSFEntryPoint; /* entry point of secure function */ - unsigned long ulMessagePtr; /* pointer to the buffer containing - the digital signature and message */ - unsigned long ulReserved1; /* reserved */ - unsigned long ulReserved2; /* reserved */ -} tSESR_args; - -/* Secure Entry Service Routine */ -static void (* const sesr)(void) = (void *)_BOOTROM_SESR; - -#endif - -/* SESR flags argument bitfields */ -#define SESR_FLAGS_STAY_AT_NMI 0x0000 -#define SESR_FLAGS_DROP_BELOW_NMI 0x0001 -#define SESR_FLAGS_NO_SF_DMA 0x0000 -#define SESR_FLAGS_DMA_SF_TO_RUN_DEST 0x0002 -#define SESR_FLAGS_USE_ADI_PUB_KEY 0x0000 -#define SESR_FLAGS_USE_CUST_PUB_KEY 0x0100 - -/* Bit masks for SECURE_SYSSWT */ -#define EMUDABL 0x00000001 /* Emulation Disable */ -#define RSTDABL 0x00000002 /* Reset Disable */ -#define L1IDABL 0x0000001c /* L1 Instruction Memory Disable */ -#define L1DADABL 0x000000e0 /* L1 Data Bank A Memory Disable */ -#define L1DBDABL 0x00000700 /* L1 Data Bank B Memory Disable */ -#define DMA0OVR 0x00000800 /* DMA0 Memory Access Override */ -#define DMA1OVR 0x00001000 /* DMA1 Memory Access Override */ -#define EMUOVR 0x00004000 /* Emulation Override */ -#define OTPSEN 0x00008000 /* OTP Secrets Enable */ -#define L2DABL 0x00070000 /* L2 Memory Disable */ - -/* Bit masks for SECURE_CONTROL */ -#define SECURE0 0x0001 /* SECURE 0 */ -#define SECURE1 0x0002 /* SECURE 1 */ -#define SECURE2 0x0004 /* SECURE 2 */ -#define SECURE3 0x0008 /* SECURE 3 */ - -/* Bit masks for SECURE_STATUS */ -#define SECMODE 0x0003 /* Secured Mode Control State */ -#define NMI 0x0004 /* Non Maskable Interrupt */ -#define AFVALID 0x0008 /* Authentication Firmware Valid */ -#define AFEXIT 0x0010 /* Authentication Firmware Exit */ -#define SECSTAT 0x00e0 /* Secure Status */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/mpu.h b/include/asm-blackfin/mach-common/bits/mpu.h deleted file mode 100644 index 39998f8..0000000 --- a/include/asm-blackfin/mach-common/bits/mpu.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * MPU Masks - */ - -#ifndef __BFIN_PERIPHERAL_MPU__ -#define __BFIN_PERIPHERAL_MPU__ - -/* - * DMEM_CONTROL Register - */ - -/* ** Bit Positions */ -#define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */ -#define DMCTL_ENDM_P ENDM_P /* "" (older define) */ -#define ENDCPLB_P 0x01 /* Enable DCPLBS */ -#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */ -#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */ -#define DMCTL_DMC0_P DMC0_P /* "" (older define) */ -#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */ -#define DMCTL_DMC1_P DMC1_P /* "" (older define) */ -#define DCBS_P 0x04 /* L1 Data Cache Bank Select */ -#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ -#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ - -/* ** Masks */ -#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */ -#define ENDCPLB 0x00000002 /* Enable DCPLB */ -#define ASRAM_BSRAM 0x00000000 -#define ACACHE_BSRAM 0x00000008 -#define ACACHE_BCACHE 0x0000000C -#define DCBS 0x00000010 /* L1 Data Cache Bank Select */ -#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ -#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ - -/* IMEM_CONTROL Register */ -/* ** Bit Positions */ -#define ENIM_P 0x00 /* Enable L1 Code Memory */ -#define IMCTL_ENIM_P 0x00 /* "" (older define) */ -#define ENICPLB_P 0x01 /* Enable ICPLB */ -#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */ -#define IMC_P 0x02 /* Enable */ -#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */ -#define ILOC0_P 0x03 /* Lock Way 0 */ -#define ILOC1_P 0x04 /* Lock Way 1 */ -#define ILOC2_P 0x05 /* Lock Way 2 */ -#define ILOC3_P 0x06 /* Lock Way 3 */ -#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */ - -/* ** Masks */ -#define ENIM 0x00000001 /* Enable L1 Code Memory */ -#define ENICPLB 0x00000002 /* Enable ICPLB */ -#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */ -#define ILOC0 0x00000008 /* Lock Way 0 */ -#define ILOC1 0x00000010 /* Lock Way 1 */ -#define ILOC2 0x00000020 /* Lock Way 2 */ -#define ILOC3 0x00000040 /* Lock Way 3 */ -#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */ - -/* DCPLB_DATA and ICPLB_DATA Registers */ -/* ** Bit Positions */ -#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ - -/* ** Masks */ -#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ -#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ -#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ -#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ -#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ -#define PAGE_SIZE_MASK 0x00030000 /* the bits for the page_size field */ -#define PAGE_SIZE_SHIFT 16 -#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */ -#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ -#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ - -/* ICPLB_DATA only */ -#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ - -/* DCPLB_DATA only */ -#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ -#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ -#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ -#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ - /* 1= allocate cache lines on write-through writes. */ -#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ - -/* ITEST_COMMAND and DTEST_COMMAND Registers */ -/* ** Masks */ -#define TEST_READ 0x00000000 /* Read Access */ -#define TEST_WRITE 0x00000002 /* Write Access */ -#define TEST_TAG 0x00000000 /* Access TAG */ -#define TEST_DATA 0x00000004 /* Access DATA */ -#define TEST_DW0 0x00000000 /* Select Double Word 0 */ -#define TEST_DW1 0x00000008 /* Select Double Word 1 */ -#define TEST_DW2 0x00000010 /* Select Double Word 2 */ -#define TEST_DW3 0x00000018 /* Select Double Word 3 */ -#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */ -#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */ -#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */ -#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */ -#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */ -#define TEST_WAY0 0x00000000 /* Access Way0 */ -#define TEST_WAY1 0x04000000 /* Access Way1 */ - -/* ** ITEST_COMMAND only */ -#define TEST_WAY2 0x08000000 /* Access Way2 */ -#define TEST_WAY3 0x0C000000 /* Access Way3 */ - -/* ** DTEST_COMMAND only */ -#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ -#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/otp.h b/include/asm-blackfin/mach-common/bits/otp.h deleted file mode 100644 index 4e3f1af..0000000 --- a/include/asm-blackfin/mach-common/bits/otp.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * OTP Masks - */ - -#ifndef __BFIN_PERIPHERAL_OTP__ -#define __BFIN_PERIPHERAL_OTP__ - -#ifndef __ASSEMBLY__ - -#include "bootrom.h" - -static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND; -static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ; -static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE; - -#endif - -/* otp_command(): defines for "command" */ -#define OTP_INIT 0x00000001 -#define OTP_CLOSE 0x00000002 - -/* otp_{read,write}(): defines for "flags" */ -#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */ -#define OTP_UPPER_HALF 0x00000001 -#define OTP_NO_ECC 0x00000010 /* do not use ECC */ -#define OTP_LOCK 0x00000020 /* sets page protection bit for page */ -#define OTP_CHECK_FOR_PREV_WRITE 0x00000080 - -/* Return values for all functions */ -#define OTP_SUCCESS 0x00000000 -#define OTP_MASTER_ERROR 0x001 -#define OTP_WRITE_ERROR 0x003 -#define OTP_READ_ERROR 0x005 -#define OTP_ACC_VIO_ERROR 0x009 -#define OTP_DATA_MULT_ERROR 0x011 -#define OTP_ECC_MULT_ERROR 0x021 -#define OTP_PREV_WR_ERROR 0x041 -#define OTP_DATA_SB_WARN 0x100 -#define OTP_ECC_SB_WARN 0x200 - -/* Predefined otp pages: Factory Programmed Settings */ -#define FPS00 0x0004 -#define FPS01 0x0005 -#define FPS02 0x0006 -#define FPS03 0x0007 -#define FPS04 0x0008 -#define FPS05 0x0009 -#define FPS06 0x000A -#define FPS07 0x000B -#define FPS08 0x000C -#define FPS09 0x000D -#define FPS10 0x000E -#define FPS11 0x000F - -/* Predefined otp pages: Customer Programmed Settings */ -#define CPS00 0x0010 -#define CPS01 0x0011 -#define CPS02 0x0012 -#define CPS03 0x0013 -#define CPS04 0x0014 -#define CPS05 0x0015 -#define CPS06 0x0016 -#define CPS07 0x0017 - -/* Predefined otp pages: Pre-Boot Settings */ -#define PBS00 0x0018 -#define PBS01 0x0019 -#define PBS02 0x001A -#define PBS03 0x001B - -#endif diff --git a/include/asm-blackfin/mach-common/bits/pata.h b/include/asm-blackfin/mach-common/bits/pata.h deleted file mode 100644 index 9b61824..0000000 --- a/include/asm-blackfin/mach-common/bits/pata.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * ATAPI Masks - */ - -#ifndef __BFIN_PERIPHERAL_PATA__ -#define __BFIN_PERIPHERAL_PATA__ - -/* Bit masks for ATAPI_CONTROL */ -#define PIO_START 0x1 /* Start PIO/Reg Op */ -#define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define XFER_DIR 0x8 /* Transfer Direction */ -#define IORDY_EN 0x10 /* IORDY Enable */ -#define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define SOFT_RST 0x40 /* Soft Reset */ -#define DEV_RST 0x80 /* Device Reset */ -#define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define END_ON_TERM 0x200 /* End/Terminate Select */ -#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ - -/* Bit masks for ATAPI_STATUS */ -#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ - -/* Bit masks for ATAPI_DEV_ADDR */ -#define DEV_ADDR 0x1f /* Device Address */ - -/* Bit masks for ATAPI_INT_MASK */ -#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ - -/* Bit masks for ATAPI_INT_STATUS */ -#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ - -/* Bit masks for ATAPI_LINE_STATUS */ -#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define ATAPI_ADDR 0x70 /* ATAPI address line status */ -#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ - -/* Bit masks for ATAPI_SM_STATE */ -#define PIO_CSTATE 0xf /* PIO mode state machine current state */ -#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ -#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ -#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ - -/* Bit masks for ATAPI_TERMINATE */ -#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ - -/* Bit masks for ATAPI_REG_TIM_0 */ -#define T2_REG 0xff /* End of cycle time for register access transfers */ -#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ - -/* Bit masks for ATAPI_PIO_TIM_0 */ -#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ -#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ -#define T4_REG 0xf000 /* DIOW data hold */ - -/* Bit masks for ATAPI_PIO_TIM_1 */ -#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ - -/* Bit masks for ATAPI_MULTI_TIM_0 */ -#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ -#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ - -/* Bit masks for ATAPI_MULTI_TIM_1 */ -#define TKW 0xff /* Selects DIOW negated pulsewidth */ -#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ - -/* Bit masks for ATAPI_MULTI_TIM_2 */ -#define TH 0xff /* Selects DIOW data hold */ -#define TEOC 0xff00 /* Selects end of cycle for DMA */ - -/* Bit masks for ATAPI_ULTRA_TIM_0 */ -#define TACK 0xff /* Selects setup and hold times for TACK */ -#define TENV 0xff00 /* Selects envelope time */ - -/* Bit masks for ATAPI_ULTRA_TIM_1 */ -#define TDVS 0xff /* Selects data valid setup time */ -#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ - -/* Bit masks for ATAPI_ULTRA_TIM_2 */ -#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ -#define TMLI 0xff00 /* Selects interlock time */ - -/* Bit masks for ATAPI_ULTRA_TIM_3 */ -#define TZAH 0xff /* Selects minimum delay required for output */ -#define READY_PAUSE 0xff00 /* Selects ready to pause */ - -/* Bit masks for ATAPI_CONTROL */ -#define PIO_START 0x1 /* Start PIO/Reg Op */ -#define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define XFER_DIR 0x8 /* Transfer Direction */ -#define IORDY_EN 0x10 /* IORDY Enable */ -#define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define SOFT_RST 0x40 /* Soft Reset */ -#define DEV_RST 0x80 /* Device Reset */ -#define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define END_ON_TERM 0x200 /* End/Terminate Select */ -#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ - -/* Bit masks for ATAPI_STATUS */ -#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ - -/* Bit masks for ATAPI_DEV_ADDR */ -#define DEV_ADDR 0x1f /* Device Address */ - -/* Bit masks for ATAPI_INT_MASK */ -#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ - -/* Bit masks for ATAPI_INT_STATUS */ -#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ - -/* Bit masks for ATAPI_LINE_STATUS */ -#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define ATAPI_ADDR 0x70 /* ATAPI address line status */ -#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ - -/* Bit masks for ATAPI_SM_STATE */ -#define PIO_CSTATE 0xf /* PIO mode state machine current state */ -#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ -#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ -#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ - -/* Bit masks for ATAPI_TERMINATE */ -#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ - -/* Bit masks for ATAPI_REG_TIM_0 */ -#define T2_REG 0xff /* End of cycle time for register access transfers */ -#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ - -/* Bit masks for ATAPI_PIO_TIM_0 */ -#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ -#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ -#define T4_REG 0xf000 /* DIOW data hold */ - -/* Bit masks for ATAPI_PIO_TIM_1 */ -#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ - -/* Bit masks for ATAPI_MULTI_TIM_0 */ -#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ -#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ - -/* Bit masks for ATAPI_MULTI_TIM_1 */ -#define TKW 0xff /* Selects DIOW negated pulsewidth */ -#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ - -/* Bit masks for ATAPI_MULTI_TIM_2 */ -#define TH 0xff /* Selects DIOW data hold */ -#define TEOC 0xff00 /* Selects end of cycle for DMA */ - -/* Bit masks for ATAPI_ULTRA_TIM_0 */ -#define TACK 0xff /* Selects setup and hold times for TACK */ -#define TENV 0xff00 /* Selects envelope time */ - -/* Bit masks for ATAPI_ULTRA_TIM_1 */ -#define TDVS 0xff /* Selects data valid setup time */ -#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ - -/* Bit masks for ATAPI_ULTRA_TIM_2 */ -#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ -#define TMLI 0xff00 /* Selects interlock time */ - -/* Bit masks for ATAPI_ULTRA_TIM_3 */ -#define TZAH 0xff /* Selects minimum delay required for output */ -#define READY_PAUSE 0xff00 /* Selects ready to pause */ - -#endif /* __BFIN_PERIPHERAL_PATA__ */ diff --git a/include/asm-blackfin/mach-common/bits/pll.h b/include/asm-blackfin/mach-common/bits/pll.h deleted file mode 100644 index 9009f26..0000000 --- a/include/asm-blackfin/mach-common/bits/pll.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * PLL Masks - */ - -#ifndef __BFIN_PERIPHERAL_PLL__ -#define __BFIN_PERIPHERAL_PLL__ - -/* PLL_CTL Masks */ -#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ -#define PLL_OFF 0x0002 /* PLL Not Powered */ -#define STOPCK 0x0008 /* Core Clock Off */ -#define PDWN 0x0020 /* Enter Deep Sleep Mode */ -#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ -#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ -#define BYPASS 0x0100 /* Bypass the PLL */ -#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ -#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */ - -/* PLL_DIV Masks */ -#define SSEL 0x000F /* System Select */ -#define CSEL 0x0030 /* Core Select */ -#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ -#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ -#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ -#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ - -#define CCLK_DIV1 CSEL_DIV1 -#define CCLK_DIV2 CSEL_DIV2 -#define CCLK_DIV4 CSEL_DIV4 -#define CCLK_DIV8 CSEL_DIV8 - -/* PLL_STAT Masks */ -#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ -#define FULL_ON 0x0002 /* Processor In Full On Mode */ -#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ -#define DEEP_SLEEP 0x0008 /* Processor In Deep Sleep Mode */ -#define SLEEP 0x0010 /* Processor In Sleep Mode */ -#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ -#define CORE_IDLE 0x0040 /* Processor In IDLE Mode */ -#define VSTAT 0x0080 /* Voltage Regulator Has Reached Programmed Voltage */ - -/* VR_CTL Masks */ -#ifdef __ADSPBF52x__ -#define FREQ_MASK 0x3000 /* Switching Oscillator Frequency For Regulator */ -#define FREQ_HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ -#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */ -#else -#define FREQ_MASK 0x0003 /* Switching Oscillator Frequency For Regulator */ -#define FREQ_HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ -#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ -#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ -#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ -#endif - -#define GAIN_MASK 0x000C /* Voltage Level Gain */ -#define GAIN_5 0x0000 /* GAIN = 5 */ -#define GAIN_10 0x0004 /* GAIN = 10 */ -#define GAIN_20 0x0008 /* GAIN = 20 */ -#define GAIN_50 0x000C /* GAIN = 50 */ - -#ifdef __ADSPBF52x__ -#define VLEV_MASK 0x00F0 /* Internal Voltage Level */ -#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#else -#define VLEV_MASK 0x00F0 /* Internal Voltage Level */ -#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ -#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ -#endif - -#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ -#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ -#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ -#define GPWE 0x0400 /* General-purpose Wakeup From Hibernate */ -#define MXVRWE 0x0400 /* MXVR Wakeup From Hibernate */ -#define USBWE 0x0800 /* USB Wakeup From Hibernate */ -#define KPADWE 0x1000 /* Keypad Wakeup From Hibernate */ -#define ROTWE 0x2000 /* Rotary Counter Wakeup From Hibernate */ -#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ -#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ports-a.h b/include/asm-blackfin/mach-common/bits/ports-a.h deleted file mode 100644 index 9f78a76..0000000 --- a/include/asm-blackfin/mach-common/bits/ports-a.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Port A Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_A__ -#define __BFIN_PERIPHERAL_PORT_A__ - -#define PA0 (1 << 0) -#define PA1 (1 << 1) -#define PA2 (1 << 2) -#define PA3 (1 << 3) -#define PA4 (1 << 4) -#define PA5 (1 << 5) -#define PA6 (1 << 6) -#define PA7 (1 << 7) -#define PA8 (1 << 8) -#define PA9 (1 << 9) -#define PA10 (1 << 10) -#define PA11 (1 << 11) -#define PA12 (1 << 12) -#define PA13 (1 << 13) -#define PA14 (1 << 14) -#define PA15 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ports-b.h b/include/asm-blackfin/mach-common/bits/ports-b.h deleted file mode 100644 index b81702f..0000000 --- a/include/asm-blackfin/mach-common/bits/ports-b.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Port B Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_B__ -#define __BFIN_PERIPHERAL_PORT_B__ - -#define PB0 (1 << 0) -#define PB1 (1 << 1) -#define PB2 (1 << 2) -#define PB3 (1 << 3) -#define PB4 (1 << 4) -#define PB5 (1 << 5) -#define PB6 (1 << 6) -#define PB7 (1 << 7) -#define PB8 (1 << 8) -#define PB9 (1 << 9) -#define PB10 (1 << 10) -#define PB11 (1 << 11) -#define PB12 (1 << 12) -#define PB13 (1 << 13) -#define PB14 (1 << 14) -#define PB15 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ports-c.h b/include/asm-blackfin/mach-common/bits/ports-c.h deleted file mode 100644 index 3cc665e..0000000 --- a/include/asm-blackfin/mach-common/bits/ports-c.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Port C Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_C__ -#define __BFIN_PERIPHERAL_PORT_C__ - -#define PC0 (1 << 0) -#define PC1 (1 << 1) -#define PC2 (1 << 2) -#define PC3 (1 << 3) -#define PC4 (1 << 4) -#define PC5 (1 << 5) -#define PC6 (1 << 6) -#define PC7 (1 << 7) -#define PC8 (1 << 8) -#define PC9 (1 << 9) -#define PC10 (1 << 10) -#define PC11 (1 << 11) -#define PC12 (1 << 12) -#define PC13 (1 << 13) -#define PC14 (1 << 14) -#define PC15 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ports-d.h b/include/asm-blackfin/mach-common/bits/ports-d.h deleted file mode 100644 index 868c6a0..0000000 --- a/include/asm-blackfin/mach-common/bits/ports-d.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Port D Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_D__ -#define __BFIN_PERIPHERAL_PORT_D__ - -#define PD0 (1 << 0) -#define PD1 (1 << 1) -#define PD2 (1 << 2) -#define PD3 (1 << 3) -#define PD4 (1 << 4) -#define PD5 (1 << 5) -#define PD6 (1 << 6) -#define PD7 (1 << 7) -#define PD8 (1 << 8) -#define PD9 (1 << 9) -#define PD10 (1 << 10) -#define PD11 (1 << 11) -#define PD12 (1 << 12) -#define PD13 (1 << 13) -#define PD14 (1 << 14) -#define PD15 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ports-e.h b/include/asm-blackfin/mach-common/bits/ports-e.h deleted file mode 100644 index c88b0d0..0000000 --- a/include/asm-blackfin/mach-common/bits/ports-e.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Port E Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_E__ -#define __BFIN_PERIPHERAL_PORT_E__ - -#define PE0 (1 << 0) -#define PE1 (1 << 1) -#define PE2 (1 << 2) -#define PE3 (1 << 3) -#define PE4 (1 << 4) -#define PE5 (1 << 5) -#define PE6 (1 << 6) -#define PE7 (1 << 7) -#define PE8 (1 << 8) -#define PE9 (1 << 9) -#define PE10 (1 << 10) -#define PE11 (1 << 11) -#define PE12 (1 << 12) -#define PE13 (1 << 13) -#define PE14 (1 << 14) -#define PE15 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ports-f.h b/include/asm-blackfin/mach-common/bits/ports-f.h deleted file mode 100644 index d6af206..0000000 --- a/include/asm-blackfin/mach-common/bits/ports-f.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Port F Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_F__ -#define __BFIN_PERIPHERAL_PORT_F__ - -#define PF0 (1 << 0) -#define PF1 (1 << 1) -#define PF2 (1 << 2) -#define PF3 (1 << 3) -#define PF4 (1 << 4) -#define PF5 (1 << 5) -#define PF6 (1 << 6) -#define PF7 (1 << 7) -#define PF8 (1 << 8) -#define PF9 (1 << 9) -#define PF10 (1 << 10) -#define PF11 (1 << 11) -#define PF12 (1 << 12) -#define PF13 (1 << 13) -#define PF14 (1 << 14) -#define PF15 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ports-g.h b/include/asm-blackfin/mach-common/bits/ports-g.h deleted file mode 100644 index 09355d3..0000000 --- a/include/asm-blackfin/mach-common/bits/ports-g.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Port G Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_G__ -#define __BFIN_PERIPHERAL_PORT_G__ - -#define PG0 (1 << 0) -#define PG1 (1 << 1) -#define PG2 (1 << 2) -#define PG3 (1 << 3) -#define PG4 (1 << 4) -#define PG5 (1 << 5) -#define PG6 (1 << 6) -#define PG7 (1 << 7) -#define PG8 (1 << 8) -#define PG9 (1 << 9) -#define PG10 (1 << 10) -#define PG11 (1 << 11) -#define PG12 (1 << 12) -#define PG13 (1 << 13) -#define PG14 (1 << 14) -#define PG15 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ports-h.h b/include/asm-blackfin/mach-common/bits/ports-h.h deleted file mode 100644 index fa3910c..0000000 --- a/include/asm-blackfin/mach-common/bits/ports-h.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Port H Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_H__ -#define __BFIN_PERIPHERAL_PORT_H__ - -#define PH0 (1 << 0) -#define PH1 (1 << 1) -#define PH2 (1 << 2) -#define PH3 (1 << 3) -#define PH4 (1 << 4) -#define PH5 (1 << 5) -#define PH6 (1 << 6) -#define PH7 (1 << 7) -#define PH8 (1 << 8) -#define PH9 (1 << 9) -#define PH10 (1 << 10) -#define PH11 (1 << 11) -#define PH12 (1 << 12) -#define PH13 (1 << 13) -#define PH14 (1 << 14) -#define PH15 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ports-i.h b/include/asm-blackfin/mach-common/bits/ports-i.h deleted file mode 100644 index f176f08..0000000 --- a/include/asm-blackfin/mach-common/bits/ports-i.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Port I Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_I__ -#define __BFIN_PERIPHERAL_PORT_I__ - -#define PI0 (1 << 0) -#define PI1 (1 << 1) -#define PI2 (1 << 2) -#define PI3 (1 << 3) -#define PI4 (1 << 4) -#define PI5 (1 << 5) -#define PI6 (1 << 6) -#define PI7 (1 << 7) -#define PI8 (1 << 8) -#define PI9 (1 << 9) -#define PI10 (1 << 10) -#define PI11 (1 << 11) -#define PI12 (1 << 12) -#define PI13 (1 << 13) -#define PI14 (1 << 14) -#define PI15 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ports-j.h b/include/asm-blackfin/mach-common/bits/ports-j.h deleted file mode 100644 index 924123e..0000000 --- a/include/asm-blackfin/mach-common/bits/ports-j.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Port J Masks - */ - -#ifndef __BFIN_PERIPHERAL_PORT_J__ -#define __BFIN_PERIPHERAL_PORT_J__ - -#define PJ0 (1 << 0) -#define PJ1 (1 << 1) -#define PJ2 (1 << 2) -#define PJ3 (1 << 3) -#define PJ4 (1 << 4) -#define PJ5 (1 << 5) -#define PJ6 (1 << 6) -#define PJ7 (1 << 7) -#define PJ8 (1 << 8) -#define PJ9 (1 << 9) -#define PJ10 (1 << 10) -#define PJ11 (1 << 11) -#define PJ12 (1 << 12) -#define PJ13 (1 << 13) -#define PJ14 (1 << 14) -#define PJ15 (1 << 15) - -#endif diff --git a/include/asm-blackfin/mach-common/bits/ppi.h b/include/asm-blackfin/mach-common/bits/ppi.h deleted file mode 100644 index 523f238..0000000 --- a/include/asm-blackfin/mach-common/bits/ppi.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * PPI Masks - */ - -#ifndef __BFIN_PERIPHERAL_PPI__ -#define __BFIN_PERIPHERAL_PPI__ - -/* PPI_CONTROL Masks */ -#define PORT_EN 0x0001 /* PPI Port Enable */ -#define PORT_DIR 0x0002 /* PPI Port Direction */ -#define XFR_TYPE 0x000C /* PPI Transfer Type */ -#define PORT_CFG 0x0030 /* PPI Port Configuration */ -#define FLD_SEL 0x0040 /* PPI Active Field Select */ -#define PACK_EN 0x0080 /* PPI Packing Mode */ -#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x3800 /* PPI Data Length */ -#define DLEN_8 0x0000 /* Data Length = 8 Bits */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - -/* PPI_STATUS Masks */ -#define FLD 0x0400 /* Field Indicator */ -#define FT_ERR 0x0800 /* Frame Track Error */ -#define OVR 0x1000 /* FIFO Overflow Error */ -#define UNDR 0x2000 /* FIFO Underrun Error */ -#define ERR_DET 0x4000 /* Error Detected Indicator */ -#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/rtc.h b/include/asm-blackfin/mach-common/bits/rtc.h deleted file mode 100644 index f5a0cdb..0000000 --- a/include/asm-blackfin/mach-common/bits/rtc.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * RTC Masks - */ - -#ifndef __BFIN_PERIPHERAL_RTC__ -#define __BFIN_PERIPHERAL_RTC__ - -/* RTC_STAT and RTC_ALARM Masks */ -#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */ -#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */ -#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */ -#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */ - -#define RTC_SEC_P 0 -#define RTC_MIN_P 6 -#define RTC_HR_P 12 -#define RTC_DAY_P 17 - -/* - * RTC_ALARM Macro - */ -#define SET_ALARM(day, hr, min, sec) \ - ( (((day) << RTC_DAY_P) & RTC_DAY) | \ - (((hr) << RTC_HR_P ) & RTC_HR ) | \ - (((min) << RTC_MIN_P) & RTC_MIN) | \ - (((sec) << RTC_SEC_P) & RTC_SEC) ) - -/* RTC_ICTL and RTC_ISTAT Masks */ -#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */ -#define ALARM 0x0002 /* Alarm Interrupt Enable */ -#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */ -#define MINUTE 0x0008 /* Minutes Interrupt Enable */ -#define HOUR 0x0010 /* Hours Interrupt Enable */ -#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */ -#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ -#define WRITE_PENDING 0x4000 /* Write Pending Status */ -#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */ - -/* RTC_FAST / RTC_PREN Mask */ -#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/sdh.h b/include/asm-blackfin/mach-common/bits/sdh.h deleted file mode 100644 index 8c5dd33..0000000 --- a/include/asm-blackfin/mach-common/bits/sdh.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * SDH Masks - */ - -#ifndef __BFIN_PERIPHERAL_SDH__ -#define __BFIN_PERIPHERAL_SDH__ - -/* Bit masks for SDH_COMMAND */ -#define CMD_IDX 0x3f /* Command Index */ -#define CMD_RSP 0x40 /* Response */ -#define CMD_L_RSP 0x80 /* Long Response */ -#define CMD_INT_E 0x100 /* Command Interrupt */ -#define CMD_PEND_E 0x200 /* Command Pending */ -#define CMD_E 0x400 /* Command Enable */ - -/* Bit masks for SDH_PWR_CTL */ -#define PWR_ON 0x3 /* Power On */ -#define SD_CMD_OD 0x40 /* Open Drain Output */ -#define ROD_CTL 0x80 /* Rod Control */ - -/* Bit masks for SDH_CLK_CTL */ -#define CLKDIV 0xff /* MC_CLK Divisor */ -#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define PWR_SV_E 0x200 /* Power Save Enable */ -#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ - -/* Bit masks for SDH_RESP_CMD */ -#define RESP_CMD 0x3f /* Response Command */ - -/* Bit masks for SDH_DATA_CTL */ -#define DTX_E 0x1 /* Data Transfer Enable */ -#define DTX_DIR 0x2 /* Data Transfer Direction */ -#define DTX_MODE 0x4 /* Data Transfer Mode */ -#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ - -/* Bit masks for SDH_STATUS */ -#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define CMD_TIME_OUT 0x4 /* CMD Time Out */ -#define DAT_TIME_OUT 0x8 /* Data Time Out */ -#define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define RX_OVERRUN 0x20 /* Receive Overrun */ -#define CMD_RESP_END 0x40 /* CMD Response End */ -#define CMD_SENT 0x80 /* CMD Sent */ -#define DAT_END 0x100 /* Data End */ -#define START_BIT_ERR 0x200 /* Start Bit Error */ -#define DAT_BLK_END 0x400 /* Data Block End */ -#define CMD_ACT 0x800 /* CMD Active */ -#define TX_ACT 0x1000 /* Transmit Active */ -#define RX_ACT 0x2000 /* Receive Active */ -#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ - -/* Bit masks for SDH_STATUS_CLR */ -#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define DAT_END_STAT 0x100 /* Data End Status */ -#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ - -/* Bit masks for SDH_MASK0 */ -#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define DAT_END_MASK 0x100 /* Data End Mask */ -#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ - -/* Bit masks for SDH_FIFO_CNT */ -#define FIFO_COUNT 0x7fff /* FIFO Count */ - -/* Bit masks for SDH_E_STATUS */ -#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define SD_CARD_DET 0x10 /* SD Card Detect */ - -/* Bit masks for SDH_E_MASK */ -#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define SCD_MSK 0x40 /* Mask Card Detect */ - -/* Bit masks for SDH_CFG */ -#define CLKS_EN 0x1 /* Clocks Enable */ -#define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define MWE 0x8 /* Moving Window Enable */ -#define SD_RST 0x10 /* SDMMC Reset */ -#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ - -/* Bit masks for SDH_RD_WAIT_EN */ -#define RWR 0x1 /* Read Wait Request */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/spi.h b/include/asm-blackfin/mach-common/bits/spi.h deleted file mode 100644 index 869dcb0..0000000 --- a/include/asm-blackfin/mach-common/bits/spi.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * SPI Masks - */ - -#ifndef __BFIN_PERIPHERAL_SPI__ -#define __BFIN_PERIPHERAL_SPI__ - -/* SPI_CTL Masks */ -#define TIMOD 0x0003 /* Transfer Initiate Mode */ -#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ -#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ -#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ -#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ -#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ -#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ -#define PSSE 0x0010 /* Slave-Select Input Enable */ -#define EMISO 0x0020 /* Enable MISO As Output */ -#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ -#define LSBF 0x0200 /* LSB First */ -#define CPHA 0x0400 /* Clock Phase */ -#define CPOL 0x0800 /* Clock Polarity */ -#define MSTR 0x1000 /* Master/Slave* */ -#define WOM 0x2000 /* Write Open Drain Master */ -#define SPE 0x4000 /* SPI Enable */ - -/* SPI_FLG Masks */ -#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_FLG Bit Positions */ -#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_STAT Masks */ -#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ -#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ -#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ -#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ -#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ -#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ -#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/sport.h b/include/asm-blackfin/mach-common/bits/sport.h deleted file mode 100644 index 88e7a5d..0000000 --- a/include/asm-blackfin/mach-common/bits/sport.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * SPORT Masks - */ - -#ifndef __BFIN_PERIPHERAL_SPORT__ -#define __BFIN_PERIPHERAL_SPORT__ - -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F /* TX Word Length */ -#define TXSE 0x0100 /* TX Secondary Enable */ -#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /* TX Right-First Data Order */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F /* RX Word Length */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 /* RX FIFO Not Empty Status */ -#define RUVF 0x0002 /* RX Underflow Status */ -#define ROVF 0x0004 /* RX Overflow Status */ -#define TXF 0x0008 /* TX FIFO Full Status */ -#define TUVF 0x0010 /* TX Underflow Status */ -#define TOVF 0x0020 /* TX Overflow Status */ -#define TXHRE 0x0040 /* TX Hold Register Empty */ - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0xF000 /* Multichannel Window Size Field */ -#define WOFF 0x03FF /* Multichannel Window Offset Field */ - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */ -#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ -#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ -#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ -#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD 0xF000 /* Multichannel Frame Delay */ -#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ -#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ -#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ -#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ -#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ -#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ -#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ -#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ -#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ -#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ -#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ -#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ -#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ -#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ -#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ -#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/timer.h b/include/asm-blackfin/mach-common/bits/timer.h deleted file mode 100644 index 9513f80..0000000 --- a/include/asm-blackfin/mach-common/bits/timer.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * General Purpose Timer Masks - */ - -#ifndef __BFIN_PERIPHERAL_TIMER__ -#define __BFIN_PERIPHERAL_TIMER__ - -/* TIMER_ENABLE Masks */ -#define TIMEN0 0x0001 /* Enable Timer 0 */ -#define TIMEN1 0x0002 /* Enable Timer 1 */ -#define TIMEN2 0x0004 /* Enable Timer 2 */ -#define TIMEN3 0x0008 /* Enable Timer 3 */ -#define TIMEN4 0x0010 /* Enable Timer 4 */ -#define TIMEN5 0x0020 /* Enable Timer 5 */ -#define TIMEN6 0x0040 /* Enable Timer 6 */ -#define TIMEN7 0x0080 /* Enable Timer 7 */ - -/* TIMER_DISABLE Masks */ -#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ -#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ -#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ -#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ -#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ -#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ -#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ -#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ - -/* TIMER_STATUS Masks */ -#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ -#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ -#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ -#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ -#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ -#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ -#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ -#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ -#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ -#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ -#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ -#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ -#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ -#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ -#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ -#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ -#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ -#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ -#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR3 TOVF_ERR3 -#define TOVL_ERR4 TOVF_ERR4 -#define TOVL_ERR5 TOVF_ERR5 -#define TOVL_ERR6 TOVF_ERR6 -#define TOVL_ERR7 TOVF_ERR7 - -/* TIMERx_CONFIG Masks */ -#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ -#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ -#define EXT_CLK 0x0003 /* External Clock Mode */ -#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ -#define PERIOD_CNT 0x0008 /* Period Count */ -#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ -#define TIN_SEL 0x0020 /* Timer Input Select */ -#define OUT_DIS 0x0040 /* Output Pad Disable */ -#define CLK_SEL 0x0080 /* Timer Clock Select */ -#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ -#define EMU_RUN 0x0200 /* Emulation Behavior Select */ -#define ERR_TYP 0xC000 /* Error Type */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/trace.h b/include/asm-blackfin/mach-common/bits/trace.h deleted file mode 100644 index 13e2134..0000000 --- a/include/asm-blackfin/mach-common/bits/trace.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Trace Unit Masks - */ - -#ifndef __BFIN_PERIPHERAL_TRACE__ -#define __BFIN_PERIPHERAL_TRACE__ - -/* Trace Buffer Control (TBUFCTL) Register Masks */ -#define TBUFPWR 0x00000001 -#define TBUFEN 0x00000002 -#define TBUFOVF 0x00000004 -#define CMPLB_SINGLE 0x00000008 -#define CMPLP_DOUBLE 0x00000010 -#define CMPLB (CMPLB_SINGLE | CMPLP_DOUBLE) - -/* Trace Buffer Status (TBUFSTAT) Register Masks */ -#define TBUFCNT 0x0000001F - -#endif diff --git a/include/asm-blackfin/mach-common/bits/twi.h b/include/asm-blackfin/mach-common/bits/twi.h deleted file mode 100644 index 8fa7d9f..0000000 --- a/include/asm-blackfin/mach-common/bits/twi.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * TWI Masks - */ - -#ifndef __BFIN_PERIPHERAL_TWI__ -#define __BFIN_PERIPHERAL_TWI__ - -/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ -#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ -#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ - -/* TWI_PRESCALE Masks */ -#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ -#define TWI_ENA 0x0080 /* TWI Enable */ -#define SCCB 0x0200 /* SCCB Compatibility Enable */ - -/* TWI_SLAVE_CTL Masks */ -#define SEN 0x0001 /* Slave Enable */ -#define SADD_LEN 0x0002 /* Slave Address Length */ -#define STDVAL 0x0004 /* Slave Transmit Data Valid */ -#define TSC_NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ -#define GEN 0x0010 /* General Call Adrress Matching Enabled */ - -/* TWI_SLAVE_STAT Masks */ -#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ -#define GCALL 0x0002 /* General Call Indicator */ - -/* TWI_MASTER_CTRL Masks */ -#define MEN 0x0001 /* Master Mode Enable */ -#define MADD_LEN 0x0002 /* Master Address Length */ -#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ -#define FAST 0x0008 /* Use Fast Mode Timing Specs */ -#define STOP 0x0010 /* Issue Stop Condition */ -#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ -#define DCNT 0x3FC0 /* Data Bytes To Transfer */ -#define SDAOVR 0x4000 /* Serial Data Override */ -#define SCLOVR 0x8000 /* Serial Clock Override */ - -/* TWI_MASTER_STAT Masks */ -#define MPROG 0x0001 /* Master Transfer In Progress */ -#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ -#define ANAK 0x0004 /* Address Not Acknowledged */ -#define DNAK 0x0008 /* Data Not Acknowledged */ -#define BUFRDERR 0x0010 /* Buffer Read Error */ -#define BUFWRERR 0x0020 /* Buffer Write Error */ -#define SDASEN 0x0040 /* Serial Data Sense */ -#define SCLSEN 0x0080 /* Serial Clock Sense */ -#define BUSBUSY 0x0100 /* Bus Busy Indicator */ - -/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ -#define SINIT 0x0001 /* Slave Transfer Initiated */ -#define SCOMP 0x0002 /* Slave Transfer Complete */ -#define SERR 0x0004 /* Slave Transfer Error */ -#define SOVF 0x0008 /* Slave Overflow */ -#define MCOMP 0x0010 /* Master Transfer Complete */ -#define MERR 0x0020 /* Master Transfer Error */ -#define XMTSERV 0x0040 /* Transmit FIFO Service */ -#define RCVSERV 0x0080 /* Receive FIFO Service */ - -/* TWI_FIFO_CTRL Masks */ -#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ -#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ -#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ -#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ - -/* TWI_FIFO_STAT Masks */ -#define XMTSTAT 0x0003 /* Transmit FIFO Status */ -#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ -#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ -#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ - -#define RCVSTAT 0x000C /* Receive FIFO Status */ -#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ -#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ -#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/uart.h b/include/asm-blackfin/mach-common/bits/uart.h deleted file mode 100644 index ac1ba11..0000000 --- a/include/asm-blackfin/mach-common/bits/uart.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * UART Masks - */ - -#ifndef __BFIN_PERIPHERAL_UART__ -#define __BFIN_PERIPHERAL_UART__ - -/* UARTx_LCR Masks */ -#define WLS 0x03 /* Word Length Select */ -#define WLS_5 0x00 /* 5 bit word */ -#define WLS_6 0x01 /* 6 bit word */ -#define WLS_7 0x02 /* 7 bit word */ -#define WLS_8 0x03 /* 8 bit word */ -#define STB 0x04 /* Stop Bits */ -#define PEN 0x08 /* Parity Enable */ -#define EPS 0x10 /* Even Parity Select */ -#define STP 0x20 /* Stick Parity */ -#define SB 0x40 /* Set Break */ -#define DLAB 0x80 /* Divisor Latch Access */ - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UARTx_MCR Mask */ -#define XOFF 0x01 /* Transmitter off */ -#define MRTS 0x02 /* Manual Request to Send */ -#define RFIT 0x04 /* Receive FIFO IRQ Threshold */ -#define RFRT 0x08 /* Receive FIFO RTS Threshold */ -#define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define FCPOL 0x20 /* Flow Control Pin Polarity */ -#define ARTS 0x40 /* Auto RTS generation for RX handshake */ -#define ACTS 0x80 /* Auto CTS operation for TX handshake */ - -#define XOFF_P 0 -#define MRTS_P 1 -#define RFIT_P 2 -#define RFRT_P 3 -#define LOOP_ENA_P 4 -#define FCPOL_P 5 -#define ARTS_P 6 -#define ACTS_P 7 - -/* UARTx_LSR Masks */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* THR Empty */ -#define TEMT 0x40 /* TSR and UART_THR Empty */ - -#define DR_P 0x00 -#define OE_P 0x01 -#define PE_P 0x02 -#define FE_P 0x03 -#define BI_P 0x04 -#define THRE_P 0x05 -#define TEMT_P 0x06 - -/* UARTx_IER Masks */ -#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ -#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ -#define ELSI 0x04 /* Enable RX Status Interrupt */ - -#define ERBFI_P 0x00 -#define ETBEI_P 0x01 -#define ELSI_P 0x02 - -/* UARTx_IIR Masks */ -#define NINT 0x01 /* Pending Interrupt */ -#define STATUS 0x06 /* Highest Priority Pending Interrupt */ - -#define NINT_P 0x00 -#define STATUS_P0 0x01 -#define STATUS_P1 0x02 - -/* UARTx_GCTL Masks */ -#define UCEN 0x01 /* Enable UARTx Clocks */ -#define IREN 0x02 /* Enable IrDA Mode */ -#define TPOLC 0x04 /* IrDA TX Polarity Change */ -#define RPOLC 0x08 /* IrDA RX Polarity Change */ -#define FPE 0x10 /* Force Parity Error On Transmit */ -#define FFE 0x20 /* Force Framing Error On Transmit */ - -#define UCEN_P 0x00 -#define IREN_P 0x01 -#define TPOLC_P 0x02 -#define RPOLC_P 0x03 -#define FPE_P 0x04 -#define FFE_P 0x05 - -#endif diff --git a/include/asm-blackfin/mach-common/bits/usb.h b/include/asm-blackfin/mach-common/bits/usb.h deleted file mode 100644 index c639058..0000000 --- a/include/asm-blackfin/mach-common/bits/usb.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * USB Masks - */ - -#ifndef __BFIN_PERIPHERAL_USB__ -#define __BFIN_PERIPHERAL_USB__ - -/* Bit masks for USB_FADDR */ - -#define FUNCTION_ADDRESS 0x7f /* Function address */ - -/* Bit masks for USB_POWER */ - -#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define RESUME_MODE 0x4 /* DMA Mode */ -#define RESET 0x8 /* Reset indicator */ -#define HS_MODE 0x10 /* High Speed mode indicator */ -#define HS_ENABLE 0x20 /* high Speed Enable */ -#define SOFT_CONN 0x40 /* Soft connect */ -#define ISO_UPDATE 0x80 /* Isochronous update */ - -/* Bit masks for USB_INTRTX */ - -#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ - -/* Bit masks for USB_INTRRX */ - -#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ - -/* Bit masks for USB_INTRTXE */ - -#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt enable */ -#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt enable */ -#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt enable */ -#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt enable */ -#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt enable */ -#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt enable */ -#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt enable */ - -/* Bit masks for USB_INTRRXE */ - -#define EP1_RX_E 0x02 /* Rx Endpoint 1 interrupt enable */ -#define EP2_RX_E 0x04 /* Rx Endpoint 2 interrupt enable */ -#define EP3_RX_E 0x08 /* Rx Endpoint 3 interrupt enable */ -#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt enable */ -#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt enable */ -#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt enable */ -#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt enable */ - -/* Bit masks for USB_INTRUSB */ - -#define SUSPEND_B 0x01 /* Suspend indicator */ -#define RESUME_B 0x02 /* Resume indicator */ -#define RESET_OR_BABLE_B 0x04 /* Reset/babble indicator */ -#define SOF_B 0x08 /* Start of frame */ -#define CONN_B 0x10 /* Connection indicator */ -#define DISCON_B 0x20 /* Disconnect indicator */ -#define SESSION_REQ_B 0x40 /* Session Request */ -#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ - -/* Bit masks for USB_INTRUSBE */ - -#define SUSPEND_BE 0x01 /* Suspend indicator int enable */ -#define RESUME_BE 0x02 /* Resume indicator int enable */ -#define RESET_OR_BABLE_BE 0x04 /* Reset/babble indicator int enable */ -#define SOF_BE 0x08 /* Start of frame int enable */ -#define CONN_BE 0x10 /* Connection indicator int enable */ -#define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ - -/* Bit masks for USB_FRAME */ - -#define FRAME_NUMBER 0x7ff /* Frame number */ - -/* Bit masks for USB_INDEX */ - -#define SELECTED_ENDPOINT 0xf /* selected endpoint */ - -/* Bit masks for USB_GLOBAL_CTL */ - -#define GLOBAL_ENA 0x0001 /* enables USB module */ -#define EP1_TX_ENA 0x0002 /* Transmit endpoint 1 enable */ -#define EP2_TX_ENA 0x0004 /* Transmit endpoint 2 enable */ -#define EP3_TX_ENA 0x0008 /* Transmit endpoint 3 enable */ -#define EP4_TX_ENA 0x0010 /* Transmit endpoint 4 enable */ -#define EP5_TX_ENA 0x0020 /* Transmit endpoint 5 enable */ -#define EP6_TX_ENA 0x0040 /* Transmit endpoint 6 enable */ -#define EP7_TX_ENA 0x0080 /* Transmit endpoint 7 enable */ -#define EP1_RX_ENA 0x0100 /* Receive endpoint 1 enable */ -#define EP2_RX_ENA 0x0200 /* Receive endpoint 2 enable */ -#define EP3_RX_ENA 0x0400 /* Receive endpoint 3 enable */ -#define EP4_RX_ENA 0x0800 /* Receive endpoint 4 enable */ -#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ - -/* Bit masks for USB_OTG_DEV_CTL */ - -#define SESSION 0x1 /* session indicator */ -#define HOST_REQ 0x2 /* Host negotiation request */ -#define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define VBUS0 0x8 /* Vbus level indicator[0] */ -#define VBUS1 0x10 /* Vbus level indicator[1] */ -#define LSDEV 0x20 /* Low-speed indicator */ -#define FSDEV 0x40 /* Full or High-speed indicator */ -#define B_DEVICE 0x80 /* A' or 'B' device indicator */ - -/* Bit masks for USB_OTG_VBUS_IRQ */ - -#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ - -/* Bit masks for USB_OTG_VBUS_MASK */ - -#define DRIVE_VBUS_ON_ENA 0x01 /* enable DRIVE_VBUS_ON interrupt */ -#define DRIVE_VBUS_OFF_ENA 0x02 /* enable DRIVE_VBUS_OFF interrupt */ -#define CHRG_VBUS_START_ENA 0x04 /* enable CHRG_VBUS_START interrupt */ -#define CHRG_VBUS_END_ENA 0x08 /* enable CHRG_VBUS_END interrupt */ -#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ - -/* Bit masks for USB_CSR0 */ - -#define RXPKTRDY 0x1 /* data packet receive indicator */ -#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define STALL_SENT 0x4 /* STALL handshake sent */ -#define DATAEND 0x8 /* Data end indicator */ -#define SETUPEND 0x10 /* Setup end */ -#define SENDSTALL 0x20 /* Send STALL handshake */ -#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define ERROR_H 0x10 /* timeout error indicator host mode */ -#define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ - -/* Bit masks for USB_COUNT0 */ - -#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ - -/* Bit masks for USB_NAKLIMIT0 */ - -#define EP0_NAK_LIMIT 0x1f /* frames/micro frames count after which EP0 timeouts */ - -/* Bit masks for USB_TX_MAX_PACKET */ - -#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ - -/* Bit masks for USB_RX_MAX_PACKET */ - -#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ - -/* Bit masks for USB_TXCSR */ - -#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define ISO_T 0x4000 /* enable Isochronous transfers */ -#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define ERROR_TH 0x4 /* error condition host mode */ -#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ - -/* Bit masks for USB_TXCOUNT */ - -#define TX_COUNT 0x1fff /* Byte len for the selected endpoint Tx FIFO */ - -/* Bit masks for USB_RXCSR */ - -#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define ISO_R 0x4000 /* enable Isochronous transfers */ -#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define INCOMPRX_RH 0x100 /* large packet is split host mode */ -#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ - -/* Bit masks for USB_RXCOUNT */ - -#define RX_COUNT 0x1fff /* Packet byte len in the Rx FIFO */ - -/* Bit masks for USB_TXTYPE */ - -#define TARGET_EP_NO_T 0xf /* EP number */ -#define PROTOCOL_T 0xc /* transfer type */ - -/* Bit masks for USB_TXINTERVAL */ - -#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ - -/* Bit masks for USB_RXTYPE */ - -#define TARGET_EP_NO_R 0xf /* EP number */ -#define PROTOCOL_R 0xc /* transfer type */ - -/* Bit masks for USB_RXINTERVAL */ - -#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ - -/* Bit masks for USB_DMA_INTERRUPT */ - -#define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define DMA7_INT 0x80 /* DMA7 pending interrupt */ - -/* Bit masks for USB_DMAxCONTROL */ - -#define DMA_ENA 0x1 /* DMA enable */ -#define DIRECTION 0x2 /* direction of DMA transfer */ -#define MODE 0x4 /* DMA Bus error */ -#define INT_ENA 0x8 /* Interrupt enable */ -#define EPNUM 0xf0 /* EP number */ -#define BUSERROR 0x100 /* DMA Bus error */ - -#endif diff --git a/include/asm-blackfin/mach-common/bits/watchdog.h b/include/asm-blackfin/mach-common/bits/watchdog.h deleted file mode 100644 index 75924f9..0000000 --- a/include/asm-blackfin/mach-common/bits/watchdog.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Watchdog Masks - */ - -#ifndef __BFIN_PERIPHERAL_WATCHDOG__ -#define __BFIN_PERIPHERAL_WATCHDOG__ - -/* Watchdog Timer WDOG_CTL Register Masks */ - -#define WDEV 0x0006 /* event generated on roll over */ -#define WDEV_RESET 0x0000 /* generate reset event on roll over */ -#define WDEV_NMI 0x0002 /* generate NMI event on roll over */ -#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ -#define WDEV_NONE 0x0006 /* no event on roll over */ -#define WDEN 0x0FF0 /* enable watchdog */ -#define WDDIS 0x0AD0 /* disable watchdog */ -#define WDRO 0x8000 /* watchdog rolled over latch */ - -#endif diff --git a/include/asm-blackfin/mem_map.h b/include/asm-blackfin/mem_map.h deleted file mode 100644 index 3e361d6..0000000 --- a/include/asm-blackfin/mem_map.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Common Blackfin memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MEM_MAP_H__ -#define __BFIN_MEM_MAP_H__ - -/* Every Blackfin so far has MMRs like this */ -#ifndef COREMMR_BASE -# define COREMMR_BASE 0xFFE00000 -#endif -#ifndef SYSMMR_BASE -# define SYSMMR_BASE 0xFFC00000 -#endif - -/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ -#ifndef L1_SRAM_SCRATCH -# define L1_SRAM_SCRATCH 0xFFB00000 -# define L1_SRAM_SCRATCH_SIZE 0x1000 -# define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#endif - -#endif diff --git a/include/asm-blackfin/net.h b/include/asm-blackfin/net.h deleted file mode 100644 index 97cb466..0000000 --- a/include/asm-blackfin/net.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * net.h - misc Blackfin network helpers - * - * Copyright (c) 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BFIN_RAND_MAC__ -#define __ASM_BFIN_RAND_MAC__ - -/* If the board does not have a real MAC assigned to it, then generate a - * locally administrated pseudo-random one based on CYCLES and compile date. - */ -static inline void bfin_gen_rand_mac(uchar *mac_addr) -{ - /* make something up */ - const char s[] = __DATE__; - size_t i; - u32 cycles; - for (i = 0; i < 6; ++i) { - asm("%0 = CYCLES;" : "=r" (cycles)); - mac_addr[i] = cycles ^ s[i]; - } - mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */ -} - -#endif diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h deleted file mode 100644 index 000ffe5..0000000 --- a/include/asm-blackfin/posix_types.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * U-boot - posix_types.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H -#define __ARCH_BLACKFIN_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned int __kernel_ipc_pid_t; -typedef unsigned int __kernel_uid_t; -typedef unsigned int __kernel_gid_t; -typedef unsigned long __kernel_size_t; -typedef long __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef int __kernel_daddr_t; -typedef char *__kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#define BOOL_WAS_DEFINED -typedef enum { false = 0, true = 1 } bool; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { - int val[2]; -} __kernel_fsid_t; - -#if defined(__KERNEL__) - -#undef __FD_SET -#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) - -#undef __FD_CLR -#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) - -#undef __FD_ISSET -#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) - -#endif /* defined(__KERNEL__) */ - -#endif diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h deleted file mode 100644 index d700cce..0000000 --- a/include/asm-blackfin/processor.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * U-boot - processor.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * include/asm-m68k/processor.h - * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN - * Copyright (C) 1995 Hamish Macdonald - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __ASM_BLACKFIN_PROCESSOR_H -#define __ASM_BLACKFIN_PROCESSOR_H - -/* Stub to make stupid common code happy */ - -#endif diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h deleted file mode 100644 index 251d5e6..0000000 --- a/include/asm-blackfin/ptrace.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_PTRACE_H -#define _BFIN_PTRACE_H - -/* - * GCC defines register number like this: - * ----------------------------- - * 0 - 7 are data registers R0-R7 - * 8 - 15 are address registers P0-P7 - * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3 - * 32 - 33 A registers A0 & A1 - * 34 - status register - * ----------------------------- - * - * We follows above, except: - * 32-33 --- Low 32-bit of A0&1 - * 34-35 --- High 8-bit of A0&1 - */ - -#ifndef __ASSEMBLY__ - -struct task_struct; - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long orig_pc; - long ipend; - long seqstat; - long rete; - long retn; - long retx; - long pc; /* PC == RETI */ - long rets; - long reserved; /* Used as scratch during system calls */ - long astat; - long lb1; - long lb0; - long lt1; - long lt0; - long lc1; - long lc0; - long a1w; - long a1x; - long a0w; - long a0x; - long b3; - long b2; - long b1; - long b0; - long l3; - long l2; - long l1; - long l0; - long m3; - long m2; - long m1; - long m0; - long i3; - long i2; - long i1; - long i0; - long usp; - long fp; - long p5; - long p4; - long p3; - long p2; - long p1; - long p0; - long r7; - long r6; - long r5; - long r4; - long r3; - long r2; - long r1; - long r0; - long orig_r0; - long orig_p0; - long syscfg; -}; - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 /* ptrace signal */ - -#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ -#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ -#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ - -#define PS_S (0x0002) - -#ifdef __KERNEL__ - -/* user_mode returns true if only one bit is set in IPEND, other than the - master interrupt enable. */ -#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1))) -#define instruction_pointer(regs) ((regs)->pc) -#define user_stack_pointer(regs) ((regs)->usp) -#define profile_pc(regs) instruction_pointer(regs) -extern void show_regs(struct pt_regs *); - -#define arch_has_single_step() (1) -extern void user_enable_single_step(struct task_struct *); -/* see arch/blackfin/kernel/ptrace.c about this redirect */ -#define user_disable_single_step(child) ptrace_disable(child) - -/* - * Get the address of the live pt_regs for the specified task. - * These are saved onto the top kernel stack when the process - * is not running. - * - * Note: if a user thread is execve'd from kernel space, the - * kernel stack will not be empty on entry to the kernel, so - * ptracing these tasks will fail. - */ -#define task_pt_regs(task) \ - (struct pt_regs *) \ - ((unsigned long)task_stack_page(task) + \ - (THREAD_SIZE - sizeof(struct pt_regs))) - -#endif /* __KERNEL__ */ - -#endif /* __ASSEMBLY__ */ - -/* - * Offsets used by 'ptrace' system call interface. - */ - -#define PT_R0 204 -#define PT_R1 200 -#define PT_R2 196 -#define PT_R3 192 -#define PT_R4 188 -#define PT_R5 184 -#define PT_R6 180 -#define PT_R7 176 -#define PT_P0 172 -#define PT_P1 168 -#define PT_P2 164 -#define PT_P3 160 -#define PT_P4 156 -#define PT_P5 152 -#define PT_FP 148 -#define PT_USP 144 -#define PT_I0 140 -#define PT_I1 136 -#define PT_I2 132 -#define PT_I3 128 -#define PT_M0 124 -#define PT_M1 120 -#define PT_M2 116 -#define PT_M3 112 -#define PT_L0 108 -#define PT_L1 104 -#define PT_L2 100 -#define PT_L3 96 -#define PT_B0 92 -#define PT_B1 88 -#define PT_B2 84 -#define PT_B3 80 -#define PT_A0X 76 -#define PT_A0W 72 -#define PT_A1X 68 -#define PT_A1W 64 -#define PT_LC0 60 -#define PT_LC1 56 -#define PT_LT0 52 -#define PT_LT1 48 -#define PT_LB0 44 -#define PT_LB1 40 -#define PT_ASTAT 36 -#define PT_RESERVED 32 -#define PT_RETS 28 -#define PT_PC 24 -#define PT_RETX 20 -#define PT_RETN 16 -#define PT_RETE 12 -#define PT_SEQSTAT 8 -#define PT_IPEND 4 - -#define PT_ORIG_R0 208 -#define PT_ORIG_P0 212 -#define PT_SYSCFG 216 -#define PT_TEXT_ADDR 220 -#define PT_TEXT_END_ADDR 224 -#define PT_DATA_ADDR 228 -#define PT_FDPIC_EXEC 232 -#define PT_FDPIC_INTERP 236 - -#endif /* _BFIN_PTRACE_H */ diff --git a/include/asm-blackfin/sdh.h b/include/asm-blackfin/sdh.h deleted file mode 100644 index 2c2f63e..0000000 --- a/include/asm-blackfin/sdh.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * sdh.h, export bfin_mmc_init - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_SDH_H__ -#define __ASM_SDH_H__ - -#include -#include - -int bfin_mmc_init(bd_t *bis); - -#endif diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h deleted file mode 100644 index 2ac8990..0000000 --- a/include/asm-blackfin/shared_resources.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * U-boot - setup.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _SHARED_RESOURCES_H_ -#define _SHARED_RESOURCES_H_ - -void swap_to(int device_id); - -#define FLASH 0 -#define ETHERNET 1 - -#endif /* _SHARED_RESOURCES_H_ */ diff --git a/include/asm-blackfin/signal.h b/include/asm-blackfin/signal.h deleted file mode 100644 index 7b1573c..0000000 --- a/include/asm-blackfin/signal.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h deleted file mode 100644 index 117f44c..0000000 --- a/include/asm-blackfin/string.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * U-boot - string.h String functions - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* Changed by Lineo Inc. May 2001 */ - -#ifndef _BLACKFINNOMMU_STRING_H_ -#define _BLACKFINNOMMU_STRING_H_ - -#ifdef __KERNEL__ /* only set these up for kernel code */ - -#define __HAVE_ARCH_STRCPY -#define __HAVE_ARCH_STRNCPY -#define __HAVE_ARCH_STRCMP -#define __HAVE_ARCH_STRNCMP -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMCMP -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_MEMMOVE - -extern char *strcpy(char *dest, const char *src); -extern char *strncpy(char *dest, const char *src, size_t n); -extern int strcmp(const char *cs, const char *ct); -extern int strncmp(const char *cs, const char *ct, size_t count); -extern void *memcpy(void *dest, const void *src, size_t count); -extern void *memset(void *s, int c, size_t count); -extern int memcmp(const void *, const void *, size_t); -extern void *memmove(void *dest, const void *src, size_t count); - -#else /* KERNEL */ - -/* - * let user libraries deal with these, - * IMHO the kernel has no place defining these functions for user apps - */ - -#define __HAVE_ARCH_STRCPY 1 -#define __HAVE_ARCH_STRNCPY 1 -#define __HAVE_ARCH_STRCAT 1 -#define __HAVE_ARCH_STRNCAT 1 -#define __HAVE_ARCH_STRCMP 1 -#define __HAVE_ARCH_STRNCMP 1 -#define __HAVE_ARCH_STRNICMP 1 -#define __HAVE_ARCH_STRCHR 1 -#define __HAVE_ARCH_STRRCHR 1 -#define __HAVE_ARCH_STRSTR 1 -#define __HAVE_ARCH_STRLEN 1 -#define __HAVE_ARCH_STRNLEN 1 -#define __HAVE_ARCH_MEMSET 1 -#define __HAVE_ARCH_MEMCPY 1 -#define __HAVE_ARCH_MEMMOVE 1 -#define __HAVE_ARCH_MEMSCAN 1 -#define __HAVE_ARCH_MEMCMP 1 -#define __HAVE_ARCH_MEMCHR 1 -#define __HAVE_ARCH_STRTOK 1 - -#endif /* KERNEL */ - -#endif /* _BLACKFIN_STRING_H_ */ diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h deleted file mode 100644 index 6bc7208..0000000 --- a/include/asm-blackfin/system.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * U-boot - system.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BLACKFIN_SYSTEM_H -#define _BLACKFIN_SYSTEM_H - -/* - * Interrupt configuring macros. - */ - -extern int irq_flags; - -#define local_irq_enable() \ - __asm__ __volatile__ ( \ - "sti %0;" \ - : \ - : "d" (irq_flags) \ - ) - -#define local_irq_disable() \ - do { \ - int __tmp_dummy; \ - __asm__ __volatile__ ( \ - "cli %0;" \ - : "=d" (__tmp_dummy) \ - ); \ - } while (0) - -# define local_irq_save(x) \ - __asm__ __volatile__ ( \ - "cli %0;" \ - : "=&d" (x) \ - ) - -#define local_save_flags(x) \ - __asm__ __volatile__ ( \ - "cli %0;" \ - "sti %0;" \ - : "=d" (x) \ - ) - -#define irqs_enabled_from_flags(x) ((x) != 0x1f) - -#define local_irq_restore(x) \ - do { \ - if (irqs_enabled_from_flags(x)) \ - local_irq_enable(); \ - } while (0) - -/* - * Force strict CPU ordering. - */ -#define nop() asm volatile ("nop;\n\t"::) -#define mb() asm volatile ("" : : :"memory") -#define rmb() asm volatile ("" : : :"memory") -#define wmb() asm volatile ("" : : :"memory") -#define set_rmb(var, value) do { xchg(&var, value); } while (0) -#define set_mb(var, value) set_rmb(var, value) -#define set_wmb(var, value) do { var = value; wmb(); } while (0) - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) - -struct __xchg_dummy { - unsigned long a[100]; -}; -#define __xg(x) ((volatile struct __xchg_dummy *)(x)) - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, - int size) -{ - unsigned long tmp = 0; - unsigned long flags = 0; - - local_irq_save(flags); - - switch (size) { - case 1: - __asm__ __volatile__ - ("%0 = b%2 (z);\n\t" - "b%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 2: - __asm__ __volatile__ - ("%0 = w%2 (z);\n\t" - "w%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 4: - __asm__ __volatile__ - ("%0 = %2;\n\t" - "%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - } - local_irq_restore(flags); - return tmp; -} - -#endif /* _BLACKFIN_SYSTEM_H */ diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h deleted file mode 100644 index 7422d3d..0000000 --- a/include/asm-blackfin/traps.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2001 Lineo, Inc - * Tony Kou - * 1993 Hamish Macdonald - * - * Licensed under the GPL-2 - */ - -#ifndef _BFIN_TRAPS_H -#define _BFIN_TRAPS_H - -#define VEC_SYS (0) -#define VEC_EXCPT01 (1) -#define VEC_EXCPT02 (2) -#define VEC_EXCPT03 (3) -#define VEC_EXCPT04 (4) -#define VEC_EXCPT05 (5) -#define VEC_EXCPT06 (6) -#define VEC_EXCPT07 (7) -#define VEC_EXCPT08 (8) -#define VEC_EXCPT09 (9) -#define VEC_EXCPT10 (10) -#define VEC_EXCPT11 (11) -#define VEC_EXCPT12 (12) -#define VEC_EXCPT13 (13) -#define VEC_EXCPT14 (14) -#define VEC_EXCPT15 (15) -#define VEC_STEP (16) -#define VEC_OVFLOW (17) -#define VEC_UNDEF_I (33) -#define VEC_ILGAL_I (34) -#define VEC_CPLB_VL (35) -#define VEC_MISALI_D (36) -#define VEC_UNCOV (37) -#define VEC_CPLB_M (38) -#define VEC_CPLB_MHIT (39) -#define VEC_WATCH (40) -#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */ -#define VEC_MISALI_I (42) -#define VEC_CPLB_I_VL (43) -#define VEC_CPLB_I_M (44) -#define VEC_CPLB_I_MHIT (45) -#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ -/* The hardware reserves (63) for future use - we use it to tell our - * normal exception handling code we have a hardware error - */ -#define VEC_HWERR (63) - -#endif /* _BFIN_TRAPS_H */ diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h deleted file mode 100644 index 2160ba0..0000000 --- a/include/asm-blackfin/types.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * U-boot - types.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _BLACKFIN_TYPES_H -#define _BLACKFIN_TYPES_H - -/* - * This file is never included by application software unless - * explicitly requested (e.g., via linux/types.h) in which case the - * application is Linux specific so (user-) name space pollution is - * not a major issue. However, for interoperability, libraries still - * need to be careful to avoid a name clashes. - */ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -/* HK0617 -- Changes to unsigned long temporarily */ -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif - -#endif diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h deleted file mode 100644 index a6e6cf0f..0000000 --- a/include/asm-blackfin/u-boot.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * U-boot - u-boot.h Structure declarations for board specific data - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _U_BOOT_H_ -#define _U_BOOT_H_ 1 - -typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned long bi_boot_params; /* where this board expects params */ - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - const char *bi_r_version; - const char *bi_cpu; - const char *bi_board_name; - unsigned long bi_vco; - unsigned long bi_cclk; - unsigned long bi_sclk; -} bd_t; - -#endif /* _U_BOOT_H_ */ diff --git a/include/asm-blackfin/unaligned.h b/include/asm-blackfin/unaligned.h deleted file mode 100644 index 6cecbbb..0000000 --- a/include/asm-blackfin/unaligned.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h deleted file mode 100644 index c7a38f2..0000000 --- a/include/asm-i386/bitops.h +++ /dev/null @@ -1,384 +0,0 @@ -#ifndef _I386_BITOPS_H -#define _I386_BITOPS_H - -/* - * Copyright 1992, Linus Torvalds. - */ - - -/* - * These have to be done with inline assembly: that way the bit-setting - * is guaranteed to be atomic. All bit operations return 0 if the bit - * was cleared before the operation and != 0 if it was not. - * - * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). - */ - -#ifdef CONFIG_SMP -#define LOCK_PREFIX "lock ; " -#else -#define LOCK_PREFIX "" -#endif - -#define ADDR (*(volatile long *) addr) - -/** - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static __inline__ void set_bit(int nr, volatile void * addr) -{ - __asm__ __volatile__( LOCK_PREFIX - "btsl %1,%0" - :"=m" (ADDR) - :"Ir" (nr)); -} - -/** - * __set_bit - Set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike set_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static __inline__ void __set_bit(int nr, volatile void * addr) -{ - __asm__( - "btsl %1,%0" - :"=m" (ADDR) - :"Ir" (nr)); -} - -/** - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() - * in order to ensure changes are visible on other processors. - */ -static __inline__ void clear_bit(int nr, volatile void * addr) -{ - __asm__ __volatile__( LOCK_PREFIX - "btrl %1,%0" - :"=m" (ADDR) - :"Ir" (nr)); -} -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -/** - * __change_bit - Toggle a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike change_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static __inline__ void __change_bit(int nr, volatile void * addr) -{ - __asm__ __volatile__( - "btcl %1,%0" - :"=m" (ADDR) - :"Ir" (nr)); -} - -/** - * change_bit - Toggle a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static __inline__ void change_bit(int nr, volatile void * addr) -{ - __asm__ __volatile__( LOCK_PREFIX - "btcl %1,%0" - :"=m" (ADDR) - :"Ir" (nr)); -} - -/** - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static __inline__ int test_and_set_bit(int nr, volatile void * addr) -{ - int oldbit; - - __asm__ __volatile__( LOCK_PREFIX - "btsl %2,%1\n\tsbbl %0,%0" - :"=r" (oldbit),"=m" (ADDR) - :"Ir" (nr) : "memory"); - return oldbit; -} - -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static __inline__ int __test_and_set_bit(int nr, volatile void * addr) -{ - int oldbit; - - __asm__( - "btsl %2,%1\n\tsbbl %0,%0" - :"=r" (oldbit),"=m" (ADDR) - :"Ir" (nr)); - return oldbit; -} - -/** - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static __inline__ int test_and_clear_bit(int nr, volatile void * addr) -{ - int oldbit; - - __asm__ __volatile__( LOCK_PREFIX - "btrl %2,%1\n\tsbbl %0,%0" - :"=r" (oldbit),"=m" (ADDR) - :"Ir" (nr) : "memory"); - return oldbit; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static __inline__ int __test_and_clear_bit(int nr, volatile void * addr) -{ - int oldbit; - - __asm__( - "btrl %2,%1\n\tsbbl %0,%0" - :"=r" (oldbit),"=m" (ADDR) - :"Ir" (nr)); - return oldbit; -} - -/* WARNING: non atomic and it can be reordered! */ -static __inline__ int __test_and_change_bit(int nr, volatile void * addr) -{ - int oldbit; - - __asm__ __volatile__( - "btcl %2,%1\n\tsbbl %0,%0" - :"=r" (oldbit),"=m" (ADDR) - :"Ir" (nr) : "memory"); - return oldbit; -} - -/** - * test_and_change_bit - Change a bit and return its new value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static __inline__ int test_and_change_bit(int nr, volatile void * addr) -{ - int oldbit; - - __asm__ __volatile__( LOCK_PREFIX - "btcl %2,%1\n\tsbbl %0,%0" - :"=r" (oldbit),"=m" (ADDR) - :"Ir" (nr) : "memory"); - return oldbit; -} - -#if 0 /* Fool kernel-doc since it doesn't do macros yet */ -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static int test_bit(int nr, const volatile void * addr); -#endif - -static __inline__ int constant_test_bit(int nr, const volatile void * addr) -{ - return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; -} - -static __inline__ int variable_test_bit(int nr, volatile void * addr) -{ - int oldbit; - - __asm__ __volatile__( - "btl %2,%1\n\tsbbl %0,%0" - :"=r" (oldbit) - :"m" (ADDR),"Ir" (nr)); - return oldbit; -} - -#define test_bit(nr,addr) \ -(__builtin_constant_p(nr) ? \ - constant_test_bit((nr),(addr)) : \ - variable_test_bit((nr),(addr))) - -/** - * find_first_zero_bit - find the first zero bit in a memory region - * @addr: The address to start the search at - * @size: The maximum size to search - * - * Returns the bit-number of the first zero bit, not the number of the byte - * containing a bit. - */ -static __inline__ int find_first_zero_bit(void * addr, unsigned size) -{ - int d0, d1, d2; - int res; - - if (!size) - return 0; - /* This looks at memory. Mark it volatile to tell gcc not to move it around */ - __asm__ __volatile__( - "movl $-1,%%eax\n\t" - "xorl %%edx,%%edx\n\t" - "repe; scasl\n\t" - "je 1f\n\t" - "xorl -4(%%edi),%%eax\n\t" - "subl $4,%%edi\n\t" - "bsfl %%eax,%%edx\n" - "1:\tsubl %%ebx,%%edi\n\t" - "shll $3,%%edi\n\t" - "addl %%edi,%%edx" - :"=d" (res), "=&c" (d0), "=&D" (d1), "=&a" (d2) - :"1" ((size + 31) >> 5), "2" (addr), "b" (addr)); - return res; -} - -/** - * find_next_zero_bit - find the first zero bit in a memory region - * @addr: The address to base the search on - * @offset: The bitnumber to start searching at - * @size: The maximum size to search - */ -static __inline__ int find_next_zero_bit (void * addr, int size, int offset) -{ - unsigned long * p = ((unsigned long *) addr) + (offset >> 5); - int set = 0, bit = offset & 31, res; - - if (bit) { - /* - * Look for zero in first byte - */ - __asm__("bsfl %1,%0\n\t" - "jne 1f\n\t" - "movl $32, %0\n" - "1:" - : "=r" (set) - : "r" (~(*p >> bit))); - if (set < (32 - bit)) - return set + offset; - set = 32 - bit; - p++; - } - /* - * No zero yet, search remaining full bytes for a zero - */ - res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr)); - return (offset + set + res); -} - -/** - * ffz - find first zero in word. - * @word: The word to search - * - * Undefined if no zero exists, so code should check against ~0UL first. - */ -static __inline__ unsigned long ffz(unsigned long word) -{ - __asm__("bsfl %1,%0" - :"=r" (word) - :"r" (~word)); - return word; -} - -#ifdef __KERNEL__ - -/** - * ffs - find first bit set - * @x: the word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -static __inline__ int ffs(int x) -{ - int r; - - __asm__("bsfl %1,%0\n\t" - "jnz 1f\n\t" - "movl $-1,%0\n" - "1:" : "=r" (r) : "g" (x)); - return r+1; -} -#define PLATFORM_FFS - -/** - * hweightN - returns the hamming weight of a N-bit word - * @x: the word to weigh - * - * The Hamming Weight of a number is the total number of bits set in it. - */ - -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) - -#endif /* __KERNEL__ */ - -#ifdef __KERNEL__ - -#define ext2_set_bit __test_and_set_bit -#define ext2_clear_bit __test_and_clear_bit -#define ext2_test_bit test_bit -#define ext2_find_first_zero_bit find_first_zero_bit -#define ext2_find_next_zero_bit find_next_zero_bit - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) __test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) __set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) __test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -#endif /* __KERNEL__ */ - -#endif /* _I386_BITOPS_H */ diff --git a/include/asm-i386/byteorder.h b/include/asm-i386/byteorder.h deleted file mode 100644 index 7dfeb8b..0000000 --- a/include/asm-i386/byteorder.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef _I386_BYTEORDER_H -#define _I386_BYTEORDER_H - -#include - -#ifdef __GNUC__ - - -static __inline__ __u32 ___arch__swab32(__u32 x) -{ -#ifdef CONFIG_X86_BSWAP - __asm__("bswap %0" : "=r" (x) : "0" (x)); -#else - __asm__("xchgb %b0,%h0\n\t" /* swap lower bytes */ - "rorl $16,%0\n\t" /* swap words */ - "xchgb %b0,%h0" /* swap higher bytes */ - :"=q" (x) - : "0" (x)); -#endif - return x; -} - -static __inline__ __u16 ___arch__swab16(__u16 x) -{ - __asm__("xchgb %b0,%h0" /* swap bytes */ \ - : "=q" (x) \ - : "0" (x)); \ - return x; -} - -#define __arch__swab32(x) ___arch__swab32(x) -#define __arch__swab16(x) ___arch__swab16(x) - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#include - -#endif /* _I386_BYTEORDER_H */ diff --git a/include/asm-i386/config.h b/include/asm-i386/config.h deleted file mode 100644 index 049c44e..0000000 --- a/include/asm-i386/config.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -#endif diff --git a/include/asm-i386/errno.h b/include/asm-i386/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/include/asm-i386/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h deleted file mode 100644 index 3abbf1d..0000000 --- a/include/asm-i386/global_data.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long have_console; /* serial_init() was called */ - unsigned long reloc_off; /* Relocation Offset */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long bus_clk; - phys_size_t ram_size; /* RAM size */ - unsigned long reset_status; /* reset status register at boot */ - void **jt; /* jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -extern gd_t *gd; - -#define DECLARE_GLOBAL_DATA_PTR - -#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-i386/i8254.h b/include/asm-i386/i8254.h deleted file mode 100644 index aafdfb8..0000000 --- a/include/asm-i386/i8254.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -/* i8254.h Intel 8254 PIT registers */ - - -#ifndef _ASMI386_I8254_H_ -#define _ASMI386_I8954_H_ 1 - - -#define PIT_T0 0x00 /* PIT channel 0 count/status */ -#define PIT_T1 0x01 /* PIT channel 1 count/status */ -#define PIT_T2 0x02 /* PIT channel 2 count/status */ -#define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */ - -/* PIT Command Register Bit Definitions */ - -#define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */ -#define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */ -#define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */ - -#define PIT_CMD_LATCH 0x00 /* Counter Latch Command */ -#define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */ -#define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */ -#define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */ - -#define PIT_CMD_MODE0 0x00 /* Select mode 0 */ -#define PIT_CMD_MODE1 0x02 /* Select mode 1 */ -#define PIT_CMD_MODE2 0x04 /* Select mode 2 */ -#define PIT_CMD_MODE3 0x06 /* Select mode 3 */ -#define PIT_CMD_MODE4 0x08 /* Select mode 4 */ -#define PIT_CMD_MODE5 0x0A /* Select mode 5 */ - -#endif diff --git a/include/asm-i386/i8259.h b/include/asm-i386/i8259.h deleted file mode 100644 index 774d7a3..0000000 --- a/include/asm-i386/i8259.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* i8259.h i8259 PIC Registers */ - -#ifndef _ASMI386_I8259_H_ -#define _ASMI386_I8959_H_ 1 - - -/* PIC I/O mapped registers */ - -#define IRR 0x0 /* Interrupt Request Register */ -#define ISR 0x0 /* In-Service Register */ -#define ICW1 0x0 /* Initialization Control Word 1 */ -#define OCW2 0x0 /* Operation Control Word 2 */ -#define OCW3 0x0 /* Operation Control Word 3 */ -#define ICW2 0x1 /* Initialization Control Word 2 */ -#define ICW3 0x1 /* Initialization Control Word 3 */ -#define ICW4 0x1 /* Initialization Control Word 4 */ -#define IMR 0x1 /* Interrupt Mask Register */ - -/* bits for IRR, IMR, ISR and ICW3 */ -#define IR7 0x80 /* IR7 */ -#define IR6 0x40 /* IR6 */ -#define IR5 0x20 /* IR5 */ -#define IR4 0x10 /* IR4 */ -#define IR3 0x08 /* IR3 */ -#define IR2 0x04 /* IR2 */ -#define IR1 0x02 /* IR1 */ -#define IR0 0x01 /* IR0 */ - -/* bits for SEOI */ -#define SEOI_IR7 0x07 /* IR7 */ -#define SEOI_IR6 0x06 /* IR6 */ -#define SEOI_IR5 0x05 /* IR5 */ -#define SEOI_IR4 0x04 /* IR4 */ -#define SEOI_IR3 0x03 /* IR3 */ -#define SEOI_IR2 0x02 /* IR2 */ -#define SEOI_IR1 0x01 /* IR1 */ -#define SEOI_IR0 0x00 /* IR0 */ - -/* OCW2 bits */ -#define OCW2_RCLR 0x00 /* Rotate/clear */ -#define OCW2_NEOI 0x20 /* Non specific EOI */ -#define OCW2_NOP 0x40 /* NOP */ -#define OCW2_SEOI 0x60 /* Specific EOI */ -#define OCW2_RSET 0x80 /* Rotate/set */ -#define OCW2_REOI 0xA0 /* Rotate on non specific EOI */ -#define OCW2_PSET 0xC0 /* Priority Set Command */ -#define OCW2_RSEOI 0xE0 /* Rotate on specific EOI */ - -/* ICW1 bits */ -#define ICW1_SEL 0x10 /* Select ICW1 */ -#define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */ -#define ICW1_ADI 0x04 /* Address Interval */ -#define ICW1_SNGL 0x02 /* Single PIC */ -#define ICW1_EICW4 0x01 /* Expect initilization ICW4 */ - -/* ICW2 is the starting vector number */ - -/* ICW2 is bit-mask of present slaves for a master device, - * or the slave ID for a slave device */ - -/* ICW4 bits */ -#define ICW4_AEOI 0x02 /* Automatic EOI Mode */ -#define ICW4_PM 0x01 /* Microprocessor Mode */ - -#endif diff --git a/include/asm-i386/ibmpc.h b/include/asm-i386/ibmpc.h deleted file mode 100644 index e35cbd8..0000000 --- a/include/asm-i386/ibmpc.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_IBMPC_H_ -#define __ASM_IBMPC_H_ 1 - -/* misc ports in an ibm compatible pc */ - -#define MASTER_PIC 0x20 -#define PIT_BASE 0x40 -#define KBDDATA 0x60 -#define SYSCTLB 0x62 -#define KBDCMD 0x64 -#define SYSCTLA 0x92 -#define SLAVE_PIC 0xa0 - -#if 1 -#define UART0_BASE 0x3f8 -#define UART1_BASE 0x2f8 -#else -/* FixMe: uarts swapped */ -#define UART0_BASE 0x2f8 -#define UART1_BASE 0x3f8 -#endif - - -#endif diff --git a/include/asm-i386/ic/pci.h b/include/asm-i386/ic/pci.h deleted file mode 100644 index bcccdbe..0000000 --- a/include/asm-i386/ic/pci.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_IC_SC520_PCI_H_ -#define _ASM_IC_SC520_PCI_H_ 1 - -/* pin number used for PCI interrupt mappings */ -#define SC520_PCI_INTA 0 -#define SC520_PCI_INTB 1 -#define SC520_PCI_INTC 2 -#define SC520_PCI_INTD 3 -#define SC520_PCI_GPIRQ0 4 -#define SC520_PCI_GPIRQ1 5 -#define SC520_PCI_GPIRQ2 6 -#define SC520_PCI_GPIRQ3 7 -#define SC520_PCI_GPIRQ4 8 -#define SC520_PCI_GPIRQ5 9 -#define SC520_PCI_GPIRQ6 10 -#define SC520_PCI_GPIRQ7 11 -#define SC520_PCI_GPIRQ8 12 -#define SC520_PCI_GPIRQ9 13 -#define SC520_PCI_GPIRQ10 14 - -extern int sc520_pci_ints[]; - -void pci_sc520_init(struct pci_controller *hose); -int pci_sc520_set_irq(int pci_pin, int irq); - -#endif diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h deleted file mode 100644 index 57c9904..0000000 --- a/include/asm-i386/ic/sc520.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_IC_SC520_H_ -#define _ASM_IC_SC520_H_ 1 - -#ifndef __ASSEMBLY__ - -void init_sc520(void); -unsigned long init_sc520_dram(void); - -/* Memory mapped configuration registers */ -typedef struct sc520_mmcr { - u16 revid; /* ElanSC520 microcontroller revision id */ - u8 cpuctl; /* am5x86 CPU control */ - - u8 pad_0x003[0x0d]; - - u8 drcctl; /* SDRAM control */ - u8 pad_0x011[0x01]; - u8 drctmctl; /* SDRAM timing control */ - u8 pad_0x013[0x01]; - u16 drccfg; /* SDRAM bank configuration*/ - u8 pad_0x016[0x02]; - u32 drcbendadr; /* SDRAM bank 0-3 ending address*/ - u8 pad_0x01c[0x04]; - u8 eccctl; /* ECC control */ - u8 eccsta; /* ECC status */ - u8 eccckbpos; /* ECC check bit position */ - u8 ecccktest; /* ECC Check Code Test */ - u32 eccsbadd; /* ECC single-bit error address */ - u32 eccmbadd; /* ECC multi-bit error address */ - - u8 pad_0x02c[0x14]; - - u8 dbctl; /* SDRAM buffer control */ - - u8 pad_0x041[0x0f]; - - u16 bootcsctl; /* /BOOTCS control */ - u8 pad_0x052[0x02]; - u16 romcs1ctl; /* /ROMCS1 control */ - u16 romcs2ctl; /* /ROMCS2 control */ - - u8 pad_0x058[0x08]; - - u16 hbctl; /* host bridge control */ - u16 hbtgtirqctl; /* host bridge target interrupt control */ - u16 hbtgtirqsta; /* host bridge target interrupt status */ - u16 hbmstirqctl; /* host bridge target interrupt control */ - u16 hbmstirqsta; /* host bridge master interrupt status */ - u8 pad_0x06a[0x02]; - u32 mstintadd; /* host bridge master interrupt address */ - - u8 sysarbctl; /* system arbiter control */ - u8 pciarbsta; /* PCI bus arbiter status */ - u16 sysarbmenb; /* system arbiter master enable */ - u32 arbprictl; /* arbiter priority control */ - - u8 pad_0x078[0x08]; - - u8 adddecctl; /* address decode control */ - u8 pad_0x081[0x01]; - u16 wpvsta; /* write-protect violation status */ - u8 pad_0x084[0x04]; - u32 par[16]; /* programmable address regions */ - - u8 pad_0x0c8[0x0b38]; - - u8 gpecho; /* GP echo mode */ - u8 gpcsdw; /* GP chip select data width */ - u16 gpcsqual; /* GP chip select qualification */ - u8 pad_0xc04[0x4]; - u8 gpcsrt; /* GP chip select recovery time */ - u8 gpcspw; /* GP chip select pulse width */ - u8 gpcsoff; /* GP chip select offset */ - u8 gprdw; /* GP read pulse width */ - u8 gprdoff; /* GP read offset */ - u8 gpwrw; /* GP write pulse width */ - u8 gpwroff; /* GP write offset */ - u8 gpalew; /* GP ale pulse width */ - u8 gpaleoff; /* GP ale offset */ - - u8 pad_0xc11[0x0f]; - - u16 piopfs15_0; /* PIO15-PIO0 pin function select */ - u16 piopfs31_16; /* PIO31-PIO16 pin function select */ - u8 cspfs; /* chip select pin function select */ - u8 pad_0xc25[0x01]; - u8 clksel; /* clock select */ - u8 pad_0xc27[0x01]; - u16 dsctl; /* drive strength control */ - u16 piodir15_0; /* PIO15-PIO0 direction */ - u16 piodir31_16; /* PIO31-PIO16 direction */ - u8 pad_0xc2e[0x02]; - u16 piodata15_0 ; /* PIO15-PIO0 data */ - u16 piodata31_16; /* PIO31-PIO16 data */ - u16 pioset15_0; /* PIO15-PIO0 set */ - u16 pioset31_16; /* PIO31-PIO16 set */ - u16 pioclr15_0; /* PIO15-PIO0 clear */ - u16 pioclr31_16; /* PIO31-PIO16 clear */ - - u8 pad_0xc3c[0x24]; - - u16 swtmrmilli; /* software timer millisecond count */ - u16 swtmrmicro; /* software timer microsecond count */ - u8 swtmrcfg; /* software timer configuration */ - - u8 pad_0xc65[0x0b]; - - u8 gptmrsta; /* GP timers status register */ - u8 pad_0xc71; - u16 gptmr0ctl; /* GP timer 0 mode/control */ - u16 gptmr0cnt; /* GP timer 0 count */ - u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */ - u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */ - u16 gptmr1ctl; /* GP timer 1 mode/control */ - u16 gptmr1cnt; /* GP timer 1 count */ - u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */ - u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/ - u16 gptmr2ctl; /* GP timer 2 mode/control */ - u16 gptmr2cnt; /* GP timer 2 count */ - u8 pad_0xc86[0x08]; - u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */ - - u8 pad_0xc90[0x20]; - - u16 wdtmrctl; /* watchdog timer control */ - u16 wdtmrcntl; /* watchdog timer count low */ - u16 wdtmrcnth; /* watchdog timer count high */ - - u8 pad_0xcb6[0x0a]; - - u8 uart1ctl; /* UART 1 general control */ - u8 uart1sta; /* UART 1 general status */ - u8 uart1fcrshad; /* UART 1 FIFO control shadow */ - u8 pad_0xcc3[0x01]; - u8 uart2ctl; /* UART 2 general control */ - u8 uart2sta; /* UART 2 general status */ - u8 uart2fcrshad; /* UART 2 FIFO control shadow */ - - u8 pad_0xcc7[0x09]; - - u8 ssictl; /* SSI control */ - u8 ssixmit; /* SSI transmit */ - u8 ssicmd; /* SSI command */ - u8 ssista; /* SSI status */ - u8 ssircv; /* SSI receive */ - - u8 pad_0xcd5[0x2b]; - - u8 picicr; /* interrupt control */ - u8 pad_0xd01[0x01]; - u8 pic_mode[3]; /* PIC interrupt mode */ - u8 pad_0xd05[0x03]; - u16 swint16_1; /* software interrupt 16-1 control */ - u8 swint22_17; /* software interrupt 22-17/NMI control */ - u8 pad_0xd0b[0x05]; - u16 intpinpol; /* interrupt pin polarity */ - u8 pad_0xd12[0x02]; - u16 pcihostmap; /* PCI host bridge interrupt mapping */ - u8 pad_0xd16[0x02]; - u16 eccmap; /* ECC interrupt mapping */ - u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */ - u8 pad_0xd1d[0x03]; - u8 pit_int_map[3]; /* PIT interrupt mapping */ - u8 pad_0xd23[0x05]; - u8 uart_int_map[2]; /* UART interrupt mapping */ - u8 pad_0xd2a[0x06]; - u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/ - u8 pad_0xd34[0x0c]; - u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */ - u8 ssimap; /* SSI interrupt mapping register */ - u8 wdtmap; /* watchdog timer interrupt mapping */ - u8 rtcmap; /* RTC interrupt mapping register */ - u8 wpvmap; /* write-protect interrupt mapping */ - u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */ - u8 ferrmap; /* floating point error interrupt mapping */ - u8 pad_0xd47[0x09]; - u8 gp_int_map[11]; /* GP IRQ interrupt mapping */ - - u8 pad_0xd5b[0x15]; - - u8 sysinfo; /* system board information */ - u8 pad_0xd71[0x01]; - u8 rescfg; /* reset configuration */ - u8 pad_0xd73[0x01]; - u8 ressta; /* reset status */ - - u8 pad_0xd75[0x0b]; - - u8 gpdmactl; /* GP-DMA Control */ - u8 gpdmammio; /* GP-DMA memory-mapped I/O */ - u16 gpdmaextchmapa; /* GP-DMA resource channel map a */ - u16 gpdmaextchmapb; /* GP-DMA resource channel map b */ - u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */ - u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */ - u8 pad_0xd8d[0x03]; - u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */ - u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */ - u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */ - u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */ - u8 pad_0xd94[0x4]; - u8 gpdmabcctl; /* buffer chaining control */ - u8 gpdmabcsta; /* buffer chaining status */ - u8 gpdmabsintenb; /* buffer chaining interrupt enable */ - u8 gpdmabcval; /* buffer chaining valid */ - u8 pad_0xd9c[0x04]; - u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */ - u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */ - u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */ - u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */ - u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */ - u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */ - u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */ - u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */ - u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */ - u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */ - u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */ - u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */ - u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */ - u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */ - u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */ - u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */ - - u8 pad_0xdc0[0x0240]; -} sc520_mmcr_t; - -extern volatile sc520_mmcr_t *sc520_mmcr; - -#endif - -/* MMCR Offsets (required for assembler code */ -#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ -#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ -#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ -#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ -#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ - -/* MMCR Register bits (not all of them :) ) */ - -/* SSI Stuff */ -#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */ -#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */ -#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */ -#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */ -#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */ -#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */ -#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */ -#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */ - -#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */ -#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */ -#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */ -#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */ - -#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */ -#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */ -#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */ -#define SSISTA_BSY 0x02 /* SSI Busy */ -#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ - -/* BITS for SC520_ADDDECCTL: */ -#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ -#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ -#define RTC_DIS 0x04 /* RTC Disable */ -#define UART2_DIS 0x02 /* UART2 Disable */ -#define UART1_DIS 0x01 /* UART1 Disable */ - -/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */ -#define SC520_REG_ADDR 0x00000cf8 -#define SC520_REG_DATA 0x00000cfc - -#define SC520_ISA_MEM_PHYS 0x00000000 -#define SC520_ISA_MEM_BUS 0x00000000 -#define SC520_ISA_MEM_SIZE 0x01000000 - -#define SC520_ISA_IO_PHYS 0x00000000 -#define SC520_ISA_IO_BUS 0x00000000 -#define SC520_ISA_IO_SIZE 0x00001000 - -/* PCI I/O space from 0x1000 to 0xdfff - * (make 0xe000-0xfdff available for stuff like PCCard boot) */ -#define SC520_PCI_IO_PHYS 0x00001000 -#define SC520_PCI_IO_BUS 0x00001000 -#define SC520_PCI_IO_SIZE 0x0000d000 - -/* system memory from 0x00000000 to 0x0fffffff */ -#define SC520_PCI_MEMORY_PHYS 0x00000000 -#define SC520_PCI_MEMORY_BUS 0x00000000 -#define SC520_PCI_MEMORY_SIZE 0x10000000 - -/* PCI bus memory from 0x10000000 to 0x26ffffff - * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */ -#define SC520_PCI_MEM_PHYS 0x10000000 -#define SC520_PCI_MEM_BUS 0x10000000 -#define SC520_PCI_MEM_SIZE 0x17000000 - -/* 0x28000000 - 0x3fffffff is used by the flash banks */ - -/* 0x40000000 - 0xffffffff is not adressable by the SC520 */ - -/* priority numbers used for interrupt channel mappings */ -#define SC520_IRQ_DISABLED 0 -#define SC520_IRQ0 1 -#define SC520_IRQ1 2 -#define SC520_IRQ2 4 /* same as IRQ9 */ -#define SC520_IRQ3 11 -#define SC520_IRQ4 12 -#define SC520_IRQ5 13 -#define SC520_IRQ6 21 -#define SC520_IRQ7 22 -#define SC520_IRQ8 3 -#define SC520_IRQ9 4 -#define SC520_IRQ10 5 -#define SC520_IRQ11 6 -#define SC520_IRQ12 7 -#define SC520_IRQ13 8 -#define SC520_IRQ14 9 -#define SC520_IRQ15 10 - -#endif diff --git a/include/asm-i386/ic/ssi.h b/include/asm-i386/ic/ssi.h deleted file mode 100644 index bd48eab..0000000 --- a/include/asm-i386/ic/ssi.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2008 - * Graeme Russ . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_IC_SSI_H_ -#define _ASM_IC_SSI_H_ 1 - -int ssi_set_interface(int, int, int, int); -void ssi_chip_select(int); -u8 ssi_txrx_byte(u8); -void ssi_tx_byte(u8); -u8 ssi_rx_byte(void); - - -#endif diff --git a/include/asm-i386/interrupt.h b/include/asm-i386/interrupt.h deleted file mode 100644 index 8d324d9..0000000 --- a/include/asm-i386/interrupt.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2009 - * Graeme Russ, graeme.russ@gmail.com - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_INTERRUPT_H_ -#define __ASM_INTERRUPT_H_ 1 - -/* cpu/i386/interrupts.c */ -void set_vector(u8 intnum, void *routine); - -/* arch/i386/lib/interupts.c */ -void disable_irq(int irq); -void enable_irq(int irq); - -/* Architecture specific functions */ -void mask_irq(int irq); -void unmask_irq(int irq); -void specific_eoi(int irq); - -extern char exception_stack[]; - -#define __isr__ void __attribute__ ((regparm(0))) - -#endif diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h deleted file mode 100644 index 9b757d4..0000000 --- a/include/asm-i386/io.h +++ /dev/null @@ -1,237 +0,0 @@ -#ifndef _ASM_IO_H -#define _ASM_IO_H - -/* - * This file contains the definitions for the x86 IO instructions - * inb/inw/inl/outb/outw/outl and the "string versions" of the same - * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" - * versions of the single-IO instructions (inb_p/inw_p/..). - * - * This file is not meant to be obfuscating: it's just complicated - * to (a) handle it all in a way that makes gcc able to optimize it - * as well as possible and (b) trying to avoid writing the same thing - * over and over again with slight variations and possibly making a - * mistake somewhere. - */ - -/* - * Thanks to James van Artsdalen for a better timing-fix than - * the two short jumps: using outb's to a nonexistent port seems - * to guarantee better timings even on fast machines. - * - * On the other hand, I'd like to be sure of a non-existent port: - * I feel a bit unsafe about using 0x80 (should be safe, though) - * - * Linus - */ - - /* - * Bit simplified and optimized by Jan Hubicka - * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. - * - * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, - * isa_read[wl] and isa_write[wl] fixed - * - Arnaldo Carvalho de Melo - */ - -#define IO_SPACE_LIMIT 0xffff - - -#ifdef __KERNEL__ - - -/* - * readX/writeX() are used to access memory mapped devices. On some - * architectures the memory mapped IO stuff needs to be accessed - * differently. On the x86 architecture, we just read/write the - * memory location directly. - */ - -#define readb(addr) (*(volatile unsigned char *) (addr)) -#define readw(addr) (*(volatile unsigned short *) (addr)) -#define readl(addr) (*(volatile unsigned int *) (addr)) -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl - -#define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b)) -#define writew(b,addr) (*(volatile unsigned short *) (addr) = (b)) -#define writel(b,addr) (*(volatile unsigned int *) (addr) = (b)) -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel - -#define memset_io(a,b,c) memset((a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(b),(c)) -#define memcpy_toio(a,b,c) memcpy((a),(b),(c)) - -/* - * ISA space is 'always mapped' on a typical x86 system, no need to - * explicitly ioremap() it. The fact that the ISA IO space is mapped - * to PAGE_OFFSET is pure coincidence - it does not mean ISA values - * are physical addresses. The following constant pointer can be - * used as the IO-area pointer (it can be iounmapped as well, so the - * analogy with PCI is quite large): - */ -#define isa_readb(a) readb((a)) -#define isa_readw(a) readw((a)) -#define isa_readl(a) readl((a)) -#define isa_writeb(b,a) writeb(b,(a)) -#define isa_writew(w,a) writew(w,(a)) -#define isa_writel(l,a) writel(l,(a)) -#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) -#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) - - -static inline int check_signature(unsigned long io_addr, - const unsigned char *signature, int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -/** - * isa_check_signature - find BIOS signatures - * @io_addr: mmio address to check - * @signature: signature block - * @length: length of signature - * - * Perform a signature comparison with the ISA mmio address io_addr. - * Returns 1 on a match. - * - * This function is deprecated. New drivers should use ioremap and - * check_signature. - */ - - -static inline int isa_check_signature(unsigned long io_addr, - const unsigned char *signature, int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#endif /* __KERNEL__ */ - -#ifdef SLOW_IO_BY_JUMPING -#define __SLOW_DOWN_IO "\njmp 1f\n1:\tjmp 1f\n1:" -#else -#define __SLOW_DOWN_IO "\noutb %%al,$0x80" -#endif - -#ifdef REALLY_SLOW_IO -#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO -#else -#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO -#endif - - -/* - * Talk about misusing macros.. - */ -#define __OUT1(s,x) \ -static inline void out##s(unsigned x value, unsigned short port) { - -#define __OUT2(s,s1,s2) \ -__asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1" - - -#define __OUT(s,s1,x) \ -__OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \ -__OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));} - -#define __IN1(s) \ -static inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v; - -#define __IN2(s,s1,s2) \ -__asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0" - -#define __IN(s,s1,i...) \ -__IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \ -__IN1(s##_p) __IN2(s,s1,"w") __FULL_SLOW_DOWN_IO : "=a" (_v) : "Nd" (port) ,##i ); return _v; } - -#define __INS(s) \ -static inline void ins##s(unsigned short port, void * addr, unsigned long count) \ -{ __asm__ __volatile__ ("rep ; ins" #s \ -: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); } - -#define __OUTS(s) \ -static inline void outs##s(unsigned short port, const void * addr, unsigned long count) \ -{ __asm__ __volatile__ ("rep ; outs" #s \ -: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); } - -#define RETURN_TYPE unsigned char -__IN(b,"") -#undef RETURN_TYPE -#define RETURN_TYPE unsigned short -__IN(w,"") -#undef RETURN_TYPE -#define RETURN_TYPE unsigned int -__IN(l,"") -#undef RETURN_TYPE - -__OUT(b,"b",char) -__OUT(w,"w",short) -__OUT(l,,int) - -__INS(b) -__INS(w) -__INS(l) - -__OUTS(b) -__OUTS(w) -__OUTS(l) - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -#endif diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h deleted file mode 100644 index 050a2bb..0000000 --- a/include/asm-i386/pci.h +++ /dev/null @@ -1,34 +0,0 @@ - - -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PCI_I386_H_ -#define _PCI_I386_H_ 1 - -void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); -int pci_enable_legacy_video_ports(struct pci_controller* hose); -int pci_shadow_rom(pci_dev_t dev, unsigned char *dest); -void pci_remove_rom_window(struct pci_controller* hose, u32 addr); -u32 pci_get_rom_window(struct pci_controller* hose, int size); -#endif diff --git a/include/asm-i386/posix_types.h b/include/asm-i386/posix_types.h deleted file mode 100644 index 5529f32..0000000 --- a/include/asm-i386/posix_types.h +++ /dev/null @@ -1,80 +0,0 @@ -#ifndef __ARCH_I386_POSIX_TYPES_H -#define __ARCH_I386_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd,fdsetp) \ - __asm__ __volatile__("btsl %1,%0": \ - "=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd))) - -#undef __FD_CLR -#define __FD_CLR(fd,fdsetp) \ - __asm__ __volatile__("btrl %1,%0": \ - "=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd))) - -#undef __FD_ISSET -#define __FD_ISSET(fd,fdsetp) (__extension__ ({ \ - unsigned char __result; \ - __asm__ __volatile__("btl %1,%2 ; setb %0" \ - :"=q" (__result) :"r" ((int) (fd)), \ - "m" (*(__kernel_fd_set *) (fdsetp))); \ - __result; })) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ -do { \ - int __d0, __d1; \ - __asm__ __volatile__("cld ; rep ; stosl" \ - :"=m" (*(__kernel_fd_set *) (fdsetp)), \ - "=&c" (__d0), "=&D" (__d1) \ - :"a" (0), "1" (__FDSET_LONGS), \ - "2" ((__kernel_fd_set *) (fdsetp)) : "memory"); \ -} while (0) - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ - -#endif diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h deleted file mode 100644 index 5dedba8..0000000 --- a/include/asm-i386/processor.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_PROCESSOR_H_ -#define __ASM_PROCESSOR_H_ 1 -/* Currently this header is unused in the i386 port - * but some generic files #include - * so this file is a placeholder. */ -#endif diff --git a/include/asm-i386/ptrace.h b/include/asm-i386/ptrace.h deleted file mode 100644 index 750e40d..0000000 --- a/include/asm-i386/ptrace.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef _I386_PTRACE_H -#define _I386_PTRACE_H - -#define EBX 0 -#define ECX 1 -#define EDX 2 -#define ESI 3 -#define EDI 4 -#define EBP 5 -#define EAX 6 -#define DS 7 -#define ES 8 -#define FS 9 -#define GS 10 -#define ORIG_EAX 11 -#define EIP 12 -#define CS 13 -#define EFL 14 -#define UESP 15 -#define SS 16 -#define FRAME_SIZE 17 - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long ebx; - long ecx; - long edx; - long esi; - long edi; - long ebp; - long eax; - int xds; - int xes; - int xfs; - int xgs; - long orig_eax; - long eip; - int xcs; - long eflags; - long esp; - int xss; -} __attribute__ ((packed)); - - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 -#define PTRACE_GETFPXREGS 18 -#define PTRACE_SETFPXREGS 19 - -#define PTRACE_SETOPTIONS 21 - -/* options set using PTRACE_SETOPTIONS */ -#define PTRACE_O_TRACESYSGOOD 0x00000001 - -#ifdef __KERNEL__ -#define user_mode(regs) ((VM_MASK & (regs)->eflags) || (3 & (regs)->xcs)) -#define instruction_pointer(regs) ((regs)->eip) -extern void show_regs(struct pt_regs *); -#endif - -#endif diff --git a/include/asm-i386/realmode.h b/include/asm-i386/realmode.h deleted file mode 100644 index 9177e4e..0000000 --- a/include/asm-i386/realmode.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_REALMODE_H_ -#define __ASM_REALMODE_H_ -#include - -int bios_setup(void); -int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out); -int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out); - -#endif diff --git a/include/asm-i386/string.h b/include/asm-i386/string.h deleted file mode 100644 index 3643a79..0000000 --- a/include/asm-i386/string.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef __ASM_I386_STRING_H -#define __ASM_I386_STRING_H - -/* - * We don't do inline string functions, since the - * optimised inline asm versions are not small. - */ -#undef __HAVE_ARCH_STRNCPY -extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n); - -#undef __HAVE_ARCH_STRRCHR -extern char * strrchr(const char * s, int c); - -#undef __HAVE_ARCH_STRCHR -extern char * strchr(const char * s, int c); - -#undef __HAVE_ARCH_MEMCPY -extern void * memcpy(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMMOVE -extern void * memmove(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMCHR -extern void * memchr(const void *, int, __kernel_size_t); - -#undef __HAVE_ARCH_MEMSET -extern void * memset(void *, int, __kernel_size_t); - -#undef __HAVE_ARCH_MEMZERO -extern void memzero(void *ptr, __kernel_size_t n); - -#endif diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h deleted file mode 100644 index 9a40e38..0000000 --- a/include/asm-i386/types.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef __ASM_I386_TYPES_H -#define __ASM_I386_TYPES_H - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif /* __KERNEL__ */ - -#endif diff --git a/include/asm-i386/u-boot-i386.h b/include/asm-i386/u-boot-i386.h deleted file mode 100644 index a08632d..0000000 --- a/include/asm-i386/u-boot-i386.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _U_BOOT_I386_H_ -#define _U_BOOT_I386_H_ 1 - -/* cpu/.../cpu.c */ -int cpu_init_r(void); -int cpu_init_f(void); - -/* cpu/.../timer.c */ -void timer_isr(void *); -typedef void (timer_fnc_t) (void); -int register_timer_isr (timer_fnc_t *isr_func); - -/* Architecture specific - can be in cpu/i386/, arch/i386/lib/, or $(BOARD)/ */ -int timer_init(void); - -/* cpu/.../interrupts.c */ -int cpu_init_interrupts(void); - -/* board/.../... */ -int board_init(void); -int dram_init(void); - -void isa_unmap_rom(u32 addr); -u32 isa_map_rom(u32 bus_addr, int size); - -/* arch/i386/lib/... */ -int video_bios_init(void); -int video_init(void); - - -#endif /* _U_BOOT_I386_H_ */ diff --git a/include/asm-i386/u-boot.h b/include/asm-i386/u-boot.h deleted file mode 100644 index 9a1eec0..0000000 --- a/include/asm-i386/u-boot.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef _U_BOOT_H_ -#define _U_BOOT_H_ 1 - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ - unsigned int bi_baudrate; /* Console Baudrate */ - unsigned long bi_boot_params; /* where this board expects params */ - struct environment_s *bi_env; - struct /* RAM configuration */ - { - ulong start; - ulong size; - }bi_dram[CONFIG_NR_DRAM_BANKS]; -} bd_t; - -#define bi_env_data bi_env->data -#define bi_env_crc bi_env->crc - -#endif /* _U_BOOT_H_ */ diff --git a/include/asm-i386/zimage.h b/include/asm-i386/zimage.h deleted file mode 100644 index b6266e4..0000000 --- a/include/asm-i386/zimage.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_ZIMAGE_H_ -#define _ASM_ZIMAGE_H_ - -/* linux i386 zImage/bzImage header. Offsets relative to - * the start of the image */ - -#define CMD_LINE_MAGIC_OFF 0x020 /* Magic 0xa33f if the offset below is valid */ -#define CMD_LINE_OFFSET_OFF 0x022 /* Offset to comandline */ -#define SETUP_SECTS_OFF 0x1F1 /* The size of the setup in sectors */ -#define ROOT_FLAGS_OFF 0x1F2 /* If set, the root is mounted readonly */ -#define VID_MODE_OFF 0x1FA /* Video mode control */ -#define ROOT_DEV_OFF 0x1FC /* Default root device number */ -#define BOOT_FLAG_OFF 0x1FE /* 0xAA55 magic number */ -#define HEADER_OFF 0x202 /* Magic signature "HdrS" */ -#define VERSION_OFF 0x206 /* Boot protocol version supported */ -#define REALMODE_SWTCH_OFF 0x208 /* Boot loader hook (see below) */ -#define START_SYS_OFF 0x20C /* Points to kernel version string */ -#define TYPE_OF_LOADER_OFF 0x210 /* Boot loader identifier */ -#define LOADFLAGS_OFF 0x211 /* Boot protocol option flags */ -#define SETUP_MOVE_SIZE_OFF 0x212 /* Move to high memory size (used with hooks) */ -#define CODE32_START_OFF 0x214 /* Boot loader hook (see below) */ -#define RAMDISK_IMAGE_OFF 0x218 /* initrd load address (set by boot loader) */ -#define RAMDISK_SIZE_OFF 0x21C /* initrd size (set by boot loader) */ -#define HEAP_END_PTR_OFF 0x224 /* Free memory after setup end */ -#define CMD_LINE_PTR_OFF 0x228 /* 32-bit pointer to the kernel command line */ - - -#define HEAP_FLAG 0x80 -#define BIG_KERNEL_FLAG 0x01 - -/* magic numbers */ -#define KERNEL_MAGIC 0xaa55 -#define KERNEL_V2_MAGIC 0x53726448 -#define COMMAND_LINE_MAGIC 0xA33F - -/* limits */ -#define BZIMAGE_MAX_SIZE 15*1024*1024 /* 15MB */ -#define ZIMAGE_MAX_SIZE 512*1024 /* 512k */ -#define SETUP_MAX_SIZE 32768 - -#define SETUP_START_OFFSET 0x200 -#define BZIMAGE_LOAD_ADDR 0x100000 -#define ZIMAGE_LOAD_ADDR 0x10000 - -void *load_zimage(char *image, unsigned long kernel_size, - unsigned long initrd_addr, unsigned long initrd_size, - int auto_boot); - -void boot_zimage(void *setup_base); - -#endif diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h deleted file mode 100644 index ad971b4..0000000 --- a/include/asm-m68k/bitops.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * bitops.h: Bit string operations on the m68k - */ - -#ifndef _M68K_BITOPS_H -#define _M68K_BITOPS_H - -#include -#include - -extern void set_bit(int nr, volatile void *addr); -extern void clear_bit(int nr, volatile void *addr); -extern void change_bit(int nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void *addr); -extern int test_and_clear_bit(int nr, volatile void *addr); -extern int test_and_change_bit(int nr, volatile void *addr); - -#ifdef __KERNEL__ - -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -extern __inline__ int ffs(int x) -{ - int r = 1; - - if (!x) - return 0; - if (!(x & 0xffff)) { - x >>= 16; - r += 16; - } - if (!(x & 0xff)) { - x >>= 8; - r += 8; - } - if (!(x & 0xf)) { - x >>= 4; - r += 4; - } - if (!(x & 3)) { - x >>= 2; - r += 2; - } - if (!(x & 1)) { - x >>= 1; - r += 1; - } - return r; -} -#define __ffs(x) (ffs(x) - 1) -#define PLATFORM_FFS - -#endif /* __KERNEL__ */ - -#endif /* _M68K_BITOPS_H */ diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h deleted file mode 100644 index 0e2a0ed..0000000 --- a/include/asm-m68k/byteorder.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _M68K_BYTEORDER_H -#define _M68K_BYTEORDER_H - -#include - -#ifdef __GNUC__ -#define __sw16(x) \ - ((__u16)( \ - (((__u16)(x) & (__u16)0x00ffU) << 8) | \ - (((__u16)(x) & (__u16)0xff00U) >> 8) )) -#define __sw32(x) \ - ((__u32)( \ - (((__u32)(x)) << 24) | \ - (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ - (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ - (((__u32)(x)) >> 24) )) - -extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) -{ - unsigned result = *addr; - return __sw16(result); -} - -extern __inline__ void st_le16(volatile unsigned short *addr, - const unsigned val) -{ - *addr = __sw16(val); -} - -extern __inline__ unsigned ld_le32(const volatile unsigned *addr) -{ - unsigned result = *addr; - return __sw32(result); -} - -extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) -{ - *addr = __sw32(val); -} - -#if 0 -/* alas, egcs sounds like it has a bug in this code that doesn't use the - inline asm correctly, and can cause file corruption. Until I hear that - it's fixed, I can live without the extra speed. I hope. */ -#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90) -#if 0 -# define __arch_swab16(x) ld_le16(&x) -# define __arch_swab32(x) ld_le32(&x) -#else -static __inline__ __attribute__ ((const)) -__u16 ___arch__swab16(__u16 value) -{ - return __sw16(value); -} - -static __inline__ __attribute__ ((const)) -__u32 ___arch__swab32(__u32 value) -{ - return __sw32(value); -} - -#define __arch__swab32(x) ___arch__swab32(x) -#define __arch__swab16(x) ___arch__swab16(x) -#endif /* 0 */ - -#endif - -/* The same, but returns converted value from the location pointer by addr. */ -#define __arch__swab16p(addr) ld_le16(addr) -#define __arch__swab32p(addr) ld_le32(addr) - -/* The same, but do the conversion in situ, ie. put the value back to addr. */ -#define __arch__swab16s(addr) st_le16(addr,*addr) -#define __arch__swab32s(addr) st_le32(addr,*addr) -#endif - -#endif /* __GNUC__ */ - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -#define __BYTEORDER_HAS_U64__ -#endif -#include - -#endif /* _M68K_BYTEORDER_H */ diff --git a/include/asm-m68k/cache.h b/include/asm-m68k/cache.h deleted file mode 100644 index 7c84e48..0000000 --- a/include/asm-m68k/cache.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * ColdFire cache - * - * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CACHE_H -#define __CACHE_H - -#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ - defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x) -#define CONFIG_CF_V2 -#endif - -#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) -#define CONFIG_CF_V3 -#endif - -#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) -#define CONFIG_CF_V4 -#if defined(CONFIG_MCF5441x) -#define CONFIG_CF_V4E /* Four Extra ACRn */ -#endif -#endif - -/* ***** CACR ***** */ -/* V2 Core */ -#ifdef CONFIG_CF_V2 - -#define CF_CACR_CENB (1 << 31) -#define CF_CACR_CPD (1 << 28) -#define CF_CACR_CFRZ (1 << 27) -#define CF_CACR_CEIB (1 << 10) -#define CF_CACR_DCM (1 << 9) -#define CF_CACR_DBWE (1 << 8) - -#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253) -#define CF_CACR_DWP (1 << 6) -#else -#define CF_CACR_CINV (1 << 24) -#define CF_CACR_DISI (1 << 23) -#define CF_CACR_DISD (1 << 22) -#define CF_CACR_INVI (1 << 21) -#define CF_CACR_INVD (1 << 20) -#define CF_CACR_DWP (1 << 5) -#define CF_CACR_EUSP (1 << 4) -#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ - -#endif /* CONFIG_CF_V2 */ - -/* V3 Core */ -#ifdef CONFIG_CF_V3 - -#define CF_CACR_EC (1 << 31) -#define CF_CACR_ESB (1 << 29) -#define CF_CACR_DPI (1 << 28) -#define CF_CACR_HLCK (1 << 27) -#define CF_CACR_CINVA (1 << 24) -#define CF_CACR_DNFB (1 << 10) -#define CF_CACR_DCM_UNMASK 0xFFFFFCFF -#define CF_CACR_DCM_WT (0 << 8) -#define CF_CACR_DCM_CB (1 << 8) -#define CF_CACR_DCM_P (2 << 8) -#define CF_CACR_DCM_IP (3 << 8) -#define CF_CACR_DW (1 << 5) -#define CF_CACR_EUSP (1 << 4) - -#endif /* CONFIG_CF_V3 */ - -/* V4 Core */ -#ifdef CONFIG_CF_V4 - -#define CF_CACR_DEC (1 << 31) -#define CF_CACR_DW (1 << 30) -#define CF_CACR_DESB (1 << 29) -#define CF_CACR_DDPI (1 << 28) -#define CF_CACR_DHLCK (1 << 27) -#define CF_CACR_DDCM_UNMASK (0xF9FFFFFF) -#define CF_CACR_DDCM_WT (0 << 25) -#define CF_CACR_DDCM_CB (1 << 25) -#define CF_CACR_DDCM_P (2 << 25) -#define CF_CACR_DDCM_IP (3 << 25) -#define CF_CACR_DCINVA (1 << 24) - -#define CF_CACR_DDSP (1 << 23) -#define CF_CACR_BEC (1 << 19) -#define CF_CACR_BCINVA (1 << 18) -#define CF_CACR_IEC (1 << 15) -#define CF_CACR_DNFB (1 << 13) -#define CF_CACR_IDPI (1 << 12) -#define CF_CACR_IHLCK (1 << 11) -#define CF_CACR_IDCM (1 << 10) -#define CF_CACR_ICINVA (1 << 8) -#define CF_CACR_IDSP (1 << 7) -#define CF_CACR_EUSP (1 << 5) - -#ifdef CONFIG_MCF5445x -#define CF_CACR_IVO (1 << 20) -#define CF_CACR_SPA (1 << 14) -#else -#define CF_CACR_DF (1 << 4) -#endif - -#endif /* CONFIG_CF_V4 */ - -/* ***** ACR ***** */ -#define CF_ACR_ADR_UNMASK (0x00FFFFFF) -#define CF_ACR_ADR(x) ((x & 0xFF) << 24) -#define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF) -#define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16) -#define CF_ACR_EN (1 << 15) -#define CF_ACR_SM_UNMASK (0xFFFF9FFF) -#define CF_ACR_SM_UM (0 << 13) -#define CF_ACR_SM_SM (1 << 13) -#define CF_ACR_SM_ALL (3 << 13) -#define CF_ACR_WP (1 << 2) - -/* V2 Core */ -#ifdef CONFIG_CF_V2 -#define CF_ACR_CM (1 << 6) -#define CF_ACR_BWE (1 << 5) -#else -/* V3 & V4 */ -#define CF_ACR_CM_UNMASK (0xFFFFFF9F) -#define CF_ACR_CM_WT (0 << 5) -#define CF_ACR_CM_CB (1 << 5) -#define CF_ACR_CM_P (2 << 5) -#define CF_ACR_CM_IP (3 << 5) -#endif /* CONFIG_CF_V2 */ - -/* V4 Core */ -#ifdef CONFIG_CF_V4 -#define CF_ACR_AMM (1 << 10) -#define CF_ACR_SP (1 << 3) -#endif /* CONFIG_CF_V4 */ - - -#ifndef CONFIG_SYS_CACHE_ICACR -#define CONFIG_SYS_CACHE_ICACR 0 -#endif - -#ifndef CONFIG_SYS_CACHE_DCACR -#ifdef CONFIG_SYS_CACHE_ICACR -#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR -#else -#define CONFIG_SYS_CACHE_DCACR 0 -#endif -#endif - -#ifndef CONFIG_SYS_CACHE_ACR0 -#define CONFIG_SYS_CACHE_ACR0 0 -#endif - -#ifndef CONFIG_SYS_CACHE_ACR1 -#define CONFIG_SYS_CACHE_ACR1 0 -#endif - -#ifndef CONFIG_SYS_CACHE_ACR2 -#define CONFIG_SYS_CACHE_ACR2 0 -#endif - -#ifndef CONFIG_SYS_CACHE_ACR3 -#define CONFIG_SYS_CACHE_ACR3 0 -#endif - -#ifndef CONFIG_SYS_CACHE_ACR4 -#define CONFIG_SYS_CACHE_ACR4 0 -#endif - -#ifndef CONFIG_SYS_CACHE_ACR5 -#define CONFIG_SYS_CACHE_ACR5 0 -#endif - -#ifndef CONFIG_SYS_CACHE_ACR6 -#define CONFIG_SYS_CACHE_ACR6 0 -#endif - -#ifndef CONFIG_SYS_CACHE_ACR7 -#define CONFIG_SYS_CACHE_ACR7 0 -#endif - -#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16) - -#ifndef __ASSEMBLY__ /* put C only stuff in this section */ - -void icache_invalid(void); -void dcache_invalid(void); - -#endif - -#endif /* __CACHE_H */ diff --git a/include/asm-m68k/coldfire/ata.h b/include/asm-m68k/coldfire/ata.h deleted file mode 100644 index 3efd03a..0000000 --- a/include/asm-m68k/coldfire/ata.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * ATA Internal Memory Map - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ATA_H__ -#define __ATA_H__ - -/* ATA */ -typedef struct atac { - /* PIO */ - u8 toff; /* 0x00 */ - u8 ton; /* 0x01 */ - u8 t1; /* 0x02 */ - u8 t2w; /* 0x03 */ - u8 t2r; /* 0x04 */ - u8 ta; /* 0x05 */ - u8 trd; /* 0x06 */ - u8 t4; /* 0x07 */ - u8 t9; /* 0x08 */ - - /* DMA */ - u8 tm; /* 0x09 */ - u8 tn; /* 0x0A */ - u8 td; /* 0x0B */ - u8 tk; /* 0x0C */ - u8 tack; /* 0x0D */ - u8 tenv; /* 0x0E */ - u8 trp; /* 0x0F */ - u8 tzah; /* 0x10 */ - u8 tmli; /* 0x11 */ - u8 tdvh; /* 0x12 */ - u8 tdzfs; /* 0x13 */ - u8 tdvs; /* 0x14 */ - u8 tcvh; /* 0x15 */ - u8 tss; /* 0x16 */ - u8 tcyc; /* 0x17 */ - - /* FIFO */ - u32 fifo32; /* 0x18 */ - u16 fifo16; /* 0x1C */ - u8 rsvd0[2]; - u8 ffill; /* 0x20 */ - u8 rsvd1[3]; - - /* ATA */ - u8 cr; /* 0x24 */ - u8 rsvd2[3]; - u8 isr; /* 0x28 */ - u8 rsvd3[3]; - u8 ier; /* 0x2C */ - u8 rsvd4[3]; - u8 icr; /* 0x30 */ - u8 rsvd5[3]; - u8 falarm; /* 0x34 */ - u8 rsvd6[106]; -} atac_t; - -#endif /* __ATA_H__ */ diff --git a/include/asm-m68k/coldfire/crossbar.h b/include/asm-m68k/coldfire/crossbar.h deleted file mode 100644 index a9c724c..0000000 --- a/include/asm-m68k/coldfire/crossbar.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Cross Bar Switch Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CROSSBAR_H__ -#define __CROSSBAR_H__ - -/********************************************************************* -* Cross-bar switch (XBS) -*********************************************************************/ -typedef struct xbs { - u32 prs1; /* 0x100 Priority Register Slave 1 */ - u32 res1[3]; /* 0x104 - 0F */ - u32 crs1; /* 0x110 Control Register Slave 1 */ - u32 res2[187]; /* 0x114 - 0x3FF */ - - u32 prs4; /* 0x400 Priority Register Slave 4 */ - u32 res3[3]; /* 0x404 - 0F */ - u32 crs4; /* 0x410 Control Register Slave 4 */ - u32 res4[123]; /* 0x414 - 0x5FF */ - - u32 prs6; /* 0x600 Priority Register Slave 6 */ - u32 res5[3]; /* 0x604 - 0F */ - u32 crs6; /* 0x610 Control Register Slave 6 */ - u32 res6[59]; /* 0x614 - 0x6FF */ - - u32 prs7; /* 0x700 Priority Register Slave 7 */ - u32 res7[3]; /* 0x704 - 0F */ - u32 crs7; /* 0x710 Control Register Slave 7 */ -} xbs_t; - -/* Bit definitions and macros for PRS group */ -#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */ -#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */ -#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */ -#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */ -#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */ -#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */ -#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */ - -/* Bit definitions and macros for CRS group */ -#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */ -#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */ -#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */ -#define XBS_CRS_RO (0x80000000) /* Read Only */ - -#define XBS_CRS_PCTL_PARK_FIELD (0) -#define XBS_CRS_PCTL_PARK_ON_LAST (1) -#define XBS_CRS_PCTL_PARK_NONE (2) -#define XBS_CRS_PCTL_PARK_CORE (0) -#define XBS_CRS_PCTL_PARK_EDMA (1) -#define XBS_CRS_PCTL_PARK_FEC0 (2) -#define XBS_CRS_PCTL_PARK_FEC1 (3) -#define XBS_CRS_PCTL_PARK_PCI (5) -#define XBS_CRS_PCTL_PARK_USB (6) -#define XBS_CRS_PCTL_PARK_SBF (7) - -#endif /* __CROSSBAR_H__ */ diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h deleted file mode 100644 index 02d1409..0000000 --- a/include/asm-m68k/coldfire/dspi.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * MCF5227x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __DSPI_H__ -#define __DSPI_H__ - -/* DMA Serial Peripheral Interface (DSPI) */ -typedef struct dspi { - u32 mcr; /* 0x00 */ - u32 resv0; /* 0x04 */ - u32 tcr; /* 0x08 */ - u32 ctar[8]; /* 0x0C - 0x28 */ - u32 sr; /* 0x2C */ - u32 irsr; /* 0x30 */ - u32 tfr; /* 0x34 - PUSHR */ - u16 resv1; /* 0x38 */ - u16 rfr; /* 0x3A - POPR */ -#ifdef CONFIG_MCF547x_8x - u32 tfdr[4]; /* 0x3C */ - u8 resv2[0x30]; /* 0x40 */ - u32 rfdr[4]; /* 0x7C */ -#else - u32 tfdr[16]; /* 0x3C */ - u32 rfdr[16]; /* 0x7C */ -#endif -} dspi_t; - -/* Module configuration */ -#define DSPI_MCR_MSTR (0x80000000) -#define DSPI_MCR_CSCK (0x40000000) -#define DSPI_MCR_DCONF(x) (((x)&0x03)<<28) -#define DSPI_MCR_FRZ (0x08000000) -#define DSPI_MCR_MTFE (0x04000000) -#define DSPI_MCR_PCSSE (0x02000000) -#define DSPI_MCR_ROOE (0x01000000) -#define DSPI_MCR_CSIS7 (0x00800000) -#define DSPI_MCR_CSIS6 (0x00400000) -#define DSPI_MCR_CSIS5 (0x00200000) -#define DSPI_MCR_CSIS4 (0x00100000) -#define DSPI_MCR_CSIS3 (0x00080000) -#define DSPI_MCR_CSIS2 (0x00040000) -#define DSPI_MCR_CSIS1 (0x00020000) -#define DSPI_MCR_CSIS0 (0x00010000) -#define DSPI_MCR_MDIS (0x00004000) -#define DSPI_MCR_DTXF (0x00002000) -#define DSPI_MCR_DRXF (0x00001000) -#define DSPI_MCR_CTXF (0x00000800) -#define DSPI_MCR_CRXF (0x00000400) -#define DSPI_MCR_SMPL_PT(x) (((x)&0x03)<<8) -#define DSPI_MCR_HALT (0x00000001) - -/* Transfer count */ -#define DSPI_TCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) - -/* Clock and transfer attributes */ -#define DSPI_CTAR_DBR (0x80000000) -#define DSPI_CTAR_TRSZ(x) (((x)&0x0F)<<27) -#define DSPI_CTAR_CPOL (0x04000000) -#define DSPI_CTAR_CPHA (0x02000000) -#define DSPI_CTAR_LSBFE (0x01000000) -#define DSPI_CTAR_PCSSCK(x) (((x)&0x03)<<22) -#define DSPI_CTAR_PCSSCK_7CLK (0x00A00000) -#define DSPI_CTAR_PCSSCK_5CLK (0x00800000) -#define DSPI_CTAR_PCSSCK_3CLK (0x00400000) -#define DSPI_CTAR_PCSSCK_1CLK (0x00000000) -#define DSPI_CTAR_PASC(x) (((x)&0x03)<<20) -#define DSPI_CTAR_PASC_7CLK (0x00300000) -#define DSPI_CTAR_PASC_5CLK (0x00200000) -#define DSPI_CTAR_PASC_3CLK (0x00100000) -#define DSPI_CTAR_PASC_1CLK (0x00000000) -#define DSPI_CTAR_PDT(x) (((x)&0x03)<<18) -#define DSPI_CTAR_PDT_7CLK (0x000A0000) -#define DSPI_CTAR_PDT_5CLK (0x00080000) -#define DSPI_CTAR_PDT_3CLK (0x00040000) -#define DSPI_CTAR_PDT_1CLK (0x00000000) -#define DSPI_CTAR_PBR(x) (((x)&0x03)<<16) -#define DSPI_CTAR_PBR_7CLK (0x00030000) -#define DSPI_CTAR_PBR_5CLK (0x00020000) -#define DSPI_CTAR_PBR_3CLK (0x00010000) -#define DSPI_CTAR_PBR_1CLK (0x00000000) -#define DSPI_CTAR_CSSCK(x) (((x)&0x0F)<<12) -#define DSPI_CTAR_ASC(x) (((x)&0x0F)<<8) -#define DSPI_CTAR_DT(x) (((x)&0x0F)<<4) -#define DSPI_CTAR_BR(x) (((x)&0x0F)) - -/* Status */ -#define DSPI_SR_TCF (0x80000000) -#define DSPI_SR_TXRXS (0x40000000) -#define DSPI_SR_EOQF (0x10000000) -#define DSPI_SR_TFUF (0x08000000) -#define DSPI_SR_TFFF (0x02000000) -#define DSPI_SR_RFOF (0x00080000) -#define DSPI_SR_RFDF (0x00020000) -#define DSPI_SR_TXCTR(x) (((x)&0x0F)<<12) -#define DSPI_SR_TXPTR(x) (((x)&0x0F)<<8) -#define DSPI_SR_RXCTR(x) (((x)&0x0F)<<4) -#define DSPI_SR_RXPTR(x) (((x)&0x0F)) - -/* DMA/interrupt request selct and enable */ -#define DSPI_IRSR_TCFE (0x80000000) -#define DSPI_IRSR_EOQFE (0x10000000) -#define DSPI_IRSR_TFUFE (0x08000000) -#define DSPI_IRSR_TFFFE (0x02000000) -#define DSPI_IRSR_TFFFS (0x01000000) -#define DSPI_IRSR_RFOFE (0x00080000) -#define DSPI_IRSR_RFDFE (0x00020000) -#define DSPI_IRSR_RFDFS (0x00010000) - -/* Transfer control - 32-bit access */ -#define DSPI_TFR_CONT (0x80000000) -#define DSPI_TFR_CTAS(x) (((x)&0x07)<<12) -#define DSPI_TFR_EOQ (0x08000000) -#define DSPI_TFR_CTCNT (0x04000000) -#define DSPI_TFR_CS7 (0x00800000) -#define DSPI_TFR_CS6 (0x00400000) -#define DSPI_TFR_CS5 (0x00200000) -#define DSPI_TFR_CS4 (0x00100000) -#define DSPI_TFR_CS3 (0x00080000) -#define DSPI_TFR_CS2 (0x00040000) -#define DSPI_TFR_CS1 (0x00020000) -#define DSPI_TFR_CS0 (0x00010000) - -/* Transfer Fifo */ -#define DSPI_TFR_TXDATA(x) (((x)&0xFFFF)) - -/* Bit definitions and macros for DRFR */ -#define DSPI_RFR_RXDATA(x) (((x)&0xFFFF)) - -/* Bit definitions and macros for DTFDR group */ -#define DSPI_TFDR_TXDATA(x) (((x)&0x0000FFFF)) -#define DSPI_TFDR_TXCMD(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for DRFDR group */ -#define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF)) - -#endif /* __DSPI_H__ */ diff --git a/include/asm-m68k/coldfire/edma.h b/include/asm-m68k/coldfire/edma.h deleted file mode 100644 index c88aea6..0000000 --- a/include/asm-m68k/coldfire/edma.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * EDMA Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __EDMA_H__ -#define __EDMA_H__ - -/********************************************************************* -* Enhanced DMA (EDMA) -*********************************************************************/ - -/* eDMA module registers */ -typedef struct edma_ctrl { - u32 cr; /* 0x00 Control Register */ - u32 es; /* 0x04 Error Status Register */ - u16 res1[3]; /* 0x08 - 0x0D */ - u16 erq; /* 0x0E Enable Request Register */ - u16 res2[3]; /* 0x10 - 0x15 */ - u16 eei; /* 0x16 Enable Error Interrupt Request */ - u8 serq; /* 0x18 Set Enable Request */ - u8 cerq; /* 0x19 Clear Enable Request */ - u8 seei; /* 0x1A Set En Error Interrupt Request */ - u8 ceei; /* 0x1B Clear En Error Interrupt Request */ - u8 cint; /* 0x1C Clear Interrupt Enable */ - u8 cerr; /* 0x1D Clear Error */ - u8 ssrt; /* 0x1E Set START Bit */ - u8 cdne; /* 0x1F Clear DONE Status Bit */ - u16 res3[3]; /* 0x20 - 0x25 */ - u16 intr; /* 0x26 Interrupt Request */ - u16 res4[3]; /* 0x28 - 0x2D */ - u16 err; /* 0x2E Error Register */ - u32 res5[52]; /* 0x30 - 0xFF */ - u8 dchpri0; /* 0x100 Channel 0 Priority */ - u8 dchpri1; /* 0x101 Channel 1 Priority */ - u8 dchpri2; /* 0x102 Channel 2 Priority */ - u8 dchpri3; /* 0x103 Channel 3 Priority */ - u8 dchpri4; /* 0x104 Channel 4 Priority */ - u8 dchpri5; /* 0x105 Channel 5 Priority */ - u8 dchpri6; /* 0x106 Channel 6 Priority */ - u8 dchpri7; /* 0x107 Channel 7 Priority */ - u8 dchpri8; /* 0x108 Channel 8 Priority */ - u8 dchpri9; /* 0x109 Channel 9 Priority */ - u8 dchpri10; /* 0x110 Channel 10 Priority */ - u8 dchpri11; /* 0x111 Channel 11 Priority */ - u8 dchpri12; /* 0x112 Channel 12 Priority */ - u8 dchpri13; /* 0x113 Channel 13 Priority */ - u8 dchpri14; /* 0x114 Channel 14 Priority */ - u8 dchpri15; /* 0x115 Channel 15 Priority */ -} edma_t; - -/* TCD - eDMA*/ -typedef struct tcd_ctrl { - u32 saddr; /* 0x00 Source Address */ - u16 attr; /* 0x04 Transfer Attributes */ - u16 soff; /* 0x06 Signed Source Address Offset */ - u32 nbytes; /* 0x08 Minor Byte Count */ - u32 slast; /* 0x0C Last Source Address Adjustment */ - u32 daddr; /* 0x10 Destination address */ - u16 citer; /* 0x14 Cur Minor Loop Link, Major Loop Cnt */ - u16 doff; /* 0x16 Signed Destination Address Offset */ - u32 dlast_sga; /* 0x18 Last Dest Adr Adj/Scatter Gather Adr */ - u16 biter; /* 0x1C Minor Loop Lnk, Major Loop Cnt */ - u16 csr; /* 0x1E Control and Status */ -} tcd_st; - -typedef struct tcd_multiple { - tcd_st tcd[16]; -} tcd_t; - -/* Bit definitions and macros for EPPAR */ -#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define EPORT_EPPAR_LEVEL (0) -#define EPORT_EPPAR_RISING (1) -#define EPORT_EPPAR_FALLING (2) -#define EPORT_EPPAR_BOTH (3) -#define EPORT_EPPAR_EPPA7_LEVEL (0x0000) -#define EPORT_EPPAR_EPPA7_RISING (0x4000) -#define EPORT_EPPAR_EPPA7_FALLING (0x8000) -#define EPORT_EPPAR_EPPA7_BOTH (0xC000) -#define EPORT_EPPAR_EPPA6_LEVEL (0x0000) -#define EPORT_EPPAR_EPPA6_RISING (0x1000) -#define EPORT_EPPAR_EPPA6_FALLING (0x2000) -#define EPORT_EPPAR_EPPA6_BOTH (0x3000) -#define EPORT_EPPAR_EPPA5_LEVEL (0x0000) -#define EPORT_EPPAR_EPPA5_RISING (0x0400) -#define EPORT_EPPAR_EPPA5_FALLING (0x0800) -#define EPORT_EPPAR_EPPA5_BOTH (0x0C00) -#define EPORT_EPPAR_EPPA4_LEVEL (0x0000) -#define EPORT_EPPAR_EPPA4_RISING (0x0100) -#define EPORT_EPPAR_EPPA4_FALLING (0x0200) -#define EPORT_EPPAR_EPPA4_BOTH (0x0300) -#define EPORT_EPPAR_EPPA3_LEVEL (0x0000) -#define EPORT_EPPAR_EPPA3_RISING (0x0040) -#define EPORT_EPPAR_EPPA3_FALLING (0x0080) -#define EPORT_EPPAR_EPPA3_BOTH (0x00C0) -#define EPORT_EPPAR_EPPA2_LEVEL (0x0000) -#define EPORT_EPPAR_EPPA2_RISING (0x0010) -#define EPORT_EPPAR_EPPA2_FALLING (0x0020) -#define EPORT_EPPAR_EPPA2_BOTH (0x0030) -#define EPORT_EPPAR_EPPA1_LEVEL (0x0000) -#define EPORT_EPPAR_EPPA1_RISING (0x0004) -#define EPORT_EPPAR_EPPA1_FALLING (0x0008) -#define EPORT_EPPAR_EPPA1_BOTH (0x000C) - -/* Bit definitions and macros for EPDDR */ -#define EPORT_EPDDR_EPDD1 (0x02) -#define EPORT_EPDDR_EPDD2 (0x04) -#define EPORT_EPDDR_EPDD3 (0x08) -#define EPORT_EPDDR_EPDD4 (0x10) -#define EPORT_EPDDR_EPDD5 (0x20) -#define EPORT_EPDDR_EPDD6 (0x40) -#define EPORT_EPDDR_EPDD7 (0x80) - -/* Bit definitions and macros for EPIER */ -#define EPORT_EPIER_EPIE1 (0x02) -#define EPORT_EPIER_EPIE2 (0x04) -#define EPORT_EPIER_EPIE3 (0x08) -#define EPORT_EPIER_EPIE4 (0x10) -#define EPORT_EPIER_EPIE5 (0x20) -#define EPORT_EPIER_EPIE6 (0x40) -#define EPORT_EPIER_EPIE7 (0x80) - -/* Bit definitions and macros for EPDR */ -#define EPORT_EPDR_EPD1 (0x02) -#define EPORT_EPDR_EPD2 (0x04) -#define EPORT_EPDR_EPD3 (0x08) -#define EPORT_EPDR_EPD4 (0x10) -#define EPORT_EPDR_EPD5 (0x20) -#define EPORT_EPDR_EPD6 (0x40) -#define EPORT_EPDR_EPD7 (0x80) - -/* Bit definitions and macros for EPPDR */ -#define EPORT_EPPDR_EPPD1 (0x02) -#define EPORT_EPPDR_EPPD2 (0x04) -#define EPORT_EPPDR_EPPD3 (0x08) -#define EPORT_EPPDR_EPPD4 (0x10) -#define EPORT_EPPDR_EPPD5 (0x20) -#define EPORT_EPPDR_EPPD6 (0x40) -#define EPORT_EPPDR_EPPD7 (0x80) - -/* Bit definitions and macros for EPFR */ -#define EPORT_EPFR_EPF1 (0x02) -#define EPORT_EPFR_EPF2 (0x04) -#define EPORT_EPFR_EPF3 (0x08) -#define EPORT_EPFR_EPF4 (0x10) -#define EPORT_EPFR_EPF5 (0x20) -#define EPORT_EPFR_EPF6 (0x40) -#define EPORT_EPFR_EPF7 (0x80) - -#endif /* __EDMA_H__ */ diff --git a/include/asm-m68k/coldfire/eport.h b/include/asm-m68k/coldfire/eport.h deleted file mode 100644 index 1d1bf63..0000000 --- a/include/asm-m68k/coldfire/eport.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Edge Port Memory Map - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __EPORT_H__ -#define __EPORT_H__ - -/* Edge Port Module (EPORT) */ -typedef struct eport { -#ifdef CONFIG_MCF547x_8x - u16 par; /* 0x00 */ - u16 res0; /* 0x02 */ - u8 ddr; /* 0x04 */ - u8 ier; /* 0x05 */ - u16 res1; /* 0x06 */ - u8 dr; /* 0x08 */ - u8 pdr; /* 0x09 */ - u16 res2; /* 0x0A */ - u8 fr; /* 0x0C */ - u8 res3[3]; /* 0x0D */ -#else - u16 par; /* 0x00 Pin Assignment */ - u8 ddr; /* 0x02 Data Direction */ - u8 ier; /* 0x03 Interrupt Enable */ - u8 dr; /* 0x04 Data */ - u8 pdr; /* 0x05 Pin Data */ - u8 fr; /* 0x06 Flag */ - u8 res0; -#endif -} eport_t; - -/* EPPAR */ -#define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2) -#define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4) -#define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6) -#define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8) -#define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10) -#define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12) -#define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14) -#define EPORT_PAR_LEVEL (0) -#define EPORT_PAR_RISING (1) -#define EPORT_PAR_FALLING (2) -#define EPORT_PAR_BOTH (3) -#define EPORT_PAR_EPPA7_LEVEL (0x0000) -#define EPORT_PAR_EPPA7_RISING (0x4000) -#define EPORT_PAR_EPPA7_FALLING (0x8000) -#define EPORT_PAR_EPPA7_BOTH (0xC000) -#define EPORT_PAR_EPPA6_LEVEL (0x0000) -#define EPORT_PAR_EPPA6_RISING (0x1000) -#define EPORT_PAR_EPPA6_FALLING (0x2000) -#define EPORT_PAR_EPPA6_BOTH (0x3000) -#define EPORT_PAR_EPPA5_LEVEL (0x0000) -#define EPORT_PAR_EPPA5_RISING (0x0400) -#define EPORT_PAR_EPPA5_FALLING (0x0800) -#define EPORT_PAR_EPPA5_BOTH (0x0C00) -#define EPORT_PAR_EPPA4_LEVEL (0x0000) -#define EPORT_PAR_EPPA4_RISING (0x0100) -#define EPORT_PAR_EPPA4_FALLING (0x0200) -#define EPORT_PAR_EPPA4_BOTH (0x0300) -#define EPORT_PAR_EPPA3_LEVEL (0x0000) -#define EPORT_PAR_EPPA3_RISING (0x0040) -#define EPORT_PAR_EPPA3_FALLING (0x0080) -#define EPORT_PAR_EPPA3_BOTH (0x00C0) -#define EPORT_PAR_EPPA2_LEVEL (0x0000) -#define EPORT_PAR_EPPA2_RISING (0x0010) -#define EPORT_PAR_EPPA2_FALLING (0x0020) -#define EPORT_PAR_EPPA2_BOTH (0x0030) -#define EPORT_PAR_EPPA1_LEVEL (0x0000) -#define EPORT_PAR_EPPA1_RISING (0x0004) -#define EPORT_PAR_EPPA1_FALLING (0x0008) -#define EPORT_PAR_EPPA1_BOTH (0x000C) - -/* EPDDR */ -#define EPORT_DDR_EPDD1 (0x02) -#define EPORT_DDR_EPDD2 (0x04) -#define EPORT_DDR_EPDD3 (0x08) -#define EPORT_DDR_EPDD4 (0x10) -#define EPORT_DDR_EPDD5 (0x20) -#define EPORT_DDR_EPDD6 (0x40) -#define EPORT_DDR_EPDD7 (0x80) - -/* EPIER */ -#define EPORT_IER_EPIE1 (0x02) -#define EPORT_IER_EPIE2 (0x04) -#define EPORT_IER_EPIE3 (0x08) -#define EPORT_IER_EPIE4 (0x10) -#define EPORT_IER_EPIE5 (0x20) -#define EPORT_IER_EPIE6 (0x40) -#define EPORT_IER_EPIE7 (0x80) - -/* EPDR */ -#define EPORT_DR_EPD1 (0x02) -#define EPORT_DR_EPD2 (0x04) -#define EPORT_DR_EPD3 (0x08) -#define EPORT_DR_EPD4 (0x10) -#define EPORT_DR_EPD5 (0x20) -#define EPORT_DR_EPD6 (0x40) -#define EPORT_DR_EPD7 (0x80) - -/* EPPDR */ -#define EPORT_PDR_EPPD1 (0x02) -#define EPORT_PDR_EPPD2 (0x04) -#define EPORT_PDR_EPPD3 (0x08) -#define EPORT_PDR_EPPD4 (0x10) -#define EPORT_PDR_EPPD5 (0x20) -#define EPORT_PDR_EPPD6 (0x40) -#define EPORT_PDR_EPPD7 (0x80) - -/* EPFR */ -#define EPORT_FR_EPF1 (0x02) -#define EPORT_FR_EPF2 (0x04) -#define EPORT_FR_EPF3 (0x08) -#define EPORT_FR_EPF4 (0x10) -#define EPORT_FR_EPF5 (0x20) -#define EPORT_FR_EPF6 (0x40) -#define EPORT_FR_EPF7 (0x80) - -#endif /* __EPORT_H__ */ diff --git a/include/asm-m68k/coldfire/flexbus.h b/include/asm-m68k/coldfire/flexbus.h deleted file mode 100644 index 51cbbd8..0000000 --- a/include/asm-m68k/coldfire/flexbus.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * FlexBus Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __FLEXBUS_H -#define __FLEXBUS_H - -/********************************************************************* -* FlexBus Chip Selects (FBCS) -*********************************************************************/ - -typedef struct fbcs { - u32 csar0; /* Chip-select Address */ - u32 csmr0; /* Chip-select Mask */ - u32 cscr0; /* Chip-select Control */ - u32 csar1; - u32 csmr1; - u32 cscr1; - u32 csar2; - u32 csmr2; - u32 cscr2; - u32 csar3; - u32 csmr3; - u32 cscr3; - u32 csar4; - u32 csmr4; - u32 cscr4; - u32 csar5; - u32 csmr5; - u32 cscr5; - u32 csar6; - u32 csmr6; - u32 cscr6; - u32 csar7; - u32 csmr7; - u32 cscr7; -} fbcs_t; - -#define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000) - -#define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16) -#define FBCS_CSMR_BAM_MASK (0x0000FFFF) -#define FBCS_CSMR_BAM_4G (0xFFFF0000) -#define FBCS_CSMR_BAM_2G (0x7FFF0000) -#define FBCS_CSMR_BAM_1G (0x3FFF0000) -#define FBCS_CSMR_BAM_1024M (0x3FFF0000) -#define FBCS_CSMR_BAM_512M (0x1FFF0000) -#define FBCS_CSMR_BAM_256M (0x0FFF0000) -#define FBCS_CSMR_BAM_128M (0x07FF0000) -#define FBCS_CSMR_BAM_64M (0x03FF0000) -#define FBCS_CSMR_BAM_32M (0x01FF0000) -#define FBCS_CSMR_BAM_16M (0x00FF0000) -#define FBCS_CSMR_BAM_8M (0x007F0000) -#define FBCS_CSMR_BAM_4M (0x003F0000) -#define FBCS_CSMR_BAM_2M (0x001F0000) -#define FBCS_CSMR_BAM_1M (0x000F0000) -#define FBCS_CSMR_BAM_1024K (0x000F0000) -#define FBCS_CSMR_BAM_512K (0x00070000) -#define FBCS_CSMR_BAM_256K (0x00030000) -#define FBCS_CSMR_BAM_128K (0x00010000) -#define FBCS_CSMR_BAM_64K (0x00000000) - -#ifdef CONFIG_M5249 -#define FBCS_CSMR_WP (0x00000080) -#define FBCS_CSMR_AM (0x00000040) -#define FBCS_CSMR_CI (0x00000020) -#define FBCS_CSMR_SC (0x00000010) -#define FBCS_CSMR_SD (0x00000008) -#define FBCS_CSMR_UC (0x00000004) -#define FBCS_CSMR_UD (0x00000002) -#else -#define FBCS_CSMR_WP (0x00000100) -#endif -#define FBCS_CSMR_V (0x00000001) /* Valid bit */ - -#define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26) -#define FBCS_CSCR_SWS_MASK (0x03FFFFFF) -#define FBCS_CSCR_SWSEN (0x00800000) -#define FBCS_CSCR_ASET(x) (((x) & 0x03) << 20) -#define FBCS_CSCR_ASET_MASK (0xFFCFFFFF) -#define FBCS_CSCR_RDAH(x) (((x) & 0x03) << 18) -#define FBCS_CSCR_RDAH_MASK (0xFFF3FFFF) -#define FBCS_CSCR_WRAH(x) (((x) & 0x03) << 16) -#define FBCS_CSCR_WRAH_MASK (0xFFFCFFFF) -#define FBCS_CSCR_WS(x) (((x) & 0x3F) << 10) -#define FBCS_CSCR_WS_MASK (0xFFFF03FF) -#define FBCS_CSCR_SBM (0x00000200) -#define FBCS_CSCR_AA (0x00000100) -#define FBCS_CSCR_PS(x) (((x) & 0x03) << 6) -#define FBCS_CSCR_PS_MASK (0xFFFFFF3F) -#define FBCS_CSCR_BEM (0x00000020) -#define FBCS_CSCR_BSTR (0x00000010) -#define FBCS_CSCR_BSTW (0x00000008) - -#define FBCS_CSCR_PS_16 (0x00000080) -#define FBCS_CSCR_PS_8 (0x00000040) -#define FBCS_CSCR_PS_32 (0x00000000) - -#endif /* __FLEXBUS_H */ diff --git a/include/asm-m68k/coldfire/flexcan.h b/include/asm-m68k/coldfire/flexcan.h deleted file mode 100644 index cafd44f..0000000 --- a/include/asm-m68k/coldfire/flexcan.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Flex CAN Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __FLEXCAN_H__ -#define __FLEXCAN_H__ - -/* FlexCan Message Buffer */ -typedef struct can_msgbuf_ctrl { -#ifdef CONFIG_M5282 - u8 tmstamp; /* 0x00 Timestamp */ - u8 ctrl; /* 0x01 Control */ - u16 idh; /* 0x02 ID High */ - u16 idl; /* 0x04 ID High */ - u8 data[8]; /* 0x06 8 Byte Data Field */ - u16 res; /* 0x0E */ -#else - u16 ctrl; /* 0x00 Control/Status */ - u16 tmstamp; /* 0x02 Timestamp */ - u32 id; /* 0x04 Identifier */ - u8 data[8]; /* 0x08 8 Byte Data Field */ -#endif -} can_msg_t; - -#ifdef CONFIG_M5282 -/* MSGBUF CTRL */ -#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x0F) << 4) -#define CAN_MSGBUF_CTRL_CODE_MASK (0x0F) -#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x0F) -#define CAN_MSGBUF_CTRL_LEN_MASK (0xF0) - -/* MSGBUF ID */ -#define CAN_MSGBUF_IDH_STD(x) (((x) & 0x07FF) << 5) -#define CAN_MSGBUF_IDH_STD_MASK (0xE003FFFF) -#define CAN_MSGBUF_IDH_SRR (0x0010) -#define CAN_MSGBUF_IDH_IDE (0x0080) -#define CAN_MSGBUF_IDH_EXTH(x) ((x) & 0x07) -#define CAN_MSGBUF_IDH_EXTH_MASK (0xFFF8) -#define CAN_MSGBUF_IDL_EXTL(x) (((x) & 0x7FFF) << 1) -#define CAN_MSGBUF_IDL_EXTL_MASK (0xFFFE) -#define CAN_MSGBUF_IDL_RTR (0x0001) -#else -/* MSGBUF CTRL */ -#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x000F) << 8) -#define CAN_MSGBUF_CTRL_CODE_MASK (0xF0FF) -#define CAN_MSGBUF_CTRL_SRR (0x0040) -#define CAN_MSGBUF_CTRL_IDE (0x0020) -#define CAN_MSGBUF_CTRL_RTR (0x0010) -#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x000F) -#define CAN_MSGBUF_CTRL_LEN_MASK (0xFFF0) - -/* MSGBUF ID */ -#define CAN_MSGBUF_ID_STD(x) (((x) & 0x000007FF) << 18) -#define CAN_MSGBUF_ID_STD_MASK (0xE003FFFF) -#define CAN_MSGBUF_ID_EXT(x) ((x) & 0x0003FFFF) -#define CAN_MSGBUF_ID_EXT_MASK (0xFFFC0000) -#endif - -/* FlexCan module */ -typedef struct can_ctrl { - u32 mcr; /* 0x00 Module Configuration */ - u32 ctrl; /* 0x04 Control */ - u32 timer; /* 0x08 Free Running Timer */ - u32 res1; /* 0x0C */ - u32 rxgmsk; /* 0x10 Rx Global Mask */ - u32 rx14msk; /* 0x14 RxBuffer 14 Mask */ - u32 rx15msk; /* 0x18 RxBuffer 15 Mask */ -#ifdef CONFIG_M5282 - u32 res2; /* 0x1C */ - u16 errstat; /* 0x20 Error and status */ - u16 imsk; /* 0x22 Interrupt Mask */ - u16 iflag; /* 0x24 Interrupt Flag */ - u16 errcnt; /* 0x26 Error Counter */ - u32 res3[3]; /* 0x28 - 0x33 */ -#else - u16 res2; /* 0x1C */ - u16 errcnt; /* 0x1E Error Counter */ - u16 res3; /* 0x20 */ - u16 errstat; /* 0x22 Error and status */ - u32 res4; /* 0x24 */ - u32 imsk; /* 0x28 Interrupt Mask */ - u32 res5; /* 0x2C */ - u16 iflag; /* 0x30 Interrupt Flag */ -#endif - u32 res6[19]; /* 0x34 - 0x7F */ - void *msgbuf; /* 0x80 Message Buffer 0-15 */ -} can_t; - -/* MCR */ -#define CAN_MCR_MDIS (0x80000000) -#define CAN_MCR_FRZ (0x40000000) -#define CAN_MCR_HALT (0x10000000) -#define CAN_MCR_NORDY (0x08000000) -#define CAN_MCF_WAKEMSK (0x04000000) /* 5282 */ -#define CAN_MCR_SOFTRST (0x02000000) -#define CAN_MCR_FRZACK (0x01000000) -#define CAN_MCR_SUPV (0x00800000) -#define CAN_MCR_SELFWAKE (0x00400000) /* 5282 */ -#define CAN_MCR_APS (0x00200000) /* 5282 */ -#define CAN_MCR_LPMACK (0x00100000) -#define CAN_MCF_BCC (0x00010000) -#define CAN_MCR_MAXMB(x) ((x) & 0x0F) -#define CAN_MCR_MAXMB_MASK (0xFFFFFFF0) - -/* CTRL */ -#define CAN_CTRL_PRESDIV(x) (((x) & 0xFF) << 24) -#define CAN_CTRL_PRESDIV_MASK (0x00FFFFFF) -#define CAN_CTRL_RJW(x) (((x) & 0x03) << 22) -#define CAN_CTRL_RJW_MASK (0xFF3FFFFF) -#define CAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) -#define CAN_CTRL_PSEG1_MASK (0xFFC7FFFF) -#define CAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) -#define CAN_CTRL_PSEG2_MASK (0xFFF8FFFF) -#define CAN_CTRL_BOFFMSK (0x00008000) -#define CAN_CTRL_ERRMSK (0x00004000) -#define CAN_CTRL_CLKSRC (0x00002000) -#define CAN_CTRL_LPB (0x00001000) -#define CAN_CTRL_RXMODE (0x00000400) /* 5282 */ -#define CAN_CTRL_TXMODE(x) (((x) & 0x03) << 8) /* 5282 */ -#define CAN_CTRL_TXMODE_MASK (0xFFFFFCFF) /* 5282 */ -#define CAN_CTRL_TXMODE_CAN0 (0x00000000) /* 5282 */ -#define CAN_CTRL_TXMODE_CAN1 (0x00000100) /* 5282 */ -#define CAN_CTRL_TXMODE_OPEN (0x00000200) /* 5282 */ -#define CAN_CTRL_SMP (0x00000080) -#define CAN_CTRL_BOFFREC (0x00000040) -#define CAN_CTRL_TSYNC (0x00000020) -#define CAN_CTRL_LBUF (0x00000010) -#define CAN_CTRL_LOM (0x00000008) -#define CAN_CTRL_PROPSEG(x) ((x) & 0x07) -#define CAN_CTRL_PROPSEG_MASK (0xFFFFFFF8) - -/* TIMER */ -/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */ -#define CAN_TIMER(x) ((x) & 0xFFFF) -#define CAN_TIMER_MASK (0xFFFF0000) - -/* RXGMASK */ -#ifdef CONFIG_M5282 -#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 21) -#define CAN_RXGMSK_MI_STD_MASK (0x001FFFFF) -#define CAN_RXGMSK_MI_EXT(x) (((x) & 0x0003FFFF) << 1) -#define CAN_RXGMSK_MI_EXT_MASK (0xFFF80001) -#else -#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 18) -#define CAN_RXGMSK_MI_STD_MASK (0xE003FFFF) -#define CAN_RXGMSK_MI_EXT(x) ((x) & 0x0003FFFF) -#define CAN_RXGMSK_MI_EXT_MASK (0xFFFC0000) -#endif - -/* ERRCNT */ -#define CAN_ERRCNT_RXECTR(x) (((x) & 0xFF) << 8) -#define CAN_ERRCNT_RXECTR_MASK (0x00FF) -#define CAN_ERRCNT_TXECTR(x) ((x) & 0xFF) -#define CAN_ERRCNT_TXECTR_MASK (0xFF00) - -/* ERRSTAT */ -#define CAN_ERRSTAT_BITERR1 (0x8000) -#define CAN_ERRSTAT_BITERR0 (0x4000) -#define CAN_ERRSTAT_ACKERR (0x2000) -#define CAN_ERRSTAT_CRCERR (0x1000) -#define CAN_ERRSTAT_FRMERR (0x0800) -#define CAN_ERRSTAT_STFERR (0x0400) -#define CAN_ERRSTAT_TXWRN (0x0200) -#define CAN_ERRSTAT_RXWRN (0x0100) -#define CAN_ERRSTAT_IDLE (0x0080) -#define CAN_ERRSTAT_TXRX (0x0040) -#define CAN_ERRSTAT_FLT_MASK (0xFFCF) -#define CAN_ERRSTAT_FLT_BUSOFF (0x0020) -#define CAN_ERRSTAT_FLT_PASSIVE (0x0010) -#define CAN_ERRSTAT_FLT_ACTIVE (0x0000) -#ifdef CONFIG_M5282 -#define CAN_ERRSTAT_BOFFINT (0x0004) -#define CAN_ERRSTAT_ERRINT (0x0002) -#else -#define CAN_ERRSTAT_ERRINT (0x0004) -#define CAN_ERRSTAT_BOFFINT (0x0002) -#define CAN_ERRSTAT_WAKEINT (0x0001) -#endif - -/* IMASK */ -#ifdef CONFIG_M5253 -#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFFFFFF)) -#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x) -#else -#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFF)) -#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x) -#endif - -/* IFLAG */ -#ifdef CONFIG_M5253 -#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFFFFFF)) -#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x) -#else -#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFF)) -#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x) -#endif - -#endif /* __FLEXCAN_H__ */ diff --git a/include/asm-m68k/coldfire/intctrl.h b/include/asm-m68k/coldfire/intctrl.h deleted file mode 100644 index ae82b29..0000000 --- a/include/asm-m68k/coldfire/intctrl.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Interrupt Controller Memory Map - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __INTCTRL_H__ -#define __INTCTRL_H__ - -#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \ - defined(CONFIG_M5275) || defined(CONFIG_M5282) || \ - defined(CONFIG_M547x) || defined(CONFIG_M548x) -# define CONFIG_SYS_CF_INTC_REG1 -#endif - -typedef struct int0_ctrl { - /* Interrupt Controller 0 */ - u32 iprh0; /* 0x00 Pending High */ - u32 iprl0; /* 0x04 Pending Low */ - u32 imrh0; /* 0x08 Mask High */ - u32 imrl0; /* 0x0C Mask Low */ - u32 frch0; /* 0x10 Force High */ - u32 frcl0; /* 0x14 Force Low */ -#if defined(CONFIG_SYS_CF_INTC_REG1) - u8 irlr; /* 0x18 */ - u8 iacklpr; /* 0x19 */ - u16 res1[19]; /* 0x1a - 0x3c */ -#else - u16 res1; /* 0x18 - 0x19 */ - u16 icfg0; /* 0x1A Configuration */ - u8 simr0; /* 0x1C Set Interrupt Mask */ - u8 cimr0; /* 0x1D Clear Interrupt Mask */ - u8 clmask0; /* 0x1E Current Level Mask */ - u8 slmask; /* 0x1F Saved Level Mask */ - u32 res2[8]; /* 0x20 - 0x3F */ -#endif - u8 icr0[64]; /* 0x40 - 0x7F Control registers */ - u32 res3[24]; /* 0x80 - 0xDF */ - u8 swiack0; /* 0xE0 Software Interrupt ack */ - u8 res4[3]; /* 0xE1 - 0xE3 */ - u8 L1iack0; /* 0xE4 Level n interrupt ack */ - u8 res5[3]; /* 0xE5 - 0xE7 */ - u8 L2iack0; /* 0xE8 Level n interrupt ack */ - u8 res6[3]; /* 0xE9 - 0xEB */ - u8 L3iack0; /* 0xEC Level n interrupt ack */ - u8 res7[3]; /* 0xED - 0xEF */ - u8 L4iack0; /* 0xF0 Level n interrupt ack */ - u8 res8[3]; /* 0xF1 - 0xF3 */ - u8 L5iack0; /* 0xF4 Level n interrupt ack */ - u8 res9[3]; /* 0xF5 - 0xF7 */ - u8 L6iack0; /* 0xF8 Level n interrupt ack */ - u8 resa[3]; /* 0xF9 - 0xFB */ - u8 L7iack0; /* 0xFC Level n interrupt ack */ - u8 resb[3]; /* 0xFD - 0xFF */ -} int0_t; - -typedef struct int1_ctrl { - /* Interrupt Controller 1 */ - u32 iprh1; /* 0x00 Pending High */ - u32 iprl1; /* 0x04 Pending Low */ - u32 imrh1; /* 0x08 Mask High */ - u32 imrl1; /* 0x0C Mask Low */ - u32 frch1; /* 0x10 Force High */ - u32 frcl1; /* 0x14 Force Low */ -#if defined(CONFIG_SYS_CF_INTC_REG1) - u8 irlr; /* 0x18 */ - u8 iacklpr; /* 0x19 */ - u16 res1[19]; /* 0x1a - 0x3c */ -#else - u16 res1; /* 0x18 */ - u16 icfg1; /* 0x1A Configuration */ - u8 simr1; /* 0x1C Set Interrupt Mask */ - u8 cimr1; /* 0x1D Clear Interrupt Mask */ - u16 res2; /* 0x1E - 0x1F */ - u32 res3[8]; /* 0x20 - 0x3F */ -#endif - u8 icr1[64]; /* 0x40 - 0x7F */ - u32 res4[24]; /* 0x80 - 0xDF */ - u8 swiack1; /* 0xE0 Software Interrupt ack */ - u8 res5[3]; /* 0xE1 - 0xE3 */ - u8 L1iack1; /* 0xE4 Level n interrupt ack */ - u8 res6[3]; /* 0xE5 - 0xE7 */ - u8 L2iack1; /* 0xE8 Level n interrupt ack */ - u8 res7[3]; /* 0xE9 - 0xEB */ - u8 L3iack1; /* 0xEC Level n interrupt ack */ - u8 res8[3]; /* 0xED - 0xEF */ - u8 L4iack1; /* 0xF0 Level n interrupt ack */ - u8 res9[3]; /* 0xF1 - 0xF3 */ - u8 L5iack1; /* 0xF4 Level n interrupt ack */ - u8 resa[3]; /* 0xF5 - 0xF7 */ - u8 L6iack1; /* 0xF8 Level n interrupt ack */ - u8 resb[3]; /* 0xF9 - 0xFB */ - u8 L7iack1; /* 0xFC Level n interrupt ack */ - u8 resc[3]; /* 0xFD - 0xFF */ -} int1_t; - -typedef struct intgack_ctrl1 { - /* Global IACK Registers */ - u8 swiack; /* 0x00 Global Software Interrupt ack */ - u8 res0[0x3]; - u8 gl1iack; /* 0x04 */ - u8 resv1[0x3]; - u8 gl2iack; /* 0x08 */ - u8 res2[0x3]; - u8 gl3iack; /* 0x0C */ - u8 res3[0x3]; - u8 gl4iack; /* 0x10 */ - u8 res4[0x3]; - u8 gl5iack; /* 0x14 */ - u8 res5[0x3]; - u8 gl6iack; /* 0x18 */ - u8 res6[0x3]; - u8 gl7iack; /* 0x1C */ - u8 res7[0x3]; -} intgack_t; - -#define INTC_IPRH_INT63 (0x80000000) -#define INTC_IPRH_INT62 (0x40000000) -#define INTC_IPRH_INT61 (0x20000000) -#define INTC_IPRH_INT60 (0x10000000) -#define INTC_IPRH_INT59 (0x08000000) -#define INTC_IPRH_INT58 (0x04000000) -#define INTC_IPRH_INT57 (0x02000000) -#define INTC_IPRH_INT56 (0x01000000) -#define INTC_IPRH_INT55 (0x00800000) -#define INTC_IPRH_INT54 (0x00400000) -#define INTC_IPRH_INT53 (0x00200000) -#define INTC_IPRH_INT52 (0x00100000) -#define INTC_IPRH_INT51 (0x00080000) -#define INTC_IPRH_INT50 (0x00040000) -#define INTC_IPRH_INT49 (0x00020000) -#define INTC_IPRH_INT48 (0x00010000) -#define INTC_IPRH_INT47 (0x00008000) -#define INTC_IPRH_INT46 (0x00004000) -#define INTC_IPRH_INT45 (0x00002000) -#define INTC_IPRH_INT44 (0x00001000) -#define INTC_IPRH_INT43 (0x00000800) -#define INTC_IPRH_INT42 (0x00000400) -#define INTC_IPRH_INT41 (0x00000200) -#define INTC_IPRH_INT40 (0x00000100) -#define INTC_IPRH_INT39 (0x00000080) -#define INTC_IPRH_INT38 (0x00000040) -#define INTC_IPRH_INT37 (0x00000020) -#define INTC_IPRH_INT36 (0x00000010) -#define INTC_IPRH_INT35 (0x00000008) -#define INTC_IPRH_INT34 (0x00000004) -#define INTC_IPRH_INT33 (0x00000002) -#define INTC_IPRH_INT32 (0x00000001) - -#define INTC_IPRL_INT31 (0x80000000) -#define INTC_IPRL_INT30 (0x40000000) -#define INTC_IPRL_INT29 (0x20000000) -#define INTC_IPRL_INT28 (0x10000000) -#define INTC_IPRL_INT27 (0x08000000) -#define INTC_IPRL_INT26 (0x04000000) -#define INTC_IPRL_INT25 (0x02000000) -#define INTC_IPRL_INT24 (0x01000000) -#define INTC_IPRL_INT23 (0x00800000) -#define INTC_IPRL_INT22 (0x00400000) -#define INTC_IPRL_INT21 (0x00200000) -#define INTC_IPRL_INT20 (0x00100000) -#define INTC_IPRL_INT19 (0x00080000) -#define INTC_IPRL_INT18 (0x00040000) -#define INTC_IPRL_INT17 (0x00020000) -#define INTC_IPRL_INT16 (0x00010000) -#define INTC_IPRL_INT15 (0x00008000) -#define INTC_IPRL_INT14 (0x00004000) -#define INTC_IPRL_INT13 (0x00002000) -#define INTC_IPRL_INT12 (0x00001000) -#define INTC_IPRL_INT11 (0x00000800) -#define INTC_IPRL_INT10 (0x00000400) -#define INTC_IPRL_INT9 (0x00000200) -#define INTC_IPRL_INT8 (0x00000100) -#define INTC_IPRL_INT7 (0x00000080) -#define INTC_IPRL_INT6 (0x00000040) -#define INTC_IPRL_INT5 (0x00000020) -#define INTC_IPRL_INT4 (0x00000010) -#define INTC_IPRL_INT3 (0x00000008) -#define INTC_IPRL_INT2 (0x00000004) -#define INTC_IPRL_INT1 (0x00000002) -#define INTC_IPRL_INT0 (0x00000001) - -#define INTC_IMRLn_MASKALL (0x00000001) - -#define INTC_IRLR(x) (((x) & 0x7F) << 1) -#define INTC_IRLR_MASK (0x01) - -#define INTC_IACKLPR_LVL(x) (((x) & 0x07) << 4) -#define INTC_IACKLPR_LVL_MASK (0x8F) -#define INTC_IACKLPR_PRI(x) ((x) & 0x0F) -#define INTC_IACKLPR_PRI_MASK (0xF0) - -#if defined(CONFIG_SYS_CF_INTC_REG1) -#define INTC_ICR_IL(x) (((x) & 0x07) << 3) -#define INTC_ICR_IL_MASK (0xC7) -#define INTC_ICR_IP(x) ((x) & 0x07) -#define INTC_ICR_IP_MASK (0xF8) -#else -#define INTC_ICR_IL(x) ((x) & 0x07) -#define INTC_ICR_IL_MASK (0xF8) -#endif - -#define INTC_ICONFIG_ELVLPRI_MASK (0x01FF) -#define INTC_ICONFIG_ELVLPRI7 (0x8000) -#define INTC_ICONFIG_ELVLPRI6 (0x4000) -#define INTC_ICONFIG_ELVLPRI5 (0x2000) -#define INTC_ICONFIG_ELVLPRI4 (0x1000) -#define INTC_ICONFIG_ELVLPRI3 (0x0800) -#define INTC_ICONFIG_ELVLPRI2 (0x0400) -#define INTC_ICONFIG_ELVLPRI1 (0x0200) -#define INTC_ICONFIG_EMASK (0x0020) - -#define INTC_SIMR_ALL (0x40) -#define INTC_SIMR(x) ((x) & 0x3F) -#define INTC_SIMR_MASK (0x80) - -#define INTC_CIMR_ALL (0x40) -#define INTC_CIMR(x) ((x) & 0x3F) -#define INTC_CIMR_MASK (0x80) - -#define INTC_CLMASK(x) ((x) & 0x0F) -#define INTC_CLMASK_MASK (0xF0) - -#define INTC_SLMASK(x) ((x) & 0x0F) -#define INTC_SLMASK_MASK (0xF0) - -#endif /* __INTCTRL_H__ */ diff --git a/include/asm-m68k/coldfire/lcd.h b/include/asm-m68k/coldfire/lcd.h deleted file mode 100644 index 66b95b3..0000000 --- a/include/asm-m68k/coldfire/lcd.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * LCD controller Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __LCDC_H__ -#define __LCDC_H__ - -/* LCD module registers */ -typedef struct lcd_ctrl { - u32 ssar; /* 0x00 Screen Start Address Register */ - u32 sr; /* 0x04 LCD Size Register */ - u32 vpw; /* 0x08 Virtual Page Width Register */ - u32 cpr; /* 0x0C Cursor Position Register */ - u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */ - u32 ccmr; /* 0x14 Color Cursor Mapping Register */ - u32 pcr; /* 0x18 Panel Configuration Register */ - u32 hcr; /* 0x1C Horizontal Configuration Register */ - u32 vcr; /* 0x20 Vertical Configuration Register */ - u32 por; /* 0x24 Panning Offset Register */ - u32 scr; /* 0x28 Sharp Configuration Register */ - u32 pccr; /* 0x2C PWM Contrast Control Register */ - u32 dcr; /* 0x30 DMA Control Register */ - u32 rmcr; /* 0x34 Refresh Mode Control Register */ - u32 icr; /* 0x38 Refresh Mode Control Register */ - u32 ier; /* 0x3C Interrupt Enable Register */ - u32 isr; /* 0x40 Interrupt Status Register */ - u32 res[4]; - u32 gwsar; /* 0x50 Graphic Window Start Address Register */ - u32 gwsr; /* 0x54 Graphic Window Size Register */ - u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */ - u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */ - u32 gwpr; /* 0x60 Graphic Window Position Register */ - u32 gwcr; /* 0x64 Graphic Window Control Register */ - u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */ -} lcd_t; - -typedef struct lcdbg_ctrl { - u32 bglut[255]; -} lcdbg_t; - -typedef struct lcdgw_ctrl { - u32 gwlut[255]; -} lcdgw_t; - -/* Bit definitions and macros for LCDC_LSSAR */ -#define LCDC_SSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for LCDC_LSR */ -#define LCDC_SR_XMAX(x) (((x)&0x0000003F)<<20) -#define LCDC_SR_YMAX(x) ((x)&0x000003FF) - -/* Bit definitions and macros for LCDC_LVPWR */ -#define LCDC_VPWR_VPW(x) (((x)&0x000003FF) - -/* Bit definitions and macros for LCDC_LCPR */ -#define LCDC_CPR_CC(x) (((x)&0x00000003)<<30) -#define LCDC_CPR_CC_AND (0xC0000000) -#define LCDC_CPR_CC_XOR (0x80000000) -#define LCDC_CPR_CC_OR (0x40000000) -#define LCDC_CPR_CC_TRANSPARENT (0x00000000) -#define LCDC_CPR_OP (0x10000000) -#define LCDC_CPR_CXP(x) (((x)&0x000003FF)<<16) -#define LCDC_CPR_CYP(x) ((x)&0x000003FF) - -/* Bit definitions and macros for LCDC_LCWHBR */ -#define LCDC_CWHBR_BK_EN (0x80000000) -#define LCDC_CWHBR_CW(x) (((x)&0x0000001F)<<24) -#define LCDC_CWHBR_CH(x) (((x)&0x0000001F)<<16) -#define LCDC_CWHBR_BD(x) ((x)&0x000000FF) - -/* Bit definitions and macros for LCDC_LCCMR */ -#define LCDC_CCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) -#define LCDC_CCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) -#define LCDC_CCMR_CUR_COL_B(x) ((x)&0x0000003F) - -/* Bit definitions and macros for LCDC_LPCR */ -#define LCDC_PCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) -#define LCDC_PCR_MODE_TFT (0xC0000000) -#define LCDC_PCR_MODE_CSTN (0x40000000) -#define LCDC_PCR_MODE_MONOCHROME (0x00000000) -#define LCDC_PCR_TFT (0x80000000) -#define LCDC_PCR_COLOR (0x40000000) -#define LCDC_PCR_PBSIZ(x) (((x)&0x00000003)<<28) -#define LCDC_PCR_PBSIZ_8 (0x30000000) -#define LCDC_PCR_PBSIZ_4 (0x20000000) -#define LCDC_PCR_PBSIZ_2 (0x10000000) -#define LCDC_PCR_PBSIZ_1 (0x00000000) -#define LCDC_PCR_BPIX(x) (((x)&0x00000007)<<25) -#define LCDC_PCR_BPIX_18bpp (0x0C000000) -#define LCDC_PCR_BPIX_16bpp (0x0A000000) -#define LCDC_PCR_BPIX_12bpp (0x08000000) -#define LCDC_PCR_BPIX_8bpp (0x06000000) -#define LCDC_PCR_BPIX_4bpp (0x04000000) -#define LCDC_PCR_BPIX_2bpp (0x02000000) -#define LCDC_PCR_BPIX_1bpp (0x00000000) -#define LCDC_PCR_PIXPOL (0x01000000) -#define LCDC_PCR_FLM (0x00800000) -#define LCDC_PCR_LPPOL (0x00400000) -#define LCDC_PCR_CLKPOL (0x00200000) -#define LCDC_PCR_OEPOL (0x00100000) -#define LCDC_PCR_SCLKIDLE (0x00080000) -#define LCDC_PCR_ENDSEL (0x00040000) -#define LCDC_PCR_SWAP_SEL (0x00020000) -#define LCDC_PCR_REV_VS (0x00010000) -#define LCDC_PCR_ACDSEL (0x00008000) -#define LCDC_PCR_ACD(x) (((x)&0x0000007F)<<8) -#define LCDC_PCR_SCLKSEL (0x00000080) -#define LCDC_PCR_SHARP (0x00000040) -#define LCDC_PCR_PCD(x) ((x)&0x0000003F) - -/* Bit definitions and macros for LCDC_LHCR */ -#define LCDC_HCR_H_WIDTH(x) (((x)&0x0000003F)<<26) -#define LCDC_HCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) -#define LCDC_HCR_H_WAIT_2(x) ((x)&0x000000FF) - -/* Bit definitions and macros for LCDC_LVCR */ -#define LCDC_VCR_V_WIDTH(x) (((x)&0x0000003F)<<26) -#define LCDC_VCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) -#define LCDC_VCR_V_WAIT_2(x) ((x)&0x000000FF) - -/* Bit definitions and macros for LCDC_SCR */ -#define LCDC_SCR_PS_R_DELAY(x) (((x)&0x0000003F) << 26) -#define LCDC_SCR_CLS_R_DELAY(x) (((x)&0x000000FF) << 16) -#define LCDC_SCR_RTG_DELAY(x) (((x)&0x0000000F) << 8) -#define LCDC_SCR_GRAY2(x) (((x)&0x0000000F) << 4) -#define LCDC_SCR_GRAY1(x) ((x)&&0x0000000F) - -/* Bit definitions and macros for LCDC_LPCCR */ -#define LCDC_PCCR_CLS_HI_WID(x) (((x)&0x000001FF)<<16) -#define LCDC_PCCR_LDMSK (0x00008000) -#define LCDC_PCCR_SCR(x) (((x)&0x00000003)<<9) -#define LCDC_PCCR_SCR_LCDCLK (0x00000400) -#define LCDC_PCCR_SCR_PIXCLK (0x00000200) -#define LCDC_PCCR_SCR_LNPULSE (0x00000000) -#define LCDC_PCCR_CC_EN (0x00000100) -#define LCDC_PCCR_PW(x) ((x)&0x000000FF) - -/* Bit definitions and macros for LCDC_LDCR */ -#define LCDC_DCR_BURST (0x80000000) -#define LCDC_DCR_HM(x) (((x)&0x0000001F)<<16) -#define LCDC_DCR_TM(x) ((x)&0x0000001F) - -/* Bit definitions and macros for LCDC_LRMCR */ -#define LCDC_RMCR_SEL_REF (0x00000001) - -/* Bit definitions and macros for LCDC_LICR */ -#define LCDC_ICR_GW_INT_CON (0x00000010) -#define LCDC_ICR_INTSYN (0x00000004) -#define LCDC_ICR_INTCON (0x00000001) - -/* Bit definitions and macros for LCDC_LIER */ -#define LCDC_IER_GW_UDR (0x00000080) -#define LCDC_IER_GW_ERR (0x00000040) -#define LCDC_IER_GW_EOF (0x00000020) -#define LCDC_IER_GW_BOF (0x00000010) -#define LCDC_IER_UDR (0x00000008) -#define LCDC_IER_ERR (0x00000004) -#define LCDC_IER_EOF (0x00000002) -#define LCDC_IER_BOF (0x00000001) - -/* Bit definitions and macros for LCDC_LGWSAR */ -#define LCDC_GWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for LCDC_LGWSR */ -#define LCDC_GWSR_GWW(x) (((x)&0x0000003F)<<20) -#define LCDC_GWSR_GWH(x) ((x)&0x000003FF) - -/* Bit definitions and macros for LCDC_LGWVPWR */ -#define LCDC_GWVPWR_GWVPW(x) ((x)&0x000003FF) - -/* Bit definitions and macros for LCDC_LGWPOR */ -#define LCDC_GWPOR_GWPO(x) ((x)&0x0000001F) - -/* Bit definitions and macros for LCDC_LGWPR */ -#define LCDC_GWPR_GWXP(x) (((x)&0x000003FF)<<16) -#define LCDC_GWPR_GWYP(x) ((x)&0x000003FF) - -/* Bit definitions and macros for LCDC_LGWCR */ -#define LCDC_GWCR_GWAV(x) (((x)&0x000000FF)<<24) -#define LCDC_GWCR_GWCKE (0x00800000) -#define LCDC_LGWCR_GWE (0x00400000) -#define LCDC_LGWCR_GW_RVS (0x00200000) -#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) -#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) -#define LCDC_LGWCR_GWCKB(x) ((x)&0x0000003F) - -/* Bit definitions and macros for LCDC_LGWDCR */ -#define LCDC_LGWDCR_GWBT (0x80000000) -#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) -#define LCDC_LGWDCR_GWTM(x) ((x)&0x0000001F) - -#endif /* __LCDC_H__ */ diff --git a/include/asm-m68k/coldfire/mdha.h b/include/asm-m68k/coldfire/mdha.h deleted file mode 100644 index b6981363..0000000 --- a/include/asm-m68k/coldfire/mdha.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Message Digest Hardware Accelerator Memory Map - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MDHA_H__ -#define __MDHA_H__ - -/* Message Digest Hardware Accelerator */ -typedef struct mdha_ctrl { - u32 mr; /* 0x00 MDHA Mode */ - u32 cr; /* 0x04 Control */ - u32 cmd; /* 0x08 Command */ - u32 sr; /* 0x0C Status */ - u32 isr; /* 0x10 Interrupt Status */ - u32 imr; /* 0x14 Interrupt Mask */ - u32 dsz; /* 0x1C Data Size */ - u32 inp; /* 0x20 Input FIFO */ - u32 res1[3]; /* 0x24 - 0x2F */ - u32 mda0; /* 0x30 Message Digest AO */ - u32 mdb0; /* 0x34 Message Digest BO */ - u32 mdc0; /* 0x38 Message Digest CO */ - u32 mdd0; /* 0x3C Message Digest DO */ - u32 mde0; /* 0x40 Message Digest EO */ - u32 mdsz; /* 0x44 Message Data Size */ - u32 res[10]; /* 0x48 - 0x6F */ - u32 mda1; /* 0x70 Message Digest A1 */ - u32 mdb1; /* 0x74 Message Digest B1 */ - u32 mdc1; /* 0x78 Message Digest C1 */ - u32 mdd1; /* 0x7C Message Digest D1 */ - u32 mde1; /* 0x80 Message Digest E1 */ -} mdha_t; - -#define MDHA_MR_SSL (0x00000400) -#define MDHA_MR_MACFUL (0x00000200) -#define MDHA_MR_SWAP (0x00000100) -#define MDHA_MR_OPAD (0x00000080) -#define MDHA_MR_IPAD (0x00000040) -#define MDHA_MR_INIT (0x00000020) -#define MDHA_MR_MAC(x) (((x) & 0x03) << 3) -#define MDHA_MR_MAC_MASK (0xFFFFFFE7) -#define MDHA_MR_MAC_EHMAC (0x00000010) -#define MDHA_MR_MAC_HMAC (0x00000008) -#define MDHA_MR_MAC_NONE (0x00000000) -#define MDHA_MR_PDATA (0x00000004) -#define MDHA_MR_ALG (0x00000001) - -#define MDHA_CR_DMAL(x) (((x) & 0x1F) << 16) /* 532x */ -#define MDHA_CR_DMAL_MASK (0xFFE0FFFF) /* 532x */ -#define MDHA_CR_END (0x00000004) /* 532x */ -#define MDHA_CR_DMA (0x00000002) /* 532x */ -#define MDHA_CR_IE (0x00000001) - -#define MDHA_CMD_GO (0x00000008) -#define MDHA_CMD_CI (0x00000004) -#define MDHA_CMD_RI (0x00000001) -#define MDHA_CMD_SWR (0x00000001) - -#define MDHA_SR_IFL(x) (((x) & 0xFF) << 16) -#define MDHA_SR_IFL_MASK (0xFF00FFFF) -#define MDHA_SR_APD(x) (((x) & 0x7) << 13) -#define MDHA_SR_APD_MASK (0xFFFF1FFF) -#define MDHA_SR_FS(x) (((x) & 0x7) << 8) -#define MDHA_SR_FS_MASK (0xFFFFF8FF) -#define MDHA_SR_GNW (0x00000080) -#define MDHA_SR_HSH (0x00000040) -#define MDHA_SR_BUSY (0x00000010) -#define MDHA_SR_RD (0x00000008) -#define MDHA_SR_ERR (0x00000004) -#define MDHA_SR_DONE (0x00000002) -#define MDHA_SR_INT (0x00000001) - -#define MDHA_ISR_DRL (0x00000400) /* 532x */ -#define MDHA_ISR_GTDS (0x00000200) -#define MDHA_ISR_ERE (0x00000100) -#define MDHA_ISR_RMDP (0x00000080) -#define MDHA_ISR_DSE (0x00000020) -#define MDHA_ISR_IME (0x00000010) -#define MDHA_ISR_NEIF (0x00000004) -#define MDHA_ISR_IFO (0x00000001) - -#endif /* __MDHA_H__ */ diff --git a/include/asm-m68k/coldfire/pwm.h b/include/asm-m68k/coldfire/pwm.h deleted file mode 100644 index f737d98..0000000 --- a/include/asm-m68k/coldfire/pwm.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Pulse Width Modulation Memory Map - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ATA_H__ -#define __ATA_H__ - -/* Pulse Width Modulation (PWM) */ -typedef struct pwm_ctrl { -#ifdef CONFIG_M5272 - u8 cr0; - u8 res1[3]; - u8 cr1; - u8 res2[3]; - u8 cr2; - u8 res3[7]; - u8 pwr0; - u8 res4[3]; - u8 pwr1; - u8 res5[3]; - u8 pwr2; - u8 res6[7]; -#else - u8 en; /* 0x00 PWM Enable */ - u8 pol; /* 0x01 Polarity */ - u8 clk; /* 0x02 Clock Select */ - u8 prclk; /* 0x03 Prescale Clock Select */ - u8 cae; /* 0x04 Center Align Enable */ - u8 ctl; /* 0x05 Control */ - u16 res1; /* 0x06 - 0x07 */ - u8 scla; /* 0x08 Scale A */ - u8 sclb; /* 0x09 Scale B */ - u16 res2; /* 0x0A - 0x0B */ -#ifdef CONFIG_M5275 - u8 cnt[4]; /* 0x0C Channel n Counter */ - u16 res3; /* 0x10 - 0x11 */ - u8 per[4]; /* 0x14 Channel n Period */ - u16 res4; /* 0x16 - 0x17 */ - u8 dty[4]; /* 0x18 Channel n Duty */ -#else - u8 cnt[8]; /* 0x0C Channel n Counter */ - u8 per[8]; /* 0x14 Channel n Period */ - u8 dty[8]; /* 0x1C Channel n Duty */ - u8 sdn; /* 0x24 Shutdown */ - u8 res3[3]; /* 0x25 - 0x27 */ -#endif /* CONFIG_M5275 */ -#endif /* CONFIG_M5272 */ -} pwm_t; - -#ifdef CONFIG_M5272 - -#define PWM_CR_EN (0x80) -#define PWM_CR_FRC1 (0x40) -#define PWM_CR_LVL (0x20) -#define PWM_CR_CLKSEL(x) ((x) & 0x0F) -#define PWM_CR_CLKSEL_MASK (0xF0) - -#else - -#define PWM_EN_PWMEn(x) (1 << ((x) & 0x07)) -#define PWM_EN_PWMEn_MASK (0xF0) - -#define PWM_POL_PPOLn(x) (1 << ((x) & 0x07)) -#define PWM_POL_PPOLn_MASK (0xF0) - -#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07)) -#define PWM_CLK_PCLKn_MASK (0xF0) - -#define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4) -#define PWM_PRCLK_PCKB_MASK (0x8F) -#define PWM_PRCLK_PCKA(x) ((x) & 0x07) -#define PWM_PRCLK_PCKA_MASK (0xF8) - -#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07)) -#define PWM_CLK_PCLKn_MASK (0xF0) - -#define PWM_CTL_CON67 (0x80) -#define PWM_CTL_CON45 (0x40) -#define PWM_CTL_CON23 (0x20) -#define PWM_CTL_CON01 (0x10) -#define PWM_CTL_PSWAR (0x08) -#define PWM_CTL_PFRZ (0x04) - -#define PWM_SDN_IF (0x80) -#define PWM_SDN_IE (0x40) -#define PWM_SDN_RESTART (0x20) -#define PWM_SDN_LVL (0x10) -#define PWM_SDN_PWM7IN (0x04) -#define PWM_SDN_PWM7IL (0x02) -#define PWM_SDN_SDNEN (0x01) - -#endif /* CONFIG_M5272 */ - -#endif /* __ATA_H__ */ diff --git a/include/asm-m68k/coldfire/qspi.h b/include/asm-m68k/coldfire/qspi.h deleted file mode 100644 index 8bcd2e4..0000000 --- a/include/asm-m68k/coldfire/qspi.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Queue Serial Peripheral Interface Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __QSPI_H__ -#define __QSPI_H__ - -/* QSPI module registers */ -typedef struct qspi_ctrl { - u16 mr; /* 0x00 Mode */ - u16 res1; - u16 dlyr; /* 0x04 Delay */ - u16 res2; - u16 wr; /* 0x08 Wrap */ - u16 res3; - u16 ir; /* 0x0C Interrupt */ - u16 res4; - u16 ar; /* 0x10 Address */ - u16 res5; - u16 dr; /* 0x14 Data */ - u16 res6; -} qspi_t; - -/* MR */ -#define QSPI_QMR_MSTR (0x8000) -#define QSPI_QMR_DOHIE (0x4000) -#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define QSPI_QMR_BITS_MASK (0xC3FF) -#define QSPI_QMR_BITS_8 (0x2000) -#define QSPI_QMR_BITS_9 (0x2400) -#define QSPI_QMR_BITS_10 (0x2800) -#define QSPI_QMR_BITS_11 (0x2C00) -#define QSPI_QMR_BITS_12 (0x3000) -#define QSPI_QMR_BITS_13 (0x3400) -#define QSPI_QMR_BITS_14 (0x3800) -#define QSPI_QMR_BITS_15 (0x3C00) -#define QSPI_QMR_BITS_16 (0x0000) -#define QSPI_QMR_CPOL (0x0200) -#define QSPI_QMR_CPHA (0x0100) -#define QSPI_QMR_BAUD(x) ((x)&0x00FF) -#define QSPI_QMR_BAUD_MASK (0xFF00) - -/* DLYR */ -#define QSPI_QDLYR_SPE (0x8000) -#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define QSPI_QDLYR_QCD_MASK (0x80FF) -#define QSPI_QDLYR_DTL(x) ((x)&0x00FF) -#define QSPI_QDLYR_DTL_MASK (0xFF00) - -/* WR */ -#define QSPI_QWR_HALT (0x8000) -#define QSPI_QWR_WREN (0x4000) -#define QSPI_QWR_WRTO (0x2000) -#define QSPI_QWR_CSIV (0x1000) -#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define QSPI_QWR_ENDQP_MASK (0xF0FF) -#define QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) -#define QSPI_QWR_CPTQP_MASK (0xFF0F) -#define QSPI_QWR_NEWQP(x) ((x)&0x000F) -#define QSPI_QWR_NEWQP_MASK (0xFFF0) - -/* IR */ -#define QSPI_QIR_WCEFB (0x8000) -#define QSPI_QIR_ABRTB (0x4000) -#define QSPI_QIR_ABRTL (0x1000) -#define QSPI_QIR_WCEFE (0x0800) -#define QSPI_QIR_ABRTE (0x0400) -#define QSPI_QIR_SPIFE (0x0100) -#define QSPI_QIR_WCEF (0x0008) -#define QSPI_QIR_ABRT (0x0004) -#define QSPI_QIR_SPIF (0x0001) - -/* AR */ -#define QSPI_QAR_ADDR(x) ((x)&0x003F) -#define QSPI_QAR_ADDR_MASK (0xFFC0) -#define QSPI_QAR_TRANS (0x0000) -#define QSPI_QAR_RECV (0x0010) -#define QSPI_QAR_CMD (0x0020) - -/* DR */ -#define QSPI_QDR_CONT (0x8000) -#define QSPI_QDR_BITSE (0x4000) -#define QSPI_QDR_DT (0x2000) -#define QSPI_QDR_DSCK (0x1000) -#define QSPI_QDR_QSPI_CS3 (0x0800) -#define QSPI_QDR_QSPI_CS2 (0x0400) -#define QSPI_QDR_QSPI_CS1 (0x0200) -#define QSPI_QDR_QSPI_CS0 (0x0100) - -#endif /* __QSPI_H__ */ diff --git a/include/asm-m68k/coldfire/rng.h b/include/asm-m68k/coldfire/rng.h deleted file mode 100644 index 1eefc56..0000000 --- a/include/asm-m68k/coldfire/rng.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * RNG Memory Map - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __RNG_H__ -#define __RNG_H__ - -/* Random Number Generator */ -typedef struct rng_ctrl { - u32 cr; /* 0x00 Control */ - u32 sr; /* 0x04 Status */ - u32 er; /* 0x08 Entropy */ - u32 out; /* 0x0C Output FIFO */ -} rng_t; - -#define RNG_CR_SLM (0x00000010) /* Sleep mode - 5445x */ -#define RNG_CR_CI (0x00000008) /* Clear interrupt */ -#define RNG_CR_IM (0x00000004) /* Interrupt mask */ -#define RNG_CR_HA (0x00000002) /* High assurance */ -#define RNG_CR_GO (0x00000001) /* Go bit */ - -#define RNG_SR_OFS(x) (((x) & 0x000000FF) << 16) -#define RNG_SR_OFS_MASK (0xFF00FFFF) -#define RNG_SR_OFL(x) (((x) & 0x000000FF) << 8) -#define RNG_SR_OFL_MASK (0xFFFF00FF) -#define RNG_SR_EI (0x00000008) -#define RNG_SR_FUF (0x00000004) -#define RNG_SR_LRS (0x00000002) -#define RNG_SR_SV (0x00000001) - -#endif /* __RNG_H__ */ diff --git a/include/asm-m68k/coldfire/skha.h b/include/asm-m68k/coldfire/skha.h deleted file mode 100644 index bd6b5af..0000000 --- a/include/asm-m68k/coldfire/skha.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Symmetric Key Hardware Accelerator Memory Map - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SKHA_H__ -#define __SKHA_H__ - -typedef struct skha_ctrl { - u32 mr; /* 0x00 Mode */ - u32 cr; /* 0x04 Control */ - u32 cmr; /* 0x08 Command */ - u32 sr; /* 0x0C Status */ - u32 esr; /* 0x10 Error Status */ - u32 emr; /* 0x14 Error Status Mask Register) */ - u32 ksr; /* 0x18 Key Size */ - u32 dsr; /* 0x1C Data Size */ - u32 in; /* 0x20 Input FIFO */ - u32 out; /* 0x24 Output FIFO */ - u32 res1[2]; /* 0x28 - 0x2F */ - u32 kdr1; /* 0x30 Key Data 1 */ - u32 kdr2; /* 0x34 Key Data 2 */ - u32 kdr3; /* 0x38 Key Data 3 */ - u32 kdr4; /* 0x3C Key Data 4 */ - u32 kdr5; /* 0x40 Key Data 5 */ - u32 kdr6; /* 0x44 Key Data 6 */ - u32 res2[10]; /* 0x48 - 0x6F */ - u32 c1; /* 0x70 Context 1 */ - u32 c2; /* 0x74 Context 2 */ - u32 c3; /* 0x78 Context 3 */ - u32 c4; /* 0x7C Context 4 */ - u32 c5; /* 0x80 Context 5 */ - u32 c6; /* 0x84 Context 6 */ - u32 c7; /* 0x88 Context 7 */ - u32 c8; /* 0x8C Context 8 */ - u32 c9; /* 0x90 Context 9 */ - u32 c10; /* 0x94 Context 10 */ - u32 c11; /* 0x98 Context 11 */ - u32 c12; /* 0x9C Context 12 - 5235, 5271, 5272 */ -} skha_t; - -#ifdef CONFIG_MCF532x -#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 9) -#define SKHA_MODE_CTRM_MASK (0xFFFFE1FF) -#define SKHA_MODE_DKP (0x00000100) -#else -#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 8) -#define SKHA_MODE_CTRM_MASK (0xFFFFF0FF) -#define SKHA_MODE_DKP (0x00000080) -#endif -#define SKHA_MODE_CM(x) (((x) & 0x03) << 3) -#define SKHA_MODE_CM_MASK (0xFFFFFFE7) -#define SKHA_MODE_DIR (0x00000004) -#define SKHA_MODE_ALG(x) ((x) & 0x03) -#define SKHA_MODE_ALG_MASK (0xFFFFFFFC) - -#define SHKA_CR_ODMAL(x) (((x) & 0x3F) << 24) -#define SHKA_CR_ODMAL_MASK (0xC0FFFFFF) -#define SHKA_CR_IDMAL(x) (((x) & 0x3F) << 16) -#define SHKA_CR_IDMAL_MASK (0xFFC0FFFF) -#define SHKA_CR_END (0x00000008) -#define SHKA_CR_ODMA (0x00000004) -#define SHKA_CR_IDMA (0x00000002) -#define SKHA_CR_IE (0x00000001) - -#define SKHA_CMR_GO (0x00000008) -#define SKHA_CMR_CI (0x00000004) -#define SKHA_CMR_RI (0x00000002) -#define SKHA_CMR_SWR (0x00000001) - -#define SKHA_SR_OFL(x) (((x) & 0xFF) << 24) -#define SKHA_SR_OFL_MASK (0x00FFFFFF) -#define SKHA_SR_IFL(x) (((x) & 0xFF) << 16) -#define SKHA_SR_IFL_MASK (0xFF00FFFF) -#define SKHA_SR_AESES(x) (((x) & 0x1F) << 11) -#define SKHA_SR_AESES_MASK (0xFFFF07FF) -#define SKHA_SR_DESES(x) (((x) & 0x7) << 8) -#define SKHA_SR_DESES_MASK (0xFFFFF8FF) -#define SKHA_SR_BUSY (0x00000010) -#define SKHA_SR_RD (0x00000008) -#define SKHA_SR_ERR (0x00000004) -#define SKHA_SR_DONE (0x00000002) -#define SKHA_SR_INT (0x00000001) - -#define SHKA_ESE_DRL (0x00000800) -#define SKHA_ESR_KRE (0x00000400) -#define SKHA_ESR_KPE (0x00000200) -#define SKHA_ESR_ERE (0x00000100) -#define SKHA_ESR_RMDP (0x00000080) -#define SKHA_ESR_KSE (0x00000040) -#define SKHA_ESR_DSE (0x00000020) -#define SKHA_ESR_IME (0x00000010) -#define SKHA_ESR_NEOF (0x00000008) -#define SKHA_ESR_NEIF (0x00000004) -#define SKHA_ESR_OFU (0x00000002) -#define SKHA_ESR_IFO (0x00000001) - -#define SKHA_KSR_SZ(x) ((x) & 0x3F) -#define SKHA_KSR_SZ_MASK (0xFFFFFFC0) - -#endif /* __SKHA_H__ */ diff --git a/include/asm-m68k/coldfire/ssi.h b/include/asm-m68k/coldfire/ssi.h deleted file mode 100644 index b3dfbfa..0000000 --- a/include/asm-m68k/coldfire/ssi.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * SSI Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SSI_H__ -#define __SSI_H__ - -typedef struct ssi { - u32 tx0; - u32 tx1; - u32 rx0; - u32 rx1; - u32 cr; - u32 isr; - u32 ier; - u32 tcr; - u32 rcr; - u32 ccr; - u8 resv0[0x4]; - u32 fcsr; - u8 resv1[0x8]; - u32 acr; - u32 acadd; - u32 acdat; - u32 atag; - u32 tmask; - u32 rmask; -} ssi_t; - -#define SSI_CR_CIS (0x00000200) -#define SSI_CR_TCH (0x00000100) -#define SSI_CR_MCE (0x00000080) -#define SSI_CR_I2S_MASK (0xFFFFFF9F) -#define SSI_CR_I2S_SLAVE (0x00000040) -#define SSI_CR_I2S_MASTER (0x00000020) -#define SSI_CR_I2S_NORMAL (0x00000000) -#define SSI_CR_SYN (0x00000010) -#define SSI_CR_NET (0x00000008) -#define SSI_CR_RE (0x00000004) -#define SSI_CR_TE (0x00000002) -#define SSI_CR_SSI_EN (0x00000001) - -#define SSI_ISR_CMDAU (0x00040000) -#define SSI_ISR_CMDDU (0x00020000) -#define SSI_ISR_RXT (0x00010000) -#define SSI_ISR_RDR1 (0x00008000) -#define SSI_ISR_RDR0 (0x00004000) -#define SSI_ISR_TDE1 (0x00002000) -#define SSI_ISR_TDE0 (0x00001000) -#define SSI_ISR_ROE1 (0x00000800) -#define SSI_ISR_ROE0 (0x00000400) -#define SSI_ISR_TUE1 (0x00000200) -#define SSI_ISR_TUE0 (0x00000100) -#define SSI_ISR_TFS (0x00000080) -#define SSI_ISR_RFS (0x00000040) -#define SSI_ISR_TLS (0x00000020) -#define SSI_ISR_RLS (0x00000010) -#define SSI_ISR_RFF1 (0x00000008) -#define SSI_ISR_RFF0 (0x00000004) -#define SSI_ISR_TFE1 (0x00000002) -#define SSI_ISR_TFE0 (0x00000001) - -#define SSI_IER_RDMAE (0x00400000) -#define SSI_IER_RIE (0x00200000) -#define SSI_IER_TDMAE (0x00100000) -#define SSI_IER_TIE (0x00080000) -#define SSI_IER_CMDAU (0x00040000) -#define SSI_IER_CMDU (0x00020000) -#define SSI_IER_RXT (0x00010000) -#define SSI_IER_RDR1 (0x00008000) -#define SSI_IER_RDR0 (0x00004000) -#define SSI_IER_TDE1 (0x00002000) -#define SSI_IER_TDE0 (0x00001000) -#define SSI_IER_ROE1 (0x00000800) -#define SSI_IER_ROE0 (0x00000400) -#define SSI_IER_TUE1 (0x00000200) -#define SSI_IER_TUE0 (0x00000100) -#define SSI_IER_TFS (0x00000080) -#define SSI_IER_RFS (0x00000040) -#define SSI_IER_TLS (0x00000020) -#define SSI_IER_RLS (0x00000010) -#define SSI_IER_RFF1 (0x00000008) -#define SSI_IER_RFF0 (0x00000004) -#define SSI_IER_TFE1 (0x00000002) -#define SSI_IER_TFE0 (0x00000001) - -#define SSI_TCR_TXBIT0 (0x00000200) -#define SSI_TCR_TFEN1 (0x00000100) -#define SSI_TCR_TFEN0 (0x00000080) -#define SSI_TCR_TFDIR (0x00000040) -#define SSI_TCR_TXDIR (0x00000020) -#define SSI_TCR_TSHFD (0x00000010) -#define SSI_TCR_TSCKP (0x00000008) -#define SSI_TCR_TFSI (0x00000004) -#define SSI_TCR_TFSL (0x00000002) -#define SSI_TCR_TEFS (0x00000001) - -#define SSI_RCR_RXEXT (0x00000400) -#define SSI_RCR_RXBIT0 (0x00000200) -#define SSI_RCR_RFEN1 (0x00000100) -#define SSI_RCR_RFEN0 (0x00000080) -#define SSI_RCR_RSHFD (0x00000010) -#define SSI_RCR_RSCKP (0x00000008) -#define SSI_RCR_RFSI (0x00000004) -#define SSI_RCR_RFSL (0x00000002) -#define SSI_RCR_REFS (0x00000001) - -#define SSI_CCR_DIV2 (0x00040000) -#define SSI_CCR_PSR (0x00020000) -#define SSI_CCR_WL(x) (((x) & 0x0F) << 13) -#define SSI_CCR_WL_MASK (0xFFFE1FFF) -#define SSI_CCR_DC(x) (((x)& 0x1F) << 8) -#define SSI_CCR_DC_MASK (0xFFFFE0FF) -#define SSI_CCR_PM(x) ((x) & 0xFF) -#define SSI_CCR_PM_MASK (0xFFFFFF00) - -#define SSI_FCSR_RFCNT1(x) (((x) & 0x0F) << 28) -#define SSI_FCSR_RFCNT1_MASK (0x0FFFFFFF) -#define SSI_FCSR_TFCNT1(x) (((x) & 0x0F) << 24) -#define SSI_FCSR_TFCNT1_MASK (0xF0FFFFFF) -#define SSI_FCSR_RFWM1(x) (((x) & 0x0F) << 20) -#define SSI_FCSR_RFWM1_MASK (0xFF0FFFFF) -#define SSI_FCSR_TFWM1(x) (((x) & 0x0F) << 16) -#define SSI_FCSR_TFWM1_MASK (0xFFF0FFFF) -#define SSI_FCSR_RFCNT0(x) (((x) & 0x0F) << 12) -#define SSI_FCSR_RFCNT0_MASK (0xFFFF0FFF) -#define SSI_FCSR_TFCNT0(x) (((x) & 0x0F) << 8) -#define SSI_FCSR_TFCNT0_MASK (0xFFFFF0FF) -#define SSI_FCSR_RFWM0(x) (((x) & 0x0F) << 4) -#define SSI_FCSR_RFWM0_MASK (0xFFFFFF0F) -#define SSI_FCSR_TFWM0(x) ((x) & 0x0F) -#define SSI_FCSR_TFWM0_MASK (0xFFFFFFF0) - -#define SSI_ACR_FRDIV(x) (((x) & 0x3F) << 5) -#define SSI_ACR_FRDIV_MASK (0xFFFFF81F) -#define SSI_ACR_WR (0x00000010) -#define SSI_ACR_RD (0x00000008) -#define SSI_ACR_TIF (0x00000004) -#define SSI_ACR_FV (0x00000002) -#define SSI_ACR_AC97EN (0x00000001) - -#define SSI_ACADD_SSI_ACADD(x) ((x) & 0x0007FFFF) - -#define SSI_ACDAT_SSI_ACDAT(x) ((x) & 0x0007FFFF) - -#define SSI_ATAG_DDI_ATAG(x) ((x) & 0x0000FFFF) - -#endif /* __SSI_H__ */ diff --git a/include/asm-m68k/config.h b/include/asm-m68k/config.h deleted file mode 100644 index 36438be..0000000 --- a/include/asm-m68k/config.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -#define CONFIG_LMB - -#endif diff --git a/include/asm-m68k/errno.h b/include/asm-m68k/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/include/asm-m68k/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h deleted file mode 100644 index 49311e5..0000000 --- a/include/asm-m68k/fec.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - * fec.h -- Fast Ethernet Controller definitions - * - * Some definitions copied from commproc.h for MPC8xx: - * MPC8xx Communication Processor Module. - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * Add FEC Structure and definitions - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef fec_h -#define fec_h - -/* Buffer descriptors used FEC. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ - -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_RO1 ((ushort)0x4000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_RO2 BD_ENET_RX_INTR -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) -#define BD_ENET_RX_MC ((ushort)0x0040) -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_TR BD_ENET_RX_CL -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_TO1 BD_ENET_TX_PAD -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_ -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_ABC BD_ENET_TX_DEF -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/********************************************************************* -* Fast Ethernet Controller (FEC) -*********************************************************************/ -/* FEC private information */ -struct fec_info_s { - int index; - u32 iobase; - u32 pinmux; - u32 miibase; - int phy_addr; - int dup_spd; - char *phy_name; - int phyname_init; - cbd_t *rxbd; /* Rx BD */ - cbd_t *txbd; /* Tx BD */ - uint rxIdx; - uint txIdx; - char *txbuf; - int initialized; - struct fec_info_s *next; -}; - -#ifdef CONFIG_MCFFEC -/* Register read/write struct */ -typedef struct fec { -#ifdef CONFIG_M5272 - u32 ecr; /* 0x00 */ - u32 eir; /* 0x04 */ - u32 eimr; /* 0x08 */ - u32 ivsr; /* 0x0C */ - u32 rdar; /* 0x10 */ - u32 tdar; /* 0x14 */ - u8 resv1[0x28]; /* 0x18 */ - u32 mmfr; /* 0x40 */ - u32 mscr; /* 0x44 */ - u8 resv2[0x44]; /* 0x48 */ - u32 frbr; /* 0x8C */ - u32 frsr; /* 0x90 */ - u8 resv3[0x10]; /* 0x94 */ - u32 tfwr; /* 0xA4 */ - u32 res4; /* 0xA8 */ - u32 tfsr; /* 0xAC */ - u8 resv4[0x50]; /* 0xB0 */ - u32 opd; /* 0x100 - dummy */ - u32 rcr; /* 0x104 */ - u32 mibc; /* 0x108 */ - u8 resv5[0x38]; /* 0x10C */ - u32 tcr; /* 0x144 */ - u8 resv6[0x270]; /* 0x148 */ - u32 iaur; /* 0x3B8 - dummy */ - u32 ialr; /* 0x3BC - dummy */ - u32 palr; /* 0x3C0 */ - u32 paur; /* 0x3C4 */ - u32 gaur; /* 0x3C8 */ - u32 galr; /* 0x3CC */ - u32 erdsr; /* 0x3D0 */ - u32 etdsr; /* 0x3D4 */ - u32 emrbr; /* 0x3D8 */ - u8 resv12[0x74]; /* 0x18C */ -#else - u8 resv0[0x4]; - u32 eir; - u32 eimr; - u8 resv1[0x4]; - u32 rdar; - u32 tdar; - u8 resv2[0xC]; - u32 ecr; - u8 resv3[0x18]; - u32 mmfr; - u32 mscr; - u8 resv4[0x1C]; - u32 mibc; - u8 resv5[0x1C]; - u32 rcr; - u8 resv6[0x3C]; - u32 tcr; - u8 resv7[0x1C]; - u32 palr; - u32 paur; - u32 opd; - u8 resv8[0x28]; - u32 iaur; - u32 ialr; - u32 gaur; - u32 galr; - u8 resv9[0x1C]; - u32 tfwr; - u8 resv10[0x4]; - u32 frbr; - u32 frsr; - u8 resv11[0x2C]; - u32 erdsr; - u32 etdsr; - u32 emrbr; - u8 resv12[0x74]; -#endif - - u32 rmon_t_drop; - u32 rmon_t_packets; - u32 rmon_t_bc_pkt; - u32 rmon_t_mc_pkt; - u32 rmon_t_crc_align; - u32 rmon_t_undersize; - u32 rmon_t_oversize; - u32 rmon_t_frag; - u32 rmon_t_jab; - u32 rmon_t_col; - u32 rmon_t_p64; - u32 rmon_t_p65to127; - u32 rmon_t_p128to255; - u32 rmon_t_p256to511; - u32 rmon_t_p512to1023; - u32 rmon_t_p1024to2047; - u32 rmon_t_p_gte2048; - u32 rmon_t_octets; - - u32 ieee_t_drop; - u32 ieee_t_frame_ok; - u32 ieee_t_1col; - u32 ieee_t_mcol; - u32 ieee_t_def; - u32 ieee_t_lcol; - u32 ieee_t_excol; - u32 ieee_t_macerr; - u32 ieee_t_cserr; - u32 ieee_t_sqe; - u32 ieee_t_fdxfc; - u32 ieee_t_octets_ok; - u8 resv13[0x8]; - - u32 rmon_r_drop; - u32 rmon_r_packets; - u32 rmon_r_bc_pkt; - u32 rmon_r_mc_pkt; - u32 rmon_r_crc_align; - u32 rmon_r_undersize; - u32 rmon_r_oversize; - u32 rmon_r_frag; - u32 rmon_r_jab; - u32 rmon_r_resvd_0; - u32 rmon_r_p64; - u32 rmon_r_p65to127; - u32 rmon_r_p128to255; - u32 rmon_r_p256to511; - u32 rmon_r_p512to1023; - u32 rmon_r_p1024to2047; - u32 rmon_r_p_gte2048; - u32 rmon_r_octets; - - u32 ieee_r_drop; - u32 ieee_r_frame_ok; - u32 ieee_r_crc; - u32 ieee_r_align; - u32 ieee_r_macerr; - u32 ieee_r_fdxfc; - u32 ieee_r_octets_ok; -} fec_t; -#endif /* CONFIG_MCFFEC */ - -/********************************************************************* -* Fast Ethernet Controller (FEC) -*********************************************************************/ -/* Bit definitions and macros for FEC_EIR */ -#define FEC_EIR_CLEAR_ALL (0xFFF80000) -#define FEC_EIR_HBERR (0x80000000) -#define FEC_EIR_BABR (0x40000000) -#define FEC_EIR_BABT (0x20000000) -#define FEC_EIR_GRA (0x10000000) -#define FEC_EIR_TXF (0x08000000) -#define FEC_EIR_TXB (0x04000000) -#define FEC_EIR_RXF (0x02000000) -#define FEC_EIR_RXB (0x01000000) -#define FEC_EIR_MII (0x00800000) -#define FEC_EIR_EBERR (0x00400000) -#define FEC_EIR_LC (0x00200000) -#define FEC_EIR_RL (0x00100000) -#define FEC_EIR_UN (0x00080000) - -/* Bit definitions and macros for FEC_RDAR */ -#define FEC_RDAR_R_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for FEC_TDAR */ -#define FEC_TDAR_X_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for FEC_ECR */ -#define FEC_ECR_ETHER_EN (0x00000002) -#define FEC_ECR_RESET (0x00000001) - -/* Bit definitions and macros for FEC_MMFR */ -#define FEC_MMFR_DATA(x) (((x)&0xFFFF)) -#define FEC_MMFR_ST(x) (((x)&0x03)<<30) -#define FEC_MMFR_ST_01 (0x40000000) -#define FEC_MMFR_OP_RD (0x20000000) -#define FEC_MMFR_OP_WR (0x10000000) -#define FEC_MMFR_PA(x) (((x)&0x1F)<<23) -#define FEC_MMFR_RA(x) (((x)&0x1F)<<18) -#define FEC_MMFR_TA(x) (((x)&0x03)<<16) -#define FEC_MMFR_TA_10 (0x00020000) - -/* Bit definitions and macros for FEC_MSCR */ -#define FEC_MSCR_DIS_PREAMBLE (0x00000080) -#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1) - -/* Bit definitions and macros for FEC_MIBC */ -#define FEC_MIBC_MIB_DISABLE (0x80000000) -#define FEC_MIBC_MIB_IDLE (0x40000000) - -/* Bit definitions and macros for FEC_RCR */ -#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16) -#define FEC_RCR_FCE (0x00000020) -#define FEC_RCR_BC_REJ (0x00000010) -#define FEC_RCR_PROM (0x00000008) -#define FEC_RCR_MII_MODE (0x00000004) -#define FEC_RCR_DRT (0x00000002) -#define FEC_RCR_LOOP (0x00000001) - -/* Bit definitions and macros for FEC_TCR */ -#define FEC_TCR_RFC_PAUSE (0x00000010) -#define FEC_TCR_TFC_PAUSE (0x00000008) -#define FEC_TCR_FDEN (0x00000004) -#define FEC_TCR_HBC (0x00000002) -#define FEC_TCR_GTS (0x00000001) - -/* Bit definitions and macros for FEC_PAUR */ -#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16) -#define FEC_PAUR_TYPE(x) ((x)&0xFFFF) - -/* Bit definitions and macros for FEC_OPD */ -#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) -#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for FEC_TFWR */ -#define FEC_TFWR_X_WMRK(x) ((x)&0x03) -#define FEC_TFWR_X_WMRK_64 (0x01) -#define FEC_TFWR_X_WMRK_128 (0x02) -#define FEC_TFWR_X_WMRK_192 (0x03) - -/* Bit definitions and macros for FEC_FRBR */ -#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2) - -/* Bit definitions and macros for FEC_FRSR */ -#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2) - -/* Bit definitions and macros for FEC_ERDSR */ -#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for FEC_ETDSR */ -#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for FEC_EMRBR */ -#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) - -#define FEC_RESET_DELAY 100 -#define FEC_RX_TOUT 100 - -int fecpin_setclear(struct eth_device *dev, int setclear); - -#ifdef CONFIG_SYS_DISCOVER_PHY -void __mii_init(void); -uint mii_send(uint mii_cmd); -int mii_discover_phy(struct eth_device *dev); -int mcffec_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int mcffec_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); -#endif - -#endif /* fec_h */ diff --git a/include/asm-m68k/fsl_i2c.h b/include/asm-m68k/fsl_i2c.h deleted file mode 100644 index 2bc9bf4..0000000 --- a/include/asm-m68k/fsl_i2c.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Freescale I2C Controller - * - * Copyright 2006 Freescale Semiconductor, Inc. - * - * Based on earlier versions by Gleb Natapov , - * Xianghua Xiao , Eran Liberty (liberty@freescale.com), - * and Jeff Brown. - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_FSL_I2C_H_ -#define _ASM_FSL_I2C_H_ - -#include - -typedef struct fsl_i2c { - - u8 adr; /* I2C slave address */ - u8 res0[3]; -#define I2C_ADR 0xFE -#define I2C_ADR_SHIFT 1 -#define I2C_ADR_RES ~(I2C_ADR) - - u8 fdr; /* I2C frequency divider register */ - u8 res1[3]; -#define IC2_FDR 0x3F -#define IC2_FDR_SHIFT 0 -#define IC2_FDR_RES ~(IC2_FDR) - - u8 cr; /* I2C control redister */ - u8 res2[3]; -#define I2C_CR_MEN 0x80 -#define I2C_CR_MIEN 0x40 -#define I2C_CR_MSTA 0x20 -#define I2C_CR_MTX 0x10 -#define I2C_CR_TXAK 0x08 -#define I2C_CR_RSTA 0x04 -#define I2C_CR_BCST 0x01 - - u8 sr; /* I2C status register */ - u8 res3[3]; -#define I2C_SR_MCF 0x80 -#define I2C_SR_MAAS 0x40 -#define I2C_SR_MBB 0x20 -#define I2C_SR_MAL 0x10 -#define I2C_SR_BCSTM 0x08 -#define I2C_SR_SRW 0x04 -#define I2C_SR_MIF 0x02 -#define I2C_SR_RXAK 0x01 - - u8 dr; /* I2C data register */ - u8 res4[3]; -#define I2C_DR 0xFF -#define I2C_DR_SHIFT 0 -#define I2C_DR_RES ~(I2C_DR) -} fsl_i2c_t; - -#endif /* _ASM_I2C_H_ */ diff --git a/include/asm-m68k/fsl_mcdmafec.h b/include/asm-m68k/fsl_mcdmafec.h deleted file mode 100644 index 7e54056..0000000 --- a/include/asm-m68k/fsl_mcdmafec.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef fsl_mcdmafec_h -#define fsl_mcdmafec_h - -/* Re-use of the definitions */ -#include - -typedef struct fecdma { - u32 rsvd0; /* 0x000 */ - u32 eir; /* 0x004 */ - u32 eimr; /* 0x008 */ - u32 rsvd1[6]; /* 0x00C - 0x023 */ - u32 ecr; /* 0x024 */ - u32 rsvd2[6]; /* 0x028 - 0x03F */ - u32 mmfr; /* 0x040 */ - u32 mscr; /* 0x044 */ - u32 rsvd3[7]; /* 0x048 - 0x063 */ - u32 mibc; /* 0x064 */ - u32 rsvd4[7]; /* 0x068 - 0x083 */ - u32 rcr; /* 0x084 */ - u32 rhr; /* 0x088 */ - u32 rsvd5[14]; /* 0x08C - 0x0C3 */ - u32 tcr; /* 0x0C4 */ - u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */ - u32 palr; /* 0x0E4 */ - u32 paur; /* 0x0E8 */ - u32 opd; /* 0x0EC */ - u32 rsvd7[10]; /* 0x0F0 - 0x117 */ - u32 iaur; /* 0x118 */ - u32 ialr; /* 0x11C */ - u32 gaur; /* 0x120 */ - u32 galr; /* 0x124 */ - u32 rsvd8[7]; /* 0x128 - 0x143 */ - u32 tfwr; /* 0x144 */ - u32 rsvd9[14]; /* 0x148 - 0x17F */ - u32 fmc; /* 0x180 */ - u32 rfdr; /* 0x184 */ - u32 rfsr; /* 0x188 */ - u32 rfcr; /* 0x18C */ - u32 rlrfp; /* 0x190 */ - u32 rlwfp; /* 0x194 */ - u32 rfar; /* 0x198 */ - u32 rfrp; /* 0x19C */ - u32 rfwp; /* 0x1A0 */ - u32 tfdr; /* 0x1A4 */ - u32 tfsr; /* 0x1A8 */ - u32 tfcr; /* 0x1AC */ - u32 tlrfp; /* 0x1B0 */ - u32 tlwfp; /* 0x1B4 */ - u32 tfar; /* 0x1B8 */ - u32 tfrp; /* 0x1BC */ - u32 tfwp; /* 0x1C0 */ - u32 frst; /* 0x1C4 */ - u32 ctcwr; /* 0x1C8 */ -} fecdma_t; - -struct fec_info_dma { - int index; - u32 iobase; - u32 pinmux; - u32 miibase; - int phy_addr; - int dup_spd; - char *phy_name; - int phyname_init; - cbd_t *rxbd; /* Rx BD */ - cbd_t *txbd; /* Tx BD */ - uint rxIdx; - uint txIdx; - char *txbuf; - int initialized; - struct fec_info_dma *next; - - u16 rxTask; /* DMA receive Task Number */ - u16 txTask; /* DMA Transmit Task Number */ - u16 rxPri; /* DMA Receive Priority */ - u16 txPri; /* DMA Transmit Priority */ - u16 rxInit; /* DMA Receive Initiator */ - u16 txInit; /* DMA Transmit Initiator */ - u16 usedTbdIdx; /* next transmit BD to clean */ - u16 cleanTbdNum; /* the number of available transmit BDs */ -}; - -/* Bit definitions and macros for IEVENT */ -#define FEC_EIR_TXERR (0x00040000) -#define FEC_EIR_RXERR (0x00020000) -#undef FEC_EIR_CLEAR_ALL -#define FEC_EIR_CLEAR_ALL (0xFFFE0000) - -/* Bit definitions and macros for R_HASH */ -#define FEC_RHASH_FCE_DC (0x80000000) -#define FEC_RHASH_MULTCAST (0x40000000) -#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24) - -/* Bit definitions and macros for FEC_TFWR */ -#undef FEC_TFWR_X_WMRK -#undef FEC_TFWR_X_WMRK_64 -#undef FEC_TFWR_X_WMRK_128 -#undef FEC_TFWR_X_WMRK_192 - -#define FEC_TFWR_X_WMRK(x) ((x)&0x0F) -#define FEC_TFWR_X_WMRK_64 (0x00) -#define FEC_TFWR_X_WMRK_128 (0x01) -#define FEC_TFWR_X_WMRK_192 (0x02) -#define FEC_TFWR_X_WMRK_256 (0x03) -#define FEC_TFWR_X_WMRK_320 (0x04) -#define FEC_TFWR_X_WMRK_384 (0x05) -#define FEC_TFWR_X_WMRK_448 (0x06) -#define FEC_TFWR_X_WMRK_512 (0x07) -#define FEC_TFWR_X_WMRK_576 (0x08) -#define FEC_TFWR_X_WMRK_640 (0x09) -#define FEC_TFWR_X_WMRK_704 (0x0A) -#define FEC_TFWR_X_WMRK_768 (0x0B) -#define FEC_TFWR_X_WMRK_832 (0x0C) -#define FEC_TFWR_X_WMRK_896 (0x0D) -#define FEC_TFWR_X_WMRK_960 (0x0E) -#define FEC_TFWR_X_WMRK_1024 (0x0F) - -/* FIFO definitions */ -/* Bit definitions and macros for FSTAT */ -#define FIFO_STAT_IP (0x80000000) -#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24) -#define FIFO_STAT_FAE (0x00800000) -#define FIFO_STAT_RXW (0x00400000) -#define FIFO_STAT_UF (0x00200000) -#define FIFO_STAT_OF (0x00100000) -#define FIFO_STAT_FR (0x00080000) -#define FIFO_STAT_FULL (0x00040000) -#define FIFO_STAT_ALARM (0x00020000) -#define FIFO_STAT_EMPTY (0x00010000) - -/* Bit definitions and macros for FCTRL */ -#define FIFO_CTRL_WCTL (0x40000000) -#define FIFO_CTRL_WFR (0x20000000) -#define FIFO_CTRL_FRAME (0x08000000) -#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24) -#define FIFO_CTRL_IPMASK (0x00800000) -#define FIFO_CTRL_FAEMASK (0x00400000) -#define FIFO_CTRL_RXWMASK (0x00200000) -#define FIFO_CTRL_UFMASK (0x00100000) -#define FIFO_CTRL_OFMASK (0x00080000) - -#endif /* fsl_mcdmafec_h */ diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h deleted file mode 100644 index 413c200..0000000 --- a/include/asm-m68k/global_data.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2002 - 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long bus_clk; -#ifdef CONFIG_PCI - unsigned long pci_clk; -#endif -#ifdef CONFIG_EXTRA_CLOCK - unsigned long inp_clk; - unsigned long vco_clk; - unsigned long flb_clk; -#endif -#ifdef CONFIG_FSL_I2C - unsigned long i2c1_clk; - unsigned long i2c2_clk; -#endif - phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ - unsigned long reset_status; /* reset status register at boot */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long have_console; /* serial_init() was called */ -#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) - unsigned long fb_base; /* Base addr of framebuffer memory */ -#endif -#ifdef CONFIG_BOARD_TYPES - unsigned long board_type; -#endif - void **jt; /* Standalone app jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#if 0 -extern gd_t *global_data; -#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data -#else -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("d7") -#endif - -#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h deleted file mode 100644 index e83ce08..0000000 --- a/include/asm-m68k/immap.h +++ /dev/null @@ -1,456 +0,0 @@ -/* - * ColdFire Internal Memory Map and Defines - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_H -#define __IMMAP_H - -#if defined(CONFIG_MCF520x) -#include -#include - -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif - -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) -#endif /* CONFIG_M520x */ - -#ifdef CONFIG_M52277 -#include -#include - -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) - -#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) - -#ifdef CONFIG_LCD -#define CONFIG_SYS_LCD_BASE (MMAP_LCD) -#endif - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif - -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) -#endif /* CONFIG_M52277 */ - -#ifdef CONFIG_M5235 -#include -#include - -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) -#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif - -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) -#endif /* CONFIG_M5235 */ - -#ifdef CONFIG_M5249 -#include -#include - -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC) -#define CONFIG_SYS_NUM_IRQS (64) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) -#define CONFIG_SYS_TMRINTR_NO (31) -#define CONFIG_SYS_TMRINTR_MASK (0x00000400) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) -#endif -#endif /* CONFIG_M5249 */ - -#ifdef CONFIG_M5253 -#include -#include -#include - -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC) -#define CONFIG_SYS_NUM_IRQS (64) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) -#define CONFIG_SYS_TMRINTR_NO (27) -#define CONFIG_SYS_TMRINTR_MASK (0x00000400) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) -#endif -#endif /* CONFIG_M5253 */ - -#ifdef CONFIG_M5271 -#include -#include - -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) -#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */ -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) -#endif /* CONFIG_M5271 */ - -#ifdef CONFIG_M5272 -#include -#include - -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC) -#define CONFIG_SYS_NUM_IRQS (64) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_TMR3) -#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr) -#define CONFIG_SYS_TMRINTR_NO (INT_TMR3) -#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24) -#define CONFIG_SYS_TMRINTR_PEND (0) -#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif -#endif /* CONFIG_M5272 */ - -#ifdef CONFIG_M5275 -#include -#include - -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (192) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) -#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif -#endif /* CONFIG_M5275 */ - -#ifdef CONFIG_M5282 -#include -#include - -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) -#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) -#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif -#endif /* CONFIG_M5282 */ - -#if defined(CONFIG_MCF5301x) -#include -#include - -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) - -#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif - -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) -#endif /* CONFIG_M5301x */ - -#if defined(CONFIG_M5329) || defined(CONFIG_M5373) -#include -#include - -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) -#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif - -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) -#endif /* CONFIG_M5329 && CONFIG_M5373 */ - -#if defined(CONFIG_M54451) || defined(CONFIG_M54455) -#include -#include - -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#if defined(CONFIG_M54455EVB) -#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#endif - -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) - -#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) - -/* Timer */ -#ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) -#endif - -#ifdef CONFIG_MCFPIT -#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) -#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) -#define CONFIG_SYS_PIT_PRESCALE (6) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) - -#ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE) -#endif -#endif /* CONFIG_M54451 || CONFIG_M54455 */ - -#ifdef CONFIG_M547x -#include -#include - -#ifdef CONFIG_FSLDMAFEC -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) - -#define FEC0_RX_TASK 0 -#define FEC0_TX_TASK 1 -#define FEC0_RX_PRIORITY 6 -#define FEC0_TX_PRIORITY 7 -#define FEC0_RX_INIT 16 -#define FEC0_TX_INIT 17 -#define FEC1_RX_TASK 2 -#define FEC1_TX_TASK 3 -#define FEC1_RX_PRIORITY 6 -#define FEC1_TX_PRIORITY 7 -#define FEC1_RX_INIT 30 -#define FEC1_TX_INIT 31 -#endif - -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) - -#ifdef CONFIG_SLTTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) -#define CONFIG_SYS_TMR_BASE (MMAP_SLT0) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) -#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) - -#ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_BAR0 (0x40000000) -#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) -#endif -#endif /* CONFIG_M547x */ - -#ifdef CONFIG_M548x -#include -#include - -#ifdef CONFIG_FSLDMAFEC -#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) - -#define FEC0_RX_TASK 0 -#define FEC0_TX_TASK 1 -#define FEC0_RX_PRIORITY 6 -#define FEC0_TX_PRIORITY 7 -#define FEC0_RX_INIT 16 -#define FEC0_TX_INIT 17 -#define FEC1_RX_TASK 2 -#define FEC1_TX_TASK 3 -#define FEC1_RX_PRIORITY 6 -#define FEC1_TX_PRIORITY 7 -#define FEC1_RX_INIT 30 -#define FEC1_TX_INIT 31 -#endif - -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) - -/* Timer */ -#ifdef CONFIG_SLTTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) -#define CONFIG_SYS_TMR_BASE (MMAP_SLT0) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) -#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) -#endif - -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) - -#ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) -#endif -#endif /* CONFIG_M548x */ - -#endif /* __IMMAP_H */ diff --git a/include/asm-m68k/immap_520x.h b/include/asm-m68k/immap_520x.h deleted file mode 100644 index 08bc109..0000000 --- a/include/asm-m68k/immap_520x.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * MCF520x Internal Memory Map - * - * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_520X__ -#define __IMMAP_520X__ - -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000) - -#include -#include -#include -#include -#include -#include - -/* System Controller Module */ -typedef struct scm1 { - u32 mpr; /* 0x00 Master Privilege */ - u32 rsvd1[7]; - u32 pacra; /* 0x20 Peripheral Access Ctrl A */ - u32 pacrb; /* 0x24 Peripheral Access Ctrl B */ - u32 pacrc; /* 0x28 Peripheral Access Ctrl C */ - u32 pacrd; /* 0x2C Peripheral Access Ctrl D */ - u32 rsvd2[4]; - u32 pacre; /* 0x40 Peripheral Access Ctrl E */ - u32 pacrf; /* 0x44 Peripheral Access Ctrl F */ - u32 rsvd3[3]; - u32 bmt; /* 0x50 bus monitor */ -} scm1_t; - -typedef struct scm2 { - u8 rsvd1[19]; /* 0x00 - 0x12 */ - u8 wcr; /* 0x13 */ - u16 rsvd2; /* 0x14 - 0x15 */ - u16 cwcr; /* 0x16 */ - u8 rsvd3[3]; /* 0x18 - 0x1A */ - u8 cwsr; /* 0x1B */ - u8 rsvd4[3]; /* 0x1C - 0x1E */ - u8 scmisr; /* 0x1F */ - u8 rsvd5[79]; /* 0x20 - 0x6F */ - u32 cfadr; /* 0x70 */ - u8 rsvd7; /* 0x74 */ - u8 cfier; /* 0x75 */ - u8 cfloc; /* 0x76 */ - u8 cfatr; /* 0x77 */ - u32 rsvd8; /* 0x78 - 0x7B */ - u32 cfdtr; /* 0x7C */ -} scm2_t; - -/* Chip configuration module */ -typedef struct rcm { - u8 rcr; - u8 rsr; -} rcm_t; - -typedef struct ccm_ctrl { - u16 ccr; /* 0x00 Chip Cfg */ - u16 res1; /* 0x02 */ - u16 rcon; /* 0x04 Reset Cfg */ - u16 cir; /* 0x06 Chip ID */ -} ccm_t; - -/* GPIO port */ -typedef struct gpio_ctrl { - /* Port Output Data */ - u8 podr_busctl; /* 0x00 */ - u8 podr_be; /* 0x01 */ - u8 podr_cs; /* 0x02 */ - u8 podr_feci2c; /* 0x03 */ - u8 podr_qspi; /* 0x04 */ - u8 podr_timer; /* 0x05 */ - u8 podr_uart; /* 0x06 */ - u8 podr_fech; /* 0x07 */ - u8 podr_fecl; /* 0x08 */ - u8 res01[3]; /* 0x9 - 0x0B */ - - /* Port Data Direction */ - u8 pddr_busctl; /* 0x0C */ - u8 pddr_be; /* 0x0D */ - u8 pddr_cs; /* 0x0E */ - u8 pddr_feci2c; /* 0x0F */ - u8 pddr_qspi; /* 0x10*/ - u8 pddr_timer; /* 0x11 */ - u8 pddr_uart; /* 0x12 */ - u8 pddr_fech; /* 0x13 */ - u8 pddr_fecl; /* 0x14 */ - u8 res02[5]; /* 0x15 - 0x19 */ - - /* Port Data Direction */ - u8 ppdr_cs; /* 0x1A */ - u8 ppdr_feci2c; /* 0x1B */ - u8 ppdr_qspi; /* 0x1C */ - u8 ppdr_timer; /* 0x1D */ - u8 ppdr_uart; /* 0x1E */ - u8 ppdr_fech; /* 0x1F */ - u8 ppdr_fecl; /* 0x20 */ - u8 res03[3]; /* 0x21 - 0x23 */ - - /* Port Clear Output Data */ - u8 pclrr_busctl; /* 0x24 */ - u8 pclrr_be; /* 0x25 */ - u8 pclrr_cs; /* 0x26 */ - u8 pclrr_feci2c; /* 0x27 */ - u8 pclrr_qspi; /* 0x28 */ - u8 pclrr_timer; /* 0x29 */ - u8 pclrr_uart; /* 0x2A */ - u8 pclrr_fech; /* 0x2B */ - u8 pclrr_fecl; /* 0x2C */ - u8 res04[3]; /* 0x2D - 0x2F */ - - /* Pin Assignment */ - u8 par_busctl; /* 0x30 */ - u8 par_be; /* 0x31 */ - u8 par_cs; /* 0x32 */ - u8 par_feci2c; /* 0x33 */ - u8 par_qspi; /* 0x34 */ - u8 par_timer; /* 0x35 */ - u16 par_uart; /* 0x36 */ - u8 par_fec; /* 0x38 */ - u8 par_irq; /* 0x39 */ - - /* Mode Select Control */ - /* Drive Strength Control */ - u8 mscr_fb; /* 0x3A */ - u8 mscr_sdram; /* 0x3B */ - - u8 dscr_i2c; /* 0x3C */ - u8 dscr_misc; /* 0x3D */ - u8 dscr_fec; /* 0x3E */ - u8 dscr_uart; /* 0x3F */ - u8 dscr_qspi; /* 0x40 */ -} gpio_t; - -/* SDRAM controller */ -typedef struct sdram_ctrl { - u32 mode; /* 0x00 Mode/Extended Mode */ - u32 ctrl; /* 0x04 Ctrl */ - u32 cfg1; /* 0x08 Cfg 1 */ - u32 cfg2; /* 0x0C Cfg 2 */ - u32 res1[64]; /* 0x10 - 0x10F */ - u32 cs0; /* 0x110 Chip Select 0 Cfg */ - u32 cs1; /* 0x114 Chip Select 1 Cfg */ -} sdram_t; - -/* Clock Module */ -typedef struct pll_ctrl { - u8 odr; /* 0x00 Output divider */ - u8 rsvd1; - u8 cr; /* 0x02 Control */ - u8 rsvd2; - u8 mdr; /* 0x04 Modulation Divider */ - u8 rsvd3; - u8 fdr; /* 0x06 Feedback Divider */ - u8 rsvd4; -} pll_t; - -/* Watchdog registers */ -typedef struct wdog_ctrl { - u16 cr; /* 0x00 Control */ - u16 mr; /* 0x02 Modulus */ - u16 cntr; /* 0x04 Count */ - u16 sr; /* 0x06 Service */ -} wdog_t; - -#endif /* __IMMAP_520X__ */ diff --git a/include/asm-m68k/immap_5227x.h b/include/asm-m68k/immap_5227x.h deleted file mode 100644 index 6f65f50..0000000 --- a/include/asm-m68k/immap_5227x.h +++ /dev/null @@ -1,254 +0,0 @@ -/* - * MCF5227x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5227X__ -#define __IMMAP_5227X__ - -/* Module Base Addresses */ -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000) -#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010) -#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) -#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000) -#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000) -#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800) -#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00) -#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000) -#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100) -#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140) -#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) -#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Reset Controller Module (RCM) */ -typedef struct rcm { - u8 rcr; - u8 rsr; -} rcm_t; - -/* Chip Configuration Module (CCM) */ -typedef struct ccm { - u16 ccr; /* Chip Configuration (Rd-only) */ - u16 resv1; - u16 rcon; /* Reset Configuration (Rd-only) */ - u16 cir; /* Chip Identification (Rd-only) */ - u32 resv2; - u16 misccr; /* Miscellaneous Control */ - u16 cdr; /* Clock Divider */ - u16 uocsr; /* USB On-the-Go Controller Status */ - u16 resv4; - u16 sbfsr; /* Serial Boot Status */ - u16 sbfcr; /* Serial Boot Control */ -} ccm_t; - -typedef struct canex_ctrl { - can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ - u32 res0[0x700]; /* 0x100 */ - can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */ -} canex_t; - -/* General Purpose I/O Module (GPIO) */ -typedef struct gpio { - /* Port Output Data Registers */ - u8 podr_be; /* 0x00 */ - u8 podr_cs; /* 0x01 */ - u8 podr_fbctl; /* 0x02 */ - u8 podr_i2c; /* 0x03 */ - u8 rsvd1; /* 0x04 */ - u8 podr_uart; /* 0x05 */ - u8 podr_dspi; /* 0x06 */ - u8 podr_timer; /* 0x07 */ - u8 podr_lcdctl; /* 0x08 */ - u8 podr_lcddatah; /* 0x09 */ - u8 podr_lcddatam; /* 0x0A */ - u8 podr_lcddatal; /* 0x0B */ - - /* Port Data Direction Registers */ - u8 pddr_be; /* 0x0C */ - u8 pddr_cs; /* 0x0D */ - u8 pddr_fbctl; /* 0x0E */ - u8 pddr_i2c; /* 0x0F */ - u8 rsvd2; /* 0x10 */ - u8 pddr_uart; /* 0x11 */ - u8 pddr_dspi; /* 0x12 */ - u8 pddr_timer; /* 0x13 */ - u8 pddr_lcdctl; /* 0x14 */ - u8 pddr_lcddatah; /* 0x15 */ - u8 pddr_lcddatam; /* 0x16 */ - u8 pddr_lcddatal; /* 0x17 */ - - /* Port Pin Data/Set Data Registers */ - u8 ppdsdr_be; /* 0x18 */ - u8 ppdsdr_cs; /* 0x19 */ - u8 ppdsdr_fbctl; /* 0x1A */ - u8 ppdsdr_i2c; /* 0x1B */ - u8 rsvd3; /* 0x1C */ - u8 ppdsdr_uart; /* 0x1D */ - u8 ppdsdr_dspi; /* 0x1E */ - u8 ppdsdr_timer; /* 0x1F */ - u8 ppdsdr_lcdctl; /* 0x20 */ - u8 ppdsdr_lcddatah; /* 0x21 */ - u8 ppdsdr_lcddatam; /* 0x22 */ - u8 ppdsdr_lcddatal; /* 0x23 */ - - /* Port Clear Output Data Registers */ - u8 pclrr_be; /* 0x24 */ - u8 pclrr_cs; /* 0x25 */ - u8 pclrr_fbctl; /* 0x26 */ - u8 pclrr_i2c; /* 0x27 */ - u8 rsvd4; /* 0x28 */ - u8 pclrr_uart; /* 0x29 */ - u8 pclrr_dspi; /* 0x2A */ - u8 pclrr_timer; /* 0x2B */ - u8 pclrr_lcdctl; /* 0x2C */ - u8 pclrr_lcddatah; /* 0x2D */ - u8 pclrr_lcddatam; /* 0x2E */ - u8 pclrr_lcddatal; /* 0x2F */ - - /* Pin Assignment Registers */ - u8 par_be; /* 0x30 */ - u8 par_cs; /* 0x31 */ - u8 par_fbctl; /* 0x32 */ - u8 par_i2c; /* 0x33 */ - u16 par_uart; /* 0x34 */ - u8 par_dspi; /* 0x36 */ - u8 par_timer; /* 0x37 */ - u8 par_lcdctl; /* 0x38 */ - u8 par_irq; /* 0x39 */ - u16 rsvd6; /* 0x3A - 0x3B */ - u32 par_lcdh; /* 0x3C */ - u32 par_lcdl; /* 0x40 */ - - /* Mode select control registers */ - u8 mscr_fb; /* 0x44 */ - u8 mscr_sdram; /* 0x45 */ - - u16 rsvd7; /* 0x46 - 0x47 */ - u8 dscr_dspi; /* 0x48 */ - u8 dscr_timer; /* 0x49 */ - u8 dscr_i2c; /* 0x4A */ - u8 dscr_lcd; /* 0x4B */ - u8 dscr_debug; /* 0x4C */ - u8 dscr_clkrst; /* 0x4D */ - u8 dscr_irq; /* 0x4E */ - u8 dscr_uart; /* 0x4F */ -} gpio_t; - -/* SDRAM Controller (SDRAMC) */ -typedef struct sdramc { - u32 sdmr; /* Mode/Extended Mode */ - u32 sdcr; /* Control */ - u32 sdcfg1; /* Configuration 1 */ - u32 sdcfg2; /* Chip Select */ - u8 resv0[0x100]; - u32 sdcs0; /* Mode/Extended Mode */ - u32 sdcs1; /* Mode/Extended Mode */ -} sdramc_t; - -/* Phase Locked Loop (PLL) */ -typedef struct pll { - u32 pcr; /* PLL Control */ - u32 psr; /* PLL Status */ -} pll_t; - -/* System Control Module register */ -typedef struct scm1 { - u32 mpr; /* 0x00 Master Privilege */ - u32 rsvd1[7]; - u32 pacra; /* 0x20 */ - u32 pacrb; /* 0x24 */ - u32 pacrc; /* 0x28 */ - u32 pacrd; /* 0x2C */ - u32 rsvd2[4]; - u32 pacre; /* 0x40 */ - u32 pacrf; /* 0x44 */ - u32 pacrg; /* 0x48 */ - u32 rsvd3; - u32 pacri; /* 0x50 */ -} scm1_t; - -typedef struct scm2_ctrl { - u8 res1[3]; /* 0x00 - 0x02 */ - u8 wcr; /* 0x03 wakeup control */ - u16 res2; /* 0x04 - 0x05 */ - u16 cwcr; /* 0x06 Core Watchdog Control */ - u8 res3[3]; /* 0x08 - 0x0A */ - u8 cwsr; /* 0x0B Core Watchdog Service */ - u8 res4[2]; /* 0x0C - 0x0D */ - u8 scmisr; /* 0x0F Interrupt Status */ - u32 res5; /* 0x20 */ - u32 bcr; /* 0x24 Burst Configuration */ -} scm2_t; - -typedef struct scm3_ctrl { - u32 cfadr; /* 0x00 Core Fault Address */ - u8 res7; /* 0x04 */ - u8 cfier; /* 0x05 Core Fault Interrupt Enable */ - u8 cfloc; /* 0x06 Core Fault Location */ - u8 cfatr; /* 0x07 Core Fault Attributes */ - u32 cfdtr; /* 0x08 Core Fault Data */ -} scm3_t; - -typedef struct rtcex { - u32 rsvd1[3]; - u32 gocu; - u32 gocl; -} rtcex_t; -#endif /* __IMMAP_5227X__ */ diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h deleted file mode 100644 index f7f35fc..0000000 --- a/include/asm-m68k/immap_5235.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * MCF5329 Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5235__ -#define __IMMAP_5235__ - -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) - -#include -#include -#include -#include -#include -#include -#include -#include - -/* System Control Module register */ -typedef struct scm_ctrl { - u32 ipsbar; /* 0x00 - MBAR */ - u32 res1; /* 0x04 */ - u32 rambar; /* 0x08 - RAMBAR */ - u32 res2; /* 0x0C */ - u8 crsr; /* 0x10 Core Reset Status Register */ - u8 cwcr; /* 0x11 Core Watchdog Control Register */ - u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */ - u8 cwsr; /* 0x13 Core Watchdog Service Register */ - u32 dmareqc; /* 0x14 */ - u32 res3; /* 0x18 */ - u32 mpark; /* 0x1C */ - u8 mpr; /* 0x20 */ - u8 res4[3]; /* 0x21 - 0x23 */ - u8 pacr0; /* 0x24 */ - u8 pacr1; /* 0x25 */ - u8 pacr2; /* 0x26 */ - u8 pacr3; /* 0x27 */ - u8 pacr4; /* 0x28 */ - u32 res5; /* 0x29 */ - u8 pacr5; /* 0x2a */ - u8 pacr6; /* 0x2b */ - u8 pacr7; /* 0x2c */ - u32 res6; /* 0x2d */ - u8 pacr8; /* 0x2e */ - u32 res7; /* 0x2f */ - u8 gpacr; /* 0x30 */ - u8 res8[3]; /* 0x31 - 0x33 */ -} scm_t; - -/* SDRAM controller registers */ -typedef struct sdram_ctrl { - u16 dcr; /* 0x00 Control register */ - u16 res1[3]; /* 0x02 - 0x07 */ - u32 dacr0; /* 0x08 address and control register 0 */ - u32 dmr0; /* 0x0C mask register block 0 */ - u32 dacr1; /* 0x10 address and control register 1 */ - u32 dmr1; /* 0x14 mask register block 1 */ -} sdram_t; - -typedef struct canex_ctrl { - can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ -} canex_t; - -/* GPIO port registers */ -typedef struct gpio_ctrl { - /* Port Output Data Registers */ - u8 podr_addr; /* 0x00 */ - u8 podr_datah; /* 0x01 */ - u8 podr_datal; /* 0x02 */ - u8 podr_busctl; /* 0x03 */ - u8 podr_bs; /* 0x04 */ - u8 podr_cs; /* 0x05 */ - u8 podr_sdram; /* 0x06 */ - u8 podr_feci2c; /* 0x07 */ - u8 podr_uarth; /* 0x08 */ - u8 podr_uartl; /* 0x09 */ - u8 podr_qspi; /* 0x0A */ - u8 podr_timer; /* 0x0B */ - u8 podr_etpu; /* 0x0C */ - u8 res1[3]; /* 0x0D - 0x0F */ - - /* Port Data Direction Registers */ - u8 pddr_addr; /* 0x10 */ - u8 pddr_datah; /* 0x11 */ - u8 pddr_datal; /* 0x12 */ - u8 pddr_busctl; /* 0x13 */ - u8 pddr_bs; /* 0x14 */ - u8 pddr_cs; /* 0x15 */ - u8 pddr_sdram; /* 0x16 */ - u8 pddr_feci2c; /* 0x17 */ - u8 pddr_uarth; /* 0x18 */ - u8 pddr_uartl; /* 0x19 */ - u8 pddr_qspi; /* 0x1A */ - u8 pddr_timer; /* 0x1B */ - u8 pddr_etpu; /* 0x1C */ - u8 res2[3]; /* 0x1D - 0x1F */ - - /* Port Data Direction Registers */ - u8 ppdsdr_addr; /* 0x20 */ - u8 ppdsdr_datah; /* 0x21 */ - u8 ppdsdr_datal; /* 0x22 */ - u8 ppdsdr_busctl; /* 0x23 */ - u8 ppdsdr_bs; /* 0x24 */ - u8 ppdsdr_cs; /* 0x25 */ - u8 ppdsdr_sdram; /* 0x26 */ - u8 ppdsdr_feci2c; /* 0x27 */ - u8 ppdsdr_uarth; /* 0x28 */ - u8 ppdsdr_uartl; /* 0x29 */ - u8 ppdsdr_qspi; /* 0x2A */ - u8 ppdsdr_timer; /* 0x2B */ - u8 ppdsdr_etpu; /* 0x2C */ - u8 res3[3]; /* 0x2D - 0x2F */ - - /* Port Clear Output Data Registers */ - u8 pclrr_addr; /* 0x30 */ - u8 pclrr_datah; /* 0x31 */ - u8 pclrr_datal; /* 0x32 */ - u8 pclrr_busctl; /* 0x33 */ - u8 pclrr_bs; /* 0x34 */ - u8 pclrr_cs; /* 0x35 */ - u8 pclrr_sdram; /* 0x36 */ - u8 pclrr_feci2c; /* 0x37 */ - u8 pclrr_uarth; /* 0x38 */ - u8 pclrr_uartl; /* 0x39 */ - u8 pclrr_qspi; /* 0x3A */ - u8 pclrr_timer; /* 0x3B */ - u8 pclrr_etpu; /* 0x3C */ - u8 res4[3]; /* 0x3D - 0x3F */ - - /* Pin Assignment Registers */ - u8 par_ad; /* 0x40 */ - u8 res5; /* 0x41 */ - u16 par_busctl; /* 0x42 */ - u8 par_bs; /* 0x44 */ - u8 par_cs; /* 0x45 */ - u8 par_sdram; /* 0x46 */ - u8 par_feci2c; /* 0x47 */ - u16 par_uart; /* 0x48 */ - u8 par_qspi; /* 0x4A */ - u8 res6; /* 0x4B */ - u16 par_timer; /* 0x4C */ - u8 par_etpu; /* 0x4E */ - u8 res7; /* 0x4F */ - - /* Drive Strength Control Registers */ - u8 dscr_eim; /* 0x50 */ - u8 dscr_etpu; /* 0x51 */ - u8 dscr_feci2c; /* 0x52 */ - u8 dscr_uart; /* 0x53 */ - u8 dscr_qspi; /* 0x54 */ - u8 dscr_timer; /* 0x55 */ - u16 res8; /* 0x56 */ -} gpio_t; - -/*Chip configuration module registers */ -typedef struct ccm_ctrl { - u8 rcr; /* 0x01 */ - u8 rsr; /* 0x02 */ - u16 res1; /* 0x03 */ - u16 ccr; /* 0x04 Chip configuration register */ - u16 lpcr; /* 0x06 Low-power Control register */ - u16 rcon; /* 0x08 Rreset configuration register */ - u16 cir; /* 0x0a Chip identification register */ -} ccm_t; - -/* Clock Module registers */ -typedef struct pll_ctrl { - u32 syncr; /* 0x00 synthesizer control register */ - u32 synsr; /* 0x04 synthesizer status register */ -} pll_t; - -/* Watchdog registers */ -typedef struct wdog_ctrl { - u16 cr; /* 0x00 Control register */ - u16 mr; /* 0x02 Modulus register */ - u16 cntr; /* 0x04 Count register */ - u16 sr; /* 0x06 Service register */ -} wdog_t; - -#endif /* __IMMAP_5235__ */ diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h deleted file mode 100644 index 0242086..0000000 --- a/include/asm-m68k/immap_5249.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * MCF5249 Internal Memory Map - * - * Copyright (c) 2003 Josef Baumgartner - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5249__ -#define __IMMAP_5249__ - -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) - -#include -#include - -#endif /* __IMMAP_5249__ */ diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h deleted file mode 100644 index 28cd107..0000000 --- a/include/asm-m68k/immap_5253.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * MCF5253 Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5253__ -#define __IMMAP_5253__ - -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) - -#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C) -#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) -#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) - -#include -#include -#include -#include - -typedef struct canex_ctrl { - can_msg_t msg[32]; /* 0x80 Message Buffer 0-31 */ -} canex_t; - -#endif /* __IMMAP_5253__ */ diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h deleted file mode 100644 index 8ddec5c..0000000 --- a/include/asm-m68k/immap_5271.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * MCF5272 Internal Memory Map - * - * Copyright (c) 2003 Josef Baumgartner - * 2006 Zachary P. Landau - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5271__ -#define __IMMAP_5271__ - -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) - -#include -#include -#include -#include -#include -#include -#include - - -#endif /* __IMMAP_5271__ */ diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h deleted file mode 100644 index 8d4254b..0000000 --- a/include/asm-m68k/immap_5272.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * MCF5272 Internal Memory Map - * - * Copyright (c) 2003 Josef Baumgartner - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5272__ -#define __IMMAP_5272__ - -#define MMAP_CFG (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000020) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x000000A0) -#define MMAP_PWM (CONFIG_SYS_MBAR + 0x000000C0) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x000000E0) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_TMR0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_TMR1 (CONFIG_SYS_MBAR + 0x00000220) -#define MMAP_TMR2 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_TMR3 (CONFIG_SYS_MBAR + 0x00000260) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_PLIC (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840) -#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000) - -#include - -/* System configuration registers */ -typedef struct sys_ctrl { - uint sc_mbar; - ushort sc_scr; - ushort sc_spr; - uint sc_pmr; - char res1[2]; - ushort sc_alpr; - uint sc_dir; - char res2[12]; -} sysctrl_t; - -/* Interrupt module registers */ -typedef struct int_ctrl { - uint int_icr1; - uint int_icr2; - uint int_icr3; - uint int_icr4; - uint int_isr; - uint int_pitr; - uint int_piwr; - uchar res1[3]; - uchar int_pivr; -} intctrl_t; - -/* Chip select module registers */ -typedef struct cs_ctlr { - uint cs_br0; - uint cs_or0; - uint cs_br1; - uint cs_or1; - uint cs_br2; - uint cs_or2; - uint cs_br3; - uint cs_or3; - uint cs_br4; - uint cs_or4; - uint cs_br5; - uint cs_or5; - uint cs_br6; - uint cs_or6; - uint cs_br7; - uint cs_or7; -} csctrl_t; - -/* GPIO port registers */ -typedef struct gpio_ctrl { - uint gpio_pacnt; - ushort gpio_paddr; - ushort gpio_padat; - uint gpio_pbcnt; - ushort gpio_pbddr; - ushort gpio_pbdat; - uchar res1[4]; - ushort gpio_pcddr; - ushort gpio_pcdat; - uint gpio_pdcnt; - uchar res2[4]; -} gpio_t; - -/* DMA module registers */ -typedef struct dma_ctrl { - ulong dma_dmr; - uchar res1[2]; - ushort dma_dir; - ulong dma_dbcr; - ulong dma_dsar; - ulong dma_ddar; - uchar res2[12]; -} dma_t; - -/* SDRAM controller registers, offset: 0x180 */ -typedef struct sdram_ctrl { - uchar res1[2]; - ushort sdram_sdcr; - uchar res2[2]; - ushort sdram_sdtr; - uchar res3[120]; -} sdramctrl_t; - -/* Watchdog registers */ -typedef struct wdog_ctrl { - ushort wdog_wrrr; - ushort res1; - ushort wdog_wirr; - ushort res2; - ushort wdog_wcr; - ushort res3; - ushort wdog_wer; - uchar res4[114]; -} wdog_t; - -/* PLIC module registers */ -typedef struct plic_ctrl { - ulong plic_p0b1rr; - ulong plic_p1b1rr; - ulong plic_p2b1rr; - ulong plic_p3b1rr; - ulong plic_p0b2rr; - ulong plic_p1b2rr; - ulong plic_p2b2rr; - ulong plic_p3b2rr; - uchar plic_p0drr; - uchar plic_p1drr; - uchar plic_p2drr; - uchar plic_p3drr; - uchar res1[4]; - ulong plic_p0b1tr; - ulong plic_p1b1tr; - ulong plic_p2b1tr; - ulong plic_p3b1tr; - ulong plic_p0b2tr; - ulong plic_p1b2tr; - ulong plic_p2b2tr; - ulong plic_p3b2tr; - uchar plic_p0dtr; - uchar plic_p1dtr; - uchar plic_p2dtr; - uchar plic_p3dtr; - uchar res2[4]; - ushort plic_p0cr; - ushort plic_p1cr; - ushort plic_p2cr; - ushort plic_p3cr; - ushort plic_p0icr; - ushort plic_p1icr; - ushort plic_p2icr; - ushort plic_p3icr; - ushort plic_p0gmr; - ushort plic_p1gmr; - ushort plic_p2gmr; - ushort plic_p3gmr; - ushort plic_p0gmt; - ushort plic_p1gmt; - ushort plic_p2gmt; - ushort plic_p3gmt; - uchar res3; - uchar plic_pgmts; - uchar plic_pgmta; - uchar res4; - uchar plic_p0gcir; - uchar plic_p1gcir; - uchar plic_p2gcir; - uchar plic_p3gcir; - uchar plic_p0gcit; - uchar plic_p1gcit; - uchar plic_p2gcit; - uchar plic_p3gcit; - uchar res5[3]; - uchar plic_pgcitsr; - uchar res6[3]; - uchar plic_pdcsr; - ushort plic_p0psr; - ushort plic_p1psr; - ushort plic_p2psr; - ushort plic_p3psr; - ushort plic_pasr; - uchar res7; - uchar plic_plcr; - ushort res8; - ushort plic_pdrqr; - ushort plic_p0sdr; - ushort plic_p1sdr; - ushort plic_p2sdr; - ushort plic_p3sdr; - ushort res9; - ushort plic_pcsr; - uchar res10[1184]; -} plic_t; - -/* USB module registers */ -typedef struct usb { - ushort res1; - ushort usb_fnr; - ushort res2; - ushort usb_fnmr; - ushort res3; - ushort usb_rfmr; - ushort res4; - ushort usb_rfmmr; - uchar res5[3]; - uchar usb_far; - ulong usb_asr; - ulong usb_drr1; - ulong usb_drr2; - ushort res6; - ushort usb_specr; - ushort res7; - ushort usb_ep0sr; - ulong usb_iep0cfg; - ulong usb_oep0cfg; - ulong usb_ep1cfg; - ulong usb_ep2cfg; - ulong usb_ep3cfg; - ulong usb_ep4cfg; - ulong usb_ep5cfg; - ulong usb_ep6cfg; - ulong usb_ep7cfg; - ulong usb_ep0ctl; - ushort res8; - ushort usb_ep1ctl; - ushort res9; - ushort usb_ep2ctl; - ushort res10; - ushort usb_ep3ctl; - ushort res11; - ushort usb_ep4ctl; - ushort res12; - ushort usb_ep5ctl; - ushort res13; - ushort usb_ep6ctl; - ushort res14; - ushort usb_ep7ctl; - ulong usb_ep0isr; - ushort res15; - ushort usb_ep1isr; - ushort res16; - ushort usb_ep2isr; - ushort res17; - ushort usb_ep3isr; - ushort res18; - ushort usb_ep4isr; - ushort res19; - ushort usb_ep5isr; - ushort res20; - ushort usb_ep6isr; - ushort res21; - ushort usb_ep7isr; - ulong usb_ep0imr; - ushort res22; - ushort usb_ep1imr; - ushort res23; - ushort usb_ep2imr; - ushort res24; - ushort usb_ep3imr; - ushort res25; - ushort usb_ep4imr; - ushort res26; - ushort usb_ep5imr; - ushort res27; - ushort usb_ep6imr; - ushort res28; - ushort usb_ep7imr; - ulong usb_ep0dr; - ulong usb_ep1dr; - ulong usb_ep2dr; - ulong usb_ep3dr; - ulong usb_ep4dr; - ulong usb_ep5dr; - ulong usb_ep6dr; - ulong usb_ep7dr; - ushort res29; - ushort usb_ep0dpr; - ushort res30; - ushort usb_ep1dpr; - ushort res31; - ushort usb_ep2dpr; - ushort res32; - ushort usb_ep3dpr; - ushort res33; - ushort usb_ep4dpr; - ushort res34; - ushort usb_ep5dpr; - ushort res35; - ushort usb_ep6dpr; - ushort res36; - ushort usb_ep7dpr; - uchar res37[788]; - uchar usb_cfgram[1024]; -} usb_t; - -#endif /* __IMMAP_5272__ */ diff --git a/include/asm-m68k/immap_5275.h b/include/asm-m68k/immap_5275.h deleted file mode 100644 index 46426a3..0000000 --- a/include/asm-m68k/immap_5275.h +++ /dev/null @@ -1,367 +0,0 @@ -/* - * MCF5274/5 Internal Memory Map - * - * Copyright (c) 2005 Arthur Shipkowski - * Based on work Copyright (c) 2003 Josef Baumgartner - * - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5275__ -#define __IMMAP_5275__ - -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800) -#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000) - -#include -#include -#include -#include -#include -#include -#include -#include - -/* System configuration registers -*/ -typedef struct sys_ctrl { - u32 ipsbar; - u32 res1; - u32 rambar; - u32 res2; - u8 crsr; - u8 cwcr; - u8 lpicr; - u8 cwsr; - u8 res3[8]; - u32 mpark; - u8 mpr; - u8 res4[3]; - u8 pacr0; - u8 pacr1; - u8 pacr2; - u8 pacr3; - u8 pacr4; - u8 res5; - u8 pacr5; - u8 pacr6; - u8 pacr7; - u8 res6; - u8 pacr8; - u8 res7; - u8 gpacr; - u8 res8[3]; -} sysctrl_t; -/* SDRAM controller registers, offset: 0x040 - */ -typedef struct sdram_ctrl { - u32 sdmr; - u32 sdcr; - u32 sdcfg1; - u32 sdcfg2; - u32 sdbar0; - u32 sdbmr0; - u32 sdbar1; - u32 sdbmr1; -} sdramctrl_t; - -/* DMA module registers, offset 0x100 - */ -typedef struct dma_ctrl { - u32 sar; - u32 dar; - u32 dsrbcr; - u32 dcr; -} dma_t; - -/* GPIO port registers -*/ -typedef struct gpio_ctrl { - /* Port Output Data Registers */ - u8 podr_res1[4]; - u8 podr_busctl; - u8 podr_addr; - u8 podr_res2[2]; - u8 podr_cs; - u8 podr_res3; - u8 podr_fec0h; - u8 podr_fec0l; - u8 podr_feci2c; - u8 podr_qspi; - u8 podr_sdram; - u8 podr_timerh; - u8 podr_timerl; - u8 podr_uartl; - u8 podr_fec1h; - u8 podr_fec1l; - u8 podr_bs; - u8 podr_res4; - u8 podr_usbh; - u8 podr_usbl; - u8 podr_uarth; - u8 podr_res5[3]; - /* Port Data Direction Registers */ - u8 pddr_res1[4]; - u8 pddr_busctl; - u8 pddr_addr; - u8 pddr_res2[2]; - u8 pddr_cs; - u8 pddr_res3; - u8 pddr_fec0h; - u8 pddr_fec0l; - u8 pddr_feci2c; - u8 pddr_qspi; - u8 pddr_sdram; - u8 pddr_timerh; - u8 pddr_timerl; - u8 pddr_uartl; - u8 pddr_fec1h; - u8 pddr_fec1l; - u8 pddr_bs; - u8 pddr_res4; - u8 pddr_usbh; - u8 pddr_usbl; - u8 pddr_uarth; - u8 pddr_res5[3]; - /* Port Pin Data/Set Registers */ - u8 ppdsdr_res1[4]; - u8 ppdsdr_busctl; - u8 ppdsdr_addr; - u8 ppdsdr_res2[2]; - u8 ppdsdr_cs; - u8 ppdsdr_res3; - u8 ppdsdr_fec0h; - u8 ppdsdr_fec0l; - u8 ppdsdr_feci2c; - u8 ppdsdr_qspi; - u8 ppdsdr_sdram; - u8 ppdsdr_timerh; - u8 ppdsdr_timerl; - u8 ppdsdr_uartl; - u8 ppdsdr_fec1h; - u8 ppdsdr_fec1l; - u8 ppdsdr_bs; - u8 ppdsdr_res4; - u8 ppdsdr_usbh; - u8 ppdsdr_usbl; - u8 ppdsdr_uarth; - u8 ppdsdr_res5[3]; - /* Port Clear Output Data Registers */ - u8 pclrr_res1[4]; - u8 pclrr_busctl; - u8 pclrr_addr; - u8 pclrr_res2[2]; - u8 pclrr_cs; - u8 pclrr_res3; - u8 pclrr_fec0h; - u8 pclrr_fec0l; - u8 pclrr_feci2c; - u8 pclrr_qspi; - u8 pclrr_sdram; - u8 pclrr_timerh; - u8 pclrr_timerl; - u8 pclrr_uartl; - u8 pclrr_fec1h; - u8 pclrr_fec1l; - u8 pclrr_bs; - u8 pclrr_res4; - u8 pclrr_usbh; - u8 pclrr_usbl; - u8 pclrr_uarth; - u8 pclrr_res5[3]; - /* Pin Assignment Registers */ - u8 par_addr; - u8 par_cs; - u16 par_busctl; - u8 par_res1[2]; - u16 par_usb; - u8 par_fec0hl; - u8 par_fec1hl; - u16 par_timer; - u16 par_uart; - u16 par_qspi; - u16 par_sdram; - u16 par_feci2c; - u8 par_bs; - u8 par_res2[3]; -} gpio_t; - - -/* Watchdog registers - */ -typedef struct wdog_ctrl { - u16 wcr; - u16 wmr; - u16 wcntr; - u16 wsr; - u8 res4[114]; -} wdog_t; - -/* USB module registers -*/ -typedef struct usb { - u16 res1; - u16 fnr; - u16 res2; - u16 fnmr; - u16 res3; - u16 rfmr; - u16 res4; - u16 rfmmr; - u8 res5[3]; - u8 far; - u32 asr; - u32 drr1; - u32 drr2; - u16 res6; - u16 specr; - u16 res7; - u16 ep0sr; - u32 iep0cfg; - u32 oep0cfg; - u32 ep1cfg; - u32 ep2cfg; - u32 ep3cfg; - u32 ep4cfg; - u32 ep5cfg; - u32 ep6cfg; - u32 ep7cfg; - u32 ep0ctl; - u16 res8; - u16 ep1ctl; - u16 res9; - u16 ep2ctl; - u16 res10; - u16 ep3ctl; - u16 res11; - u16 ep4ctl; - u16 res12; - u16 ep5ctl; - u16 res13; - u16 ep6ctl; - u16 res14; - u16 ep7ctl; - u32 ep0isr; - u16 res15; - u16 ep1isr; - u16 res16; - u16 ep2isr; - u16 res17; - u16 ep3isr; - u16 res18; - u16 ep4isr; - u16 res19; - u16 ep5isr; - u16 res20; - u16 ep6isr; - u16 res21; - u16 ep7isr; - u32 ep0imr; - u16 res22; - u16 ep1imr; - u16 res23; - u16 ep2imr; - u16 res24; - u16 ep3imr; - u16 res25; - u16 ep4imr; - u16 res26; - u16 ep5imr; - u16 res27; - u16 ep6imr; - u16 res28; - u16 ep7imr; - u32 ep0dr; - u32 ep1dr; - u32 ep2dr; - u32 ep3dr; - u32 ep4dr; - u32 ep5dr; - u32 ep6dr; - u32 ep7dr; - u16 res29; - u16 ep0dpr; - u16 res30; - u16 ep1dpr; - u16 res31; - u16 ep2dpr; - u16 res32; - u16 ep3dpr; - u16 res33; - u16 ep4dpr; - u16 res34; - u16 ep5dpr; - u16 res35; - u16 ep6dpr; - u16 res36; - u16 ep7dpr; - u8 res37[788]; - u8 cfgram[1024]; -} usb_t; - -/* PLL module registers - */ -typedef struct pll_ctrl { - u32 syncr; - u32 synsr; -} pll_t; - -typedef struct rcm { - u8 rcr; - u8 rsr; -} rcm_t; - -#endif /* __IMMAP_5275__ */ diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h deleted file mode 100644 index dd526a1..0000000 --- a/include/asm-m68k/immap_5282.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * MCF5282 Internal Memory Map - * - * Copyright (c) 2003 Josef Baumgartner - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5282__ -#define __IMMAP_5282__ - -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_QADC (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_GPTMRA (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_GPTMRB (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000) - -#include -#include -#include -#include -#include - -/* System Control Module */ -typedef struct scm_ctrl { - u32 ipsbar; - u32 res1; - u32 rambar; - u32 res2; - u8 crsr; - u8 cwcr; - u8 lpicr; - u8 cwsr; - u32 res3; - u8 mpark; - u8 res4[3]; - u8 pacr0; - u8 pacr1; - u8 pacr2; - u8 pacr3; - u8 pacr4; - u8 res5; - u8 pacr5; - u8 pacr6; - u8 pacr7; - u8 res6; - u8 pacr8; - u8 res7; - u8 gpacr0; - u8 gpacr1; - u16 res8; -} scm_t; - -typedef struct canex_ctrl { - can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ -} canex_t; - -/* Clock Module registers */ -typedef struct pll_ctrl { - u16 syncr; /* 0x00 synthesizer control register */ - u16 synsr; /* 0x02 synthesizer status register */ -} pll_t; - -/* Watchdog registers */ -typedef struct wdog_ctrl { - ushort wcr; - ushort wmr; - ushort wcntr; - ushort wsr; -} wdog_t; - -#endif /* __IMMAP_5282__ */ diff --git a/include/asm-m68k/immap_5301x.h b/include/asm-m68k/immap_5301x.h deleted file mode 100644 index 87ac770..0000000 --- a/include/asm-m68k/immap_5301x.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * MCF5301x Internal Memory Map - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5301X__ -#define __IMMAP_5301X__ - -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000) -#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000) -#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000) -#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000) -#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000) -#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) -#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000) -#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000) -#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000) - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* System Controller Module */ -typedef struct scm1 { - u32 mpr; /* 0x00 Master Privilege */ - u32 rsvd1[7]; - u32 pacra; /* 0x20 Peripheral Access Ctrl A */ - u32 pacrb; /* 0x24 Peripheral Access Ctrl B */ - u32 pacrc; /* 0x28 Peripheral Access Ctrl C */ - u32 pacrd; /* 0x2C Peripheral Access Ctrl D */ - u32 rsvd2[4]; - u32 pacre; /* 0x40 Peripheral Access Ctrl E */ - u32 pacrf; /* 0x44 Peripheral Access Ctrl F */ - u32 pacrg; /* 0x48 Peripheral Access Ctrl G */ -} scm1_t; - -typedef struct scm2 { - u8 rsvd1[19]; /* 0x00 - 0x12 */ - u8 wcr; /* 0x13 */ - u16 rsvd2; /* 0x14 - 0x15 */ - u16 cwcr; /* 0x16 */ - u8 rsvd3[3]; /* 0x18 - 0x1A */ - u8 cwsr; /* 0x1B */ - u8 rsvd4[3]; /* 0x1C - 0x1E */ - u8 scmisr; /* 0x1F */ - u32 rsvd5; /* 0x20 - 0x23 */ - u8 bcr; /* 0x24 */ - u8 rsvd6[74]; /* 0x25 - 0x6F */ - u32 cfadr; /* 0x70 */ - u8 rsvd7; /* 0x74 */ - u8 cfier; /* 0x75 */ - u8 cfloc; /* 0x76 */ - u8 cfatr; /* 0x77 */ - u32 rsvd8; /* 0x78 - 0x7B */ - u32 cfdtr; /* 0x7C */ -} scm2_t; - -/* PWM module */ -typedef struct pwm_ctrl { - u8 en; /* 0x00 PWM Enable */ - u8 pol; /* 0x01 Polarity */ - u8 clk; /* 0x02 Clock Select */ - u8 prclk; /* 0x03 Prescale Clock Select */ - u8 cae; /* 0x04 Center Align Enable */ - u8 ctl; /* 0x05 Ctrl */ - u8 res1[2]; /* 0x06 - 0x07 */ - u8 scla; /* 0x08 Scale A */ - u8 sclb; /* 0x09 Scale B */ - u8 res2[2]; /* 0x0A - 0x0B */ - u8 cnt0; /* 0x0C Channel 0 Counter */ - u8 cnt1; /* 0x0D Channel 1 Counter */ - u8 cnt2; /* 0x0E Channel 2 Counter */ - u8 cnt3; /* 0x0F Channel 3 Counter */ - u8 cnt4; /* 0x10 Channel 4 Counter */ - u8 cnt5; /* 0x11 Channel 5 Counter */ - u8 cnt6; /* 0x12 Channel 6 Counter */ - u8 cnt7; /* 0x13 Channel 7 Counter */ - u8 per0; /* 0x14 Channel 0 Period */ - u8 per1; /* 0x15 Channel 1 Period */ - u8 per2; /* 0x16 Channel 2 Period */ - u8 per3; /* 0x17 Channel 3 Period */ - u8 per4; /* 0x18 Channel 4 Period */ - u8 per5; /* 0x19 Channel 5 Period */ - u8 per6; /* 0x1A Channel 6 Period */ - u8 per7; /* 0x1B Channel 7 Period */ - u8 dty0; /* 0x1C Channel 0 Duty */ - u8 dty1; /* 0x1D Channel 1 Duty */ - u8 dty2; /* 0x1E Channel 2 Duty */ - u8 dty3; /* 0x1F Channel 3 Duty */ - u8 dty4; /* 0x20 Channel 4 Duty */ - u8 dty5; /* 0x21 Channel 5 Duty */ - u8 dty6; /* 0x22 Channel 6 Duty */ - u8 dty7; /* 0x23 Channel 7 Duty */ - u8 sdn; /* 0x24 Shutdown */ - u8 res3[3]; /* 0x25 - 0x27 */ -} pwm_t; - -/* Chip configuration module */ -typedef struct rcm { - u8 rcr; - u8 rsr; -} rcm_t; - -typedef struct ccm_ctrl { - u16 ccr; /* 0x00 Chip Cfg */ - u16 res1; /* 0x02 */ - u16 rcon; /* 0x04 Reset Cfg */ - u16 cir; /* 0x06 Chip ID */ - u32 res2; /* 0x08 */ - u16 misccr; /* 0x0A Misc Ctrl */ - u16 cdr; /* 0x0C Clock divider */ - u16 uhcsr; /* 0x10 USB Host status */ - u16 uocsr; /* 0x12 USB On-the-Go Status */ - u16 res3; /* 0x14 */ - u16 codeccr; /* 0x16 Codec Control */ - u16 misccr2; /* 0x18 Misc2 Ctrl */ -} ccm_t; - -/* GPIO port */ -typedef struct gpio_ctrl { - /* Port Output Data */ - u8 podr_fbctl; /* 0x00 */ - u8 podr_be; /* 0x01 */ - u8 podr_cs; /* 0x02 */ - u8 podr_dspi; /* 0x03 */ - u8 res01; /* 0x04 */ - u8 podr_fec0; /* 0x05 */ - u8 podr_feci2c; /* 0x06 */ - u8 res02[2]; /* 0x07 - 0x08 */ - u8 podr_simp1; /* 0x09 */ - u8 podr_simp0; /* 0x0A */ - u8 podr_timer; /* 0x0B */ - u8 podr_uart; /* 0x0C */ - u8 podr_debug; /* 0x0D */ - u8 res03; /* 0x0E */ - u8 podr_sdhc; /* 0x0F */ - u8 podr_ssi; /* 0x10 */ - u8 res04[3]; /* 0x11 - 0x13 */ - - /* Port Data Direction */ - u8 pddr_fbctl; /* 0x14 */ - u8 pddr_be; /* 0x15 */ - u8 pddr_cs; /* 0x16 */ - u8 pddr_dspi; /* 0x17 */ - u8 res05; /* 0x18 */ - u8 pddr_fec0; /* 0x19 */ - u8 pddr_feci2c; /* 0x1A */ - u8 res06[2]; /* 0x1B - 0x1C */ - u8 pddr_simp1; /* 0x1D */ - u8 pddr_simp0; /* 0x1E */ - u8 pddr_timer; /* 0x1F */ - u8 pddr_uart; /* 0x20 */ - u8 pddr_debug; /* 0x21 */ - u8 res07; /* 0x22 */ - u8 pddr_sdhc; /* 0x23 */ - u8 pddr_ssi; /* 0x24 */ - u8 res08[3]; /* 0x25 - 0x27 */ - - /* Port Data Direction */ - u8 ppdr_fbctl; /* 0x28 */ - u8 ppdr_be; /* 0x29 */ - u8 ppdr_cs; /* 0x2A */ - u8 ppdr_dspi; /* 0x2B */ - u8 res09; /* 0x2C */ - u8 ppdr_fec0; /* 0x2D */ - u8 ppdr_feci2c; /* 0x2E */ - u8 res10[2]; /* 0x2F - 0x30 */ - u8 ppdr_simp1; /* 0x31 */ - u8 ppdr_simp0; /* 0x32 */ - u8 ppdr_timer; /* 0x33 */ - u8 ppdr_uart; /* 0x34 */ - u8 ppdr_debug; /* 0x35 */ - u8 res11; /* 0x36 */ - u8 ppdr_sdhc; /* 0x37 */ - u8 ppdr_ssi; /* 0x38 */ - u8 res12[3]; /* 0x39 - 0x3B */ - - /* Port Clear Output Data */ - u8 pclrr_fbctl; /* 0x3C */ - u8 pclrr_be; /* 0x3D */ - u8 pclrr_cs; /* 0x3E */ - u8 pclrr_dspi; /* 0x3F */ - u8 res13; /* 0x40 */ - u8 pclrr_fec0; /* 0x41 */ - u8 pclrr_feci2c; /* 0x42 */ - u8 res14[2]; /* 0x43 - 0x44 */ - u8 pclrr_simp1; /* 0x45 */ - u8 pclrr_simp0; /* 0x46 */ - u8 pclrr_timer; /* 0x47 */ - u8 pclrr_uart; /* 0x48 */ - u8 pclrr_debug; /* 0x49 */ - u8 res15; /* 0x4A */ - u8 pclrr_sdhc; /* 0x4B */ - u8 pclrr_ssi; /* 0x4C */ - u8 res16[3]; /* 0x4D - 0x4F */ - - /* Pin Assignment */ - u8 par_fbctl; /* 0x50 */ - u8 par_be; /* 0x51 */ - u8 par_cs; /* 0x52 */ - u8 res17; /* 0x53 */ - u8 par_dspih; /* 0x54 */ - u8 par_dspil; /* 0x55 */ - u8 par_fec; /* 0x56 */ - u8 par_feci2c; /* 0x57 */ - u8 par_irq0h; /* 0x58 */ - u8 par_irq0l; /* 0x59 */ - u8 par_irq1h; /* 0x5A */ - u8 par_irq1l; /* 0x5B */ - u8 par_simp1h; /* 0x5C */ - u8 par_simp1l; /* 0x5D */ - u8 par_simp0; /* 0x5E */ - u8 par_timer; /* 0x5F */ - u8 par_uart; /* 0x60 */ - u8 res18; /* 0x61 */ - u8 par_debug; /* 0x62 */ - u8 par_sdhc; /* 0x63 */ - u8 par_ssih; /* 0x64 */ - u8 par_ssil; /* 0x65 */ - u8 res19[2]; /* 0x66 - 0x67 */ - - /* Mode Select Control */ - /* Drive Strength Control */ - u8 mscr_mscr1; /* 0x68 */ - u8 mscr_mscr2; /* 0x69 */ - u8 mscr_mscr3; /* 0x6A */ - u8 mscr_mscr45; /* 0x6B */ - u8 srcr_dspi; /* 0x6C */ - u8 dscr_fec; /* 0x6D */ - u8 srcr_i2c; /* 0x6E */ - u8 srcr_irq; /* 0x6F */ - - u8 srcr_sim; /* 0x70 */ - u8 srcr_timer; /* 0x71 */ - u8 srcr_uart; /* 0x72 */ - u8 res20; /* 0x73 */ - u8 srcr_sdhc; /* 0x74 */ - u8 srcr_ssi; /* 0x75 */ - u8 res21[2]; /* 0x76 - 0x77 */ - u8 pcr_pcrh; /* 0x78 */ - u8 pcr_pcrl; /* 0x79 */ -} gpio_t; - -/* SDRAM controller */ -typedef struct sdram_ctrl { - u32 mode; /* 0x00 Mode/Extended Mode */ - u32 ctrl; /* 0x04 Ctrl */ - u32 cfg1; /* 0x08 Cfg 1 */ - u32 cfg2; /* 0x0C Cfg 2 */ - u32 res1[64]; /* 0x10 - 0x10F */ - u32 cs0; /* 0x110 Chip Select 0 Cfg */ - u32 cs1; /* 0x114 Chip Select 1 Cfg */ -} sdram_t; - -/* Clock Module */ -typedef struct pll_ctrl { - u32 pcr; /* 0x00 Ctrl */ - u32 pdr; /* 0x04 Divider */ - u32 psr; /* 0x08 Status */ -} pll_t; - -typedef struct rtcex { - u32 rsvd1[3]; - u32 gocu; - u32 gocl; -} rtcex_t; -#endif /* __IMMAP_5301X__ */ diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h deleted file mode 100644 index 4f255c6..0000000 --- a/include/asm-m68k/immap_5329.h +++ /dev/null @@ -1,402 +0,0 @@ -/* - * MCF5329 Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5329__ -#define __IMMAP_5329__ - -#define MMAP_SCM1 0xEC000000 -#define MMAP_MDHA 0xEC080000 -#define MMAP_SKHA 0xEC084000 -#define MMAP_RNG 0xEC088000 -#define MMAP_SCM2 0xFC000000 -#define MMAP_XBS 0xFC004000 -#define MMAP_FBCS 0xFC008000 -#define MMAP_CAN 0xFC020000 -#define MMAP_FEC 0xFC030000 -#define MMAP_SCM3 0xFC040000 -#define MMAP_EDMA 0xFC044000 -#define MMAP_TCD 0xFC045000 -#define MMAP_INTC0 0xFC048000 -#define MMAP_INTC1 0xFC04C000 -#define MMAP_INTCACK 0xFC054000 -#define MMAP_I2C 0xFC058000 -#define MMAP_QSPI 0xFC05C000 -#define MMAP_UART0 0xFC060000 -#define MMAP_UART1 0xFC064000 -#define MMAP_UART2 0xFC068000 -#define MMAP_DTMR0 0xFC070000 -#define MMAP_DTMR1 0xFC074000 -#define MMAP_DTMR2 0xFC078000 -#define MMAP_DTMR3 0xFC07C000 -#define MMAP_PIT0 0xFC080000 -#define MMAP_PIT1 0xFC084000 -#define MMAP_PIT2 0xFC088000 -#define MMAP_PIT3 0xFC08C000 -#define MMAP_PWM 0xFC090000 -#define MMAP_EPORT 0xFC094000 -#define MMAP_WDOG 0xFC098000 -#define MMAP_RCM 0xFC0A0000 -#define MMAP_CCM 0xFC0A0004 -#define MMAP_GPIO 0xFC0A4000 -#define MMAP_RTC 0xFC0A8000 -#define MMAP_LCDC 0xFC0AC000 -#define MMAP_USBOTG 0xFC0B0000 -#define MMAP_USBH 0xFC0B4000 -#define MMAP_SDRAM 0xFC0B8000 -#define MMAP_SSI 0xFC0BC000 -#define MMAP_PLL 0xFC0C0000 - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* System control module registers */ -typedef struct scm1_ctrl { - u32 mpr0; /* 0x00 Master Privilege Register 0 */ - u32 res1[15]; /* 0x04 - 0x3F */ - u32 pacrh; /* 0x40 Peripheral Access Control Register H */ - u32 res2[3]; /* 0x44 - 0x53 */ - u32 bmt0; /*0x54 Bus Monitor Timeout 0 */ -} scm1_t; - -/* System control module registers 2 */ -typedef struct scm2_ctrl { - u32 mpr1; /* 0x00 Master Privilege Register */ - u32 res1[7]; /* 0x04 - 0x1F */ - u32 pacra; /* 0x20 Peripheral Access Control Register A */ - u32 pacrb; /* 0x24 Peripheral Access Control Register B */ - u32 pacrc; /* 0x28 Peripheral Access Control Register C */ - u32 pacrd; /* 0x2C Peripheral Access Control Register D */ - u32 res2[4]; /* 0x30 - 0x3F */ - u32 pacre; /* 0x40 Peripheral Access Control Register E */ - u32 pacrf; /* 0x44 Peripheral Access Control Register F */ - u32 pacrg; /* 0x48 Peripheral Access Control Register G */ - u32 res3[2]; /* 0x4C - 0x53 */ - u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */ -} scm2_t; - -/* System Control Module register 3 */ -typedef struct scm3_ctrl { - u8 res1[19]; /* 0x00 - 0x12 */ - u8 wcr; /* 0x13 wakeup control register */ - u16 res2; /* 0x14 - 0x15 */ - u16 cwcr; /* 0x16 Core Watchdog Control Register */ - u8 res3[3]; /* 0x18 - 0x1A */ - u8 cwsr; /* 0x1B Core Watchdog Service Register */ - u8 res4[2]; /* 0x1C - 0x1D */ - u8 scmisr; /* 0x1F Interrupt Status Register */ - u32 res5; /* 0x20 */ - u32 bcr; /* 0x24 Burst Configuration Register */ - u32 res6[18]; /* 0x28 - 0x6F */ - u32 cfadr; /* 0x70 Core Fault Address Register */ - u8 res7[4]; /* 0x71 - 0x74 */ - u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */ - u8 cfloc; /* 0x76 Core Fault Location Register */ - u8 cfatr; /* 0x77 Core Fault Attributes Register */ - u32 res8; /* 0x78 */ - u32 cfdtr; /* 0x7C Core Fault Data Register */ -} scm3_t; - -typedef struct canex_ctrl { - can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ -} canex_t; - -/* Watchdog registers */ -typedef struct wdog_ctrl { - u16 cr; /* 0x00 Control register */ - u16 mr; /* 0x02 Modulus register */ - u16 cntr; /* 0x04 Count register */ - u16 sr; /* 0x06 Service register */ -} wdog_t; - -/*Chip configuration module registers */ -typedef struct ccm_ctrl { - u16 ccr; /* 0x00 Chip configuration register */ - u16 res2; /* 0x02 */ - u16 rcon; /* 0x04 Rreset configuration register */ - u16 cir; /* 0x06 Chip identification register */ - u32 res3; /* 0x08 */ - u16 misccr; /* 0x0A Miscellaneous control register */ - u16 cdr; /* 0x0C Clock divider register */ - u16 uhcsr; /* 0x10 USB Host controller status register */ - u16 uocsr; /* 0x12 USB On-the-Go Controller Status Reg */ -} ccm_t; - -typedef struct rcm { - u8 rcr; - u8 rsr; -} rcm_t; - -/* GPIO port registers */ -typedef struct gpio_ctrl { - /* Port Output Data Registers */ -#ifdef CONFIG_M5329 - u8 podr_fech; /* 0x00 */ - u8 podr_fecl; /* 0x01 */ -#else - u16 res00; /* 0x00 - 0x01 */ -#endif - u8 podr_ssi; /* 0x02 */ - u8 podr_busctl; /* 0x03 */ - u8 podr_be; /* 0x04 */ - u8 podr_cs; /* 0x05 */ - u8 podr_pwm; /* 0x06 */ - u8 podr_feci2c; /* 0x07 */ - u8 res08; /* 0x08 */ - u8 podr_uart; /* 0x09 */ - u8 podr_qspi; /* 0x0A */ - u8 podr_timer; /* 0x0B */ -#ifdef CONFIG_M5329 - u8 res0C; /* 0x0C */ - u8 podr_lcddatah; /* 0x0D */ - u8 podr_lcddatam; /* 0x0E */ - u8 podr_lcddatal; /* 0x0F */ - u8 podr_lcdctlh; /* 0x10 */ - u8 podr_lcdctll; /* 0x11 */ -#else - u16 res0C; /* 0x0C - 0x0D */ - u8 podr_fech; /* 0x0E */ - u8 podr_fecl; /* 0x0F */ - u16 res10[3]; /* 0x10 - 0x15 */ -#endif - - /* Port Data Direction Registers */ -#ifdef CONFIG_M5329 - u16 res12; /* 0x12 - 0x13 */ - u8 pddr_fech; /* 0x14 */ - u8 pddr_fecl; /* 0x15 */ -#endif - u8 pddr_ssi; /* 0x16 */ - u8 pddr_busctl; /* 0x17 */ - u8 pddr_be; /* 0x18 */ - u8 pddr_cs; /* 0x19 */ - u8 pddr_pwm; /* 0x1A */ - u8 pddr_feci2c; /* 0x1B */ - u8 res1C; /* 0x1C */ - u8 pddr_uart; /* 0x1D */ - u8 pddr_qspi; /* 0x1E */ - u8 pddr_timer; /* 0x1F */ -#ifdef CONFIG_M5329 - u8 res20; /* 0x20 */ - u8 pddr_lcddatah; /* 0x21 */ - u8 pddr_lcddatam; /* 0x22 */ - u8 pddr_lcddatal; /* 0x23 */ - u8 pddr_lcdctlh; /* 0x24 */ - u8 pddr_lcdctll; /* 0x25 */ - u16 res26; /* 0x26 - 0x27 */ -#else - u16 res20; /* 0x20 - 0x21 */ - u8 pddr_fech; /* 0x22 */ - u8 pddr_fecl; /* 0x23 */ - u16 res24[3]; /* 0x24 - 0x29 */ -#endif - - /* Port Data Direction Registers */ -#ifdef CONFIG_M5329 - u8 ppd_fech; /* 0x28 */ - u8 ppd_fecl; /* 0x29 */ -#endif - u8 ppd_ssi; /* 0x2A */ - u8 ppd_busctl; /* 0x2B */ - u8 ppd_be; /* 0x2C */ - u8 ppd_cs; /* 0x2D */ - u8 ppd_pwm; /* 0x2E */ - u8 ppd_feci2c; /* 0x2F */ - u8 res30; /* 0x30 */ - u8 ppd_uart; /* 0x31 */ - u8 ppd_qspi; /* 0x32 */ - u8 ppd_timer; /* 0x33 */ -#ifdef CONFIG_M5329 - u8 res34; /* 0x34 */ - u8 ppd_lcddatah; /* 0x35 */ - u8 ppd_lcddatam; /* 0x36 */ - u8 ppd_lcddatal; /* 0x37 */ - u8 ppd_lcdctlh; /* 0x38 */ - u8 ppd_lcdctll; /* 0x39 */ - u16 res3A; /* 0x3A - 0x3B */ -#else - u16 res34; /* 0x34 - 0x35 */ - u8 ppd_fech; /* 0x36 */ - u8 ppd_fecl; /* 0x37 */ - u16 res38[3]; /* 0x38 - 0x3D */ -#endif - - /* Port Clear Output Data Registers */ -#ifdef CONFIG_M5329 - u8 res3C; /* 0x3C */ - u8 pclrr_fech; /* 0x3D */ - u8 pclrr_fecl; /* 0x3E */ -#else - u8 pclrr_ssi; /* 0x3E */ -#endif - u8 pclrr_busctl; /* 0x3F */ - u8 pclrr_be; /* 0x40 */ - u8 pclrr_cs; /* 0x41 */ - u8 pclrr_pwm; /* 0x42 */ - u8 pclrr_feci2c; /* 0x43 */ - u8 res44; /* 0x44 */ - u8 pclrr_uart; /* 0x45 */ - u8 pclrr_qspi; /* 0x46 */ - u8 pclrr_timer; /* 0x47 */ -#ifdef CONFIG_M5329 - u8 pclrr_lcddatah; /* 0x48 */ - u8 pclrr_lcddatam; /* 0x49 */ - u8 pclrr_lcddatal; /* 0x4A */ - u8 pclrr_ssi; /* 0x4B */ - u8 pclrr_lcdctlh; /* 0x4C */ - u8 pclrr_lcdctll; /* 0x4D */ - u16 res4E; /* 0x4E - 0x4F */ -#else - u16 res48; /* 0x48 - 0x49 */ - u8 pclrr_fech; /* 0x4A */ - u8 pclrr_fecl; /* 0x4B */ - u8 res4C[5]; /* 0x4C - 0x50 */ -#endif - - /* Pin Assignment Registers */ -#ifdef CONFIG_M5329 - u8 par_fec; /* 0x50 */ -#endif - u8 par_pwm; /* 0x51 */ - u8 par_busctl; /* 0x52 */ - u8 par_feci2c; /* 0x53 */ - u8 par_be; /* 0x54 */ - u8 par_cs; /* 0x55 */ - u16 par_ssi; /* 0x56 */ - u16 par_uart; /* 0x58 */ - u16 par_qspi; /* 0x5A */ - u8 par_timer; /* 0x5C */ -#ifdef CONFIG_M5329 - u8 par_lcddata; /* 0x5D */ - u16 par_lcdctl; /* 0x5E */ -#else - u8 par_fec; /* 0x5D */ - u16 res5E; /* 0x5E - 0x5F */ -#endif - u16 par_irq; /* 0x60 */ - u16 res62; /* 0x62 - 0x63 */ - - /* Mode Select Control Registers */ - u8 mscr_flexbus; /* 0x64 */ - u8 mscr_sdram; /* 0x65 */ - u16 res66; /* 0x66 - 0x67 */ - - /* Drive Strength Control Registers */ - u8 dscr_i2c; /* 0x68 */ - u8 dscr_pwm; /* 0x69 */ - u8 dscr_fec; /* 0x6A */ - u8 dscr_uart; /* 0x6B */ - u8 dscr_qspi; /* 0x6C */ - u8 dscr_timer; /* 0x6D */ - u8 dscr_ssi; /* 0x6E */ -#ifdef CONFIG_M5329 - u8 dscr_lcd; /* 0x6F */ -#else - u8 res6F; /* 0x6F */ -#endif - u8 dscr_debug; /* 0x70 */ - u8 dscr_clkrst; /* 0x71 */ - u8 dscr_irq; /* 0x72 */ -} gpio_t; - -/* USB OTG module registers */ -typedef struct usb_otg { - u32 id; /* 0x000 Identification Register */ - u32 hwgeneral; /* 0x004 General HW Parameters */ - u32 hwhost; /* 0x008 Host HW Parameters */ - u32 hwdev; /* 0x00C Device HW parameters */ - u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */ - u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */ - u32 res1[58]; /* 0x18 - 0xFF */ - u8 caplength; /* 0x100 Capability Register Length */ - u8 res2; /* 0x101 */ - u16 hciver; /* 0x102 Host Interface Version Number */ - u32 hcsparams; /* 0x104 Host Structural Parameters */ - u32 hccparams; /* 0x108 Host Capability Parameters */ - u32 res3[5]; /* 0x10C - 0x11F */ - u16 dciver; /* 0x120 Device Interface Version Number */ - u16 res4; /* 0x122 */ - u32 dccparams; /* 0x124 Device Capability Parameters */ - u32 res5[6]; /* 0x128 - 0x13F */ - u32 cmd; /* 0x140 USB Command */ - u32 sts; /* 0x144 USB Status */ - u32 intr; /* 0x148 USB Interrupt Enable */ - u32 frindex; /* 0x14C USB Frame Index */ - u32 res6; /* 0x150 */ - u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */ - u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */ - u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */ - u32 burstsize; /* 0x160 Master Interface Data Burst Size */ - u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */ - u32 res7[6]; /* 0x168 - 0x17F */ - u32 cfgflag; /* 0x180 Configure Flag Register */ - u32 portsc1; /* 0x184 Port Status/Control */ - u32 res8[7]; /* 0x188 - 0x1A3 */ - u32 otgsc; /* 0x1A4 On The Go Status and Control */ - u32 mode; /* 0x1A8 USB mode register */ - u32 eptsetstat; /* 0x1AC Endpoint Setup status */ - u32 eptprime; /* 0x1B0 Endpoint initialization */ - u32 eptflush; /* 0x1B4 Endpoint de-initialize */ - u32 eptstat; /* 0x1B8 Endpoint status */ - u32 eptcomplete; /* 0x1BC Endpoint Complete */ - u32 eptctrl0; /* 0x1C0 Endpoint control 0 */ - u32 eptctrl1; /* 0x1C4 Endpoint control 1 */ - u32 eptctrl2; /* 0x1C8 Endpoint control 2 */ - u32 eptctrl3; /* 0x1CC Endpoint control 3 */ -} usbotg_t; - -/* SDRAM controller registers */ -typedef struct sdram_ctrl { - u32 mode; /* 0x00 Mode/Extended Mode register */ - u32 ctrl; /* 0x04 Control register */ - u32 cfg1; /* 0x08 Configuration register 1 */ - u32 cfg2; /* 0x0C Configuration register 2 */ - u32 res1[64]; /* 0x10 - 0x10F */ - u32 cs0; /* 0x110 Chip Select 0 Configuration */ - u32 cs1; /* 0x114 Chip Select 1 Configuration */ -} sdram_t; - -/* Clock Module registers */ -typedef struct pll_ctrl { - u8 podr; /* 0x00 Output Divider Register */ - u8 res1[3]; - u8 pcr; /* 0x04 Control Register */ - u8 res2[3]; - u8 pmdr; /* 0x08 Modulation Divider Register */ - u8 res3[3]; - u8 pfdr; /* 0x0C Feedback Divider Register */ - u8 res4[3]; -} pll_t; - -#endif /* __IMMAP_5329__ */ diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h deleted file mode 100644 index 57cf3ec..0000000 --- a/include/asm-m68k/immap_5445x.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - * MCF5445x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_5445X__ -#define __IMMAP_5445X__ - -/* Module Base Addresses */ -#define MMAP_SCM1 0xFC000000 -#define MMAP_XBS 0xFC004000 -#define MMAP_FBCS 0xFC008000 -#define MMAP_FEC0 0xFC030000 -#define MMAP_FEC1 0xFC034000 -#define MMAP_RTC 0xFC03C000 -#define MMAP_SCM2 0xFC040000 -#define MMAP_EDMA 0xFC044000 -#define MMAP_INTC0 0xFC048000 -#define MMAP_INTC1 0xFC04C000 -#define MMAP_IACK 0xFC054000 -#define MMAP_I2C 0xFC058000 -#define MMAP_DSPI 0xFC05C000 -#define MMAP_UART0 0xFC060000 -#define MMAP_UART1 0xFC064000 -#define MMAP_UART2 0xFC068000 -#define MMAP_DTMR0 0xFC070000 -#define MMAP_DTMR1 0xFC074000 -#define MMAP_DTMR2 0xFC078000 -#define MMAP_DTMR3 0xFC07C000 -#define MMAP_PIT0 0xFC080000 -#define MMAP_PIT1 0xFC084000 -#define MMAP_PIT2 0xFC088000 -#define MMAP_PIT3 0xFC08C000 -#define MMAP_EPORT 0xFC094000 -#define MMAP_WTM 0xFC098000 -#define MMAP_SBF 0xFC0A0000 -#define MMAP_RCM 0xFC0A0000 -#define MMAP_CCM 0xFC0A0000 -#define MMAP_GPIO 0xFC0A4000 -#define MMAP_PCI 0xFC0A8000 -#define MMAP_PCIARB 0xFC0AC000 -#define MMAP_RNG 0xFC0B4000 -#define MMAP_SDRAM 0xFC0B8000 -#define MMAP_SSI 0xFC0BC000 -#define MMAP_PLL 0xFC0C4000 -#define MMAP_ATA 0x90000000 -#define MMAP_USBHW 0xFC0B0000 -#define MMAP_USBCAPS 0xFC0B0100 -#define MMAP_USBEHCI 0xFC0B0140 -#define MMAP_USBOTG 0xFC0B01A0 - -#include -#include -#include -#include -#include -#include -#include -#include - -/* Watchdog Timer Modules (WTM) */ -typedef struct wtm { - u16 wcr; - u16 wmr; - u16 wcntr; - u16 wsr; -} wtm_t; - -/* Serial Boot Facility (SBF) */ -typedef struct sbf { - u8 resv0[0x18]; - u16 sbfsr; /* Serial Boot Facility Status Register */ - u8 resv1[0x6]; - u16 sbfcr; /* Serial Boot Facility Control Register */ -} sbf_t; - -/* Reset Controller Module (RCM) */ -typedef struct rcm { - u8 rcr; - u8 rsr; -} rcm_t; - -/* Chip Configuration Module (CCM) */ -typedef struct ccm { - u8 ccm_resv0[0x4]; - u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */ - u8 resv1[0x2]; - u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */ - u16 cir; /* Chip Identification Register (Read-only) */ - u8 resv2[0x4]; - u16 misccr; /* Miscellaneous Control Register */ - u16 cdr; /* Clock Divider Register */ - u16 uocsr; /* USB On-the-Go Controller Status Register */ -} ccm_t; - -/* General Purpose I/O Module (GPIO) */ -typedef struct gpio { - u8 podr_fec0h; /* FEC0 High Port Output Data Register */ - u8 podr_fec0l; /* FEC0 Low Port Output Data Register */ - u8 podr_ssi; /* SSI Port Output Data Register */ - u8 podr_fbctl; /* Flexbus Control Port Output Data Register */ - u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */ - u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */ - u8 podr_dma; /* DMA Port Output Data Register */ - u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */ - u8 resv0[0x1]; - u8 podr_uart; /* UART Port Output Data Register */ - u8 podr_dspi; /* DSPI Port Output Data Register */ - u8 podr_timer; /* Timer Port Output Data Register */ - u8 podr_pci; /* PCI Port Output Data Register */ - u8 podr_usb; /* USB Port Output Data Register */ - u8 podr_atah; /* ATA High Port Output Data Register */ - u8 podr_atal; /* ATA Low Port Output Data Register */ - u8 podr_fec1h; /* FEC1 High Port Output Data Register */ - u8 podr_fec1l; /* FEC1 Low Port Output Data Register */ - u8 resv1[0x2]; - u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */ - u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */ - u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */ - u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */ - u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */ - u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */ - u8 pddr_ssi; /* SSI Port Data Direction Register */ - u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */ - u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */ - u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */ - u8 pddr_dma; /* DMA Port Data Direction Register */ - u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */ - u8 resv2[0x1]; - u8 pddr_uart; /* UART Port Data Direction Register */ - u8 pddr_dspi; /* DSPI Port Data Direction Register */ - u8 pddr_timer; /* Timer Port Data Direction Register */ - u8 pddr_pci; /* PCI Port Data Direction Register */ - u8 pddr_usb; /* USB Port Data Direction Register */ - u8 pddr_atah; /* ATA High Port Data Direction Register */ - u8 pddr_atal; /* ATA Low Port Data Direction Register */ - u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */ - u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */ - u8 resv3[0x2]; - u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */ - u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */ - u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */ - u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */ - u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */ - u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */ - u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */ - u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */ - u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */ - u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */ - u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */ - u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */ - u8 resv4[0x1]; - u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */ - u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */ - u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */ - u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */ - u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */ - u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */ - u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */ - u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */ - u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */ - u8 resv5[0x2]; - u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */ - u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */ - u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */ - u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */ - u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */ - u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */ - u8 pclrr_ssi; /* SSI Port Clear Output Data Register */ - u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */ - u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */ - u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */ - u8 pclrr_dma; /* DMA Port Clear Output Data Register */ - u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */ - u8 resv6[0x1]; - u8 pclrr_uart; /* UART Port Clear Output Data Register */ - u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */ - u8 pclrr_timer; /* Timer Port Clear Output Data Register */ - u8 pclrr_pci; /* PCI Port Clear Output Data Register */ - u8 pclrr_usb; /* USB Port Clear Output Data Register */ - u8 pclrr_atah; /* ATA High Port Clear Output Data Register */ - u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */ - u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */ - u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */ - u8 resv7[0x2]; - u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */ - u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */ - u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */ - u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */ - u8 par_fec; /* FEC Pin Assignment Register */ - u8 par_dma; /* DMA Pin Assignment Register */ - u8 par_fbctl; /* Flexbus Control Pin Assignment Register */ - u8 par_dspi; /* DSPI Pin Assignment Register */ - u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */ - u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */ - u8 par_timer; /* Time Pin Assignment Register */ - u8 par_usb; /* USB Pin Assignment Register */ - u8 resv8[0x1]; - u8 par_uart; /* UART Pin Assignment Register */ - u16 par_feci2c; /* FEC / I2C Pin Assignment Register */ - u16 par_ssi; /* SSI Pin Assignment Register */ - u16 par_ata; /* ATA Pin Assignment Register */ - u8 par_irq; /* IRQ Pin Assignment Register */ - u8 resv9[0x1]; - u16 par_pci; /* PCI Pin Assignment Register */ - u8 mscr_sdram; /* SDRAM Mode Select Control Register */ - u8 mscr_pci; /* PCI Mode Select Control Register */ - u8 resv10[0x2]; - u8 dscr_i2c; /* I2C Drive Strength Control Register */ - u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */ - u8 dscr_fec; /* FEC Drive Strength Control Register */ - u8 dscr_uart; /* UART Drive Strength Control Register */ - u8 dscr_dspi; /* DSPI Drive Strength Control Register */ - u8 dscr_timer; /* TIMER Drive Strength Control Register */ - u8 dscr_ssi; /* SSI Drive Strength Control Register */ - u8 dscr_dma; /* DMA Drive Strength Control Register */ - u8 dscr_debug; /* DEBUG Drive Strength Control Register */ - u8 dscr_reset; /* RESET Drive Strength Control Register */ - u8 dscr_irq; /* IRQ Drive Strength Control Register */ - u8 dscr_usb; /* USB Drive Strength Control Register */ - u8 dscr_ata; /* ATA Drive Strength Control Register */ -} gpio_t; - -/* SDRAM Controller (SDRAMC) */ -typedef struct sdramc { - u32 sdmr; /* SDRAM Mode/Extended Mode Register */ - u32 sdcr; /* SDRAM Control Register */ - u32 sdcfg1; /* SDRAM Configuration Register 1 */ - u32 sdcfg2; /* SDRAM Chip Select Register */ - u8 resv0[0x100]; - u32 sdcs0; /* SDRAM Mode/Extended Mode Register */ - u32 sdcs1; /* SDRAM Mode/Extended Mode Register */ -} sdramc_t; - -/* Phase Locked Loop (PLL) */ -typedef struct pll { - u32 pcr; /* PLL Control Register */ - u32 psr; /* PLL Status Register */ -} pll_t; - -typedef struct pci { - u32 idr; /* 0x00 Device Id / Vendor Id Register */ - u32 scr; /* 0x04 Status / command Register */ - u32 ccrir; /* 0x08 Class Code / Revision Id Register */ - u32 cr1; /* 0x0c Configuration 1 Register */ - u32 bar0; /* 0x10 Base address register 0 Register */ - u32 bar1; /* 0x14 Base address register 1 Register */ - u32 bar2; /* 0x18 Base address register 2 Register */ - u32 bar3; /* 0x1c Base address register 3 Register */ - u32 bar4; /* 0x20 Base address register 4 Register */ - u32 bar5; /* 0x24 Base address register 5 Register */ - u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */ - u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */ - u32 erbar; /* 0x30 Expansion ROM Base Address Register */ - u32 cpr; /* 0x34 Capabilities Pointer Register */ - u32 rsvd1; /* 0x38 */ - u32 cr2; /* 0x3c Configuration Register 2 */ - u32 rsvd2[8]; /* 0x40 - 0x5f */ - - /* General control / status registers */ - u32 gscr; /* 0x60 Global Status / Control Register */ - u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */ - u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */ - u32 tcr1; /* 0x6c Target Control 1 Register */ - u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */ - u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */ - u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */ - u32 rsvd3; /* 0x7c */ - u32 iwcr; /* 0x80 Initiator Window Configuration Register */ - u32 icr; /* 0x84 Initiator Control Register */ - u32 isr; /* 0x88 Initiator Status Register */ - u32 tcr2; /* 0x8c Target Control 2 Register */ - u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */ - u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */ - u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */ - u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */ - u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */ - u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */ - u32 intr; /* 0xa8 Interrupt Register */ - u32 rsvd4[19]; /* 0xac - 0xf7 */ - u32 car; /* 0xf8 Configuration Address Register */ -} pci_t; - -typedef struct pci_arbiter { - /* Pci Arbiter Registers */ - union { - u32 acr; /* Arbiter Control Register */ - u32 asr; /* Arbiter Status Register */ - }; -} pciarb_t; - -/* Register read/write struct */ -typedef struct scm1 { - u32 mpr; /* 0x00 Master Privilege Register */ - u32 rsvd1[7]; - u32 pacra; /* 0x20 Peripheral Access Control Register A */ - u32 pacrb; /* 0x24 Peripheral Access Control Register B */ - u32 pacrc; /* 0x28 Peripheral Access Control Register C */ - u32 pacrd; /* 0x2C Peripheral Access Control Register D */ - u32 rsvd2[4]; - u32 pacre; /* 0x40 Peripheral Access Control Register E */ - u32 pacrf; /* 0x44 Peripheral Access Control Register F */ - u32 pacrg; /* 0x48 Peripheral Access Control Register G */ -} scm1_t; - -typedef struct scm2 { - u8 rsvd1[19]; /* 0x00 - 0x12 */ - u8 wcr; /* 0x13 */ - u16 rsvd2; /* 0x14 - 0x15 */ - u16 cwcr; /* 0x16 */ - u8 rsvd3[3]; /* 0x18 - 0x1A */ - u8 cwsr; /* 0x1B */ - u8 rsvd4[3]; /* 0x1C - 0x1E */ - u8 scmisr; /* 0x1F */ - u32 rsvd5; /* 0x20 - 0x23 */ - u8 bcr; /* 0x24 */ - u8 rsvd6[74]; /* 0x25 - 0x6F */ - u32 cfadr; /* 0x70 */ - u8 rsvd7; /* 0x74 */ - u8 cfier; /* 0x75 */ - u8 cfloc; /* 0x76 */ - u8 cfatr; /* 0x77 */ - u32 rsvd8; /* 0x78 - 0x7B */ - u32 cfdtr; /* 0x7C */ -} scm2_t; - -typedef struct rtcex { - u32 rsvd1[3]; - u32 gocu; - u32 gocl; -} rtcex_t; -#endif /* __IMMAP_5445X__ */ diff --git a/include/asm-m68k/immap_547x_8x.h b/include/asm-m68k/immap_547x_8x.h deleted file mode 100644 index 50f8b05d98..0000000 --- a/include/asm-m68k/immap_547x_8x.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - * MCF547x_8x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_547x_8x__ -#define __IMMAP_547x_8x__ - -#define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700) -#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800) -#define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900) -#define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00) -#define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00) -#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00) -#define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800) -#define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900) -#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800) -#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800) -#define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000) -#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000) -#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00) -#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000) - -#include -#include -#include -#include -#include - -typedef struct siu { - u32 mbar; /* 0x00 */ - u32 drv; /* 0x04 */ - u32 rsvd1[2]; /* 0x08 - 0x1F */ - u32 sbcr; /* 0x10 */ - u32 rsvd2[3]; /* 0x14 - 0x1F */ - u32 cs0cfg; /* 0x20 */ - u32 cs1cfg; /* 0x24 */ - u32 cs2cfg; /* 0x28 */ - u32 cs3cfg; /* 0x2C */ - u32 rsvd3[2]; /* 0x30 - 0x37 */ - u32 secsacr; /* 0x38 */ - u32 rsvd4[2]; /* 0x3C - 0x43 */ - u32 rsr; /* 0x44 */ - u32 rsvd5[2]; /* 0x48 - 0x4F */ - u32 jtagid; /* 0x50 */ -} siu_t; - -typedef struct sdram { - u32 mode; /* 0x00 */ - u32 ctrl; /* 0x04 */ - u32 cfg1; /* 0x08 */ - u32 cfg2; /* 0x0c */ -} sdram_t; - -typedef struct xlb_arb { - u32 cfg; /* 0x240 */ - u32 ver; /* 0x244 */ - u32 sr; /* 0x248 */ - u32 imr; /* 0x24c */ - u32 adrcap; /* 0x250 */ - u32 sigcap; /* 0x254 */ - u32 adrto; /* 0x258 */ - u32 datto; /* 0x25c */ - u32 busto; /* 0x260 */ - u32 prien; /* 0x264 */ - u32 pri; /* 0x268 */ -} xlbarb_t; - -typedef struct gptmr { - u8 ocpw; - u8 octict; - u8 ctrl; - u8 mode; - - u16 pre; /* Prescale */ - u16 cnt; - - u16 pwmwidth; - u8 pwmop; /* Output Polarity */ - u8 pwmld; /* Immediate Update */ - - u16 cap; /* Capture internal counter */ - u8 ovfpin; /* Ovf and Pin */ - u8 intr; /* Interrupts */ -} gptmr_t; - -typedef struct canex_ctrl { - can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ -} canex_t; - - -typedef struct slt { - u32 tcnt; /* 0x00 */ - u32 cr; /* 0x04 */ - u32 cnt; /* 0x08 */ - u32 sr; /* 0x0C */ -} slt_t; - -typedef struct gpio { - /* Port Output Data Registers */ - u8 podr_fbctl; /*0x00 */ - u8 podr_fbcs; /*0x01 */ - u8 podr_dma; /*0x02 */ - u8 rsvd1; /*0x03 */ - u8 podr_fec0h; /*0x04 */ - u8 podr_fec0l; /*0x05 */ - u8 podr_fec1h; /*0x06 */ - u8 podr_fec1l; /*0x07 */ - u8 podr_feci2c; /*0x08 */ - u8 podr_pcibg; /*0x09 */ - u8 podr_pcibr; /*0x0A */ - u8 rsvd2; /*0x0B */ - u8 podr_psc3psc2; /*0x0C */ - u8 podr_psc1psc0; /*0x0D */ - u8 podr_dspi; /*0x0E */ - u8 rsvd3; /*0x0F */ - - /* Port Data Direction Registers */ - u8 pddr_fbctl; /*0x10 */ - u8 pddr_fbcs; /*0x11 */ - u8 pddr_dma; /*0x12 */ - u8 rsvd4; /*0x13 */ - u8 pddr_fec0h; /*0x14 */ - u8 pddr_fec0l; /*0x15 */ - u8 pddr_fec1h; /*0x16 */ - u8 pddr_fec1l; /*0x17 */ - u8 pddr_feci2c; /*0x18 */ - u8 pddr_pcibg; /*0x19 */ - u8 pddr_pcibr; /*0x1A */ - u8 rsvd5; /*0x1B */ - u8 pddr_psc3psc2; /*0x1C */ - u8 pddr_psc1psc0; /*0x1D */ - u8 pddr_dspi; /*0x1E */ - u8 rsvd6; /*0x1F */ - - /* Port Pin Data/Set Data Registers */ - u8 ppdsdr_fbctl; /*0x20 */ - u8 ppdsdr_fbcs; /*0x21 */ - u8 ppdsdr_dma; /*0x22 */ - u8 rsvd7; /*0x23 */ - u8 ppdsdr_fec0h; /*0x24 */ - u8 ppdsdr_fec0l; /*0x25 */ - u8 ppdsdr_fec1h; /*0x26 */ - u8 ppdsdr_fec1l; /*0x27 */ - u8 ppdsdr_feci2c; /*0x28 */ - u8 ppdsdr_pcibg; /*0x29 */ - u8 ppdsdr_pcibr; /*0x2A */ - u8 rsvd8; /*0x2B */ - u8 ppdsdr_psc3psc2; /*0x2C */ - u8 ppdsdr_psc1psc0; /*0x2D */ - u8 ppdsdr_dspi; /*0x2E */ - u8 rsvd9; /*0x2F */ - - /* Port Clear Output Data Registers */ - u8 pclrr_fbctl; /*0x30 */ - u8 pclrr_fbcs; /*0x31 */ - u8 pclrr_dma; /*0x32 */ - u8 rsvd10; /*0x33 */ - u8 pclrr_fec0h; /*0x34 */ - u8 pclrr_fec0l; /*0x35 */ - u8 pclrr_fec1h; /*0x36 */ - u8 pclrr_fec1l; /*0x37 */ - u8 pclrr_feci2c; /*0x38 */ - u8 pclrr_pcibg; /*0x39 */ - u8 pclrr_pcibr; /*0x3A */ - u8 rsvd11; /*0x3B */ - u8 pclrr_psc3psc2; /*0x3C */ - u8 pclrr_psc1psc0; /*0x3D */ - u8 pclrr_dspi; /*0x3E */ - u8 rsvd12; /*0x3F */ - - /* Pin Assignment Registers */ - u16 par_fbctl; /*0x40 */ - u8 par_fbcs; /*0x42 */ - u8 par_dma; /*0x43 */ - u16 par_feci2cirq; /*0x44 */ - u16 rsvd13; /*0x46 */ - u16 par_pcibg; /*0x48 */ - u16 par_pcibr; /*0x4A */ - u8 par_psc3; /*0x4C */ - u8 par_psc2; /*0x4D */ - u8 par_psc1; /*0x4E */ - u8 par_psc0; /*0x4F */ - u16 par_dspi; /*0x50 */ - u8 par_timer; /*0x52 */ - u8 rsvd14; /*0x53 */ -} gpio_t; - -typedef struct pci { - u32 idr; /* 0x00 Device Id / Vendor Id */ - u32 scr; /* 0x04 Status / command */ - u32 ccrir; /* 0x08 Class Code / Revision Id */ - u32 cr1; /* 0x0c Configuration 1 */ - u32 bar0; /* 0x10 Base address register 0 */ - u32 bar1; /* 0x14 Base address register 1 */ - u32 bar2; /* 0x18 NA */ - u32 bar3; /* 0x1c NA */ - u32 bar4; /* 0x20 NA */ - u32 bar5; /* 0x24 NA */ - u32 ccpr; /* 0x28 Cardbus CIS Pointer */ - u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */ - u32 erbar; /* 0x30 Expansion ROM Base Address */ - u32 cpr; /* 0x34 Capabilities Pointer */ - u32 rsvd1; /* 0x38 */ - u32 cr2; /* 0x3c Configuration 2 */ - u32 rsvd2[8]; /* 0x40 - 0x5f */ - - /* General control / status registers */ - u32 gscr; /* 0x60 Global Status / Control */ - u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */ - u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */ - u32 tcr1; /* 0x6c Target Control 1 Register */ - u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */ - u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */ - u32 iw2btar; /* 0x78 NA */ - u32 rsvd3; /* 0x7c */ - u32 iwcr; /* 0x80 Initiator Window Configuration */ - u32 icr; /* 0x84 Initiator Control */ - u32 isr; /* 0x88 Initiator Status */ - u32 tcr2; /* 0x8c NA */ - u32 tbatr0; /* 0x90 NA */ - u32 tbatr1; /* 0x94 NA */ - u32 tbatr2; /* 0x98 NA */ - u32 tbatr3; /* 0x9c NA */ - u32 tbatr4; /* 0xa0 NA */ - u32 tbatr5; /* 0xa4 NA */ - u32 intr; /* 0xa8 NA */ - u32 rsvd4[19]; /* 0xac - 0xf7 */ - u32 car; /* 0xf8 Configuration Address */ -} pci_t; - -typedef struct pci_arbiter { - /* Pci Arbiter Registers */ - union { - u32 acr; /* Arbiter Control */ - u32 asr; /* Arbiter Status */ - }; -} pciarb_t; -#endif /* __IMMAP_547x_8x__ */ diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h deleted file mode 100644 index 531f420..0000000 --- a/include/asm-m68k/io.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * IO header file - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_M68K_IO_H__ -#define __ASM_M68K_IO_H__ - -#include - -#ifndef _IO_BASE -#define _IO_BASE 0 -#endif - -#define __raw_readb(addr) (*(volatile u8 *)(addr)) -#define __raw_readw(addr) (*(volatile u16 *)(addr)) -#define __raw_readl(addr) (*(volatile u32 *)(addr)) - -#define __raw_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) -#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w)) -#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l)) - -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) -#if !defined(__BIG_ENDIAN) -#define readw(addr) (*(volatile u16 *) (addr)) -#define readl(addr) (*(volatile u32 *) (addr)) -#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) -#else -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) -#endif - -/* - * The insw/outsw/insl/outsl macros don't do byte-swapping. - * They are only used in practice for transferring buffers which - * are arrays of bytes, and byte-swapping is not appropriate in - * that case. - paulus - */ -#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - -#define inb(port) in_8((u8 *)((port)+_IO_BASE)) -#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) -#if !defined(__BIG_ENDIAN) -#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) -#else -#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) -#endif - -extern inline void _insb(volatile u8 * port, void *buf, int ns) -{ - u8 *data = (u8 *) buf; - while (ns--) - *data++ = *port; -} - -extern inline void _outsb(volatile u8 * port, const void *buf, int ns) -{ - u8 *data = (u8 *) buf; - while (ns--) - *port = *data++; -} - -extern inline void _insw(volatile u16 * port, void *buf, int ns) -{ - u16 *data = (u16 *) buf; - while (ns--) - *data++ = __sw16(*port); -} - -extern inline void _outsw(volatile u16 * port, const void *buf, int ns) -{ - u16 *data = (u16 *) buf; - while (ns--) { - *port = __sw16(*data); - data++; - } -} - -extern inline void _insl(volatile u32 * port, void *buf, int nl) -{ - u32 *data = (u32 *) buf; - while (nl--) - *data++ = __sw32(*port); -} - -extern inline void _outsl(volatile u32 * port, const void *buf, int nl) -{ - u32 *data = (u32 *) buf; - while (nl--) { - *port = __sw32(*data); - data++; - } -} - -extern inline void _insw_ns(volatile u16 * port, void *buf, int ns) -{ - u16 *data = (u16 *) buf; - while (ns--) - *data++ = *port; -} - -extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) -{ - u16 *data = (u16 *) buf; - while (ns--) { - *port = *data++; - } -} - -extern inline void _insl_ns(volatile u32 * port, void *buf, int nl) -{ - u32 *data = (u32 *) buf; - while (nl--) - *data++ = *port; -} - -extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) -{ - u32 *data = (u32 *) buf; - while (nl--) { - *port = *data; - data++; - } -} - -/* - * The *_ns versions below don't do byte-swapping. - * Neither do the standard versions now, these are just here - * for older code. - */ -#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - -#define IO_SPACE_LIMIT ~0 - -/* - * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - */ -extern inline int in_8(volatile u8 * addr) -{ - return (int)*addr; -} - -extern inline void out_8(volatile u8 * addr, int val) -{ - *addr = (u8) val; -} - -extern inline int in_le16(volatile u16 * addr) -{ - return __sw16(*addr); -} - -extern inline int in_be16(volatile u16 * addr) -{ - return (*addr & 0xFFFF); -} - -extern inline void out_le16(volatile u16 * addr, int val) -{ - *addr = __sw16(val); -} - -extern inline void out_be16(volatile u16 * addr, int val) -{ - *addr = (u16) val; -} - -extern inline unsigned in_le32(volatile u32 * addr) -{ - return __sw32(*addr); -} - -extern inline unsigned in_be32(volatile u32 * addr) -{ - return (*addr); -} - -extern inline void out_le32(volatile unsigned *addr, int val) -{ - *addr = __sw32(val); -} - -extern inline void out_be32(volatile unsigned *addr, int val) -{ - *addr = val; -} - -static inline void sync(void) -{ - /* This sync function is for PowerPC or other architecture instruction - * ColdFire does not have this instruction. Dummy function, added for - * compatibility (CFI driver) - */ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void *map_physmem(phys_addr_t paddr, unsigned long len, - unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -#endif /* __ASM_M68K_IO_H__ */ diff --git a/include/asm-m68k/m520x.h b/include/asm-m68k/m520x.h deleted file mode 100644 index 71f147e..0000000 --- a/include/asm-m68k/m520x.h +++ /dev/null @@ -1,357 +0,0 @@ -/* - * m520x.h -- Definitions for Freescale Coldfire 520x - * - * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __M520X__ -#define __M520X__ - -/* *** System Control Module (SCM) *** */ -#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) -#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) -#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) -#define MPROT_MTR 4 -#define MPROT_MTW 2 -#define MPROT_MPL 1 - -#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) -#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) -#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) - -#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) - -#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) -#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) -#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) -#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8) -#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4) -#define SCM_PACRC_PACR23(x) ((x) & 0x0F) - -#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28) -#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24) -#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20) -#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12) -#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8) -#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4) -#define SCM_PACRD_PACR31(x) ((x) & 0x0F) - -#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28) -#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24) -#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20) -#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16) -#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12) - -#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28) -#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24) -#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20) - -#define PACR_SP 4 -#define PACR_WP 2 -#define PACR_TP 1 - -#define SCM_BMT_BME (0x00000008) -#define SCM_BMT_BMT(x) ((x) & 0x07) -#define SCM_BMT_BMT1024 (0x0000) -#define SCM_BMT_BMT512 (0x0001) -#define SCM_BMT_BMT256 (0x0002) -#define SCM_BMT_BMT128 (0x0003) -#define SCM_BMT_BMT64 (0x0004) -#define SCM_BMT_BMT32 (0x0005) -#define SCM_BMT_BMT16 (0x0006) -#define SCM_BMT_BMT8 (0x0007) - -#define SCM_CWCR_RO (0x8000) -#define SCM_CWCR_CWR_WH (0x0100) -#define SCM_CWCR_CWE (0x0080) -#define SCM_CWRI_WINDOW (0x0060) -#define SCM_CWRI_RESET (0x0040) -#define SCM_CWRI_INT_RESET (0x0020) -#define SCM_CWRI_INT (0x0000) -#define SCM_CWCR_CWT(x) (((x) & 0x001F)) - -#define SCM_ISR_CFEI (0x02) -#define SCM_ISR_CWIC (0x01) - -#define SCM_CFIER_ECFEI (0x01) - -#define SCM_CFLOC_LOC (0x80) - -#define SCM_CFATR_WRITE (0x80) -#define SCM_CFATR_SZ32 (0x20) -#define SCM_CFATR_SZ16 (0x10) -#define SCM_CFATR_SZ08 (0x00) -#define SCM_CFATR_CACHE (0x08) -#define SCM_CFATR_MODE (0x02) -#define SCM_CFATR_TYPE (0x01) - -/* *** Interrupt Controller (INTC) *** */ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT_F1 (1) -#define INT0_LO_EPORT_F4 (2) -#define INT0_LO_EPORT_F7 (3) -#define INT1_LO_PIT0 (4) -#define INT1_LO_PIT1 (5) -/* 6 - 7 rsvd */ -#define INT0_LO_EDMA_00 (8) -#define INT0_LO_EDMA_01 (9) -#define INT0_LO_EDMA_02 (10) -#define INT0_LO_EDMA_03 (11) -#define INT0_LO_EDMA_04 (12) -#define INT0_LO_EDMA_05 (13) -#define INT0_LO_EDMA_06 (14) -#define INT0_LO_EDMA_07 (15) -#define INT0_LO_EDMA_08 (16) -#define INT0_LO_EDMA_09 (17) -#define INT0_LO_EDMA_10 (18) -#define INT0_LO_EDMA_11 (19) -#define INT0_LO_EDMA_12 (20) -#define INT0_LO_EDMA_13 (21) -#define INT0_LO_EDMA_14 (22) -#define INT0_LO_EDMA_15 (23) -#define INT0_LO_EDMA_ERR (24) -#define INT0_LO_SCM_CWIC (25) -#define INT0_LO_UART0 (26) -#define INT0_LO_UART1 (27) -#define INT0_LO_UART2 (28) -/* 29 rsvd */ -#define INT0_LO_I2C (30) -#define INT0_LO_QSPI (31) - -#define INT0_HI_DTMR0 (32) -#define INT0_HI_DTMR1 (33) -#define INT0_HI_DTMR2 (34) -#define INT0_HI_DTMR3 (35) -#define INT0_HI_FEC0_TXF (36) -#define INT0_HI_FEC0_TXB (37) -#define INT0_HI_FEC0_UN (38) -#define INT0_HI_FEC0_RL (39) -#define INT0_HI_FEC0_RXF (40) -#define INT0_HI_FEC0_RXB (41) -#define INT0_HI_FEC0_MII (42) -#define INT0_HI_FEC0_LC (43) -#define INT0_HI_FEC0_HBERR (44) -#define INT0_HI_FEC0_GRA (45) -#define INT0_HI_FEC0_EBERR (46) -#define INT0_HI_FEC0_BABT (47) -#define INT0_HI_FEC0_BABR (48) -/* 49 - 61 rsvd */ -#define INT0_HI_SCMISR_CFEI (62) - -/* *** Reset Controller Module (RCM) *** */ -#define RCM_RCR_SOFTRST (0x80) -#define RCM_RCR_FRCRSTOUT (0x40) - -#define RCM_RSR_SOFT (0x20) -#define RCM_RSR_WDOG (0x10) -#define RCM_RSR_POR (0x08) -#define RCM_RSR_EXT (0x04) -#define RCM_RSR_WDR_CORE (0x02) -#define RCM_RSR_LOL (0x01) - -/* *** Chip Configuration Module (CCM) *** */ -#define CCM_CCR_CSC (0x0200) -#define CCM_CCR_OSCFREQ (0x0080) -#define CCM_CCR_LIMP (0x0040) -#define CCM_CCR_LOAD (0x0020) -#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3) -#define CCM_CCR_OSC_MODE (0x0004) -#define CCM_CCR_PLL_MODE (0x0002) -#define CCM_CCR_RESERVED (0x0001) - -#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) -#define CCM_CIR_PRN(x) ((x) & 0x003F) - -/* *** General Purpose I/O (GPIO) *** */ -#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F) -#define GPIO_PDR_BE(x) ((x) & 0x0F) -#define GPIO_PDR_CS(x) (((x) & 0x07) << 1) -#define GPIO_PDR_FECI2C(x) ((x) & 0x0F) -#define GPIO_PDR_QSPI(x) ((x) & 0x0F) -#define GPIO_PDR_TIMER(x) ((x) & 0x0F) -#define GPIO_PDR_UART(x) ((x) & 0xFF) -#define GPIO_PDR_FECH(x) ((x) & 0xFF) -#define GPIO_PDR_FECL(x) ((x) & 0xFF) - -#define GPIO_PAR_FBCTL_OE (0x10) -#define GPIO_PAR_FBCTL_TA (0x08) -#define GPIO_PAR_FBCTL_RWB (0x04) -#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC) -#define GPIO_PAR_FBCTL_TS_TS (0x03) -#define GPIO_PAR_FBCTL_TS_DMA (0x02) - -#define GPIO_PAR_BE3 (0x08) -#define GPIO_PAR_BE2 (0x04) -#define GPIO_PAR_BE1 (0x02) -#define GPIO_PAR_BE0 (0x01) - -#define GPIO_PAR_CS3 (0x08) -#define GPIO_PAR_CS2 (0x04) -#define GPIO_PAR_CS1_UNMASK (0xFC) -#define GPIO_PAR_CS1_CS1 (0x03) -#define GPIO_PAR_CS1_SDCS1 (0x02) - -#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F) -#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F) -#define GPIO_PAR_FECI2C_MDC_MDC (0xC0) -#define GPIO_PAR_FECI2C_MDC_SCL (0x80) -#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40) -#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF) -#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30) -#define GPIO_PAR_FECI2C_MDIO_SDA (0x20) -#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10) -#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0) -#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3) -#define GPIO_PAR_FECI2C_SCL_SCL (0x0C) -#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04) -#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC) -#define GPIO_PAR_FECI2C_SDA_SDA (0x03) -#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01) - -#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F) -#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0) -#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80) -#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40) -#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF) -#define GPIO_PAR_QSPI_DIN_DIN (0x30) -#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20) -#define GPIO_PAR_QSPI_DIN_U2CTS (0x10) -#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3) -#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C) -#define GPIO_PAR_QSPI_DOUT_SDA (0x08) -#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC) -#define GPIO_PAR_QSPI_SCK_SCK (0x03) -#define GPIO_PAR_QSPI_SCK_SCL (0x02) - -#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6) -#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4) -#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2) -#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03) -#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F) -#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0) -#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80) -#define GPIO_PAR_TMR_TIN3_U2CTS (0x40) -#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF) -#define GPIO_PAR_TMR_TIN2_TIN2 (0x30) -#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20) -#define GPIO_PAR_TMR_TIN2_U2RTS (0x10) -#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3) -#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C) -#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08) -#define GPIO_PAR_TMR_TIN1_U2RXD (0x04) -#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC) -#define GPIO_PAR_TMR_TIN0_TIN0 (0x03) -#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02) -#define GPIO_PAR_TMR_TIN0_U2TXD (0x01) - -#define GPIO_PAR_UART1_UNMASK (0xF03F) -#define GPIO_PAR_UART0_UNMASK (0xFFC0) -#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF) -#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00) -#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800) -#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400) -#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF) -#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300) -#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200) -#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100) -#define GPIO_PAR_UART_U1TXD (0x0080) -#define GPIO_PAR_UART_U1RXD (0x0040) -#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF) -#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030) -#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020) -#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010) -#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3) -#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C) -#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008) -#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004) -#define GPIO_PAR_UART_U0TXD (0x0002) -#define GPIO_PAR_UART_U0RXD (0x0001) - -#define GPIO_PAR_FEC_7W_UNMASK (0xF3) -#define GPIO_PAR_FEC_7W_FEC (0x0C) -#define GPIO_PAR_FEC_7W_U1RTS (0x04) -#define GPIO_PAR_FEC_MII_UNMASK (0xFC) -#define GPIO_PAR_FEC_MII_FEC (0x03) -#define GPIO_PAR_FEC_MII_UnCTS (0x01) - -#define GPIO_PAR_IRQ_IRQ4 (0x01) - -#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6) -#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4) -#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2) -#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03) -#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F) -#define GPIO_MSCR_FB_DUP_UNMASK (0xCF) -#define GPIO_MSCR_FB_DLO_UNMASK (0xF3) -#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC) - -#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4) -#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2) -#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03) -#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF) -#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3) -#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC) - -#define MSCR_25VDDR (0x03) -#define MSCR_18VDDR_FULL (0x02) -#define MSCR_OPENDRAIN (0x01) -#define MSCR_18VDDR_HALF (0x00) - -#define GPIO_DSCR_I2C(x) ((x) & 0x03) -#define GPIO_DSCR_I2C_UNMASK (0xFC) - -#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF) -#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3) -#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03) -#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC) - -#define GPIO_DSCR_FEC(x) ((x) & 0x03) -#define GPIO_DSCR_FEC_UNMASK (0xFC) - -#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4) -#define GPIO_DSCR_UART_UART1_UNMASK (0xCF) -#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2) -#define GPIO_DSCR_UART_UART0_UNMASK (0xF3) -#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03) -#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC) - -#define GPIO_DSCR_QSPI(x) ((x) & 0x03) -#define GPIO_DSCR_QSPI_UNMASK (0xFC) - -#define DSCR_50PF (0x03) -#define DSCR_30PF (0x02) -#define DSCR_20PF (0x01) -#define DSCR_10PF (0x00) - -/* *** Phase Locked Loop (PLL) *** */ -#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4) -#define PLL_PODR_CPUDIV_UNMASK (0x0F) -#define PLL_PODR_BUSDIV(x) ((x) & 0x0F) -#define PLL_PODR_BUSDIV_UNMASK (0xF0) - -#define PLL_PCR_DITHEN (0x80) -#define PLL_PCR_DITHDEV(x) ((x) & 0x07) -#define PLL_PCR_DITHDEV_UNMASK (0xF8) - -#endif /* __M520X__ */ diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h deleted file mode 100644 index c77d5dd..0000000 --- a/include/asm-m68k/m5227x.h +++ /dev/null @@ -1,563 +0,0 @@ -/* - * MCF5227x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MCF5227X__ -#define __MCF5227X__ - -/* Interrupt Controller (INTC) */ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_EDMA_00 (8) -#define INT0_LO_EDMA_01 (9) -#define INT0_LO_EDMA_02 (10) -#define INT0_LO_EDMA_03 (11) -#define INT0_LO_EDMA_04 (12) -#define INT0_LO_EDMA_05 (13) -#define INT0_LO_EDMA_06 (14) -#define INT0_LO_EDMA_07 (15) -#define INT0_LO_EDMA_08 (16) -#define INT0_LO_EDMA_09 (17) -#define INT0_LO_EDMA_10 (18) -#define INT0_LO_EDMA_11 (19) -#define INT0_LO_EDMA_12 (20) -#define INT0_LO_EDMA_13 (21) -#define INT0_LO_EDMA_14 (22) -#define INT0_LO_EDMA_15 (23) -#define INT0_LO_EDMA_ERR (24) -#define INT0_LO_SCM_CWIC (25) -#define INT0_LO_UART0 (26) -#define INT0_LO_UART1 (27) -#define INT0_LO_UART2 (28) -#define INT0_LO_I2C (30) -#define INT0_LO_DSPI (31) -#define INT0_HI_DTMR0 (32) -#define INT0_HI_DTMR1 (33) -#define INT0_HI_DTMR2 (34) -#define INT0_HI_DTMR3 (35) -#define INT0_HI_SCMIR (62) -#define INT0_HI_RTC_ISR (63) - -#define INT1_HI_CAN_BOFFINT (1) -#define INT1_HI_CAN_ERRINT (3) -#define INT1_HI_CAN_BUF0I (4) -#define INT1_HI_CAN_BUF1I (5) -#define INT1_HI_CAN_BUF2I (6) -#define INT1_HI_CAN_BUF3I (7) -#define INT1_HI_CAN_BUF4I (8) -#define INT1_HI_CAN_BUF5I (9) -#define INT1_HI_CAN_BUF6I (10) -#define INT1_HI_CAN_BUF7I (11) -#define INT1_HI_CAN_BUF8I (12) -#define INT1_HI_CAN_BUF9I (13) -#define INT1_HI_CAN_BUF10I (14) -#define INT1_HI_CAN_BUF11I (15) -#define INT1_HI_CAN_BUF12I (16) -#define INT1_HI_CAN_BUF13I (17) -#define INT1_HI_CAN_BUF14I (18) -#define INT1_HI_CAN_BUF15I (19) -#define INT1_HI_PIT0_PIF (43) -#define INT1_HI_PIT1_PIF (44) -#define INT1_HI_USBOTG_STS (47) -#define INT1_HI_SSI_ISR (49) -#define INT1_HI_PWM_INT (50) -#define INT1_HI_LCDC_ISR (51) -#define INT1_HI_CCM_UOCSR (53) -#define INT1_HI_DSPI_EOQF (54) -#define INT1_HI_DSPI_TFFF (55) -#define INT1_HI_DSPI_TCF (56) -#define INT1_HI_DSPI_TFUF (57) -#define INT1_HI_DSPI_RFDF (58) -#define INT1_HI_DSPI_RFOF (59) -#define INT1_HI_DSPI_RFOF_TFUF (60) -#define INT1_HI_TOUCH_ADC (61) -#define INT1_HI_PLL_LOCKS (62) - -/********************************************************************* -* Reset Controller Module (RCM) -*********************************************************************/ - -/* Bit definitions and macros for RCR */ -#define RCM_RCR_FRCRSTOUT (0x40) -#define RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for RSR */ -#define RCM_RSR_LOL (0x01) -#define RCM_RSR_WDR_CORE (0x02) -#define RCM_RSR_EXT (0x04) -#define RCM_RSR_POR (0x08) -#define RCM_RSR_SOFT (0x20) - -/********************************************************************* -* Chip Configuration Module (CCM) -*********************************************************************/ - -/* Bit definitions and macros for CCR */ -#define CCM_CCR_DRAMSEL (0x0100) -#define CCM_CCR_CSC_UNMASK (0xFF3F) -#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0) -#define CCM_CCR_CSC_FBCS5_A22 (0x0080) -#define CCM_CCR_CSC_FB_A23_A22 (0x0040) -#define CCM_CCR_LIMP (0x0020) -#define CCM_CCR_LOAD (0x0010) -#define CCM_CCR_BOOTPS_UNMASK (0xFFF3) -#define CCM_CCR_BOOTPS_PS16 (0x0008) -#define CCM_CCR_BOOTPS_PS8 (0x0004) -#define CCM_CCR_BOOTPS_PS32 (0x0000) -#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002) - -/* Bit definitions and macros for RCON */ -#define CCM_RCON_CSC_UNMASK (0xFF3F) -#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0) -#define CCM_RCON_CSC_FBCS5_A22 (0x0080) -#define CCM_RCON_CSC_FB_A23_A22 (0x0040) -#define CCM_RCON_LIMP (0x0020) -#define CCM_RCON_LOAD (0x0010) -#define CCM_RCON_BOOTPS_UNMASK (0xFFF3) -#define CCM_RCON_BOOTPS_PS16 (0x0008) -#define CCM_RCON_BOOTPS_PS8 (0x0004) -#define CCM_RCON_BOOTPS_PS32 (0x0000) -#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002) - -/* Bit definitions and macros for CIR */ -#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) -#define CCM_CIR_PRN(x) ((x) & 0x003F) -#define CCM_CIR_PIN_MCF52277 (0x0000) - -/* Bit definitions and macros for MISCCR */ -#define CCM_MISCCR_RTCSRC (0x4000) -#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */ -#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ - -#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */ -#define CCM_MISCCR_BMT_65536 (0) -#define CCM_MISCCR_BMT_32768 (1) -#define CCM_MISCCR_BMT_16384 (2) -#define CCM_MISCCR_BMT_8192 (3) -#define CCM_MISCCR_BMT_4096 (4) -#define CCM_MISCCR_BMT_2048 (5) -#define CCM_MISCCR_BMT_1024 (6) -#define CCM_MISCCR_BMT_512 (7) - -#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ -#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ -#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ -#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ -#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */ -#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */ -#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ - -/* Bit definitions and macros for CDR */ -#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12) -#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */ -#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */ - -/* Bit definitions and macros for UOCSR */ -#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */ -#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */ -#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */ -#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */ -#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */ -#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ -#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ -#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ -#define CCM_UOCSR_SEND (0x0010) /* Session end */ -#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ -#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */ -#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */ - -/********************************************************************* -* General Purpose I/O Module (GPIO) -*********************************************************************/ -/* Bit definitions and macros for PAR_BE */ -#define GPIO_PAR_BE_UNMASK (0x0F) -#define GPIO_PAR_BE_BE3_BE3 (0x08) -#define GPIO_PAR_BE_BE3_GPIO (0x00) -#define GPIO_PAR_BE_BE2_BE2 (0x04) -#define GPIO_PAR_BE_BE2_GPIO (0x00) -#define GPIO_PAR_BE_BE1_BE1 (0x02) -#define GPIO_PAR_BE_BE1_GPIO (0x00) -#define GPIO_PAR_BE_BE0_BE0 (0x01) -#define GPIO_PAR_BE_BE0_GPIO (0x00) - -/* Bit definitions and macros for PAR_CS */ -#define GPIO_PAR_CS_CS3 (0x10) -#define GPIO_PAR_CS_CS2 (0x08) -#define GPIO_PAR_CS_CS1_FBCS1 (0x06) -#define GPIO_PAR_CS_CS1_SDCS1 (0x04) -#define GPIO_PAR_CS_CS1_GPIO (0x00) -#define GPIO_PAR_CS_CS0 (0x01) - -/* Bit definitions and macros for PAR_FBCTL */ -#define GPIO_PAR_FBCTL_OE (0x80) -#define GPIO_PAR_FBCTL_TA (0x40) -#define GPIO_PAR_FBCTL_RW (0x20) -#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) -#define GPIO_PAR_FBCTL_TS_FBTS (0x18) -#define GPIO_PAR_FBCTL_TS_DMAACK (0x10) -#define GPIO_PAR_FBCTL_TS_GPIO (0x00) - -/* Bit definitions and macros for PAR_FECI2C */ -#define GPIO_PAR_I2C_SCL_UNMASK (0xF3) -#define GPIO_PAR_I2C_SCL_SCL (0x0C) -#define GPIO_PAR_I2C_SCL_CANTXD (0x08) -#define GPIO_PAR_I2C_SCL_U2TXD (0x04) -#define GPIO_PAR_I2C_SCL_GPIO (0x00) - -#define GPIO_PAR_I2C_SDA_UNMASK (0xFC) -#define GPIO_PAR_I2C_SDA_SDA (0x03) -#define GPIO_PAR_I2C_SDA_CANRXD (0x02) -#define GPIO_PAR_I2C_SDA_U2RXD (0x01) -#define GPIO_PAR_I2C_SDA_GPIO (0x00) - -/* Bit definitions and macros for PAR_UART */ -#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF) -#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000) -#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000) -#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000) -#define GPIO_PAR_UART_U1CTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF) -#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000) -#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000) -#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000) -#define GPIO_PAR_UART_U1RTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF) -#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) -#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800) -#define GPIO_PAR_UART_U1RXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF) -#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) -#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200) -#define GPIO_PAR_UART_U1TXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F) -#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0) -#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080) -#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040) -#define GPIO_PAR_UART_U0CTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF) -#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030) -#define GPIO_PAR_UART_U0RTS_T1IN (0x0020) -#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010) -#define GPIO_PAR_UART_U0RTS_GPIO (0x0000) - -#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3) -#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C) -#define GPIO_PAR_UART_U0RXD_CANRX (0x0008) -#define GPIO_PAR_UART_U0RXD_GPIO (0x0000) - -#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC) -#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003) -#define GPIO_PAR_UART_U0TXD_CANTX (0x0002) -#define GPIO_PAR_UART_U0TXD_GPIO (0x0000) - -/* Bit definitions and macros for PAR_DSPI */ -#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F) -#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0) -#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80) -#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) -#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF) -#define GPIO_PAR_DSPI_SIN_SIN (0x30) -#define GPIO_PAR_DSPI_SIN_U2RXD (0x20) -#define GPIO_PAR_DSPI_SIN_GPIO (0x00) -#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3) -#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C) -#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08) -#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) -#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC) -#define GPIO_PAR_DSPI_SCK_SCK (0x03) -#define GPIO_PAR_DSPI_SCK_U2CTS (0x02) -#define GPIO_PAR_DSPI_SCK_GPIO (0x00) - -/* Bit definitions and macros for PAR_TIMER */ -#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) -#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) -#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) -#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40) -#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) -#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) -#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) -#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10) -#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) -#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) -#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) -#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04) -#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) -#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) -#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) -#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) -#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01) -#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) - -/* Bit definitions and macros for GPIO_PAR_LCDCTL */ -#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7) -#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18) -#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10) -#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00) -#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04) -#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02) -#define GPIO_PAR_LCDCTL_LSCLK (0x01) - -/* Bit definitions and macros for PAR_IRQ */ -#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3) -#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C) -#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08) -#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) -#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC) -#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03) -#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02) -#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01) -#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) - -/* Bit definitions and macros for GPIO_PAR_LCDH */ -#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF) -#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00) -#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800) -#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF) -#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300) -#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200) -#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F) -#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0) -#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080) -#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF) -#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030) -#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020) -#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3) -#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C) -#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008) -#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000) - -#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC) -#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003) -#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002) -#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000) - -/* Bit definitions and macros for GPIO_PAR_LCDL */ -#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF) -#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000) -#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000) -#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF) -#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000) -#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000) -#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF) -#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000) -#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000) -#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF) -#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000) -#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000) -#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF) -#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000) -#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000) -#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF) -#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000) -#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000) -#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF) -#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000) -#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000) -#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF) -#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000) -#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000) -#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF) -#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000) -#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000) -#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF) -#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000) -#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000) -#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF) -#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00) -#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800) -#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000) - -#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF) -#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300) -#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200) -#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000) - -/* Bit definitions and macros for MSCR_FB */ -#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF) -#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30) -#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20) -#define GPIO_MSCR_FB_DUPPER_OD (0x10) -#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00) - -#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3) -#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C) -#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08) -#define GPIO_MSCR_FB_DLOWER_OD (0x04) -#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00) - -#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC) -#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03) -#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02) -#define GPIO_MSCR_FB_ADDRCTL_OD (0x01) -#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00) - -/* Bit definitions and macros for MSCR_SDRAM */ -#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF) -#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30) -#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20) -#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10) -#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00) - -#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) -#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C) -#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08) -#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04) -#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00) - -#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) -#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03) -#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02) -#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01) -#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00) - -/* Bit definitions and macros for Drive Strength Control */ -#define DSCR_LOAD_50PF (0x03) -#define DSCR_LOAD_30PF (0x02) -#define DSCR_LOAD_20PF (0x01) -#define DSCR_LOAD_10PF (0x00) - -/********************************************************************* -* SDRAM Controller (SDRAMC) -*********************************************************************/ - -/* Bit definitions and macros for SDMR */ -#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ -#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ -#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ -#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ -#define SDRAMC_SDMR_BK_LMR (0x00000000) -#define SDRAMC_SDMR_BK_LEMR (0x40000000) - -/* Bit definitions and macros for SDCR */ -#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ -#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ -#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ -#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ -#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ -#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ -#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ -#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ -#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ -#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ -#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ -#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ -#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ -#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) - -/* Bit definitions and macros for SDCFG1 */ -#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ -#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ -#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ -#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ -#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ -#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ -#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ - -/* Bit definitions and macros for SDCFG2 */ -#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ -#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ -#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ -#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ - -/* Bit definitions and macros for SDCS group */ -#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ -#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ -#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) -#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) -#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) -#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) -#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) -#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) -#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) -#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) -#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) -#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) -#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) -#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) -#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) -#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) -#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) - -/********************************************************************* -* Phase Locked Loop (PLL) -*********************************************************************/ - -/* Bit definitions and macros for PCR */ -#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ -#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */ -#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */ -#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ -#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ -#define PLL_PCR_PFDR_MASK (0x000F0000) -#define PLL_PCR_OUTDIV5_MASK (0x000F0000) -#define PLL_PCR_OUTDIV3_MASK (0x00000F00) -#define PLL_PCR_OUTDIV2_MASK (0x000000F0) -#define PLL_PCR_OUTDIV1_MASK (0x0000000F) - -/* Bit definitions and macros for PSR */ -#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ -#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ -#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ -#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ - -/********************************************************************/ - -#endif /* __MCF5227X__ */ diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h deleted file mode 100644 index 71a40d3..0000000 --- a/include/asm-m68k/m5235.h +++ /dev/null @@ -1,602 +0,0 @@ -/* - * mcf5329.h -- Definitions for Freescale Coldfire 5329 - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef mcf5235_h -#define mcf5235_h -/****************************************************************************/ - -/********************************************************************* -* System Control Module (SCM) -*********************************************************************/ - -/* Bit definition and macros for SCM_IPSBAR */ -#define SCM_IPSBAR_BA(x) (((x)&0x03)<<30) -#define SCM_IPSBAR_V (0x00000001) - -/* Bit definition and macros for SCM_RAMBAR */ -#define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16) -#define SCM_RAMBAR_BDE (0x00000200) - -/* Bit definition and macros for SCM_CRSR */ -#define SCM_CRSR_EXT (0x80) - -/* Bit definitions and macros for SCM_CWCR */ -#define SCM_CWCR_CWE (0x80) -#define SCM_CWCR_CWRI (0x40) -#define SCM_CWCR_CWT(x) (((x)&0x07)<<3) -#define SCM_CWCR_CWTA (0x04) -#define SCM_CWCR_CWTAVAL (0x02) -#define SCM_CWCR_CWTIC (0x01) - -/* Bit definitions and macros for SCM_LPICR */ -#define SCM_LPICR_ENBSTOP (0x80) -#define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) -#define SCM_LPICR_XLPM_IPL_ANY (0x00) -#define SCM_LPICR_XLPM_IPL_L2_7 (0x10) -#define SCM_LPICR_XLPM_IPL_L3_7 (0x20) -#define SCM_LPICR_XLPM_IPL_L4_7 (0x30) -#define SCM_LPICR_XLPM_IPL_L5_7 (0x40) -#define SCM_LPICR_XLPM_IPL_L6_7 (0x50) -#define SCM_LPICR_XLPM_IPL_L7 (0x70) - -/* Bit definitions and macros for SCM_DMAREQC */ -#define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16) -#define SCM_DMAREQC_EXT_ETPU (0x00080000) -#define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000) -#define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000) -#define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000) -#define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12) -#define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8) -#define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4) -#define SCM_DMAREQC_DMAC0(x) (((x)&0x0F)) -#define SCM_DMAREQC_DMACn_DTMR0 (0x04) -#define SCM_DMAREQC_DMACn_DTMR1 (0x05) -#define SCM_DMAREQC_DMACn_DTMR2 (0x06) -#define SCM_DMAREQC_DMACn_DTMR3 (0x07) -#define SCM_DMAREQC_DMACn_UART0RX (0x08) -#define SCM_DMAREQC_DMACn_UART1RX (0x09) -#define SCM_DMAREQC_DMACn_UART2RX (0x0A) -#define SCM_DMAREQC_DMACn_UART0TX (0x0C) -#define SCM_DMAREQC_DMACn_UART1TX (0x0D) -#define SCM_DMAREQC_DMACn_UART3TX (0x0E) - -/* Bit definitions and macros for SCM_MPARK */ -#define SCM_MPARK_M2_P_EN (0x02000000) -#define SCM_MPARK_M3_PRTY_MSK (0x00C00000) -#define SCM_MPARK_M3_PRTY_4TH (0x00000000) -#define SCM_MPARK_M3_PRTY_3RD (0x00400000) -#define SCM_MPARK_M3_PRTY_2ND (0x00800000) -#define SCM_MPARK_M3_PRTY_1ST (0x00C00000) -#define SCM_MPARK_M2_PRTY_MSK (0x00300000) -#define SCM_MPARK_M2_PRTY_4TH (0x00000000) -#define SCM_MPARK_M2_PRTY_3RD (0x00100000) -#define SCM_MPARK_M2_PRTY_2ND (0x00200000) -#define SCM_MPARK_M2_PRTY_1ST (0x00300000) -#define SCM_MPARK_M0_PRTY_MSK (0x000C0000) -#define SCM_MPARK_M0_PRTY_4TH (0x00000000) -#define SCM_MPARK_M0_PRTY_3RD (0x00040000) -#define SCM_MPARK_M0_PRTY_2ND (0x00080000) -#define SCM_MPARK_M0_PRTY_1ST (0x000C0000) -#define SCM_MPARK_FIXED (0x00004000) -#define SCM_MPARK_TIMEOUT (0x00002000) -#define SCM_MPARK_PRKLAST (0x00001000) -#define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8) - -/* Bit definitions and macros for SCM_MPR */ -#define SCM_MPR_MPR3 (0x08) -#define SCM_MPR_MPR2 (0x04) -#define SCM_MPR_MPR1 (0x02) -#define SCM_MPR_MPR0 (0x01) - -/* Bit definitions and macros for SCM_PACRn */ -#define SCM_PACRn_LOCK1 (0x80) -#define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4) -#define SCM_PACRn_LOCK0 (0x08) -#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) - -/* Bit definitions and macros for SCM_GPACR */ -#define SCM_PACRn_LOCK (0x80) -#define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) - -/********************************************************************* -* SDRAM Controller (SDRAMC) -*********************************************************************/ -/* Bit definitions and macros for SDRAMC_DCR */ -#define SDRAMC_DCR_NAM (0x2000) -#define SDRAMC_DCR_COC (0x1000) -#define SDRAMC_DCR_IS (0x0800) -#define SDRAMC_DCR_RTIM_MASK (0x0C00) -#define SDRAMC_DCR_RTIM_3CLKS (0x0000) -#define SDRAMC_DCR_RTIM_6CLKS (0x0200) -#define SDRAMC_DCR_RTIM_9CLKS (0x0400) -#define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8) - -/* Bit definitions and macros for SDRAMC_DARCn */ -#define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18) -#define SDRAMC_DARCn_RE (0x00008000) -#define SDRAMC_DARCn_CASL_MASK (0x00003000) -#define SDRAMC_DARCn_CASL_C0 (0x00000000) -#define SDRAMC_DARCn_CASL_C1 (0x00001000) -#define SDRAMC_DARCn_CASL_C2 (0x00002000) -#define SDRAMC_DARCn_CASL_C3 (0x00003000) -#define SDRAMC_DARCn_CBM_MASK (0x00000700) -#define SDRAMC_DARCn_CBM_CMD17 (0x00000000) -#define SDRAMC_DARCn_CBM_CMD18 (0x00000100) -#define SDRAMC_DARCn_CBM_CMD19 (0x00000200) -#define SDRAMC_DARCn_CBM_CMD20 (0x00000300) -#define SDRAMC_DARCn_CBM_CMD21 (0x00000400) -#define SDRAMC_DARCn_CBM_CMD22 (0x00000500) -#define SDRAMC_DARCn_CBM_CMD23 (0x00000600) -#define SDRAMC_DARCn_CBM_CMD24 (0x00000700) -#define SDRAMC_DARCn_IMRS (0x00000040) -#define SDRAMC_DARCn_PS_MASK (0x00000030) -#define SDRAMC_DARCn_PS_32 (0x00000000) -#define SDRAMC_DARCn_PS_16 (0x00000010) -#define SDRAMC_DARCn_PS_8 (0x00000020) -#define SDRAMC_DARCn_IP (0x00000008) - -/* Bit definitions and macros for SDRAMC_DMRn */ -#define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18) -#define SDRAMC_DMRn_WP (0x00000100) -#define SDRAMC_DMRn_V (0x00000001) - -/********************************************************************* -* Interrupt Controller (INTC) -*********************************************************************/ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_SCM (8) -#define INT0_LO_DMA0 (9) -#define INT0_LO_DMA1 (10) -#define INT0_LO_DMA2 (11) -#define INT0_LO_DMA3 (12) -#define INT0_LO_UART0 (13) -#define INT0_LO_UART1 (14) -#define INT0_LO_UART2 (15) -#define INT0_LO_RSVD1 (16) -#define INT0_LO_I2C (17) -#define INT0_LO_QSPI (18) -#define INT0_LO_DTMR0 (19) -#define INT0_LO_DTMR1 (20) -#define INT0_LO_DTMR2 (21) -#define INT0_LO_DTMR3 (22) -#define INT0_LO_FEC_TXF (23) -#define INT0_LO_FEC_TXB (24) -#define INT0_LO_FEC_UN (25) -#define INT0_LO_FEC_RL (26) -#define INT0_LO_FEC_RXF (27) -#define INT0_LO_FEC_RXB (28) -#define INT0_LO_FEC_MII (29) -#define INT0_LO_FEC_LC (30) -#define INT0_LO_FEC_HBERR (31) -#define INT0_HI_FEC_GRA (32) -#define INT0_HI_FEC_EBERR (33) -#define INT0_HI_FEC_BABT (34) -#define INT0_HI_FEC_BABR (35) -#define INT0_HI_PIT0 (36) -#define INT0_HI_PIT1 (37) -#define INT0_HI_PIT2 (38) -#define INT0_HI_PIT3 (39) -#define INT0_HI_RNG (40) -#define INT0_HI_SKHA (41) -#define INT0_HI_MDHA (42) -#define INT0_HI_CAN1_BUF0I (43) -#define INT0_HI_CAN1_BUF1I (44) -#define INT0_HI_CAN1_BUF2I (45) -#define INT0_HI_CAN1_BUF3I (46) -#define INT0_HI_CAN1_BUF4I (47) -#define INT0_HI_CAN1_BUF5I (48) -#define INT0_HI_CAN1_BUF6I (49) -#define INT0_HI_CAN1_BUF7I (50) -#define INT0_HI_CAN1_BUF8I (51) -#define INT0_HI_CAN1_BUF9I (52) -#define INT0_HI_CAN1_BUF10I (53) -#define INT0_HI_CAN1_BUF11I (54) -#define INT0_HI_CAN1_BUF12I (55) -#define INT0_HI_CAN1_BUF13I (56) -#define INT0_HI_CAN1_BUF14I (57) -#define INT0_HI_CAN1_BUF15I (58) -#define INT0_HI_CAN1_ERRINT (59) -#define INT0_HI_CAN1_BOFFINT (60) -/* 60-63 Reserved */ - -/* 0 - 7 Reserved */ -#define INT1_LO_CAN1_BUF0I (8) -#define INT1_LO_CAN1_BUF1I (9) -#define INT1_LO_CAN1_BUF2I (10) -#define INT1_LO_CAN1_BUF3I (11) -#define INT1_LO_CAN1_BUF4I (12) -#define INT1_LO_CAN1_BUF5I (13) -#define INT1_LO_CAN1_BUF6I (14) -#define INT1_LO_CAN1_BUF7I (15) -#define INT1_LO_CAN1_BUF8I (16) -#define INT1_LO_CAN1_BUF9I (17) -#define INT1_LO_CAN1_BUF10I (18) -#define INT1_LO_CAN1_BUF11I (19) -#define INT1_LO_CAN1_BUF12I (20) -#define INT1_LO_CAN1_BUF13I (21) -#define INT1_LO_CAN1_BUF14I (22) -#define INT1_LO_CAN1_BUF15I (23) -#define INT1_LO_CAN1_ERRINT (24) -#define INT1_LO_CAN1_BOFFINT (25) -/* 26 Reserved */ -#define INT1_LO_ETPU_TC0F (27) -#define INT1_LO_ETPU_TC1F (28) -#define INT1_LO_ETPU_TC2F (29) -#define INT1_LO_ETPU_TC3F (30) -#define INT1_LO_ETPU_TC4F (31) -#define INT1_HI_ETPU_TC5F (32) -#define INT1_HI_ETPU_TC6F (33) -#define INT1_HI_ETPU_TC7F (34) -#define INT1_HI_ETPU_TC8F (35) -#define INT1_HI_ETPU_TC9F (36) -#define INT1_HI_ETPU_TC10F (37) -#define INT1_HI_ETPU_TC11F (38) -#define INT1_HI_ETPU_TC12F (39) -#define INT1_HI_ETPU_TC13F (40) -#define INT1_HI_ETPU_TC14F (41) -#define INT1_HI_ETPU_TC15F (42) -#define INT1_HI_ETPU_TC16F (43) -#define INT1_HI_ETPU_TC17F (44) -#define INT1_HI_ETPU_TC18F (45) -#define INT1_HI_ETPU_TC19F (46) -#define INT1_HI_ETPU_TC20F (47) -#define INT1_HI_ETPU_TC21F (48) -#define INT1_HI_ETPU_TC22F (49) -#define INT1_HI_ETPU_TC23F (50) -#define INT1_HI_ETPU_TC24F (51) -#define INT1_HI_ETPU_TC25F (52) -#define INT1_HI_ETPU_TC26F (53) -#define INT1_HI_ETPU_TC27F (54) -#define INT1_HI_ETPU_TC28F (55) -#define INT1_HI_ETPU_TC29F (56) -#define INT1_HI_ETPU_TC30F (57) -#define INT1_HI_ETPU_TC31F (58) -#define INT1_HI_ETPU_TGIF (59) - -/********************************************************************* -* General Purpose I/O (GPIO) -*********************************************************************/ -/* Bit definitions and macros for GPIO_PODR */ -#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5) -#define GPIO_PODR_ADDR_MASK (0xE0) -#define GPIO_PODR_BS(x) ((x)&0x0F) -#define GPIO_PODR_BS_MASK (0x0F) -#define GPIO_PODR_CS(x) (((x)&0x7F)<<1) -#define GPIO_PODR_CS_MASK (0xFE) -#define GPIO_PODR_SDRAM(X) ((x)&0x3F) -#define GPIO_PODR_SDRAM_MASK (0x3F) -#define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x) -#define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK -#define GPIO_PODR_UARTH(x) ((x)&0x03) -#define GPIO_PODR_UARTH_MASK (0x03) -#define GPIO_PODR_QSPI(x) ((x)&0x1F) -#define GPIO_PODR_QSPI_MASK (0x1F) -#define GPIO_PODR_ETPU(x) ((x)&0x07) -#define GPIO_PODR_ETPU_MASK (0x07) - -/* Bit definitions and macros for GPIO_PDDR */ -#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x) -#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK -#define GPIO_PDDR_BS(x) GPIO_PODR_BS(x) -#define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK -#define GPIO_PDDR_CS(x) GPIO_PODR_CS(x) -#define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK -#define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X) -#define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK -#define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x) -#define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK -#define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x) -#define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK -#define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x) -#define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK -#define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x) -#define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK - -/* Bit definitions and macros for GPIO_PPDSDR */ -#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x) -#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK -#define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x) -#define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK -#define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x) -#define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK -#define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X) -#define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK -#define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x) -#define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK -#define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x) -#define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK -#define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x) -#define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK -#define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x) -#define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK - -/* Bit definitions and macros for GPIO_PCLRR */ -#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x) -#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK -#define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x) -#define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK -#define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x) -#define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK -#define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X) -#define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK -#define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x) -#define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK -#define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x) -#define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK -#define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x) -#define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK -#define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x) -#define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK - -/* Bit definitions and macros for GPIO_PAR */ -#define GPIO_PAR_AD_ADDR23 (0x80) -#define GPIO_PAR_AD_ADDR22 (0x40) -#define GPIO_PAR_AD_ADDR21 (0x20) -#define GPIO_PAR_AD_DATAL (0x01) -#define GPIO_PAR_BUSCTL_OE (0x4000) -#define GPIO_PAR_BUSCTL_TA (0x1000) -#define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10) -#define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00) -#define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400) -#define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800) -#define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00) -#define GPIO_PAR_BUSCTL_RWB (0x0100) -#define GPIO_PAR_BUSCTL_TSIZ1 (0x0040) -#define GPIO_PAR_BUSCTL_TSIZ0 (0x0010) -#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2) -#define GPIO_PAR_BUSCTL_TS_MASK (0x0C) -#define GPIO_PAR_BUSCTL_TS_GPIO (0x04) -#define GPIO_PAR_BUSCTL_TS_DACK2 (0x08) -#define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C) -#define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03) -#define GPIO_PAR_BUSCTL_TIP_MASK (0x03) -#define GPIO_PAR_BUSCTL_TIP_GPIO (0x01) -#define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02) -#define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03) -#define GPIO_PAR_BS(x) ((x)&0x0F) -#define GPIO_PAR_BS_MASK (0x0F) -#define GPIO_PAR_CS(x) (((x)&0x7F)<<1) -#define GPIO_PAR_CS_MASK (0xFE) -#define GPIO_PAR_CS_CS7 (0x80) -#define GPIO_PAR_CS_CS6 (0x40) -#define GPIO_PAR_CS_CS5 (0x20) -#define GPIO_PAR_CS_CS4 (0x10) -#define GPIO_PAR_CS_CS3 (0x08) -#define GPIO_PAR_CS_CS2 (0x04) -#define GPIO_PAR_CS_CS1 (0x02) -#define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3 -#define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2 -#define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6) -#define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0) -#define GPIO_PAR_SDRAM_SDWE (0x20) -#define GPIO_PAR_SDRAM_SCAS (0x10) -#define GPIO_PAR_SDRAM_SRAS (0x08) -#define GPIO_PAR_SDRAM_SCKE (0x04) -#define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03) -#define GPIO_PAR_SDRAM_SDCS_MASK (0x03) -#define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6) -#define GPIO_PAR_FECI2C_EMDC_MASK (0xC0) -#define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40) -#define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80) -#define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0) -#define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4) -#define GPIO_PAR_FECI2C_EMDIO_MASK (0x30) -#define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10) -#define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20) -#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30) -#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) -#define GPIO_PAR_FECI2C_SCL_MASK (0x0C) -#define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08) -#define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C) -#define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03) -#define GPIO_PAR_FECI2C_SDA_MASK (0x03) -#define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02) -#define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03) -#define GPIO_PAR_UART_DREQ2 (0x8000) -#define GPIO_PAR_UART_CAN1EN (0x4000) -#define GPIO_PAR_UART_U2RXD (0x2000) -#define GPIO_PAR_UART_U2TXD (0x1000) -#define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10) -#define GPIO_PAR_UART_U1RXD_MASK (0x0C00) -#define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800) -#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) -#define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8) -#define GPIO_PAR_UART_U1TXD_MASK (0x0300) -#define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200) -#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) -#define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6) -#define GPIO_PAR_UART_U1CTS_MASK (0x00C0) -#define GPIO_PAR_UART_U1CTS_U2CTS (0x0080) -#define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0) -#define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4) -#define GPIO_PAR_UART_U1RTS_MASK (0x0030) -#define GPIO_PAR_UART_U1RTS_U2RTS (0x0020) -#define GPIO_PAR_UART_U1RTS_U1RTS (0x0030) -#define GPIO_PAR_UART_U0RXD (0x0008) -#define GPIO_PAR_UART_U0TXD (0x0004) -#define GPIO_PAR_UART_U0CTS (0x0002) -#define GPIO_PAR_UART_U0RTS (0x0001) -#define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6) -#define GPIO_PAR_QSPI_CS1_MASK (0xC0) -#define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80) -#define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0) -#define GPIO_PAR_QSPI_CS0 (0x20) -#define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3) -#define GPIO_PAR_QSPI_DIN_MASK (0x18) -#define GPIO_PAR_QSPI_DIN_I2CSDA (0x10) -#define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18) -#define GPIO_PAR_QSPI_DOUT (0x04) -#define GPIO_PAR_QSPI_SCK(x) ((x)&0x03) -#define GPIO_PAR_QSPI_SCK_MASK (0x03) -#define GPIO_PAR_QSPI_SCK_I2CSCL (0x02) -#define GPIO_PAR_QSPI_SCK_QSPISCK (0x03) -#define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14) -#define GPIO_PAR_DT3IN_MASK (0xC000) -#define GPIO_PAR_DT3IN_QSPICS2 (0x4000) -#define GPIO_PAR_DT3IN_U2CTS (0x8000) -#define GPIO_PAR_DT3IN_DT3IN (0xC000) -#define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12) -#define GPIO_PAR_DT2IN_MASK (0x3000) -#define GPIO_PAR_DT2IN_DT2OUT (0x1000) -#define GPIO_PAR_DT2IN_DREQ2 (0x2000) -#define GPIO_PAR_DT2IN_DT2IN (0x3000) -#define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10) -#define GPIO_PAR_DT1IN_MASK (0x0C00) -#define GPIO_PAR_DT1IN_DT1OUT (0x0400) -#define GPIO_PAR_DT1IN_DREQ1 (0x0800) -#define GPIO_PAR_DT1IN_DT1IN (0x0C00) -#define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8) -#define GPIO_PAR_DT0IN_MASK (0x0300) -#define GPIO_PAR_DT0IN_DREQ0 (0x0200) -#define GPIO_PAR_DT0IN_DT0IN (0x0300) -#define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6) -#define GPIO_PAR_DT3OUT_MASK (0x00C0) -#define GPIO_PAR_DT3OUT_QSPICS3 (0x0040) -#define GPIO_PAR_DT3OUT_U2RTS (0x0080) -#define GPIO_PAR_DT3OUT_DT3OUT (0x00C0) -#define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4) -#define GPIO_PAR_DT2OUT_MASK (0x0030) -#define GPIO_PAR_DT2OUT_DACK2 (0x0020) -#define GPIO_PAR_DT2OUT_DT2OUT (0x0030) -#define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2) -#define GPIO_PAR_DT1OUT_MASK (0x000C) -#define GPIO_PAR_DT1OUT_DACK1 (0x0008) -#define GPIO_PAR_DT1OUT_DT1OUT (0x000C) -#define GPIO_PAR_DT0OUT(x) ((x)&0x03) -#define GPIO_PAR_DT0OUT_MASK (0x0003) -#define GPIO_PAR_DT0OUT_DACK0 (0x0002) -#define GPIO_PAR_DT0OUT_DT0OUT (0x0003) -#define GPIO_PAR_ETPU_TCRCLK (0x04) -#define GPIO_PAR_ETPU_UTPU_ODIS (0x02) -#define GPIO_PAR_ETPU_LTPU_ODIS (0x01) - -/* Bit definitions and macros for GPIO_DSCR */ -#define GPIO_DSCR_EIM_EIM1 (0x10) -#define GPIO_DSCR_EIM_EIM0 (0x01) -#define GPIO_DSCR_ETPU_ETPU31_24 (0x40) -#define GPIO_DSCR_ETPU_ETPU23_16 (0x10) -#define GPIO_DSCR_ETPU_ETPU15_8 (0x04) -#define GPIO_DSCR_ETPU_ETPU7_0 (0x01) -#define GPIO_DSCR_FECI2C_FEC (0x10) -#define GPIO_DSCR_FECI2C_I2C (0x01) -#define GPIO_DSCR_UART_IRQ (0x40) -#define GPIO_DSCR_UART_UART2 (0x10) -#define GPIO_DSCR_UART_UART1 (0x04) -#define GPIO_DSCR_UART_UART0 (0x01) -#define GPIO_DSCR_QSPI_QSPI (0x01) -#define GPIO_DSCR_TIMER (0x01) - -/********************************************************************* -* Chip Configuration Module (CCM) -*********************************************************************/ -/* Bit definitions and macros for CCM_RCR */ -#define CCM_RCR_SOFTRST (0x80) -#define CCM_RCR_FRCRSTOUT (0x40) - -/* Bit definitions and macros for CCM_RSR */ -#define CCM_RSR_SOFT (0x20) -#define CCM_RSR_WDR (0x10) -#define CCM_RSR_POR (0x08) -#define CCM_RSR_EXT (0x04) -#define CCM_RSR_LOC (0x02) -#define CCM_RSR_LOL (0x01) - -/* Bit definitions and macros for CCM_CCR */ -#define CCM_CCR_LOAD (0x8000) -#define CCM_CCR_SZEN (0x0040) -#define CCM_CCR_PSTEN (0x0020) -#define CCM_CCR_BME (0x0008) -#define CCM_CCR_BMT(x) ((x)&0x07) -#define CCM_CCR_BMT_MASK (0x0007) -#define CCM_CCR_BMT_64K (0x0000) -#define CCM_CCR_BMT_32K (0x0001) -#define CCM_CCR_BMT_16K (0x0002) -#define CCM_CCR_BMT_8K (0x0003) -#define CCM_CCR_BMT_4K (0x0004) -#define CCM_CCR_BMT_2K (0x0005) -#define CCM_CCR_BMT_1K (0x0006) -#define CCM_CCR_BMT_512 (0x0007) - -/* Bit definitions and macros for CCM_RCON */ -#define CCM_RCON_RCSC(x) (((x)&0x0003)<<8) -#define CCM_RCON_RLOAD (0x0020) -#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) -#define CCM_RCON_BOOTPS_MASK (0x0018) -#define CCM_RCON_BOOTPS_32 (0x0018) -#define CCM_RCON_BOOTPS_16 (0x0008) -#define CCM_RCON_BOOTPS_8 (0x0010) -#define CCM_RCON_MODE (0x0001) - -/* Bit definitions and macros for CCM_CIR */ -#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6) -#define CCM_CIR_PRN(x) ((x) & 0x003F) - -/********************************************************************* -* PLL Clock Module -*********************************************************************/ -/* Bit definitions and macros for PLL_SYNCR */ -#define PLL_SYNCR_MFD(x) (((x)&0x07)<<24) -#define PLL_SYNCR_MFD_MASK (0x07000000) -#define PLL_SYNCR_RFC(x) (((x)&0x07)<<19) -#define PLL_SYNCR_RFC_MASK (0x00380000) -#define PLL_SYNCR_LOCEN (0x00040000) -#define PLL_SYNCR_LOLRE (0x00020000) -#define PLL_SYNCR_LOCRE (0x00010000) -#define PLL_SYNCR_DISCLK (0x00008000) -#define PLL_SYNCR_LOLIRQ (0x00004000) -#define PLL_SYNCR_LOCIRQ (0x00002000) -#define PLL_SYNCR_RATE (0x00001000) -#define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10) -#define PLL_SYNCR_EXP(x) ((x)&0x03FF) - -/* Bit definitions and macros for PLL_SYNSR */ -#define PLL_SYNSR_LOLF (0x00000200) -#define PLL_SYNSR_LOC (0x00000100) -#define PLL_SYNSR_MODE (0x00000080) -#define PLL_SYNSR_PLLSEL (0x00000040) -#define PLL_SYNSR_PLLREF (0x00000020) -#define PLL_SYNSR_LOCKS (0x00000010) -#define PLL_SYNSR_LOCK (0x00000008) -#define PLL_SYNSR_LOCF (0x00000004) -#define PLL_SYNSR_CALDONE (0x00000002) -#define PLL_SYNSR_CALPASS (0x00000001) - -/********************************************************************* -* Watchdog Timer Modules (WTM) -*********************************************************************/ -/* Bit definitions and macros for WTM_WCR */ -#define WTM_WCR_WAIT (0x0008) -#define WTM_WCR_DOZE (0x0004) -#define WTM_WCR_HALTED (0x0002) -#define WTM_WCR_EN (0x0001) - -#endif /* mcf5235_h */ diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h deleted file mode 100644 index fa0cb14..0000000 --- a/include/asm-m68k/m5249.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * mcf5249.h -- Definitions for Motorola Coldfire 5249 - * - * Based on mcf5272sim.h of uCLinux distribution: - * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef mcf5249_h -#define mcf5249_h -/****************************************************************************/ - -/* - * useful definitions for reading/writing MBAR offset memory - */ -#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y -#define mbar2_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) -#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y -#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y -#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y - -/* - * Size of internal RAM - */ - -#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */ -#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */ - -/* - * Define the 5249 SIM register set addresses. - */ - -/***************** - ***** MBAR1 ***** - *****************/ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ -#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ - -#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ -#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ -#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ -#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ -#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ -#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ -#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ -#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ -#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ -#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ - -#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ -#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ - -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ - -/***************** - ***** MBAR2 ***** - *****************/ - -/* GPIO Addresses - * Note: These are offset from MBAR2! - */ -#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */ -#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */ -#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */ -#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */ -#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */ -#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */ -#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */ -#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */ - -#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */ -#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */ -#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */ - -#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */ -#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */ -#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */ - -#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */ -#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */ -#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */ -#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */ -#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */ -#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */ -#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */ -#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */ - -#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */ -#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */ - -#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */ -#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */ - -#define MCFSIM_PLLCR 0x180 /* PLL Control register */ - -/* - * Some symbol defines for the above... - */ -#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ -#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ -#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ -#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ -#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ -#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ -/* XXX - If needed, DMA ICRs go here */ -#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */ - -/* - * Bit definitions for the ICR family of registers. - */ -#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ -#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ -#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ -#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ -#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ -#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ -#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ -#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ -#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ - -#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ -#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ -#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ -#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ - -/* - * Macros to read/set IMR register. It is 32 bits on the 5249. - */ - -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#endif /* mcf5249_h */ diff --git a/include/asm-m68k/m5253.h b/include/asm-m68k/m5253.h deleted file mode 100644 index eda3472..0000000 --- a/include/asm-m68k/m5253.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef m5253_h -#define m5253_h -/****************************************************************************/ - -/* -* PLL Module (PLL) -*/ - -/* Register read/write macros */ -#define PLL_PLLCR (0x000180) - -#define SIM_RSR (0x000000) -#define SIM_SYPCR (0x000001) -#define SIM_SWIVR (0x000002) -#define SIM_SWSR (0x000003) -#define SIM_MPARK (0x00000C) - -/* Bit definitions and macros for RSR */ -#define SIM_RSR_SWTR (0x20) -#define SIM_RSR_HRST (0x80) - -/* Register read/write macros */ -#define CIM_MISCCR (0x000500) -#define CIM_ATA_DADDR (0x000504) -#define CIM_ATA_DCOUNT (0x000508) -#define CIM_RTC_TIME (0x00050C) -#define CIM_USB_CANCLK (0x000510) - -/* Bit definitions and macros for MISCCR */ -#define CIM_MISCCR_ADTA (0x00000001) -#define CIM_MISCCR_ADTD (0x00000002) -#define CIM_MISCCR_ADIE (0x00000004) -#define CIM_MISCCR_ADIC (0x00000008) -#define CIM_MISCCR_ADIP (0x00000010) -#define CIM_MISCCR_CPUEND (0x00000020) -#define CIM_MISCCR_DMAEND (0x00000040) -#define CIM_MISCCR_RTCCLR (0x00000080) -#define CIM_MISCCR_RTCPL (0x00000100) -#define CIM_MISCCR_URIE (0x00000800) -#define CIM_MISCCR_URIC (0x00001000) -#define CIM_MISCCR_URIP (0x00002000) - -/* Bit definitions and macros for ATA_DADDR */ -#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2) -#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for ATA_DCOUNT */ -#define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF)) - -#endif /* m5253_h */ diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h deleted file mode 100644 index d25261b..0000000 --- a/include/asm-m68k/m5271.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * mcf5271.h -- Definitions for Motorola Coldfire 5271 - * - * (C) Copyright 2006, Lab X Technologies - * Based on mcf5272sim.h of uCLinux distribution: - * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _MCF5271_H_ -#define _MCF5271_H_ - -#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) -#define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) -#define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y - -#define MCF_FMPLL_SYNCR 0x120000 -#define MCF_FMPLL_SYNSR 0x120004 - -#define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24) -#define MCF_SYNCR_MFD_4X 0x00000000 -#define MCF_SYNCR_MFD_6X 0x01000000 -#define MCF_SYNCR_MFD_8X 0x02000000 -#define MCF_SYNCR_MFD_10X 0x03000000 -#define MCF_SYNCR_MFD_12X 0x04000000 -#define MCF_SYNCR_MFD_14X 0x05000000 -#define MCF_SYNCR_MFD_16X 0x06000000 -#define MCF_SYNCR_MFD_18X 0x07000000 - -#define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19) -#define MCF_SYNCR_RFD_DIV1 0x00000000 -#define MCF_SYNCR_RFD_DIV2 0x00080000 -#define MCF_SYNCR_RFD_DIV4 0x00100000 -#define MCF_SYNCR_RFD_DIV8 0x00180000 -#define MCF_SYNCR_RFD_DIV16 0x00200000 -#define MCF_SYNCR_RFD_DIV32 0x00280000 -#define MCF_SYNCR_RFD_DIV64 0x00300000 -#define MCF_SYNCR_RFD_DIV128 0x00380000 - -#define MCF_FMPLL_SYNSR_LOCK 0x8 - -#define MCF_WTM_WCR 0x140000 -#define MCF_WTM_WCNTR 0x140004 -#define MCF_WTM_WSR 0x140006 -#define MCF_WTM_WCR_EN 0x0001 - -#define MCF_RCM_RCR 0x110000 -#define MCF_RCM_RCR_FRCRSTOUT 0x40 -#define MCF_RCM_RCR_SOFTRST 0x80 - -#define MCF_GPIO_PODR_ADDR 0x100000 -#define MCF_GPIO_PODR_DATAH 0x100001 -#define MCF_GPIO_PODR_DATAL 0x100002 -#define MCF_GPIO_PODR_BUSCTL 0x100003 -#define MCF_GPIO_PODR_BS 0x100004 -#define MCF_GPIO_PODR_CS 0x100005 -#define MCF_GPIO_PODR_SDRAM 0x100006 -#define MCF_GPIO_PODR_FECI2C 0x100007 -#define MCF_GPIO_PODR_UARTH 0x100008 -#define MCF_GPIO_PODR_UARTL 0x100009 -#define MCF_GPIO_PODR_QSPI 0x10000A -#define MCF_GPIO_PODR_TIMER 0x10000B - -#define MCF_GPIO_PDDR_ADDR 0x100010 -#define MCF_GPIO_PDDR_DATAH 0x100011 -#define MCF_GPIO_PDDR_DATAL 0x100012 -#define MCF_GPIO_PDDR_BUSCTL 0x100013 -#define MCF_GPIO_PDDR_BS 0x100014 -#define MCF_GPIO_PDDR_CS 0x100015 -#define MCF_GPIO_PDDR_SDRAM 0x100016 -#define MCF_GPIO_PDDR_FECI2C 0x100017 -#define MCF_GPIO_PDDR_UARTH 0x100018 -#define MCF_GPIO_PDDR_UARTL 0x100019 -#define MCF_GPIO_PDDR_QSPI 0x10001A -#define MCF_GPIO_PDDR_TIMER 0x10001B - -#define MCF_GPIO_PPDSDR_ADDR 0x100020 -#define MCF_GPIO_PPDSDR_DATAH 0x100021 -#define MCF_GPIO_PPDSDR_DATAL 0x100022 -#define MCF_GPIO_PPDSDR_BUSCTL 0x100023 -#define MCF_GPIO_PPDSDR_BS 0x100024 -#define MCF_GPIO_PPDSDR_CS 0x100025 -#define MCF_GPIO_PPDSDR_SDRAM 0x100026 -#define MCF_GPIO_PPDSDR_FECI2C 0x100027 -#define MCF_GPIO_PPDSDR_UARTH 0x100028 -#define MCF_GPIO_PPDSDR_UARTL 0x100029 -#define MCF_GPIO_PPDSDR_QSPI 0x10002A -#define MCF_GPIO_PPDSDR_TIMER 0x10002B - -#define MCF_GPIO_PCLRR_ADDR 0x100030 -#define MCF_GPIO_PCLRR_DATAH 0x100031 -#define MCF_GPIO_PCLRR_DATAL 0x100032 -#define MCF_GPIO_PCLRR_BUSCTL 0x100033 -#define MCF_GPIO_PCLRR_BS 0x100034 -#define MCF_GPIO_PCLRR_CS 0x100035 -#define MCF_GPIO_PCLRR_SDRAM 0x100036 -#define MCF_GPIO_PCLRR_FECI2C 0x100037 -#define MCF_GPIO_PCLRR_UARTH 0x100038 -#define MCF_GPIO_PCLRR_UARTL 0x100039 -#define MCF_GPIO_PCLRR_QSPI 0x10003A -#define MCF_GPIO_PCLRR_TIMER 0x10003B - -#define MCF_GPIO_PAR_AD 0x100040 -#define MCF_GPIO_PAR_BUSCTL 0x100042 -#define MCF_GPIO_PAR_BS 0x100044 -#define MCF_GPIO_PAR_CS 0x100045 -#define MCF_GPIO_PAR_SDRAM 0x100046 -#define MCF_GPIO_PAR_FECI2C 0x100047 -#define MCF_GPIO_PAR_UART 0x100048 -#define MCF_GPIO_PAR_QSPI 0x10004A -#define MCF_GPIO_PAR_TIMER 0x10004C - -#define MCF_DSCR_EIM 0x100050 -#define MCF_DCSR_FEC12C 0x100052 -#define MCF_DCSR_UART 0x100053 -#define MCF_DCSR_QSPI 0x100054 -#define MCF_DCSR_TIMER 0x100055 - -#define MCF_CCM_CIR 0x11000A -#define MCF_CCM_CIR_PRN_MASK 0x3F -#define MCF_CCM_CIR_PIN_LEN 6 -#define MCF_CCM_CIR_PIN_MCF5270 0x002e -#define MCF_CCM_CIR_PIN_MCF5271 0x0032 - -#define MCF_GPIO_AD_ADDR23 0x80 -#define MCF_GPIO_AD_ADDR22 0x40 -#define MCF_GPIO_AD_ADDR21 0x20 -#define MCF_GPIO_AD_DATAL 0x01 -#define MCF_GPIO_AD_MASK 0xe1 - -#define MCF_GPIO_PAR_CS_PAR_CS2 0x04 - -#define MCF_GPIO_SDRAM_CSSDCS_00 0x00 /* CS[3:2] pins: CS3, CS2 */ -#define MCF_GPIO_SDRAM_CSSDCS_01 0x40 /* CS[3:2] pins: CS3, SD_CS0 */ -#define MCF_GPIO_SDRAM_CSSDCS_10 0x80 /* CS[3:2] pins: SD_CS1, SC2 */ -#define MCF_GPIO_SDRAM_CSSDCS_11 0xc0 /* CS[3:2] pins: SD_CS1, SD_CS0 */ -#define MCF_GPIO_SDRAM_SDWE 0x20 /* WE pin */ -#define MCF_GPIO_SDRAM_SCAS 0x10 /* CAS pin */ -#define MCF_GPIO_SDRAM_SRAS 0x08 /* RAS pin */ -#define MCF_GPIO_SDRAM_SCKE 0x04 /* CKE pin */ -#define MCF_GPIO_SDRAM_SDCS_00 0x00 /* SD_CS[0:1] pins: GPIO, GPIO */ -#define MCF_GPIO_SDRAM_SDCS_01 0x01 /* SD_CS[0:1] pins: GPIO, SD_CS0 */ -#define MCF_GPIO_SDRAM_SDCS_10 0x02 /* SD_CS[0:1] pins: SD_CS1, GPIO */ -#define MCF_GPIO_SDRAM_SDCS_11 0x03 /* SD_CS[0:1] pins: SD_CS1, SD_CS0 */ - -#define MCF_GPIO_PAR_UART_U0RTS 0x0001 -#define MCF_GPIO_PAR_UART_U0CTS 0x0002 -#define MCF_GPIO_PAR_UART_U0TXD 0x0004 -#define MCF_GPIO_PAR_UART_U0RXD 0x0008 -#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00 -#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300 - -#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) - -#define MCF_SDRAMC_DCR 0x000040 -#define MCF_SDRAMC_DACR0 0x000048 -#define MCF_SDRAMC_DMR0 0x00004C - -#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) -#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) -#define MCF_SDRAMC_DCR_IS 0x0800 -#define MCF_SDRAMC_DCR_COC 0x1000 -#define MCF_SDRAMC_DCR_NAM 0x2000 - -#define MCF_SDRAMC_DACRn_IP 0x00000008 -#define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_DACRn_MRS 0x00000040 -#define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8) -#define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_DACRn_RE 0x00008000 -#define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18) - -#define MCF_SDRAMC_DMRn_BAM_8M 0x007C0000 -#define MCF_SDRAMC_DMRn_BAM_16M 0x00FC0000 -#define MCF_SDRAMC_DMRn_V 0x00000001 - -#define MCFSIM_ICR1 0x000C41 - -/* Interrupt Controller (INTC) */ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_SCM (8) -#define INT0_LO_DMA0 (9) -#define INT0_LO_DMA1 (10) -#define INT0_LO_DMA2 (11) -#define INT0_LO_DMA3 (12) -#define INT0_LO_UART0 (13) -#define INT0_LO_UART1 (14) -#define INT0_LO_UART2 (15) -#define INT0_LO_RSVD1 (16) -#define INT0_LO_I2C (17) -#define INT0_LO_QSPI (18) -#define INT0_LO_DTMR0 (19) -#define INT0_LO_DTMR1 (20) -#define INT0_LO_DTMR2 (21) -#define INT0_LO_DTMR3 (22) -#define INT0_LO_FEC_TXF (23) -#define INT0_LO_FEC_TXB (24) -#define INT0_LO_FEC_UN (25) -#define INT0_LO_FEC_RL (26) -#define INT0_LO_FEC_RXF (27) -#define INT0_LO_FEC_RXB (28) -#define INT0_LO_FEC_MII (29) -#define INT0_LO_FEC_LC (30) -#define INT0_LO_FEC_HBERR (31) -#define INT0_HI_FEC_GRA (32) -#define INT0_HI_FEC_EBERR (33) -#define INT0_HI_FEC_BABT (34) -#define INT0_HI_FEC_BABR (35) -#define INT0_HI_PIT0 (36) -#define INT0_HI_PIT1 (37) -#define INT0_HI_PIT2 (38) -#define INT0_HI_PIT3 (39) -#define INT0_HI_RNG (40) -#define INT0_HI_SKHA (41) -#define INT0_HI_MDHA (42) -#define INT0_HI_CAN1_BUF0I (43) -#define INT0_HI_CAN1_BUF1I (44) -#define INT0_HI_CAN1_BUF2I (45) -#define INT0_HI_CAN1_BUF3I (46) -#define INT0_HI_CAN1_BUF4I (47) -#define INT0_HI_CAN1_BUF5I (48) -#define INT0_HI_CAN1_BUF6I (49) -#define INT0_HI_CAN1_BUF7I (50) -#define INT0_HI_CAN1_BUF8I (51) -#define INT0_HI_CAN1_BUF9I (52) -#define INT0_HI_CAN1_BUF10I (53) -#define INT0_HI_CAN1_BUF11I (54) -#define INT0_HI_CAN1_BUF12I (55) -#define INT0_HI_CAN1_BUF13I (56) -#define INT0_HI_CAN1_BUF14I (57) -#define INT0_HI_CAN1_BUF15I (58) -#define INT0_HI_CAN1_ERRINT (59) -#define INT0_HI_CAN1_BOFFINT (60) -/* 60-63 Reserved */ - -#endif /* _MCF5271_H_ */ diff --git a/include/asm-m68k/m5272.h b/include/asm-m68k/m5272.h deleted file mode 100644 index 895f89d..0000000 --- a/include/asm-m68k/m5272.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * mcf5272.h -- Definitions for Motorola Coldfire 5272 - * - * Based on mcf5272sim.h of uCLinux distribution: - * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef mcf5272_h -#define mcf5272_h -/****************************************************************************/ - -/* - * Size of internal RAM - */ - -#define INT_RAM_SIZE 4096 - -#define GPIO_PACNT_PA15MSK (0xC0000000) -#define GPIO_PACNT_DGNT1 (0x40000000) -#define GPIO_PACNT_PA14MSK (0x30000000) -#define GPIO_PACNT_DREQ1 (0x10000000) -#define GPIO_PACNT_PA13MSK (0x0C000000) -#define GPIO_PACNT_DFSC3 (0x04000000) -#define GPIO_PACNT_PA12MSK (0x03000000) -#define GPIO_PACNT_DFSC2 (0x01000000) -#define GPIO_PACNT_PA11MSK (0x00C00000) -#define GPIO_PACNT_QSPI_CS1 (0x00800000) -#define GPIO_PACNT_PA10MSK (0x00300000) -#define GPIO_PACNT_DREQ0 (0x00100000) -#define GPIO_PACNT_PA9MSK (0x000C0000) -#define GPIO_PACNT_DGNT0 (0x00040000) -#define GPIO_PACNT_PA8MSK (0x00030000) -#define GPIO_PACNT_FSC0 (0x00010000) -#define GPIO_PACNT_FSR0 (0x00010000) -#define GPIO_PACNT_PA7MSK (0x0000C000) -#define GPIO_PACNT_DOUT3 (0x00008000) -#define GPIO_PACNT_QSPI_CS3 (0x00004000) -#define GPIO_PACNT_PA6MSK (0x00003000) -#define GPIO_PACNT_USB_RXD (0x00001000) -#define GPIO_PACNT_PA5MSK (0x00000C00) -#define GPIO_PACNT_USB_TXEN (0x00000400) -#define GPIO_PACNT_PA4MSK (0x00000300) -#define GPIO_PACNT_USB_SUSP (0x00000100) -#define GPIO_PACNT_PA3MSK (0x000000C0) -#define GPIO_PACNT_USB_TN (0x00000040) -#define GPIO_PACNT_PA2MSK (0x00000030) -#define GPIO_PACNT_USB_RN (0x00000010) -#define GPIO_PACNT_PA1MSK (0x0000000C) -#define GPIO_PACNT_USB_RP (0x00000004) -#define GPIO_PACNT_PA0MSK (0x00000003) -#define GPIO_PACNT_USB_TP (0x00000001) - -#define GPIO_PBCNT_PB15MSK (0xC0000000) -#define GPIO_PBCNT_E_MDC (0x40000000) -#define GPIO_PBCNT_PB14MSK (0x30000000) -#define GPIO_PBCNT_E_RXER (0x10000000) -#define GPIO_PBCNT_PB13MSK (0x0C000000) -#define GPIO_PBCNT_E_RXD1 (0x04000000) -#define GPIO_PBCNT_PB12MSK (0x03000000) -#define GPIO_PBCNT_E_RXD2 (0x01000000) -#define GPIO_PBCNT_PB11MSK (0x00C00000) -#define GPIO_PBCNT_E_RXD3 (0x00400000) -#define GPIO_PBCNT_PB10MSK (0x00300000) -#define GPIO_PBCNT_E_TXD1 (0x00100000) -#define GPIO_PBCNT_PB9MSK (0x000C0000) -#define GPIO_PBCNT_E_TXD2 (0x00040000) -#define GPIO_PBCNT_PB8MSK (0x00030000) -#define GPIO_PBCNT_E_TXD3 (0x00010000) -#define GPIO_PBCNT_PB7MSK (0x0000C000) -#define GPIO_PBCNT_TOUT0 (0x00004000) -#define GPIO_PBCNT_PB6MSK (0x00003000) -#define GPIO_PBCNT_TA (0x00001000) -#define GPIO_PBCNT_PB4MSK (0x00000300) -#define GPIO_PBCNT_URT0_CLK (0x00000100) -#define GPIO_PBCNT_PB3MSK (0x000000C0) -#define GPIO_PBCNT_URT0_RTS (0x00000040) -#define GPIO_PBCNT_PB2MSK (0x00000030) -#define GPIO_PBCNT_URT0_CTS (0x00000010) -#define GPIO_PBCNT_PB1MSK (0x0000000C) -#define GPIO_PBCNT_URT0_RXD (0x00000004) -#define GPIO_PBCNT_URT0_TIN2 (0x00000004) -#define GPIO_PBCNT_PB0MSK (0x00000003) -#define GPIO_PBCNT_URT0_TXD (0x00000001) - -#define GPIO_PDCNT_PD7MSK (0x0000C000) -#define GPIO_PDCNT_TIN1 (0x00008000) -#define GPIO_PDCNT_PWM_OUT2 (0x00004000) -#define GPIO_PDCNT_PD6MSK (0x00003000) -#define GPIO_PDCNT_TOUT1 (0x00002000) -#define GPIO_PDCNT_PWM_OUT1 (0x00001000) -#define GPIO_PDCNT_PD5MSK (0x00000C00) -#define GPIO_PDCNT_INT4 (0x00000C00) -#define GPIO_PDCNT_DIN3 (0x00000800) -#define GPIO_PDCNT_PD4MSK (0x00000300) -#define GPIO_PDCNT_URT1_TXD (0x00000200) -#define GPIO_PDCNT_DOUT0 (0x00000100) -#define GPIO_PDCNT_PD3MSK (0x000000C0) -#define GPIO_PDCNT_INT5 (0x000000C0) -#define GPIO_PDCNT_URT1_RTS (0x00000080) -#define GPIO_PDCNT_PD2MSK (0x00000030) -#define GPIO_PDCNT_QSPI_CS2 (0x00000030) -#define GPIO_PDCNT_URT1_CTS (0x00000020) -#define GPIO_PDCNT_PD1MSK (0x0000000C) -#define GPIO_PDCNT_URT1_RXD (0x00000008) -#define GPIO_PDCNT_URT1_TIN3 (0x00000008) -#define GPIO_PDCNT_DIN0 (0x00000004) -#define GPIO_PDCNT_PD0MSK (0x00000003) -#define GPIO_PDCNT_URT1_CLK (0x00000002) -#define GPIO_PDCNT_DCL0 (0x00000001) - -#define INT_RSVD0 (0) -#define INT_INT1 (1) -#define INT_INT2 (2) -#define INT_INT3 (3) -#define INT_INT4 (4) -#define INT_TMR0 (5) -#define INT_TMR1 (6) -#define INT_TMR2 (7) -#define INT_TMR3 (8) -#define INT_UART1 (9) -#define INT_UART2 (10) -#define INT_PLIP (11) -#define INT_PLIA (12) -#define INT_USB0 (13) -#define INT_USB1 (14) -#define INT_USB2 (15) -#define INT_USB3 (16) -#define INT_USB4 (17) -#define INT_USB5 (18) -#define INT_USB6 (19) -#define INT_USB7 (20) -#define INT_DMA (21) -#define INT_ERX (22) -#define INT_ETX (23) -#define INT_ENTC (24) -#define INT_QSPI (25) -#define INT_INT5 (26) -#define INT_INT6 (27) -#define INT_SWTO (28) - -#define INT_ICR1_TMR0MASK (0x000F000) -#define INT_ICR1_TMR0PI (0x0008000) -#define INT_ICR1_TMR0IPL(x) (((x)&0x7)<<12) -#define INT_ICR1_TMR1MASK (0x0000F00) -#define INT_ICR1_TMR1PI (0x0000800) -#define INT_ICR1_TMR1IPL(x) (((x)&0x7)<<8) -#define INT_ICR1_TMR2MASK (0x00000F0) -#define INT_ICR1_TMR2PI (0x0000080) -#define INT_ICR1_TMR2IPL(x) (((x)&0x7)<<4) -#define INT_ICR1_TMR3MASK (0x000000F) -#define INT_ICR1_TMR3PI (0x0000008) -#define INT_ICR1_TMR3IPL(x) (((x)&0x7)) - -#define INT_ISR_INT31 (0x80000000) -#define INT_ISR_INT30 (0x40000000) -#define INT_ISR_INT29 (0x20000000) -#define INT_ISR_INT28 (0x10000000) -#define INT_ISR_INT27 (0x08000000) -#define INT_ISR_INT26 (0x04000000) -#define INT_ISR_INT25 (0x02000000) -#define INT_ISR_INT24 (0x01000000) -#define INT_ISR_INT23 (0x00800000) -#define INT_ISR_INT22 (0x00400000) -#define INT_ISR_INT21 (0x00200000) -#define INT_ISR_INT20 (0x00100000) -#define INT_ISR_INT19 (0x00080000) -#define INT_ISR_INT18 (0x00040000) -#define INT_ISR_INT17 (0x00020000) -#define INT_ISR_INT16 (0x00010000) -#define INT_ISR_INT15 (0x00008000) -#define INT_ISR_INT14 (0x00004000) -#define INT_ISR_INT13 (0x00002000) -#define INT_ISR_INT12 (0x00001000) -#define INT_ISR_INT11 (0x00000800) -#define INT_ISR_INT10 (0x00000400) -#define INT_ISR_INT9 (0x00000200) -#define INT_ISR_INT8 (0x00000100) -#define INT_ISR_INT7 (0x00000080) -#define INT_ISR_INT6 (0x00000040) -#define INT_ISR_INT5 (0x00000020) -#define INT_ISR_INT4 (0x00000010) -#define INT_ISR_INT3 (0x00000008) -#define INT_ISR_INT2 (0x00000004) -#define INT_ISR_INT1 (0x00000002) -#define INT_ISR_INT0 (0x00000001) - -#endif /* mcf5272_h */ diff --git a/include/asm-m68k/m5275.h b/include/asm-m68k/m5275.h deleted file mode 100644 index 24dbae2..0000000 --- a/include/asm-m68k/m5275.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * MCF5275 Internal Memory Map - * - * Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __M5275_H__ -#define __M5275_H__ - -/* - * Define the 5275 SIM register set addresses. These are similar, - * but not quite identical to the 5282 registers and offsets. - */ -#define MCF_GPIO_PAR_UART 0x10007c -#define UART0_ENABLE_MASK 0x000f -#define UART1_ENABLE_MASK 0x00f0 -#define UART2_ENABLE_MASK 0x3f00 - -#define MCF_GPIO_PAR_FECI2C 0x100082 -#define PAR_SDA_ENABLE_MASK 0x0003 -#define PAR_SCL_ENABLE_MASK 0x000c - -#define MCFSIM_WRRR 0x140000 -#define MCFSIM_SDCR 0x40 - -/********************************************************************* - * SDRAM Controller (SDRAMC) - *********************************************************************/ - -/* Register read/write macros */ -#define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040])) -#define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044])) -#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048])) -#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C])) -#define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050])) -#define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058])) -#define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054])) -#define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C])) - -/* Bit definitions and macros for MCF_SDRAMC_SDMR */ -#define MCF_SDRAMC_SDMR_CMD (0x00010000) -#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) -#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) -#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) -#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDCR */ -#define MCF_SDRAMC_SDCR_IPALL (0x00000002) -#define MCF_SDRAMC_SDCR_IREF (0x00000004) -#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) -#define MCF_SDRAMC_SDCR_DQP_BP (0x00008000) -#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) -#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) -#define MCF_SDRAMC_SDCR_REF (0x10000000) -#define MCF_SDRAMC_SDCR_CKE (0x40000000) -#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ -#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) -#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) -#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) -#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) -#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) -#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) -#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ -#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) -#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) -#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) -#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SDRAMC_SDBARn */ -#define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18) -#define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000) - -/* Bit definitions and macros for MCF_SDRAMC_SDMRn */ -#define MCF_SDRAMC_SDMRn_V (0x00000001) -#define MCF_SDRAMC_SDMRn_WP (0x00000080) -#define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18) -#define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000) -#define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000) -#define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000) -#define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000) -#define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000) -#define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000) -#define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000) -#define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000) -#define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000) -#define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000) -#define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000) -#define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000) -#define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000) -#define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000) -#define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000) -#define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000) -#define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000) -#define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000) -#define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000) - -/********************************************************************* - * Interrupt Controller (INTC) - ********************************************************************/ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_SCM (8) -#define INT0_LO_DMA0 (9) -#define INT0_LO_DMA1 (10) -#define INT0_LO_DMA2 (11) -#define INT0_LO_DMA3 (12) -#define INT0_LO_UART0 (13) -#define INT0_LO_UART1 (14) -#define INT0_LO_UART2 (15) -#define INT0_LO_RSVD1 (16) -#define INT0_LO_I2C (17) -#define INT0_LO_QSPI (18) -#define INT0_LO_DTMR0 (19) -#define INT0_LO_DTMR1 (20) -#define INT0_LO_DTMR2 (21) -#define INT0_LO_DTMR3 (22) -#define INT0_LO_FEC0_TXF (23) -#define INT0_LO_FEC0_TXB (24) -#define INT0_LO_FEC0_UN (25) -#define INT0_LO_FEC0_RL (26) -#define INT0_LO_FEC0_RXF (27) -#define INT0_LO_FEC0_RXB (28) -#define INT0_LO_FEC0_MII (29) -#define INT0_LO_FEC0_LC (30) -#define INT0_LO_FEC0_HBERR (31) -#define INT0_HI_FEC0_GRA (32) -#define INT0_HI_FEC0_EBERR (33) -#define INT0_HI_FEC0_BABT (34) -#define INT0_HI_FEC0_BABR (35) -#define INT0_HI_PIT0 (36) -#define INT0_HI_PIT1 (37) -#define INT0_HI_PIT2 (38) -#define INT0_HI_PIT3 (39) -#define INT0_HI_RNG (40) -#define INT0_HI_SKHA (41) -#define INT0_HI_MDHA (42) -#define INT0_HI_USB (43) -#define INT0_HI_USB_EP0 (44) -#define INT0_HI_USB_EP1 (45) -#define INT0_HI_USB_EP2 (46) -#define INT0_HI_USB_EP3 (47) -/* 48-63 Reserved */ - -/* 0-22 Reserved */ -#define INT1_LO_FEC1_TXF (23) -#define INT1_LO_FEC1_TXB (24) -#define INT1_LO_FEC1_UN (25) -#define INT1_LO_FEC1_RL (26) -#define INT1_LO_FEC1_RXF (27) -#define INT1_LO_FEC1_RXB (28) -#define INT1_LO_FEC1_MII (29) -#define INT1_LO_FEC1_LC (30) -#define INT1_LO_FEC1_HBERR (31) -#define INT1_HI_FEC1_GRA (32) -#define INT1_HI_FEC1_EBERR (33) -#define INT1_HI_FEC1_BABT (34) -#define INT1_HI_FEC1_BABR (35) -/* 36-63 Reserved */ - -/* Bit definitions and macros for RCR */ -#define RCM_RCR_FRCRSTOUT (0x40) -#define RCM_RCR_SOFTRST (0x80) - -#define FMPLL_SYNSR_LOCK (0x00000008) - -#endif /* __M5275_H__ */ diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h deleted file mode 100644 index d59a8b2..0000000 --- a/include/asm-m68k/m5282.h +++ /dev/null @@ -1,608 +0,0 @@ -/* - * mcf5282.h -- Definitions for Motorola Coldfire 5282 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/****************************************************************************/ -#ifndef m5282_h -#define m5282_h - -/********************************************************************* -* PLL Clock Module -*********************************************************************/ -/* Bit definitions and macros for PLL_SYNCR */ -#define PLL_SYNCR_LOLRE (0x8000) -#define PLL_SYNCR_MFD2 (0x4000) -#define PLL_SYNCR_MFD1 (0x2000) -#define PLL_SYNCR_MFD0 (0x1000) -#define PLL_SYNCR_LOCRE (0x0800) -#define PLL_SYNCR_RFC2 (0x0400) -#define PLL_SYNCR_RFC1 (0x0200) -#define PLL_SYNCR_RFC0 (0x0100) -#define PLL_SYNCR_LOCEN (0x0080) -#define PLL_SYNCR_DISCLK (0x0040) -#define PLL_SYNCR_FWKUP (0x0020) -#define PLL_SYNCR_STPMD1 (0x0008) -#define PLL_SYNCR_STPMD0 (0x0004) - -/* Bit definitions and macros for PLL_SYNSR */ -#define PLL_SYNSR_MODE (0x0080) -#define PLL_SYNSR_PLLSEL (0x0040) -#define PLL_SYNSR_PLLREF (0x0020) -#define PLL_SYNSR_LOCKS (0x0010) -#define PLL_SYNSR_LOCK (0x0008) -#define PLL_SYNSR_LOCS (0x0004) - -/********************************************************************* -* Interrupt Controller (INTC) -*********************************************************************/ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_SCM_SWT1 (8) -#define INT0_LO_DMA_00 (9) -#define INT0_LO_DMA_01 (10) -#define INT0_LO_DMA_02 (11) -#define INT0_LO_DMA_03 (12) -#define INT0_LO_UART0 (13) -#define INT0_LO_UART1 (14) -#define INT0_LO_UART2 (15) -#define INT0_LO_RSVD1 (16) -#define INT0_LO_I2C (17) -#define INT0_LO_QSPI (18) -#define INT0_LO_DTMR0 (19) -#define INT0_LO_DTMR1 (20) -#define INT0_LO_DTMR2 (21) -#define INT0_LO_DTMR3 (22) -#define INT0_LO_FEC_TXF (23) -#define INT0_LO_FEC_TXB (24) -#define INT0_LO_FEC_UN (25) -#define INT0_LO_FEC_RL (26) -#define INT0_LO_FEC_RXF (27) -#define INT0_LO_FEC_RXB (28) -#define INT0_LO_FEC_MII (29) -#define INT0_LO_FEC_LC (30) -#define INT0_LO_FEC_HBERR (31) -#define INT0_HI_FEC_GRA (32) -#define INT0_HI_FEC_EBERR (33) -#define INT0_HI_FEC_BABT (34) -#define INT0_HI_FEC_BABR (35) -#define INT0_HI_PMM_LVDF (36) -#define INT0_HI_QADC_CF1 (37) -#define INT0_HI_QADC_CF2 (38) -#define INT0_HI_QADC_PF1 (39) -#define INT0_HI_QADC_PF2 (40) -#define INT0_HI_GPTA_TOF (41) -#define INT0_HI_GPTA_PAIF (42) -#define INT0_HI_GPTA_PAOVF (43) -#define INT0_HI_GPTA_C0F (44) -#define INT0_HI_GPTA_C1F (45) -#define INT0_HI_GPTA_C2F (46) -#define INT0_HI_GPTA_C3F (47) -#define INT0_HI_GPTB_TOF (48) -#define INT0_HI_GPTB_PAIF (49) -#define INT0_HI_GPTB_PAOVF (50) -#define INT0_HI_GPTB_C0F (51) -#define INT0_HI_GPTB_C1F (52) -#define INT0_HI_GPTB_C2F (53) -#define INT0_HI_GPTB_C3F (54) -#define INT0_HI_PIT0 (55) -#define INT0_HI_PIT1 (56) -#define INT0_HI_PIT2 (57) -#define INT0_HI_PIT3 (58) -#define INT0_HI_CFM_CBEIF (59) -#define INT0_HI_CFM_CCIF (60) -#define INT0_HI_CFM_PVIF (61) -#define INT0_HI_CFM_AEIF (62) - -/* - * Size of internal RAM - */ - -#define INT_RAM_SIZE 65536 - -/* General Purpose I/O Module GPIO */ - -#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000)) -#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001)) -#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002)) -#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003)) -#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004)) -#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005)) -#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006)) -#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007)) -#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008)) -#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009)) -#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A)) -#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B)) -#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C)) -#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D)) -#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E)) -#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F)) -#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010)) -#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011)) - -#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014)) -#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015)) -#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016)) -#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017)) -#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018)) -#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019)) -#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A)) -#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B)) -#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C)) -#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D)) -#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E)) -#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F)) -#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020)) -#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021)) -#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022)) -#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023)) -#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024)) -#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025)) - -#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) -#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) -#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) -#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) -#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) -#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) -#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) -#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) -#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) -#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) -#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) -#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) -#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) -#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) -#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) -#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) -#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) -#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) - -#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) -#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) -#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) -#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) -#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) -#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) -#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) -#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) -#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) -#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) -#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) -#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) -#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) -#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) -#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) -#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) -#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) -#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) - -#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C)) -#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D)) -#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E)) -#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F)) -#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040)) -#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041)) -#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042)) -#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043)) -#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044)) -#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045)) -#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046)) -#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047)) -#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048)) -#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049)) -#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A)) -#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B)) -#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C)) -#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D)) - -#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050)) -#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051)) -#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052)) -#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054)) -#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055)) -#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056)) -#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058)) -#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059)) -#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A)) -#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B)) -#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C)) - -/* Bit level definitions and macros */ -#define MCFGPIO_PORT7 (0x80) -#define MCFGPIO_PORT6 (0x40) -#define MCFGPIO_PORT5 (0x20) -#define MCFGPIO_PORT4 (0x10) -#define MCFGPIO_PORT3 (0x08) -#define MCFGPIO_PORT2 (0x04) -#define MCFGPIO_PORT1 (0x02) -#define MCFGPIO_PORT0 (0x01) -#define MCFGPIO_PORT(x) (0x01<fds_bits[__FDELT(d)] |= __FDMASK(d)) -#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) -#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) -#define __FD_ZERO(set) \ - ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set))) - -#else /* __GNUC__ */ - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ - || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) -/* With GNU C, use inline functions instead so args are evaluated only once: */ - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - fdsetp->fds_bits[_tmp] |= (1UL<<_rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem); -} - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *p) -{ - unsigned int *tmp = (unsigned int *)p->fds_bits; - int i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 8: - tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0; - tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0; - return; - } - } - i = __FDSET_LONGS; - while (i) { - i--; - *tmp = 0; - tmp++; - } -} - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ -#endif /* __GNUC__ */ -#endif /* _M68K_POSIX_TYPES_H */ diff --git a/include/asm-m68k/processor.h b/include/asm-m68k/processor.h deleted file mode 100644 index 3fafa6f..0000000 --- a/include/asm-m68k/processor.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __ASM_M68K_PROCESSOR_H -#define __ASM_M68K_PROCESSOR_H - -#include -#include - -#define _GLOBAL(n)\ - .globl n;\ -n: - -/* Macros for setting and retrieving special purpose registers */ -#define setvbr(v) asm volatile("movec %0,%%VBR" : : "r" (v)) - -#ifndef __ASSEMBLY__ - -#endif /* ifndef ASSEMBLY*/ - -#endif /* __ASM_M68K_PROCESSOR_H */ diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h deleted file mode 100644 index 01535be..0000000 --- a/include/asm-m68k/ptrace.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _M68K_PTRACE_H -#define _M68K_PTRACE_H - -/* - * This struct defines the way the registers are stored on the - * kernel stack during an exception. - */ -#ifndef __ASSEMBLY__ - -struct pt_regs { - ulong d0; - ulong d1; - ulong d2; - ulong d3; - ulong d4; - ulong d5; - ulong d6; - ulong d7; - ulong a0; - ulong a1; - ulong a2; - ulong a3; - ulong a4; - ulong a5; - ulong a6; -#if defined(__M68K__) - unsigned format:4; /* frame format specifier */ - unsigned vector:12; /* vector offset */ - unsigned short sr; - unsigned long pc; -#else - unsigned short sr; - unsigned long pc; -#endif -}; - -#endif /* #ifndef __ASSEMBLY__ */ - -#endif /* #ifndef _M68K_PTRACE_H */ diff --git a/include/asm-m68k/rtc.h b/include/asm-m68k/rtc.h deleted file mode 100644 index 7651ca9..0000000 --- a/include/asm-m68k/rtc.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * RealTime Clock - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MCFRTC_H__ -#define __MCFRTC_H__ - -/* Real time Clock */ -typedef struct rtc_ctrl { - u32 hourmin; /* 0x00 Hours and Minutes Counter Register */ - u32 seconds; /* 0x04 Seconds Counter Register */ - u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */ - u32 alrm_sec; /* 0x0C Seconds Alarm Register */ - u32 cr; /* 0x10 Control Register */ - u32 isr; /* 0x14 Interrupt Status Register */ - u32 ier; /* 0x18 Interrupt Enable Register */ - u32 stpwatch; /* 0x1C Stopwatch Minutes Register */ - u32 days; /* 0x20 Days Counter Register */ - u32 alrm_day; /* 0x24 Days Alarm Register */ - void *extended; -} rtc_t; - -/* Bit definitions and macros for HOURMIN */ -#define RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)) -#define RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) - -/* Bit definitions and macros for SECONDS */ -#define RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)) - -/* Bit definitions and macros for ALRM_HM */ -#define RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)) -#define RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) - -/* Bit definitions and macros for ALRM_SEC */ -#define RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)) - -/* Bit definitions and macros for CR */ -#define RTC_CR_SWR (0x00000001) -#define RTC_CR_XTL(x) (((x)&0x00000003)<<5) -#define RTC_CR_EN (0x00000080) -#define RTC_CR_32768 (0x0) -#define RTC_CR_32000 (0x1) -#define RTC_CR_38400 (0x2) - -/* Bit definitions and macros for ISR */ -#define RTC_ISR_SW (0x00000001) -#define RTC_ISR_MIN (0x00000002) -#define RTC_ISR_ALM (0x00000004) -#define RTC_ISR_DAY (0x00000008) -#define RTC_ISR_1HZ (0x00000010) -#define RTC_ISR_HR (0x00000020) -#define RTC_ISR_2HZ (0x00000080) -#define RTC_ISR_SAM0 (0x00000100) -#define RTC_ISR_SAM1 (0x00000200) -#define RTC_ISR_SAM2 (0x00000400) -#define RTC_ISR_SAM3 (0x00000800) -#define RTC_ISR_SAM4 (0x00001000) -#define RTC_ISR_SAM5 (0x00002000) -#define RTC_ISR_SAM6 (0x00004000) -#define RTC_ISR_SAM7 (0x00008000) - -/* Bit definitions and macros for IER */ -#define RTC_IER_SW (0x00000001) -#define RTC_IER_MIN (0x00000002) -#define RTC_IER_ALM (0x00000004) -#define RTC_IER_DAY (0x00000008) -#define RTC_IER_1HZ (0x00000010) -#define RTC_IER_HR (0x00000020) -#define RTC_IER_2HZ (0x00000080) -#define RTC_IER_SAM0 (0x00000100) -#define RTC_IER_SAM1 (0x00000200) -#define RTC_IER_SAM2 (0x00000400) -#define RTC_IER_SAM3 (0x00000800) -#define RTC_IER_SAM4 (0x00001000) -#define RTC_IER_SAM5 (0x00002000) -#define RTC_IER_SAM6 (0x00004000) -#define RTC_IER_SAM7 (0x00008000) - -/* Bit definitions and macros for STPWCH */ -#define RTC_STPWCH_CNT(x) (((x)&0x0000003F)) - -/* Bit definitions and macros for DAYS */ -#define RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)) - -/* Bit definitions and macros for ALRM_DAY */ -#define RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)) - -#endif /* __MCFRTC_H__ */ diff --git a/include/asm-m68k/string.h b/include/asm-m68k/string.h deleted file mode 100644 index e0773a8..0000000 --- a/include/asm-m68k/string.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _M68K_STRING_H_ -#define _M68K_STRING_H_ - -#if 0 -#define __HAVE_ARCH_STRCPY -#define __HAVE_ARCH_STRNCPY -#define __HAVE_ARCH_STRLEN -#define __HAVE_ARCH_STRCMP -#define __HAVE_ARCH_STRCAT -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_BCOPY -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMMOVE -#define __HAVE_ARCH_MEMCMP -#define __HAVE_ARCH_MEMCHR -#endif - -extern int strcasecmp(const char *, const char *); -extern int strncasecmp(const char *, const char *, int); -extern char * strcpy(char *,const char *); -extern char * strncpy(char *,const char *, __kernel_size_t); -extern __kernel_size_t strlen(const char *); -extern int strcmp(const char *,const char *); -extern char * strcat(char *, const char *); -extern void * memset(void *,int,__kernel_size_t); -extern void * memcpy(void *,const void *,__kernel_size_t); -extern void * memmove(void *,const void *,__kernel_size_t); -extern int memcmp(const void *,const void *,__kernel_size_t); -extern void * memchr(const void *,int,__kernel_size_t); - -#endif diff --git a/include/asm-m68k/timer.h b/include/asm-m68k/timer.h deleted file mode 100644 index 1a5de05..0000000 --- a/include/asm-m68k/timer.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * timer.h -- ColdFire internal TIMER support defines. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/****************************************************************************/ -#ifndef timer_h -#define timer_h -/****************************************************************************/ - -/****************************************************************************/ -/* Timer structure */ -/****************************************************************************/ -/* DMA Timer module registers */ -typedef struct dtimer_ctrl { -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272) - u16 tmr; /* 0x00 Mode register */ - u16 res1; /* 0x02 */ - u16 trr; /* 0x04 Reference register */ - u16 res2; /* 0x06 */ - u16 tcr; /* 0x08 Capture register */ - u16 res3; /* 0x0A */ - u16 tcn; /* 0x0C Counter register */ - u16 res4; /* 0x0E */ - u8 res6; /* 0x10 */ - u8 ter; /* 0x11 Event register */ - u16 res7; /* 0x12 */ -#else - u16 tmr; /* 0x00 Mode register */ - u8 txmr; /* 0x02 Extended Mode register */ - u8 ter; /* 0x03 Event register */ - u32 trr; /* 0x04 Reference register */ - u32 tcr; /* 0x08 Capture register */ - u32 tcn; /* 0x0C Counter register */ -#endif -} dtmr_t; - -/*Programmable Interrupt Timer */ -typedef struct pit_ctrl { - u16 pcsr; /* 0x00 Control and Status Register */ - u16 pmr; /* 0x02 Modulus Register */ - u16 pcntr; /* 0x04 Count Register */ -} pit_t; - -/********************************************************************* -* DMA Timers (DTIM) -*********************************************************************/ -/* Bit definitions and macros for DTMR */ -#define DTIM_DTMR_RST (0x0001) /* Reset */ -#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ -#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */ -#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */ -#define DTIM_DTMR_OM (0x0020) /* Output Mode */ -#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ -#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ -#define DTIM_DTMR_RST_EN (0x0001) -#define DTIM_DTMR_RST_RST (0x0000) -#define DTIM_DTMR_CE_ANY (0x00C0) -#define DTIM_DTMR_CE_FALL (0x0080) -#define DTIM_DTMR_CE_RISE (0x0040) -#define DTIM_DTMR_CE_NONE (0x0000) -#define DTIM_DTMR_CLK_DTIN (0x0006) -#define DTIM_DTMR_CLK_DIV16 (0x0004) -#define DTIM_DTMR_CLK_DIV1 (0x0002) -#define DTIM_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for DTXMR */ -#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ -#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */ - -/* Bit definitions and macros for DTER */ -#define DTIM_DTER_CAP (0x01) /* Capture event */ -#define DTIM_DTER_REF (0x02) /* Output reference event */ - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Bit definitions and macros for PCSR */ -#define PIT_PCSR_EN (0x0001) -#define PIT_PCSR_RLD (0x0002) -#define PIT_PCSR_PIF (0x0004) -#define PIT_PCSR_PIE (0x0008) -#define PIT_PCSR_OVW (0x0010) -#define PIT_PCSR_HALTED (0x0020) -#define PIT_PCSR_DOZE (0x0040) -#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for PMR */ -#define PIT_PMR_PM(x) (x) - -/* Bit definitions and macros for PCNTR */ -#define PIT_PCNTR_PC(x) (x) - -/****************************************************************************/ -#endif /* timer_h */ diff --git a/include/asm-m68k/types.h b/include/asm-m68k/types.h deleted file mode 100644 index 3ffcab2..0000000 --- a/include/asm-m68k/types.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef _M68K_TYPES_H -#define _M68K_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -typedef struct { - __u32 u[4]; -} __attribute__((aligned(16))) vector128; - -#ifdef __KERNEL__ -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* DMA addresses are 32-bits wide */ -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif /* __KERNEL__ */ -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h deleted file mode 100644 index a0f2983..0000000 --- a/include/asm-m68k/u-boot.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2000 - 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef __U_BOOT_H__ -#define __U_BOOT_H__ - -/* - * Board information passed to Linux kernel from U-Boot - * - * include/asm-ppc/u-boot.h - */ - -#ifndef __ASSEMBLY__ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_mbar_base; /* base of internal registers */ - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_boot_params; /* where this board expects params */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ -#ifdef CONFIG_PCI - unsigned long bi_pcifreq; /* pci Freq in MHz */ -#endif -#ifdef CONFIG_EXTRA_CLOCK - unsigned long bi_inpfreq; /* input Freq in MHz */ - unsigned long bi_vcofreq; /* vco Freq in MHz */ - unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ -#endif - unsigned long bi_baudrate; /* Console Baudrate */ -} bd_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __U_BOOT_H__ */ diff --git a/include/asm-m68k/uart.h b/include/asm-m68k/uart.h deleted file mode 100644 index 9a528ea..0000000 --- a/include/asm-m68k/uart.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * uart.h -- ColdFire internal UART support defines. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/****************************************************************************/ -#ifndef uart_h -#define uart_h -/****************************************************************************/ - -/* UART module registers */ -/* Register read/write struct */ -typedef struct uart { - u8 umr; /* 0x00 Mode Register */ - u8 resv0[0x3]; - union { - u8 usr; /* 0x04 Status Register */ - u8 ucsr; /* 0x04 Clock Select Register */ - }; - u8 resv1[0x3]; - u8 ucr; /* 0x08 Command Register */ - u8 resv2[0x3]; - union { - u8 utb; /* 0x0c Transmit Buffer */ - u8 urb; /* 0x0c Receive Buffer */ - }; - u8 resv3[0x3]; - union { - u8 uipcr; /* 0x10 Input Port Change Register */ - u8 uacr; /* 0x10 Auxiliary Control reg */ - }; - u8 resv4[0x3]; - union { - u8 uimr; /* 0x14 Interrupt Mask reg */ - u8 uisr; /* 0x14 Interrupt Status reg */ - }; - u8 resv5[0x3]; - u8 ubg1; /* 0x18 Counter Timer Upper Register */ - u8 resv6[0x3]; - u8 ubg2; /* 0x1c Counter Timer Lower Register */ - u8 resv7[0x17]; - u8 uip; /* 0x34 Input Port Register */ - u8 resv8[0x3]; - u8 uop1; /* 0x38 Output Port Set Register */ - u8 resv9[0x3]; - u8 uop0; /* 0x3c Output Port Reset Register */ -} uart_t; - -/********************************************************************* -* Universal Asynchronous Receiver Transmitter (UART) -*********************************************************************/ -/* Bit definitions and macros for UMR */ -#define UART_UMR_BC(x) (((x)&0x03)) -#define UART_UMR_PT (0x04) -#define UART_UMR_PM(x) (((x)&0x03)<<3) -#define UART_UMR_ERR (0x20) -#define UART_UMR_RXIRQ (0x40) -#define UART_UMR_RXRTS (0x80) -#define UART_UMR_SB(x) (((x)&0x0F)) -#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */ -#define UART_UMR_TXRTS (0x20) /* Transmit RTS */ -#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */ -#define UART_UMR_PM_MULTI_ADDR (0x1C) -#define UART_UMR_PM_MULTI_DATA (0x18) -#define UART_UMR_PM_NONE (0x10) -#define UART_UMR_PM_FORCE_HI (0x0C) -#define UART_UMR_PM_FORCE_LO (0x08) -#define UART_UMR_PM_ODD (0x04) -#define UART_UMR_PM_EVEN (0x00) -#define UART_UMR_BC_5 (0x00) -#define UART_UMR_BC_6 (0x01) -#define UART_UMR_BC_7 (0x02) -#define UART_UMR_BC_8 (0x03) -#define UART_UMR_CM_NORMAL (0x00) -#define UART_UMR_CM_ECH (0x40) -#define UART_UMR_CM_LOCAL_LOOP (0x80) -#define UART_UMR_CM_REMOTE_LOOP (0xC0) -#define UART_UMR_SB_STOP_BITS_1 (0x07) -#define UART_UMR_SB_STOP_BITS_15 (0x08) -#define UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for USR */ -#define UART_USR_RXRDY (0x01) -#define UART_USR_FFULL (0x02) -#define UART_USR_TXRDY (0x04) -#define UART_USR_TXEMP (0x08) -#define UART_USR_OE (0x10) -#define UART_USR_PE (0x20) -#define UART_USR_FE (0x40) -#define UART_USR_RB (0x80) - -/* Bit definitions and macros for UCSR */ -#define UART_UCSR_TCS(x) (((x)&0x0F)) -#define UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define UART_UCSR_RCS_SYS_CLK (0xD0) -#define UART_UCSR_RCS_CTM16 (0xE0) -#define UART_UCSR_RCS_CTM (0xF0) -#define UART_UCSR_TCS_SYS_CLK (0x0D) -#define UART_UCSR_TCS_CTM16 (0x0E) -#define UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for UCR */ -#define UART_UCR_RXC(x) (((x)&0x03)) -#define UART_UCR_TXC(x) (((x)&0x03)<<2) -#define UART_UCR_MISC(x) (((x)&0x07)<<4) -#define UART_UCR_NONE (0x00) -#define UART_UCR_STOP_BREAK (0x70) -#define UART_UCR_START_BREAK (0x60) -#define UART_UCR_BKCHGINT (0x50) -#define UART_UCR_RESET_ERROR (0x40) -#define UART_UCR_RESET_TX (0x30) -#define UART_UCR_RESET_RX (0x20) -#define UART_UCR_RESET_MR (0x10) -#define UART_UCR_TX_DISABLED (0x08) -#define UART_UCR_TX_ENABLED (0x04) -#define UART_UCR_RX_DISABLED (0x02) -#define UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for UIPCR */ -#define UART_UIPCR_CTS (0x01) -#define UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for UACR */ -#define UART_UACR_IEC (0x01) - -/* Bit definitions and macros for UIMR */ -#define UART_UIMR_TXRDY (0x01) -#define UART_UIMR_RXRDY_FU (0x02) -#define UART_UIMR_DB (0x04) -#define UART_UIMR_COS (0x80) - -/* Bit definitions and macros for UISR */ -#define UART_UISR_TXRDY (0x01) -#define UART_UISR_RXRDY_FU (0x02) -#define UART_UISR_DB (0x04) -#define UART_UISR_RXFTO (0x08) -#define UART_UISR_TXFIFO (0x10) -#define UART_UISR_RXFIFO (0x20) -#define UART_UISR_COS (0x80) - -/* Bit definitions and macros for UIP */ -#define UART_UIP_CTS (0x01) - -/* Bit definitions and macros for UOP1 */ -#define UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for UOP0 */ -#define UART_UOP0_RTS (0x01) - -/****************************************************************************/ -#endif /* mcfuart_h */ diff --git a/include/asm-m68k/unaligned.h b/include/asm-m68k/unaligned.h deleted file mode 100644 index 328aa0c..0000000 --- a/include/asm-m68k/unaligned.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _ASM_M68K_UNALIGNED_H -#define _ASM_M68K_UNALIGNED_H - -#ifdef CONFIG_COLDFIRE -#include -#else -#include -#endif - -#include - -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#endif /* _ASM_M68K_UNALIGNED_H */ diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h deleted file mode 100644 index deb23e0..0000000 --- a/include/asm-microblaze/asm.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* FSL macros */ -#define NGET(val, fslnum) \ - __asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val)); - -#define GET(val, fslnum) \ - __asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val)); - -#define NCGET(val, fslnum) \ - __asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val)); - -#define CGET(val, fslnum) \ - __asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val)); - -#define NPUT(val, fslnum) \ - __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val)); - -#define PUT(val, fslnum) \ - __asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val)); - -#define NCPUT(val, fslnum) \ - __asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val)); - -#define CPUT(val, fslnum) \ - __asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val)); - -/* CPU dependent */ -/* machine status register */ -#define MFS(val, reg) \ - __asm__ __volatile__ ("mfs %0," #reg :"=r" (val)); - -#define MTS(val, reg) \ - __asm__ __volatile__ ("mts " #reg ", %0"::"r" (val)); - -/* get return address from interrupt */ -#define R14(val) \ - __asm__ __volatile__ ("addi %0, r14, 0":"=r" (val)); - -#define NOP __asm__ __volatile__ ("nop"); - -/* use machine status registe USE_MSR_REG */ -#ifdef XILINX_USE_MSR_INSTR -#define MSRSET(val) \ - __asm__ __volatile__ ("msrset r0," #val ); - -#define MSRCLR(val) \ - __asm__ __volatile__ ("msrclr r0," #val ); - -#else -#define MSRSET(val) \ -{ \ - register unsigned tmp; \ - __asm__ __volatile__ (" \ - mfs %0, rmsr; \ - ori %0, %0, "#val"; \ - mts rmsr, %0; \ - nop;" \ - : "=r" (tmp) \ - : "d" (val) \ - : "memory"); \ -} - -#define MSRCLR(val) \ -{ \ - register unsigned tmp; \ - __asm__ __volatile__ (" \ - mfs %0, rmsr; \ - andi %0, %0, ~"#val"; \ - mts rmsr, %0; \ - nop;" \ - : "=r" (tmp) \ - : "d" (val) \ - : "memory"); \ -} -#endif diff --git a/include/asm-microblaze/bitops.h b/include/asm-microblaze/bitops.h deleted file mode 100644 index e8c835f..0000000 --- a/include/asm-microblaze/bitops.h +++ /dev/null @@ -1,392 +0,0 @@ -#ifndef _MICROBLAZE_BITOPS_H -#define _MICROBLAZE_BITOPS_H - -/* - * Copyright 1992, Linus Torvalds. - */ - -#include -#include /* swab32 */ -#include /* save_flags */ - -#ifdef __KERNEL__ -/* - * Function prototypes to keep gcc -Wall happy - */ - -/* - * The __ functions are not atomic - */ - -extern void set_bit(int nr, volatile void * addr); -extern void __set_bit(int nr, volatile void * addr); - -extern void clear_bit(int nr, volatile void * addr); -#define __clear_bit(nr, addr) clear_bit(nr, addr) -#define PLATFORM__CLEAR_BIT - -extern void change_bit(int nr, volatile void * addr); -extern void __change_bit(int nr, volatile void * addr); -extern int test_and_set_bit(int nr, volatile void * addr); -extern int __test_and_set_bit(int nr, volatile void * addr); -extern int test_and_clear_bit(int nr, volatile void * addr); -extern int __test_and_clear_bit(int nr, volatile void * addr); -extern int test_and_change_bit(int nr, volatile void * addr); -extern int __test_and_change_bit(int nr, volatile void * addr); -extern int __constant_test_bit(int nr, const volatile void * addr); -extern int __test_bit(int nr, volatile void * addr); -extern int find_first_zero_bit(void * addr, unsigned size); -extern int find_next_zero_bit (void * addr, int size, int offset); - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -extern __inline__ unsigned long ffz(unsigned long word) -{ - unsigned long result = 0; - - while(word & 1) { - result++; - word >>= 1; - } - return result; -} - - -extern __inline__ void set_bit(int nr, volatile void * addr) -{ - int * a = (int *) addr; - int mask; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_flags_cli(flags); - *a |= mask; - restore_flags(flags); -} - -extern __inline__ void __set_bit(int nr, volatile void * addr) -{ - int * a = (int *) addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a |= mask; -} -#define PLATFORM__SET_BIT - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -extern __inline__ void clear_bit(int nr, volatile void * addr) -{ - int * a = (int *) addr; - int mask; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_flags_cli(flags); - *a &= ~mask; - restore_flags(flags); -} - -extern __inline__ void change_bit(int nr, volatile void * addr) -{ - int mask; - unsigned long flags; - unsigned long *ADDR = (unsigned long *) addr; - - ADDR += nr >> 5; - mask = 1 << (nr & 31); - save_flags_cli(flags); - *ADDR ^= mask; - restore_flags(flags); -} - -extern __inline__ void __change_bit(int nr, volatile void * addr) -{ - int mask; - unsigned long *ADDR = (unsigned long *) addr; - - ADDR += nr >> 5; - mask = 1 << (nr & 31); - *ADDR ^= mask; -} - -extern __inline__ int test_and_set_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_flags_cli(flags); - retval = (mask & *a) != 0; - *a |= mask; - restore_flags(flags); - - return retval; -} - -extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a |= mask; - return retval; -} - -extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_flags_cli(flags); - retval = (mask & *a) != 0; - *a &= ~mask; - restore_flags(flags); - - return retval; -} - -extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a &= ~mask; - return retval; -} - -extern __inline__ int test_and_change_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - save_flags_cli(flags); - retval = (mask & *a) != 0; - *a ^= mask; - restore_flags(flags); - - return retval; -} - -extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = (volatile unsigned int *) addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a ^= mask; - return retval; -} - -/* - * This routine doesn't need to be atomic. - */ -extern __inline__ int __constant_test_bit(int nr, const volatile void * addr) -{ - return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; -} - -extern __inline__ int __test_bit(int nr, volatile void * addr) -{ - int * a = (int *) addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - return ((mask & *a) != 0); -} - -#define test_bit(nr,addr) \ -(__builtin_constant_p(nr) ? \ - __constant_test_bit((nr),(addr)) : \ - __test_bit((nr),(addr))) - -#define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) - -extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (32-offset); - if (size < 32) - goto found_first; - if (~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while (size & ~31UL) { - if (~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; - -found_first: - tmp |= ~0UL >> size; -found_middle: - return result + ffz(tmp); -} - -/* - * hweightN: returns the hamming weight (i.e. the number - * of bits set) of a N-bit word - */ - -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) - - -extern __inline__ int ext2_set_bit(int nr, volatile void * addr) -{ - int mask, retval; - unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - save_flags_cli(flags); - retval = (mask & *ADDR) != 0; - *ADDR |= mask; - restore_flags(flags); - return retval; -} - -extern __inline__ int ext2_clear_bit(int nr, volatile void * addr) -{ - int mask, retval; - unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - save_flags_cli(flags); - retval = (mask & *ADDR) != 0; - *ADDR &= ~mask; - restore_flags(flags); - return retval; -} - -extern __inline__ int ext2_test_bit(int nr, const volatile void * addr) -{ - int mask; - const volatile unsigned char *ADDR = (const unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - return ((mask & *ADDR) != 0); -} - -#define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) - -extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if(offset) { - /* We hold the little endian value in tmp, but then the - * shift is illegal. So we could keep a big endian value - * in tmp, like this: - * - * tmp = __swab32(*(p++)); - * tmp |= ~0UL >> (32-offset); - * - * but this would decrease preformance, so we change the - * shift: - */ - tmp = *(p++); - tmp |= __swab32(~0UL >> (32-offset)); - if(size < 32) - goto found_first; - if(~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while(size & ~31UL) { - if(~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if(!size) - return result; - tmp = *p; - -found_first: - /* tmp is little endian, so we would have to swab the shift, - * see above. But then we have to swab tmp below for ffz, so - * we might as well do this here. - */ - return result + ffz(__swab32(tmp) | (~0UL << size)); -found_middle: - return result + ffz(__swab32(tmp)); -} - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -/** - * hweightN - returns the hamming weight of a N-bit word - * @x: the word to weigh - * - * The Hamming Weight of a number is the total number of bits set in it. - */ - -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) - -#endif /* __KERNEL__ */ - -#endif /* _MICROBLAZE_BITOPS_H */ diff --git a/include/asm-microblaze/byteorder.h b/include/asm-microblaze/byteorder.h deleted file mode 100644 index a4a75b7..0000000 --- a/include/asm-microblaze/byteorder.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * include/asm-microblaze/byteorder.h -- Endian id and conversion ops - * - * Copyright (C) 2003 John Williams - * Copyright (C) 2001 NEC Corporation - * Copyright (C) 2001 Miles Bader - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - * - * Written by Miles Bader - * Microblaze port by John Williams - */ - -#ifndef __MICROBLAZE_BYTEORDER_H__ -#define __MICROBLAZE_BYTEORDER_H__ - -#include - -#ifdef __GNUC__ - -/* This is effectively a dupe of the arch-independent byteswap - code in include/linux/byteorder/swab.h, however we force a cast - of the result up to 32 bits. This in turn forces the compiler - to explicitly clear the high 16 bits, which it wasn't doing otherwise. - - I think this is a symptom of a bug in mb-gcc. JW 20040303 -*/ - - -static __inline__ __u16 ___arch__swab16 (__u16 half_word) -{ - /* 32 bit temp to cast result, forcing clearing of high word */ - __u32 temp; - - temp = ((half_word & 0x00FFU) << 8) | ((half_word & 0xFF00U) >> 8); - - return (__u16) temp; -} - -#define __arch__swab16(x) ___arch__swab16(x) - -/* Microblaze has no arch-specific endian conversion insns */ - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#include - -#endif /* __MICROBLAZE_BYTEORDER_H__ */ diff --git a/include/asm-microblaze/config.h b/include/asm-microblaze/config.h deleted file mode 100644 index 8a9064b..0000000 --- a/include/asm-microblaze/config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -/* Relocation to SDRAM works on all Microblaze boards */ -#define CONFIG_RELOC_FIXUP_WORKS - -#endif diff --git a/include/asm-microblaze/errno.h b/include/asm-microblaze/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/include/asm-microblaze/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h deleted file mode 100644 index ec7837f..0000000 --- a/include/asm-microblaze/global_data.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long have_console; /* serial_init() was called */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long fb_base; /* base address of frame buffer */ - void **jt; /* jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31") - -#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h deleted file mode 100644 index 7e190d1..0000000 --- a/include/asm-microblaze/io.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * include/asm-microblaze/io.h -- Misc I/O operations - * - * Copyright (C) 2003 John Williams - * Copyright (C) 2001,02 NEC Corporation - * Copyright (C) 2001,02 Miles Bader - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - * - * Written by Miles Bader - * Microblaze port by John Williams - */ - -#ifndef __MICROBLAZE_IO_H__ -#define __MICROBLAZE_IO_H__ - -#include - -#define IO_SPACE_LIMIT 0xFFFFFFFF - -#define readb(addr) \ - ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) -#define readw(addr) \ - ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) -#define readl(addr) \ - ({ unsigned long __v = (*(volatile unsigned long *) (addr)); __v; }) - -#define writeb(b, addr) \ - (void)((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b, addr) \ - (void)((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b, addr) \ - (void)((*(volatile unsigned int *) (addr)) = (b)) - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -#define inb(addr) readb (addr) -#define inw(addr) readw (addr) -#define inl(addr) readl (addr) -#define outb(x, addr) ((void) writeb (x, addr)) -#define outw(x, addr) ((void) writew (x, addr)) -#define outl(x, addr) ((void) writel (x, addr)) - -/* Some #definitions to keep strange Xilinx code happy */ -#define in_8(addr) readb (addr) -#define in_be16(addr) readw (addr) -#define in_be32(addr) readl (addr) - -#define out_8(addr,x ) outb (x,addr) -#define out_be16(addr,x ) outw (x,addr) -#define out_be32(addr,x ) outl (x,addr) - - -#define inb_p(port) inb((port)) -#define outb_p(val, port) outb((val), (port)) -#define inw_p(port) inw((port)) -#define outw_p(val, port) outw((val), (port)) -#define inl_p(port) inl((port)) -#define outl_p(val, port) outl((val), (port)) - -/* Some defines to keep the MTD flash drivers happy */ - -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel - -static inline void io_insb (unsigned long port, void *dst, unsigned long count) -{ - unsigned char *p = dst; - while (count--) - *p++ = inb (port); -} -static inline void io_insw (unsigned long port, void *dst, unsigned long count) -{ - unsigned short *p = dst; - while (count--) - *p++ = inw (port); -} -static inline void io_insl (unsigned long port, void *dst, unsigned long count) -{ - unsigned long *p = dst; - while (count--) - *p++ = inl (port); -} - -static inline void -io_outsb (unsigned long port, const void *src, unsigned long count) -{ - const unsigned char *p = src; - while (count--) - outb (*p++, port); -} -static inline void -io_outsw (unsigned long port, const void *src, unsigned long count) -{ - const unsigned short *p = src; - while (count--) - outw (*p++, port); -} -static inline void -io_outsl (unsigned long port, const void *src, unsigned long count) -{ - const unsigned long *p = src; - while (count--) - outl (*p++, port); -} - -#define outsb(a,b,l) io_outsb(a,b,l) -#define outsw(a,b,l) io_outsw(a,b,l) -#define outsl(a,b,l) io_outsl(a,b,l) - -#define insb(a,b,l) io_insb(a,b,l) -#define insw(a,b,l) io_insw(a,b,l) -#define insl(a,b,l) io_insl(a,b,l) - - -#define iounmap(addr) ((void)0) -#define ioremap(physaddr, size) (physaddr) -#define ioremap_nocache(physaddr, size) (physaddr) -#define ioremap_writethrough(physaddr, size) (physaddr) -#define ioremap_fullcache(physaddr, size) (physaddr) - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -#endif /* __MICROBLAZE_IO_H__ */ diff --git a/include/asm-microblaze/microblaze_intc.h b/include/asm-microblaze/microblaze_intc.h deleted file mode 100644 index 4c385aa..0000000 --- a/include/asm-microblaze/microblaze_intc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -typedef volatile struct microblaze_intc_t { - int isr; /* interrupt status register */ - int ipr; /* interrupt pending register */ - int ier; /* interrupt enable register */ - int iar; /* interrupt acknowledge register */ - int sie; /* set interrupt enable bits */ - int cie; /* clear interrupt enable bits */ - int ivr; /* interrupt vector register */ - int mer; /* master enable register */ -} microblaze_intc_t; - -struct irq_action { - interrupt_handler_t *handler; /* pointer to interrupt rutine */ - void *arg; - int count; /* number of interrupt */ -}; - -void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, - void *arg); diff --git a/include/asm-microblaze/microblaze_timer.h b/include/asm-microblaze/microblaze_timer.h deleted file mode 100644 index 844c8db..0000000 --- a/include/asm-microblaze/microblaze_timer.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define TIMER_ENABLE_ALL 0x400 /* ENALL */ -#define TIMER_PWM 0x200 /* PWMA0 */ -#define TIMER_INTERRUPT 0x100 /* T0INT */ -#define TIMER_ENABLE 0x080 /* ENT0 */ -#define TIMER_ENABLE_INTR 0x040 /* ENIT0 */ -#define TIMER_RESET 0x020 /* LOAD0 */ -#define TIMER_RELOAD 0x010 /* ARHT0 */ -#define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */ -#define TIMER_EXT_COMPARE 0x004 /* GENT0 */ -#define TIMER_DOWN_COUNT 0x002 /* UDT0 */ -#define TIMER_CAPTURE_MODE 0x001 /* MDT0 */ - -typedef volatile struct microblaze_timer_t { - int control; /* control/statuc register TCSR */ - int loadreg; /* load register TLR */ - int counter; /* timer/counter register */ -} microblaze_timer_t; diff --git a/include/asm-microblaze/posix_types.h b/include/asm-microblaze/posix_types.h deleted file mode 100644 index 9a2cc66..0000000 --- a/include/asm-microblaze/posix_types.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * include/asm-microblaze/posix_types.h -- Kernel versions of standard types - * - * Copyright (C) 2003 John Williams - * Copyright (C) 2001,2002 NEC Corporation - * Copyright (C) 2001,2002 Miles Bader - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - * - * Written by Miles Bader - * Microblaze port by John Williams - */ - -#ifndef __MICROBLAZE_POSIX_TYPES_H__ -#define __MICROBLAZE_POSIX_TYPES_H__ - -#include - - -typedef unsigned int __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned long long __kernel_ino64_t; -typedef unsigned int __kernel_mode_t; -typedef unsigned int __kernel_nlink_t; -typedef long __kernel_off_t; -typedef long long __kernel_loff_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned int __kernel_uid_t; -typedef unsigned int __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd, fd_set) \ - __set_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) -#undef __FD_CLR -#define __FD_CLR(fd, fd_set) \ - __clear_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) -#undef __FD_ISSET -#define __FD_ISSET(fd, fd_set) \ - __test_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) -#undef __FD_ZERO -#define __FD_ZERO(fd_set) \ - memset (fd_set, 0, sizeof (*(fd_set *)fd_set)) - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ - -#endif /* __MICROBLAZE_POSIX_TYPES_H__ */ diff --git a/include/asm-microblaze/processor.h b/include/asm-microblaze/processor.h deleted file mode 100644 index 78b8976..0000000 --- a/include/asm-microblaze/processor.h +++ /dev/null @@ -1 +0,0 @@ -/* FIXME: Implement this! */ diff --git a/include/asm-microblaze/ptrace.h b/include/asm-microblaze/ptrace.h deleted file mode 100644 index b796d4f..0000000 --- a/include/asm-microblaze/ptrace.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * include/asm-microblaze/ptrace.h -- Access to CPU registers - * - * Copyright (C) 2003 John Williams - * Copyright (C) 2001,2002 NEC Corporation - * Copyright (C) 2001,2002 Miles Bader - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - * - * Written by Miles Bader - * Microblaze port by John Williams - */ - -#ifndef __MICROBLAZE_PTRACE_H__ -#define __MICROBLAZE_PTRACE_H__ - - -/* Microblaze general purpose registers with special meanings. */ -#define GPR_ZERO 0 /* constant zero */ -#define GPR_ASM 18 /* reserved for assembler */ -#define GPR_SP 1 /* stack pointer */ -#define GPR_GP 2 /* global data pointer */ -#define GPR_EP 30 /* `element pointer' */ -#define GPR_LP 15 /* link pointer (current return address) */ - -/* These aren't official names, but they make some code more descriptive. */ -#define GPR_ARG0 5 -#define GPR_ARG1 6 -#define GPR_ARG2 7 -#define GPR_ARG3 8 -#define GPR_ARG4 9 -#define GPR_ARG5 10 -#define GPR_RVAL0 3 -#define GPR_RVAL1 4 -#define GPR_RVAL GPR_RVAL0 - -#define NUM_GPRS 32 - -/* `system' registers. */ -/* Note these are old v850 values, microblaze has many fewer */ -#define SR_EIPC 0 -#define SR_EIPSW 1 -#define SR_FEPC 2 -#define SR_FEPSW 3 -#define SR_ECR 4 -#define SR_PSW 5 -#define SR_CTPC 16 -#define SR_CTPSW 17 -#define SR_DBPC 18 -#define SR_DBPSW 19 -#define SR_CTBP 20 -#define SR_DIR 21 -#define SR_ASID 23 - - -#ifndef __ASSEMBLY__ - -typedef unsigned long microblaze_reg_t; - -/* How processor state is stored on the stack during a syscall/signal. - If you change this structure, change the associated assembly-language - macros below too (PT_*)! */ -struct pt_regs -{ - /* General purpose registers. */ - microblaze_reg_t gpr[NUM_GPRS]; - - microblaze_reg_t pc; /* program counter */ - microblaze_reg_t psw; /* program status word */ - - microblaze_reg_t kernel_mode; /* 1 if in `kernel mode', 0 if user mode */ - microblaze_reg_t single_step; /* 1 if in single step mode */ -}; - - -#define instruction_pointer(regs) ((regs)->pc) -#define user_mode(regs) (!(regs)->kernel_mode) - -/* When a struct pt_regs is used to save user state for a system call in - the kernel, the system call is stored in the space for R0 (since it's - never used otherwise, R0 being a constant 0). Non-system-calls - simply store 0 there. */ -#define PT_REGS_SYSCALL(regs) (regs)->gpr[0] -#define PT_REGS_SET_SYSCALL(regs, val) ((regs)->gpr[0] = (val)) - -#endif /* !__ASSEMBLY__ */ - - -/* The number of bytes used to store each register. */ -#define _PT_REG_SIZE 4 - -/* Offset of a general purpose register in a stuct pt_regs. */ -#define PT_GPR(num) ((num) * _PT_REG_SIZE) - -/* Offsets of various special registers & fields in a struct pt_regs. */ -#define NUM_SPECIAL 4 -#define PT_PC ((NUM_GPRS + 0) * _PT_REG_SIZE) -#define PT_PSW ((NUM_GPRS + 1) * _PT_REG_SIZE) -#define PT_KERNEL_MODE ((NUM_GPRS + 2) * _PT_REG_SIZE) -#define PT_SINGLESTEP ((NUM_GPRS + 3) * _PT_REG_SIZE) - -#define PT_SYSCALL PT_GPR(0) - -/* Size of struct pt_regs, including alignment. */ -#define PT_SIZE ((NUM_GPRS + NUM_SPECIAL) * _PT_REG_SIZE) - -/* These are `magic' values for PTRACE_PEEKUSR that return info about where - a process is located in memory. */ -#define PT_TEXT_ADDR (PT_SIZE + 1) -#define PT_TEXT_LEN (PT_SIZE + 2) -#define PT_DATA_ADDR (PT_SIZE + 3) -#define PT_DATA_LEN (PT_SIZE + 4) - -#endif /* __MICROBLAZE_PTRACE_H__ */ diff --git a/include/asm-microblaze/string.h b/include/asm-microblaze/string.h deleted file mode 100644 index 724f5bd..0000000 --- a/include/asm-microblaze/string.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * include/asm-microblaze/string.h -- Architecture specific string routines - * - * Copyright (C) 2003 John Williams - * Copyright (C) 2001,2002 NEC Corporation - * Copyright (C) 2001,2002 Miles Bader - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - * - * Written by Miles Bader - * Microblaze port by John Williams - */ - -#ifndef __MICROBLAZE_STRING_H__ -#define __MICROBLAZE_STRING_H__ - -#if 0 -#define __HAVE_ARCH_BCOPY -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_MEMMOVE - -extern void *memcpy (void *, const void *, __kernel_size_t); -extern void bcopy (const char *, char *, int); -extern void *memset (void *, int, __kernel_size_t); -extern void *memmove (void *, const void *, __kernel_size_t); -#endif - -#endif /* __MICROBLAZE_STRING_H__ */ diff --git a/include/asm-microblaze/system.h b/include/asm-microblaze/system.h deleted file mode 100644 index 0297a11..0000000 --- a/include/asm-microblaze/system.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * include/asm-microblaze/system.h -- Low-level interrupt/thread ops - * - * Copyright (C) 2003 John Williams (jwilliams@itee.uq.edu.au) - * based upon microblaze version - * Copyright (C) 2001 NEC Corporation - * Copyright (C) 2001 Miles Bader - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - * - * Written by Miles Bader - * Microblaze port by John Williams - * Microblaze port by John Williams - */ - -#ifndef __MICROBLAZE_SYSTEM_H__ -#define __MICROBLAZE_SYSTEM_H__ - -#if 0 -#include -#endif -#include - -#define prepare_to_switch() do { } while (0) - -/* - * switch_to(n) should switch tasks to task ptr, first checking that - * ptr isn't the current task, in which case it does nothing. - */ -struct thread_struct; -extern void *switch_thread (struct thread_struct *last, - struct thread_struct *next); -#define switch_to(prev,next,last) do { \ - if (prev != next) { \ - (last) = switch_thread (&prev->thread, &next->thread); \ - } \ -} while (0) - - -/* Enable/disable interrupts. */ -#define __sti() \ -{ \ - register unsigned tmp; \ - __asm__ __volatile__ (" \ - mfs %0, rmsr; \ - ori %0, %0, 2; \ - mts rmsr, %0" \ - : "=r" (tmp) \ - : \ - : "memory"); \ -} - -#define __cli() \ -{ \ - register unsigned tmp; \ - __asm__ __volatile__ (" \ - mfs %0, rmsr; \ - andi %0, %0, ~2; \ - mts rmsr, %0" \ - : "=r" (tmp) \ - : \ - : "memory"); \ -} - -#define __save_flags(flags) \ - __asm__ __volatile__ ("mfs %0, rmsr" : "=r" (flags)) -#define __restore_flags(flags) \ - __asm__ __volatile__ ("mts rmsr, %0" :: "r" (flags)) - -#define __save_flags_cli(flags) \ -{ \ - register unsigned tmp; \ - __asm__ __volatile__ (" \ - mfs %0, rmsr; \ - andi %1, %0, ~2; \ - mts rmsr, %1;" \ - : "=r" (flags), "=r" (tmp) \ - : \ - : "memory"); \ -} - -#define __save_flags_sti(flags) \ -{ \ - register unsigned tmp; \ - __asm__ __volatile__ (" \ - mfs %0, rmsr; \ - ori %1, %0, 2; \ - mts rmsr, %1;" \ - : "=r" (flags) ,"=r" (tmp) \ - : \ - : "memory"); \ -} - -/* For spinlocks etc */ -#define local_irq_save(flags) __save_flags_cli (flags) -#define local_irq_set(flags) __save_flags_sti (flags) -#define local_irq_restore(flags) __restore_flags (flags) -#define local_irq_disable() __cli () -#define local_irq_enable() __sti () - -#define cli() __cli () -#define sti() __sti () -#define save_flags(flags) __save_flags (flags) -#define restore_flags(flags) __restore_flags (flags) -#define save_flags_cli(flags) __save_flags_cli (flags) - -/* - * Force strict CPU ordering. - * Not really required on microblaze... - */ -#define nop() __asm__ __volatile__ ("nop") -#define mb() __asm__ __volatile__ ("nop" ::: "memory") -#define rmb() mb () -#define wmb() mb () -#define set_mb(var, value) do { var = value; mb(); } while (0) -#define set_wmb(var, value) do { var = value; wmb (); } while (0) - -#ifdef CONFIG_SMP -#define smp_mb() mb () -#define smp_rmb() rmb () -#define smp_wmb() wmb () -#else -#define smp_mb() barrier () -#define smp_rmb() barrier () -#define smp_wmb() barrier () -#endif - -#define xchg(ptr, with) \ - ((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr)))) -#define tas(ptr) (xchg ((ptr), 1)) - -extern inline unsigned long __xchg (unsigned long with, - __volatile__ void *ptr, int size) -{ - unsigned long tmp, flags; - - save_flags_cli (flags); - - switch (size) { - case 1: - tmp = *(unsigned char *)ptr; - *(unsigned char *)ptr = with; - break; - case 2: - tmp = *(unsigned short *)ptr; - *(unsigned short *)ptr = with; - break; - case 4: - tmp = *(unsigned long *)ptr; - *(unsigned long *)ptr = with; - break; - } - - restore_flags (flags); - - return tmp; -} - -#endif /* __MICROBLAZE_SYSTEM_H__ */ diff --git a/include/asm-microblaze/types.h b/include/asm-microblaze/types.h deleted file mode 100644 index 77094f6..0000000 --- a/include/asm-microblaze/types.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef _ASM_TYPES_H -#define _ASM_TYPES_H - -/* - * This file is never included by application software unless - * explicitly requested (e.g., via linux/types.h) in which case the - * application is Linux specific so (user-) name space pollution is - * not a major issue. However, for interoperability, libraries still - * need to be careful to avoid a name clashes. - */ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; -#endif /* __KERNEL__ */ - -#endif /* _ASM_TYPES_H */ diff --git a/include/asm-microblaze/u-boot.h b/include/asm-microblaze/u-boot.h deleted file mode 100644 index 543a6b1..0000000 --- a/include/asm-microblaze/u-boot.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef _U_BOOT_H_ -#define _U_BOOT_H_ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned long bi_baudrate; /* Console Baudrate */ -} bd_t; - - -#endif /* _U_BOOT_H_ */ diff --git a/include/asm-microblaze/unaligned.h b/include/asm-microblaze/unaligned.h deleted file mode 100644 index 785c2e9..0000000 --- a/include/asm-microblaze/unaligned.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _ASM_MICROBLAZE_UNALIGNED_H -#define _ASM_MICROBLAZE_UNALIGNED_H - -#ifdef __KERNEL__ - -/* - * The Microblaze can do unaligned accesses itself in big endian mode. - */ -#include -#include - -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#endif /* __KERNEL__ */ -#endif /* _ASM_MICROBLAZE_UNALIGNED_H */ diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h deleted file mode 100644 index 3a1e6d6..0000000 --- a/include/asm-mips/addrspace.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 99 Ralf Baechle - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. - */ -#ifndef _ASM_ADDRSPACE_H -#define _ASM_ADDRSPACE_H - -/* - * Configure language - */ -#ifdef __ASSEMBLY__ -#define _ATYPE_ -#define _ATYPE32_ -#define _ATYPE64_ -#define _CONST64_(x) x -#else -#define _ATYPE_ __PTRDIFF_TYPE__ -#define _ATYPE32_ int -#define _ATYPE64_ __s64 -#ifdef CONFIG_64BIT -#define _CONST64_(x) x ## L -#else -#define _CONST64_(x) x ## LL -#endif -#endif - -/* - * 32-bit MIPS address spaces - */ -#ifdef __ASSEMBLY__ -#define _ACAST32_ -#define _ACAST64_ -#else -#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ -#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ -#endif - -/* - * Returns the kernel segment base of a given address - */ -#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) - -/* - * Returns the physical address of a CKSEGx / XKPHYS address - */ -#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) -#define XPHYSADDR(a) ((_ACAST64_(a)) & \ - _CONST64_(0x000000ffffffffff)) - -#ifdef CONFIG_64BIT - -/* - * Memory segments (64bit kernel mode addresses) - * The compatibility segments use the full 64-bit sign extended value. Note - * the R8000 doesn't have them so don't reference these in generic MIPS code. - */ -#define XKUSEG _CONST64_(0x0000000000000000) -#define XKSSEG _CONST64_(0x4000000000000000) -#define XKPHYS _CONST64_(0x8000000000000000) -#define XKSEG _CONST64_(0xc000000000000000) -#define CKSEG0 _CONST64_(0xffffffff80000000) -#define CKSEG1 _CONST64_(0xffffffffa0000000) -#define CKSSEG _CONST64_(0xffffffffc0000000) -#define CKSEG3 _CONST64_(0xffffffffe0000000) - -#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) - -#else - -#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) - -/* - * Map an address to a certain kernel segment - */ -#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) -#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) -#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) -#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) - -/* - * Memory segments (32bit kernel mode addresses) - * These are the traditional names used in the 32-bit universe. - */ -#define KUSEG 0x00000000 -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 -#define KSEG2 0xc0000000 -#define KSEG3 0xe0000000 - -#define CKUSEG 0x00000000 -#define CKSEG0 0x80000000 -#define CKSEG1 0xa0000000 -#define CKSEG2 0xc0000000 -#define CKSEG3 0xe0000000 - -#endif - -/* - * Cache modes for XKPHYS address conversion macros - */ -#define K_CALG_COH_EXCL1_NOL2 0 -#define K_CALG_COH_SHRL1_NOL2 1 -#define K_CALG_UNCACHED 2 -#define K_CALG_NONCOHERENT 3 -#define K_CALG_COH_EXCL 4 -#define K_CALG_COH_SHAREABLE 5 -#define K_CALG_NOTUSED 6 -#define K_CALG_UNCACHED_ACCEL 7 - -/* - * 64-bit address conversions - */ -#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) -#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) -#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ - (_CONST64_(cm) << 59) | (a)) - -/* - * Returns the uncached address of a sdram address - */ -#ifndef __ASSEMBLY__ -#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) -/* We use a 36 bit physical address map here and - cannot access physical memory directly from core */ -#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) -#else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) KSEG1ADDR(a) -#endif /* CONFIG_SOC_AU1X00 */ -#endif /* __ASSEMBLY__ */ - -/* - * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting - * the region, 3 bits for the CCA mode. This leaves 59 bits of which the - * R8000 implements most with its 48-bit physical address space. - */ -#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ - -#ifndef CONFIG_CPU_R8000 - -/* - * The R8000 doesn't have the 32-bit compat spaces so we don't define them - * in order to catch bugs in the source code. - */ - -#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) -#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ - -#endif - -#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) -#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) - -#endif /* _ASM_ADDRSPACE_H */ diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h deleted file mode 100644 index 608cfcf..0000000 --- a/include/asm-mips/asm.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle - * Copyright (C) 1999 by Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - * Copyright (C) 2002 Maciej W. Rozycki - * - * Some useful macros for MIPS assembler code - * - * Some of the routines below contain useless nops that will be optimized - * away by gas in -O mode. These nops are however required to fill delay - * slots in noreorder mode. - */ -#ifndef __ASM_ASM_H -#define __ASM_ASM_H - -#include - -#ifndef CAT -#ifdef __STDC__ -#define __CAT(str1, str2) str1##str2 -#else -#define __CAT(str1, str2) str1/**/str2 -#endif -#define CAT(str1, str2) __CAT(str1, str2) -#endif - -/* - * PIC specific declarations - * Not used for the kernel but here seems to be the right place. - */ -#ifdef __PIC__ -#define CPRESTORE(register) \ - .cprestore register -#define CPADD(register) \ - .cpadd register -#define CPLOAD(register) \ - .cpload register -#else -#define CPRESTORE(register) -#define CPADD(register) -#define CPLOAD(register) -#endif - -/* - * LEAF - declare leaf routine - */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ -symbol: .frame sp, 0, ra - -/* - * NESTED - declare nested routine entry point - */ -#define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ -symbol: .frame sp, framesize, rpc - -/* - * END - mark end of function - */ -#define END(function) \ - .end function; \ - .size function, .-function - -/* - * EXPORT - export definition of symbol - */ -#define EXPORT(symbol) \ - .globl symbol; \ -symbol: - -/* - * FEXPORT - export definition of a function symbol - */ -#define FEXPORT(symbol) \ - .globl symbol; \ - .type symbol, @function; \ -symbol: - -/* - * ABS - export absolute symbol - */ -#define ABS(symbol,value) \ - .globl symbol; \ -symbol = value - -#define PANIC(msg) \ - .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal panic; \ -9: b 9b; \ - .set pop; \ - TEXT(msg) - -/* - * Print formatted string - */ -#ifdef CONFIG_PRINTK -#define PRINT(string) \ - .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal printk; \ - .set pop; \ - TEXT(string) -#else -#define PRINT(string) -#endif - -#define TEXT(msg) \ - .pushsection .data; \ -8: .asciiz msg; \ - .popsection; - -/* - * Build text tables - */ -#define TTABLE(string) \ - .pushsection .text; \ - .word 1f; \ - .popsection \ - .pushsection .data; \ -1: .asciiz string; \ - .popsection - -/* - * MIPS IV pref instruction. - * Use with .set noreorder only! - * - * MIPS IV implementations are free to treat this as a nop. The R5000 - * is one of them. So we should have an option not to use this instruction. - */ -#ifdef CONFIG_CPU_HAS_PREFETCH - -#define PREF(hint,addr) \ - .set push; \ - .set mips4; \ - pref hint, addr; \ - .set pop - -#define PREFX(hint,addr) \ - .set push; \ - .set mips4; \ - prefx hint, addr; \ - .set pop - -#else /* !CONFIG_CPU_HAS_PREFETCH */ - -#define PREF(hint, addr) -#define PREFX(hint, addr) - -#endif /* !CONFIG_CPU_HAS_PREFETCH */ - -/* - * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. - */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) -#define MOVN(rd, rs, rt) \ - .set push; \ - .set reorder; \ - beqz rt, 9f; \ - move rd, rs; \ - .set pop; \ -9: -#define MOVZ(rd, rs, rt) \ - .set push; \ - .set reorder; \ - bnez rt, 9f; \ - move rd, rs; \ - .set pop; \ -9: -#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) -#define MOVN(rd, rs, rt) \ - .set push; \ - .set noreorder; \ - bnezl rt, 9f; \ - move rd, rs; \ - .set pop; \ -9: -#define MOVZ(rd, rs, rt) \ - .set push; \ - .set noreorder; \ - beqzl rt, 9f; \ - move rd, rs; \ - .set pop; \ -9: -#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MOVN(rd, rs, rt) \ - movn rd, rs, rt -#define MOVZ(rd, rs, rt) \ - movz rd, rs, rt -#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ - -/* - * Stack alignment - */ -#if (_MIPS_SIM == _MIPS_SIM_ABI32) -#define ALSZ 7 -#define ALMASK ~7 -#endif -#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) -#define ALSZ 15 -#define ALMASK ~15 -#endif - -/* - * Macros to handle different pointer/register sizes for 32/64-bit code - */ - -/* - * Size of a register - */ -#ifdef __mips64 -#define SZREG 8 -#else -#define SZREG 4 -#endif - -/* - * Use the following macros in assemblercode to load/store registers, - * pointers etc. - */ -#if (_MIPS_SIM == _MIPS_SIM_ABI32) -#define REG_S sw -#define REG_L lw -#define REG_SUBU subu -#define REG_ADDU addu -#endif -#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) -#define REG_S sd -#define REG_L ld -#define REG_SUBU dsubu -#define REG_ADDU daddu -#endif - -/* - * How to add/sub/load/store/shift C int variables. - */ -#if (_MIPS_SZINT == 32) -#define INT_ADD add -#define INT_ADDU addu -#define INT_ADDI addi -#define INT_ADDIU addiu -#define INT_SUB sub -#define INT_SUBU subu -#define INT_L lw -#define INT_S sw -#define INT_SLL sll -#define INT_SLLV sllv -#define INT_SRL srl -#define INT_SRLV srlv -#define INT_SRA sra -#define INT_SRAV srav -#endif - -#if (_MIPS_SZINT == 64) -#define INT_ADD dadd -#define INT_ADDU daddu -#define INT_ADDI daddi -#define INT_ADDIU daddiu -#define INT_SUB dsub -#define INT_SUBU dsubu -#define INT_L ld -#define INT_S sd -#define INT_SLL dsll -#define INT_SLLV dsllv -#define INT_SRL dsrl -#define INT_SRLV dsrlv -#define INT_SRA dsra -#define INT_SRAV dsrav -#endif - -/* - * How to add/sub/load/store/shift C long variables. - */ -#if (_MIPS_SZLONG == 32) -#define LONG_ADD add -#define LONG_ADDU addu -#define LONG_ADDI addi -#define LONG_ADDIU addiu -#define LONG_SUB sub -#define LONG_SUBU subu -#define LONG_L lw -#define LONG_S sw -#define LONG_SLL sll -#define LONG_SLLV sllv -#define LONG_SRL srl -#define LONG_SRLV srlv -#define LONG_SRA sra -#define LONG_SRAV srav - -#define LONG .word -#define LONGSIZE 4 -#define LONGMASK 3 -#define LONGLOG 2 -#endif - -#if (_MIPS_SZLONG == 64) -#define LONG_ADD dadd -#define LONG_ADDU daddu -#define LONG_ADDI daddi -#define LONG_ADDIU daddiu -#define LONG_SUB dsub -#define LONG_SUBU dsubu -#define LONG_L ld -#define LONG_S sd -#define LONG_SLL dsll -#define LONG_SLLV dsllv -#define LONG_SRL dsrl -#define LONG_SRLV dsrlv -#define LONG_SRA dsra -#define LONG_SRAV dsrav - -#define LONG .dword -#define LONGSIZE 8 -#define LONGMASK 7 -#define LONGLOG 3 -#endif - -/* - * How to add/sub/load/store/shift pointers. - */ -#if (_MIPS_SZPTR == 32) -#define PTR_ADD add -#define PTR_ADDU addu -#define PTR_ADDI addi -#define PTR_ADDIU addiu -#define PTR_SUB sub -#define PTR_SUBU subu -#define PTR_L lw -#define PTR_S sw -#define PTR_LA la -#define PTR_LI li -#define PTR_SLL sll -#define PTR_SLLV sllv -#define PTR_SRL srl -#define PTR_SRLV srlv -#define PTR_SRA sra -#define PTR_SRAV srav - -#define PTR_SCALESHIFT 2 - -#define PTR .word -#define PTRSIZE 4 -#define PTRLOG 2 -#endif - -#if (_MIPS_SZPTR == 64) -#define PTR_ADD dadd -#define PTR_ADDU daddu -#define PTR_ADDI daddi -#define PTR_ADDIU daddiu -#define PTR_SUB dsub -#define PTR_SUBU dsubu -#define PTR_L ld -#define PTR_S sd -#define PTR_LA dla -#define PTR_LI dli -#define PTR_SLL dsll -#define PTR_SLLV dsllv -#define PTR_SRL dsrl -#define PTR_SRLV dsrlv -#define PTR_SRA dsra -#define PTR_SRAV dsrav - -#define PTR_SCALESHIFT 3 - -#define PTR .dword -#define PTRSIZE 8 -#define PTRLOG 3 -#endif - -/* - * Some cp0 registers were extended to 64bit for MIPS III. - */ -#if (_MIPS_SIM == _MIPS_SIM_ABI32) -#define MFC0 mfc0 -#define MTC0 mtc0 -#endif -#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) -#define MFC0 dmfc0 -#define MTC0 dmtc0 -#endif - -#define SSNOP sll zero, zero, 1 - -#ifdef CONFIG_SGI_IP28 -/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ -#include -#define R10KCBARRIER(addr) cache Cache_Barrier, addr; -#else -#define R10KCBARRIER(addr) -#endif - -#endif /* __ASM_ASM_H */ diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h deleted file mode 100644 index 2a948e8..0000000 --- a/include/asm-mips/au1x00.h +++ /dev/null @@ -1,1090 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Include file for Alchemy Semiconductor's Au1k CPU. - * - * Copyright 2000,2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - - /* - * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp - */ - -#ifndef _AU1X00_H_ -#define _AU1X00_H_ - -#ifndef __ASSEMBLY__ -/* cpu pipeline flush */ -void static inline au_sync(void) -{ - __asm__ volatile ("sync"); -} - -void static inline au_sync_udelay(int us) -{ - __asm__ volatile ("sync"); - udelay(us); -} - -void static inline au_writeb(u8 val, int reg) -{ - *(volatile u8 *)(reg) = val; -} - -void static inline au_writew(u16 val, int reg) -{ - *(volatile u16 *)(reg) = val; -} - -void static inline au_writel(u32 val, int reg) -{ - *(volatile u32 *)(reg) = val; -} - -static inline u8 au_readb(unsigned long port) -{ - return (*(volatile u8 *)port); -} - -static inline u16 au_readw(unsigned long port) -{ - return (*(volatile u16 *)port); -} - -static inline u32 au_readl(unsigned long port) -{ - return (*(volatile u32 *)port); -} - -/* These next three functions should be a generic part of the MIPS - * kernel (with the 'au_' removed from the name) and selected for - * processors that support the instructions. - * Taken from PPC tree. -- Dan - */ -/* Return the bit position of the most significant 1 bit in a word */ -static __inline__ int __ilog2(unsigned int x) -{ - int lz; - - asm volatile ( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips32\n\t" - "clz\t%0,%1\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (lz) - : "r" (x)); - - return 31 - lz; -} - -static __inline__ int au_ffz(unsigned int x) -{ - if ((x = ~x) == 0) - return 32; - return __ilog2(x & -x); -} - -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -static __inline__ int au_ffs(int x) -{ - return __ilog2(x & -x) + 1; -} - -#define gpio_set(Value) outl(Value, SYS_OUTPUTSET) -#define gpio_clear(Value) outl(Value, SYS_OUTPUTCLR) -#define gpio_read() inl(SYS_PINSTATERD) -#define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR) - -#endif /* !ASSEMBLY */ - -#ifdef CONFIG_PM -/* no CP0 timer irq */ -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) -#else -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) -#endif - -#define CP0_IWATCHLO $18,1 -#define CP0_DEBUG $23 - -/* SDRAM Controller */ -#ifdef CONFIG_SOC_AU1550 - -#define MEM_SDMODE0 0xB4000800 -#define MEM_SDMODE1 0xB4000808 -#define MEM_SDMODE2 0xB4000810 - -#define MEM_SDADDR0 0xB4000820 -#define MEM_SDADDR1 0xB4000828 -#define MEM_SDADDR2 0xB4000830 - -#define MEM_SDCONFIGA 0xB4000840 -#define MEM_SDCONFIGB 0xB4000848 -#define MEM_SDPRECMD 0xB40008c0 -#define MEM_SDAUTOREF 0xB40008c8 - -#define MEM_SDWRMD0 0xB4000880 -#define MEM_SDWRMD1 0xB4000888 -#define MEM_SDWRMD2 0xB4000890 - -#else /* CONFIG_SOC_AU1550 */ - -#define MEM_SDMODE0 0xB4000000 -#define MEM_SDMODE1 0xB4000004 -#define MEM_SDMODE2 0xB4000008 - -#define MEM_SDADDR0 0xB400000C -#define MEM_SDADDR1 0xB4000010 -#define MEM_SDADDR2 0xB4000014 - -#define MEM_SDREFCFG 0xB4000018 -#define MEM_SDPRECMD 0xB400001C -#define MEM_SDAUTOREF 0xB4000020 - -#define MEM_SDWRMD0 0xB4000024 -#define MEM_SDWRMD1 0xB4000028 -#define MEM_SDWRMD2 0xB400002C - -#endif /* CONFIG_SOC_AU1550 */ - -#define MEM_SDSLEEP 0xB4000030 -#define MEM_SDSMCKE 0xB4000034 - -/* Static Bus Controller */ -#define MEM_STCFG0 0xB4001000 -#define MEM_STTIME0 0xB4001004 -#define MEM_STADDR0 0xB4001008 - -#define MEM_STCFG1 0xB4001010 -#define MEM_STTIME1 0xB4001014 -#define MEM_STADDR1 0xB4001018 - -#define MEM_STCFG2 0xB4001020 -#define MEM_STTIME2 0xB4001024 -#define MEM_STADDR2 0xB4001028 - -#define MEM_STCFG3 0xB4001030 -#define MEM_STTIME3 0xB4001034 -#define MEM_STADDR3 0xB4001038 - -/* Interrupt Controller 0 */ -#define IC0_CFG0RD 0xB0400040 -#define IC0_CFG0SET 0xB0400040 -#define IC0_CFG0CLR 0xB0400044 - -#define IC0_CFG1RD 0xB0400048 -#define IC0_CFG1SET 0xB0400048 -#define IC0_CFG1CLR 0xB040004C - -#define IC0_CFG2RD 0xB0400050 -#define IC0_CFG2SET 0xB0400050 -#define IC0_CFG2CLR 0xB0400054 - -#define IC0_REQ0INT 0xB0400054 -#define IC0_SRCRD 0xB0400058 -#define IC0_SRCSET 0xB0400058 -#define IC0_SRCCLR 0xB040005C -#define IC0_REQ1INT 0xB040005C - -#define IC0_ASSIGNRD 0xB0400060 -#define IC0_ASSIGNSET 0xB0400060 -#define IC0_ASSIGNCLR 0xB0400064 - -#define IC0_WAKERD 0xB0400068 -#define IC0_WAKESET 0xB0400068 -#define IC0_WAKECLR 0xB040006C - -#define IC0_MASKRD 0xB0400070 -#define IC0_MASKSET 0xB0400070 -#define IC0_MASKCLR 0xB0400074 - -#define IC0_RISINGRD 0xB0400078 -#define IC0_RISINGCLR 0xB0400078 -#define IC0_FALLINGRD 0xB040007C -#define IC0_FALLINGCLR 0xB040007C - -#define IC0_TESTBIT 0xB0400080 - -/* Interrupt Controller 1 */ -#define IC1_CFG0RD 0xB1800040 -#define IC1_CFG0SET 0xB1800040 -#define IC1_CFG0CLR 0xB1800044 - -#define IC1_CFG1RD 0xB1800048 -#define IC1_CFG1SET 0xB1800048 -#define IC1_CFG1CLR 0xB180004C - -#define IC1_CFG2RD 0xB1800050 -#define IC1_CFG2SET 0xB1800050 -#define IC1_CFG2CLR 0xB1800054 - -#define IC1_REQ0INT 0xB1800054 -#define IC1_SRCRD 0xB1800058 -#define IC1_SRCSET 0xB1800058 -#define IC1_SRCCLR 0xB180005C -#define IC1_REQ1INT 0xB180005C - -#define IC1_ASSIGNRD 0xB1800060 -#define IC1_ASSIGNSET 0xB1800060 -#define IC1_ASSIGNCLR 0xB1800064 - -#define IC1_WAKERD 0xB1800068 -#define IC1_WAKESET 0xB1800068 -#define IC1_WAKECLR 0xB180006C - -#define IC1_MASKRD 0xB1800070 -#define IC1_MASKSET 0xB1800070 -#define IC1_MASKCLR 0xB1800074 - -#define IC1_RISINGRD 0xB1800078 -#define IC1_RISINGCLR 0xB1800078 -#define IC1_FALLINGRD 0xB180007C -#define IC1_FALLINGCLR 0xB180007C - -#define IC1_TESTBIT 0xB1800080 - -/* Interrupt Configuration Modes */ -#define INTC_INT_DISABLED 0 -#define INTC_INT_RISE_EDGE 0x1 -#define INTC_INT_FALL_EDGE 0x2 -#define INTC_INT_RISE_AND_FALL_EDGE 0x3 -#define INTC_INT_HIGH_LEVEL 0x5 -#define INTC_INT_LOW_LEVEL 0x6 -#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 - -/* Interrupt Numbers */ -#define AU1X00_UART0_INT 0 -#define AU1000_UART1_INT 1 /* au1000 */ -#define AU1000_UART2_INT 2 /* au1000 */ - -#define AU1500_PCI_INTA 1 /* au1500 */ -#define AU1500_PCI_INTB 2 /* au1500 */ - -#define AU1X00_UART3_INT 3 - -#define AU1000_SSI0_INT 4 /* au1000 */ -#define AU1000_SSI1_INT 5 /* au1000 */ - -#define AU1500_PCI_INTC 4 /* au1500 */ -#define AU1500_PCI_INTD 5 /* au1500 */ - -#define AU1X00_DMA_INT_BASE 6 -#define AU1X00_TOY_INT 14 -#define AU1X00_TOY_MATCH0_INT 15 -#define AU1X00_TOY_MATCH1_INT 16 -#define AU1X00_TOY_MATCH2_INT 17 -#define AU1X00_RTC_INT 18 -#define AU1X00_RTC_MATCH0_INT 19 -#define AU1X00_RTC_MATCH1_INT 20 -#define AU1X00_RTC_MATCH2_INT 21 -#define AU1000_IRDA_TX_INT 22 /* au1000 */ -#define AU1000_IRDA_RX_INT 23 /* au1000 */ -#define AU1X00_USB_DEV_REQ_INT 24 -#define AU1X00_USB_DEV_SUS_INT 25 -#define AU1X00_USB_HOST_INT 26 -#define AU1X00_ACSYNC_INT 27 -#define AU1X00_MAC0_DMA_INT 28 -#define AU1X00_MAC1_DMA_INT 29 -#define AU1X00_ETH0_IRQ AU1X00_MAC0_DMA_INT -#define AU1X00_ETH1_IRQ AU1X00_MAC1_DMA_INT -#define AU1000_I2S_UO_INT 30 /* au1000 */ -#define AU1X00_AC97C_INT 31 -#define AU1X00_LAST_INTC0_INT AU1X00_AC97C_INT -#define AU1X00_GPIO_0 32 -#define AU1X00_GPIO_1 33 -#define AU1X00_GPIO_2 34 -#define AU1X00_GPIO_3 35 -#define AU1X00_GPIO_4 36 -#define AU1X00_GPIO_5 37 -#define AU1X00_GPIO_6 38 -#define AU1X00_GPIO_7 39 -#define AU1X00_GPIO_8 40 -#define AU1X00_GPIO_9 41 -#define AU1X00_GPIO_10 42 -#define AU1X00_GPIO_11 43 -#define AU1X00_GPIO_12 44 -#define AU1X00_GPIO_13 45 -#define AU1X00_GPIO_14 46 -#define AU1X00_GPIO_15 47 - -/* Au1000 only */ -#define AU1000_GPIO_16 48 -#define AU1000_GPIO_17 49 -#define AU1000_GPIO_18 50 -#define AU1000_GPIO_19 51 -#define AU1000_GPIO_20 52 -#define AU1000_GPIO_21 53 -#define AU1000_GPIO_22 54 -#define AU1000_GPIO_23 55 -#define AU1000_GPIO_24 56 -#define AU1000_GPIO_25 57 -#define AU1000_GPIO_26 58 -#define AU1000_GPIO_27 59 -#define AU1000_GPIO_28 60 -#define AU1000_GPIO_29 61 -#define AU1000_GPIO_30 62 -#define AU1000_GPIO_31 63 - -/* Au1500 only */ -#define AU1500_GPIO_200 48 -#define AU1500_GPIO_201 49 -#define AU1500_GPIO_202 50 -#define AU1500_GPIO_203 51 -#define AU1500_GPIO_20 52 -#define AU1500_GPIO_204 53 -#define AU1500_GPIO_205 54 -#define AU1500_GPIO_23 55 -#define AU1500_GPIO_24 56 -#define AU1500_GPIO_25 57 -#define AU1500_GPIO_26 58 -#define AU1500_GPIO_27 59 -#define AU1500_GPIO_28 60 -#define AU1500_GPIO_206 61 -#define AU1500_GPIO_207 62 -#define AU1500_GPIO_208_215 63 - -#define AU1X00_MAX_INTR 63 - -#define AU1100_SD 2 -#define AU1100_GPIO_208_215 29 -/* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */ - -/* Programmable Counters 0 and 1 */ -#define SYS_BASE 0xB1900000 -#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) -#define SYS_CNTRL_E1S (1<<23) -#define SYS_CNTRL_T1S (1<<20) -#define SYS_CNTRL_M21 (1<<19) -#define SYS_CNTRL_M11 (1<<18) -#define SYS_CNTRL_M01 (1<<17) -#define SYS_CNTRL_C1S (1<<16) -#define SYS_CNTRL_BP (1<<14) -#define SYS_CNTRL_EN1 (1<<13) -#define SYS_CNTRL_BT1 (1<<12) -#define SYS_CNTRL_EN0 (1<<11) -#define SYS_CNTRL_BT0 (1<<10) -#define SYS_CNTRL_E0 (1<<8) -#define SYS_CNTRL_E0S (1<<7) -#define SYS_CNTRL_32S (1<<5) -#define SYS_CNTRL_T0S (1<<4) -#define SYS_CNTRL_M20 (1<<3) -#define SYS_CNTRL_M10 (1<<2) -#define SYS_CNTRL_M00 (1<<1) -#define SYS_CNTRL_C0S (1<<0) - -/* Programmable Counter 0 Registers */ -#define SYS_TOYTRIM (SYS_BASE + 0) -#define SYS_TOYWRITE (SYS_BASE + 4) -#define SYS_TOYMATCH0 (SYS_BASE + 8) -#define SYS_TOYMATCH1 (SYS_BASE + 0xC) -#define SYS_TOYMATCH2 (SYS_BASE + 0x10) -#define SYS_TOYREAD (SYS_BASE + 0x40) - -/* Programmable Counter 1 Registers */ -#define SYS_RTCTRIM (SYS_BASE + 0x44) -#define SYS_RTCWRITE (SYS_BASE + 0x48) -#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) -#define SYS_RTCMATCH1 (SYS_BASE + 0x50) -#define SYS_RTCMATCH2 (SYS_BASE + 0x54) -#define SYS_RTCREAD (SYS_BASE + 0x58) - -/* I2S Controller */ -#define I2S_DATA 0xB1000000 -#define I2S_DATA_MASK (0xffffff) -#define I2S_CONFIG 0xB1000004 -#define I2S_CONFIG_XU (1<<25) -#define I2S_CONFIG_XO (1<<24) -#define I2S_CONFIG_RU (1<<23) -#define I2S_CONFIG_RO (1<<22) -#define I2S_CONFIG_TR (1<<21) -#define I2S_CONFIG_TE (1<<20) -#define I2S_CONFIG_TF (1<<19) -#define I2S_CONFIG_RR (1<<18) -#define I2S_CONFIG_RE (1<<17) -#define I2S_CONFIG_RF (1<<16) -#define I2S_CONFIG_PD (1<<11) -#define I2S_CONFIG_LB (1<<10) -#define I2S_CONFIG_IC (1<<9) -#define I2S_CONFIG_FM_BIT 7 -#define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) -#define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) -#define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) -#define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) -#define I2S_CONFIG_TN (1<<6) -#define I2S_CONFIG_RN (1<<5) -#define I2S_CONFIG_SZ_BIT 0 -#define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) - -#define I2S_CONTROL 0xB1000008 -#define I2S_CONTROL_D (1<<1) -#define I2S_CONTROL_CE (1<<0) - -/* USB Host Controller */ -/* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */ -#define USB_OHCI_BASE 0x10100000 -#define USB_OHCI_LEN 0x00100000 -#define USB_HOST_CONFIG 0xB017fffc - -/* USB Device Controller */ -#define USBD_EP0RD 0xB0200000 -#define USBD_EP0WR 0xB0200004 -#define USBD_EP2WR 0xB0200008 -#define USBD_EP3WR 0xB020000C -#define USBD_EP4RD 0xB0200010 -#define USBD_EP5RD 0xB0200014 -#define USBD_INTEN 0xB0200018 -#define USBD_INTSTAT 0xB020001C -#define USBDEV_INT_SOF (1<<12) -#define USBDEV_INT_HF_BIT 6 -#define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) -#define USBDEV_INT_CMPLT_BIT 0 -#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) -#define USBD_CONFIG 0xB0200020 -#define USBD_EP0CS 0xB0200024 -#define USBD_EP2CS 0xB0200028 -#define USBD_EP3CS 0xB020002C -#define USBD_EP4CS 0xB0200030 -#define USBD_EP5CS 0xB0200034 -#define USBDEV_CS_SU (1<<14) -#define USBDEV_CS_NAK (1<<13) -#define USBDEV_CS_ACK (1<<12) -#define USBDEV_CS_BUSY (1<<11) -#define USBDEV_CS_TSIZE_BIT 1 -#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) -#define USBDEV_CS_STALL (1<<0) -#define USBD_EP0RDSTAT 0xB0200040 -#define USBD_EP0WRSTAT 0xB0200044 -#define USBD_EP2WRSTAT 0xB0200048 -#define USBD_EP3WRSTAT 0xB020004C -#define USBD_EP4RDSTAT 0xB0200050 -#define USBD_EP5RDSTAT 0xB0200054 -#define USBDEV_FSTAT_FLUSH (1<<6) -#define USBDEV_FSTAT_UF (1<<5) -#define USBDEV_FSTAT_OF (1<<4) -#define USBDEV_FSTAT_FCNT_BIT 0 -#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) -#define USBD_ENABLE 0xB0200058 -#define USBDEV_ENABLE (1<<1) -#define USBDEV_CE (1<<0) - -/* Ethernet Controllers */ -#define AU1000_ETH0_BASE 0xB0500000 -#define AU1000_ETH1_BASE 0xB0510000 -#define AU1500_ETH0_BASE 0xB1500000 -#define AU1500_ETH1_BASE 0xB1510000 -#define AU1100_ETH0_BASE 0xB0500000 -#define AU1550_ETH0_BASE 0xB0500000 -#define AU1550_ETH1_BASE 0xB0510000 - -/* 4 byte offsets from AU1000_ETH_BASE */ -#define MAC_CONTROL 0x0 -#define MAC_RX_ENABLE (1<<2) -#define MAC_TX_ENABLE (1<<3) -#define MAC_DEF_CHECK (1<<5) -#define MAC_SET_BL(X) (((X)&0x3)<<6) -#define MAC_AUTO_PAD (1<<8) -#define MAC_DISABLE_RETRY (1<<10) -#define MAC_DISABLE_BCAST (1<<11) -#define MAC_LATE_COL (1<<12) -#define MAC_HASH_MODE (1<<13) -#define MAC_HASH_ONLY (1<<15) -#define MAC_PASS_ALL (1<<16) -#define MAC_INVERSE_FILTER (1<<17) -#define MAC_PROMISCUOUS (1<<18) -#define MAC_PASS_ALL_MULTI (1<<19) -#define MAC_FULL_DUPLEX (1<<20) -#define MAC_NORMAL_MODE 0 -#define MAC_INT_LOOPBACK (1<<21) -#define MAC_EXT_LOOPBACK (1<<22) -#define MAC_DISABLE_RX_OWN (1<<23) -#define MAC_BIG_ENDIAN (1<<30) -#define MAC_RX_ALL (1<<31) -#define MAC_ADDRESS_HIGH 0x4 -#define MAC_ADDRESS_LOW 0x8 -#define MAC_MCAST_HIGH 0xC -#define MAC_MCAST_LOW 0x10 -#define MAC_MII_CNTRL 0x14 -#define MAC_MII_BUSY (1<<0) -#define MAC_MII_READ 0 -#define MAC_MII_WRITE (1<<1) -#define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) -#define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) -#define MAC_MII_DATA 0x18 -#define MAC_FLOW_CNTRL 0x1C -#define MAC_FLOW_CNTRL_BUSY (1<<0) -#define MAC_FLOW_CNTRL_ENABLE (1<<1) -#define MAC_PASS_CONTROL (1<<2) -#define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) -#define MAC_VLAN1_TAG 0x20 -#define MAC_VLAN2_TAG 0x24 - -/* Ethernet Controller Enable */ -#define AU1000_MAC0_ENABLE 0xB0520000 -#define AU1000_MAC1_ENABLE 0xB0520004 -#define AU1500_MAC0_ENABLE 0xB1520000 -#define AU1500_MAC1_ENABLE 0xB1520004 -#define AU1100_MAC0_ENABLE 0xB0520000 -#define AU1550_MAC0_ENABLE 0xB0520000 -#define AU1550_MAC1_ENABLE 0xB0520004 - -#define MAC_EN_CLOCK_ENABLE (1<<0) -#define MAC_EN_RESET0 (1<<1) -#define MAC_EN_TOSS (0<<2) -#define MAC_EN_CACHEABLE (1<<3) -#define MAC_EN_RESET1 (1<<4) -#define MAC_EN_RESET2 (1<<5) -#define MAC_DMA_RESET (1<<6) - -/* Ethernet Controller DMA Channels */ - -#define MAC0_TX_DMA_ADDR 0xB4004000 -#define MAC1_TX_DMA_ADDR 0xB4004200 -/* offsets from MAC_TX_RING_ADDR address */ -#define MAC_TX_BUFF0_STATUS 0x0 -#define TX_FRAME_ABORTED (1<<0) -#define TX_JAB_TIMEOUT (1<<1) -#define TX_NO_CARRIER (1<<2) -#define TX_LOSS_CARRIER (1<<3) -#define TX_EXC_DEF (1<<4) -#define TX_LATE_COLL_ABORT (1<<5) -#define TX_EXC_COLL (1<<6) -#define TX_UNDERRUN (1<<7) -#define TX_DEFERRED (1<<8) -#define TX_LATE_COLL (1<<9) -#define TX_COLL_CNT_MASK (0xF<<10) -#define TX_PKT_RETRY (1<<31) -#define MAC_TX_BUFF0_ADDR 0x4 -#define TX_DMA_ENABLE (1<<0) -#define TX_T_DONE (1<<1) -#define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) -#define MAC_TX_BUFF0_LEN 0x8 -#define MAC_TX_BUFF1_STATUS 0x10 -#define MAC_TX_BUFF1_ADDR 0x14 -#define MAC_TX_BUFF1_LEN 0x18 -#define MAC_TX_BUFF2_STATUS 0x20 -#define MAC_TX_BUFF2_ADDR 0x24 -#define MAC_TX_BUFF2_LEN 0x28 -#define MAC_TX_BUFF3_STATUS 0x30 -#define MAC_TX_BUFF3_ADDR 0x34 -#define MAC_TX_BUFF3_LEN 0x38 - -#define MAC0_RX_DMA_ADDR 0xB4004100 -#define MAC1_RX_DMA_ADDR 0xB4004300 -/* offsets from MAC_RX_RING_ADDR */ -#define MAC_RX_BUFF0_STATUS 0x0 -#define RX_FRAME_LEN_MASK 0x3fff -#define RX_WDOG_TIMER (1<<14) -#define RX_RUNT (1<<15) -#define RX_OVERLEN (1<<16) -#define RX_COLL (1<<17) -#define RX_ETHER (1<<18) -#define RX_MII_ERROR (1<<19) -#define RX_DRIBBLING (1<<20) -#define RX_CRC_ERROR (1<<21) -#define RX_VLAN1 (1<<22) -#define RX_VLAN2 (1<<23) -#define RX_LEN_ERROR (1<<24) -#define RX_CNTRL_FRAME (1<<25) -#define RX_U_CNTRL_FRAME (1<<26) -#define RX_MCAST_FRAME (1<<27) -#define RX_BCAST_FRAME (1<<28) -#define RX_FILTER_FAIL (1<<29) -#define RX_PACKET_FILTER (1<<30) -#define RX_MISSED_FRAME (1<<31) - -#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ - RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ - RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) -#define MAC_RX_BUFF0_ADDR 0x4 -#define RX_DMA_ENABLE (1<<0) -#define RX_T_DONE (1<<1) -#define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) -#define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) -#define MAC_RX_BUFF1_STATUS 0x10 -#define MAC_RX_BUFF1_ADDR 0x14 -#define MAC_RX_BUFF2_STATUS 0x20 -#define MAC_RX_BUFF2_ADDR 0x24 -#define MAC_RX_BUFF3_STATUS 0x30 -#define MAC_RX_BUFF3_ADDR 0x34 - - -/* UARTS 0-3 */ -#define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 -#define UART2_ADDR 0xB1300000 -#define UART3_ADDR 0xB1400000 -#define UART_BASE UART0_ADDR -#define UART_DEBUG_BASE UART2_ADDR - -#define UART_RX 0 /* Receive buffer */ -#define UART_TX 4 /* Transmit buffer */ -#define UART_IER 8 /* Interrupt Enable Register */ -#define UART_IIR 0xC /* Interrupt ID Register */ -#define UART_FCR 0x10 /* FIFO Control Register */ -#define UART_LCR 0x14 /* Line Control Register */ -#define UART_MCR 0x18 /* Modem Control Register */ -#define UART_LSR 0x1C /* Line Status Register */ -#define UART_MSR 0x20 /* Modem Status Register */ -#define UART_CLK 0x28 /* Baud Rate Clock Divider */ -#define UART_ENABLE 0x100 /* Uart enable */ - -#define UART_EN_CE 1 /* Clock enable */ -#define UART_EN_E 2 /* Enable */ - -#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ -#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ -#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ -#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ -#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ -#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ -#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ -#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ -#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ -#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ - -/* - * These are the definitions for the Line Control Register - */ -#define UART_LCR_SBC 0x40 /* Set break control */ -#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ -#define UART_LCR_EPAR 0x10 /* Even parity select */ -#define UART_LCR_PARITY 0x08 /* Parity Enable */ -#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ -#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ -#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ -#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ -#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ - -/* - * These are the definitions for the Line Status Register - */ -#define UART_LSR_TEMT 0x40 /* Transmitter empty */ -#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ -#define UART_LSR_BI 0x10 /* Break interrupt indicator */ -#define UART_LSR_FE 0x08 /* Frame error indicator */ -#define UART_LSR_PE 0x04 /* Parity error indicator */ -#define UART_LSR_OE 0x02 /* Overrun error indicator */ -#define UART_LSR_DR 0x01 /* Receiver data ready */ - -/* - * These are the definitions for the Interrupt Identification Register - */ -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ -#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ - -/* - * These are the definitions for the Interrupt Enable Register - */ -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ - -/* - * These are the definitions for the Modem Control Register - */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ -#define UART_MCR_OUT2 0x08 /* Out2 complement */ -#define UART_MCR_OUT1 0x04 /* Out1 complement */ -#define UART_MCR_RTS 0x02 /* RTS complement */ -#define UART_MCR_DTR 0x01 /* DTR complement */ - -/* - * These are the definitions for the Modem Status Register - */ -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ -#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ - - -/* SSIO */ -#define SSI0_STATUS 0xB1600000 -#define SSI_STATUS_BF (1<<4) -#define SSI_STATUS_OF (1<<3) -#define SSI_STATUS_UF (1<<2) -#define SSI_STATUS_D (1<<1) -#define SSI_STATUS_B (1<<0) -#define SSI0_INT 0xB1600004 -#define SSI_INT_OI (1<<3) -#define SSI_INT_UI (1<<2) -#define SSI_INT_DI (1<<1) -#define SSI0_INT_ENABLE 0xB1600008 -#define SSI_INTE_OIE (1<<3) -#define SSI_INTE_UIE (1<<2) -#define SSI_INTE_DIE (1<<1) -#define SSI0_CONFIG 0xB1600020 -#define SSI_CONFIG_AO (1<<24) -#define SSI_CONFIG_DO (1<<23) -#define SSI_CONFIG_ALEN_BIT 20 -#define SSI_CONFIG_ALEN_MASK (0x7<<20) -#define SSI_CONFIG_DLEN_BIT 16 -#define SSI_CONFIG_DLEN_MASK (0x7<<16) -#define SSI_CONFIG_DD (1<<11) -#define SSI_CONFIG_AD (1<<10) -#define SSI_CONFIG_BM_BIT 8 -#define SSI_CONFIG_BM_MASK (0x3<<8) -#define SSI_CONFIG_CE (1<<7) -#define SSI_CONFIG_DP (1<<6) -#define SSI_CONFIG_DL (1<<5) -#define SSI_CONFIG_EP (1<<4) -#define SSI0_ADATA 0xB1600024 -#define SSI_AD_D (1<<24) -#define SSI_AD_ADDR_BIT 16 -#define SSI_AD_ADDR_MASK (0xff<<16) -#define SSI_AD_DATA_BIT 0 -#define SSI_AD_DATA_MASK (0xfff<<0) -#define SSI0_CLKDIV 0xB1600028 -#define SSI0_CONTROL 0xB1600100 -#define SSI_CONTROL_CD (1<<1) -#define SSI_CONTROL_E (1<<0) - -/* SSI1 */ -#define SSI1_STATUS 0xB1680000 -#define SSI1_INT 0xB1680004 -#define SSI1_INT_ENABLE 0xB1680008 -#define SSI1_CONFIG 0xB1680020 -#define SSI1_ADATA 0xB1680024 -#define SSI1_CLKDIV 0xB1680028 -#define SSI1_ENABLE 0xB1680100 - -/* - * Register content definitions - */ -#define SSI_STATUS_BF (1<<4) -#define SSI_STATUS_OF (1<<3) -#define SSI_STATUS_UF (1<<2) -#define SSI_STATUS_D (1<<1) -#define SSI_STATUS_B (1<<0) - -/* SSI_INT */ -#define SSI_INT_OI (1<<3) -#define SSI_INT_UI (1<<2) -#define SSI_INT_DI (1<<1) - -/* SSI_INTEN */ -#define SSI_INTEN_OIE (1<<3) -#define SSI_INTEN_UIE (1<<2) -#define SSI_INTEN_DIE (1<<1) - -#define SSI_CONFIG_AO (1<<24) -#define SSI_CONFIG_DO (1<<23) -#define SSI_CONFIG_ALEN (7<<20) -#define SSI_CONFIG_DLEN (15<<16) -#define SSI_CONFIG_DD (1<<11) -#define SSI_CONFIG_AD (1<<10) -#define SSI_CONFIG_BM (3<<8) -#define SSI_CONFIG_CE (1<<7) -#define SSI_CONFIG_DP (1<<6) -#define SSI_CONFIG_DL (1<<5) -#define SSI_CONFIG_EP (1<<4) -#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) -#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) -#define SSI_CONFIG_BM_HI (0<<8) -#define SSI_CONFIG_BM_LO (1<<8) -#define SSI_CONFIG_BM_CY (2<<8) - -#define SSI_ADATA_D (1<<24) -#define SSI_ADATA_ADDR (0xFF<<16) -#define SSI_ADATA_DATA (0x0FFF) -#define SSI_ADATA_ADDR_N(N) (N<<16) - -#define SSI_ENABLE_CD (1<<1) -#define SSI_ENABLE_E (1<<0) - - -/* IrDA Controller */ -#define IRDA_BASE 0xB0300000 -#define IR_RING_PTR_STATUS (IRDA_BASE+0x00) -#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) -#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) -#define IR_RING_SIZE (IRDA_BASE+0x0C) -#define IR_RING_PROMPT (IRDA_BASE+0x10) -#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) -#define IR_INT_CLEAR (IRDA_BASE+0x18) -#define IR_CONFIG_1 (IRDA_BASE+0x20) -#define IR_RX_INVERT_LED (1<<0) -#define IR_TX_INVERT_LED (1<<1) -#define IR_ST (1<<2) -#define IR_SF (1<<3) -#define IR_SIR (1<<4) -#define IR_MIR (1<<5) -#define IR_FIR (1<<6) -#define IR_16CRC (1<<7) -#define IR_TD (1<<8) -#define IR_RX_ALL (1<<9) -#define IR_DMA_ENABLE (1<<10) -#define IR_RX_ENABLE (1<<11) -#define IR_TX_ENABLE (1<<12) -#define IR_LOOPBACK (1<<14) -#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ - IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) -#define IR_SIR_FLAGS (IRDA_BASE+0x24) -#define IR_ENABLE (IRDA_BASE+0x28) -#define IR_RX_STATUS (1<<9) -#define IR_TX_STATUS (1<<10) -#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) -#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) -#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) -#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) -#define IR_CONFIG_2 (IRDA_BASE+0x3C) -#define IR_MODE_INV (1<<0) -#define IR_ONE_PIN (1<<1) -#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) - -/* GPIO */ -#define SYS_PINFUNC 0xB190002C -#define SYS_PF_USB (1<<15) /* 2nd USB device/host */ -#define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ -#define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ -#define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ -#define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ -#define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ -#define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ -#define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ -#define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ -#define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ -#define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ -#define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ -#define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ -#define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ -#define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ -#define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ -#define SYS_TRIOUTRD 0xB1900100 -#define SYS_TRIOUTCLR 0xB1900100 -#define SYS_OUTPUTRD 0xB1900108 -#define SYS_OUTPUTSET 0xB1900108 -#define SYS_OUTPUTCLR 0xB190010C -#define SYS_PINSTATERD 0xB1900110 -#define SYS_PININPUTEN 0xB1900110 - -/* GPIO2, Au1500 only */ -#define GPIO2_BASE 0xB1700000 -#define GPIO2_DIR (GPIO2_BASE + 0) -#define GPIO2_DATA_EN (GPIO2_BASE + 8) -#define GPIO2_PIN_STATE (GPIO2_BASE + 0xC) -#define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10) -#define GPIO2_ENABLE (GPIO2_BASE + 0x14) - -/* Power Management */ -#define SYS_SCRATCH0 0xB1900018 -#define SYS_SCRATCH1 0xB190001C -#define SYS_WAKEMSK 0xB1900034 -#define SYS_ENDIAN 0xB1900038 -#define SYS_POWERCTRL 0xB190003C -#define SYS_WAKESRC 0xB190005C -#define SYS_SLPPWR 0xB1900078 -#define SYS_SLEEP 0xB190007C - -/* Clock Controller */ -#define SYS_FREQCTRL0 0xB1900020 -#define SYS_FC_FRDIV2_BIT 22 -#define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT) -#define SYS_FC_FE2 (1<<21) -#define SYS_FC_FS2 (1<<20) -#define SYS_FC_FRDIV1_BIT 12 -#define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT) -#define SYS_FC_FE1 (1<<11) -#define SYS_FC_FS1 (1<<10) -#define SYS_FC_FRDIV0_BIT 2 -#define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT) -#define SYS_FC_FE0 (1<<1) -#define SYS_FC_FS0 (1<<0) -#define SYS_FREQCTRL1 0xB1900024 -#define SYS_FC_FRDIV5_BIT 22 -#define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT) -#define SYS_FC_FE5 (1<<21) -#define SYS_FC_FS5 (1<<20) -#define SYS_FC_FRDIV4_BIT 12 -#define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT) -#define SYS_FC_FE4 (1<<11) -#define SYS_FC_FS4 (1<<10) -#define SYS_FC_FRDIV3_BIT 2 -#define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT) -#define SYS_FC_FE3 (1<<1) -#define SYS_FC_FS3 (1<<0) -#define SYS_CLKSRC 0xB1900028 -#define SYS_CS_ME1_BIT 27 -#define SYS_CS_ME1_MASK (0x7< -#include /* sigh ... */ - -#ifdef __KERNEL__ - -#include -#include -#include - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -/* - * Only disable interrupt for kernel mode stuff to keep usermode stuff - * that dares to use kernel include files alive. - */ -#define __bi_flags unsigned long flags -#define __bi_cli() __cli() -#define __bi_save_flags(x) __save_flags(x) -#define __bi_save_and_cli(x) __save_and_cli(x) -#define __bi_restore_flags(x) __restore_flags(x) -#else -#define __bi_flags -#define __bi_cli() -#define __bi_save_flags(x) -#define __bi_save_and_cli(x) -#define __bi_restore_flags(x) -#endif /* __KERNEL__ */ - -#ifdef CONFIG_CPU_HAS_LLSC - -#include - -/* - * These functions for MIPS ISA > 1 are interrupt and SMP proof and - * interrupt friendly - */ - -/* - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static __inline__ void -set_bit(int nr, volatile void *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); - unsigned long temp; - - __asm__ __volatile__( - "1:\tll\t%0, %1\t\t# set_bit\n\t" - "or\t%0, %2\n\t" - "sc\t%0, %1\n\t" - "beqz\t%0, 1b" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << (nr & 0x1f)), "m" (*m)); -} - -/* - * __set_bit - Set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike set_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static __inline__ void __set_bit(int nr, volatile void * addr) -{ - unsigned long * m = ((unsigned long *) addr) + (nr >> 5); - - *m |= 1UL << (nr & 31); -} -#define PLATFORM__SET_BIT - -/* - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() - * in order to ensure changes are visible on other processors. - */ -static __inline__ void -clear_bit(int nr, volatile void *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); - unsigned long temp; - - __asm__ __volatile__( - "1:\tll\t%0, %1\t\t# clear_bit\n\t" - "and\t%0, %2\n\t" - "sc\t%0, %1\n\t" - "beqz\t%0, 1b\n\t" - : "=&r" (temp), "=m" (*m) - : "ir" (~(1UL << (nr & 0x1f))), "m" (*m)); -} - -/* - * change_bit - Toggle a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static __inline__ void -change_bit(int nr, volatile void *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); - unsigned long temp; - - __asm__ __volatile__( - "1:\tll\t%0, %1\t\t# change_bit\n\t" - "xor\t%0, %2\n\t" - "sc\t%0, %1\n\t" - "beqz\t%0, 1b" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << (nr & 0x1f)), "m" (*m)); -} - -/* - * __change_bit - Toggle a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike change_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static __inline__ void __change_bit(int nr, volatile void * addr) -{ - unsigned long * m = ((unsigned long *) addr) + (nr >> 5); - - *m ^= 1UL << (nr & 31); -} - -/* - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static __inline__ int -test_and_set_bit(int nr, volatile void *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); - unsigned long temp, res; - - __asm__ __volatile__( - ".set\tnoreorder\t\t# test_and_set_bit\n" - "1:\tll\t%0, %1\n\t" - "or\t%2, %0, %3\n\t" - "sc\t%2, %1\n\t" - "beqz\t%2, 1b\n\t" - " and\t%2, %0, %3\n\t" - ".set\treorder" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << (nr & 0x1f)), "m" (*m) - : "memory"); - - return res != 0; -} - -/* - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static __inline__ int __test_and_set_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a |= mask; - - return retval; -} - -/* - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static __inline__ int -test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); - unsigned long temp, res; - - __asm__ __volatile__( - ".set\tnoreorder\t\t# test_and_clear_bit\n" - "1:\tll\t%0, %1\n\t" - "or\t%2, %0, %3\n\t" - "xor\t%2, %3\n\t" - "sc\t%2, %1\n\t" - "beqz\t%2, 1b\n\t" - " and\t%2, %0, %3\n\t" - ".set\treorder" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << (nr & 0x1f)), "m" (*m) - : "memory"); - - return res != 0; -} - -/* - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static __inline__ int __test_and_clear_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a &= ~mask; - - return retval; -} - -/* - * test_and_change_bit - Change a bit and return its new value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static __inline__ int -test_and_change_bit(int nr, volatile void *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); - unsigned long temp, res; - - __asm__ __volatile__( - ".set\tnoreorder\t\t# test_and_change_bit\n" - "1:\tll\t%0, %1\n\t" - "xor\t%2, %0, %3\n\t" - "sc\t%2, %1\n\t" - "beqz\t%2, 1b\n\t" - " and\t%2, %0, %3\n\t" - ".set\treorder" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << (nr & 0x1f)), "m" (*m) - : "memory"); - - return res != 0; -} - -/* - * __test_and_change_bit - Change a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static __inline__ int __test_and_change_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a ^= mask; - - return retval; -} - -#else /* MIPS I */ - -/* - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static __inline__ void set_bit(int nr, volatile void * addr) -{ - int mask; - volatile int *a = addr; - __bi_flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - __bi_save_and_cli(flags); - *a |= mask; - __bi_restore_flags(flags); -} - -/* - * __set_bit - Set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike set_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static __inline__ void __set_bit(int nr, volatile void * addr) -{ - int mask; - volatile int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a |= mask; -} - -/* - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() - * in order to ensure changes are visible on other processors. - */ -static __inline__ void clear_bit(int nr, volatile void * addr) -{ - int mask; - volatile int *a = addr; - __bi_flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - __bi_save_and_cli(flags); - *a &= ~mask; - __bi_restore_flags(flags); -} - -/* - * change_bit - Toggle a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static __inline__ void change_bit(int nr, volatile void * addr) -{ - int mask; - volatile int *a = addr; - __bi_flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - __bi_save_and_cli(flags); - *a ^= mask; - __bi_restore_flags(flags); -} - -/* - * __change_bit - Toggle a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike change_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static __inline__ void __change_bit(int nr, volatile void * addr) -{ - unsigned long * m = ((unsigned long *) addr) + (nr >> 5); - - *m ^= 1UL << (nr & 31); -} - -/* - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static __inline__ int test_and_set_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile int *a = addr; - __bi_flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - __bi_save_and_cli(flags); - retval = (mask & *a) != 0; - *a |= mask; - __bi_restore_flags(flags); - - return retval; -} - -/* - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static __inline__ int __test_and_set_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a |= mask; - - return retval; -} - -/* - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static __inline__ int test_and_clear_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile int *a = addr; - __bi_flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - __bi_save_and_cli(flags); - retval = (mask & *a) != 0; - *a &= ~mask; - __bi_restore_flags(flags); - - return retval; -} - -/* - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static __inline__ int __test_and_clear_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a &= ~mask; - - return retval; -} - -/* - * test_and_change_bit - Change a bit and return its new value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static __inline__ int test_and_change_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile int *a = addr; - __bi_flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - __bi_save_and_cli(flags); - retval = (mask & *a) != 0; - *a ^= mask; - __bi_restore_flags(flags); - - return retval; -} - -/* - * __test_and_change_bit - Change a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static __inline__ int __test_and_change_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a ^= mask; - - return retval; -} - -#undef __bi_flags -#undef __bi_cli -#undef __bi_save_flags -#undef __bi_restore_flags - -#endif /* MIPS I */ - -/* - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static __inline__ int test_bit(int nr, volatile void *addr) -{ - return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0; -} - -#ifndef __MIPSEB__ - -/* Little endian versions. */ - -/* - * find_first_zero_bit - find the first zero bit in a memory region - * @addr: The address to start the search at - * @size: The maximum size to search - * - * Returns the bit-number of the first zero bit, not the number of the byte - * containing a bit. - */ -static __inline__ int find_first_zero_bit (void *addr, unsigned size) -{ - unsigned long dummy; - int res; - - if (!size) - return 0; - - __asm__ (".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tsubu\t$1,%6,%0\n\t" - "blez\t$1,2f\n\t" - "lw\t$1,(%5)\n\t" - "addiu\t%5,4\n\t" -#if (_MIPS_ISA == _MIPS_ISA_MIPS2 ) || (_MIPS_ISA == _MIPS_ISA_MIPS3 ) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5 ) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) - "beql\t%1,$1,1b\n\t" - "addiu\t%0,32\n\t" -#else - "addiu\t%0,32\n\t" - "beq\t%1,$1,1b\n\t" - "nop\n\t" - "subu\t%0,32\n\t" -#endif -#ifdef __MIPSEB__ -#error "Fix this for big endian" -#endif /* __MIPSEB__ */ - "li\t%1,1\n" - "1:\tand\t%2,$1,%1\n\t" - "beqz\t%2,2f\n\t" - "sll\t%1,%1,1\n\t" - "bnez\t%1,1b\n\t" - "add\t%0,%0,1\n\t" - ".set\tat\n\t" - ".set\treorder\n" - "2:" - : "=r" (res), "=r" (dummy), "=r" (addr) - : "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff), - "2" (addr), "r" (size) - : "$1"); - - return res; -} - -/* - * find_next_zero_bit - find the first zero bit in a memory region - * @addr: The address to base the search on - * @offset: The bitnumber to start searching at - * @size: The maximum size to search - */ -static __inline__ int find_next_zero_bit (void * addr, int size, int offset) -{ - unsigned int *p = ((unsigned int *) addr) + (offset >> 5); - int set = 0, bit = offset & 31, res; - unsigned long dummy; - - if (bit) { - /* - * Look for zero in first byte - */ -#ifdef __MIPSEB__ -#error "Fix this for big endian byte order" -#endif - __asm__(".set\tnoreorder\n\t" - ".set\tnoat\n" - "1:\tand\t$1,%4,%1\n\t" - "beqz\t$1,1f\n\t" - "sll\t%1,%1,1\n\t" - "bnez\t%1,1b\n\t" - "addiu\t%0,1\n\t" - ".set\tat\n\t" - ".set\treorder\n" - "1:" - : "=r" (set), "=r" (dummy) - : "0" (0), "1" (1 << bit), "r" (*p) - : "$1"); - if (set < (32 - bit)) - return set + offset; - set = 32 - bit; - p++; - } - /* - * No zero yet, search remaining full bytes for a zero - */ - res = find_first_zero_bit(p, size - 32 * (p - (unsigned int *) addr)); - return offset + set + res; -} - -#endif /* !(__MIPSEB__) */ - -/* - * ffz - find first zero in word. - * @word: The word to search - * - * Undefined if no zero exists, so code should check against ~0UL first. - */ -static __inline__ unsigned long ffz(unsigned long word) -{ - unsigned int __res; - unsigned int mask = 1; - - __asm__ ( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "move\t%0,$0\n" - "1:\tand\t$1,%2,%1\n\t" - "beqz\t$1,2f\n\t" - "sll\t%1,1\n\t" - "bnez\t%1,1b\n\t" - "addiu\t%0,1\n\t" - ".set\tat\n\t" - ".set\treorder\n" - "2:\n\t" - : "=&r" (__res), "=r" (mask) - : "r" (word), "1" (mask) - : "$1"); - - return __res; -} - -#ifdef __KERNEL__ - -/* - * hweightN - returns the hamming weight of a N-bit word - * @x: the word to weigh - * - * The Hamming Weight of a number is the total number of bits set in it. - */ - -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) - -#endif /* __KERNEL__ */ - -#ifdef __MIPSEB__ -/* - * find_next_zero_bit - find the first zero bit in a memory region - * @addr: The address to base the search on - * @offset: The bitnumber to start searching at - * @size: The maximum size to search - */ -static __inline__ int find_next_zero_bit(void *addr, int size, int offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (32-offset); - if (size < 32) - goto found_first; - if (~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while (size & ~31UL) { - if (~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; - -found_first: - tmp |= ~0UL << size; -found_middle: - return result + ffz(tmp); -} - -/* Linus sez that gcc can optimize the following correctly, we'll see if this - * holds on the Sparc as it does for the ALPHA. - */ - -#if 0 /* Fool kernel-doc since it doesn't do macros yet */ -/* - * find_first_zero_bit - find the first zero bit in a memory region - * @addr: The address to start the search at - * @size: The maximum size to search - * - * Returns the bit-number of the first zero bit, not the number of the byte - * containing a bit. - */ -static int find_first_zero_bit (void *addr, unsigned size); -#endif - -#define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) - -#endif /* (__MIPSEB__) */ - -/* Now for the ext2 filesystem bit operations and helper routines. */ - -#ifdef __MIPSEB__ -static __inline__ int ext2_set_bit(int nr, void * addr) -{ - int mask, retval, flags; - unsigned char *ADDR = (unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - save_and_cli(flags); - retval = (mask & *ADDR) != 0; - *ADDR |= mask; - restore_flags(flags); - return retval; -} - -static __inline__ int ext2_clear_bit(int nr, void * addr) -{ - int mask, retval, flags; - unsigned char *ADDR = (unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - save_and_cli(flags); - retval = (mask & *ADDR) != 0; - *ADDR &= ~mask; - restore_flags(flags); - return retval; -} - -static __inline__ int ext2_test_bit(int nr, const void * addr) -{ - int mask; - const unsigned char *ADDR = (const unsigned char *) addr; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - return ((mask & *ADDR) != 0); -} - -#define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) - -static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if(offset) { - /* We hold the little endian value in tmp, but then the - * shift is illegal. So we could keep a big endian value - * in tmp, like this: - * - * tmp = __swab32(*(p++)); - * tmp |= ~0UL >> (32-offset); - * - * but this would decrease preformance, so we change the - * shift: - */ - tmp = *(p++); - tmp |= __swab32(~0UL >> (32-offset)); - if(size < 32) - goto found_first; - if(~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while(size & ~31UL) { - if(~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if(!size) - return result; - tmp = *p; - -found_first: - /* tmp is little endian, so we would have to swab the shift, - * see above. But then we have to swab tmp below for ffz, so - * we might as well do this here. - */ - return result + ffz(__swab32(tmp) | (~0UL << size)); -found_middle: - return result + ffz(__swab32(tmp)); -} -#else /* !(__MIPSEB__) */ - -/* Native ext2 byte ordering, just collapse using defines. */ -#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr)) -#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr)) -#define ext2_test_bit(nr, addr) test_bit((nr), (addr)) -#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size)) -#define ext2_find_next_zero_bit(addr, size, offset) \ - find_next_zero_bit((addr), (size), (offset)) - -#endif /* !(__MIPSEB__) */ - -/* - * Bitmap functions for the minix filesystem. - * FIXME: These assume that Minix uses the native byte/bitorder. - * This limits the Minix filesystem's value for data exchange very much. - */ -#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -#endif /* _ASM_BITOPS_H */ diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h deleted file mode 100644 index b5e685f..0000000 --- a/include/asm-mips/byteorder.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 99, 2003 by Ralf Baechle - */ -#ifndef _ASM_BYTEORDER_H -#define _ASM_BYTEORDER_H - -#include - -#ifdef __GNUC__ - -#ifdef CONFIG_CPU_MIPSR2 - -static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) -{ - __asm__( - " wsbh %0, %1 \n" - : "=r" (x) - : "r" (x)); - - return x; -} -#define __arch__swab16(x) ___arch__swab16(x) - -static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) -{ - __asm__( - " wsbh %0, %1 \n" - " rotr %0, %0, 16 \n" - : "=r" (x) - : "r" (x)); - - return x; -} -#define __arch__swab32(x) ___arch__swab32(x) - -#ifdef CONFIG_CPU_MIPS64_R2 - -static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) -{ - __asm__( - " dsbh %0, %1 \n" - " dshd %0, %0 \n" - " drotr %0, %0, 32 \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -#define __arch__swab64(x) ___arch__swab64(x) - -#endif /* CONFIG_CPU_MIPS64_R2 */ - -#endif /* CONFIG_CPU_MIPSR2 */ - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#if defined(__MIPSEB__) -# include -#elif defined(__MIPSEL__) -# include -#else -# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" -#endif - -#endif /* _ASM_BYTEORDER_H */ diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h deleted file mode 100644 index f3ce721..0000000 --- a/include/asm-mips/cachectl.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996 by Ralf Baechle - */ -#ifndef _ASM_CACHECTL -#define _ASM_CACHECTL - -/* - * Options for cacheflush system call - */ -#define ICACHE (1<<0) /* flush instruction cache */ -#define DCACHE (1<<1) /* writeback and flush data cache */ -#define BCACHE (ICACHE|DCACHE) /* flush both caches */ - -/* - * Caching modes for the cachectl(2) call - * - * cachectl(2) is currently not supported and returns ENOSYS. - */ -#define CACHEABLE 0 /* make pages cacheable */ -#define UNCACHEABLE 1 /* make pages uncacheable */ - -#endif /* _ASM_CACHECTL */ diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h deleted file mode 100644 index 70bcad7..0000000 --- a/include/asm-mips/cacheops.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Cache operations for the cache instruction. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle - * (C) Copyright 1999 Silicon Graphics, Inc. - */ -#ifndef __ASM_CACHEOPS_H -#define __ASM_CACHEOPS_H - -/* - * Cache Operations available on all MIPS processors with R4000-style caches - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 -#else -#define Hit_Invalidate_I 0x10 -#endif -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 - -/* - * R4000-specific cacheops - */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - -/* - * R4000SC and R4400SC-specific cacheops - */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -/* - * R5000-specific cacheops - */ -#define R5K_Page_Invalidate_S 0x17 - -/* - * RM7000-specific cacheops - */ -#define Page_Invalidate_T 0x16 - -/* - * R10000-specific cacheops - * - * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. - * Most of the _S cacheops are identical to the R4000SC _SD cacheops. - */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f - -#endif /* __ASM_CACHEOPS_H */ diff --git a/include/asm-mips/config.h b/include/asm-mips/config.h deleted file mode 100644 index 049c44e..0000000 --- a/include/asm-mips/config.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -#endif diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h deleted file mode 100644 index 1665a63..0000000 --- a/include/asm-mips/errno.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle - */ -#ifndef _ASM_MIPS_ERRNO_H -#define _ASM_MIPS_ERRNO_H - -/* - * These first 34 error codes are from Linux 2.6, - */ -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Argument list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ - -/* - * These error numbers are intended to be MIPS ABI compatible - */ -#define ENOMSG 35 /* No message of desired type */ -#define EIDRM 36 /* Identifier removed */ -#define ECHRNG 37 /* Channel number out of range */ -#define EL2NSYNC 38 /* Level 2 not synchronized */ -#define EL3HLT 39 /* Level 3 halted */ -#define EL3RST 40 /* Level 3 reset */ -#define ELNRNG 41 /* Link number out of range */ -#define EUNATCH 42 /* Protocol driver not attached */ -#define ENOCSI 43 /* No CSI structure available */ -#define EL2HLT 44 /* Level 2 halted */ -#define EDEADLK 45 /* Resource deadlock would occur */ -#define ENOLCK 46 /* No record locks available */ -#define EBADE 50 /* Invalid exchange */ -#define EBADR 51 /* Invalid request descriptor */ -#define EXFULL 52 /* Exchange full */ -#define ENOANO 53 /* No anode */ -#define EBADRQC 54 /* Invalid request code */ -#define EBADSLT 55 /* Invalid slot */ -#define EDEADLOCK 56 /* File locking deadlock error */ -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EDOTDOT 73 /* RFS specific error */ -#define EMULTIHOP 74 /* Multihop attempted */ -#define EBADMSG 77 /* Not a data message */ -#define ENAMETOOLONG 78 /* File name too long */ -#define EOVERFLOW 79 /* Value too large for defined data type */ -#define ENOTUNIQ 80 /* Name not unique on network */ -#define EBADFD 81 /* File descriptor in bad state */ -#define EREMCHG 82 /* Remote address changed */ -#define ELIBACC 83 /* Can not access a needed shared library */ -#define ELIBBAD 84 /* Accessing a corrupted shared library */ -#define ELIBSCN 85 /* .lib section in a.out corrupted */ -#define ELIBMAX 86 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 87 /* Cannot exec a shared library directly */ -#define EILSEQ 88 /* Illegal byte sequence */ -#define ENOSYS 89 /* Function not implemented */ -#define ELOOP 90 /* Too many symbolic links encountered */ -#define ERESTART 91 /* Interrupted system call should be restarted */ -#define ESTRPIPE 92 /* Streams pipe error */ -#define ENOTEMPTY 93 /* Directory not empty */ -#define EUSERS 94 /* Too many users */ -#define ENOTSOCK 95 /* Socket operation on non-socket */ -#define EDESTADDRREQ 96 /* Destination address required */ -#define EMSGSIZE 97 /* Message too long */ -#define EPROTOTYPE 98 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 99 /* Protocol not available */ -#define EPROTONOSUPPORT 120 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 121 /* Socket type not supported */ -#define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 123 /* Protocol family not supported */ -#define EAFNOSUPPORT 124 /* Address family not supported by protocol */ -#define EADDRINUSE 125 /* Address already in use */ -#define EADDRNOTAVAIL 126 /* Cannot assign requested address */ -#define ENETDOWN 127 /* Network is down */ -#define ENETUNREACH 128 /* Network is unreachable */ -#define ENETRESET 129 /* Network dropped connection because of reset */ -#define ECONNABORTED 130 /* Software caused connection abort */ -#define ECONNRESET 131 /* Connection reset by peer */ -#define ENOBUFS 132 /* No buffer space available */ -#define EISCONN 133 /* Transport endpoint is already connected */ -#define ENOTCONN 134 /* Transport endpoint is not connected */ -#define EUCLEAN 135 /* Structure needs cleaning */ -#define ENOTNAM 137 /* Not a XENIX named type file */ -#define ENAVAIL 138 /* No XENIX semaphores available */ -#define EISNAM 139 /* Is a named type file */ -#define EREMOTEIO 140 /* Remote I/O error */ -#define EINIT 141 /* Reserved */ -#define EREMDEV 142 /* Error 142 */ -#define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 144 /* Too many references: cannot splice */ -#define ETIMEDOUT 145 /* Connection timed out */ -#define ECONNREFUSED 146 /* Connection refused */ -#define EHOSTDOWN 147 /* Host is down */ -#define EHOSTUNREACH 148 /* No route to host */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define EALREADY 149 /* Operation already in progress */ -#define EINPROGRESS 150 /* Operation now in progress */ -#define ESTALE 151 /* Stale NFS file handle */ -#define ECANCELED 158 /* AIO operation canceled */ - -#endif /* _ASM_MIPS_ERRNO_H */ diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h deleted file mode 100644 index b2c4891..0000000 --- a/include/asm-mips/global_data.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * (C) Copyright 2002-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H - -#include - -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - void **jt; /* jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0") - -#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-mips/inca-ip.h b/include/asm-mips/inca-ip.h deleted file mode 100644 index e787a1d..0000000 --- a/include/asm-mips/inca-ip.h +++ /dev/null @@ -1,2441 +0,0 @@ - -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ - -#define INCA_IP_WDT (0xB8000000) -/***********************************************************************/ - - -/***Reset Status Register Power On***/ -#define INCA_IP_WDT_RST_SR ((volatile u32*)(INCA_IP_WDT+ 0x0014)) - -/***Reset Request Register***/ -#define INCA_IP_WDT_RST_REQ ((volatile u32*)(INCA_IP_WDT+ 0x0010)) -#define INCA_IP_WDT_RST_REQ_SWBOOT (1 << 24) -#define INCA_IP_WDT_RST_REQ_SWCFG (1 << 16) -#define INCA_IP_WDT_RST_REQ_RRPHY (1 << 5) -#define INCA_IP_WDT_RST_REQ_RRHSP (1 << 4) -#define INCA_IP_WDT_RST_REQ_RRFPI (1 << 3) -#define INCA_IP_WDT_RST_REQ_RREXT (1 << 2) -#define INCA_IP_WDT_RST_REQ_RRDSP (1 << 1) -#define INCA_IP_WDT_RST_REQ_RRCPU (1 << 0) - -/***NMI Status Register***/ -#define INCA_IP_WDT_NMISR ((volatile u32*)(INCA_IP_WDT+ 0x002C)) -#define INCA_IP_WDT_NMISR_NMIWDT (1 << 2) -#define INCA_IP_WDT_NMISR_NMIPLL (1 << 1) -#define INCA_IP_WDT_NMISR_NMIEXT (1 << 0) - -/***Manufacturer Identification Register***/ -#define INCA_IP_WDT_MANID ((volatile u32*)(INCA_IP_WDT+ 0x0070)) -#define INCA_IP_WDT_MANID_MANUF (value) (((( 1 << 11) - 1) & (value)) << 5) - -/***Chip Identification Register***/ -#define INCA_IP_WDT_CHIPID ((volatile u32*)(INCA_IP_WDT+ 0x0074)) -#define INCA_IP_WDT_CHIPID_VERSION (value) (((( 1 << 4) - 1) & (value)) << 28) -#define INCA_IP_WDT_CHIPID_PART_NUMBER (value) (((( 1 << 16) - 1) & (value)) << 12) -#define INCA_IP_WDT_CHIPID_MANID (value) (((( 1 << 11) - 1) & (value)) << 1) - -/***Redesign Tracing Identification Register***/ -#define INCA_IP_WDT_RTID ((volatile u32*)(INCA_IP_WDT+ 0x0078)) -#define INCA_IP_WDT_RTID_LC (1 << 15) -#define INCA_IP_WDT_RTID_RIX (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Watchdog Timer Control Register 0***/ -#define INCA_IP_WDT_WDT_CON0 ((volatile u32*)(INCA_IP_WDT+ 0x0020)) - -/***Watchdog Timer Control Register 1***/ -#define INCA_IP_WDT_WDT_CON1 ((volatile u32*)(INCA_IP_WDT+ 0x0024)) -#define INCA_IP_WDT_WDT_CON1_WDTDR (1 << 3) -#define INCA_IP_WDT_WDT_CON1_WDTIR (1 << 2) - -/***Watchdog Timer Status Register***/ -#define INCA_IP_WDT_WDT_SR ((volatile u32*)(INCA_IP_WDT+ 0x0028)) -#define INCA_IP_WDT_WDT_SR_WDTTIM (value) (((( 1 << 16) - 1) & (value)) << 16) -#define INCA_IP_WDT_WDT_SR_WDTPR (1 << 5) -#define INCA_IP_WDT_WDT_SR_WDTTO (1 << 4) -#define INCA_IP_WDT_WDT_SR_WDTDS (1 << 3) -#define INCA_IP_WDT_WDT_SR_WDTIS (1 << 2) -#define INCA_IP_WDT_WDT_SR_WDTOE (1 << 1) -#define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0) - -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_CGU (0xBF107000) -/***********************************************************************/ - - -/***CGU PLL1 Control Register***/ -#define INCA_IP_CGU_CGU_PLL1CR ((volatile u32*)(INCA_IP_CGU+ 0x0008)) -#define INCA_IP_CGU_CGU_PLL1CR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_PLL1CR_EN (1 << 30) -#define INCA_IP_CGU_CGU_PLL1CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_PLL1CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***CGU PLL0 Control Register***/ -#define INCA_IP_CGU_CGU_PLL0CR ((volatile u32*)(INCA_IP_CGU+ 0x0000)) -#define INCA_IP_CGU_CGU_PLL0CR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_PLL0CR_EN (1 << 30) -#define INCA_IP_CGU_CGU_PLL0CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_PLL0CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***CGU PLL0 Status Register***/ -#define INCA_IP_CGU_CGU_PLL0SR ((volatile u32*)(INCA_IP_CGU+ 0x0004)) -#define INCA_IP_CGU_CGU_PLL0SR_LOCK (1 << 31) -#define INCA_IP_CGU_CGU_PLL0SR_RCF (1 << 29) -#define INCA_IP_CGU_CGU_PLL0SR_PLLBYP (1 << 15) - -/***CGU PLL1 Status Register***/ -#define INCA_IP_CGU_CGU_PLL1SR ((volatile u32*)(INCA_IP_CGU+ 0x000C)) -#define INCA_IP_CGU_CGU_PLL1SR_LOCK (1 << 31) -#define INCA_IP_CGU_CGU_PLL1SR_RCF (1 << 29) -#define INCA_IP_CGU_CGU_PLL1SR_PLLBYP (1 << 15) - -/***CGU Divider Control Register***/ -#define INCA_IP_CGU_CGU_DIVCR ((volatile u32*)(INCA_IP_CGU+ 0x0010)) - -/***CGU Multiplexer Control Register***/ -#define INCA_IP_CGU_CGU_MUXCR ((volatile u32*)(INCA_IP_CGU+ 0x0014)) -#define INCA_IP_CGU_CGU_MUXCR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_MUXCR_MUXII (1 << 1) -#define INCA_IP_CGU_CGU_MUXCR_MUXI (1 << 0) - -/***CGU Fractional Divider Control Register***/ -#define INCA_IP_CGU_CGU_FDCR ((volatile u32*)(INCA_IP_CGU+ 0x0018)) -#define INCA_IP_CGU_CGU_FDCR_FDEN (1 << 31) -#define INCA_IP_CGU_CGU_FDCR_INTEGER (value) (((( 1 << 12) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : PMU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_PMU (0xBF102000) -/***********************************************************************/ - - -/***PM Global Enable Register***/ -#define INCA_IP_PMU_PM_GEN ((volatile u32*)(INCA_IP_PMU+ 0x0000)) -#define INCA_IP_PMU_PM_GEN_EN16 (1 << 16) -#define INCA_IP_PMU_PM_GEN_EN15 (1 << 15) -#define INCA_IP_PMU_PM_GEN_EN14 (1 << 14) -#define INCA_IP_PMU_PM_GEN_EN13 (1 << 13) -#define INCA_IP_PMU_PM_GEN_EN12 (1 << 12) -#define INCA_IP_PMU_PM_GEN_EN11 (1 << 11) -#define INCA_IP_PMU_PM_GEN_EN10 (1 << 10) -#define INCA_IP_PMU_PM_GEN_EN9 (1 << 9) -#define INCA_IP_PMU_PM_GEN_EN8 (1 << 8) -#define INCA_IP_PMU_PM_GEN_EN7 (1 << 7) -#define INCA_IP_PMU_PM_GEN_EN6 (1 << 6) -#define INCA_IP_PMU_PM_GEN_EN5 (1 << 5) -#define INCA_IP_PMU_PM_GEN_EN4 (1 << 4) -#define INCA_IP_PMU_PM_GEN_EN3 (1 << 3) -#define INCA_IP_PMU_PM_GEN_EN2 (1 << 2) -#define INCA_IP_PMU_PM_GEN_EN0 (1 << 0) - -/***PM Power Down Enable Register***/ -#define INCA_IP_PMU_PM_PDEN ((volatile u32*)(INCA_IP_PMU+ 0x0008)) -#define INCA_IP_PMU_PM_PDEN_EN16 (1 << 16) -#define INCA_IP_PMU_PM_PDEN_EN15 (1 << 15) -#define INCA_IP_PMU_PM_PDEN_EN14 (1 << 14) -#define INCA_IP_PMU_PM_PDEN_EN13 (1 << 13) -#define INCA_IP_PMU_PM_PDEN_EN12 (1 << 12) -#define INCA_IP_PMU_PM_PDEN_EN11 (1 << 11) -#define INCA_IP_PMU_PM_PDEN_EN10 (1 << 10) -#define INCA_IP_PMU_PM_PDEN_EN9 (1 << 9) -#define INCA_IP_PMU_PM_PDEN_EN8 (1 << 8) -#define INCA_IP_PMU_PM_PDEN_EN7 (1 << 7) -#define INCA_IP_PMU_PM_PDEN_EN5 (1 << 5) -#define INCA_IP_PMU_PM_PDEN_EN4 (1 << 4) -#define INCA_IP_PMU_PM_PDEN_EN3 (1 << 3) -#define INCA_IP_PMU_PM_PDEN_EN2 (1 << 2) -#define INCA_IP_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ -#define INCA_IP_PMU_PM_WUP ((volatile u32*)(INCA_IP_PMU+ 0x0010)) -#define INCA_IP_PMU_PM_WUP_WUP16 (1 << 16) -#define INCA_IP_PMU_PM_WUP_WUP15 (1 << 15) -#define INCA_IP_PMU_PM_WUP_WUP14 (1 << 14) -#define INCA_IP_PMU_PM_WUP_WUP13 (1 << 13) -#define INCA_IP_PMU_PM_WUP_WUP12 (1 << 12) -#define INCA_IP_PMU_PM_WUP_WUP11 (1 << 11) -#define INCA_IP_PMU_PM_WUP_WUP10 (1 << 10) -#define INCA_IP_PMU_PM_WUP_WUP9 (1 << 9) -#define INCA_IP_PMU_PM_WUP_WUP8 (1 << 8) -#define INCA_IP_PMU_PM_WUP_WUP7 (1 << 7) -#define INCA_IP_PMU_PM_WUP_WUP5 (1 << 5) -#define INCA_IP_PMU_PM_WUP_WUP4 (1 << 4) -#define INCA_IP_PMU_PM_WUP_WUP3 (1 << 3) -#define INCA_IP_PMU_PM_WUP_WUP2 (1 << 2) -#define INCA_IP_PMU_PM_WUP_WUP0 (1 << 0) - -/***PM Control Register***/ -#define INCA_IP_PMU_PM_CR ((volatile u32*)(INCA_IP_PMU+ 0x0014)) -#define INCA_IP_PMU_PM_CR_AWEN (1 << 31) -#define INCA_IP_PMU_PM_CR_SWRST (1 << 30) -#define INCA_IP_PMU_PM_CR_SWCR (1 << 2) -#define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BCU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_BCU (0xB8000100) -/***********************************************************************/ - - -/***BCU Control Register (0010H)***/ -#define INCA_IP_BCU_BCU_CON ((volatile u32*)(INCA_IP_BCU+ 0x0010)) -#define INCA_IP_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_BCU_BCU_CON_SPE (1 << 19) -#define INCA_IP_BCU_BCU_CON_PSE (1 << 18) -#define INCA_IP_BCU_BCU_CON_DBG (1 << 16) -#define INCA_IP_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***BCU Error Control Capture Register (0020H)***/ -#define INCA_IP_BCU_BCU_ECON ((volatile u32*)(INCA_IP_BCU+ 0x0020)) -#define INCA_IP_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) -#define INCA_IP_BCU_BCU_ECON_RDN (1 << 23) -#define INCA_IP_BCU_BCU_ECON_WRN (1 << 22) -#define INCA_IP_BCU_BCU_ECON_SVM (1 << 21) -#define INCA_IP_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19) -#define INCA_IP_BCU_BCU_ECON_ABT (1 << 18) -#define INCA_IP_BCU_BCU_ECON_RDY (1 << 17) -#define INCA_IP_BCU_BCU_ECON_TOUT (1 << 16) -#define INCA_IP_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) -#define INCA_IP_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) - -/***BCU Error Address Capture Register (0024 H)***/ -#define INCA_IP_BCU_BCU_EADD ((volatile u32*)(INCA_IP_BCU+ 0x0024)) -#define INCA_IP_BCU_BCU_EADD_FPIADR - -/***BCU Error Data Capture Register (0028H)***/ -#define INCA_IP_BCU_BCU_EDAT ((volatile u32*)(INCA_IP_BCU+ 0x0028)) -#define INCA_IP_BCU_BCU_EDAT_FPIDAT - -/***********************************************************************/ -/* Module : MBC register address and bits */ -/***********************************************************************/ - -#define INCA_IP_MBC (0xBF103000) -/***********************************************************************/ - - -/***Mailbox CPU Configuration Register***/ -#define INCA_IP_MBC_MBC_CFG ((volatile u32*)(INCA_IP_MBC+ 0x0080)) -#define INCA_IP_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_MBC_MBC_CFG_RES (1 << 5) -#define INCA_IP_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) -#define INCA_IP_MBC_MBC_CFG_SIZE (1 << 0) - -/***Mailbox CPU Interrupt Status Register***/ -#define INCA_IP_MBC_MBC_ISR ((volatile u32*)(INCA_IP_MBC+ 0x0084)) -#define INCA_IP_MBC_MBC_ISR_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_ISR_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_ISR_B1E (1 << 29) -#define INCA_IP_MBC_MBC_ISR_B0E (1 << 28) -#define INCA_IP_MBC_MBC_ISR_WDT (1 << 27) -#define INCA_IP_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask Register***/ -#define INCA_IP_MBC_MBC_MSK ((volatile u32*)(INCA_IP_MBC+ 0x0088)) -#define INCA_IP_MBC_MBC_MSK_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 01 Register***/ -#define INCA_IP_MBC_MBC_MSK01 ((volatile u32*)(INCA_IP_MBC+ 0x008C)) -#define INCA_IP_MBC_MBC_MSK01_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK01_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK01_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK01_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK01_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 10 Register***/ -#define INCA_IP_MBC_MBC_MSK10 ((volatile u32*)(INCA_IP_MBC+ 0x0090)) -#define INCA_IP_MBC_MBC_MSK10_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK10_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK10_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK10_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK10_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Short Command Register***/ -#define INCA_IP_MBC_MBC_CMD ((volatile u32*)(INCA_IP_MBC+ 0x0094)) -#define INCA_IP_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***Mailbox CPU Input Data of Buffer 0***/ -#define INCA_IP_MBC_MBC_ID0 ((volatile u32*)(INCA_IP_MBC+ 0x0000)) -#define INCA_IP_MBC_MBC_ID0_INDATA - -/***Mailbox CPU Input Data of Buffer 1***/ -#define INCA_IP_MBC_MBC_ID1 ((volatile u32*)(INCA_IP_MBC+ 0x0020)) -#define INCA_IP_MBC_MBC_ID1_INDATA - -/***Mailbox CPU Output Data of Buffer 2***/ -#define INCA_IP_MBC_MBC_OD2 ((volatile u32*)(INCA_IP_MBC+ 0x0040)) -#define INCA_IP_MBC_MBC_OD2_OUTDATA - -/***Mailbox CPU Output Data of Buffer 3***/ -#define INCA_IP_MBC_MBC_OD3 ((volatile u32*)(INCA_IP_MBC+ 0x0060)) -#define INCA_IP_MBC_MBC_OD3_OUTDATA - -/***Mailbox CPU Control Register of Buffer 0***/ -#define INCA_IP_MBC_MBC_CR0 ((volatile u32*)(INCA_IP_MBC+ 0x0004)) -#define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 1***/ -#define INCA_IP_MBC_MBC_CR1 ((volatile u32*)(INCA_IP_MBC+ 0x0024)) -#define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 2***/ -#define INCA_IP_MBC_MBC_CR2 ((volatile u32*)(INCA_IP_MBC+ 0x0044)) -#define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 3***/ -#define INCA_IP_MBC_MBC_CR3 ((volatile u32*)(INCA_IP_MBC+ 0x0064)) -#define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Free Space of Buffer 0***/ -#define INCA_IP_MBC_MBC_FS0 ((volatile u32*)(INCA_IP_MBC+ 0x0008)) -#define INCA_IP_MBC_MBC_FS0_FS - -/***Mailbox CPU Free Space of Buffer 1***/ -#define INCA_IP_MBC_MBC_FS1 ((volatile u32*)(INCA_IP_MBC+ 0x0028)) -#define INCA_IP_MBC_MBC_FS1_FS - -/***Mailbox CPU Free Space of Buffer 2***/ -#define INCA_IP_MBC_MBC_FS2 ((volatile u32*)(INCA_IP_MBC+ 0x0048)) -#define INCA_IP_MBC_MBC_FS2_FS - -/***Mailbox CPU Free Space of Buffer 3***/ -#define INCA_IP_MBC_MBC_FS3 ((volatile u32*)(INCA_IP_MBC+ 0x0068)) -#define INCA_IP_MBC_MBC_FS3_FS - -/***Mailbox CPU Data Available in Buffer 0***/ -#define INCA_IP_MBC_MBC_DA0 ((volatile u32*)(INCA_IP_MBC+ 0x000C)) -#define INCA_IP_MBC_MBC_DA0_DA - -/***Mailbox CPU Data Available in Buffer 1***/ -#define INCA_IP_MBC_MBC_DA1 ((volatile u32*)(INCA_IP_MBC+ 0x002C)) -#define INCA_IP_MBC_MBC_DA1_DA - -/***Mailbox CPU Data Available in Buffer 2***/ -#define INCA_IP_MBC_MBC_DA2 ((volatile u32*)(INCA_IP_MBC+ 0x004C)) -#define INCA_IP_MBC_MBC_DA2_DA - -/***Mailbox CPU Data Available in Buffer 3***/ -#define INCA_IP_MBC_MBC_DA3 ((volatile u32*)(INCA_IP_MBC+ 0x006C)) -#define INCA_IP_MBC_MBC_DA3_DA - -/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_IABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0010)) -#define INCA_IP_MBC_MBC_IABS0_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_IABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0030)) -#define INCA_IP_MBC_MBC_IABS1_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_IABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0050)) -#define INCA_IP_MBC_MBC_IABS2_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_IABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0070)) -#define INCA_IP_MBC_MBC_IABS3_IABS - -/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_ITMP0 ((volatile u32*)(INCA_IP_MBC+ 0x0014)) -#define INCA_IP_MBC_MBC_ITMP0_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_ITMP1 ((volatile u32*)(INCA_IP_MBC+ 0x0034)) -#define INCA_IP_MBC_MBC_ITMP1_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_ITMP2 ((volatile u32*)(INCA_IP_MBC+ 0x0054)) -#define INCA_IP_MBC_MBC_ITMP2_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_ITMP3 ((volatile u32*)(INCA_IP_MBC+ 0x0074)) -#define INCA_IP_MBC_MBC_ITMP3_ITMP - -/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_OABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0018)) -#define INCA_IP_MBC_MBC_OABS0_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_OABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0038)) -#define INCA_IP_MBC_MBC_OABS1_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_OABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0058)) -#define INCA_IP_MBC_MBC_OABS2_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_OABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0078)) -#define INCA_IP_MBC_MBC_OABS3_OABS - -/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_OTMP0 ((volatile u32*)(INCA_IP_MBC+ 0x001C)) -#define INCA_IP_MBC_MBC_OTMP0_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_OTMP1 ((volatile u32*)(INCA_IP_MBC+ 0x003C)) -#define INCA_IP_MBC_MBC_OTMP1_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_OTMP2 ((volatile u32*)(INCA_IP_MBC+ 0x005C)) -#define INCA_IP_MBC_MBC_OTMP2_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_OTMP3 ((volatile u32*)(INCA_IP_MBC+ 0x007C)) -#define INCA_IP_MBC_MBC_OTMP3_OTMP - -/***DSP Control Register***/ -#define INCA_IP_MBC_DCTRL ((volatile u32*)(INCA_IP_MBC+ 0x00A0)) -#define INCA_IP_MBC_DCTRL_BA (1 << 0) -#define INCA_IP_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) -#define INCA_IP_MBC_DCTRL_IDL (1 << 4) -#define INCA_IP_MBC_DCTRL_RES (1 << 15) - -/***DSP Status Register***/ -#define INCA_IP_MBC_DSTA ((volatile u32*)(INCA_IP_MBC+ 0x00A4)) -#define INCA_IP_MBC_DSTA_IDLE (1 << 0) -#define INCA_IP_MBC_DSTA_PD (1 << 1) - -/***DSP Test 1 Register***/ -#define INCA_IP_MBC_DTST1 ((volatile u32*)(INCA_IP_MBC+ 0x00A8)) -#define INCA_IP_MBC_DTST1_ABORT (1 << 0) -#define INCA_IP_MBC_DTST1_HWF32 (1 << 1) -#define INCA_IP_MBC_DTST1_HWF4M (1 << 2) -#define INCA_IP_MBC_DTST1_HWFOP (1 << 3) - -/***********************************************************************/ -/* Module : Switch register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Switch (0xBF104000) -/***********************************************************************/ - - -/***Unknown Destination Register***/ -#define INCA_IP_Switch_UN_DEST ((volatile u32*)(INCA_IP_Switch+ 0x0000)) -#define INCA_IP_Switch_UN_DEST_CB (1 << 8) -#define INCA_IP_Switch_UN_DEST_LB (1 << 7) -#define INCA_IP_Switch_UN_DEST_PB (1 << 6) -#define INCA_IP_Switch_UN_DEST_CM (1 << 5) -#define INCA_IP_Switch_UN_DEST_LM (1 << 4) -#define INCA_IP_Switch_UN_DEST_PM (1 << 3) -#define INCA_IP_Switch_UN_DEST_CU (1 << 2) -#define INCA_IP_Switch_UN_DEST_LU (1 << 1) -#define INCA_IP_Switch_UN_DEST_PU (1 << 0) - -/***VLAN Control Register***/ -#define INCA_IP_Switch_VLAN_CTRL ((volatile u32*)(INCA_IP_Switch+ 0x0004)) -#define INCA_IP_Switch_VLAN_CTRL_SC (1 << 6) -#define INCA_IP_Switch_VLAN_CTRL_SL (1 << 5) -#define INCA_IP_Switch_VLAN_CTRL_SP (1 << 4) -#define INCA_IP_Switch_VLAN_CTRL_TC (1 << 3) -#define INCA_IP_Switch_VLAN_CTRL_TL (1 << 2) -#define INCA_IP_Switch_VLAN_CTRL_TP (1 << 1) -#define INCA_IP_Switch_VLAN_CTRL_VA (1 << 0) - -/***PC VLAN Configuration Register***/ -#define INCA_IP_Switch_PC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0008)) -#define INCA_IP_Switch_PC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_PC_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***LAN VLAN Configuration Register***/ -#define INCA_IP_Switch_LAN_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x000C)) -#define INCA_IP_Switch_LAN_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***CPU VLAN Configuration Register***/ -#define INCA_IP_Switch_CPU_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0010)) -#define INCA_IP_Switch_CPU_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***Priority CoS Mapping Register***/ -#define INCA_IP_Switch_PRI_CoS ((volatile u32*)(INCA_IP_Switch+ 0x0014)) -#define INCA_IP_Switch_PRI_CoS_P7 (1 << 7) -#define INCA_IP_Switch_PRI_CoS_P6 (1 << 6) -#define INCA_IP_Switch_PRI_CoS_P5 (1 << 5) -#define INCA_IP_Switch_PRI_CoS_P4 (1 << 4) -#define INCA_IP_Switch_PRI_CoS_P3 (1 << 3) -#define INCA_IP_Switch_PRI_CoS_P2 (1 << 2) -#define INCA_IP_Switch_PRI_CoS_P1 (1 << 1) -#define INCA_IP_Switch_PRI_CoS_P0 (1 << 0) - -/***Spanning Tree Port Status Register***/ -#define INCA_IP_Switch_ST_PT ((volatile u32*)(INCA_IP_Switch+ 0x0018)) -#define INCA_IP_Switch_ST_PT_CPS (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_Switch_ST_PT_LPS (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_Switch_ST_PT_PPS (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***ARL Control Register***/ -#define INCA_IP_Switch_ARL_CTL ((volatile u32*)(INCA_IP_Switch+ 0x001C)) -#define INCA_IP_Switch_ARL_CTL_CHCC (1 << 15) -#define INCA_IP_Switch_ARL_CTL_CHCL (1 << 14) -#define INCA_IP_Switch_ARL_CTL_CHCP (1 << 13) -#define INCA_IP_Switch_ARL_CTL_CC (1 << 12) -#define INCA_IP_Switch_ARL_CTL_CL (1 << 11) -#define INCA_IP_Switch_ARL_CTL_CP (1 << 10) -#define INCA_IP_Switch_ARL_CTL_CG (1 << 9) -#define INCA_IP_Switch_ARL_CTL_PS (1 << 8) -#define INCA_IP_Switch_ARL_CTL_MRO (1 << 7) -#define INCA_IP_Switch_ARL_CTL_SRC (1 << 6) -#define INCA_IP_Switch_ARL_CTL_ATS (1 << 5) -#define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_ARL_CTL_MAF (1 << 1) -#define INCA_IP_Switch_ARL_CTL_ENL (1 << 0) -#define INCA_IP_Switch_ARL_CTL_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - -/***CPU Access Control Register***/ -#define INCA_IP_Switch_CPU_ACTL ((volatile u32*)(INCA_IP_Switch+ 0x0020)) -#define INCA_IP_Switch_CPU_ACTL_RA (1 << 31) -#define INCA_IP_Switch_CPU_ACTL_RW (1 << 30) -#define INCA_IP_Switch_CPU_ACTL_Res (value) (((( 1 << 21) - 1) & (value)) << 9) -#define INCA_IP_Switch_CPU_ACTL_AVA (1 << 8) -#define INCA_IP_Switch_CPU_ACTL_IDX (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***CPU Access Data Register 1***/ -#define INCA_IP_Switch_DATA1 ((volatile u32*)(INCA_IP_Switch+ 0x0024)) -#define INCA_IP_Switch_DATA1_Data (value) (((( 1 << 24) - 1) & (value)) << 0) - -/***CPU Access Data Register 2***/ -#define INCA_IP_Switch_DATA2 ((volatile u32*)(INCA_IP_Switch+ 0x0028)) -#define INCA_IP_Switch_DATA2_Data - -/***CPU Port Control Register***/ -#define INCA_IP_Switch_CPU_PCTL ((volatile u32*)(INCA_IP_Switch+ 0x002C)) -#define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value) (((( 1 << 3) - 1) & (value)) << 11) -#define INCA_IP_Switch_CPU_PCTL_DAC (1 << 10) -#define INCA_IP_Switch_CPU_PCTL_MA_STATE (value) (((( 1 << 3) - 1) & (value)) << 7) -#define INCA_IP_Switch_CPU_PCTL_MAM (1 << 6) -#define INCA_IP_Switch_CPU_PCTL_MA_Ports (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_Switch_CPU_PCTL_MAC (1 << 2) -#define INCA_IP_Switch_CPU_PCTL_EML (1 << 1) -#define INCA_IP_Switch_CPU_PCTL_EDL (1 << 0) -#define INCA_IP_Switch_CPU_PCTL_Res (value) (((( 1 << 18) - 1) & (value)) << 14) - -/***DSCP CoS Mapping Register 1***/ -#define INCA_IP_Switch_DSCP_COS1 ((volatile u32*)(INCA_IP_Switch+ 0x0030)) -#define INCA_IP_Switch_DSCP_COS1_DSCP - -/***DSCP CoS Mapping Register 1***/ -#define INCA_IP_Switch_DSCP_COS2 ((volatile u32*)(INCA_IP_Switch+ 0x0034)) -#define INCA_IP_Switch_DSCP_COS2_DSCP - -/***PC WFQ Control Register***/ -#define INCA_IP_Switch_PC_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0080)) -#define INCA_IP_Switch_PC_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_PC_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***PC TX Control Register***/ -#define INCA_IP_Switch_PC_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0084)) -#define INCA_IP_Switch_PC_TX_CTL_ELR (1 << 1) -#define INCA_IP_Switch_PC_TX_CTL_EER (1 << 0) - -/***LAN WFQ Control Register***/ -#define INCA_IP_Switch_LAN_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0100)) -#define INCA_IP_Switch_LAN_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_LAN_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***LAN TX Control Register***/ -#define INCA_IP_Switch_LAN_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0104)) -#define INCA_IP_Switch_LAN_TX_CTL_ELR (1 << 1) -#define INCA_IP_Switch_LAN_TX_CTL_EER (1 << 0) - -/***CPU WFQ Control Register***/ -#define INCA_IP_Switch_CPU_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0180)) -#define INCA_IP_Switch_CPU_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_CPU_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***PM PC RX Watermark Register***/ -#define INCA_IP_Switch_PC_WM ((volatile u32*)(INCA_IP_Switch+ 0x0200)) -#define INCA_IP_Switch_PC_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_PC_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_PC_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_PC_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM LAN RX Watermark Register***/ -#define INCA_IP_Switch_LAN_WM ((volatile u32*)(INCA_IP_Switch+ 0x0204)) -#define INCA_IP_Switch_LAN_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_LAN_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_LAN_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_LAN_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM CPU RX Watermark Register***/ -#define INCA_IP_Switch_CPU_WM ((volatile u32*)(INCA_IP_Switch+ 0x0208)) -#define INCA_IP_Switch_CPU_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_CPU_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_CPU_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_CPU_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM CPU RX Watermark Register***/ -#define INCA_IP_Switch_GBL_WM ((volatile u32*)(INCA_IP_Switch+ 0x020C)) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM Control Register***/ -#define INCA_IP_Switch_PM_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0210)) -#define INCA_IP_Switch_PM_CTL_GDN (1 << 3) -#define INCA_IP_Switch_PM_CTL_CDN (1 << 2) -#define INCA_IP_Switch_PM_CTL_LDN (1 << 1) -#define INCA_IP_Switch_PM_CTL_PDN (1 << 0) - -/***PM Header Control Register***/ -#define INCA_IP_Switch_PMAC_HD_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0280)) -#define INCA_IP_Switch_PMAC_HD_CTL_RL2 (1 << 21) -#define INCA_IP_Switch_PMAC_HD_CTL_RC (1 << 20) -#define INCA_IP_Switch_PMAC_HD_CTL_CM (1 << 19) -#define INCA_IP_Switch_PMAC_HD_CTL_CV (1 << 18) -#define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value) (((( 1 << 16) - 1) & (value)) << 2) -#define INCA_IP_Switch_PMAC_HD_CTL_TAG (1 << 1) -#define INCA_IP_Switch_PMAC_HD_CTL_ADD (1 << 0) - -/***PM Source Address Register 1***/ -#define INCA_IP_Switch_PMAC_SA1 ((volatile u32*)(INCA_IP_Switch+ 0x0284)) -#define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***PM Source Address Register 2***/ -#define INCA_IP_Switch_PMAC_SA2 ((volatile u32*)(INCA_IP_Switch+ 0x0288)) -#define INCA_IP_Switch_PMAC_SA2_SA_31_0 - -/***PM Dest Address Register 1***/ -#define INCA_IP_Switch_PMAC_DA1 ((volatile u32*)(INCA_IP_Switch+ 0x028C)) -#define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***PM Dest Address Register 2***/ -#define INCA_IP_Switch_PMAC_DA2 ((volatile u32*)(INCA_IP_Switch+ 0x0290)) -#define INCA_IP_Switch_PMAC_DA2_DA_31_0 - -/***PM VLAN Register***/ -#define INCA_IP_Switch_PMAC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0294)) -#define INCA_IP_Switch_PMAC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 13) -#define INCA_IP_Switch_PMAC_VLAN_CFI (1 << 12) -#define INCA_IP_Switch_PMAC_VLAN_VLANID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***PM TX IPG Counter Register***/ -#define INCA_IP_Switch_PMAC_TX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x0298)) -#define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM RX IPG Counter Register***/ -#define INCA_IP_Switch_PMAC_RX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x029C)) -#define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Mirror Register***/ -#define INCA_IP_Switch_MRR ((volatile u32*)(INCA_IP_Switch+ 0x0300)) -#define INCA_IP_Switch_MRR_MRR (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_Switch_MRR_EC (1 << 5) -#define INCA_IP_Switch_MRR_EL (1 << 4) -#define INCA_IP_Switch_MRR_EP (1 << 3) -#define INCA_IP_Switch_MRR_IC (1 << 2) -#define INCA_IP_Switch_MRR_IL (1 << 1) -#define INCA_IP_Switch_MRR_IP (1 << 0) - -/***Packet Length Register***/ -#define INCA_IP_Switch_PKT_LEN ((volatile u32*)(INCA_IP_Switch+ 0x0304)) -#define INCA_IP_Switch_PKT_LEN_ADD (1 << 11) -#define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value) (((( 1 << 11) - 1) & (value)) << 0) - -/***MDIO Access Register***/ -#define INCA_IP_Switch_MDIO_ACC ((volatile u32*)(INCA_IP_Switch+ 0x0480)) -#define INCA_IP_Switch_MDIO_ACC_RA (1 << 31) -#define INCA_IP_Switch_MDIO_ACC_RW (1 << 30) -#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21) -#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16) -#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Ethernet PHY Register***/ -#define INCA_IP_Switch_EPHY ((volatile u32*)(INCA_IP_Switch+ 0x0484)) -#define INCA_IP_Switch_EPHY_SL (1 << 7) -#define INCA_IP_Switch_EPHY_SP (1 << 6) -#define INCA_IP_Switch_EPHY_LL (1 << 5) -#define INCA_IP_Switch_EPHY_LP (1 << 4) -#define INCA_IP_Switch_EPHY_DL (1 << 3) -#define INCA_IP_Switch_EPHY_DP (1 << 2) -#define INCA_IP_Switch_EPHY_PL (1 << 1) -#define INCA_IP_Switch_EPHY_PP (1 << 0) - -/***Pause Write Enable Register***/ -#define INCA_IP_Switch_PWR_EN ((volatile u32*)(INCA_IP_Switch+ 0x0488)) -#define INCA_IP_Switch_PWR_EN_PL (1 << 1) -#define INCA_IP_Switch_PWR_EN_PP (1 << 0) - -/***MDIO Configuration Register***/ -#define INCA_IP_Switch_MDIO_CFG ((volatile u32*)(INCA_IP_Switch+ 0x048C)) -#define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14) -#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9) -#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value) (((( 1 << 5) - 1) & (value)) << 4) -#define INCA_IP_Switch_MDIO_CFG_UEP (1 << 3) -#define INCA_IP_Switch_MDIO_CFG_PS (1 << 2) -#define INCA_IP_Switch_MDIO_CFG_PT (1 << 1) -#define INCA_IP_Switch_MDIO_CFG_UMM (1 << 0) - -/***Clock Configuration Register***/ -#define INCA_IP_Switch_CLK_CFG ((volatile u32*)(INCA_IP_Switch+ 0x0500)) -#define INCA_IP_Switch_CLK_CFG_ARL_ID (1 << 9) -#define INCA_IP_Switch_CLK_CFG_CPU_ID (1 << 8) -#define INCA_IP_Switch_CLK_CFG_LAN_ID (1 << 7) -#define INCA_IP_Switch_CLK_CFG_PC_ID (1 << 6) -#define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5) - -/***********************************************************************/ -/* Module : SSC1 register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SSC1 (0xB8000500) -/***********************************************************************/ - - -/***Control Register (Programming Mode)***/ -#define INCA_IP_SSC1_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) -#define INCA_IP_SSC1_SCC_CON_PRG_EN (1 << 15) -#define INCA_IP_SSC1_SCC_CON_PRG_MS (1 << 14) -#define INCA_IP_SSC1_SCC_CON_PRG_AREN (1 << 12) -#define INCA_IP_SSC1_SCC_CON_PRG_BEN (1 << 11) -#define INCA_IP_SSC1_SCC_CON_PRG_PEN (1 << 10) -#define INCA_IP_SSC1_SCC_CON_PRG_REN (1 << 9) -#define INCA_IP_SSC1_SCC_CON_PRG_TEN (1 << 8) -#define INCA_IP_SSC1_SCC_CON_PRG_LB (1 << 7) -#define INCA_IP_SSC1_SCC_CON_PRG_PO (1 << 6) -#define INCA_IP_SSC1_SCC_CON_PRG_PH (1 << 5) -#define INCA_IP_SSC1_SCC_CON_PRG_HB (1 << 4) -#define INCA_IP_SSC1_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SCC Control Register (Operating Mode)***/ -#define INCA_IP_SSC1_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) -#define INCA_IP_SSC1_SCC_CON_OPR_EN (1 << 15) -#define INCA_IP_SSC1_SCC_CON_OPR_MS (1 << 14) -#define INCA_IP_SSC1_SCC_CON_OPR_BSY (1 << 12) -#define INCA_IP_SSC1_SCC_CON_OPR_BE (1 << 11) -#define INCA_IP_SSC1_SCC_CON_OPR_PE (1 << 10) -#define INCA_IP_SSC1_SCC_CON_OPR_RE (1 << 9) -#define INCA_IP_SSC1_SCC_CON_OPR_TE (1 << 8) -#define INCA_IP_SSC1_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SSC Write Hardware Modified Control Register***/ -#define INCA_IP_SSC1_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC1+ 0x0040)) -#define INCA_IP_SSC1_SSC_WHBCON_SETBE (1 << 15) -#define INCA_IP_SSC1_SSC_WHBCON_SETPE (1 << 14) -#define INCA_IP_SSC1_SSC_WHBCON_SETRE (1 << 13) -#define INCA_IP_SSC1_SSC_WHBCON_SETTE (1 << 12) -#define INCA_IP_SSC1_SSC_WHBCON_CLRBE (1 << 11) -#define INCA_IP_SSC1_SSC_WHBCON_CLRPE (1 << 10) -#define INCA_IP_SSC1_SSC_WHBCON_CLRRE (1 << 9) -#define INCA_IP_SSC1_SSC_WHBCON_CLRTE (1 << 8) - -/***SSC Baudrate Timer Reload Register***/ -#define INCA_IP_SSC1_SSC_BR ((volatile u32*)(INCA_IP_SSC1+ 0x0014)) -#define INCA_IP_SSC1_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Transmitter Buffer Register***/ -#define INCA_IP_SSC1_SSC_TB ((volatile u32*)(INCA_IP_SSC1+ 0x0020)) -#define INCA_IP_SSC1_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receiver Buffer Register***/ -#define INCA_IP_SSC1_SSC_RB ((volatile u32*)(INCA_IP_SSC1+ 0x0024)) -#define INCA_IP_SSC1_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receive FIFO Control Register***/ -#define INCA_IP_SSC1_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0030)) -#define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_SSC1_SSC_RXFCON_RXFLU (1 << 1) -#define INCA_IP_SSC1_SSC_RXFCON_RXFEN (1 << 0) - -/***SSC Transmit FIFO Control Register***/ -#define INCA_IP_SSC1_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0034)) -#define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_SSC1_SSC_TXFCON_TXFLU (1 << 1) -#define INCA_IP_SSC1_SSC_TXFCON_TXFEN (1 << 0) - -/***SSC FIFO Status Register***/ -#define INCA_IP_SSC1_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC1+ 0x0038)) -#define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***SSC Clock Control Register***/ -#define INCA_IP_SSC1_SSC_CLC ((volatile u32*)(INCA_IP_SSC1+ 0x0000)) -#define INCA_IP_SSC1_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_CLC_DISS (1 << 1) -#define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : SSC2 register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SSC2 (0xB8000600) -/***********************************************************************/ - - -/***Control Register (Programming Mode)***/ -#define INCA_IP_SSC2_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) -#define INCA_IP_SSC2_SCC_CON_PRG_EN (1 << 15) -#define INCA_IP_SSC2_SCC_CON_PRG_MS (1 << 14) -#define INCA_IP_SSC2_SCC_CON_PRG_AREN (1 << 12) -#define INCA_IP_SSC2_SCC_CON_PRG_BEN (1 << 11) -#define INCA_IP_SSC2_SCC_CON_PRG_PEN (1 << 10) -#define INCA_IP_SSC2_SCC_CON_PRG_REN (1 << 9) -#define INCA_IP_SSC2_SCC_CON_PRG_TEN (1 << 8) -#define INCA_IP_SSC2_SCC_CON_PRG_LB (1 << 7) -#define INCA_IP_SSC2_SCC_CON_PRG_PO (1 << 6) -#define INCA_IP_SSC2_SCC_CON_PRG_PH (1 << 5) -#define INCA_IP_SSC2_SCC_CON_PRG_HB (1 << 4) -#define INCA_IP_SSC2_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SCC Control Register (Operating Mode)***/ -#define INCA_IP_SSC2_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) -#define INCA_IP_SSC2_SCC_CON_OPR_EN (1 << 15) -#define INCA_IP_SSC2_SCC_CON_OPR_MS (1 << 14) -#define INCA_IP_SSC2_SCC_CON_OPR_BSY (1 << 12) -#define INCA_IP_SSC2_SCC_CON_OPR_BE (1 << 11) -#define INCA_IP_SSC2_SCC_CON_OPR_PE (1 << 10) -#define INCA_IP_SSC2_SCC_CON_OPR_RE (1 << 9) -#define INCA_IP_SSC2_SCC_CON_OPR_TE (1 << 8) -#define INCA_IP_SSC2_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SSC Write Hardware Modified Control Register***/ -#define INCA_IP_SSC2_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC2+ 0x0040)) -#define INCA_IP_SSC2_SSC_WHBCON_SETBE (1 << 15) -#define INCA_IP_SSC2_SSC_WHBCON_SETPE (1 << 14) -#define INCA_IP_SSC2_SSC_WHBCON_SETRE (1 << 13) -#define INCA_IP_SSC2_SSC_WHBCON_SETTE (1 << 12) -#define INCA_IP_SSC2_SSC_WHBCON_CLRBE (1 << 11) -#define INCA_IP_SSC2_SSC_WHBCON_CLRPE (1 << 10) -#define INCA_IP_SSC2_SSC_WHBCON_CLRRE (1 << 9) -#define INCA_IP_SSC2_SSC_WHBCON_CLRTE (1 << 8) - -/***SSC Baudrate Timer Reload Register***/ -#define INCA_IP_SSC2_SSC_BR ((volatile u32*)(INCA_IP_SSC2+ 0x0014)) -#define INCA_IP_SSC2_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Transmitter Buffer Register***/ -#define INCA_IP_SSC2_SSC_TB ((volatile u32*)(INCA_IP_SSC2+ 0x0020)) -#define INCA_IP_SSC2_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receiver Buffer Register***/ -#define INCA_IP_SSC2_SSC_RB ((volatile u32*)(INCA_IP_SSC2+ 0x0024)) -#define INCA_IP_SSC2_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receive FIFO Control Register***/ -#define INCA_IP_SSC2_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0030)) -#define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_SSC2_SSC_RXFCON_RXFLU (1 << 1) -#define INCA_IP_SSC2_SSC_RXFCON_RXFEN (1 << 0) - -/***SSC Transmit FIFO Control Register***/ -#define INCA_IP_SSC2_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0034)) -#define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_SSC2_SSC_TXFCON_TXFLU (1 << 1) -#define INCA_IP_SSC2_SSC_TXFCON_TXFEN (1 << 0) - -/***SSC FIFO Status Register***/ -#define INCA_IP_SSC2_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC2+ 0x0038)) -#define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***SSC Clock Control Register***/ -#define INCA_IP_SSC2_SSC_CLC ((volatile u32*)(INCA_IP_SSC2+ 0x0000)) -#define INCA_IP_SSC2_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_CLC_DISS (1 << 1) -#define INCA_IP_SSC2_SSC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#if defined(CONFIG_INCA_IP) -#define INCA_IP_EBU (0xB8000200) -#elif defined(CONFIG_PURPLE) -#define INCA_IP_EBU (0xB800D800) -#endif - -/***********************************************************************/ - - -/***EBU Clock Control Register***/ -#define INCA_IP_EBU_EBU_CLC ((volatile u32*)(INCA_IP_EBU+ 0x0000)) -#define INCA_IP_EBU_EBU_CLC_DISS (1 << 1) -#define INCA_IP_EBU_EBU_CLC_DISR (1 << 0) - -/***EBU Global Control Register***/ -#define INCA_IP_EBU_EBU_CON ((volatile u32*)(INCA_IP_EBU+ 0x0010)) -#define INCA_IP_EBU_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_EBU_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_CON_ARBSYNC (1 << 5) -#define INCA_IP_EBU_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ -#define INCA_IP_EBU_EBU_ADDSEL0 ((volatile u32*)(INCA_IP_EBU+ 0x0020)) -#define INCA_IP_EBU_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL0_REGEN (1 << 0) - -/***EBU Address Select Register 1***/ -#define INCA_IP_EBU_EBU_ADDSEL1 ((volatile u32*)(INCA_IP_EBU+ 0x0024)) -#define INCA_IP_EBU_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL1_REGEN (1 << 0) - -/***EBU Address Select Register 2***/ -#define INCA_IP_EBU_EBU_ADDSEL2 ((volatile u32*)(INCA_IP_EBU+ 0x0028)) -#define INCA_IP_EBU_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL2_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ -#define INCA_IP_EBU_EBU_BUSCON0 ((volatile u32*)(INCA_IP_EBU+ 0x0060)) -#define INCA_IP_EBU_EBU_BUSCON0_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON0_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON0_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ -#define INCA_IP_EBU_EBU_BUSCON1 ((volatile u32*)(INCA_IP_EBU+ 0x0064)) -#define INCA_IP_EBU_EBU_BUSCON1_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON1_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON1_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define INCA_IP_EBU_EBU_BUSCON2 ((volatile u32*)(INCA_IP_EBU+ 0x0068)) -#define INCA_IP_EBU_EBU_BUSCON2_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON2_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON2_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : SDRAM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SDRAM (0xBF800000) -/***********************************************************************/ - - -/***MC Access Error Cause Register***/ -#define INCA_IP_SDRAM_MC_ERRCAUSE ((volatile u32*)(INCA_IP_SDRAM+ 0x0100)) -#define INCA_IP_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***MC Access Error Address Register***/ -#define INCA_IP_SDRAM_MC_ERRADDR ((volatile u32*)(INCA_IP_SDRAM+ 0x0108)) -#define INCA_IP_SDRAM_MC_ERRADDR_ADDR - -/***MC I/O General Purpose Register***/ -#define INCA_IP_SDRAM_MC_IOGP ((volatile u32*)(INCA_IP_SDRAM+ 0x0800)) -#define INCA_IP_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) -#define INCA_IP_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) -#define INCA_IP_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20) -#define INCA_IP_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_IOGP_CPS (1 << 11) -#define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***MC Self Refresh Register***/ -#define INCA_IP_SDRAM_MC_SELFRFSH ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00)) -#define INCA_IP_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -#define INCA_IP_SDRAM_MC_SELFRFSH_PWD (1 << 0) -#define INCA_IP_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) - -/***MC Enable Register***/ -#define INCA_IP_SDRAM_MC_CTRLENA ((volatile u32*)(INCA_IP_SDRAM+ 0x1000)) -#define INCA_IP_SDRAM_MC_CTRLENA_ENA (1 << 0) -#define INCA_IP_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) - -/***MC Mode Register Setup Code***/ -#define INCA_IP_SDRAM_MC_MRSCODE ((volatile u32*)(INCA_IP_SDRAM+ 0x1008)) -#define INCA_IP_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) -#define INCA_IP_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_MRSCODE_WT (1 << 3) -#define INCA_IP_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***MC Configuration Data-word Width Register***/ -#define INCA_IP_SDRAM_MC_CFGDW ((volatile u32*)(INCA_IP_SDRAM+ 0x1010)) -#define INCA_IP_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) - -/***MC Configuration Physical Bank 0 Register***/ -#define INCA_IP_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP_SDRAM+ 0x1018)) -#define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) - -/***MC Latency Register***/ -#define INCA_IP_SDRAM_MC_LATENCY ((volatile u32*)(INCA_IP_SDRAM+ 0x1038)) -#define INCA_IP_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) - -/***MC Refresh Cycle Time Register***/ -#define INCA_IP_SDRAM_MC_TREFRESH ((volatile u32*)(INCA_IP_SDRAM+ 0x1040)) -#define INCA_IP_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - -/***********************************************************************/ -/* Module : GPTU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_GPTU (0xB8000300) -/***********************************************************************/ - - -/***GPT Clock Control Register***/ -#define INCA_IP_GPTU_GPT_CLC ((volatile u32*)(INCA_IP_GPTU+ 0x0000)) -#define INCA_IP_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_GPTU_GPT_CLC_DISS (1 << 1) -#define INCA_IP_GPTU_GPT_CLC_DISR (1 << 0) - -/***GPT Timer 3 Control Register***/ -#define INCA_IP_GPTU_GPT_T3CON ((volatile u32*)(INCA_IP_GPTU+ 0x0014)) -#define INCA_IP_GPTU_GPT_T3CON_T3RDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T3CON_T3CHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T3CON_T3EDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define INCA_IP_GPTU_GPT_T3CON_T3OTL (1 << 10) -#define INCA_IP_GPTU_GPT_T3CON_T3UD (1 << 7) -#define INCA_IP_GPTU_GPT_T3CON_T3R (1 << 6) -#define INCA_IP_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write Hardware Modified Timer 3 Control Register -If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT3CON ((volatile u32*)(INCA_IP_GPTU+ 0x004C)) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) - -/***GPT Timer 2 Control Register***/ -#define INCA_IP_GPTU_GPT_T2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0010)) -#define INCA_IP_GPTU_GPT_T2CON_TxRDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T2CON_TxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T2CON_TxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T2CON_TxIRDIS (1 << 12) -#define INCA_IP_GPTU_GPT_T2CON_TxRC (1 << 9) -#define INCA_IP_GPTU_GPT_T2CON_TxUD (1 << 7) -#define INCA_IP_GPTU_GPT_T2CON_TxR (1 << 6) -#define INCA_IP_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Timer 4 Control Register***/ -#define INCA_IP_GPTU_GPT_T4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0018)) -#define INCA_IP_GPTU_GPT_T4CON_TxRDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T4CON_TxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T4CON_TxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T4CON_TxIRDIS (1 << 12) -#define INCA_IP_GPTU_GPT_T4CON_TxRC (1 << 9) -#define INCA_IP_GPTU_GPT_T4CON_TxUD (1 << 7) -#define INCA_IP_GPTU_GPT_T4CON_TxR (1 << 6) -#define INCA_IP_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 2 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0048)) -#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) - -/***GPT Write HW Modified Timer 4 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0050)) -#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) - -/***GPT Capture Reload Register***/ -#define INCA_IP_GPTU_GPT_CAPREL ((volatile u32*)(INCA_IP_GPTU+ 0x0030)) -#define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 2 Register***/ -#define INCA_IP_GPTU_GPT_T2 ((volatile u32*)(INCA_IP_GPTU+ 0x0034)) -#define INCA_IP_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 3 Register***/ -#define INCA_IP_GPTU_GPT_T3 ((volatile u32*)(INCA_IP_GPTU+ 0x0038)) -#define INCA_IP_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 4 Register***/ -#define INCA_IP_GPTU_GPT_T4 ((volatile u32*)(INCA_IP_GPTU+ 0x003C)) -#define INCA_IP_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 5 Register***/ -#define INCA_IP_GPTU_GPT_T5 ((volatile u32*)(INCA_IP_GPTU+ 0x0040)) -#define INCA_IP_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Register***/ -#define INCA_IP_GPTU_GPT_T6 ((volatile u32*)(INCA_IP_GPTU+ 0x0044)) -#define INCA_IP_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Control Register***/ -#define INCA_IP_GPTU_GPT_T6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0020)) -#define INCA_IP_GPTU_GPT_T6CON_T6SR (1 << 15) -#define INCA_IP_GPTU_GPT_T6CON_T6CLR (1 << 14) -#define INCA_IP_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define INCA_IP_GPTU_GPT_T6CON_T6OTL (1 << 10) -#define INCA_IP_GPTU_GPT_T6CON_T6UD (1 << 7) -#define INCA_IP_GPTU_GPT_T6CON_T6R (1 << 6) -#define INCA_IP_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 6 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0054)) -#define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) -#define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) - -/***GPT Timer 5 Control Register***/ -#define INCA_IP_GPTU_GPT_T5CON ((volatile u32*)(INCA_IP_GPTU+ 0x001C)) -#define INCA_IP_GPTU_GPT_T5CON_T5SC (1 << 15) -#define INCA_IP_GPTU_GPT_T5CON_T5CLR (1 << 14) -#define INCA_IP_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12) -#define INCA_IP_GPTU_GPT_T5CON_T5CC (1 << 11) -#define INCA_IP_GPTU_GPT_T5CON_CT3 (1 << 10) -#define INCA_IP_GPTU_GPT_T5CON_T5RC (1 << 9) -#define INCA_IP_GPTU_GPT_T5CON_T5UDE (1 << 8) -#define INCA_IP_GPTU_GPT_T5CON_T5UD (1 << 7) -#define INCA_IP_GPTU_GPT_T5CON_T5R (1 << 6) -#define INCA_IP_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : IOM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_IOM (0xBF105000) -/***********************************************************************/ - - -/***Receive FIFO***/ -#define INCA_IP_IOM_RFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) -#define INCA_IP_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Transmit FIFO***/ -#define INCA_IP_IOM_XFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) -#define INCA_IP_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Interrupt Status Register HDLC***/ -#define INCA_IP_IOM_ISTAH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) -#define INCA_IP_IOM_ISTAH_RME (1 << 7) -#define INCA_IP_IOM_ISTAH_RPF (1 << 6) -#define INCA_IP_IOM_ISTAH_RFO (1 << 5) -#define INCA_IP_IOM_ISTAH_XPR (1 << 4) -#define INCA_IP_IOM_ISTAH_XMR (1 << 3) -#define INCA_IP_IOM_ISTAH_XDU (1 << 2) - -/***Interrupt Mask Register HDLC***/ -#define INCA_IP_IOM_MASKH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) -#define INCA_IP_IOM_MASKH_RME (1 << 7) -#define INCA_IP_IOM_MASKH_RPF (1 << 6) -#define INCA_IP_IOM_MASKH_RFO (1 << 5) -#define INCA_IP_IOM_MASKH_XPR (1 << 4) -#define INCA_IP_IOM_MASKH_XMR (1 << 3) -#define INCA_IP_IOM_MASKH_XDU (1 << 2) - -/***Status Register***/ -#define INCA_IP_IOM_STAR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) -#define INCA_IP_IOM_STAR_XDOV (1 << 7) -#define INCA_IP_IOM_STAR_XFW (1 << 6) -#define INCA_IP_IOM_STAR_RACI (1 << 3) -#define INCA_IP_IOM_STAR_XACI (1 << 1) - -/***Command Register***/ -#define INCA_IP_IOM_CMDR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) -#define INCA_IP_IOM_CMDR_RMC (1 << 7) -#define INCA_IP_IOM_CMDR_RRES (1 << 6) -#define INCA_IP_IOM_CMDR_XTF (1 << 3) -#define INCA_IP_IOM_CMDR_XME (1 << 1) -#define INCA_IP_IOM_CMDR_XRES (1 << 0) - -/***Mode Register***/ -#define INCA_IP_IOM_MODEH ((volatile u32*)(INCA_IP_IOM+ 0x0088)) -#define INCA_IP_IOM_MODEH_MDS2 (1 << 7) -#define INCA_IP_IOM_MODEH_MDS1 (1 << 6) -#define INCA_IP_IOM_MODEH_MDS0 (1 << 5) -#define INCA_IP_IOM_MODEH_RAC (1 << 3) -#define INCA_IP_IOM_MODEH_DIM2 (1 << 2) -#define INCA_IP_IOM_MODEH_DIM1 (1 << 1) -#define INCA_IP_IOM_MODEH_DIM0 (1 << 0) - -/***Extended Mode Register***/ -#define INCA_IP_IOM_EXMR ((volatile u32*)(INCA_IP_IOM+ 0x008C)) -#define INCA_IP_IOM_EXMR_XFBS (1 << 7) -#define INCA_IP_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) -#define INCA_IP_IOM_EXMR_SRA (1 << 4) -#define INCA_IP_IOM_EXMR_XCRC (1 << 3) -#define INCA_IP_IOM_EXMR_RCRC (1 << 2) -#define INCA_IP_IOM_EXMR_ITF (1 << 0) - -/***SAPI1 Register***/ -#define INCA_IP_IOM_SAP1 ((volatile u32*)(INCA_IP_IOM+ 0x0094)) -#define INCA_IP_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_SAP1_MHA (1 << 0) - -/***Receive Frame Byte Count Low***/ -#define INCA_IP_IOM_RBCL ((volatile u32*)(INCA_IP_IOM+ 0x0098)) -#define INCA_IP_IOM_RBCL_RBC(value) (1 << value) - - -/***SAPI2 Register***/ -#define INCA_IP_IOM_SAP2 ((volatile u32*)(INCA_IP_IOM+ 0x0098)) -#define INCA_IP_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_SAP2_MLA (1 << 0) - -/***Receive Frame Byte Count High***/ -#define INCA_IP_IOM_RBCH ((volatile u32*)(INCA_IP_IOM+ 0x009C)) -#define INCA_IP_IOM_RBCH_OV (1 << 4) -#define INCA_IP_IOM_RBCH_RBC11 (1 << 3) -#define INCA_IP_IOM_RBCH_RBC10 (1 << 2) -#define INCA_IP_IOM_RBCH_RBC9 (1 << 1) -#define INCA_IP_IOM_RBCH_RBC8 (1 << 0) - -/***TEI1 Register 1***/ -#define INCA_IP_IOM_TEI1 ((volatile u32*)(INCA_IP_IOM+ 0x009C)) -#define INCA_IP_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define INCA_IP_IOM_TEI1_EA (1 << 0) - -/***Receive Status Register***/ -#define INCA_IP_IOM_RSTA ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) -#define INCA_IP_IOM_RSTA_VFR (1 << 7) -#define INCA_IP_IOM_RSTA_RDO (1 << 6) -#define INCA_IP_IOM_RSTA_CRC (1 << 5) -#define INCA_IP_IOM_RSTA_RAB (1 << 4) -#define INCA_IP_IOM_RSTA_SA1 (1 << 3) -#define INCA_IP_IOM_RSTA_SA0 (1 << 2) -#define INCA_IP_IOM_RSTA_TA (1 << 0) -#define INCA_IP_IOM_RSTA_CR (1 << 1) - -/***TEI2 Register***/ -#define INCA_IP_IOM_TEI2 ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) -#define INCA_IP_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define INCA_IP_IOM_TEI2_EA (1 << 0) - -/***Test Mode Register HDLC***/ -#define INCA_IP_IOM_TMH ((volatile u32*)(INCA_IP_IOM+ 0x00A4)) -#define INCA_IP_IOM_TMH_TLP (1 << 0) - -/***Command/Indication Receive 0***/ -#define INCA_IP_IOM_CIR0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) -#define INCA_IP_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_IOM_CIR0_CIC0 (1 << 3) -#define INCA_IP_IOM_CIR0_CIC1 (1 << 2) -#define INCA_IP_IOM_CIR0_SG (1 << 1) -#define INCA_IP_IOM_CIR0_BAS (1 << 0) - -/***Command/Indication Transmit 0***/ -#define INCA_IP_IOM_CIX0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) -#define INCA_IP_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_IOM_CIX0_TBA2 (1 << 3) -#define INCA_IP_IOM_CIX0_TBA1 (1 << 2) -#define INCA_IP_IOM_CIX0_TBA0 (1 << 1) -#define INCA_IP_IOM_CIX0_BAC (1 << 0) - -/***Command/Indication Receive 1***/ -#define INCA_IP_IOM_CIR1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) -#define INCA_IP_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) - -/***Command/Indication Transmit 1***/ -#define INCA_IP_IOM_CIX1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) -#define INCA_IP_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_CIX1_CICW (1 << 1) -#define INCA_IP_IOM_CIX1_CI1E (1 << 0) - -/***Controller Data Access Reg. (CH10)***/ -#define INCA_IP_IOM_CDA10 ((volatile u32*)(INCA_IP_IOM+ 0x0100)) -#define INCA_IP_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH11)***/ -#define INCA_IP_IOM_CDA11 ((volatile u32*)(INCA_IP_IOM+ 0x0104)) -#define INCA_IP_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH20)***/ -#define INCA_IP_IOM_CDA20 ((volatile u32*)(INCA_IP_IOM+ 0x0108)) -#define INCA_IP_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH21)***/ -#define INCA_IP_IOM_CDA21 ((volatile u32*)(INCA_IP_IOM+ 0x010C)) -#define INCA_IP_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define INCA_IP_IOM_CDA_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0110)) -#define INCA_IP_IOM_CDA_TSDP10_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define INCA_IP_IOM_CDA_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0114)) -#define INCA_IP_IOM_CDA_TSDP11_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define INCA_IP_IOM_CDA_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0118)) -#define INCA_IP_IOM_CDA_TSDP20_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define INCA_IP_IOM_CDA_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x011C)) -#define INCA_IP_IOM_CDA_TSDP21_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define INCA_IP_IOM_CO_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0120)) -#define INCA_IP_IOM_CO_TSDP10_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define INCA_IP_IOM_CO_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0124)) -#define INCA_IP_IOM_CO_TSDP11_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define INCA_IP_IOM_CO_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0128)) -#define INCA_IP_IOM_CO_TSDP20_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define INCA_IP_IOM_CO_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x012C)) -#define INCA_IP_IOM_CO_TSDP21_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define INCA_IP_IOM_CDA1_CR ((volatile u32*)(INCA_IP_IOM+ 0x0138)) -#define INCA_IP_IOM_CDA1_CR_EN_TBM (1 << 5) -#define INCA_IP_IOM_CDA1_CR_EN_I1 (1 << 4) -#define INCA_IP_IOM_CDA1_CR_EN_I0 (1 << 3) -#define INCA_IP_IOM_CDA1_CR_EN_O1 (1 << 2) -#define INCA_IP_IOM_CDA1_CR_EN_O0 (1 << 1) -#define INCA_IP_IOM_CDA1_CR_SWAP (1 << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define INCA_IP_IOM_CDA2_CR ((volatile u32*)(INCA_IP_IOM+ 0x013C)) -#define INCA_IP_IOM_CDA2_CR_EN_TBM (1 << 5) -#define INCA_IP_IOM_CDA2_CR_EN_I1 (1 << 4) -#define INCA_IP_IOM_CDA2_CR_EN_I0 (1 << 3) -#define INCA_IP_IOM_CDA2_CR_EN_O1 (1 << 2) -#define INCA_IP_IOM_CDA2_CR_EN_O0 (1 << 1) -#define INCA_IP_IOM_CDA2_CR_SWAP (1 << 0) - -/***Control Register B-Channel Data***/ -#define INCA_IP_IOM_BCHA_CR ((volatile u32*)(INCA_IP_IOM+ 0x0144)) -#define INCA_IP_IOM_BCHA_CR_EN_BC2 (1 << 4) -#define INCA_IP_IOM_BCHA_CR_EN_BC1 (1 << 3) - -/***Control Register B-Channel Data***/ -#define INCA_IP_IOM_BCHB_CR ((volatile u32*)(INCA_IP_IOM+ 0x0148)) -#define INCA_IP_IOM_BCHB_CR_EN_BC2 (1 << 4) -#define INCA_IP_IOM_BCHB_CR_EN_BC1 (1 << 3) - -/***Control Reg. for HDLC and CI1 Data***/ -#define INCA_IP_IOM_DCI_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) -#define INCA_IP_IOM_DCI_CR_DPS_CI1 (1 << 7) -#define INCA_IP_IOM_DCI_CR_EN_CI1 (1 << 6) -#define INCA_IP_IOM_DCI_CR_EN_D (1 << 5) - -/***Control Reg. for HDLC and CI1 Data***/ -#define INCA_IP_IOM_DCIC_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) -#define INCA_IP_IOM_DCIC_CR_DPS_CI0 (1 << 7) -#define INCA_IP_IOM_DCIC_CR_EN_CI0 (1 << 6) -#define INCA_IP_IOM_DCIC_CR_DPS_D (1 << 5) - -/***Control Reg. Serial Data Strobe x***/ -#define INCA_IP_IOM_SDS_CR ((volatile u32*)(INCA_IP_IOM+ 0x0154)) -#define INCA_IP_IOM_SDS_CR_ENS_TSS (1 << 7) -#define INCA_IP_IOM_SDS_CR_ENS_TSS_1 (1 << 6) -#define INCA_IP_IOM_SDS_CR_ENS_TSS_3 (1 << 5) -#define INCA_IP_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Control Register IOM Data***/ -#define INCA_IP_IOM_IOM_CR ((volatile u32*)(INCA_IP_IOM+ 0x015C)) -#define INCA_IP_IOM_IOM_CR_SPU (1 << 7) -#define INCA_IP_IOM_IOM_CR_CI_CS (1 << 5) -#define INCA_IP_IOM_IOM_CR_TIC_DIS (1 << 4) -#define INCA_IP_IOM_IOM_CR_EN_BCL (1 << 3) -#define INCA_IP_IOM_IOM_CR_CLKM (1 << 2) -#define INCA_IP_IOM_IOM_CR_Res (1 << 1) -#define INCA_IP_IOM_IOM_CR_DIS_IOM (1 << 0) - -/***Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_STI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) -#define INCA_IP_IOM_STI_STOV21 (1 << 7) -#define INCA_IP_IOM_STI_STOV20 (1 << 6) -#define INCA_IP_IOM_STI_STOV11 (1 << 5) -#define INCA_IP_IOM_STI_STOV10 (1 << 4) -#define INCA_IP_IOM_STI_STI21 (1 << 3) -#define INCA_IP_IOM_STI_STI20 (1 << 2) -#define INCA_IP_IOM_STI_STI11 (1 << 1) -#define INCA_IP_IOM_STI_STI10 (1 << 0) - -/***Acknowledge Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_ASTI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) -#define INCA_IP_IOM_ASTI_ACK21 (1 << 3) -#define INCA_IP_IOM_ASTI_ACK20 (1 << 2) -#define INCA_IP_IOM_ASTI_ACK11 (1 << 1) -#define INCA_IP_IOM_ASTI_ACK10 (1 << 0) - -/***Mask Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_MSTI ((volatile u32*)(INCA_IP_IOM+ 0x0164)) -#define INCA_IP_IOM_MSTI_STOV21 (1 << 7) -#define INCA_IP_IOM_MSTI_STOV20 (1 << 6) -#define INCA_IP_IOM_MSTI_STOV11 (1 << 5) -#define INCA_IP_IOM_MSTI_STOV10 (1 << 4) -#define INCA_IP_IOM_MSTI_STI21 (1 << 3) -#define INCA_IP_IOM_MSTI_STI20 (1 << 2) -#define INCA_IP_IOM_MSTI_STI11 (1 << 1) -#define INCA_IP_IOM_MSTI_STI10 (1 << 0) - -/***Configuration Register for Serial Data Strobes***/ -#define INCA_IP_IOM_SDS_CONF ((volatile u32*)(INCA_IP_IOM+ 0x0168)) -#define INCA_IP_IOM_SDS_CONF_SDS_BCL (1 << 0) - -/***Monitoring CDA Bits***/ -#define INCA_IP_IOM_MCDA ((volatile u32*)(INCA_IP_IOM+ 0x016C)) -#define INCA_IP_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : ASC register address and bits */ -/***********************************************************************/ - -#if defined(CONFIG_INCA_IP) -#define INCA_IP_ASC (0xB8000400) -#elif defined(CONFIG_PURPLE) -#define INCA_IP_ASC (0xBE500000) -#endif - -/***********************************************************************/ - - -/***ASC Port Input Select Register***/ -#define INCA_IP_ASC_ASC_PISEL ((volatile u32*)(INCA_IP_ASC+ 0x0004)) -#define INCA_IP_ASC_ASC_PISEL_RIS (1 << 0) - -/***ASC Control Register***/ -#define INCA_IP_ASC_ASC_CON ((volatile u32*)(INCA_IP_ASC+ 0x0010)) -#define INCA_IP_ASC_ASC_CON_R (1 << 15) -#define INCA_IP_ASC_ASC_CON_LB (1 << 14) -#define INCA_IP_ASC_ASC_CON_BRS (1 << 13) -#define INCA_IP_ASC_ASC_CON_ODD (1 << 12) -#define INCA_IP_ASC_ASC_CON_FDE (1 << 11) -#define INCA_IP_ASC_ASC_CON_OE (1 << 10) -#define INCA_IP_ASC_ASC_CON_FE (1 << 9) -#define INCA_IP_ASC_ASC_CON_PE (1 << 8) -#define INCA_IP_ASC_ASC_CON_OEN (1 << 7) -#define INCA_IP_ASC_ASC_CON_FEN (1 << 6) -#define INCA_IP_ASC_ASC_CON_PENRXDI (1 << 5) -#define INCA_IP_ASC_ASC_CON_REN (1 << 4) -#define INCA_IP_ASC_ASC_CON_STP (1 << 3) -#define INCA_IP_ASC_ASC_CON_M (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***ASC Write Hardware Modified Control Register***/ -#define INCA_IP_ASC_ASC_WHBCON ((volatile u32*)(INCA_IP_ASC+ 0x0050)) -#define INCA_IP_ASC_ASC_WHBCON_SETOE (1 << 13) -#define INCA_IP_ASC_ASC_WHBCON_SETFE (1 << 12) -#define INCA_IP_ASC_ASC_WHBCON_SETPE (1 << 11) -#define INCA_IP_ASC_ASC_WHBCON_CLROE (1 << 10) -#define INCA_IP_ASC_ASC_WHBCON_CLRFE (1 << 9) -#define INCA_IP_ASC_ASC_WHBCON_CLRPE (1 << 8) -#define INCA_IP_ASC_ASC_WHBCON_SETREN (1 << 5) -#define INCA_IP_ASC_ASC_WHBCON_CLRREN (1 << 4) - -/***ASC Baudrate Timer/Reload Register***/ -#define INCA_IP_ASC_ASC_BTR ((volatile u32*)(INCA_IP_ASC+ 0x0014)) -#define INCA_IP_ASC_ASC_BTR_BR_VALUE (value) (((( 1 << 13) - 1) & (value)) << 0) - -/***ASC Fractional Divider Register***/ -#define INCA_IP_ASC_ASC_FDV ((volatile u32*)(INCA_IP_ASC+ 0x0018)) -#define INCA_IP_ASC_ASC_FDV_FD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC IrDA Pulse Mode/Width Register***/ -#define INCA_IP_ASC_ASC_PMW ((volatile u32*)(INCA_IP_ASC+ 0x001C)) -#define INCA_IP_ASC_ASC_PMW_IRPW (1 << 8) -#define INCA_IP_ASC_ASC_PMW_PW_VALUE (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***ASC Transmit Buffer Register***/ -#define INCA_IP_ASC_ASC_TBUF ((volatile u32*)(INCA_IP_ASC+ 0x0020)) -#define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Receive Buffer Register***/ -#define INCA_IP_ASC_ASC_RBUF ((volatile u32*)(INCA_IP_ASC+ 0x0024)) -#define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Autobaud Control Register***/ -#define INCA_IP_ASC_ASC_ABCON ((volatile u32*)(INCA_IP_ASC+ 0x0030)) -#define INCA_IP_ASC_ASC_ABCON_RXINV (1 << 11) -#define INCA_IP_ASC_ASC_ABCON_TXINV (1 << 10) -#define INCA_IP_ASC_ASC_ABCON_ABEM (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_ASC_ASC_ABCON_FCDETEN (1 << 4) -#define INCA_IP_ASC_ASC_ABCON_ABDETEN (1 << 3) -#define INCA_IP_ASC_ASC_ABCON_ABSTEN (1 << 2) -#define INCA_IP_ASC_ASC_ABCON_AUREN (1 << 1) -#define INCA_IP_ASC_ASC_ABCON_ABEN (1 << 0) - -/***Receive FIFO Control Register***/ -#define INCA_IP_ASC_RXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0040)) -#define INCA_IP_ASC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_ASC_RXFCON_RXFFLU (1 << 1) -#define INCA_IP_ASC_RXFCON_RXFEN (1 << 0) - -/***Transmit FIFO Control Register***/ -#define INCA_IP_ASC_TXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0044)) -#define INCA_IP_ASC_TXFCON_TXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_ASC_TXFCON_TXFFLU (1 << 1) -#define INCA_IP_ASC_TXFCON_TXFEN (1 << 0) - -/***FIFO Status Register***/ -#define INCA_IP_ASC_FSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0048)) -#define INCA_IP_ASC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***ASC Write HW Modified Autobaud Control Register***/ -#define INCA_IP_ASC_ASC_WHBABCON ((volatile u32*)(INCA_IP_ASC+ 0x0054)) -#define INCA_IP_ASC_ASC_WHBABCON_SETABEN (1 << 1) -#define INCA_IP_ASC_ASC_WHBABCON_CLRABEN (1 << 0) - -/***ASC Autobaud Status Register***/ -#define INCA_IP_ASC_ASC_ABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0034)) -#define INCA_IP_ASC_ASC_ABSTAT_DETWAIT (1 << 4) -#define INCA_IP_ASC_ASC_ABSTAT_SCCDET (1 << 3) -#define INCA_IP_ASC_ASC_ABSTAT_SCSDET (1 << 2) -#define INCA_IP_ASC_ASC_ABSTAT_FCCDET (1 << 1) -#define INCA_IP_ASC_ASC_ABSTAT_FCSDET (1 << 0) - -/***ASC Write HW Modified Autobaud Status Register***/ -#define INCA_IP_ASC_ASC_WHBABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0058)) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT (1 << 9) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCCDET (1 << 7) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCCDET (1 << 6) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCSDET (1 << 5) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCSDET (1 << 4) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCCDET (1 << 3) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET (1 << 2) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET (1 << 1) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET (1 << 0) - -/***ASC Clock Control Register***/ -#define INCA_IP_ASC_ASC_CLC ((volatile u32*)(INCA_IP_ASC+ 0x0000)) -#define INCA_IP_ASC_ASC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_ASC_ASC_CLC_DISS (1 << 1) -#define INCA_IP_ASC_ASC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define INCA_IP_DMA (0xBF108000) -/***********************************************************************/ - - -/***DMA RX Channel 0 Command Register***/ -#define INCA_IP_DMA_DMA_RXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0800)) -#define INCA_IP_DMA_DMA_RXCCR0_LBE (1 << 31) -#define INCA_IP_DMA_DMA_RXCCR0_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_RXCCR0_INIT (1 << 2) -#define INCA_IP_DMA_DMA_RXCCR0_OFF (1 << 1) -#define INCA_IP_DMA_DMA_RXCCR0_HR (1 << 0) - -/***DMA RX Channel 1 Command Register***/ -#define INCA_IP_DMA_DMA_RXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0804)) -#define INCA_IP_DMA_DMA_RXCCR1_LBE (1 << 31) -#define INCA_IP_DMA_DMA_RXCCR1_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_RXCCR1_INIT (1 << 2) -#define INCA_IP_DMA_DMA_RXCCR1_OFF (1 << 1) -#define INCA_IP_DMA_DMA_RXCCR1_HR (1 << 0) - -/***DMA Receive Interrupt Status Register***/ -#define INCA_IP_DMA_DMA_RXISR ((volatile u32*)(INCA_IP_DMA+ 0x0808)) -#define INCA_IP_DMA_DMA_RXISR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_RXISR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_RXISR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_RXISR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA Receive Interrupt Mask Register***/ -#define INCA_IP_DMA_DMA_RXIMR ((volatile u32*)(INCA_IP_DMA+ 0x080C)) -#define INCA_IP_DMA_DMA_RXIMR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_RXIMR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_RXIMR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_RXIMR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Rx Channel 0 -***/ -#define INCA_IP_DMA_DMA_RXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x0810)) -#define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Rx Channel 1 -***/ -#define INCA_IP_DMA_DMA_RXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x0814)) -#define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA Receive Channel Polling Time***/ -#define INCA_IP_DMA_DMA_RXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x0818)) -#define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 30) -#define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 28) -#define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***DMA TX Channel 0 Command Register (Voice Port)***/ -#define INCA_IP_DMA_DMA_TXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0880)) -#define INCA_IP_DMA_DMA_TXCCR0_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR0_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR0_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR0_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR0_INIT (1 << 0) - -/***DMA TX Channel 1 Command Register (Mangmt Port)***/ -#define INCA_IP_DMA_DMA_TXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0884)) -#define INCA_IP_DMA_DMA_TXCCR1_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR1_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR1_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR1_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR1_INIT (1 << 0) - -/***DMA TX Channel 2 Command Register (SSC Port)***/ -#define INCA_IP_DMA_DMA_TXCCR2 ((volatile u32*)(INCA_IP_DMA+ 0x0888)) -#define INCA_IP_DMA_DMA_TXCCR2_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR2_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR2_HBF (1 << 29) -#define INCA_IP_DMA_DMA_TXCCR2_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR2_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR2_INIT (1 << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 0 -***/ -#define INCA_IP_DMA_DMA_TXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x08A0)) -#define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 1 -***/ -#define INCA_IP_DMA_DMA_TXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x08A4)) -#define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 2 -***/ -#define INCA_IP_DMA_DMA_TXFRDA2 ((volatile u32*)(INCA_IP_DMA+ 0x08A8)) -#define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA Transmit Channel Arbitration Register***/ -#define INCA_IP_DMA_DMA_TXWGT ((volatile u32*)(INCA_IP_DMA+ 0x08C0)) -#define INCA_IP_DMA_DMA_TXWGT_TX2PR (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA Transmit Channel Polling Time***/ -#define INCA_IP_DMA_DMA_TXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x08C4)) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value) (((( 1 << 2) - 1) & (value)) << 30) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 28) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***DMA Transmit Interrupt Status Register***/ -#define INCA_IP_DMA_DMA_TXISR ((volatile u32*)(INCA_IP_DMA+ 0x08C8)) -#define INCA_IP_DMA_DMA_TXISR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_DMA_DMA_TXISR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) -#define INCA_IP_DMA_DMA_TXISR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_TXISR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***DMA Transmit Interrupt Mask Register***/ -#define INCA_IP_DMA_DMA_TXIMR ((volatile u32*)(INCA_IP_DMA+ 0x08CC)) -#define INCA_IP_DMA_DMA_TXIMR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_DMA_DMA_TXIMR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) -#define INCA_IP_DMA_DMA_TXIMR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_TXIMR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : Debug register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Debug (0xBF106000) -/***********************************************************************/ - - -/***MCD Break Bus Switch Register***/ -#define INCA_IP_Debug_MCD_BBS ((volatile u32*)(INCA_IP_Debug+ 0x0000)) -#define INCA_IP_Debug_MCD_BBS_BTP1 (1 << 19) -#define INCA_IP_Debug_MCD_BBS_BTP0 (1 << 18) -#define INCA_IP_Debug_MCD_BBS_BSP1 (1 << 17) -#define INCA_IP_Debug_MCD_BBS_BSP0 (1 << 16) -#define INCA_IP_Debug_MCD_BBS_BT5EN (1 << 15) -#define INCA_IP_Debug_MCD_BBS_BT4EN (1 << 14) -#define INCA_IP_Debug_MCD_BBS_BT5 (1 << 13) -#define INCA_IP_Debug_MCD_BBS_BT4 (1 << 12) -#define INCA_IP_Debug_MCD_BBS_BS5EN (1 << 7) -#define INCA_IP_Debug_MCD_BBS_BS4EN (1 << 6) -#define INCA_IP_Debug_MCD_BBS_BS5 (1 << 5) -#define INCA_IP_Debug_MCD_BBS_BS4 (1 << 4) - -/***MCD Multiplexer Control Register***/ -#define INCA_IP_Debug_MCD_MCR ((volatile u32*)(INCA_IP_Debug+ 0x0008)) -#define INCA_IP_Debug_MCD_MCR_MUX5 (1 << 4) -#define INCA_IP_Debug_MCD_MCR_MUX4 (1 << 3) -#define INCA_IP_Debug_MCD_MCR_MUX1 (1 << 0) - -/***********************************************************************/ -/* Module : TSF register address and bits */ -/***********************************************************************/ - -#define INCA_IP_TSF (0xB8000900) -/***********************************************************************/ - - -/***TSF Configuration Register (0000H)***/ -#define INCA_IP_TSF_TSF_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0000)) -#define INCA_IP_TSF_TSF_CONF_PWMEN (1 << 2) -#define INCA_IP_TSF_TSF_CONF_LEDEN (1 << 1) -#define INCA_IP_TSF_TSF_CONF_KEYEN (1 << 0) - -/***Key scan Configuration Register (0004H)***/ -#define INCA_IP_TSF_KEY_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0004)) -#define INCA_IP_TSF_KEY_CONF_SL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Scan Register Line 0 and 1 (0008H)***/ -#define INCA_IP_TSF_SREG01 ((volatile u32*)(INCA_IP_TSF+ 0x0008)) -#define INCA_IP_TSF_SREG01_RES1x (value) (((( 1 << 12) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG01_RES0x (value) (((( 1 << 13) - 1) & (value)) << 0) - -/***Scan Register Line 2 and 3 (000CH)***/ -#define INCA_IP_TSF_SREG23 ((volatile u32*)(INCA_IP_TSF+ 0x000C)) -#define INCA_IP_TSF_SREG23_RES3x (value) (((( 1 << 10) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG23_RES2x (value) (((( 1 << 11) - 1) & (value)) << 0) - -/***Scan Register Line 4, 5 and 6 (0010H)***/ -#define INCA_IP_TSF_SREG456 ((volatile u32*)(INCA_IP_TSF+ 0x0010)) -#define INCA_IP_TSF_SREG456_RES6x (value) (((( 1 << 7) - 1) & (value)) << 24) -#define INCA_IP_TSF_SREG456_RES5x (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG456_RES4x (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***Scan Register Line 7 to 12 (0014H)***/ -#define INCA_IP_TSF_SREG7to12 ((volatile u32*)(INCA_IP_TSF+ 0x0014)) -#define INCA_IP_TSF_SREG7to12_RES12x (1 << 28) -#define INCA_IP_TSF_SREG7to12_RES11x (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_TSF_SREG7to12_RES10x (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_TSF_SREG7to12_RES9x (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG7to12_RES8x (value) (((( 1 << 5) - 1) & (value)) << 8) -#define INCA_IP_TSF_SREG7to12_RES7x (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***LEDMUX Configuration Register (0018H)***/ -#define INCA_IP_TSF_LEDMUX_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0018)) -#define INCA_IP_TSF_LEDMUX_CONF_ETL1 (1 << 25) -#define INCA_IP_TSF_LEDMUX_CONF_ESTA1 (1 << 24) -#define INCA_IP_TSF_LEDMUX_CONF_EDPX1 (1 << 23) -#define INCA_IP_TSF_LEDMUX_CONF_EACT1 (1 << 22) -#define INCA_IP_TSF_LEDMUX_CONF_ESPD1 (1 << 21) -#define INCA_IP_TSF_LEDMUX_CONF_ETL0 (1 << 20) -#define INCA_IP_TSF_LEDMUX_CONF_ESTA0 (1 << 19) -#define INCA_IP_TSF_LEDMUX_CONF_EDPX0 (1 << 18) -#define INCA_IP_TSF_LEDMUX_CONF_EACT0 (1 << 17) -#define INCA_IP_TSF_LEDMUX_CONF_ESPD0 (1 << 16) -#define INCA_IP_TSF_LEDMUX_CONF_INV (1 << 1) -#define INCA_IP_TSF_LEDMUX_CONF_NCOL (1 << 0) - -/***LED Register (001CH)***/ -#define INCA_IP_TSF_LED_REG ((volatile u32*)(INCA_IP_TSF+ 0x001C)) -#define INCA_IP_TSF_LED_REG_Lxy (value) (((( 1 << 24) - 1) & (value)) << 0) - -/***Pulse Width Modulator 1 and 2 Register (0020H)***/ -#define INCA_IP_TSF_PWM12 ((volatile u32*)(INCA_IP_TSF+ 0x0020)) -#define INCA_IP_TSF_PWM12_PW2PW1 (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***********************************************************************/ -/* Module : Ports register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Ports (0xB8000A00) -/***********************************************************************/ - - -/***Port 1 Data Output Register (0020H)***/ -#define INCA_IP_Ports_P1_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0020)) -#define INCA_IP_Ports_P1_OUT_P(value) (1 << value) - - -/***Port 2 Data Output Register (0040H)***/ -#define INCA_IP_Ports_P2_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0040)) -#define INCA_IP_Ports_P2_OUT_P(value) (1 << value) - - -/***Port 1 Data Input Register (0024H)***/ -#define INCA_IP_Ports_P1_IN ((volatile u32*)(INCA_IP_Ports+ 0x0024)) -#define INCA_IP_Ports_P1_IN_P(value) (1 << value) - - -/***Port 2 Data Input Register (0044H)***/ -#define INCA_IP_Ports_P2_IN ((volatile u32*)(INCA_IP_Ports+ 0x0044)) -#define INCA_IP_Ports_P2_IN_P(value) (1 << value) - - -/***Port 1 Direction Register (0028H)***/ -#define INCA_IP_Ports_P1_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0028)) -#define INCA_IP_Ports_P1_DIR_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Port 2 Direction Register (0048H)***/ -#define INCA_IP_Ports_P2_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0048)) -#define INCA_IP_Ports_P2_DIR_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Port 0 Alternate Function Select Register 0 (000C H) -***/ -#define INCA_IP_Ports_P0_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x000C)) -#define INCA_IP_Ports_P0_ALTSEL_Port0P(value) (1 << value) - - -/***Port 1 Alternate Function Select Register 0 (002C H) -***/ -#define INCA_IP_Ports_P1_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x002C)) -#define INCA_IP_Ports_P1_ALTSEL_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_ALTSEL_Port2P(value) (1 << value) - - -/***Port 2 Alternate Function Select Register 0 (004C H) -***/ -#define INCA_IP_Ports_P2_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x004C)) -#define INCA_IP_Ports_P2_ALTSEL_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_ALTSEL_Port2P(value) (1 << value) - - -/***Port 0 Input Schmitt-Trigger Off Register (0010 H) -***/ -#define INCA_IP_Ports_P0_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0010)) -#define INCA_IP_Ports_P0_STOFF_Port0P(value) (1 << value) - - -/***Port 1 Input Schmitt-Trigger Off Register (0030 H) -***/ -#define INCA_IP_Ports_P1_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0030)) -#define INCA_IP_Ports_P1_STOFF_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_STOFF_Port2P(value) (1 << value) - - -/***Port 2 Input Schmitt-Trigger Off Register (0050 H) -***/ -#define INCA_IP_Ports_P2_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0050)) -#define INCA_IP_Ports_P2_STOFF_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_STOFF_Port2P(value) (1 << value) - - -/***Port 2 Open Drain Control Register (0054H)***/ -#define INCA_IP_Ports_P2_OD ((volatile u32*)(INCA_IP_Ports+ 0x0054)) -#define INCA_IP_Ports_P2_OD_Port2P(value) (1 << value) - - -/***Port 0 Pull Up Device Enable Register (0018 H)***/ -#define INCA_IP_Ports_P0_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0018)) -#define INCA_IP_Ports_P0_PUDEN_Port0P(value) (1 << value) - - -/***Port 2 Pull Up Device Enable Register (0058 H)***/ -#define INCA_IP_Ports_P2_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0058)) -#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) - -#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) - - -/***Port 0 Pull Up/Pull Down Select Register (001C H)***/ -#define INCA_IP_Ports_P0_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x001C)) -#define INCA_IP_Ports_P0_PUDSEL_Port0P(value) (1 << value) - - -/***Port 2 Pull Up/Pull Down Select Register (005C H)***/ -#define INCA_IP_Ports_P2_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x005C)) -#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) - -#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) - - -/***********************************************************************/ -/* Module : DES/3DES register address and bits */ -/***********************************************************************/ - -#define INCA_IP_DES_3DES (0xB8000800) -/***********************************************************************/ - - -/***DES Input Data High Register***/ -#define INCA_IP_DES_3DES_DES_IHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000)) -#define INCA_IP_DES_3DES_DES_IHR_IH(value) (1 << value) - - -/***DES Input Data Low Register***/ -#define INCA_IP_DES_3DES_DES_ILR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004)) -#define INCA_IP_DES_3DES_DES_ILR_IL(value) (1 << value) - - -/***DES Key #1 High Register***/ -#define INCA_IP_DES_3DES_DES_K1HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008)) -#define INCA_IP_DES_3DES_DES_K1HR_K1H(value) (1 << value) - - -/***DES Key #1 Low Register***/ -#define INCA_IP_DES_3DES_DES_K1LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C)) -#define INCA_IP_DES_3DES_DES_K1LR_K1L(value) (1 << value) - - -/***DES Key #2 High Register***/ -#define INCA_IP_DES_3DES_DES_K2HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010)) -#define INCA_IP_DES_3DES_DES_K2HR_K2H(value) (1 << value) - - -/***DES Key #2 Low Register***/ -#define INCA_IP_DES_3DES_DES_K2LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014)) -#define INCA_IP_DES_3DES_DES_K2LR_K2L(value) (1 << value) - - -/***DES Key #3 High Register***/ -#define INCA_IP_DES_3DES_DES_K3HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018)) -#define INCA_IP_DES_3DES_DES_K3HR_K3H(value) (1 << value) - - -/***DES Key #3 Low Register***/ -#define INCA_IP_DES_3DES_DES_K3LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C)) -#define INCA_IP_DES_3DES_DES_K3LR_K3L(value) (1 << value) - - -/***DES Initialization Vector High Register***/ -#define INCA_IP_DES_3DES_DES_IVHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020)) -#define INCA_IP_DES_3DES_DES_IVHR_IVH(value) (1 << value) - - -/***DES Initialization Vector Low Register***/ -#define INCA_IP_DES_3DES_DES_IVLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024)) -#define INCA_IP_DES_3DES_DES_IVLR_IVL(value) (1 << value) - - -/***DES Control Register***/ -#define INCA_IP_DES_3DES_DES_CONTROLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028)) -#define INCA_IP_DES_3DES_DES_CONTROLR_KRE (1 << 31) -#define INCA_IP_DES_3DES_DES_CONTROLR_DAU (1 << 16) -#define INCA_IP_DES_3DES_DES_CONTROLR_F(value) (1 << value) - -#define INCA_IP_DES_3DES_DES_CONTROLR_O(value) (1 << value) - -#define INCA_IP_DES_3DES_DES_CONTROLR_GO (1 << 8) -#define INCA_IP_DES_3DES_DES_CONTROLR_STP (1 << 7) -#define INCA_IP_DES_3DES_DES_CONTROLR_IEN (1 << 6) -#define INCA_IP_DES_3DES_DES_CONTROLR_BUS (1 << 5) -#define INCA_IP_DES_3DES_DES_CONTROLR_SM (1 << 4) -#define INCA_IP_DES_3DES_DES_CONTROLR_E_D (1 << 3) -#define INCA_IP_DES_3DES_DES_CONTROLR_M(value) (1 << value) - - -/***DES Output Data High Register***/ -#define INCA_IP_DES_3DES_DES_OHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C)) -#define INCA_IP_DES_3DES_DES_OHR_OH(value) (1 << value) - - -/***DES Output Data Low Register***/ -#define INCA_IP_DES_3DES_DES_OLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030)) -#define INCA_IP_DES_3DES_DES_OLR_OL(value) (1 << value) - - -/***********************************************************************/ -/* Module : AES register address and bits */ -/***********************************************************************/ - -#define INCA_IP_AES (0xB8000880) -/***********************************************************************/ - - -/***AES Input Data 3 Register***/ -#define INCA_IP_AES_AES_ID3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID3R_I(value) (1 << value) - - -/***AES Input Data 2 Register***/ -#define INCA_IP_AES_AES_ID2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID2R_I(value) (1 << value) - - -/***AES Input Data 1 Register***/ -#define INCA_IP_AES_AES_ID1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID1R_I(value) (1 << value) - - -/***AES Input Data 0 Register***/ -#define INCA_IP_AES_AES_ID0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID0R_I(value) (1 << value) - - -/***AES Output Data 3 Register***/ -#define INCA_IP_AES_AES_OD3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD3R_O(value) (1 << value) - - -/***AES Output Data 2 Register***/ -#define INCA_IP_AES_AES_OD2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD2R_O(value) (1 << value) - - -/***AES Output Data 1 Register***/ -#define INCA_IP_AES_AES_OD1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD1R_O(value) (1 << value) - - -/***AES Output Data 0 Register***/ -#define INCA_IP_AES_AES_OD0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD0R_O(value) (1 << value) - - -/***AES Key 7 Register***/ -#define INCA_IP_AES_AES_K7R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K7R_K(value) (1 << value) - - -/***AES Key 6 Register***/ -#define INCA_IP_AES_AES_K6R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K6R_K(value) (1 << value) - - -/***AES Key 5 Register***/ -#define INCA_IP_AES_AES_K5R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K5R_K(value) (1 << value) - - -/***AES Key 4 Register***/ -#define INCA_IP_AES_AES_K4R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K4R_K(value) (1 << value) - - -/***AES Key 3 Register***/ -#define INCA_IP_AES_AES_K3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K3R_K(value) (1 << value) - - -/***AES Key 2 Register***/ -#define INCA_IP_AES_AES_K2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K2R_K(value) (1 << value) - - -/***AES Key 1 Register***/ -#define INCA_IP_AES_AES_K1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K1R_K(value) (1 << value) - - -/***AES Key 0 Register***/ -#define INCA_IP_AES_AES_K0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K0R_K(value) (1 << value) - - -/***AES Initialization Vector 3 Register***/ -#define INCA_IP_AES_AES_IV3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV3R_IV(value) (1 << value) - - -/***AES Initialization Vector 2 Register***/ -#define INCA_IP_AES_AES_IV2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV2R_IV(value) (1 << value) - - -/***AES Initialization Vector 1 Register***/ -#define INCA_IP_AES_AES_IV1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV1R_IV(value) (1 << value) - - -/***AES Initialization Vector 0 Register***/ -#define INCA_IP_AES_AES_IV0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV0R_IV (value) (((( 1 << 32) - 1) &(value)) << 0) - -/***AES Control Register***/ -#define INCA_IP_AES_AES_CONTROLR ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_CONTROLR_KRE (1 << 31) -#define INCA_IP_AES_AES_CONTROLR_DAU (1 << 16) -#define INCA_IP_AES_AES_CONTROLR_PNK (1 << 15) -#define INCA_IP_AES_AES_CONTROLR_F(value) (1 << value) - -#define INCA_IP_AES_AES_CONTROLR_O(value) (1 << value) - -#define INCA_IP_AES_AES_CONTROLR_GO (1 << 8) -#define INCA_IP_AES_AES_CONTROLR_STP (1 << 7) -#define INCA_IP_AES_AES_CONTROLR_IEN (1 << 6) -#define INCA_IP_AES_AES_CONTROLR_BUS (1 << 5) -#define INCA_IP_AES_AES_CONTROLR_SM (1 << 4) -#define INCA_IP_AES_AES_CONTROLR_E_D (1 << 3) -#define INCA_IP_AES_AES_CONTROLR_KV (1 << 2) -#define INCA_IP_AES_AES_CONTROLR_K(value) (1 << value) - - -/***********************************************************************/ -/* Module : I²C register address and bits */ -/***********************************************************************/ - -#define INCA_IP_IIC (0xB8000700) -/***********************************************************************/ - - -/***I²C Port Input Select Register***/ -#define INCA_IP_IIC_IIC_PISEL ((volatile u32*)(INCA_IP_IIC+ 0x0004)) -#define INCA_IP_IIC_IIC_PISEL_SDAIS(value) (1 << value) - -#define INCA_IP_IIC_IIC_PISEL_SCLIS(value) (1 << value) - - -/***I²C Clock Control Register***/ -#define INCA_IP_IIC_IIC_CLC ((volatile u32*)(INCA_IP_IIC+ 0x0000)) -#define INCA_IP_IIC_IIC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_CLC_DISS (1 << 1) -#define INCA_IP_IIC_IIC_CLC_DISR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_0_WMEN (1 << 31) -#define INCA_IP_IIC_IIC_SYSCON_0_CI (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_IIC_IIC_SYSCON_0_STP (1 << 25) -#define INCA_IP_IIC_IIC_SYSCON_0_IGE (1 << 24) -#define INCA_IP_IIC_IIC_SYSCON_0_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_0_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_0_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_0_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_0_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_0_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_0_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_0_RMEN (1 << 15) -#define INCA_IP_IIC_IIC_SYSCON_0_CO (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_0_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_0_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_0_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_0_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_0_ADR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_1_RM (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_IIC_IIC_SYSCON_1_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_1_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_1_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_1_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_1_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_1_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_1_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_1_RMEN (1 << 15) -#define INCA_IP_IIC_IIC_SYSCON_1_CO (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_1_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_1_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_1_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_1_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_1_ADR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_2 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_2_WMEN (1 << 31) -#define INCA_IP_IIC_IIC_SYSCON_2_CI (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_IIC_IIC_SYSCON_2_STP (1 << 25) -#define INCA_IP_IIC_IIC_SYSCON_2_IGE (1 << 24) -#define INCA_IP_IIC_IIC_SYSCON_2_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_2_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_2_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_2_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_2_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_2_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_2_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_2_WM (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_2_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_2_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_2_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_2_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_2_ADR (1 << 0) - -/***I²C Write Hardware Modified System Control Register -***/ -#define INCA_IP_IIC_IIC_WHBSYSCON ((volatile u32*)(INCA_IP_IIC+ 0x0020)) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRWMEN (1 << 31) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETWMEN (1 << 30) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETSTP (1 << 26) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRSTP (1 << 25) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETTRX (1 << 24) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRTRX (1 << 23) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETACKDIS (1 << 22) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETBUM (1 << 20) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRBUM (1 << 19) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETRSC (1 << 17) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRSC (1 << 16) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETRMEN (1 << 15) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRMEN (1 << 14) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQE (1 << 10) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQP (1 << 9) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQD (1 << 8) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQE (1 << 7) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQP (1 << 6) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQD (1 << 5) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETAL (1 << 2) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRAL (1 << 1) - -/***I²C Bus Control Register***/ -#define INCA_IP_IIC_IIC_BUSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) -#define INCA_IP_IIC_IIC_BUSCON_0_BRPMOD (1 << 31) -#define INCA_IP_IIC_IIC_BUSCON_0_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_IIC_IIC_BUSCON_0_ICA9_0 (value) (((( 1 << 10) - 1) & (value)) << 16) -#define INCA_IP_IIC_IIC_BUSCON_0_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_BUSCON_0_SCLEN(value) (1 << value) - -#define INCA_IP_IIC_IIC_BUSCON_0_SDAEN(value) (1 << value) - - -/***I²C Bus Control Register***/ -#define INCA_IP_IIC_IIC_BUSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) -#define INCA_IP_IIC_IIC_BUSCON_1_BRPMOD (1 << 31) -#define INCA_IP_IIC_IIC_BUSCON_1_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_IIC_IIC_BUSCON_1_ICA7_1 (value) (((( 1 << 7) - 1) & (value)) << 17) -#define INCA_IP_IIC_IIC_BUSCON_1_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_BUSCON_1_SCLEN(value) (1 << value) - -#define INCA_IP_IIC_IIC_BUSCON_1_SDAEN(value) (1 << value) - - -/***I²C Receive Transmit Buffer***/ -#define INCA_IP_IIC_IIC_RTB ((volatile u32*)(INCA_IP_IIC+ 0x0018)) -#define INCA_IP_IIC_IIC_RTB_RTB(value) (1 << value) - - -/***********************************************************************/ -/* Module : FB register address and bits */ -/***********************************************************************/ - -#define INCA_IP_FB (0xBF880000) -/***********************************************************************/ - - -/***FB Access Error Cause Register***/ -#define INCA_IP_FB_FB_ERRCAUSE ((volatile u32*)(INCA_IP_FB+ 0x0100)) -#define INCA_IP_FB_FB_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_FB_FB_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_FB_FB_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***FB Access Error Address Register***/ -#define INCA_IP_FB_FB_ERRADDR ((volatile u32*)(INCA_IP_FB+ 0x0108)) -#define INCA_IP_FB_FB_ERRADDR_ADDR - -/***FB Configuration Register***/ -#define INCA_IP_FB_FB_CFG ((volatile u32*)(INCA_IP_FB+ 0x0800)) -#define INCA_IP_FB_FB_CFG_SVM (1 << 0) - -/***********************************************************************/ -/* Module : SRAM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SRAM (0xBF980000) -/***********************************************************************/ - - -/***SRAM Size Register***/ -#define INCA_IP_SRAM_SRAM_SIZE ((volatile u32*)(INCA_IP_SRAM+ 0x0800)) -#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BIU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_BIU (0xBFA80000) -/***********************************************************************/ - - -/***BIU Identification Register***/ -#define INCA_IP_BIU_BIU_ID ((volatile u32*)(INCA_IP_BIU+ 0x0000)) -#define INCA_IP_BIU_BIU_ID_ARCH (1 << 16) -#define INCA_IP_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***BIU Access Error Cause Register***/ -#define INCA_IP_BIU_BIU_ERRCAUSE ((volatile u32*)(INCA_IP_BIU+ 0x0100)) -#define INCA_IP_BIU_BIU_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***BIU Access Error Address Register***/ -#define INCA_IP_BIU_BIU_ERRADDR ((volatile u32*)(INCA_IP_BIU+ 0x0108)) -#define INCA_IP_BIU_BIU_ERRADDR_ADDR - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_ICU (0xBF101000) -/***********************************************************************/ - - -/***IM0 Interrupt Status Register***/ -#define INCA_IP_ICU_IM0_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0000)) -#define INCA_IP_ICU_IM0_ISR_IR(value) (1 << value) - - -/***IM1 Interrupt Status Register***/ -#define INCA_IP_ICU_IM1_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0200)) -#define INCA_IP_ICU_IM1_ISR_IR(value) (1 << value) - - -/***IM2 Interrupt Status Register***/ -#define INCA_IP_ICU_IM2_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0400)) -#define INCA_IP_ICU_IM2_ISR_IR(value) (1 << value) - - -/***IM0 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM0_IER ((volatile u32*)(INCA_IP_ICU+ 0x0008)) -#define INCA_IP_ICU_IM0_IER_IR(value) (1 << value) - - -/***IM1 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM1_IER ((volatile u32*)(INCA_IP_ICU+ 0x0208)) -#define INCA_IP_ICU_IM1_IER_IR(value) (1 << value) - - -/***IM2 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM2_IER ((volatile u32*)(INCA_IP_ICU+ 0x0408)) -#define INCA_IP_ICU_IM2_IER_IR(value) (1 << value) - - -/***IM0 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM0_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0010)) -#define INCA_IP_ICU_IM0_IOSR_IR(value) (1 << value) - - -/***IM1 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM1_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0210)) -#define INCA_IP_ICU_IM1_IOSR_IR(value) (1 << value) - - -/***IM2 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM2_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0410)) -#define INCA_IP_ICU_IM2_IOSR_IR(value) (1 << value) - - -/***IM0 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM0_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0018)) -#define INCA_IP_ICU_IM0_IRSR_IR(value) (1 << value) - - -/***IM1 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM1_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0218)) -#define INCA_IP_ICU_IM1_IRSR_IR(value) (1 << value) - - -/***IM2 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM2_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0418)) -#define INCA_IP_ICU_IM2_IRSR_IR(value) (1 << value) - - -/***External Interrupt Control Register***/ -#define INCA_IP_ICU_ICU_EICR ((volatile u32*)(INCA_IP_ICU+ 0x0B00)) -#define INCA_IP_ICU_ICU_EICR_EII5 (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_ICU_ICU_EICR_EII4 (value) (((( 1 << 3) - 1) & (value)) << 16) -#define INCA_IP_ICU_ICU_EICR_EII3 (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_ICU_ICU_EICR_EII2 (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_ICU_ICU_EICR_EII1 (value) (((( 1 << 3) - 1) & (value)) << 4) -#define INCA_IP_ICU_ICU_EICR_EII0 (value) (((( 1 << 3) - 1) & (value)) << 0) diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h deleted file mode 100644 index 025012a..0000000 --- a/include/asm-mips/io.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995 Waldorf GmbH - * Copyright (C) 1994 - 2000 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 FSMLabs, Inc. - */ -#ifndef _ASM_IO_H -#define _ASM_IO_H - -#include -#if 0 -#include -#endif -#include -#include - -/* - * Slowdown I/O port space accesses for antique hardware. - */ -#undef CONF_SLOWDOWN_IO - -/* - * Sane hardware offers swapping of I/O space accesses in hardware; less - * sane hardware forces software to fiddle with this ... - */ -#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__) - -#define __ioswab8(x) (x) -#define __ioswab16(x) swab16(x) -#define __ioswab32(x) swab32(x) - -#else - -#define __ioswab8(x) (x) -#define __ioswab16(x) (x) -#define __ioswab32(x) (x) - -#endif - -/* - * This file contains the definitions for the MIPS counterpart of the - * x86 in/out instructions. This heap of macros and C results in much - * better code than the approach of doing it in plain C. The macros - * result in code that is to fast for certain hardware. On the other - * side the performance of the string functions should be improved for - * sake of certain devices like EIDE disks that do highspeed polled I/O. - * - * Ralf - * - * This file contains the definitions for the x86 IO instructions - * inb/inw/inl/outb/outw/outl and the "string versions" of the same - * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" - * versions of the single-IO instructions (inb_p/inw_p/..). - * - * This file is not meant to be obfuscating: it's just complicated - * to (a) handle it all in a way that makes gcc able to optimize it - * as well as possible and (b) trying to avoid writing the same thing - * over and over again with slight variations and possibly making a - * mistake somewhere. - */ - -/* - * On MIPS I/O ports are memory mapped, so we access them using normal - * load/store instructions. mips_io_port_base is the virtual address to - * which all ports are being mapped. For sake of efficiency some code - * assumes that this is an address that can be loaded with a single lui - * instruction, so the lower 16 bits must be zero. Should be true on - * on any sane architecture; generic code does not use this assumption. - */ -extern const unsigned long mips_io_port_base; - -/* - * Gcc will generate code to load the value of mips_io_port_base after each - * function call which may be fairly wasteful in some cases. So we don't - * play quite by the book. We tell gcc mips_io_port_base is a long variable - * which solves the code generation issue. Now we need to violate the - * aliasing rules a little to make initialization possible and finally we - * will need the barrier() to fight side effects of the aliasing chat. - * This trickery will eventually collapse under gcc's optimizer. Oh well. - */ -static inline void set_io_port_base(unsigned long base) -{ - * (unsigned long *) &mips_io_port_base = base; -} - -/* - * Thanks to James van Artsdalen for a better timing-fix than - * the two short jumps: using outb's to a nonexistent port seems - * to guarantee better timings even on fast machines. - * - * On the other hand, I'd like to be sure of a non-existent port: - * I feel a bit unsafe about using 0x80 (should be safe, though) - * - * Linus - * - */ - -#define __SLOW_DOWN_IO \ - __asm__ __volatile__( \ - "sb\t$0,0x80(%0)" \ - : : "r" (mips_io_port_base)); - -#ifdef CONF_SLOWDOWN_IO -#ifdef REALLY_SLOW_IO -#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } -#else -#define SLOW_DOWN_IO __SLOW_DOWN_IO -#endif -#else -#define SLOW_DOWN_IO -#endif - -/* - * Change virtual addresses to physical addresses and vv. - * These are trivial on the 1:1 Linux/MIPS mapping - */ -extern inline phys_addr_t virt_to_phys(volatile void * address) -{ - return CPHYSADDR(address); -} - -extern inline void * phys_to_virt(unsigned long address) -{ - return (void *)KSEG0ADDR(address); -} - -/* - * IO bus memory addresses are also 1:1 with the physical address - */ -extern inline unsigned long virt_to_bus(volatile void * address) -{ - return CPHYSADDR(address); -} - -extern inline void * bus_to_virt(unsigned long address) -{ - return (void *)KSEG0ADDR(address); -} - -/* - * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. - */ -extern unsigned long isa_slot_offset; - -extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); - -#if 0 -extern inline void *ioremap(unsigned long offset, unsigned long size) -{ - return __ioremap(offset, size, _CACHE_UNCACHED); -} - -extern inline void *ioremap_nocache(unsigned long offset, unsigned long size) -{ - return __ioremap(offset, size, _CACHE_UNCACHED); -} - -extern void iounmap(void *addr); -#endif - -/* - * XXX We need system specific versions of these to handle EISA address bits - * 24-31 on SNI. - * XXX more SNI hacks. - */ -#define readb(addr) (*(volatile unsigned char *)(addr)) -#define readw(addr) __ioswab16((*(volatile unsigned short *)(addr))) -#define readl(addr) __ioswab32((*(volatile unsigned int *)(addr))) -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl - -#define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b) -#define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b)) -#define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b)) -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -/* END SNI HACKS ... */ - -/* - * ISA space is 'always mapped' on currently supported MIPS systems, no need - * to explicitly ioremap() it. The fact that the ISA IO space is mapped - * to PAGE_OFFSET is pure coincidence - it does not mean ISA values - * are physical addresses. The following constant pointer can be - * used as the IO-area pointer (it can be iounmapped as well, so the - * analogy with PCI is quite large): - */ -#define __ISA_IO_base ((char *)(PAGE_OFFSET)) - -#define isa_readb(a) readb(a) -#define isa_readw(a) readw(a) -#define isa_readl(a) readl(a) -#define isa_writeb(b,a) writeb(b,a) -#define isa_writew(w,a) writew(w,a) -#define isa_writel(l,a) writel(l,a) - -#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) -#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) - -/* - * We don't have csum_partial_copy_fromio() yet, so we cheat here and - * just copy it. The net code will then do the checksum later. - */ -#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len)) -#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d)) - -static inline int check_signature(unsigned long io_addr, - const unsigned char *signature, int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} -#define isa_check_signature(io, s, l) check_signature(i,s,l) - -/* - * Talk about misusing macros.. - */ - -#define __OUT1(s) \ -extern inline void __out##s(unsigned int value, unsigned int port) { - -#define __OUT2(m) \ -__asm__ __volatile__ ("s" #m "\t%0,%1(%2)" - -#define __OUT(m,s,w) \ -__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \ -__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \ -__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \ - SLOW_DOWN_IO; } \ -__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \ - SLOW_DOWN_IO; } - -#define __IN1(t,s) \ -extern __inline__ t __in##s(unsigned int port) { t _v; - -/* - * Required nops will be inserted by the assembler - */ -#define __IN2(m) \ -__asm__ __volatile__ ("l" #m "\t%0,%1(%2)" - -#define __IN(t,m,s,w) \ -__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \ -__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \ -__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \ -__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); } - -#define __INS1(s) \ -extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) { - -#define __INS2(m) \ -if (count) \ -__asm__ __volatile__ ( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n" \ - "1:\tl" #m "\t$1,%4(%5)\n\t" \ - "subu\t%1,1\n\t" \ - "s" #m "\t$1,(%0)\n\t" \ - "bne\t$0,%1,1b\n\t" \ - "addiu\t%0,%6\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" - -#define __INS(m,s,i) \ -__INS1(s) __INS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (0), \ - "r" (mips_io_port_base+port), "I" (i) \ - : "$1");} \ -__INS1(s##c) __INS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "ir" (port), \ - "r" (mips_io_port_base), "I" (i) \ - : "$1");} - -#define __OUTS1(s) \ -extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) { - -#define __OUTS2(m) \ -if (count) \ -__asm__ __volatile__ ( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n" \ - "1:\tl" #m "\t$1,(%0)\n\t" \ - "subu\t%1,1\n\t" \ - "s" #m "\t$1,%4(%5)\n\t" \ - "bne\t$0,%1,1b\n\t" \ - "addiu\t%0,%6\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" - -#define __OUTS(m,s,i) \ -__OUTS1(s) __OUTS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \ - : "$1");} \ -__OUTS1(s##c) __OUTS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \ - : "$1");} - -__IN(unsigned char,b,b,8) -__IN(unsigned short,h,w,16) -__IN(unsigned int,w,l,32) - -__OUT(b,b,8) -__OUT(h,w,16) -__OUT(w,l,32) - -__INS(b,b,1) -__INS(h,w,2) -__INS(w,l,4) - -__OUTS(b,b,1) -__OUTS(h,w,2) -__OUTS(w,l,4) - - -/* - * Note that due to the way __builtin_constant_p() works, you - * - can't use it inside an inline function (it will never be true) - * - you don't have to worry about side effects within the __builtin.. - */ -#define outb(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outbc((val),(port)) : \ - __outb((val),(port))) - -#define inb(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inbc(port) : \ - __inb(port)) - -#define outb_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outbc_p((val),(port)) : \ - __outb_p((val),(port))) - -#define inb_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inbc_p(port) : \ - __inb_p(port)) - -#define outw(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outwc((val),(port)) : \ - __outw((val),(port))) - -#define inw(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inwc(port) : \ - __inw(port)) - -#define outw_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outwc_p((val),(port)) : \ - __outw_p((val),(port))) - -#define inw_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inwc_p(port) : \ - __inw_p(port)) - -#define outl(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outlc((val),(port)) : \ - __outl((val),(port))) - -#define inl(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inlc(port) : \ - __inl(port)) - -#define outl_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outlc_p((val),(port)) : \ - __outl_p((val),(port))) - -#define inl_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inlc_p(port) : \ - __inl_p(port)) - - -#define outsb(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outsbc((port),(addr),(count)) : \ - __outsb ((port),(addr),(count))) - -#define insb(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __insbc((port),(addr),(count)) : \ - __insb((port),(addr),(count))) - -#define outsw(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outswc((port),(addr),(count)) : \ - __outsw ((port),(addr),(count))) - -#define insw(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inswc((port),(addr),(count)) : \ - __insw((port),(addr),(count))) - -#define outsl(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outslc((port),(addr),(count)) : \ - __outsl ((port),(addr),(count))) - -#define insl(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inslc((port),(addr),(count)) : \ - __insl((port),(addr),(count))) - -#define IO_SPACE_LIMIT 0xffff - -/* - * The caches on some architectures aren't dma-coherent and have need to - * handle this in software. There are three types of operations that - * can be applied to dma buffers. - * - * - dma_cache_wback_inv(start, size) makes caches and coherent by - * writing the content of the caches back to memory, if necessary. - * The function also invalidates the affected part of the caches as - * necessary before DMA transfers from outside to memory. - * - dma_cache_wback(start, size) makes caches and coherent by - * writing the content of the caches back to memory, if necessary. - * The function also invalidates the affected part of the caches as - * necessary before DMA transfers from outside to memory. - * - dma_cache_inv(start, size) invalidates the affected parts of the - * caches. Dirty lines of the caches may be written back or simply - * be discarded. This operation is necessary before dma operations - * to the memory. - */ -extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); -extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); -extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); - -#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size) -#define dma_cache_wback(start,size) _dma_cache_wback(start,size) -#define dma_cache_inv(start,size) _dma_cache_inv(start,size) - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -#endif /* _ASM_IO_H */ diff --git a/include/asm-mips/isadep.h b/include/asm-mips/isadep.h deleted file mode 100644 index 24c6cda..0000000 --- a/include/asm-mips/isadep.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Various ISA level dependent constants. - * Most of the following constants reflect the different layout - * of Coprocessor 0 registers. - * - * Copyright (c) 1998 Harald Koerfgen - */ - -#ifndef __ASM_ISADEP_H -#define __ASM_ISADEP_H - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) -/* - * R2000 or R3000 - */ - -/* - * kernel or user mode? (CP0_STATUS) - */ -#define KU_MASK 0x08 -#define KU_USER 0x08 -#define KU_KERN 0x00 - -#else -/* - * kernel or user mode? - */ -#define KU_MASK 0x18 -#define KU_USER 0x10 -#define KU_KERN 0x00 - -#endif - -#endif /* __ASM_ISADEP_H */ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h deleted file mode 100644 index be7e5c6..0000000 --- a/include/asm-mips/mipsregs.h +++ /dev/null @@ -1,1364 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - * Modified for further R[236]000 support by Paul M. Antoine, 1996. - * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 07 MIPS Technologies, Inc. - * Copyright (C) 2003, 2004 Maciej W. Rozycki - */ -#ifndef _ASM_MIPSREGS_H -#define _ASM_MIPSREGS_H - -#if 0 -#include -#endif - -/* - * The following macros are especially useful for __asm__ - * inline assembler. - */ -#ifndef __STR -#define __STR(x) #x -#endif -#ifndef STR -#define STR(x) __STR(x) -#endif - -/* - * Configure language - */ -#ifdef __ASSEMBLY__ -#define _ULCAST_ -#else -#define _ULCAST_ (unsigned long) -#endif - -/* - * Coprocessor 0 register names - */ -#define CP0_INDEX $0 -#define CP0_RANDOM $1 -#define CP0_ENTRYLO0 $2 -#define CP0_ENTRYLO1 $3 -#define CP0_CONF $3 -#define CP0_CONTEXT $4 -#define CP0_PAGEMASK $5 -#define CP0_WIRED $6 -#define CP0_INFO $7 -#define CP0_BADVADDR $8 -#define CP0_COUNT $9 -#define CP0_ENTRYHI $10 -#define CP0_COMPARE $11 -#define CP0_STATUS $12 -#define CP0_CAUSE $13 -#define CP0_EPC $14 -#define CP0_PRID $15 -#define CP0_CONFIG $16 -#define CP0_LLADDR $17 -#define CP0_WATCHLO $18 -#define CP0_WATCHHI $19 -#define CP0_XCONTEXT $20 -#define CP0_FRAMEMASK $21 -#define CP0_DIAGNOSTIC $22 -#define CP0_DEBUG $23 -#define CP0_DEPC $24 -#define CP0_PERFORMANCE $25 -#define CP0_ECC $26 -#define CP0_CACHEERR $27 -#define CP0_TAGLO $28 -#define CP0_TAGHI $29 -#define CP0_ERROREPC $30 -#define CP0_DESAVE $31 - -/* - * R4640/R4650 cp0 register names. These registers are listed - * here only for completeness; without MMU these CPUs are not useable - * by Linux. A future ELKS port might take make Linux run on them - * though ... - */ -#define CP0_IBASE $0 -#define CP0_IBOUND $1 -#define CP0_DBASE $2 -#define CP0_DBOUND $3 -#define CP0_CALG $17 -#define CP0_IWATCH $18 -#define CP0_DWATCH $19 - -/* - * Coprocessor 0 Set 1 register names - */ -#define CP0_S1_DERRADDR0 $26 -#define CP0_S1_DERRADDR1 $27 -#define CP0_S1_INTCONTROL $20 - -/* - * Coprocessor 0 Set 2 register names - */ -#define CP0_S2_SRSCTL $12 /* MIPSR2 */ - -/* - * Coprocessor 0 Set 3 register names - */ -#define CP0_S3_SRSMAP $12 /* MIPSR2 */ - -/* - * TX39 Series - */ -#define CP0_TX39_CACHE $7 - -/* - * Coprocessor 1 (FPU) register names - */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 - -/* - * FPU Status Register Values - */ -/* - * Status Register Values - */ - -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ - -/* - * X the exception cause indicator - * E the exception enable - * S the sticky/flag bit - */ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 - -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 - -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 - -/* rounding mode */ -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ - -/* - * Values for PageMask register - */ -#ifdef CONFIG_CPU_VR41XX - -/* Why doesn't stupidity hurt ... */ - -#define PM_1K 0x00000000 -#define PM_4K 0x00001800 -#define PM_16K 0x00007800 -#define PM_64K 0x0001f800 -#define PM_256K 0x0007f800 - -#else - -#define PM_4K 0x00000000 -#define PM_16K 0x00006000 -#define PM_64K 0x0001e000 -#define PM_256K 0x0007e000 -#define PM_1M 0x001fe000 -#define PM_4M 0x007fe000 -#define PM_16M 0x01ffe000 -#define PM_64M 0x07ffe000 -#define PM_256M 0x1fffe000 - -#endif - -/* - * Values used for computation of new tlb entries - */ -#define PL_4K 12 -#define PL_16K 14 -#define PL_64K 16 -#define PL_256K 18 -#define PL_1M 20 -#define PL_4M 22 -#define PL_16M 24 -#define PL_64M 26 -#define PL_256M 28 - -/* - * R4x00 interrupt enable / cause bits - */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) -#define IE_IRQ0 (_ULCAST_(1) << 10) -#define IE_IRQ1 (_ULCAST_(1) << 11) -#define IE_IRQ2 (_ULCAST_(1) << 12) -#define IE_IRQ3 (_ULCAST_(1) << 13) -#define IE_IRQ4 (_ULCAST_(1) << 14) -#define IE_IRQ5 (_ULCAST_(1) << 15) - -/* - * R4x00 interrupt cause bits - */ -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) -#define C_IRQ0 (_ULCAST_(1) << 10) -#define C_IRQ1 (_ULCAST_(1) << 11) -#define C_IRQ2 (_ULCAST_(1) << 12) -#define C_IRQ3 (_ULCAST_(1) << 13) -#define C_IRQ4 (_ULCAST_(1) << 14) -#define C_IRQ5 (_ULCAST_(1) << 15) - -/* - * Bitfields in the R4xx0 cp0 status register - */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_KSU 0x00000018 -# define KSU_USER 0x00000010 -# define KSU_SUPERVISOR 0x00000008 -# define KSU_KERNEL 0x00000000 -#define ST0_UX 0x00000020 -#define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 -#define ST0_DE 0x00010000 -#define ST0_CE 0x00020000 - -/* - * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate - * cacheops in userspace. This bit exists only on RM7000 and RM9000 - * processors. - */ -#define ST0_CO 0x08000000 - -/* - * Bitfields in the R[23]000 cp0 status register. - */ -#define ST0_IEC 0x00000001 -#define ST0_KUC 0x00000002 -#define ST0_IEP 0x00000004 -#define ST0_KUP 0x00000008 -#define ST0_IEO 0x00000010 -#define ST0_KUO 0x00000020 -/* bits 6 & 7 are reserved on R[23]000 */ -#define ST0_ISC 0x00010000 -#define ST0_SWC 0x00020000 -#define ST0_CM 0x00080000 - -/* - * Bits specific to the R4640/R4650 - */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) - -/* - * Enable the MIPS MDMX and DSP ASEs - */ -#define ST0_MX 0x01000000 - -/* - * Bitfields in the TX39 family CP0 Configuration Register 3 - */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 - -/* - * Status register bits available in all MIPS CPUs. - */ -#define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) -#define ST0_CH 0x00040000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_FR 0x04000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#define ST0_XX 0x80000000 /* MIPS IV naming */ - -/* - * Bitfields and bit numbers in the coprocessor 0 cause register. - * - * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. - */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) - -/* - * Bits in the coprocessor 0 config register. - */ -/* Generic bits. */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) - -/* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) - -/* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) - -/* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) - -/* Bits specific to the RM7000. */ -#define RM7K_CONF_SE (_ULCAST_(1) << 3) -#define RM7K_CONF_TE (_ULCAST_(1) << 12) -#define RM7K_CONF_CLK (_ULCAST_(1) << 16) -#define RM7K_CONF_TC (_ULCAST_(1) << 17) -#define RM7K_CONF_SI (_ULCAST_(3) << 20) -#define RM7K_CONF_SC (_ULCAST_(1) << 31) - -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) - -/* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_P4K (_ULCAST_(1) << 13) -#define VR41_CONF_BP (_ULCAST_(1) << 16) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) - -/* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) - -/* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) - -/* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) - -/* - * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. - */ -#define MIPS_CONF1_FP (_ULCAST_(1) << 0) -#define MIPS_CONF1_EP (_ULCAST_(1) << 1) -#define MIPS_CONF1_CA (_ULCAST_(1) << 2) -#define MIPS_CONF1_WR (_ULCAST_(1) << 3) -#define MIPS_CONF1_PC (_ULCAST_(1) << 4) -#define MIPS_CONF1_MD (_ULCAST_(1) << 5) -#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) -#define MIPS_CONF1_DA (_ULCAST_(7) << 7) -#define MIPS_CONF1_DL (_ULCAST_(7) << 10) -#define MIPS_CONF1_DS (_ULCAST_(7) << 13) -#define MIPS_CONF1_IA (_ULCAST_(7) << 16) -#define MIPS_CONF1_IL (_ULCAST_(7) << 19) -#define MIPS_CONF1_IS (_ULCAST_(7) << 22) -#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) - -#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) -#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) -#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) -#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) -#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) -#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) -#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) -#define MIPS_CONF2_TU (_ULCAST_(7) << 28) - -#define MIPS_CONF3_TL (_ULCAST_(1) << 0) -#define MIPS_CONF3_SM (_ULCAST_(1) << 1) -#define MIPS_CONF3_MT (_ULCAST_(1) << 2) -#define MIPS_CONF3_SP (_ULCAST_(1) << 4) -#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) -#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) -#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) -#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) -#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) - -#define MIPS_CONF7_WII (_ULCAST_(1) << 31) - -#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) - -/* - * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. - */ -#define MIPS_FPIR_S (_ULCAST_(1) << 16) -#define MIPS_FPIR_D (_ULCAST_(1) << 17) -#define MIPS_FPIR_PS (_ULCAST_(1) << 18) -#define MIPS_FPIR_3D (_ULCAST_(1) << 19) -#define MIPS_FPIR_W (_ULCAST_(1) << 20) -#define MIPS_FPIR_L (_ULCAST_(1) << 21) -#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) - -#ifndef __ASSEMBLY__ - -/* - * Functions to access the R10000 performance counters. These are basically - * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit - * performance counter number encoded into bits 1 ... 5 of the instruction. - * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware - * disassembler these will look like an access to sel 0 or 1. - */ -#define read_r10k_perf_cntr(counter) \ -({ \ - unsigned int __res; \ - __asm__ __volatile__( \ - "mfpc\t%0, %1" \ - : "=r" (__res) \ - : "i" (counter)); \ - \ - __res; \ -}) - -#define write_r10k_perf_cntr(counter,val) \ -do { \ - __asm__ __volatile__( \ - "mtpc\t%0, %1" \ - : \ - : "r" (val), "i" (counter)); \ -} while (0) - -#define read_r10k_perf_event(counter) \ -({ \ - unsigned int __res; \ - __asm__ __volatile__( \ - "mfps\t%0, %1" \ - : "=r" (__res) \ - : "i" (counter)); \ - \ - __res; \ -}) - -#define write_r10k_perf_cntl(counter,val) \ -do { \ - __asm__ __volatile__( \ - "mtps\t%0, %1" \ - : \ - : "r" (val), "i" (counter)); \ -} while (0) - -/* - * Macros to access the system control coprocessor - */ - -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __read_64bit_c0_register(source, sel) \ -({ unsigned long long __res; \ - if (sizeof(unsigned long) == 4) \ - __res = __read_64bit_c0_split(source, sel); \ - else if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -#define __write_64bit_c0_register(register, sel, value) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_64bit_c0_split(register, sel, value); \ - else if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ -} while (0) - -#define __read_ulong_c0_register(reg, sel) \ - ((sizeof(unsigned long) == 4) ? \ - (unsigned long) __read_32bit_c0_register(reg, sel) : \ - (unsigned long) __read_64bit_c0_register(reg, sel)) - -#define __write_ulong_c0_register(reg, sel, val) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_32bit_c0_register(reg, sel, val); \ - else \ - __write_64bit_c0_register(reg, sel, val); \ -} while (0) - -/* - * On RM7000/RM9000 these are uses to access cop0 set 1 registers - */ -#define __read_32bit_c0_ctrl_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - "cfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_ctrl_register(register, value) \ -do { \ - __asm__ __volatile__( \ - "ctc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -/* - * These versions are only needed for systems with more than 38 bits of - * physical address space running the 32-bit kernel. That's none atm :-) - */ -#define __read_64bit_c0_split(source, sel) \ -({ \ - unsigned long long __val; \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (__val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (__val)); \ - local_irq_restore(__flags); \ - \ - __val; \ -}) - -#define __write_64bit_c0_split(source, sel, val) \ -do { \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - local_irq_restore(__flags); \ -} while (0) - -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) - -#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) - -#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) - -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) - -#define read_c0_context() __read_ulong_c0_register($4, 0) -#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) - -#define read_c0_userlocal() __read_ulong_c0_register($4, 2) -#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) - -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) - -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) - -#define read_c0_info() __read_32bit_c0_register($7, 0) - -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) - -#define read_c0_badvaddr() __read_ulong_c0_register($8, 0) -#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) - -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) - -#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ -#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) - -#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ -#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) - -#define read_c0_entryhi() __read_ulong_c0_register($10, 0) -#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) - -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) - -#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ -#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) - -#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ -#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) - -#define read_c0_status() __read_32bit_c0_register($12, 0) -#ifdef CONFIG_MIPS_MT_SMTC -#define write_c0_status(val) \ -do { \ - __write_32bit_c0_register($12, 0, val); \ - __ehb(); \ -} while (0) -#else -/* - * Legacy non-SMTC code, which may be hazardous - * but which might not support EHB - */ -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) -#endif /* CONFIG_MIPS_MT_SMTC */ - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) - -#define read_c0_epc() __read_ulong_c0_register($14, 0) -#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) - -#define read_c0_prid() __read_32bit_c0_register($15, 0) - -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define read_c0_config4() __read_32bit_c0_register($16, 4) -#define read_c0_config5() __read_32bit_c0_register($16, 5) -#define read_c0_config6() __read_32bit_c0_register($16, 6) -#define read_c0_config7() __read_32bit_c0_register($16, 7) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) -#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) -#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) -#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) -#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) - -/* - * The WatchLo register. There may be upto 8 of them. - */ -#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) -#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) -#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) -#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) -#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) -#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) -#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) -#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) -#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) -#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) -#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) -#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) -#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) -#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) -#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) -#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) - -/* - * The WatchHi register. There may be upto 8 of them. - */ -#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) -#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) -#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) -#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) -#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) -#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) -#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) -#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) - -#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) -#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) -#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) -#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) -#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) -#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) -#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) -#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) - -#define read_c0_xcontext() __read_ulong_c0_register($20, 0) -#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) - -#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) -#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) - -#define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) - -/* RM9000 PerfControl performance counter control register */ -#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) -#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) - -#define read_c0_diag() __read_32bit_c0_register($22, 0) -#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) - -#define read_c0_diag1() __read_32bit_c0_register($22, 1) -#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) - -#define read_c0_diag2() __read_32bit_c0_register($22, 2) -#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) - -#define read_c0_diag3() __read_32bit_c0_register($22, 3) -#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) - -#define read_c0_diag4() __read_32bit_c0_register($22, 4) -#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) - -#define read_c0_diag5() __read_32bit_c0_register($22, 5) -#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) - -#define read_c0_debug() __read_32bit_c0_register($23, 0) -#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) - -#define read_c0_depc() __read_ulong_c0_register($24, 0) -#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) - -/* - * MIPS32 / MIPS64 performance counters - */ -#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) -#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) -#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) -#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) -#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) -#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) -#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) -#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) -#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) -#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) -#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) -#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) -#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) -#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) -#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) -#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) - -/* RM9000 PerfCount performance counter register */ -#define read_c0_perfcount() __read_64bit_c0_register($25, 0) -#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) - -#define read_c0_ecc() __read_32bit_c0_register($26, 0) -#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) - -#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) - -#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) - -#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) - -#define read_c0_taglo() __read_32bit_c0_register($28, 0) -#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) - -#define read_c0_dtaglo() __read_32bit_c0_register($28, 2) -#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) - -#define read_c0_taghi() __read_32bit_c0_register($29, 0) -#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) - -#define read_c0_errorepc() __read_ulong_c0_register($30, 0) -#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) - -/* MIPSR2 */ -#define read_c0_hwrena() __read_32bit_c0_register($7, 0) -#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) - -#define read_c0_intctl() __read_32bit_c0_register($12, 1) -#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) - -#define read_c0_srsctl() __read_32bit_c0_register($12, 2) -#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) - -#define read_c0_srsmap() __read_32bit_c0_register($12, 3) -#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) - -#define read_c0_ebase() __read_32bit_c0_register($15, 1) -#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) - -/* - * Macros to access the floating point coprocessor control registers - */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) - -#define rddsp(mask) \ -({ \ - unsigned int __res; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ - : "i" (mask)); \ - __res; \ -}) - -#define wrdsp(val, mask) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ - " .set pop \n" \ - : \ - : "r" (val), "i" (mask)); \ -} while (0) - -#define mfhi0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac0 \n" \ - " .word 0x00000810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac1 \n" \ - " .word 0x00200810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac2 \n" \ - " .word 0x00400810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi3() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac3 \n" \ - " .word 0x00600810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac0 \n" \ - " .word 0x00000812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac1 \n" \ - " .word 0x00200812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac2 \n" \ - " .word 0x00400812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo3() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac3 \n" \ - " .word 0x00600812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mthi0(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac0 \n" \ - " .word 0x00200011 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mthi1(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac1 \n" \ - " .word 0x00200811 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mthi2(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac2 \n" \ - " .word 0x00201011 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mthi3(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac3 \n" \ - " .word 0x00201811 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo0(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac0 \n" \ - " .word 0x00200013 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo1(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac1 \n" \ - " .word 0x00200813 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo2(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac2 \n" \ - " .word 0x00201013 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo3(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac3 \n" \ - " .word 0x00201813 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -/* - * TLB operations. - * - * It is responsibility of the caller to take care of any TLB hazards. - */ -static inline void tlb_probe(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbp\n\t" - ".set reorder"); -} - -static inline void tlb_read(void) -{ -#if MIPS34K_MISSED_ITLB_WAR - int res = 0; - - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set mips32r2 \n" - " .word 0x41610001 # dvpe $1 \n" - " move %0, $1 \n" - " ehb \n" - " .set pop \n" - : "=r" (res)); - - instruction_hazard(); -#endif - - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbr\n\t" - ".set reorder"); - -#if MIPS34K_MISSED_ITLB_WAR - if ((res & _ULCAST_(1))) - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set mips32r2 \n" - " .word 0x41600021 # evpe \n" - " ehb \n" - " .set pop \n"); -#endif -} - -static inline void tlb_write_indexed(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwi\n\t" - ".set reorder"); -} - -static inline void tlb_write_random(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwr\n\t" - ".set reorder"); -} - -/* - * Manipulate bits in a c0 register. - */ -#define __BUILD_SET_C0(name) \ -static inline unsigned int \ -set_c0_##name(unsigned int set) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ - \ - return res; \ -} - -__BUILD_SET_C0(status) -__BUILD_SET_C0(cause) -__BUILD_SET_C0(config) -__BUILD_SET_C0(intcontrol) -__BUILD_SET_C0(intctl) -__BUILD_SET_C0(srsmap) - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_MIPSREGS_H */ diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h deleted file mode 100644 index 879aae2..0000000 --- a/include/asm-mips/posix_types.h +++ /dev/null @@ -1,123 +0,0 @@ -/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle - */ -#ifndef _ASM_POSIX_TYPES_H -#define _ASM_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned int __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned int __kernel_mode_t; -typedef int __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef int __kernel_ipc_pid_t; -typedef int __kernel_uid_t; -typedef int __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef long __kernel_daddr_t; -typedef char * __kernel_caddr_t; - -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef int __kernel_uid32_t; -typedef int __kernel_gid32_t; -typedef __kernel_uid_t __kernel_old_uid_t; -typedef __kernel_gid_t __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { - long val[2]; -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); -} - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *__p) -{ - unsigned long *__tmp = __p->fds_bits; - int __i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 16: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - __tmp[ 8] = 0; __tmp[ 9] = 0; - __tmp[10] = 0; __tmp[11] = 0; - __tmp[12] = 0; __tmp[13] = 0; - __tmp[14] = 0; __tmp[15] = 0; - return; - - case 8: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - return; - - case 4: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - return; - } - } - __i = __FDSET_LONGS; - while (__i) { - __i--; - *__tmp = 0; - __tmp++; - } -} - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ - -#endif /* _ASM_POSIX_TYPES_H */ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h deleted file mode 100644 index 24858dd..0000000 --- a/include/asm-mips/processor.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 Waldorf GMBH - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle - * Copyright (C) 1996 Paul M. Antoine - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PROCESSOR_H -#define _ASM_PROCESSOR_H - -#include - -#include - -#include -#include -#include -#include - -/* - * Return current * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -/* - * System setup and hardware flags.. - */ -extern void (*cpu_wait)(void); - -extern unsigned int vced_count, vcei_count; - -#define NUM_FPU_REGS 32 - -typedef __u64 fpureg_t; - -/* - * It would be nice to add some more fields for emulator statistics, but there - * are a number of fixed offsets in offset.h and elsewhere that would have to - * be recalculated by hand. So the additional information will be private to - * the FPU emulator for now. See asm-mips/fpu_emulator.h. - */ - -struct mips_fpu_struct { - fpureg_t fpr[NUM_FPU_REGS]; - unsigned int fcr31; -}; - -#define NUM_DSP_REGS 6 - -typedef __u32 dspreg_t; - -struct mips_dsp_state { - dspreg_t dspr[NUM_DSP_REGS]; - unsigned int dspcontrol; -}; - -typedef struct { - unsigned long seg; -} mm_segment_t; - -#define ARCH_MIN_TASKALIGN 8 - -struct mips_abi; - -/* - * If you change thread_struct remember to change the #defines below too! - */ -struct thread_struct { - /* Saved main processor registers. */ - unsigned long reg16; - unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; - unsigned long reg29, reg30, reg31; - - /* Saved cp0 stuff. */ - unsigned long cp0_status; - - /* Saved fpu/fpu emulator stuff. */ - struct mips_fpu_struct fpu; -#ifdef CONFIG_MIPS_MT_FPAFF - /* Emulated instruction count */ - unsigned long emulated_fp; - /* Saved per-thread scheduler affinity mask */ - cpumask_t user_cpus_allowed; -#endif /* CONFIG_MIPS_MT_FPAFF */ - - /* Saved state of the DSP ASE, if available. */ - struct mips_dsp_state dsp; - - /* Other stuff associated with the thread. */ - unsigned long cp0_badvaddr; /* Last user fault */ - unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ - unsigned long error_code; - unsigned long trap_no; - unsigned long irix_trampoline; /* Wheee... */ - unsigned long irix_oldctx; - struct mips_abi *abi; -}; - -struct task_struct; - -/* Free all resources held by a thread. */ -#define release_thread(thread) do { } while(0) - -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while (0) - -#define cpu_relax() barrier() - -/* - * Return_address is a replacement for __builtin_return_address(count) - * which on certain architectures cannot reasonably be implemented in GCC - * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). - * Note that __builtin_return_address(x>=1) is forbidden because GCC - * aborts compilation on some CPUs. It's simply not possible to unwind - * some CPU's stackframes. - * - * __builtin_return_address works only for non-leaf functions. We avoid the - * overhead of a function call by forcing the compiler to save the return - * address register on the stack. - */ -#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) - -#ifdef CONFIG_CPU_HAS_PREFETCH - -#define ARCH_HAS_PREFETCH - -static inline void prefetch(const void *addr) -{ - __asm__ __volatile__( - " .set mips4 \n" - " pref %0, (%1) \n" - " .set mips0 \n" - : - : "i" (Pref_Load), "r" (addr)); -} - -#endif - -#endif /* _ASM_PROCESSOR_H */ diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h deleted file mode 100644 index 5659c0c..0000000 --- a/include/asm-mips/ptrace.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PTRACE_H -#define _ASM_PTRACE_H - -/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ -#define FPR_BASE 32 -#define PC 64 -#define CAUSE 65 -#define BADVADDR 66 -#define MMHI 67 -#define MMLO 68 -#define FPC_CSR 69 -#define FPC_EIR 70 -#define DSP_BASE 71 /* 3 more hi / lo register pairs */ -#define DSP_CONTROL 77 -#define ACX 78 - -/* - * This struct defines the way the registers are stored on the stack during a - * system call/exception. As usual the registers k0/k1 aren't being saved. - */ -struct pt_regs { -#ifdef CONFIG_32BIT - /* Pad bytes for argument save space on the stack. */ - unsigned long pad0[6]; -#endif - - /* Saved main processor registers. */ - unsigned long regs[32]; - - /* Saved special registers. */ - unsigned long cp0_status; - unsigned long hi; - unsigned long lo; -#ifdef CONFIG_CPU_HAS_SMARTMIPS - unsigned long acx; -#endif - unsigned long cp0_badvaddr; - unsigned long cp0_cause; - unsigned long cp0_epc; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long cp0_tcstatus; -#endif /* CONFIG_MIPS_MT_SMTC */ -} __attribute__ ((aligned (8))); - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 -/* #define PTRACE_GETFPXREGS 18 */ -/* #define PTRACE_SETFPXREGS 19 */ - -#define PTRACE_OLDSETOPTIONS 21 - -#define PTRACE_GET_THREAD_AREA 25 -#define PTRACE_SET_THREAD_AREA 26 - -/* Calls to trace a 64bit program from a 32bit program. */ -#define PTRACE_PEEKTEXT_3264 0xc0 -#define PTRACE_PEEKDATA_3264 0xc1 -#define PTRACE_POKETEXT_3264 0xc2 -#define PTRACE_POKEDATA_3264 0xc3 -#define PTRACE_GET_THREAD_AREA_3264 0xc4 - -#ifdef __KERNEL__ - -#include - -/* - * Does the process account for user or for system time? - */ -#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) - -#define instruction_pointer(regs) ((regs)->cp0_epc) -#define profile_pc(regs) instruction_pointer(regs) - -#endif - -#endif /* _ASM_PTRACE_H */ diff --git a/include/asm-mips/reboot.h b/include/asm-mips/reboot.h deleted file mode 100644 index 978d206..0000000 --- a/include/asm-mips/reboot.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef _ASM_REBOOT_H -#define _ASM_REBOOT_H - -extern void _machine_restart(void); - -#endif /* _ASM_REBOOT_H */ diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h deleted file mode 100644 index fc6bc0c..0000000 --- a/include/asm-mips/reg.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Various register offset definitions for debuggers, core file - * examiners and whatnot. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999 by Ralf Baechle - * Copyright (C) 1995, 1999 Silicon Graphics - */ -#ifndef __ASM_MIPS_REG_H -#define __ASM_MIPS_REG_H - -#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H) - -#define EF_R0 6 -#define EF_R1 7 -#define EF_R2 8 -#define EF_R3 9 -#define EF_R4 10 -#define EF_R5 11 -#define EF_R6 12 -#define EF_R7 13 -#define EF_R8 14 -#define EF_R9 15 -#define EF_R10 16 -#define EF_R11 17 -#define EF_R12 18 -#define EF_R13 19 -#define EF_R14 20 -#define EF_R15 21 -#define EF_R16 22 -#define EF_R17 23 -#define EF_R18 24 -#define EF_R19 25 -#define EF_R20 26 -#define EF_R21 27 -#define EF_R22 28 -#define EF_R23 29 -#define EF_R24 30 -#define EF_R25 31 - -/* - * k0/k1 unsaved - */ -#define EF_R26 32 -#define EF_R27 33 - -#define EF_R28 34 -#define EF_R29 35 -#define EF_R30 36 -#define EF_R31 37 - -/* - * Saved special registers - */ -#define EF_LO 38 -#define EF_HI 39 - -#define EF_CP0_EPC 40 -#define EF_CP0_BADVADDR 41 -#define EF_CP0_STATUS 42 -#define EF_CP0_CAUSE 43 -#define EF_UNUSED0 44 - -#define EF_SIZE 180 - -#endif - -#ifdef CONFIG_64BIT - -#define EF_R0 0 -#define EF_R1 1 -#define EF_R2 2 -#define EF_R3 3 -#define EF_R4 4 -#define EF_R5 5 -#define EF_R6 6 -#define EF_R7 7 -#define EF_R8 8 -#define EF_R9 9 -#define EF_R10 10 -#define EF_R11 11 -#define EF_R12 12 -#define EF_R13 13 -#define EF_R14 14 -#define EF_R15 15 -#define EF_R16 16 -#define EF_R17 17 -#define EF_R18 18 -#define EF_R19 19 -#define EF_R20 20 -#define EF_R21 21 -#define EF_R22 22 -#define EF_R23 23 -#define EF_R24 24 -#define EF_R25 25 - -/* - * k0/k1 unsaved - */ -#define EF_R26 26 -#define EF_R27 27 - -#define EF_R28 28 -#define EF_R29 29 -#define EF_R30 30 -#define EF_R31 31 - -/* - * Saved special registers - */ -#define EF_LO 32 -#define EF_HI 33 - -#define EF_CP0_EPC 34 -#define EF_CP0_BADVADDR 35 -#define EF_CP0_STATUS 36 -#define EF_CP0_CAUSE 37 - -#define EF_SIZE 304 /* size in bytes */ - -#endif /* CONFIG_64BIT */ - -#endif /* __ASM_MIPS_REG_H */ diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h deleted file mode 100644 index 2e65cc3..0000000 --- a/include/asm-mips/regdef.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1985 MIPS Computer Systems, Inc. - * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle - * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_REGDEF_H -#define _ASM_REGDEF_H - -#include - -#if _MIPS_SIM == _MIPS_SIM_ABI32 - -/* - * Symbolic register names for 32 bit ABI - */ -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - -#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 - -#define zero $0 /* wired zero */ -#define AT $at /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value - caller saved */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ -#define ta0 $8 -#define a5 $9 -#define ta1 $9 -#define a6 $10 -#define ta2 $10 -#define a7 $11 -#define ta3 $11 -#define t0 $12 /* caller saved */ -#define t1 $13 -#define t2 $14 -#define t3 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 /* callee address for PIC/temp */ -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel temporary */ -#define k1 $27 -#define gp $28 /* global pointer - caller saved for PIC */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* callee saved */ -#define ra $31 /* return address */ - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ - -#endif /* _ASM_REGDEF_H */ diff --git a/include/asm-mips/sgidefs.h b/include/asm-mips/sgidefs.h deleted file mode 100644 index 67f2658..0000000 --- a/include/asm-mips/sgidefs.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1999, 2001 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef __ASM_SGIDEFS_H -#define __ASM_SGIDEFS_H - -/* - * Using a Linux compiler for building Linux seems logic but not to - * everybody. - */ -#if 0 /* ndef __linux__ */ -#error Use a Linux compiler or give up. -#endif - -/* - * Definitions for the ISA levels - * - * With the introduction of MIPS32 / MIPS64 instruction sets definitions - * MIPS ISAs are no longer subsets of each other. Therefore comparisons - * on these symbols except with == may result in unexpected results and - * are forbidden! - */ -#define _MIPS_ISA_MIPS1 1 -#define _MIPS_ISA_MIPS2 2 -#define _MIPS_ISA_MIPS3 3 -#define _MIPS_ISA_MIPS4 4 -#define _MIPS_ISA_MIPS5 5 -#define _MIPS_ISA_MIPS32 6 -#define _MIPS_ISA_MIPS64 7 - -/* - * Subprogram calling convention - */ -#define _MIPS_SIM_ABI32 1 -#define _MIPS_SIM_NABI32 2 -#define _MIPS_SIM_ABI64 3 - -#endif /* __ASM_SGIDEFS_H */ diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h deleted file mode 100644 index 579a591..0000000 --- a/include/asm-mips/string.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle - * Copyright (c) 2000 by Silicon Graphics, Inc. - * Copyright (c) 2001 MIPS Technologies, Inc. - */ -#ifndef _ASM_STRING_H -#define _ASM_STRING_H - -/* - * We don't do inline string functions, since the - * optimised inline asm versions are not small. - */ - -#undef __HAVE_ARCH_STRCPY -extern char *strcpy(char *__dest, __const__ char *__src); - -#undef __HAVE_ARCH_STRNCPY -extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n); - -#undef __HAVE_ARCH_STRCMP -extern int strcmp(__const__ char *__cs, __const__ char *__ct); - -#undef __HAVE_ARCH_STRNCMP -extern int strncmp(__const__ char *__cs, __const__ char *__ct, __kernel_size_t __count); - -#undef __HAVE_ARCH_MEMSET -extern void *memset(void *__s, int __c, __kernel_size_t __count); - -#undef __HAVE_ARCH_MEMCPY -extern void *memcpy(void *__to, __const__ void *__from, __kernel_size_t __n); - -#undef __HAVE_ARCH_MEMMOVE -extern void *memmove(void *__dest, __const__ void *__src, __kernel_size_t __n); - -#endif /* _ASM_STRING_H */ diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h deleted file mode 100644 index b6d50e2..0000000 --- a/include/asm-mips/system.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999 by Ralf Baechle - * Copyright (C) 1996 by Paul M. Antoine - * Copyright (C) 1994 - 1999 by Ralf Baechle - * - * Changed set_except_vector declaration to allow return of previous - * vector address value - necessary for "borrowing" vectors. - * - * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. - */ -#ifndef _ASM_SYSTEM_H -#define _ASM_SYSTEM_H - -#include -#include -#include -#if 0 -#include -#endif - -extern __inline__ void -__sti(void) -{ - __asm__ __volatile__( - ".set\tpush\n\t" - ".set\treorder\n\t" - ".set\tnoat\n\t" - "mfc0\t$1,$12\n\t" - "ori\t$1,0x1f\n\t" - "xori\t$1,0x1e\n\t" - "mtc0\t$1,$12\n\t" - ".set\tpop\n\t" - : /* no outputs */ - : /* no inputs */ - : "$1", "memory"); -} - -/* - * For cli() we have to insert nops to make shure that the new value - * has actually arrived in the status register before the end of this - * macro. - * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs - * no nops at all. - */ -extern __inline__ void -__cli(void) -{ - __asm__ __volatile__( - ".set\tpush\n\t" - ".set\treorder\n\t" - ".set\tnoat\n\t" - "mfc0\t$1,$12\n\t" - "ori\t$1,1\n\t" - "xori\t$1,1\n\t" - ".set\tnoreorder\n\t" - "mtc0\t$1,$12\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - ".set\tpop\n\t" - : /* no outputs */ - : /* no inputs */ - : "$1", "memory"); -} - -#define __save_flags(x) \ -__asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "mfc0\t%0,$12\n\t" \ - ".set\tpop\n\t" \ - : "=r" (x)) - -#define __save_and_cli(x) \ -__asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - ".set\tnoat\n\t" \ - "mfc0\t%0,$12\n\t" \ - "ori\t$1,%0,1\n\t" \ - "xori\t$1,1\n\t" \ - ".set\tnoreorder\n\t" \ - "mtc0\t$1,$12\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - ".set\tpop\n\t" \ - : "=r" (x) \ - : /* no inputs */ \ - : "$1", "memory") - -#define __restore_flags(flags) \ -do { \ - unsigned long __tmp1; \ - \ - __asm__ __volatile__( \ - ".set\tnoreorder\t\t\t# __restore_flags\n\t" \ - ".set\tnoat\n\t" \ - "mfc0\t$1, $12\n\t" \ - "andi\t%0, 1\n\t" \ - "ori\t$1, 1\n\t" \ - "xori\t$1, 1\n\t" \ - "or\t%0, $1\n\t" \ - "mtc0\t%0, $12\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - : "=r" (__tmp1) \ - : "0" (flags) \ - : "$1", "memory"); \ -} while(0) - -#ifdef CONFIG_SMP - -extern void __global_sti(void); -extern void __global_cli(void); -extern unsigned long __global_save_flags(void); -extern void __global_restore_flags(unsigned long); -# define sti() __global_sti() -# define cli() __global_cli() -# define save_flags(x) do { x = __global_save_flags(); } while (0) -# define restore_flags(x) __global_restore_flags(x) -# define save_and_cli(x) do { save_flags(x); cli(); } while(0) - -#else /* Single processor */ - -# define sti() __sti() -# define cli() __cli() -# define save_flags(x) __save_flags(x) -# define save_and_cli(x) __save_and_cli(x) -# define restore_flags(x) __restore_flags(x) - -#endif /* SMP */ - -/* For spinlocks etc */ -#define local_irq_save(x) __save_and_cli(x); -#define local_irq_restore(x) __restore_flags(x); -#define local_irq_disable() __cli(); -#define local_irq_enable() __sti(); - -/* - * These are probably defined overly paranoid ... - */ -#ifdef CONFIG_CPU_HAS_WB - -#include -#define rmb() do { } while(0) -#define wmb() wbflush() -#define mb() wbflush() - -#else /* CONFIG_CPU_HAS_WB */ - -#define mb() \ -__asm__ __volatile__( \ - "# prevent instructions being moved around\n\t" \ - ".set\tnoreorder\n\t" \ - "# 8 nops to fool the R4400 pipeline\n\t" \ - "nop;nop;nop;nop;nop;nop;nop;nop\n\t" \ - ".set\treorder" \ - : /* no output */ \ - : /* no input */ \ - : "memory") -#define rmb() mb() -#define wmb() mb() - -#endif /* CONFIG_CPU_HAS_WB */ - -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#endif - -#define set_mb(var, value) \ -do { var = value; mb(); } while (0) - -#define set_wmb(var, value) \ -do { var = value; wmb(); } while (0) - -#if !defined (_LANGUAGE_ASSEMBLY) -/* - * switch_to(n) should switch tasks to task nr n, first - * checking that n isn't the current task, in which case it does nothing. - */ -#if 0 -extern asmlinkage void *resume(void *last, void *next); -#endif -#endif /* !defined (_LANGUAGE_ASSEMBLY) */ - -#define prepare_to_switch() do { } while(0) -#define switch_to(prev,next,last) \ -do { \ - (last) = resume(prev, next); \ -} while(0) - -/* - * For 32 and 64 bit operands we can take advantage of ll and sc. - * FIXME: This doesn't work for R3000 machines. - */ -extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) -{ -#ifdef CONFIG_CPU_HAS_LLSC - unsigned long dummy; - - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# xchg_u32\n\t" - ".set\tnoat\n\t" - "ll\t%0, %3\n" - "1:\tmove\t$1, %2\n\t" - "sc\t$1, %1\n\t" - "beqzl\t$1, 1b\n\t" - " ll\t%0, %3\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (val), "=o" (*m), "=r" (dummy) - : "o" (*m), "2" (val) - : "memory"); - - return val; -#else - unsigned long flags, retval; - - save_flags(flags); - cli(); - retval = *m; - *m = val; - restore_flags(flags); - return retval; -#endif /* Processor-dependent optimization */ -} - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -#define tas(ptr) (xchg((ptr),1)) - -static __inline__ unsigned long -__xchg(unsigned long x, volatile void * ptr, int size) -{ - switch (size) { - case 4: - return xchg_u32(ptr, x); - } - return x; -} - -extern void *set_except_vector(int n, void *addr); - -extern void __die(const char *, struct pt_regs *, const char *where, - unsigned long line) __attribute__((noreturn)); -extern void __die_if_kernel(const char *, struct pt_regs *, const char *where, - unsigned long line); - -#define die(msg, regs) \ - __die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) -#define die_if_kernel(msg, regs) \ - __die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) - -#endif /* _ASM_SYSTEM_H */ diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h deleted file mode 100644 index d4bb859..0000000 --- a/include/asm-mips/types.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_TYPES_H -#define _ASM_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if (_MIPS_SZLONG == 64) - -typedef __signed__ long __s64; -typedef unsigned long __u64; - -#else - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG _MIPS_SZLONG - -#ifndef __ASSEMBLY__ - -typedef __signed char s8; -typedef unsigned char u8; - -typedef __signed short s16; -typedef unsigned short u16; - -typedef __signed int s32; -typedef unsigned int u32; - -#if (_MIPS_SZLONG == 64) - -typedef __signed__ long s64; -typedef unsigned long u64; - -#else - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long s64; -typedef unsigned long long u64; -#endif - -#endif - -#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ - || defined(CONFIG_64BIT) -typedef u64 dma_addr_t; - -typedef u64 phys_addr_t; -typedef u64 phys_size_t; - -#else -typedef u32 dma_addr_t; - -typedef u32 phys_addr_t; -typedef u32 phys_size_t; - -#endif -typedef u64 dma64_addr_t; - -/* - * Don't use phys_t. You've been warned. - */ -#ifdef CONFIG_64BIT_PHYS_ADDR -typedef unsigned long long phys_t; -#else -typedef unsigned long phys_t; -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_TYPES_H */ diff --git a/include/asm-mips/u-boot.h b/include/asm-mips/u-boot.h deleted file mode 100644 index d9c14ca..0000000 --- a/include/asm-mips/u-boot.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef _U_BOOT_H_ -#define _U_BOOT_H_ 1 - -typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned long bi_arch_number; /* unique id for this board */ - unsigned long bi_boot_params; /* where this board expects params */ - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ -} bd_t; -#define bi_env_data bi_env->data -#define bi_env_crc bi_env->crc - -#endif /* _U_BOOT_H_ */ diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h deleted file mode 100644 index 1d5112e..0000000 --- a/include/asm-mips/unaligned.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_MIPS_UNALIGNED_H -#define _ASM_MIPS_UNALIGNED_H - -#include -#if defined(__MIPSEB__) -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#elif defined(__MIPSEL__) -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#else -#error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" -#endif - -#include -#include -#include - -#endif /* _ASM_MIPS_UNALIGNED_H */ diff --git a/include/asm-nios/bitops.h b/include/asm-nios/bitops.h deleted file mode 100644 index 0be74f4..0000000 --- a/include/asm-nios/bitops.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_NIOS_BITOPS_H_ -#define _ASM_NIOS_BITOPS_H_ - - -extern void set_bit(int nr, volatile void * a); -extern void clear_bit(int nr, volatile void * a); -extern int test_and_clear_bit(int nr, volatile void * a); -extern void change_bit(unsigned long nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void * a); -extern int test_and_change_bit(int nr, volatile void * addr); -extern int test_bit(int nr, volatile void * a); -extern int ffs(int i); -#define PLATFORM_FFS - -#endif /* _ASM_NIOS_BITOPS_H */ diff --git a/include/asm-nios/byteorder.h b/include/asm-nios/byteorder.h deleted file mode 100644 index dc71021..0000000 --- a/include/asm-nios/byteorder.h +++ /dev/null @@ -1,30 +0,0 @@ -/* -* (C) Copyright 2003, Psyent Corporation -* Scott McNutt -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#ifndef __ASM_NIOS_BYTEORDER_H -#define __ASM_NIOS_BYTEORDER_H - -#include -#include - -#endif diff --git a/include/asm-nios/cache.h b/include/asm-nios/cache.h deleted file mode 100644 index 3cdb703..0000000 --- a/include/asm-nios/cache.h +++ /dev/null @@ -1 +0,0 @@ -/*FIXME: Implement this! */ diff --git a/include/asm-nios/config.h b/include/asm-nios/config.h deleted file mode 100644 index 2efe898..0000000 --- a/include/asm-nios/config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -/* Relocation to SDRAM works on all NIOS boards */ -#define CONFIG_RELOC_FIXUP_WORKS - -#endif diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h deleted file mode 100644 index fa54ee4..0000000 --- a/include/asm-nios/global_data.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_NIOS_GLOBALDATA_H -#define __ASM_NIOS_GLOBALDATA_H - -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid */ -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - unsigned long post_log_word; /* Record POST activities */ - unsigned long post_init_f_time; /* When post_init_f started */ -#endif - void **jt; /* Standalone app jump table */ -} gd_t; - -/* flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("%g7") - -#endif /* __ASM_NIOS_GLOBALDATA_H */ diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h deleted file mode 100644 index 899682c..0000000 --- a/include/asm-nios/io.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_NIOS_IO_H_ -#define __ASM_NIOS_IO_H_ - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -#define readb(addr)\ - ({unsigned char val;\ - asm volatile( " pfxio 0 \n"\ - " ld %0, [%1] \n"\ - " ext8d %0, %1 \n"\ - :"=r"(val) : "r" (addr)); val;}) - -#define readw(addr)\ - ({unsigned short val;\ - asm volatile( " pfxio 0 \n"\ - " ld %0, [%1] \n"\ - " ext16d %0, %1 \n"\ - :"=r"(val) : "r" (addr)); val;}) - -#define readl(addr)\ - ({unsigned long val;\ - asm volatile( " pfxio 0 \n"\ - " ld %0, [%1] \n"\ - :"=r"(val) : "r" (addr)); val;}) - -#define writeb(addr,val)\ - asm volatile ( " fill8 %%r0, %1 \n"\ - " st8d [%0], %%r0 \n"\ - : : "r" (addr), "r" (val) : "r0") - -#define writew(addr,val)\ - asm volatile ( " fill16 %%r0, %1 \n"\ - " st16d [%0], %%r0 \n"\ - : : "r" (addr), "r" (val) : "r0") - -#define writel(addr,val)\ - asm volatile ( " st [%0], %1 \n"\ - : : "r" (addr), "r" (val)) - -#define inb(addr) readb(addr) -#define inw(addr) readw(addr) -#define inl(addr) readl(addr) -#define outb(val,addr) writeb(addr,val) -#define outw(val,addr) writew(addr,val) -#define outl(val,addr) writel(addr,val) - -static inline void insb (unsigned long port, void *dst, unsigned long count) -{ - unsigned char *p = dst; - while (count--) *p++ = inb (port); -} -static inline void insw (unsigned long port, void *dst, unsigned long count) -{ - unsigned short *p = dst; - while (count--) *p++ = inw (port); -} -static inline void insl (unsigned long port, void *dst, unsigned long count) -{ - unsigned long *p = dst; - while (count--) *p++ = inl (port); -} - -static inline void outsb (unsigned long port, const void *src, unsigned long count) -{ - const unsigned char *p = src; - while (count--) outb (*p++, port); -} - -static inline void outsw (unsigned long port, const void *src, unsigned long count) -{ - const unsigned short *p = src; - while (count--) outw (*p++, port); -} -static inline void outsl (unsigned long port, const void *src, unsigned long count) -{ - const unsigned long *p = src; - while (count--) outl (*p++, port); -} - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -#endif /* __ASM_NIOS_IO_H_ */ diff --git a/include/asm-nios/posix_types.h b/include/asm-nios/posix_types.h deleted file mode 100644 index eb74214..0000000 --- a/include/asm-nios/posix_types.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __ASM_NIOS_POSIX_TYPES_H -#define __ASM_NIOS_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned long __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) - -#undef __FD_CLR -#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) - -#undef __FD_ISSET -#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ - -#endif diff --git a/include/asm-nios/processor.h b/include/asm-nios/processor.h deleted file mode 100644 index 78b8976..0000000 --- a/include/asm-nios/processor.h +++ /dev/null @@ -1 +0,0 @@ -/* FIXME: Implement this! */ diff --git a/include/asm-nios/psr.h b/include/asm-nios/psr.h deleted file mode 100644 index 6e8eba8..0000000 --- a/include/asm-nios/psr.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _NIOS_PSR_H -#define _NIOS_PSR_H - - -#endif /* _NIOS_PSR_H */ diff --git a/include/asm-nios/ptrace.h b/include/asm-nios/ptrace.h deleted file mode 100644 index 73754c8..0000000 --- a/include/asm-nios/ptrace.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _NIOS_PTRACE_H -#define _NIOS_PTRACE_H - -struct pt_regs { - unsigned global[8]; - unsigned in[8]; - unsigned status; - unsigned istatus; - unsigned retaddr; -}; - - -#endif /* _NIOS_PTRACE_H */ diff --git a/include/asm-nios/status_led.h b/include/asm-nios/status_led.h deleted file mode 100644 index 241c917..0000000 --- a/include/asm-nios/status_led.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * asm-nios/status_led.h - * - * NIOS PIO based status led support functions - */ - -#ifndef __ASM_STATUS_LED_H__ -#define __ASM_STATUS_LED_H__ - -#include - -/* led_id_t is unsigned int mask */ -typedef unsigned int led_id_t; - -#ifdef STATUS_LED_WRONLY /* emulate read access */ -static led_id_t __led_portval = 0; -#endif - -static inline void __led_init (led_id_t mask, int state) -{ - nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE; - -#ifdef STATUS_LED_WRONLY /* emulate read access */ - -#if (STATUS_LED_ACTIVE == 0) - if (state == STATUS_LED_ON) - __led_portval &= ~mask; - else - __led_portval |= mask; -#else - if (state == STATUS_LED_ON) - __led_portval |= mask; - else - __led_portval &= ~mask; -#endif - - piop->data = __led_portval; - -#else /* !STATUS_LED_WRONLY */ - -#if (STATUS_LED_ACTIVE == 0) - if (state == STATUS_LED_ON) - piop->data &= ~mask; - else - piop->data |= mask; -#else - if (state == STATUS_LED_ON) - piop->data |= mask; - else - piop->data &= ~mask; -#endif - - piop->direction |= mask; - -#endif /* STATUS_LED_WRONLY */ -} - -static inline void __led_toggle (led_id_t mask) -{ - nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE; - -#ifdef STATUS_LED_WRONLY /* emulate read access */ - - __led_portval ^= mask; - piop->data = __led_portval; - -#else /* !STATUS_LED_WRONLY */ - - piop->data ^= mask; - -#endif /* STATUS_LED_WRONLY */ -} - -static inline void __led_set (led_id_t mask, int state) -{ - nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE; - -#ifdef STATUS_LED_WRONLY /* emulate read access */ - -#if (STATUS_LED_ACTIVE == 0) - if (state == STATUS_LED_ON) - __led_portval &= ~mask; - else - __led_portval |= mask; -#else - if (state == STATUS_LED_ON) - __led_portval |= mask; - else - __led_portval &= ~mask; -#endif - - piop->data = __led_portval; - -#else /* !STATUS_LED_WRONLY */ - -#if (STATUS_LED_ACTIVE == 0) - if (state == STATUS_LED_ON) - piop->data &= ~mask; - else - piop->data |= mask; -#else - if (state == STATUS_LED_ON) - piop->data |= mask; - else - piop->data &= ~mask; -#endif - -#endif /* STATUS_LED_WRONLY */ -} - -#endif /* __ASM_STATUS_LED_H__ */ diff --git a/include/asm-nios/string.h b/include/asm-nios/string.h deleted file mode 100644 index fa33275..0000000 --- a/include/asm-nios/string.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __ASM_NIOS_STRING_H -#define __ASM_NIOS_STRING_H - -#undef __HAVE_ARCH_STRRCHR -extern char * strrchr(const char * s, int c); - -#undef __HAVE_ARCH_STRCHR -extern char * strchr(const char * s, int c); - -#undef __HAVE_ARCH_MEMCPY -extern void * memcpy(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMMOVE -extern void * memmove(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMCHR -extern void * memchr(const void *, int, __kernel_size_t); - -#undef __HAVE_ARCH_MEMSET -extern void * memset(void *, int, __kernel_size_t); - -#undef __HAVE_ARCH_MEMZERO -extern void memzero(void *ptr, __kernel_size_t n); - -#endif diff --git a/include/asm-nios/system.h b/include/asm-nios/system.h deleted file mode 100644 index 9a9383d..0000000 --- a/include/asm-nios/system.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _ASM_NIOS_SYSTEM_H_ -#define _ASM_NIOS_SYSTEM_H_ - -#endif /* _ASM_NIOS_SYSTEM_H */ diff --git a/include/asm-nios/types.h b/include/asm-nios/types.h deleted file mode 100644 index 636e12f..0000000 --- a/include/asm-nios/types.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef _NIOS_TYPES_H -#define _NIOS_TYPES_H - -/* - * This file is never included by application software unless - * explicitly requested (e.g., via linux/types.h) in which case the - * application is Linux specific so (user-) name space pollution is - * not a major issue. However, for interoperability, libraries still - * need to be careful to avoid a name clashes. - */ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; -#endif /* __KERNEL__ */ - -#endif /* _NIOS_TYPES_H */ diff --git a/include/asm-nios/u-boot.h b/include/asm-nios/u-boot.h deleted file mode 100644 index bdb6cf2..0000000 --- a/include/asm-nios/u-boot.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2003 - * Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef _U_BOOT_H_ -#define _U_BOOT_H_ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned long bi_baudrate; /* Console Baudrate */ -} bd_t; - - -#endif /* _U_BOOT_H_ */ diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h deleted file mode 100644 index cf48ff7..0000000 --- a/include/asm-nios2/bitops.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_NIOS2_BITOPS_H_ -#define __ASM_NIOS2_BITOPS_H_ - -/* copied from linux-2.6/include/asm-generic/bitops */ -#include -#include -#include - -#endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-nios2/bitops/atomic.h b/include/asm-nios2/bitops/atomic.h deleted file mode 100644 index c894646..0000000 --- a/include/asm-nios2/bitops/atomic.h +++ /dev/null @@ -1,189 +0,0 @@ -#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ -#define _ASM_GENERIC_BITOPS_ATOMIC_H_ - -#include -#include - -#ifdef CONFIG_SMP -#include -#include /* we use L1_CACHE_BYTES */ - -/* Use an array of spinlocks for our atomic_ts. - * Hash function to index into a different SPINLOCK. - * Since "a" is usually an address, use one spinlock per cacheline. - */ -# define ATOMIC_HASH_SIZE 4 -# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) - -extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; - -/* Can't use raw_spin_lock_irq because of #include problems, so - * this is the substitute */ -#define _atomic_spin_lock_irqsave(l,f) do { \ - raw_spinlock_t *s = ATOMIC_HASH(l); \ - local_irq_save(f); \ - __raw_spin_lock(s); \ -} while(0) - -#define _atomic_spin_unlock_irqrestore(l,f) do { \ - raw_spinlock_t *s = ATOMIC_HASH(l); \ - __raw_spin_unlock(s); \ - local_irq_restore(f); \ -} while(0) - - -#else -# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) -# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) -#endif - -/* - * NMI events can occur at any time, including when interrupts have been - * disabled by *_irqsave(). So you can get NMI events occurring while a - * *_bit function is holding a spin lock. If the NMI handler also wants - * to do bit manipulation (and they do) then you can get a deadlock - * between the original caller of *_bit() and the NMI handler. - * - * by Keith Owens - */ - -/** - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * - * Note: there are no guarantees that this function will not be reordered - * on non x86 architectures, so if you are writing portable code, - * make sure not to rely on its reordering guarantees. - * - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void set_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p |= mask; - _atomic_spin_unlock_irqrestore(p, flags); -} - -/** - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() - * in order to ensure changes are visible on other processors. - */ -static inline void clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p &= ~mask; - _atomic_spin_unlock_irqrestore(p, flags); -} - -/** - * change_bit - Toggle a bit in memory - * @nr: Bit to change - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. It may be - * reordered on other architectures than x86. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void change_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p ^= mask; - _atomic_spin_unlock_irqrestore(p, flags); -} - -/** - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It may be reordered on other architectures than x86. - * It also implies a memory barrier. - */ -static inline int test_and_set_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old | mask; - _atomic_spin_unlock_irqrestore(p, flags); - - return (old & mask) != 0; -} - -/** - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It can be reorderdered on other architectures other than x86. - * It also implies a memory barrier. - */ -static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old & ~mask; - _atomic_spin_unlock_irqrestore(p, flags); - - return (old & mask) != 0; -} - -/** - * test_and_change_bit - Change a bit and return its old value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline int test_and_change_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old ^ mask; - _atomic_spin_unlock_irqrestore(p, flags); - - return (old & mask) != 0; -} - -#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ diff --git a/include/asm-nios2/bitops/ffs.h b/include/asm-nios2/bitops/ffs.h deleted file mode 100644 index fbbb43a..0000000 --- a/include/asm-nios2/bitops/ffs.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _ASM_GENERIC_BITOPS_FFS_H_ -#define _ASM_GENERIC_BITOPS_FFS_H_ - -/** - * ffs - find first bit set - * @x: the word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -static inline int ffs(int x) -{ - int r = 1; - - if (!x) - return 0; - if (!(x & 0xffff)) { - x >>= 16; - r += 16; - } - if (!(x & 0xff)) { - x >>= 8; - r += 8; - } - if (!(x & 0xf)) { - x >>= 4; - r += 4; - } - if (!(x & 3)) { - x >>= 2; - r += 2; - } - if (!(x & 1)) { - x >>= 1; - r += 1; - } - return r; -} - -#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */ diff --git a/include/asm-nios2/bitops/non-atomic.h b/include/asm-nios2/bitops/non-atomic.h deleted file mode 100644 index 697cc2b..0000000 --- a/include/asm-nios2/bitops/non-atomic.h +++ /dev/null @@ -1,108 +0,0 @@ -#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ -#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ - -#include - -/** - * __set_bit - Set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike set_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static inline void __set_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - - *p |= mask; -} - -static inline void __clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - - *p &= ~mask; -} - -/** - * __change_bit - Toggle a bit in memory - * @nr: the bit to change - * @addr: the address to start counting from - * - * Unlike change_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static inline void __change_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - - *p ^= mask; -} - -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old = *p; - - *p = old | mask; - return (old & mask) != 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old = *p; - - *p = old & ~mask; - return (old & mask) != 0; -} - -/* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, - volatile unsigned long *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old = *p; - - *p = old ^ mask; - return (old & mask) != 0; -} - -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile unsigned long *addr) -{ - return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); -} - -#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */ diff --git a/include/asm-nios2/byteorder.h b/include/asm-nios2/byteorder.h deleted file mode 100644 index 495c823..0000000 --- a/include/asm-nios2/byteorder.h +++ /dev/null @@ -1,30 +0,0 @@ -/* -* (C) Copyright 2004, Psyent Corporation -* Scott McNutt -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#ifndef __ASM_NIOS2_BYTEORDER_H_ -#define __ASM_NIOS2_BYTEORDER_H_ - -#include -#include - -#endif /* __ASM_NIOS2_BYTEORDER_H_ */ diff --git a/include/asm-nios2/cache.h b/include/asm-nios2/cache.h deleted file mode 100644 index c78f343..0000000 --- a/include/asm-nios2/cache.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_NIOS2_CACHE_H_ -#define __ASM_NIOS2_CACHE_H_ - -extern void flush_dcache (unsigned long start, unsigned long size); -extern void flush_icache (unsigned long start, unsigned long size); - -#endif /* __ASM_NIOS2_CACHE_H_ */ diff --git a/include/asm-nios2/config.h b/include/asm-nios2/config.h deleted file mode 100644 index 011d603..0000000 --- a/include/asm-nios2/config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -/* Relocation to SDRAM works on all NIOS2 boards */ -#define CONFIG_RELOC_FIXUP_WORKS - -#endif diff --git a/include/asm-nios2/errno.h b/include/asm-nios2/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/include/asm-nios2/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h deleted file mode 100644 index 34aa962..0000000 --- a/include/asm-nios2/global_data.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_NIOS2_GLOBALDATA_H_ -#define __ASM_NIOS2_GLOBALDATA_H_ - -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid */ -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - unsigned long post_log_word; /* Record POST activities */ - unsigned long post_init_f_time; /* When post_init_f started */ -#endif - void **jt; /* Standalone app jump table */ -} gd_t; - -/* flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r15") - -#endif /* __ASM_NIOS2_GLOBALDATA_H_ */ diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h deleted file mode 100644 index 121405c..0000000 --- a/include/asm-nios2/io.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_NIOS2_IO_H_ -#define __ASM_NIOS2_IO_H_ - -static inline void sync(void) -{ - __asm__ __volatile__ ("sync" : : : "memory"); -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -extern unsigned char inb (unsigned char *port); -extern unsigned short inw (unsigned short *port); -extern unsigned inl (unsigned port); - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -#define readb(addr)\ - ({unsigned char val;\ - asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) -#define readw(addr)\ - ({unsigned short val;\ - asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) -#define readl(addr)\ - ({unsigned long val;\ - asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) - -#define writeb(val,addr)\ - asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr)) -#define writew(val,addr)\ - asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr)) -#define writel(val,addr)\ - asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr)) - -#define inb(addr) readb(addr) -#define inw(addr) readw(addr) -#define inl(addr) readl(addr) -#define outb(val, addr) writeb(val,addr) -#define outw(val, addr) writew(val,addr) -#define outl(val, addr) writel(val,addr) - -static inline void insb (unsigned long port, void *dst, unsigned long count) -{ - unsigned char *p = dst; - while (count--) *p++ = inb (port); -} -static inline void insw (unsigned long port, void *dst, unsigned long count) -{ - unsigned short *p = dst; - while (count--) *p++ = inw (port); -} -static inline void insl (unsigned long port, void *dst, unsigned long count) -{ - unsigned long *p = dst; - while (count--) *p++ = inl (port); -} - -static inline void outsb (unsigned long port, const void *src, unsigned long count) -{ - const unsigned char *p = src; - while (count--) outb (*p++, port); -} - -static inline void outsw (unsigned long port, const void *src, unsigned long count) -{ - const unsigned short *p = src; - while (count--) outw (*p++, port); -} -static inline void outsl (unsigned long port, const void *src, unsigned long count) -{ - const unsigned long *p = src; - while (count--) outl (*p++, port); -} - -#endif /* __ASM_NIOS2_IO_H_ */ diff --git a/include/asm-nios2/opcodes.h b/include/asm-nios2/opcodes.h deleted file mode 100644 index 211f8ba..0000000 --- a/include/asm-nios2/opcodes.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_NIOS2_OPCODES_H_ -#define __ASM_NIOS2_OPCODES_H_ - -#define OPCODE_OP(inst) ((inst) & 0x3f) -#define OPCODE_OPX(inst) (((inst)>>11) & 0x3f) -#define OPCODE_RA(inst) (((inst)>>27) & 01f) -#define OPCODE_RB(inst) (((inst)>>22) & 01f) -#define OPCODE_RC(inst) (((inst)>>17) & 01f) - -/* I-TYPE (immediate) and J-TYPE (jump) opcodes - */ -#define OPCODE_CALL 0x00 -#define OPCODE_LDBU 0x03 -#define OPCODE_ADDI 0x04 -#define OPCODE_STB 0x05 -#define OPCODE_BR 0x06 -#define OPCODE_LDB 0x07 -#define OPCODE_CMPGEI 0x08 -#define OPCODE_LDHU 0x0B -#define OPCODE_ANDI 0x0C -#define OPCODE_STH 0x0D -#define OPCODE_BGE 0x0E -#define OPCODE_LDH 0x0F -#define OPCODE_CMPLTI 0x10 -#define OPCODE_XORI 0x1C -#define OPCODE_ORI 0x14 -#define OPCODE_STW 0x15 -#define OPCODE_BLT 0x16 -#define OPCODE_LDW 0x17 -#define OPCODE_CMPNEI 0x18 -#define OPCODE_BNE 0x1E -#define OPCODE_CMPEQI 0x20 -#define OPCODE_LDBUIO 0x23 -#define OPCODE_MULI 0x24 -#define OPCODE_STBIO 0x25 -#define OPCODE_BEQ 0x26 -#define OPCODE_LDBIO 0x27 -#define OPCODE_CMPGEUI 0x28 -#define OPCODE_ANDHI 0x2C -#define OPCODE_STHIO 0x2D -#define OPCODE_BGEU 0x2E -#define OPCODE_LDHIO 0x2F -#define OPCODE_CMPLTUI 0x30 -#define OPCODE_CUSTOM 0x32 -#define OPCODE_INITD 0x33 -#define OPCODE_ORHI 0x34 -#define OPCODE_STWIO 0x35 -#define OPCODE_BLTU 0x36 -#define OPCODE_LDWIO 0x37 -#define OPCODE_RTYPE 0x3A -#define OPCODE_LDHUIO 0x2B -#define OPCODE_FLUSHD 0x3B -#define OPCODE_XORHI 0x3C - -/* R-Type (register) OPX field encodings - */ -#define OPCODE_ERET 0x01 -#define OPCODE_ROLI 0x02 -#define OPCODE_ROL 0x03 -#define OPCODE_FLUSHP 0x04 -#define OPCODE_RET 0x05 -#define OPCODE_NOR 0x06 -#define OPCODE_MULXUU 0x07 -#define OPCODE_CMPGE 0x08 -#define OPCODE_BRET 0x09 -#define OPCODE_ROR 0x0B -#define OPCODE_FLUSHI 0x0C -#define OPCODE_JMP 0x0D -#define OPCODE_AND 0x0E - -#define OPCODE_CMPLT 0x10 -#define OPCODE_SLLI 0x12 -#define OPCODE_SLL 0x13 -#define OPCODE_OR 0x16 -#define OPCODE_MULXSU 0x17 -#define OPCODE_CMPNE 0x18 -#define OPCODE_SRLI 0x1A -#define OPCODE_SRL 0x1B -#define OPCODE_NEXTPC 0x1C -#define OPCODE_CALLR 0x1D -#define OPCODE_XOR 0x1E -#define OPCODE_MULXSS 0x1F - -#define OPCODE_CMPEQ 0x20 -#define OPCODE_CMPLTU 0x30 -#define OPCODE_ADD 0x31 -#define OPCODE_DIVU 0x24 -#define OPCODE_DIV 0x25 -#define OPCODE_RDCTL 0x26 -#define OPCODE_MUL 0x27 -#define OPCODE_CMPGEU 0x28 -#define OPCODE_TRAP 0x2D -#define OPCODE_WRCTL 0x2E - -#define OPCODE_BREAK 0x34 -#define OPCODE_SYNC 0x36 -#define OPCODE_INITI 0x29 -#define OPCODE_SUB 0x39 -#define OPCODE_SRAI 0x3A -#define OPCODE_SRA 0x3B - -/*Full instruction encodings for R-Type, without the R's ;-) - * - * TODO: BREAK, BRET, ERET, RET, SYNC (as needed) - */ -#define OPC_TRAP 0x003b683a - -#endif /* __ASM_NIOS2_OPCODES_H_ */ diff --git a/include/asm-nios2/posix_types.h b/include/asm-nios2/posix_types.h deleted file mode 100644 index c2deea6..0000000 --- a/include/asm-nios2/posix_types.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __ASM_NIOS2_POSIX_TYPES_H_ -#define __ASM_NIOS2_POSIX_TYPES_H_ - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned long __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) - -#undef __FD_CLR -#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) - -#undef __FD_ISSET -#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ - -#endif /* __ASM_NIOS2_POSIX_TYPES_H_ */ diff --git a/include/asm-nios2/processor.h b/include/asm-nios2/processor.h deleted file mode 100644 index 68502a5..0000000 --- a/include/asm-nios2/processor.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_NIOS2_PROCESSOR_H_ -#define __ASM_NIOS2_PROCESSOR_H_ -#endif /* __ASM_NIOS2_PROCESSOR_H_ */ diff --git a/include/asm-nios2/psr.h b/include/asm-nios2/psr.h deleted file mode 100644 index a498b46..0000000 --- a/include/asm-nios2/psr.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_NIOS2_PSR_H_ -#define __ASM_NIOS2_PSR_H_ - - -#endif /* __ASM_NIOS2_PSR_H_ */ diff --git a/include/asm-nios2/ptrace.h b/include/asm-nios2/ptrace.h deleted file mode 100644 index 5430880..0000000 --- a/include/asm-nios2/ptrace.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_NIOS2_PTRACE_H_ -#define __ASM_NIOS2_PTRACE_H_ - -struct pt_regs { - unsigned reg[32]; - unsigned status; -}; - - -#endif /* __ASM_NIOS2_PTRACE_H_ */ diff --git a/include/asm-nios2/status_led.h b/include/asm-nios2/status_led.h deleted file mode 100644 index 20f8d90..0000000 --- a/include/asm-nios2/status_led.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_STATUS_LED_H__ -#define __ASM_STATUS_LED_H__ - -typedef unsigned led_id_t; -extern void __led_init (led_id_t mask, int state); -extern void __led_set (led_id_t mask, int state); -inline void __led_toggle (led_id_t mask); - -#endif /* __ASM_STATUS_LED_H__ */ diff --git a/include/asm-nios2/string.h b/include/asm-nios2/string.h deleted file mode 100644 index e864903..0000000 --- a/include/asm-nios2/string.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_NIOS2_STRING_H_ -#define __ASM_NIOS2_STRING_H_ - -#undef __HAVE_ARCH_STRRCHR -extern char * strrchr(const char * s, int c); - -#undef __HAVE_ARCH_STRCHR -extern char * strchr(const char * s, int c); - -#undef __HAVE_ARCH_MEMCPY -extern void * memcpy(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMMOVE -extern void * memmove(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMCHR -extern void * memchr(const void *, int, __kernel_size_t); - -#undef __HAVE_ARCH_MEMSET -extern void * memset(void *, int, __kernel_size_t); - -#undef __HAVE_ARCH_MEMZERO -extern void memzero(void *ptr, __kernel_size_t n); - -#endif /* __ASM_NIOS2_STRING_H_ */ diff --git a/include/asm-nios2/system.h b/include/asm-nios2/system.h deleted file mode 100644 index bb03ca5..0000000 --- a/include/asm-nios2/system.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_NIOS2_SYSTEM_H_ -#define __ASM_NIOS2_SYSTEM_H_ - -#define local_irq_enable() __asm__ __volatile__ ( \ - "rdctl r8, status\n" \ - "ori r8, r8, 1\n" \ - "wrctl status, r8\n" \ - : : : "r8") - -#define local_irq_disable() __asm__ __volatile__ ( \ - "rdctl r8, status\n" \ - "andi r8, r8, 0xfffe\n" \ - "wrctl status, r8\n" \ - : : : "r8") - -#define local_save_flags(x) __asm__ __volatile__ ( \ - "rdctl r8, status\n" \ - "mov %0, r8\n" \ - : "=r" (x) : : "r8", "memory") - -#define local_irq_restore(x) __asm__ __volatile__ ( \ - "mov r8, %0\n" \ - "wrctl status, r8\n" \ - : : "r" (x) : "r8", "memory") - -/* For spinlocks etc */ -#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \ - while (0) - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ -}) - -#endif /* __ASM_NIOS2_SYSTEM_H */ diff --git a/include/asm-nios2/types.h b/include/asm-nios2/types.h deleted file mode 100644 index ea859c0..0000000 --- a/include/asm-nios2/types.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __ASM_NIOS2_TYPES_H_ -#define __ASM_NIOS2_TYPES_H_ - -/* - * This file is never included by application software unless - * explicitly requested (e.g., via linux/types.h) in which case the - * application is Linux specific so (user-) name space pollution is - * not a major issue. However, for interoperability, libraries still - * need to be careful to avoid a name clashes. - */ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; -#endif /* __KERNEL__ */ - -#endif /* __ASM_NIOS2_TYPES_H */ diff --git a/include/asm-nios2/u-boot.h b/include/asm-nios2/u-boot.h deleted file mode 100644 index ec844d0..0000000 --- a/include/asm-nios2/u-boot.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef __ASM_NIOS2_U_BOOT_H_ -#define __ASM_NIOS2_U_BOOT_H_ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned long bi_baudrate; /* Console Baudrate */ -} bd_t; - - -#endif /* __ASM_NIOS2_U_BOOT_H_ */ diff --git a/include/asm-nios2/unaligned.h b/include/asm-nios2/unaligned.h deleted file mode 100644 index 779117c..0000000 --- a/include/asm-nios2/unaligned.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_NIOS2_UNALIGNED_H -#define _ASM_NIOS2_UNALIGNED_H - -#include - -#endif /* _ASM_NIOS2_UNALIGNED_H */ diff --git a/include/asm-ppc/4xx_pci.h b/include/asm-ppc/4xx_pci.h deleted file mode 100644 index f686e7c..0000000 --- a/include/asm-ppc/4xx_pci.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef _405GP_PCI_H -#define _405GP_PCI_H - -#include - -/*----------------------------------------------------------------------------+ -| 405GP PCI core memory map defines. -+----------------------------------------------------------------------------*/ -#define MIN_PCI_MEMADDR1 0x80000000 -#define MIN_PCI_MEMADDR2 0x00000000 -#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ -#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ -#define MAX_PCI_DEVICES 32 - -/*----------------------------------------------------------------------------+ -| Defines for the 405GP PCI Config address and data registers followed by -| defines for the standard PCI device configuration header. -+----------------------------------------------------------------------------*/ -#define PCICFGADR 0xEEC00000 -#define PCICFGDATA 0xEEC00004 - -#define PCIBUSNUM 0x40 /* 405GP specific parameters */ -#define PCISUBBUSNUM 0x41 -#define PCIDISCOUNT 0x42 -#define PCIBRDGOPT1 0x4A -#define PCIBRDGOPT2 0x60 - -/*----------------------------------------------------------------------------+ -| Defines for 405GP PCI Master local configuration regs. -+----------------------------------------------------------------------------*/ -#define PMM0LA 0xEF400000 -#define PMM0MA 0xEF400004 -#define PMM0PCILA 0xEF400008 -#define PMM0PCIHA 0xEF40000C -#define PMM1LA 0xEF400010 -#define PMM1MA 0xEF400014 -#define PMM1PCILA 0xEF400018 -#define PMM1PCIHA 0xEF40001C -#define PMM2LA 0xEF400020 -#define PMM2MA 0xEF400024 -#define PMM2PCILA 0xEF400028 -#define PMM2PCIHA 0xEF40002C - -/*----------------------------------------------------------------------------+ -| Defines for 405GP PCI Target local configuration regs. -+----------------------------------------------------------------------------*/ -#define PTM1MS 0xEF400030 -#define PTM1LA 0xEF400034 -#define PTM2MS 0xEF400038 -#define PTM2LA 0xEF40003C - -#define PCIDEVID_405GP 0x0 - -void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev); -int pci_arbiter_enabled(void); -int __pci_pre_init(struct pci_controller *hose); -void __pci_target_init(struct pci_controller *hose); -void __pci_master_init(struct pci_controller *hose); - -#endif diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h deleted file mode 100644 index a0e88de..0000000 --- a/include/asm-ppc/4xx_pcie.h +++ /dev/null @@ -1,417 +0,0 @@ -/* - * Copyright (c) 2005 Cisco Systems. All rights reserved. - * Roland Dreier - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __4XX_PCIE_H -#define __4XX_PCIE_H - -#include -#include - -#define DCRN_SDR0_CFGADDR 0x00e -#define DCRN_SDR0_CFGDATA 0x00f - -#if defined(CONFIG_440SPE) -#define CONFIG_SYS_PCIE_NR_PORTS 3 - -#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d - -#define DCRN_PCIE0_BASE 0x100 -#define DCRN_PCIE1_BASE 0x120 -#define DCRN_PCIE2_BASE 0x140 - -#define PCIE0_SDR 0x300 -#define PCIE1_SDR 0x340 -#define PCIE2_SDR 0x370 -#endif - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define CONFIG_SYS_PCIE_NR_PORTS 2 - -#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d - -#define DCRN_PCIE0_BASE 0x100 -#define DCRN_PCIE1_BASE 0x120 - -#define PCIE0_SDR 0x300 -#define PCIE1_SDR 0x340 -#endif - -#if defined(CONFIG_405EX) -#define CONFIG_SYS_PCIE_NR_PORTS 2 - -#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000 - -#define DCRN_PCIE0_BASE 0x040 -#define DCRN_PCIE1_BASE 0x060 - -#define PCIE0_SDR 0x400 -#define PCIE1_SDR 0x440 -#endif - -#define PCIE0 DCRN_PCIE0_BASE -#define PCIE1 DCRN_PCIE1_BASE -#define PCIE2 DCRN_PCIE2_BASE - -#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) -#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) -#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) -#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) -#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) -#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) -#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) -#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) -#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) -#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) -#define DCRN_PEGPL_REGBAH(base) (base + 0x12) -#define DCRN_PEGPL_REGBAL(base) (base + 0x13) -#define DCRN_PEGPL_REGMSK(base) (base + 0x14) -#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) -#define DCRN_PEGPL_CFG(base) (base + 0x16) - -/* - * System DCRs (SDRs) - */ -#define PESDR0_PLLLCT1 0x03a0 -#define PESDR0_PLLLCT2 0x03a1 -#define PESDR0_PLLLCT3 0x03a2 - -/* common regs, at for all 4xx with PCIe core */ -#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00) -#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01) -#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02) -#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03) -#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04) -#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05) - -#if defined(CONFIG_440SPE) -#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06) -#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07) -#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08) -#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09) -#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a) -#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b) -#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c) -#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d) -#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e) -#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f) -#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10) -#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11) - -#define PESDR0_UTLSET1 0x0300 -#define PESDR0_UTLSET2 0x0301 -#define PESDR0_DLPSET 0x0302 -#define PESDR0_LOOP 0x0303 -#define PESDR0_RCSSET 0x0304 -#define PESDR0_RCSSTS 0x0305 -#define PESDR0_HSSL0SET1 0x0306 -#define PESDR0_HSSL0SET2 0x0307 -#define PESDR0_HSSL0STS 0x0308 -#define PESDR0_HSSL1SET1 0x0309 -#define PESDR0_HSSL1SET2 0x030a -#define PESDR0_HSSL1STS 0x030b -#define PESDR0_HSSL2SET1 0x030c -#define PESDR0_HSSL2SET2 0x030d -#define PESDR0_HSSL2STS 0x030e -#define PESDR0_HSSL3SET1 0x030f -#define PESDR0_HSSL3SET2 0x0310 -#define PESDR0_HSSL3STS 0x0311 -#define PESDR0_HSSL4SET1 0x0312 -#define PESDR0_HSSL4SET2 0x0313 -#define PESDR0_HSSL4STS 0x0314 -#define PESDR0_HSSL5SET1 0x0315 -#define PESDR0_HSSL5SET2 0x0316 -#define PESDR0_HSSL5STS 0x0317 -#define PESDR0_HSSL6SET1 0x0318 -#define PESDR0_HSSL6SET2 0x0319 -#define PESDR0_HSSL6STS 0x031a -#define PESDR0_HSSL7SET1 0x031b -#define PESDR0_HSSL7SET2 0x031c -#define PESDR0_HSSL7STS 0x031d -#define PESDR0_HSSCTLSET 0x031e -#define PESDR0_LANE_ABCD 0x031f -#define PESDR0_LANE_EFGH 0x0320 - -#define PESDR1_UTLSET1 0x0340 -#define PESDR1_UTLSET2 0x0341 -#define PESDR1_DLPSET 0x0342 -#define PESDR1_LOOP 0x0343 -#define PESDR1_RCSSET 0x0344 -#define PESDR1_RCSSTS 0x0345 -#define PESDR1_HSSL0SET1 0x0346 -#define PESDR1_HSSL0SET2 0x0347 -#define PESDR1_HSSL0STS 0x0348 -#define PESDR1_HSSL1SET1 0x0349 -#define PESDR1_HSSL1SET2 0x034a -#define PESDR1_HSSL1STS 0x034b -#define PESDR1_HSSL2SET1 0x034c -#define PESDR1_HSSL2SET2 0x034d -#define PESDR1_HSSL2STS 0x034e -#define PESDR1_HSSL3SET1 0x034f -#define PESDR1_HSSL3SET2 0x0350 -#define PESDR1_HSSL3STS 0x0351 -#define PESDR1_HSSCTLSET 0x0352 -#define PESDR1_LANE_ABCD 0x0353 - -#define PESDR2_UTLSET1 0x0370 -#define PESDR2_UTLSET2 0x0371 -#define PESDR2_DLPSET 0x0372 -#define PESDR2_LOOP 0x0373 -#define PESDR2_RCSSET 0x0374 -#define PESDR2_RCSSTS 0x0375 -#define PESDR2_HSSL0SET1 0x0376 -#define PESDR2_HSSL0SET2 0x0377 -#define PESDR2_HSSL0STS 0x0378 -#define PESDR2_HSSL1SET1 0x0379 -#define PESDR2_HSSL1SET2 0x037a -#define PESDR2_HSSL1STS 0x037b -#define PESDR2_HSSL2SET1 0x037c -#define PESDR2_HSSL2SET2 0x037d -#define PESDR2_HSSL2STS 0x037e -#define PESDR2_HSSL3SET1 0x037f -#define PESDR2_HSSL3SET2 0x0380 -#define PESDR2_HSSL3STS 0x0381 -#define PESDR2_HSSCTLSET 0x0382 -#define PESDR2_LANE_ABCD 0x0383 - -#elif defined(CONFIG_405EX) - -#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06) -#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07) -#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08) -#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b) -#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c) - -#define PESDR0_UTLSET1 0x0400 -#define PESDR0_UTLSET2 0x0401 -#define PESDR0_DLPSET 0x0402 -#define PESDR0_LOOP 0x0403 -#define PESDR0_RCSSET 0x0404 -#define PESDR0_RCSSTS 0x0405 -#define PESDR0_PHYSET1 0x0406 -#define PESDR0_PHYSET2 0x0407 -#define PESDR0_BIST 0x0408 -#define PESDR0_LPB 0x040B -#define PESDR0_PHYSTA 0x040C - -#define PESDR1_UTLSET1 0x0440 -#define PESDR1_UTLSET2 0x0441 -#define PESDR1_DLPSET 0x0442 -#define PESDR1_LOOP 0x0443 -#define PESDR1_RCSSET 0x0444 -#define PESDR1_RCSSTS 0x0445 -#define PESDR1_PHYSET1 0x0446 -#define PESDR1_PHYSET2 0x0447 -#define PESDR1_BIST 0x0448 -#define PESDR1_LPB 0x044B -#define PESDR1_PHYSTA 0x044C - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define PESDR0_L0BIST 0x0308 /* PE0 L0 built in self test */ -#define PESDR0_L0BISTSTS 0x0309 /* PE0 L0 built in self test status */ -#define PESDR0_L0CDRCTL 0x030A /* PE0 L0 CDR control */ -#define PESDR0_L0DRV 0x030B /* PE0 L0 drive */ -#define PESDR0_L0REC 0x030C /* PE0 L0 receiver */ -#define PESDR0_L0LPB 0x030D /* PE0 L0 loopback */ -#define PESDR0_L0CLK 0x030E /* PE0 L0 clocking */ -#define PESDR0_PHY_CTL_RST 0x030F /* PE0 PHY control reset */ -#define PESDR0_RSTSTA 0x0310 /* PE0 reset status */ -#define PESDR0_OBS 0x0311 /* PE0 observation register */ -#define PESDR0_L0ERRC 0x0320 /* PE0 L0 error counter */ - -#define PESDR1_L0BIST 0x0348 /* PE1 L0 built in self test */ -#define PESDR1_L1BIST 0x0349 /* PE1 L1 built in self test */ -#define PESDR1_L2BIST 0x034A /* PE1 L2 built in self test */ -#define PESDR1_L3BIST 0x034B /* PE1 L3 built in self test */ -#define PESDR1_L0BISTSTS 0x034C /* PE1 L0 built in self test status */ -#define PESDR1_L1BISTSTS 0x034D /* PE1 L1 built in self test status */ -#define PESDR1_L2BISTSTS 0x034E /* PE1 L2 built in self test status */ -#define PESDR1_L3BISTSTS 0x034F /* PE1 L3 built in self test status */ -#define PESDR1_L0CDRCTL 0x0350 /* PE1 L0 CDR control */ -#define PESDR1_L1CDRCTL 0x0351 /* PE1 L1 CDR control */ -#define PESDR1_L2CDRCTL 0x0352 /* PE1 L2 CDR control */ -#define PESDR1_L3CDRCTL 0x0353 /* PE1 L3 CDR control */ -#define PESDR1_L0DRV 0x0354 /* PE1 L0 drive */ -#define PESDR1_L1DRV 0x0355 /* PE1 L1 drive */ -#define PESDR1_L2DRV 0x0356 /* PE1 L2 drive */ -#define PESDR1_L3DRV 0x0357 /* PE1 L3 drive */ -#define PESDR1_L0REC 0x0358 /* PE1 L0 receiver */ -#define PESDR1_L1REC 0x0359 /* PE1 L1 receiver */ -#define PESDR1_L2REC 0x035A /* PE1 L2 receiver */ -#define PESDR1_L3REC 0x035B /* PE1 L3 receiver */ -#define PESDR1_L0LPB 0x035C /* PE1 L0 loopback */ -#define PESDR1_L1LPB 0x035D /* PE1 L1 loopback */ -#define PESDR1_L2LPB 0x035E /* PE1 L2 loopback */ -#define PESDR1_L3LPB 0x035F /* PE1 L3 loopback */ -#define PESDR1_L0CLK 0x0360 /* PE1 L0 clocking */ -#define PESDR1_L1CLK 0x0361 /* PE1 L1 clocking */ -#define PESDR1_L2CLK 0x0362 /* PE1 L2 clocking */ -#define PESDR1_L3CLK 0x0363 /* PE1 L3 clocking */ -#define PESDR1_PHY_CTL_RST 0x0364 /* PE1 PHY control reset */ -#define PESDR1_RSTSTA 0x0365 /* PE1 reset status */ -#define PESDR1_OBS 0x0366 /* PE1 observation register */ -#define PESDR1_L0ERRC 0x0368 /* PE1 L0 error counter */ -#define PESDR1_L1ERRC 0x0369 /* PE1 L1 error counter */ -#define PESDR1_L2ERRC 0x036A /* PE1 L2 error counter */ -#define PESDR1_L3ERRC 0x036B /* PE1 L3 error counter */ -#define PESDR0_IHS1 0x036C /* PE interrupt handler interfact setting 1 */ -#define PESDR0_IHS2 0x036D /* PE interrupt handler interfact setting 2 */ - -#endif - -/* SDR Bit Mappings */ -#define PESDRx_RCSSET_HLDPLB 0x10000000 -#define PESDRx_RCSSET_RSTGU 0x01000000 -#define PESDRx_RCSSET_RDY 0x00100000 -#define PESDRx_RCSSET_RSTDL 0x00010000 -#define PESDRx_RCSSET_RSTPYN 0x00001000 - -#define PESDRx_RCSSTS_PLBIDL 0x10000000 -#define PESDRx_RCSSTS_HRSTRQ 0x01000000 -#define PESDRx_RCSSTS_PGRST 0x00100000 -#define PESDRx_RCSSTS_VC0ACT 0x00010000 -#define PESDRx_RCSSTS_BMEN 0x00000100 - -/* - * UTL register offsets - */ -#define PEUTL_PBCTL 0x00 -#define PEUTL_PBBSZ 0x20 -#define PEUTL_OPDBSZ 0x68 -#define PEUTL_IPHBSZ 0x70 -#define PEUTL_IPDBSZ 0x78 -#define PEUTL_OUTTR 0x90 -#define PEUTL_INTR 0x98 -#define PEUTL_PCTL 0xa0 -#define PEUTL_RCSTA 0xb0 -#define PEUTL_RCIRQEN 0xb8 - -/* - * Config space register offsets - */ -#define PECFG_BAR0LMPA 0x210 -#define PECFG_BAR0HMPA 0x214 -#define PECFG_BAR1MPA 0x218 -#define PECFG_BAR2LMPA 0x220 -#define PECFG_BAR2HMPA 0x224 - -#define PECFG_PIMEN 0x33c -#define PECFG_PIM0LAL 0x340 -#define PECFG_PIM0LAH 0x344 -#define PECFG_PIM1LAL 0x348 -#define PECFG_PIM1LAH 0x34c -#define PECFG_PIM01SAL 0x350 -#define PECFG_PIM01SAH 0x354 - -#define PECFG_POM0LAL 0x380 -#define PECFG_POM0LAH 0x384 - -#define SDR_READ(offset) ({\ - mtdcr(DCRN_SDR0_CFGADDR, offset); \ - mfdcr(DCRN_SDR0_CFGDATA);}) - -#define SDR_WRITE(offset, data) ({\ - mtdcr(DCRN_SDR0_CFGADDR, offset); \ - mtdcr(DCRN_SDR0_CFGDATA,data);}) - -#define GPL_DMER_MASK_DISA 0x02000000 - -#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) -#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) - -/* - * Prototypes - */ -int ppc4xx_init_pcie(void); -int ppc4xx_init_pcie_rootport(int port); -int ppc4xx_init_pcie_endport(int port); -void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port); -int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port); -int pcie_hose_scan(struct pci_controller *hose, int bus); - -/* - * Function to determine root port or endport from env variable. - */ -static inline int is_end_point(int port) -{ - char s[10], *tk; - char *pcie_mode = getenv("pcie_mode"); - - if (pcie_mode == NULL) - return 0; - - strcpy(s, pcie_mode); - tk = strtok(s, ":"); - - switch (port) { - case 0: - if (tk != NULL) { - if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) - return 1; - else - return 0; - } - else - return 0; - - case 1: - tk = strtok(NULL, ":"); - if (tk != NULL) { - if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) - return 1; - else - return 0; - } - else - return 0; - - case 2: - tk = strtok(NULL, ":"); - if (tk != NULL) - tk = strtok(NULL, ":"); - if (tk != NULL) { - if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) - return 1; - else - return 0; - } - else - return 0; - } - - return 0; -} - -static inline void mdelay(int n) -{ - u32 ms = n; - - while (ms--) - udelay(1000); -} - -#if defined(PCIE0_SDR) -static inline u32 sdr_base(int port) -{ - switch (port) { - default: /* to satisfy compiler */ - case 0: - return PCIE0_SDR; - case 1: - return PCIE1_SDR; -#if CONFIG_SYS_PCIE_NR_PORTS > 2 - case 2: - return PCIE2_SDR; -#endif - } -} -#endif /* defined(PCIE0_SDR) */ - -#endif /* __4XX_PCIE_H */ diff --git a/include/asm-ppc/5xx_immap.h b/include/asm-ppc/5xx_immap.h deleted file mode 100644 index 72cbab4..0000000 --- a/include/asm-ppc/5xx_immap.h +++ /dev/null @@ -1,439 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, - */ - -/* - * File: 5xx_immap.h - * - * Discription: MPC555 Internal Memory Map - * - */ - -#ifndef __IMMAP_5XX__ -#define __IMMAP_5XX__ - -/* System Configuration Registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - char res1[6]; - ushort sc_swsr; - uint sc_sipend; - uint sc_simask; - uint sc_siel; - uint sc_sivec; - uint sc_tesr; - uint sc_sgpiodt1; - uint sc_sgpiodt2; - uint sc_sgpiocr; - uint sc_emcr; - uint sc_res1aa; - uint sc_res1ab; - uint sc_pdmcr; - char res3[192]; -} sysconf5xx_t; - - -/* Memory Controller Registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - char res1[32]; - uint memc_dmbr; - uint memc_dmor; - char res2[48]; - ushort memc_mstat; - ushort memc_res4a; - char res3[132]; -} memctl5xx_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - ushort sit_tbscr; - char res1[2]; - uint sit_tbref0; - uint sit_tbref1; - char res2[20]; - ushort sit_rtcsc; - char res3[2]; - uint sit_rtc; - uint sit_rtsec; - uint sit_rtcal; - char res4[16]; - ushort sit_piscr; - char res5[2]; - uint sit_pitc; - uint sit_pitr; - char res6[52]; -} sit5xx_t; - -/* Clocks and Reset -*/ -typedef struct clk_and_reset { - uint car_sccr; - uint car_plprcr; - ushort car_rsr; - ushort car_res7a; - ushort car_colir; - ushort car_res7b; - ushort car_vsrmcr; - ushort car_res7c; - char res1[108]; - -} car5xx_t; - -#define TBSCR_TBE ((ushort)0x0001) - -/* System Integration Timer Keys -*/ -typedef struct sitk { - uint sitk_tbscrk; - uint sitk_tbref0k; - uint sitk_tbref1k; - uint sitk_tbk; - char res1[16]; - uint sitk_rtcsck; - uint sitk_rtck; - uint sitk_rtseck; - uint sitk_rtcalk; - char res2[16]; - uint sitk_piscrk; - uint sitk_pitck; - char res3[56]; -} sitk5xx_t; - -/* Clocks and Reset Keys. -*/ -typedef struct cark { - uint cark_sccrk; - uint cark_plprcrk; - uint cark_rsrk; - char res1[1140]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* Flash Configuration -*/ -typedef struct fl { - uint fl_cmfmcr; - uint fl_cmftst; - uint fl_cmfctl; - char res1[52]; -} fl5xx_t; - -/* Dpram Control -*/ -typedef struct dprc { - ushort dprc_dptmcr; - ushort dprc_ramtst; - ushort dprc_rambar; - ushort dprc_misrh; - ushort dprc_misrl; - ushort dprc_miscnt; -} dprc5xx_t; - -/* Time Processor Unit -*/ -typedef struct tpu { - ushort tpu_tpumcr; - ushort tpu_tcr; - ushort tpu_dscr; - ushort tpu_dssr; - ushort tpu_ticr; - ushort tpu_cier; - ushort tpu_cfsr0; - ushort tpu_cfsr1; - ushort tpu_cfsr2; - ushort tpu_cfsr3; - ushort tpu_hsqr0; - ushort tpu_hsqr1; - ushort tpu_hsrr0; - ushort tpu_hsrr1; - ushort tpu_cpr0; - ushort tpu_cpr1; - ushort tpu_cisr; - ushort tpu_lr; - ushort tpu_sglr; - ushort tpu_dcnr; - ushort tpu_tpumcr2; - ushort tpu_tpumcr3; - ushort tpu_isdr; - ushort tpu_iscr; - char res1[208]; - char tpu[16][16]; - char res2[512]; -} tpu5xx_t; - -/* QADC -*/ -typedef struct qadc { - ushort qadc_64mcr; - ushort qadc_64test; - ushort qadc_64int; - u_char qadc_portqa; - u_char qadc_portqb; - ushort qadc_ddrqa; - ushort qadc_qacr0; - ushort qadc_qacr1; - ushort qadc_qacr2; - ushort qadc_qasr0; - ushort qadc_qasr1; - char res1[492]; - /* command convertion word table */ - ushort qadc_ccw[64]; - /* result word table, unsigned right justified */ - ushort qadc_rjurr[64]; - /* result word table, signed left justified */ - ushort qadc_ljsrr[64]; - /* result word table, unsigned left justified */ - ushort qadc_ljurr[64]; -} qadc5xx_t; - -/* QSMCM -*/ -typedef struct qsmcm { - ushort qsmcm_qsmcr; - ushort qsmcm_qtest; - ushort qsmcm_qdsci_il; - ushort qsmcm_qspi_il; - ushort qsmcm_scc1r0; - ushort qsmcm_scc1r1; - ushort qsmcm_sc1sr; - ushort qsmcm_sc1dr; - char res1[2]; - char res2[2]; - ushort qsmcm_portqs; - u_char qsmcm_pqspar; - u_char qsmcm_ddrqs; - ushort qsmcm_spcr0; - ushort qsmcm_spcr1; - ushort qsmcm_spcr2; - u_char qsmcm_spcr3; - u_char qsmcm_spsr; - ushort qsmcm_scc2r0; - ushort qsmcm_scc2r1; - ushort qsmcm_sc2sr; - ushort qsmcm_sc2dr; - ushort qsmcm_qsci1cr; - ushort qsmcm_qsci1sr; - ushort qsmcm_sctq[16]; - ushort qsmcm_scrq[16]; - char res3[212]; - ushort qsmcm_recram[32]; - ushort qsmcm_tranram[32]; - u_char qsmcm_comdram[32]; - char res[3616]; -} qsmcm5xx_t; - - -/* MIOS -*/ - -typedef struct mios { - ushort mios_mpwmsm0perr; /* mpwmsm0 */ - ushort mios_mpwmsm0pulr; - ushort mios_mpwmsm0cntr; - ushort mios_mpwmsm0scr; - ushort mios_mpwmsm1perr; /* mpwmsm1 */ - ushort mios_mpwmsm1pulr; - ushort mios_mpwmsm1cntr; - ushort mios_mpwmsm1scr; - ushort mios_mpwmsm2perr; /* mpwmsm2 */ - ushort mios_mpwmsm2pulr; - ushort mios_mpwmsm2cntr; - ushort mios_mpwmsm2scr; - ushort mios_mpwmsm3perr; /* mpwmsm3 */ - ushort mios_mpwmsm3pulr; - ushort mios_mpwmsm3cntr; - ushort mios_mpwmsm3scr; - char res1[16]; - ushort mios_mmcsm6cnt; /* mmcsm6 */ - ushort mios_mmcsm6mlr; - ushort mios_mmcsm6scrd, mmcsm6scr; - char res2[32]; - ushort mios_mdasm11ar; /* mdasm11 */ - ushort mios_mdasm11br; - ushort mios_mdasm11scrd, mdasm11scr; - ushort mios_mdasm12ar; /* mdasm12 */ - ushort mios_mdasm12br; - ushort mios_mdasm12scrd, mdasm12scr; - ushort mios_mdasm13ar; /* mdasm13 */ - ushort mios_mdasm13br; - ushort mios_mdasm13scrd, mdasm13scr; - ushort mios_mdasm14ar; /* mdasm14 */ - ushort mios_mdasm14br; - ushort mios_mdasm14scrd, mdasm14scr; - ushort mios_mdasm15ar; /* mdasm15 */ - ushort mios_mdasm15br; - ushort mios_mdasm15scrd, mdasm15scr; - ushort mios_mpwmsm16perr; /* mpwmsm16 */ - ushort mios_mpwmsm16pulr; - ushort mios_mpwmsm16cntr; - ushort mios_mpwmsm16scr; - ushort mios_mpwmsm17perr; /* mpwmsm17 */ - ushort mios_mpwmsm17pulr; - ushort mios_mpwmsm17cntr; - ushort mios_mpwmsm17scr; - ushort mios_mpwmsm18perr; /* mpwmsm18 */ - ushort mios_mpwmsm18pulr; - ushort mios_mpwmsm18cntr; - ushort mios_mpwmsm18scr; - ushort mios_mpwmsm19perr; /* mpwmsm19 */ - ushort mios_mpwmsm19pulr; - ushort mios_mpwmsm19cntr; - ushort mios_mpwmsm19scr; - char res3[16]; - ushort mios_mmcsm22cnt; /* mmcsm22 */ - ushort mios_mmcsm22mlr; - ushort mios_mmcsm22scrd, mmcsm22scr; - char res4[32]; - ushort mios_mdasm27ar; /* mdasm27 */ - ushort mios_mdasm27br; - ushort mios_mdasm27scrd, mdasm27scr; - ushort mios_mdasm28ar; /*mdasm28 */ - ushort mios_mdasm28br; - ushort mios_mdasm28scrd, mdasm28scr; - ushort mios_mdasm29ar; /* mdasm29 */ - ushort mios_mdasm29br; - ushort mios_mdasm29scrd, mdasm29scr; - ushort mios_mdasm30ar; /* mdasm30 */ - ushort mios_mdasm30br; - ushort mios_mdasm30scrd, mdasm30scr; - ushort mios_mdasm31ar; /* mdasm31 */ - ushort mios_mdasm31br; - ushort mios_mdasm31scrd, mdasm31scr; - ushort mios_mpiosm32dr; - ushort mios_mpiosm32ddr; - char res5[1788]; - ushort mios_mios1tpcr; - char mios_res13[2]; - ushort mios_mios1vnr; - ushort mios_mios1mcr; - char res6[12]; - ushort mios_res42z; - ushort mios_mcpsmscr; - char res7[1000]; - ushort mios_mios1sr0; - char res12[2]; - ushort mios_mios1er0; - ushort mios_mios1rpr0; - char res8[40]; - ushort mios_mios1lvl0; - char res9[14]; - ushort mios_mios1sr1; - char res10[2]; - ushort mios_mios1er1; - ushort mios_mios1rpr1; - char res11[40]; - ushort mios_mios1lvl1; - char res13[1038]; -} mios5xx_t; - -/* Toucan Module -*/ -typedef struct tcan { - ushort tcan_tcnmcr; - ushort tcan_cantcr; - ushort tcan_canicr; - u_char tcan_canctrl0; - u_char tcan_canctrl1; - u_char tcan_presdiv; - u_char tcan_canctrl2; - ushort tcan_timer; - char res1[4]; - ushort tcan_rxgmskhi; - ushort tcan_rxgmsklo; - ushort tcan_rx14mskhi; - ushort tcan_rx14msklo; - ushort tcan_rx15mskhi; - ushort tcan_rx15msklo; - char res2[4]; - ushort tcan_estat; - ushort tcan_imask; - ushort tcan_iflag; - u_char tcan_rxectr; - u_char tcan_txectr; - char res3[88]; - struct { - ushort scr; - ushort id_high; - ushort id_low; - u_char data[8]; - char res4[2]; - } tcan_mbuff[16]; - char res5[640]; -} tcan5xx_t; - -/* UIMB -*/ -typedef struct uimb { - uint uimb_umcr; - char res1[12]; - uint uimb_utstcreg; - char res2[12]; - uint uimb_uipend; -} uimb5xx_t; - - -/* Internal Memory Map MPC555 -*/ -typedef struct immap { - char res1[262144]; /* CMF Flash A 256 Kbytes */ - char res2[196608]; /* CMF Flash B 192 Kbytes */ - char res3[2670592]; /* Reserved for Flash */ - sysconf5xx_t im_siu_conf; /* SIU Configuration */ - memctl5xx_t im_memctl; /* Memory Controller */ - sit5xx_t im_sit; /* System Integration Timers */ - car5xx_t im_clkrst; /* Clocks and Reset */ - sitk5xx_t im_sitk; /* System Integration Timer Keys*/ - cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ - fl5xx_t im_fla; /* Flash Module A */ - fl5xx_t im_flb; /* Flash Module B */ - char res4[14208]; /* Reserved for SIU */ - dprc5xx_t im_dprc; /* Dpram Control Register */ - char res5[8180]; /* Reserved */ - char dptram[6144]; /* Dptram */ - char res6[2048]; /* Reserved */ - tpu5xx_t im_tpua; /* Time Proessing Unit A */ - tpu5xx_t im_tpub; /* Time Processing Unit B */ - qadc5xx_t im_qadca; /* QADC A */ - qadc5xx_t im_qadcb; /* QADC B */ - qsmcm5xx_t im_qsmcm; /* SCI and SPI */ - mios5xx_t im_mios; /* MIOS */ - tcan5xx_t im_tcana; /* Toucan A */ - tcan5xx_t im_tcanb; /* Toucan B */ - char res7[1792]; /* Reserved */ - uimb5xx_t im_uimb; /* UIMB */ -} immap_t; - -#endif /* __IMMAP_5XX__ */ diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h deleted file mode 100644 index 40679cb..0000000 --- a/include/asm-ppc/8xx_immap.h +++ /dev/null @@ -1,511 +0,0 @@ - -/* - * MPC8xx Internal Memory Map - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * The I/O on the MPC860 is comprised of blocks of special registers - * and the dual port ram for the Communication Processor Module. - * Within this space are functional units such as the SIU, memory - * controller, system timers, and other control functions. It is - * a combination that I found difficult to separate into logical - * functional files.....but anyone else is welcome to try. -- Dan - */ -#ifndef __IMMAP_8XX__ -#define __IMMAP_8XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - uint sc_swt; - char res1[2]; - ushort sc_swsr; - uint sc_sipend; - uint sc_simask; - uint sc_siel; - uint sc_sivec; - uint sc_tesr; - char res2[0xc]; - uint sc_sdcr; - char res3[0x4c]; -} sysconf8xx_t; - -/* PCMCIA configuration registers. -*/ -typedef struct pcmcia_conf { - uint pcmc_pbr0; - uint pcmc_por0; - uint pcmc_pbr1; - uint pcmc_por1; - uint pcmc_pbr2; - uint pcmc_por2; - uint pcmc_pbr3; - uint pcmc_por3; - uint pcmc_pbr4; - uint pcmc_por4; - uint pcmc_pbr5; - uint pcmc_por5; - uint pcmc_pbr6; - uint pcmc_por6; - uint pcmc_pbr7; - uint pcmc_por7; - char res1[0x20]; - uint pcmc_pgcra; - uint pcmc_pgcrb; - uint pcmc_pscr; - char res2[4]; - uint pcmc_pipr; - char res3[4]; - uint pcmc_per; - char res4[4]; -} pcmconf8xx_t; - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - uint memc_br4; - uint memc_or4; - uint memc_br5; - uint memc_or5; - uint memc_br6; - uint memc_or6; - uint memc_br7; - uint memc_or7; - char res1[0x24]; - uint memc_mar; - uint memc_mcr; - char res2[4]; - uint memc_mamr; - uint memc_mbmr; - ushort memc_mstat; - ushort memc_mptpr; - uint memc_mdr; - char res3[0x80]; -} memctl8xx_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - ushort sit_tbscr; - char res0[0x02]; - uint sit_tbreff0; - uint sit_tbreff1; - char res1[0x14]; - ushort sit_rtcsc; - char res2[0x02]; - uint sit_rtc; - uint sit_rtsec; - uint sit_rtcal; - char res3[0x10]; - ushort sit_piscr; - char res4[2]; - uint sit_pitc; - uint sit_pitr; - char res5[0x34]; -} sit8xx_t; - -#define TBSCR_TBIRQ_MASK ((ushort)0xff00) -#define TBSCR_REFA ((ushort)0x0080) -#define TBSCR_REFB ((ushort)0x0040) -#define TBSCR_REFAE ((ushort)0x0008) -#define TBSCR_REFBE ((ushort)0x0004) -#define TBSCR_TBF ((ushort)0x0002) -#define TBSCR_TBE ((ushort)0x0001) - -#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) -#define RTCSC_SEC ((ushort)0x0080) -#define RTCSC_ALR ((ushort)0x0040) -#define RTCSC_38K ((ushort)0x0010) -#define RTCSC_SIE ((ushort)0x0008) -#define RTCSC_ALE ((ushort)0x0004) -#define RTCSC_RTF ((ushort)0x0002) -#define RTCSC_RTE ((ushort)0x0001) - -#define PISCR_PIRQ_MASK ((ushort)0xff00) -#define PISCR_PS ((ushort)0x0080) -#define PISCR_PIE ((ushort)0x0004) -#define PISCR_PTF ((ushort)0x0002) -#define PISCR_PTE ((ushort)0x0001) - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - uint car_sccr; - uint car_plprcr; - uint car_rsr; - char res[0x74]; /* Reserved area */ -} car8xx_t; - -/* System Integration Timers keys. -*/ -typedef struct sitk { - uint sitk_tbscrk; - uint sitk_tbreff0k; - uint sitk_tbreff1k; - uint sitk_tbk; - char res1[0x10]; - uint sitk_rtcsck; - uint sitk_rtck; - uint sitk_rtseck; - uint sitk_rtcalk; - char res2[0x10]; - uint sitk_piscrk; - uint sitk_pitck; - char res3[0x38]; -} sitk8xx_t; - -/* Clocks and reset keys. -*/ -typedef struct cark { - uint cark_sccrk; - uint cark_plprcrk; - uint cark_rsrk; - char res[0x474]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* Video interface. MPC823 Only. -*/ -typedef struct vid823 { - ushort vid_vccr; - ushort res1; - u_char vid_vsr; - u_char res2; - u_char vid_vcmr; - u_char res3; - uint vid_vbcb; - uint res4; - uint vid_vfcr0; - uint vid_vfaa0; - uint vid_vfba0; - uint vid_vfcr1; - uint vid_vfaa1; - uint vid_vfba1; - u_char res5[0x18]; -} vid823_t; - -/* LCD interface. 823 Only. -*/ -typedef struct lcd { - uint lcd_lccr; - uint lcd_lchcr; - uint lcd_lcvcr; - char res1[4]; - uint lcd_lcfaa; - uint lcd_lcfba; - char lcd_lcsr; - char res2[0x7]; -} lcd823_t; - -/* I2C -*/ -typedef struct i2c { - u_char i2c_i2mod; - char res1[3]; - u_char i2c_i2add; - char res2[3]; - u_char i2c_i2brg; - char res3[3]; - u_char i2c_i2com; - char res4[3]; - u_char i2c_i2cer; - char res5[3]; - u_char i2c_i2cmr; - char res6[0x8b]; -} i2c8xx_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res1[4]; - uint sdma_sdar; - u_char sdma_sdsr; - char res3[3]; - u_char sdma_sdmr; - char res4[3]; - u_char sdma_idsr1; - char res5[3]; - u_char sdma_idmr1; - char res6[3]; - u_char sdma_idsr2; - char res7[3]; - u_char sdma_idmr2; - char res8[0x13]; -} sdma8xx_t; - -/* Communication Processor Module Interrupt Controller. -*/ -typedef struct cpm_ic { - ushort cpic_civr; - char res[0xe]; - uint cpic_cicr; - uint cpic_cipr; - uint cpic_cimr; - uint cpic_cisr; -} cpic8xx_t; - -/* Input/Output Port control/status registers. -*/ -typedef struct io_port { - ushort iop_padir; - ushort iop_papar; - ushort iop_paodr; - ushort iop_padat; - char res1[8]; - ushort iop_pcdir; - ushort iop_pcpar; - ushort iop_pcso; - ushort iop_pcdat; - ushort iop_pcint; - char res2[6]; - ushort iop_pddir; - ushort iop_pdpar; - char res3[2]; - ushort iop_pddat; - uint utmode; - char res4[4]; -} iop8xx_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - ushort cpmt_tgcr; - char res1[0xe]; - ushort cpmt_tmr1; - ushort cpmt_tmr2; - ushort cpmt_trr1; - ushort cpmt_trr2; - ushort cpmt_tcr1; - ushort cpmt_tcr2; - ushort cpmt_tcn1; - ushort cpmt_tcn2; - ushort cpmt_tmr3; - ushort cpmt_tmr4; - ushort cpmt_trr3; - ushort cpmt_trr4; - ushort cpmt_tcr3; - ushort cpmt_tcr4; - ushort cpmt_tcn3; - ushort cpmt_tcn4; - ushort cpmt_ter1; - ushort cpmt_ter2; - ushort cpmt_ter3; - ushort cpmt_ter4; - char res2[8]; -} cpmtimer8xx_t; - -/* Finally, the Communication Processor stuff..... -*/ -typedef struct scc { /* Serial communication channels */ - uint scc_gsmrl; - uint scc_gsmrh; - ushort scc_psmr; - char res1[2]; - ushort scc_todr; - ushort scc_dsr; - ushort scc_scce; - char res2[2]; - ushort scc_sccm; - char res3; - u_char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - ushort smc_smcmr; - char res2[2]; - u_char smc_smce; - char res3[3]; - u_char smc_smcm; - char res4[5]; -} smc_t; - -/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but - * it fits within the address space. - */ - -typedef struct fec { - uint fec_addr_low; /* lower 32 bits of station address */ - ushort fec_addr_high; /* upper 16 bits of station address */ - ushort res1; /* reserved */ - uint fec_hash_table_high; /* upper 32-bits of hash table */ - uint fec_hash_table_low; /* lower 32-bits of hash table */ - uint fec_r_des_start; /* beginning of Rx descriptor ring */ - uint fec_x_des_start; /* beginning of Tx descriptor ring */ - uint fec_r_buff_size; /* Rx buffer size */ - uint res2[9]; /* reserved */ - uint fec_ecntrl; /* ethernet control register */ - uint fec_ievent; /* interrupt event register */ - uint fec_imask; /* interrupt mask register */ - uint fec_ivec; /* interrupt level and vector status */ - uint fec_r_des_active; /* Rx ring updated flag */ - uint fec_x_des_active; /* Tx ring updated flag */ - uint res3[10]; /* reserved */ - uint fec_mii_data; /* MII data register */ - uint fec_mii_speed; /* MII speed control register */ - uint res4[17]; /* reserved */ - uint fec_r_bound; /* end of RAM (read-only) */ - uint fec_r_fstart; /* Rx FIFO start address */ - uint res5[6]; /* reserved */ - uint fec_x_fstart; /* Tx FIFO start address */ - uint res6[17]; /* reserved */ - uint fec_fun_code; /* fec SDMA function code */ - uint res7[3]; /* reserved */ - uint fec_r_cntrl; /* Rx control register */ - uint fec_r_hash; /* Rx hash register */ - uint res8[14]; /* reserved */ - uint fec_x_cntrl; /* Tx control register */ - uint res9[0x1e]; /* reserved */ -} fec_t; - -/* The FEC and LCD color map share the same address space.... - * I guess we will never see an 823T :-). - */ -union fec_lcd { - fec_t fl_un_fec; - u_char fl_un_cmap[0x200]; -}; - -typedef struct comm_proc { - /* General control and status registers. - */ - ushort cp_cpcr; - u_char res1[2]; - ushort cp_rccr; - u_char res2; - u_char cp_rmds; - u_char res3[4]; - ushort cp_cpmcr1; - ushort cp_cpmcr2; - ushort cp_cpmcr3; - ushort cp_cpmcr4; - u_char res4[2]; - ushort cp_rter; - u_char res5[2]; - ushort cp_rtmr; - u_char res6[0x14]; - - /* Baud rate generators. - */ - uint cp_brgc1; - uint cp_brgc2; - uint cp_brgc3; - uint cp_brgc4; - - /* Serial Communication Channels. - */ - scc_t cp_scc[4]; - - /* Serial Management Channels. - */ - smc_t cp_smc[2]; - - /* Serial Peripheral Interface. - */ - ushort cp_spmode; - u_char res7[4]; - u_char cp_spie; - u_char res8[3]; - u_char cp_spim; - u_char res9[2]; - u_char cp_spcom; - u_char res10[2]; - - /* Parallel Interface Port. - */ - u_char res11[2]; - ushort cp_pipc; - u_char res12[2]; - ushort cp_ptpr; - uint cp_pbdir; - uint cp_pbpar; - u_char res13[2]; - ushort cp_pbodr; - uint cp_pbdat; - - /* Port E - MPC87x/88x only. - */ - uint cp_pedir; - uint cp_pepar; - uint cp_peso; - uint cp_peodr; - uint cp_pedat; - - /* Communications Processor Timing Register - - Contains RMII Timing for the FECs on MPC87x/88x only. - */ - uint cp_cptr; - - /* Serial Interface and Time Slot Assignment. - */ - uint cp_simode; - u_char cp_sigmr; - u_char res15; - u_char cp_sistr; - u_char cp_sicmr; - u_char res16[4]; - uint cp_sicr; - uint cp_sirp; - u_char res17[0xc]; - - /* 256 bytes of MPC823 video controller RAM array. - */ - u_char cp_vcram[0x100]; - u_char cp_siram[0x200]; - - /* The fast ethernet controller is not really part of the CPM, - * but it resides in the address space. - * The LCD color map is also here. - */ - union fec_lcd fl_un; -#define cp_fec fl_un.fl_un_fec -#define lcd_cmap fl_un.fl_un_cmap - char res18[0xE00]; - - /* The MPC885 family has a second FEC here */ - fec_t cp_fec2; -#define cp_fec1 cp_fec /* consistency macro */ - - /* Dual Ported RAM follows. - * There are many different formats for this memory area - * depending upon the devices used and options chosen. - * Some processors don't have all of it populated. - */ - u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ - u_char cp_dparam[0x400]; /* Parameter RAM */ -} cpm8xx_t; - -/* Internal memory map. -*/ -typedef struct immap { - sysconf8xx_t im_siu_conf; /* SIU Configuration */ - pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ - memctl8xx_t im_memctl; /* Memory Controller */ - sit8xx_t im_sit; /* System integration timers */ - car8xx_t im_clkrst; /* Clocks and reset */ - sitk8xx_t im_sitk; /* Sys int timer keys */ - cark8xx_t im_clkrstk; /* Clocks and reset keys */ - vid823_t im_vid; /* Video (823 only) */ - lcd823_t im_lcd; /* LCD (823 only) */ - i2c8xx_t im_i2c; /* I2C control/status */ - sdma8xx_t im_sdma; /* SDMA control/status */ - cpic8xx_t im_cpic; /* CPM Interrupt Controller */ - iop8xx_t im_ioport; /* IO Port control/status */ - cpmtimer8xx_t im_cpmtimer; /* CPM timers */ - cpm8xx_t im_cpm; /* Communication processor */ -} immap_t; - -#endif /* __IMMAP_8XX__ */ diff --git a/include/asm-ppc/atomic.h b/include/asm-ppc/atomic.h deleted file mode 100644 index 23f22df..0000000 --- a/include/asm-ppc/atomic.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * PowerPC atomic operations - */ - -#ifndef _ASM_PPC_ATOMIC_H_ -#define _ASM_PPC_ATOMIC_H_ - -#include - -#ifdef CONFIG_SMP -typedef struct { volatile int counter; } atomic_t; -#else -typedef struct { int counter; } atomic_t; -#endif - -#define ATOMIC_INIT(i) { (i) } - -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) - -extern void atomic_clear_mask(unsigned long mask, unsigned long *addr); -extern void atomic_set_mask(unsigned long mask, unsigned long *addr); - -extern __inline__ int atomic_add_return(int a, atomic_t *v) -{ - int t; - - __asm__ __volatile__("\n\ -1: lwarx %0,0,%3\n\ - add %0,%2,%0\n\ - stwcx. %0,0,%3\n\ - bne- 1b" - : "=&r" (t), "=m" (*v) - : "r" (a), "r" (v), "m" (*v) - : "cc"); - - return t; -} - -extern __inline__ int atomic_sub_return(int a, atomic_t *v) -{ - int t; - - __asm__ __volatile__("\n\ -1: lwarx %0,0,%3\n\ - subf %0,%2,%0\n\ - stwcx. %0,0,%3\n\ - bne- 1b" - : "=&r" (t), "=m" (*v) - : "r" (a), "r" (v), "m" (*v) - : "cc"); - - return t; -} - -extern __inline__ int atomic_inc_return(atomic_t *v) -{ - int t; - - __asm__ __volatile__("\n\ -1: lwarx %0,0,%2\n\ - addic %0,%0,1\n\ - stwcx. %0,0,%2\n\ - bne- 1b" - : "=&r" (t), "=m" (*v) - : "r" (v), "m" (*v) - : "cc"); - - return t; -} - -extern __inline__ int atomic_dec_return(atomic_t *v) -{ - int t; - - __asm__ __volatile__("\n\ -1: lwarx %0,0,%2\n\ - addic %0,%0,-1\n\ - stwcx. %0,0,%2\n\ - bne 1b" - : "=&r" (t), "=m" (*v) - : "r" (v), "m" (*v) - : "cc"); - - return t; -} - -#define atomic_add(a, v) ((void) atomic_add_return((a), (v))) -#define atomic_sub(a, v) ((void) atomic_sub_return((a), (v))) -#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0) -#define atomic_inc(v) ((void) atomic_inc_return((v))) -#define atomic_dec(v) ((void) atomic_dec_return((v))) -#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0) - -#endif /* _ASM_PPC_ATOMIC_H_ */ diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h deleted file mode 100644 index adaf091..0000000 --- a/include/asm-ppc/bitops.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - * bitops.h: Bit string operations on the ppc - */ - -#ifndef _PPC_BITOPS_H -#define _PPC_BITOPS_H - -#include -#include - -extern void set_bit(int nr, volatile void *addr); -extern void clear_bit(int nr, volatile void *addr); -extern void change_bit(int nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void *addr); -extern int test_and_clear_bit(int nr, volatile void *addr); -extern int test_and_change_bit(int nr, volatile void *addr); - -/* - * Arguably these bit operations don't imply any memory barrier or - * SMP ordering, but in fact a lot of drivers expect them to imply - * both, since they do on x86 cpus. - */ -#ifdef CONFIG_SMP -#define SMP_WMB "eieio\n" -#define SMP_MB "\nsync" -#else -#define SMP_WMB -#define SMP_MB -#endif /* CONFIG_SMP */ - -#define __INLINE_BITOPS 1 - -#if __INLINE_BITOPS -/* - * These used to be if'd out here because using : "cc" as a constraint - * resulted in errors from egcs. Things may be OK with gcc-2.95. - */ -extern __inline__ void set_bit(int nr, volatile void * addr) -{ - unsigned long old; - unsigned long mask = 1 << (nr & 0x1f); - unsigned long *p = ((unsigned long *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%3\n\ - or %0,%0,%2\n\ - stwcx. %0,0,%3\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc" ); -} - -extern __inline__ void clear_bit(int nr, volatile void *addr) -{ - unsigned long old; - unsigned long mask = 1 << (nr & 0x1f); - unsigned long *p = ((unsigned long *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%3\n\ - andc %0,%0,%2\n\ - stwcx. %0,0,%3\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc"); -} - -extern __inline__ void change_bit(int nr, volatile void *addr) -{ - unsigned long old; - unsigned long mask = 1 << (nr & 0x1f); - unsigned long *p = ((unsigned long *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%3\n\ - xor %0,%0,%2\n\ - stwcx. %0,0,%3\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc"); -} - -extern __inline__ int test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int old, t; - unsigned int mask = 1 << (nr & 0x1f); - volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%4\n\ - or %1,%0,%3\n\ - stwcx. %1,0,%4\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=&r" (t), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc"); - - return (old & mask) != 0; -} - -extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int old, t; - unsigned int mask = 1 << (nr & 0x1f); - volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%4\n\ - andc %1,%0,%3\n\ - stwcx. %1,0,%4\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=&r" (t), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc"); - - return (old & mask) != 0; -} - -extern __inline__ int test_and_change_bit(int nr, volatile void *addr) -{ - unsigned int old, t; - unsigned int mask = 1 << (nr & 0x1f); - volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); - - __asm__ __volatile__(SMP_WMB "\ -1: lwarx %0,0,%4\n\ - xor %1,%0,%3\n\ - stwcx. %1,0,%4\n\ - bne 1b" - SMP_MB - : "=&r" (old), "=&r" (t), "=m" (*p) - : "r" (mask), "r" (p), "m" (*p) - : "cc"); - - return (old & mask) != 0; -} -#endif /* __INLINE_BITOPS */ - -extern __inline__ int test_bit(int nr, __const__ volatile void *addr) -{ - __const__ unsigned int *p = (__const__ unsigned int *) addr; - - return ((p[nr >> 5] >> (nr & 0x1f)) & 1) != 0; -} - -/* Return the bit position of the most significant 1 bit in a word */ -/* - the result is undefined when x == 0 */ -extern __inline__ int __ilog2(unsigned int x) -{ - int lz; - - asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x)); - return 31 - lz; -} - -extern __inline__ int ffz(unsigned int x) -{ - if ((x = ~x) == 0) - return 32; - return __ilog2(x & -x); -} - -/* - * fls: find last (most-significant) bit set. - * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. - * - * On powerpc, __ilog2(0) returns -1, but this is not safe in general - */ -static __inline__ int fls(unsigned int x) -{ - return __ilog2(x) + 1; -} -#define PLATFORM_FLS - -/** - * fls64 - find last set bit in a 64-bit word - * @x: the word to search - * - * This is defined in a similar way as the libc and compiler builtin - * ffsll, but returns the position of the most significant set bit. - * - * fls64(value) returns 0 if value is 0 or the position of the last - * set bit if value is nonzero. The last (most significant) bit is - * at position 64. - */ -#if BITS_PER_LONG == 32 -static inline int fls64(__u64 x) -{ - __u32 h = x >> 32; - if (h) - return fls(h) + 32; - return fls(x); -} -#elif BITS_PER_LONG == 64 -static inline int fls64(__u64 x) -{ - if (x == 0) - return 0; - return __ilog2(x) + 1; -} -#else -#error BITS_PER_LONG not 32 or 64 -#endif - -static inline int __ilog2_u64(u64 n) -{ - return fls64(n) - 1; -} - -static inline int ffs64(u64 x) -{ - return __ilog2_u64(x & -x) + 1ull; -} - -#ifdef __KERNEL__ - -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -extern __inline__ int ffs(int x) -{ - return __ilog2(x & -x) + 1; -} -#define PLATFORM_FFS - -/* - * hweightN: returns the hamming weight (i.e. the number - * of bits set) of a N-bit word - */ - -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) - -#endif /* __KERNEL__ */ - -/* - * This implementation of find_{first,next}_zero_bit was stolen from - * Linus' asm-alpha/bitops.h. - */ -#define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) - -extern __inline__ unsigned long find_next_zero_bit(void * addr, - unsigned long size, unsigned long offset) -{ - unsigned int * p = ((unsigned int *) addr) + (offset >> 5); - unsigned int result = offset & ~31UL; - unsigned int tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = *p++; - tmp |= ~0UL >> (32-offset); - if (size < 32) - goto found_first; - if (tmp != ~0U) - goto found_middle; - size -= 32; - result += 32; - } - while (size >= 32) { - if ((tmp = *p++) != ~0U) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = *p; -found_first: - tmp |= ~0UL << size; -found_middle: - return result + ffz(tmp); -} - - -#define _EXT2_HAVE_ASM_BITOPS_ - -#ifdef __KERNEL__ -/* - * test_and_{set,clear}_bit guarantee atomicity without - * disabling interrupts. - */ -#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 0x18, addr) -#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 0x18, addr) - -#else -extern __inline__ int ext2_set_bit(int nr, void * addr) -{ - int mask; - unsigned char *ADDR = (unsigned char *) addr; - int oldbit; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - oldbit = (*ADDR & mask) ? 1 : 0; - *ADDR |= mask; - return oldbit; -} - -extern __inline__ int ext2_clear_bit(int nr, void * addr) -{ - int mask; - unsigned char *ADDR = (unsigned char *) addr; - int oldbit; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - oldbit = (*ADDR & mask) ? 1 : 0; - *ADDR = *ADDR & ~mask; - return oldbit; -} -#endif /* __KERNEL__ */ - -extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) -{ - __const__ unsigned char *ADDR = (__const__ unsigned char *) addr; - - return (ADDR[nr >> 3] >> (nr & 7)) & 1; -} - -/* - * This implementation of ext2_find_{first,next}_zero_bit was stolen from - * Linus' asm-alpha/bitops.h and modified for a big-endian machine. - */ - -#define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) - -static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, - unsigned long size, unsigned long offset) -{ - unsigned int *p = ((unsigned int *) addr) + (offset >> 5); - unsigned int result = offset & ~31UL; - unsigned int tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if (offset) { - tmp = cpu_to_le32p(p++); - tmp |= ~0UL >> (32-offset); - if (size < 32) - goto found_first; - if (tmp != ~0U) - goto found_middle; - size -= 32; - result += 32; - } - while (size >= 32) { - if ((tmp = cpu_to_le32p(p++)) != ~0U) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - tmp = cpu_to_le32p(p); -found_first: - tmp |= ~0U << size; -found_middle: - return result + ffz(tmp); -} - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr) -#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr)) -#define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) ext2_test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size) - -#endif /* _PPC_BITOPS_H */ diff --git a/include/asm-ppc/byteorder.h b/include/asm-ppc/byteorder.h deleted file mode 100644 index 3f5bcf6..0000000 --- a/include/asm-ppc/byteorder.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef _PPC_BYTEORDER_H -#define _PPC_BYTEORDER_H - -#include - -#ifdef __GNUC__ - -extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) -{ - unsigned val; - - __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); - return val; -} - -extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) -{ - __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); -} - -extern __inline__ unsigned ld_le32(const volatile unsigned *addr) -{ - unsigned val; - - __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); - return val; -} - -extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) -{ - __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); -} - -/* alas, egcs sounds like it has a bug in this code that doesn't use the - inline asm correctly, and can cause file corruption. Until I hear that - it's fixed, I can live without the extra speed. I hope. */ -#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90) -#if 0 -# define __arch_swab16(x) ld_le16(&x) -# define __arch_swab32(x) ld_le32(&x) -#else -static __inline__ __attribute__((const)) __u16 ___arch__swab16(__u16 value) -{ - __u16 result; - - __asm__("rlwimi %0,%1,8,16,23" - : "=r" (result) - : "r" (value), "0" (value >> 8)); - return result; -} - -static __inline__ __attribute__((const)) __u32 ___arch__swab32(__u32 value) -{ - __u32 result; - - __asm__("rlwimi %0,%1,24,16,23\n\t" - "rlwimi %0,%1,8,8,15\n\t" - "rlwimi %0,%1,24,0,7" - : "=r" (result) - : "r" (value), "0" (value >> 24)); - return result; -} -#define __arch__swab32(x) ___arch__swab32(x) -#define __arch__swab16(x) ___arch__swab16(x) -#endif /* 0 */ - -#endif - -/* The same, but returns converted value from the location pointer by addr. */ -#define __arch__swab16p(addr) ld_le16(addr) -#define __arch__swab32p(addr) ld_le32(addr) - -/* The same, but do the conversion in situ, ie. put the value back to addr. */ -#define __arch__swab16s(addr) st_le16(addr,*addr) -#define __arch__swab32s(addr) st_le32(addr,*addr) - -#endif /* __GNUC__ */ - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -#define __BYTEORDER_HAS_U64__ -#endif -#include - -#endif /* _PPC_BYTEORDER_H */ diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h deleted file mode 100644 index 53e8d05..0000000 --- a/include/asm-ppc/cache.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * include/asm-ppc/cache.h - */ -#ifndef __ARCH_PPC_CACHE_H -#define __ARCH_PPC_CACHE_H - -#include -#include - -/* bytes per L1 cache line */ -#if defined(CONFIG_8xx) || defined(CONFIG_IOP480) -#define L1_CACHE_SHIFT 4 -#elif defined(CONFIG_PPC64BRIDGE) -#define L1_CACHE_SHIFT 7 -#elif defined(CONFIG_E500MC) -#define L1_CACHE_SHIFT 6 -#else -#define L1_CACHE_SHIFT 5 -#endif - -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -/* - * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too - */ -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES -#endif - -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) -#define L1_CACHE_PAGES 8 - -#define SMP_CACHE_BYTES L1_CACHE_BYTES - -#ifdef MODULE -#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) -#else -#define __cacheline_aligned \ - __attribute__((__aligned__(L1_CACHE_BYTES), \ - __section__(".data.cacheline_aligned"))) -#endif - -#if defined(__KERNEL__) && !defined(__ASSEMBLY__) -extern void flush_dcache_range(unsigned long start, unsigned long stop); -extern void clean_dcache_range(unsigned long start, unsigned long stop); -extern void invalidate_dcache_range(unsigned long start, unsigned long stop); -extern void flush_dcache(void); -extern void invalidate_dcache(void); -extern void invalidate_icache(void); -#ifdef CONFIG_SYS_INIT_RAM_LOCK -extern void unlock_ram_in_cache(void); -#endif /* CONFIG_SYS_INIT_RAM_LOCK */ -#endif /* __ASSEMBLY__ */ - -/* prep registers for L2 */ -#define CACHECRBA 0x80000823 /* Cache configuration register address */ -#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ -#define L2CACHE_512KB 0x00 /* 512KB */ -#define L2CACHE_256KB 0x01 /* 256KB */ -#define L2CACHE_1MB 0x02 /* 1MB */ -#define L2CACHE_NONE 0x03 /* NONE */ -#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ - -#ifdef CONFIG_8xx -/* Cache control on the MPC8xx is provided through some additional - * special purpose registers. - */ -#define IC_CST 560 /* Instruction cache control/status */ -#define IC_ADR 561 /* Address needed for some commands */ -#define IC_DAT 562 /* Read-only data register */ -#define DC_CST 568 /* Data cache control/status */ -#define DC_ADR 569 /* Address needed for some commands */ -#define DC_DAT 570 /* Read-only data register */ - -/* Commands. Only the first few are available to the instruction cache. -*/ -#define IDC_ENABLE 0x02000000 /* Cache enable */ -#define IDC_DISABLE 0x04000000 /* Cache disable */ -#define IDC_LDLCK 0x06000000 /* Load and lock */ -#define IDC_UNLINE 0x08000000 /* Unlock line */ -#define IDC_UNALL 0x0a000000 /* Unlock all */ -#define IDC_INVALL 0x0c000000 /* Invalidate all */ - -#define DC_FLINE 0x0e000000 /* Flush data cache line */ -#define DC_SFWT 0x01000000 /* Set forced writethrough mode */ -#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ -#define DC_SLES 0x05000000 /* Set little endian swap mode */ -#define DC_CLES 0x07000000 /* Clear little endian swap mode */ - -/* Status. -*/ -#define IDC_ENABLED 0x80000000 /* Cache is enabled */ -#define IDC_CERR1 0x00200000 /* Cache error 1 */ -#define IDC_CERR2 0x00100000 /* Cache error 2 */ -#define IDC_CERR3 0x00080000 /* Cache error 3 */ - -#define DC_DFWT 0x40000000 /* Data cache is forced write through */ -#define DC_LES 0x20000000 /* Caches are little endian mode */ -#endif /* CONFIG_8xx */ - -#endif diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h deleted file mode 100644 index fc3facb..0000000 --- a/include/asm-ppc/config.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -#define CONFIG_LMB - -#ifndef CONFIG_MAX_MEM_MAPPED -#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) -#else -#define CONFIG_MAX_MEM_MAPPED (256 << 20) -#endif -#endif - -/* Check if boards need to enable FSL DMA engine for SDRAM init */ -#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) -#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ - ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ - !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) -#define CONFIG_FSL_DMA -#endif -#endif - -#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ - defined(CONFIG_P2020) || defined(CONFIG_MPC8641) -#define CONFIG_MAX_CPUS 2 -#elif defined(CONFIG_PPC_P4080) -#define CONFIG_MAX_CPUS 8 -#else -#define CONFIG_MAX_CPUS 1 -#endif - -/* - * Provide a default boot page translation virtual address that lines up with - * Freescale's default e500 reset page. - */ -#if (defined(CONFIG_E500) && defined(CONFIG_MP)) -#ifndef CONFIG_BPTR_VIRT_ADDR -#define CONFIG_BPTR_VIRT_ADDR 0xfffff000 -#endif -#endif - -/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ -#if defined(CONFIG_TSEC_ENET) && \ - (defined(CONFIG_P1020) || defined(CONFIG_P1011)) -#define CONFIG_TSECV2 -#endif - -/* Number of TLB CAM entries we have on FSL Book-E chips */ -#if defined(CONFIG_E500MC) -#define CONFIG_SYS_NUM_TLBCAMS 64 -#elif defined(CONFIG_E500) -#define CONFIG_SYS_NUM_TLBCAMS 16 -#endif - -/* Relocation to SDRAM works on all PPC boards */ -#define CONFIG_RELOC_FIXUP_WORKS - -#endif /* _ASM_CONFIG_H_ */ diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h deleted file mode 100644 index 8302404..0000000 --- a/include/asm-ppc/cpm_8260.h +++ /dev/null @@ -1,796 +0,0 @@ - -/* - * MPC8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * - * This file contains structures and information for the communication - * processor channels found in the dual port RAM or parameter RAM. - * All CPM control and status is available through the MPC8260 internal - * memory map. See immap.h for details. - */ -#ifndef __CPM_82XX__ -#define __CPM_82XX__ - -#include - -/* CPM Command register. -*/ -#define CPM_CR_RST ((uint)0x80000000) -#define CPM_CR_PAGE ((uint)0x7c000000) -#define CPM_CR_SBLOCK ((uint)0x03e00000) -#define CPM_CR_FLG ((uint)0x00010000) -#define CPM_CR_MCN ((uint)0x00003fc0) -#define CPM_CR_OPCODE ((uint)0x0000000f) - -/* Device sub-block and page codes. -*/ -#define CPM_CR_SCC1_SBLOCK (0x04) -#define CPM_CR_SCC2_SBLOCK (0x05) -#define CPM_CR_SCC3_SBLOCK (0x06) -#define CPM_CR_SCC4_SBLOCK (0x07) -#define CPM_CR_SMC1_SBLOCK (0x08) -#define CPM_CR_SMC2_SBLOCK (0x09) -#define CPM_CR_SPI_SBLOCK (0x0a) -#define CPM_CR_I2C_SBLOCK (0x0b) -#define CPM_CR_TIMER_SBLOCK (0x0f) -#define CPM_CR_RAND_SBLOCK (0x0e) -#define CPM_CR_FCC1_SBLOCK (0x10) -#define CPM_CR_FCC2_SBLOCK (0x11) -#define CPM_CR_FCC3_SBLOCK (0x12) -#define CPM_CR_IDMA1_SBLOCK (0x14) -#define CPM_CR_IDMA2_SBLOCK (0x15) -#define CPM_CR_IDMA3_SBLOCK (0x16) -#define CPM_CR_IDMA4_SBLOCK (0x17) -#define CPM_CR_MCC1_SBLOCK (0x1c) - -#define CPM_CR_SCC1_PAGE (0x00) -#define CPM_CR_SCC2_PAGE (0x01) -#define CPM_CR_SCC3_PAGE (0x02) -#define CPM_CR_SCC4_PAGE (0x03) -#define CPM_CR_SMC1_PAGE (0x07) -#define CPM_CR_SMC2_PAGE (0x08) -#define CPM_CR_SPI_PAGE (0x09) -#define CPM_CR_I2C_PAGE (0x0a) -#define CPM_CR_TIMER_PAGE (0x0a) -#define CPM_CR_RAND_PAGE (0x0a) -#define CPM_CR_FCC1_PAGE (0x04) -#define CPM_CR_FCC2_PAGE (0x05) -#define CPM_CR_FCC3_PAGE (0x06) -#define CPM_CR_IDMA1_PAGE (0x07) -#define CPM_CR_IDMA2_PAGE (0x08) -#define CPM_CR_IDMA3_PAGE (0x09) -#define CPM_CR_IDMA4_PAGE (0x0a) -#define CPM_CR_MCC1_PAGE (0x07) -#define CPM_CR_MCC2_PAGE (0x08) - -/* Some opcodes (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_SET_GADDR ((ushort)0x0008) - -#define mk_cr_cmd(PG, SBC, MCN, OP) \ - ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) - -/* Dual Port RAM addresses. The first 16K is available for almost - * any CPM use, so we put the BDs there. The first 128 bytes are - * used for SMC1 and SMC2 parameter RAM, so we start allocating - * BDs above that. All of this must change when we start - * downloading RAM microcode. - */ -#define CPM_DATAONLY_BASE ((uint)128) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) -#ifndef CONFIG_MPC8272_FAMILY -#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) -#else /* 8247/48/71/72 */ -#define CPM_DATAONLY_SIZE ((uint)(4 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) -#endif /* !CONFIG_MPC8272_FAMILY */ - -/* The number of pages of host memory we allocate for CPM. This is - * done early in kernel initialization to get physically contiguous - * pages. - */ -#define NUM_CPM_HOST_PAGES 2 - - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -extern cpm8260_t *cpmp; /* Pointer to comm processor */ -uint m8260_cpm_dpalloc(uint size, uint align); -uint m8260_cpm_hostalloc(uint size, uint align); -void m8260_cpm_setbrg(uint brg, uint rate); -void m8260_cpm_fastbrg(uint brg, uint rate, int div16); -void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ - -/* Function code bits, usually generic to devices. -*/ -#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ -#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ -#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ -#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ -#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ - -/* Parameter RAM offsets from the base. -*/ -#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR -#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ -#else -#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR -#endif - -#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) -#else -#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#endif - -#define PROFF_SCC1 ((uint)0x8000) -#define PROFF_SCC2 ((uint)0x8100) -#define PROFF_SCC3 ((uint)0x8200) -#define PROFF_SCC4 ((uint)0x8300) -#define PROFF_FCC1 ((uint)0x8400) -#define PROFF_FCC2 ((uint)0x8500) -#define PROFF_FCC3 ((uint)0x8600) -#define PROFF_MCC1 ((uint)0x8700) -#define PROFF_SMC1_BASE ((uint)0x87fc) -#define PROFF_IDMA1_BASE ((uint)0x87fe) -#define PROFF_MCC2 ((uint)0x8800) -#define PROFF_SMC2_BASE ((uint)0x88fc) -#define PROFF_IDMA2_BASE ((uint)0x88fe) -#define PROFF_SPI_BASE ((uint)0x89fc) -#define PROFF_IDMA3_BASE ((uint)0x89fe) -#define PROFF_TIMERS ((uint)0x8ae0) -#define PROFF_REVNUM ((uint)0x8af0) -#define PROFF_RAND ((uint)0x8af8) -#define PROFF_I2C_BASE ((uint)0x8afc) -#define PROFF_IDMA4_BASE ((uint)0x8afe) - -/* The SMCs are relocated to any of the first eight DPRAM pages. - * We will fix these at the first locations of DPRAM, until we - * get some microcode patches :-). - * The parameter ram space for the SMCs is fifty-some bytes, and - * they are required to start on a 64 byte boundary. - */ -#define PROFF_SMC1 (0) -#define PROFF_SMC2 (64) -#define PROFF_SPI ((16*1024) - 128) - -/* Define enough so I can at least use the serial port as a UART. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ - uint smc_stmp; /* SDMA Temp */ -} smc_uart_t; - -/* SMC uart mode register (Internal memory map). -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC Event and Mask register. -*/ -#define SMCM_TXE ((unsigned char)0x10) -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* CPM Ethernet through SCC1. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PSMR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. - * Common to SCC and FCC. - */ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. - * Common to SCC and FCC. - */ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PSMR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0003) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* SCC as HDLC controller - taken from commproc.h - */ -typedef struct scc_hdlc { - sccp_t sh_genscc; - /* - * HDLC specific parameter RAM - */ - uchar res[4]; /* reserved */ - ulong sh_cmask; /* CRC constant */ - ulong sh_cpres; /* CRC preset */ - ushort sh_disfc; /* discarded frame counter */ - ushort sh_crcec; /* CRC error counter */ - ushort sh_abtsc; /* abort sequence counter */ - ushort sh_nmarc; /* nonmatching address rx cnt */ - ushort sh_retrc; /* frame retransmission cnt */ - ushort sh_mflr; /* maximum frame length reg */ - ushort sh_maxcnt; /* maximum length counter */ - ushort sh_rfthr; /* received frames threshold */ - ushort sh_rfcnt; /* received frames count */ - ushort sh_hmask; /* user defined frm addr mask */ - ushort sh_haddr1; /* user defined frm address 1 */ - ushort sh_haddr2; /* user defined frm address 2 */ - ushort sh_haddr3; /* user defined frm address 3 */ - ushort sh_haddr4; /* user defined frm address 4 */ - ushort tmp; /* temp */ - ushort tmp_mb; /* temp */ -} scc_hdlc_t; - -/* How about some FCCs..... -*/ -#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) -#define FCC_GFMR_DIAG_LE ((uint)0x40000000) -#define FCC_GFMR_DIAG_AE ((uint)0x80000000) -#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) -#define FCC_GFMR_TCI ((uint)0x20000000) -#define FCC_GFMR_TRX ((uint)0x10000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_CDP ((uint)0x04000000) -#define FCC_GFMR_CTSP ((uint)0x02000000) -#define FCC_GFMR_CDS ((uint)0x01000000) -#define FCC_GFMR_CTSS ((uint)0x00800000) -#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) -#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) -#define FCC_GFMR_SYNL_8 ((uint)0x00008000) -#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) -#define FCC_GFMR_RTSM ((uint)0x00002000) -#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) -#define FCC_GFMR_REVD ((uint)0x00000400) -#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) -#define FCC_GFMR_TCRC_16 ((uint)0x00000000) -#define FCC_GFMR_TCRC_32 ((uint)0x00000080) -#define FCC_GFMR_ENR ((uint)0x00000020) -#define FCC_GFMR_ENT ((uint)0x00000010) -#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) -#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) -#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) - -/* Generic FCC parameter ram. -*/ -typedef struct fcc_param { - ushort fcc_riptr; /* Rx Internal temp pointer */ - ushort fcc_tiptr; /* Tx Internal temp pointer */ - ushort fcc_res1; - ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ - uint fcc_rstate; /* Upper byte is Func code, must be set */ - uint fcc_rbase; /* Receive BD base */ - ushort fcc_rbdstat; /* RxBD status */ - ushort fcc_rbdlen; /* RxBD down counter */ - uint fcc_rdptr; /* RxBD internal data pointer */ - uint fcc_tstate; /* Upper byte is Func code, must be set */ - uint fcc_tbase; /* Transmit BD base */ - ushort fcc_tbdstat; /* TxBD status */ - ushort fcc_tbdlen; /* TxBD down counter */ - uint fcc_tdptr; /* TxBD internal data pointer */ - uint fcc_rbptr; /* Rx BD Internal buf pointer */ - uint fcc_tbptr; /* Tx BD Internal buf pointer */ - uint fcc_rcrc; /* Rx temp CRC */ - uint fcc_res2; - uint fcc_tcrc; /* Tx temp CRC */ -} fccp_t; - - -/* Ethernet controller through FCC. -*/ -typedef struct fcc_enet { - fccp_t fen_genfcc; - uint fen_statbuf; /* Internal status buffer */ - uint fen_camptr; /* CAM address */ - uint fen_cmask; /* Constant mask for CRC */ - uint fen_cpres; /* Preset CRC */ - uint fen_crcec; /* CRC Error counter */ - uint fen_alec; /* alignment error counter */ - uint fen_disfc; /* discard frame counter */ - ushort fen_retlim; /* Retry limit */ - ushort fen_retcnt; /* Retry counter */ - ushort fen_pper; /* Persistence */ - ushort fen_boffcnt; /* backoff counter */ - uint fen_gaddrh; /* Group address filter, high 32-bits */ - uint fen_gaddrl; /* Group address filter, low 32-bits */ - ushort fen_tfcstat; /* out of sequence TxBD */ - ushort fen_tfclen; - uint fen_tfcptr; - ushort fen_mflr; /* Maximum frame length (1518) */ - ushort fen_paddrh; /* MAC address */ - ushort fen_paddrm; - ushort fen_paddrl; - ushort fen_ibdcount; /* Internal BD counter */ - ushort fen_idbstart; /* Internal BD start pointer */ - ushort fen_ibdend; /* Internal BD end pointer */ - ushort fen_txlen; /* Internal Tx frame length counter */ - uint fen_ibdbase[8]; /* Internal use */ - uint fen_iaddrh; /* Individual address filter */ - uint fen_iaddrl; - ushort fen_minflr; /* Minimum frame length (64) */ - ushort fen_taddrh; /* Filter transfer MAC address */ - ushort fen_taddrm; - ushort fen_taddrl; - ushort fen_padptr; /* Pointer to pad byte buffer */ - ushort fen_cftype; /* control frame type */ - ushort fen_cfrange; /* control frame range */ - ushort fen_maxb; /* maximum BD count */ - ushort fen_maxd1; /* Max DMA1 length (1520) */ - ushort fen_maxd2; /* Max DMA2 length (1520) */ - ushort fen_maxd; /* internal max DMA count */ - ushort fen_dmacnt; /* internal DMA counter */ - uint fen_octc; /* Total octect counter */ - uint fen_colc; /* Total collision counter */ - uint fen_broc; /* Total broadcast packet counter */ - uint fen_mulc; /* Total multicast packet count */ - uint fen_uspc; /* Total packets < 64 bytes */ - uint fen_frgc; /* Total packets < 64 bytes with errors */ - uint fen_ospc; /* Total packets > 1518 */ - uint fen_jbrc; /* Total packets > 1518 with errors */ - uint fen_p64c; /* Total packets == 64 bytes */ - uint fen_p65c; /* Total packets 64 < bytes <= 127 */ - uint fen_p128c; /* Total packets 127 < bytes <= 255 */ - uint fen_p256c; /* Total packets 256 < bytes <= 511 */ - uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ - uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ - uint fen_cambuf; /* Internal CAM buffer poiner */ - ushort fen_rfthr; /* Received frames threshold */ - ushort fen_rfcnt; /* Received frames count */ -} fcc_enet_t; - -/* FCC Event/Mask register as used by Ethernet. -*/ -#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ -#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ -#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ -#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* FCC Mode Register (FPSMR) as used by Ethernet. -*/ -#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ -#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ -#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ -#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ -#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ -#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ -#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ -#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ -#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ -#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ -#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ -#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ -#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ -#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ -} iic_t; - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; /* Tx temp. */ - uint spi_res1[4]; /* SDMA temp. */ -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) -#define SPMODE_PM(x) ((x) &0xF) - -/* SPI Event/Mask register. -*/ -#define SPI_EMASK 0x37 /* Event Mask */ -#define SPI_MME 0x20 /* Multi-Master Error */ -#define SPI_TXE 0x10 /* Transmit Error */ -#define SPI_BSY 0x04 /* Busy */ -#define SPI_TXB 0x02 /* Tx Buffer Empty */ -#define SPI_RXB 0x01 /* RX Buffer full/closed */ - -#define SPI_STR 0x80 /* SPCOM: Start transmit */ - -#define SPI_EB ((u_char)0x10) /* big endian byte order */ - -#define BD_IIC_START ((ushort)0x0400) - -#endif /* __CPM_82XX__ */ diff --git a/include/asm-ppc/cpm_85xx.h b/include/asm-ppc/cpm_85xx.h deleted file mode 100644 index a74a3a1..0000000 --- a/include/asm-ppc/cpm_85xx.h +++ /dev/null @@ -1,830 +0,0 @@ - -/* - * MPC85xx Communication Processor Module - * Copyright (c) 2003,Motorola Inc. - * Xianghua Xiao (X.Xiao@motorola.com) - * - * MPC8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * - * This file contains structures and information for the communication - * processor channels found in the dual port RAM or parameter RAM. - * All CPM control and status is available through the MPC8260 internal - * memory map. See immap.h for details. - */ -#ifndef __CPM_85XX__ -#define __CPM_85XX__ - -#include - -/* CPM Command register. -*/ -#define CPM_CR_RST ((uint)0x80000000) -#define CPM_CR_PAGE ((uint)0x7c000000) -#define CPM_CR_SBLOCK ((uint)0x03e00000) -#define CPM_CR_FLG ((uint)0x00010000) -#define CPM_CR_MCN ((uint)0x00003fc0) -#define CPM_CR_OPCODE ((uint)0x0000000f) - -/* Device sub-block and page codes. -*/ -#define CPM_CR_SCC1_SBLOCK (0x04) -#define CPM_CR_SCC2_SBLOCK (0x05) -#define CPM_CR_SCC3_SBLOCK (0x06) -#define CPM_CR_SCC4_SBLOCK (0x07) -#define CPM_CR_SMC1_SBLOCK (0x08) -#define CPM_CR_SMC2_SBLOCK (0x09) -#define CPM_CR_SPI_SBLOCK (0x0a) -#define CPM_CR_I2C_SBLOCK (0x0b) -#define CPM_CR_TIMER_SBLOCK (0x0f) -#define CPM_CR_RAND_SBLOCK (0x0e) -#define CPM_CR_FCC1_SBLOCK (0x10) -#define CPM_CR_FCC2_SBLOCK (0x11) -#define CPM_CR_FCC3_SBLOCK (0x12) -#define CPM_CR_MCC1_SBLOCK (0x1c) - -#define CPM_CR_SCC1_PAGE (0x00) -#define CPM_CR_SCC2_PAGE (0x01) -#define CPM_CR_SCC3_PAGE (0x02) -#define CPM_CR_SCC4_PAGE (0x03) -#define CPM_CR_SPI_PAGE (0x09) -#define CPM_CR_I2C_PAGE (0x0a) -#define CPM_CR_TIMER_PAGE (0x0a) -#define CPM_CR_RAND_PAGE (0x0a) -#define CPM_CR_FCC1_PAGE (0x04) -#define CPM_CR_FCC2_PAGE (0x05) -#define CPM_CR_FCC3_PAGE (0x06) -#define CPM_CR_MCC1_PAGE (0x07) -#define CPM_CR_MCC2_PAGE (0x08) - -/* Some opcodes (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_SET_GADDR ((ushort)0x0008) - -#define mk_cr_cmd(PG, SBC, MCN, OP) \ - ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) - -/* Dual Port RAM addresses. The first 16K is available for almost - * any CPM use, so we put the BDs there. The first 128 bytes are - * used for SMC1 and SMC2 parameter RAM, so we start allocating - * BDs above that. All of this must change when we start - * downloading RAM microcode. - */ -#define CPM_DATAONLY_BASE ((uint)128) -#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF) -#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) -#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) -#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) -#else /* MPC8540, MPC8560 */ -#define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000) -#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) -#endif - -/* The number of pages of host memory we allocate for CPM. This is - * done early in kernel initialization to get physically contiguous - * pages. - */ -#define NUM_CPM_HOST_PAGES 2 - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -/*extern cpm8560_t *cpmp; Pointer to comm processor */ -uint m8560_cpm_dpalloc(uint size, uint align); -uint m8560_cpm_hostalloc(uint size, uint align); -void m8560_cpm_setbrg(uint brg, uint rate); -void m8560_cpm_fastbrg(uint brg, uint rate, int div16); -void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ - -/* Function code bits, usually generic to devices. -*/ -#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ -#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ -#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ -#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ -#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ - -/* Parameter RAM offsets from the base. -*/ -#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ -#define PROFF_SCC1 ((uint)0x8000) -#define PROFF_SCC2 ((uint)0x8100) -#define PROFF_SCC3 ((uint)0x8200) -#define PROFF_SCC4 ((uint)0x8300) -#define PROFF_FCC1 ((uint)0x8400) -#define PROFF_FCC2 ((uint)0x8500) -#define PROFF_FCC3 ((uint)0x8600) -#define PROFF_MCC1 ((uint)0x8700) -#define PROFF_MCC2 ((uint)0x8800) -#define PROFF_SPI_BASE ((uint)0x89fc) -#define PROFF_TIMERS ((uint)0x8ae0) -#define PROFF_REVNUM ((uint)0x8af0) -#define PROFF_RAND ((uint)0x8af8) -#define PROFF_I2C_BASE ((uint)0x8afc) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* CPM Ethernet through SCC1. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PSMR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. - * Common to SCC and FCC. - */ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. - * Common to SCC and FCC. - */ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PSMR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0003) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* How about some FCCs..... -*/ -#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) -#define FCC_GFMR_DIAG_LE ((uint)0x40000000) -#define FCC_GFMR_DIAG_AE ((uint)0x80000000) -#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) -#define FCC_GFMR_TCI ((uint)0x20000000) -#define FCC_GFMR_TRX ((uint)0x10000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_CDP ((uint)0x04000000) -#define FCC_GFMR_CTSP ((uint)0x02000000) -#define FCC_GFMR_CDS ((uint)0x01000000) -#define FCC_GFMR_CTSS ((uint)0x00800000) -#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) -#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) -#define FCC_GFMR_SYNL_8 ((uint)0x00008000) -#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) -#define FCC_GFMR_RTSM ((uint)0x00002000) -#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) -#define FCC_GFMR_REVD ((uint)0x00000400) -#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) -#define FCC_GFMR_TCRC_16 ((uint)0x00000000) -#define FCC_GFMR_TCRC_32 ((uint)0x00000080) -#define FCC_GFMR_ENR ((uint)0x00000020) -#define FCC_GFMR_ENT ((uint)0x00000010) -#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) -#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) -#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) - -/* Generic FCC parameter ram. -*/ -typedef struct fcc_param { - ushort fcc_riptr; /* Rx Internal temp pointer */ - ushort fcc_tiptr; /* Tx Internal temp pointer */ - ushort fcc_res1; - ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ - uint fcc_rstate; /* Upper byte is Func code, must be set */ - uint fcc_rbase; /* Receive BD base */ - ushort fcc_rbdstat; /* RxBD status */ - ushort fcc_rbdlen; /* RxBD down counter */ - uint fcc_rdptr; /* RxBD internal data pointer */ - uint fcc_tstate; /* Upper byte is Func code, must be set */ - uint fcc_tbase; /* Transmit BD base */ - ushort fcc_tbdstat; /* TxBD status */ - ushort fcc_tbdlen; /* TxBD down counter */ - uint fcc_tdptr; /* TxBD internal data pointer */ - uint fcc_rbptr; /* Rx BD Internal buf pointer */ - uint fcc_tbptr; /* Tx BD Internal buf pointer */ - uint fcc_rcrc; /* Rx temp CRC */ - uint fcc_res2; - uint fcc_tcrc; /* Tx temp CRC */ -} fccp_t; - - -/* Ethernet controller through FCC. -*/ -typedef struct fcc_enet { - fccp_t fen_genfcc; - uint fen_statbuf; /* Internal status buffer */ - uint fen_camptr; /* CAM address */ - uint fen_cmask; /* Constant mask for CRC */ - uint fen_cpres; /* Preset CRC */ - uint fen_crcec; /* CRC Error counter */ - uint fen_alec; /* alignment error counter */ - uint fen_disfc; /* discard frame counter */ - ushort fen_retlim; /* Retry limit */ - ushort fen_retcnt; /* Retry counter */ - ushort fen_pper; /* Persistence */ - ushort fen_boffcnt; /* backoff counter */ - uint fen_gaddrh; /* Group address filter, high 32-bits */ - uint fen_gaddrl; /* Group address filter, low 32-bits */ - ushort fen_tfcstat; /* out of sequence TxBD */ - ushort fen_tfclen; - uint fen_tfcptr; - ushort fen_mflr; /* Maximum frame length (1518) */ - ushort fen_paddrh; /* MAC address */ - ushort fen_paddrm; - ushort fen_paddrl; - ushort fen_ibdcount; /* Internal BD counter */ - ushort fen_ibdstart; /* Internal BD start pointer */ - ushort fen_ibdend; /* Internal BD end pointer */ - ushort fen_txlen; /* Internal Tx frame length counter */ - uint fen_ibdbase[8]; /* Internal use */ - uint fen_iaddrh; /* Individual address filter */ - uint fen_iaddrl; - ushort fen_minflr; /* Minimum frame length (64) */ - ushort fen_taddrh; /* Filter transfer MAC address */ - ushort fen_taddrm; - ushort fen_taddrl; - ushort fen_padptr; /* Pointer to pad byte buffer */ - ushort fen_cftype; /* control frame type */ - ushort fen_cfrange; /* control frame range */ - ushort fen_maxb; /* maximum BD count */ - ushort fen_maxd1; /* Max DMA1 length (1520) */ - ushort fen_maxd2; /* Max DMA2 length (1520) */ - ushort fen_maxd; /* internal max DMA count */ - ushort fen_dmacnt; /* internal DMA counter */ - uint fen_octc; /* Total octect counter */ - uint fen_colc; /* Total collision counter */ - uint fen_broc; /* Total broadcast packet counter */ - uint fen_mulc; /* Total multicast packet count */ - uint fen_uspc; /* Total packets < 64 bytes */ - uint fen_frgc; /* Total packets < 64 bytes with errors */ - uint fen_ospc; /* Total packets > 1518 */ - uint fen_jbrc; /* Total packets > 1518 with errors */ - uint fen_p64c; /* Total packets == 64 bytes */ - uint fen_p65c; /* Total packets 64 < bytes <= 127 */ - uint fen_p128c; /* Total packets 127 < bytes <= 255 */ - uint fen_p256c; /* Total packets 256 < bytes <= 511 */ - uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ - uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ - uint fen_cambuf; /* Internal CAM buffer poiner */ - ushort fen_rfthr; /* Received frames threshold */ - ushort fen_rfcnt; /* Received frames count */ -} fcc_enet_t; - -/* FCC Event/Mask register as used by Ethernet. -*/ -#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ -#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ -#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ -#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* FCC Mode Register (FPSMR) as used by Ethernet. -*/ -#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ -#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ -#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ -#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ -#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ -#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ -#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ -#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ -#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ -#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ -#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ -#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ -#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ -} iic_t; - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; /* Tx temp. */ - uint spi_res1[4]; /* SDMA temp. */ -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) -#define SPMODE_PM(x) ((x) &0xF) - -#define SPI_EB ((u_char)0x10) /* big endian byte order */ - -#define BD_IIC_START ((ushort)0x0400) - -/*----------------------------------------------------------------------- - * CMXFCR - CMX FCC Clock Route Register 15-12 - */ -#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ -#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ -#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ -#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ -#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ -#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ -#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ -#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ -#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ - -#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ -#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ -#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ -#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ -#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ -#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ -#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ -#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ - -#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ -#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ -#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ -#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ -#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ -#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ -#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ -#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ - -#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ -#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ -#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ -#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ -#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ -#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ -#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ -#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ - -#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ -#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ -#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ -#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ -#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ -#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ -#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ -#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ - -#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ -#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ -#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ -#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ -#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ -#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ -#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ -#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ - -#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ -#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ -#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ -#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ -#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ -#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ -#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ -#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ - -/*----------------------------------------------------------------------- - * CMXSCR - CMX SCC Clock Route Register 15-14 - */ -#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ -#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ -#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ -#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ -#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ -#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ -#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ -#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ -#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ -#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ -#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ -#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ -#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ -#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ -#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ -#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ - -#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ -#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ -#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ -#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ -#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ -#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ -#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ -#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ -#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ -#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ -#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ -#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ -#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ -#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ -#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ -#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ -#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ -#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ -#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ -#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ -#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ -#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ -#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ -#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ -#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ -#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ -#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ -#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ -#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ -#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ -#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ -#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ -#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ -#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ -#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ -#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ -#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ -#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ -#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ -#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ -#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ -#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ -#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ - -#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ -#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ -#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ -#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ -#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ -#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ -#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ -#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ -#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ -#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ -#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ -#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ -#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ -#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ -#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ - -#endif /* __CPM_85XX__ */ diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h deleted file mode 100644 index bfef4df..0000000 --- a/include/asm-ppc/e300.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor, Inc. - * Liberty Eran (liberty@freescale.com) - */ - -#ifndef __E300_H__ -#define __E300_H__ - -#define PVR_E300C1 0x80830000 -#define PVR_E300C2 0x80840000 -#define PVR_E300C3 0x80850000 -#define PVR_E300C4 0x80860000 - -/* - * Hardware Implementation-Dependent Register 0 (HID0) - */ - -/* #define HID0 1008 already defined in processor.h */ -#define HID0_MASK_MACHINE_CHECK 0x00000000 -#define HID0_ENABLE_MACHINE_CHECK 0x80000000 - -#define HID0_DISABLE_CACHE_PARITY 0x00000000 -#define HID0_ENABLE_CACHE_PARITY 0x40000000 - -#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ -#define HID0_ENABLE_ADDRESS_PARITY 0x20000000 - -#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ -#define HID0_ENABLE_DATE_PARITY 0x10000000 - -#define HID0_CORE_CLK_OUT 0x00000000 -#define HID0_CORE_CLK_OUT_DIV_2 0x08000000 - -#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */ -#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000 - -#define HID0_DISABLE_DOSE_MODE 0x00000000 -#define HID0_ENABLE_DOSE_MODE 0x00800000 - -#define HID0_DISABLE_NAP_MODE 0x00000000 -#define HID0_ENABLE_NAP_MODE 0x00400000 - -#define HID0_DISABLE_SLEEP_MODE 0x00000000 -#define HID0_ENABLE_SLEEP_MODE 0x00200000 - -#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000 -#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000 - -#define HID0_SOFT_RESET 0x00010000 - -#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 -#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 - -#define HID0_DISABLE_DATA_CACHE 0x00000000 -#define HID0_ENABLE_DATA_CACHE 0x00004000 - -#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 - -#define HID0_LOCK_DATA_CACHE 0x00001000 - -#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800 - -#define HID0_INVALIDATE_DATA_CACHE 0x00000400 - -#define HID0_DISABLE_M_BIT 0x00000000 -#define HID0_ENABLE_M_BIT 0x00000080 - -#define HID0_FBIOB 0x00000010 - -#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 -#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 - -#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000 -#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001 - -/* - * Hardware Implementation-Dependent Register 2 (HID2) - */ -#define HID2 1011 - -#define HID2_LET 0x08000000 -#define HID2_HBE 0x00040000 -#define HID2_IWLCK_000 0x00000000 /* no ways locked */ -#define HID2_IWLCK_001 0x00002000 /* way 0 locked */ -#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */ -#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */ -#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */ -#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ -#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */ - -#endif /* __E300_H__ */ diff --git a/include/asm-ppc/errno.h b/include/asm-ppc/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/include/asm-ppc/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h deleted file mode 100644 index 55923e0..0000000 --- a/include/asm-ppc/fsl_ddr_dimm_params.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef DDR2_DIMM_PARAMS_H -#define DDR2_DIMM_PARAMS_H - -/* Parameters for a DDR2 dimm computed from the SPD */ -typedef struct dimm_params_s { - - /* DIMM organization parameters */ - char mpart[19]; /* guaranteed null terminated */ - - unsigned int n_ranks; - unsigned long long rank_density; - unsigned long long capacity; - unsigned int data_width; - unsigned int primary_sdram_width; - unsigned int ec_sdram_width; - unsigned int registered_dimm; - - /* SDRAM device parameters */ - unsigned int n_row_addr; - unsigned int n_col_addr; - unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ - unsigned int n_banks_per_sdram_device; - unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ - unsigned int row_density; - - /* used in computing base address of DIMMs */ - unsigned long long base_address; - /* mirrored DIMMs */ - unsigned int mirrored_dimm; /* only for ddr3 */ - - /* DIMM timing parameters */ - - unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ - unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */ - unsigned int tFAW_ps; /* four active window delay, only for ddr3 */ - - /* - * SDRAM clock periods - * The range for these are 1000-10000 so a short should be sufficient - */ - unsigned int tCKmin_X_ps; - unsigned int tCKmin_X_minus_1_ps; - unsigned int tCKmin_X_minus_2_ps; - unsigned int tCKmax_ps; - - /* SPD-defined CAS latencies */ - unsigned int caslat_X; - unsigned int caslat_X_minus_1; - unsigned int caslat_X_minus_2; - - unsigned int caslat_lowest_derated; /* Derated CAS latency */ - - /* basic timing parameters */ - unsigned int tRCD_ps; - unsigned int tRP_ps; - unsigned int tRAS_ps; - - unsigned int tWR_ps; /* maximum = 63750 ps */ - unsigned int tWTR_ps; /* maximum = 63750 ps */ - unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns - = 511750 ps */ - - unsigned int tRRD_ps; /* maximum = 63750 ps */ - unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - - unsigned int refresh_rate_ps; - - /* DDR3 doesn't need these as below */ - unsigned int tIS_ps; /* byte 32, spd->ca_setup */ - unsigned int tIH_ps; /* byte 33, spd->ca_hold */ - unsigned int tDS_ps; /* byte 34, spd->data_setup */ - unsigned int tDH_ps; /* byte 35, spd->data_hold */ - unsigned int tRTP_ps; /* byte 38, spd->trtp */ - unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tQHS_ps; /* byte 45, spd->tqhs */ -} dimm_params_t; - -extern unsigned int ddr_compute_dimm_parameters( - const generic_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number); - -#endif diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h deleted file mode 100644 index 3216a50..0000000 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef FSL_DDR_MEMCTL_H -#define FSL_DDR_MEMCTL_H - -/* - * Pick a basic DDR Technology. - */ -#include - -#define SDRAM_TYPE_DDR1 2 -#define SDRAM_TYPE_DDR2 3 -#define SDRAM_TYPE_LPDDR1 6 -#define SDRAM_TYPE_DDR3 7 - -#define DDR_BL4 4 /* burst length 4 */ -#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ -#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ -#define DDR_BL8 8 /* burst length 8 */ - -#if defined(CONFIG_FSL_DDR1) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) -typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 -#endif -#elif defined(CONFIG_FSL_DDR2) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) -typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 -#endif -#elif defined(CONFIG_FSL_DDR3) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ -typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 -#endif -#endif /* #if defined(CONFIG_FSL_DDR1) */ - -/* define bank(chip select) interleaving mode */ -#define FSL_DDR_CS0_CS1 0x40 -#define FSL_DDR_CS2_CS3 0x20 -#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) -#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) - -/* define memory controller interleaving mode */ -#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 -#define FSL_DDR_PAGE_INTERLEAVING 0x1 -#define FSL_DDR_BANK_INTERLEAVING 0x2 -#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 - -/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration - */ -#define SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG_SREN 0x40000000 -#define SDRAM_CFG_ECC_EN 0x20000000 -#define SDRAM_CFG_RD_EN 0x10000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 -#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 -#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 -#define SDRAM_CFG_DYN_PWR 0x00200000 -#define SDRAM_CFG_32_BE 0x00080000 -#define SDRAM_CFG_8_BE 0x00040000 -#define SDRAM_CFG_NCAP 0x00020000 -#define SDRAM_CFG_2T_EN 0x00008000 -#define SDRAM_CFG_BI 0x00000001 - -#if defined(CONFIG_P4080) -#define RD_TO_PRE_MASK 0xf -#define RD_TO_PRE_SHIFT 13 -#define WR_DATA_DELAY_MASK 0xf -#define WR_DATA_DELAY_SHIFT 9 -#else -#define RD_TO_PRE_MASK 0x7 -#define RD_TO_PRE_SHIFT 13 -#define WR_DATA_DELAY_MASK 0x7 -#define WR_DATA_DELAY_SHIFT 10 -#endif - -/* Record of register values computed */ -typedef struct fsl_ddr_cfg_regs_s { - struct { - unsigned int bnds; - unsigned int config; - unsigned int config_2; - } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; - unsigned int timing_cfg_3; - unsigned int timing_cfg_0; - unsigned int timing_cfg_1; - unsigned int timing_cfg_2; - unsigned int ddr_sdram_cfg; - unsigned int ddr_sdram_cfg_2; - unsigned int ddr_sdram_mode; - unsigned int ddr_sdram_mode_2; - unsigned int ddr_sdram_md_cntl; - unsigned int ddr_sdram_interval; - unsigned int ddr_data_init; - unsigned int ddr_sdram_clk_cntl; - unsigned int ddr_init_addr; - unsigned int ddr_init_ext_addr; - unsigned int timing_cfg_4; - unsigned int timing_cfg_5; - unsigned int ddr_zq_cntl; - unsigned int ddr_wrlvl_cntl; - unsigned int ddr_sr_cntr; - unsigned int ddr_sdram_rcw_1; - unsigned int ddr_sdram_rcw_2; -} fsl_ddr_cfg_regs_t; - -typedef struct memctl_options_partial_s { - unsigned int all_DIMMs_ECC_capable; - unsigned int all_DIMMs_tCKmax_ps; - unsigned int all_DIMMs_burst_lengths_bitmask; - unsigned int all_DIMMs_registered; - unsigned int all_DIMMs_unbuffered; - /* unsigned int lowest_common_SPD_caslat; */ - unsigned int all_DIMMs_minimum_tRCD_ps; -} memctl_options_partial_t; - -/* - * Generalized parameters for memory controller configuration, - * might be a little specific to the FSL memory controller - */ -typedef struct memctl_options_s { - /* - * Memory organization parameters - * - * if DIMM is present in the system - * where DIMMs are with respect to chip select - * where chip selects are with respect to memory boundaries - */ - unsigned int registered_dimm_en; /* use registered DIMM support */ - - /* Options local to a Chip Select */ - struct cs_local_opts_s { - unsigned int auto_precharge; - unsigned int odt_rd_cfg; - unsigned int odt_wr_cfg; - } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; - - /* Special configurations for chip select */ - unsigned int memctl_interleaving; - unsigned int memctl_interleaving_mode; - unsigned int ba_intlv_ctl; - - /* Operational mode parameters */ - unsigned int ECC_mode; /* Use ECC? */ - /* Initialize ECC using memory controller? */ - unsigned int ECC_init_using_memctl; - unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */ - /* SREN - self-refresh during sleep */ - unsigned int self_refresh_in_sleep; - unsigned int dynamic_power; /* DYN_PWR */ - /* memory data width to use (16-bit, 32-bit, 64-bit) */ - unsigned int data_bus_width; - unsigned int burst_length; /* BL4, OTF and BL8 */ - /* On-The-Fly Burst Chop enable */ - unsigned int OTF_burst_chop_en; - /* mirrior DIMMs for DDR3 */ - unsigned int mirrored_dimm; - - /* Global Timing Parameters */ - unsigned int cas_latency_override; - unsigned int cas_latency_override_value; - unsigned int use_derated_caslat; - unsigned int additive_latency_override; - unsigned int additive_latency_override_value; - - unsigned int clk_adjust; /* */ - unsigned int cpo_override; - unsigned int write_data_delay; /* DQS adjust */ - - unsigned int wrlvl_override; - unsigned int wrlvl_sample; /* Write leveling */ - unsigned int wrlvl_start; - - unsigned int half_strength_driver_enable; - unsigned int twoT_en; - unsigned int threeT_en; - unsigned int bstopre; - unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ - unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ - - /* Rtt impedance */ - unsigned int rtt_override; /* rtt_override enable */ - unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ - unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ - - /* Automatic self refresh */ - unsigned int auto_self_refresh_en; - unsigned int sr_it; - /* ZQ calibration */ - unsigned int zq_en; - /* Write leveling */ - unsigned int wrlvl_en; -} memctl_options_t; - -extern phys_size_t fsl_ddr_sdram(void); -#endif diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h deleted file mode 100644 index 1164191..0000000 --- a/include/asm-ppc/fsl_dma.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Freescale DMA Controller - * - * Copyright 2006 Freescale Semiconductor, Inc. - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_FSL_DMA_H_ -#define _ASM_FSL_DMA_H_ - -#include - -#ifdef CONFIG_MPC83xx -typedef struct fsl_dma { - uint mr; /* DMA mode register */ -#define FSL_DMA_MR_CS 0x00000001 /* Channel start */ -#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */ -#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */ -#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */ -#define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */ -#define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */ -#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */ -#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */ -#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */ -#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */ -#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */ -#define FSL_DMA_MR_IRQS 0x00080000 /* Interrupt steer */ -#define FSL_DMA_MR_DMSEN 0x00100000 /* Direct mode snooping en */ -#define FSL_DMA_MR_BWC_MASK 0x00e00000 /* Bandwidth/pause ctl */ -#define FSL_DMA_MR_DRCNT 0x0f000000 /* DMA request count */ - uint sr; /* DMA status register */ -#define FSL_DMA_SR_EOCDI 0x00000001 /* End-of-chain/direct interrupt */ -#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */ -#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */ -#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */ - uint cdar; /* DMA current descriptor address register */ - char res0[4]; - uint sar; /* DMA source address register */ - char res1[4]; - uint dar; /* DMA destination address register */ - char res2[4]; - uint bcr; /* DMA byte count register */ - uint ndar; /* DMA next descriptor address register */ - uint gsr; /* DMA general status register (DMA3 ONLY!) */ - char res3[84]; -} fsl_dma_t; -#else -typedef struct fsl_dma { - uint mr; /* DMA mode register */ -#define FSL_DMA_MR_CS 0x00000001 /* Channel start */ -#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */ -#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */ -#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */ -#define FSL_DMA_MR_CA 0x00000008 /* Channel abort */ -#define FSL_DMA_MR_CDSM 0x00000010 -#define FSL_DMA_MR_XFE 0x00000020 /* Extended features en */ -#define FSL_DMA_MR_EIE 0x00000040 /* Error interrupt en */ -#define FSL_DMA_MR_EOLSIE 0x00000080 /* End-of-lists interrupt en */ -#define FSL_DMA_MR_EOLNIE 0x00000100 /* End-of-links interrupt en */ -#define FSL_DMA_MR_EOSIE 0x00000200 /* End-of-seg interrupt en */ -#define FSL_DMA_MR_SRW 0x00000400 /* Single register write */ -#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */ -#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */ -#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */ -#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */ -#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */ -#define FSL_DMA_MR_EMP_EN 0x00200000 /* Ext master pause en */ -#define FSL_DMA_MR_BWC_MASK 0x0f000000 /* Bandwidth/pause ctl */ -#define FSL_DMA_MR_BWC_DIS 0x0f000000 /* Bandwidth/pause ctl disable */ - uint sr; /* DMA status register */ -#define FSL_DMA_SR_EOLSI 0x00000001 /* End-of-list interrupt */ -#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */ -#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */ -#define FSL_DMA_SR_EOLNI 0x00000008 /* End-of-links interrupt */ -#define FSL_DMA_SR_PE 0x00000010 /* Programming error */ -#define FSL_DMA_SR_CH 0x00000020 /* Channel halted */ -#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */ - char res0[4]; - uint clndar; /* DMA current link descriptor address register */ - uint satr; /* DMA source attributes register */ -#define FSL_DMA_SATR_ESAD_MASK 0x000001ff /* Extended source addr */ -#define FSL_DMA_SATR_SREAD_NO_SNOOP 0x00040000 /* Read, don't snoop */ -#define FSL_DMA_SATR_SREAD_SNOOP 0x00050000 /* Read, snoop */ -#define FSL_DMA_SATR_SREAD_UNLOCK 0x00070000 /* Read, unlock l2 */ -#define FSL_DMA_SATR_STRAN_MASK 0x00f00000 /* Source interface */ -#define FSL_DMA_SATR_SSME 0x01000000 /* Source stride en */ -#define FSL_DMA_SATR_SPCIORDER 0x02000000 /* PCI transaction order */ -#define FSL_DMA_SATR_STFLOWLVL_MASK 0x0c000000 /* RIO flow level */ -#define FSL_DMA_SATR_SBPATRMU 0x20000000 /* Bypass ATMU */ - uint sar; /* DMA source address register */ - uint datr; /* DMA destination attributes register */ -#define FSL_DMA_DATR_EDAD_MASK 0x000001ff /* Extended dest addr */ -#define FSL_DMA_DATR_DWRITE_NO_SNOOP 0x00040000 /* Write, don't snoop */ -#define FSL_DMA_DATR_DWRITE_SNOOP 0x00050000 /* Write, snoop */ -#define FSL_DMA_DATR_DWRITE_ALLOC 0x00060000 /* Write, alloc l2 */ -#define FSL_DMA_DATR_DWRITE_LOCK 0x00070000 /* Write, lock l2 */ -#define FSL_DMA_DATR_DTRAN_MASK 0x00f00000 /* Dest interface */ -#define FSL_DMA_DATR_DSME 0x01000000 /* Dest stride en */ -#define FSL_DMA_DATR_DPCIORDER 0x02000000 /* PCI transaction order */ -#define FSL_DMA_DATR_DTFLOWLVL_MASK 0x0c000000 /* RIO flow level */ -#define FSL_DMA_DATR_DBPATRMU 0x20000000 /* Bypass ATMU */ - uint dar; /* DMA destination address register */ - uint bcr; /* DMA byte count register */ - char res1[4]; - uint nlndar; /* DMA next link descriptor address register */ - char res2[8]; - uint clabdar; /* DMA current List - alternate base descriptor address Register */ - char res3[4]; - uint nlsdar; /* DMA next list descriptor address register */ - uint ssr; /* DMA source stride register */ - uint dsr; /* DMA destination stride register */ - char res4[56]; -} fsl_dma_t; -#endif /* !CONFIG_MPC83xx */ - -#ifdef CONFIG_FSL_DMA -void dma_init(void); -int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n); -#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) -void dma_meminit(uint val, uint size); -#endif -#endif - -#endif /* _ASM_DMA_H_ */ diff --git a/include/asm-ppc/fsl_i2c.h b/include/asm-ppc/fsl_i2c.h deleted file mode 100644 index 4f71341..0000000 --- a/include/asm-ppc/fsl_i2c.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Freescale I2C Controller - * - * Copyright 2006 Freescale Semiconductor, Inc. - * - * Based on earlier versions by Gleb Natapov , - * Xianghua Xiao , Eran Liberty (liberty@freescale.com), - * and Jeff Brown. - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_FSL_I2C_H_ -#define _ASM_FSL_I2C_H_ - -#include - -typedef struct fsl_i2c { - - u8 adr; /* I2C slave address */ - u8 res0[3]; -#define I2C_ADR 0xFE -#define I2C_ADR_SHIFT 1 -#define I2C_ADR_RES ~(I2C_ADR) - - u8 fdr; /* I2C frequency divider register */ - u8 res1[3]; -#define IC2_FDR 0x3F -#define IC2_FDR_SHIFT 0 -#define IC2_FDR_RES ~(IC2_FDR) - - u8 cr; /* I2C control redister */ - u8 res2[3]; -#define I2C_CR_MEN 0x80 -#define I2C_CR_MIEN 0x40 -#define I2C_CR_MSTA 0x20 -#define I2C_CR_MTX 0x10 -#define I2C_CR_TXAK 0x08 -#define I2C_CR_RSTA 0x04 -#define I2C_CR_BCST 0x01 - - u8 sr; /* I2C status register */ - u8 res3[3]; -#define I2C_SR_MCF 0x80 -#define I2C_SR_MAAS 0x40 -#define I2C_SR_MBB 0x20 -#define I2C_SR_MAL 0x10 -#define I2C_SR_BCSTM 0x08 -#define I2C_SR_SRW 0x04 -#define I2C_SR_MIF 0x02 -#define I2C_SR_RXAK 0x01 - - u8 dr; /* I2C data register */ - u8 res4[3]; -#define I2C_DR 0xFF -#define I2C_DR_SHIFT 0 -#define I2C_DR_RES ~(I2C_DR) - - u8 dfsrr; /* I2C digital filter sampling rate register */ - u8 res5[3]; -#define I2C_DFSRR 0x3F -#define I2C_DFSRR_SHIFT 0 -#define I2C_DFSRR_RES ~(I2C_DR) - - /* Fill out the reserved block */ - u8 res6[0xE8]; -} fsl_i2c_t; - -#endif /* _ASM_I2C_H_ */ diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h deleted file mode 100644 index 34c56a2..0000000 --- a/include/asm-ppc/fsl_law.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef _FSL_LAW_H_ -#define _FSL_LAW_H_ - -#include - -#define LAW_EN 0x80000000 - -#define SET_LAW_ENTRY(idx, a, sz, trgt) \ - { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } - -#define SET_LAW(a, sz, trgt) \ - { .index = -1, .addr = a, .size = sz, .trgt_id = trgt } - -enum law_size { - LAW_SIZE_4K = 0xb, - LAW_SIZE_8K, - LAW_SIZE_16K, - LAW_SIZE_32K, - LAW_SIZE_64K, - LAW_SIZE_128K, - LAW_SIZE_256K, - LAW_SIZE_512K, - LAW_SIZE_1M, - LAW_SIZE_2M, - LAW_SIZE_4M, - LAW_SIZE_8M, - LAW_SIZE_16M, - LAW_SIZE_32M, - LAW_SIZE_64M, - LAW_SIZE_128M, - LAW_SIZE_256M, - LAW_SIZE_512M, - LAW_SIZE_1G, - LAW_SIZE_2G, - LAW_SIZE_4G, - LAW_SIZE_8G, - LAW_SIZE_16G, - LAW_SIZE_32G, -}; - -#define law_size_bits(sz) (__ilog2_u64(sz) - 1) - -#ifdef CONFIG_FSL_CORENET -enum law_trgt_if { - LAW_TRGT_IF_PCIE_1 = 0x00, - LAW_TRGT_IF_PCIE_2 = 0x01, - LAW_TRGT_IF_PCIE_3 = 0x02, - LAW_TRGT_IF_RIO_1 = 0x08, - LAW_TRGT_IF_RIO_2 = 0x09, - - LAW_TRGT_IF_DDR_1 = 0x10, - LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ - LAW_TRGT_IF_DDR_INTRLV = 0x14, - - LAW_TRGT_IF_BMAN = 0x18, - LAW_TRGT_IF_DCSR = 0x1d, - LAW_TRGT_IF_LBC = 0x1f, - LAW_TRGT_IF_QMAN = 0x3c, -}; -#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 -#else -enum law_trgt_if { - LAW_TRGT_IF_PCI = 0x00, - LAW_TRGT_IF_PCI_2 = 0x01, -#ifndef CONFIG_MPC8641 - LAW_TRGT_IF_PCIE_1 = 0x02, -#endif -#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) - LAW_TRGT_IF_PCIE_3 = 0x03, -#endif - LAW_TRGT_IF_LBC = 0x04, - LAW_TRGT_IF_CCSR = 0x08, - LAW_TRGT_IF_DDR_INTRLV = 0x0b, - LAW_TRGT_IF_RIO = 0x0c, - LAW_TRGT_IF_RIO_2 = 0x0d, - LAW_TRGT_IF_DDR = 0x0f, - LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ -}; -#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR -#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI -#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI -#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 - -#ifdef CONFIG_MPC8641 -#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI -#endif - -#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) -#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI -#endif -#endif /* CONFIG_FSL_CORENET */ - -struct law_entry { - int index; - phys_addr_t addr; - enum law_size size; - enum law_trgt_if trgt_id; -}; - -extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); -extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); -extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); -extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id); -extern struct law_entry find_law(phys_addr_t addr); -extern void disable_law(u8 idx); -extern void init_laws(void); -extern void print_laws(void); - -/* define in board code */ -extern struct law_entry law_table[]; -extern int num_law_entries; -#endif diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h deleted file mode 100644 index 5723de6..0000000 --- a/include/asm-ppc/fsl_lbc.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#ifndef __ASM_PPC_FSL_LBC_H -#define __ASM_PPC_FSL_LBC_H - -#include - -/* BR - Base Registers - */ -#define BR0 0x5000 /* Register offset to immr */ -#define BR1 0x5008 -#define BR2 0x5010 -#define BR3 0x5018 -#define BR4 0x5020 -#define BR5 0x5028 -#define BR6 0x5030 -#define BR7 0x5038 - -#define BR_BA 0xFFFF8000 -#define BR_BA_SHIFT 15 -#define BR_XBA 0x00006000 -#define BR_XBA_SHIFT 13 -#define BR_PS 0x00001800 -#define BR_PS_SHIFT 11 -#define BR_PS_8 0x00000800 /* Port Size 8 bit */ -#define BR_PS_16 0x00001000 /* Port Size 16 bit */ -#define BR_PS_32 0x00001800 /* Port Size 32 bit */ -#define BR_DECC 0x00000600 -#define BR_DECC_SHIFT 9 -#define BR_DECC_OFF 0x00000000 -#define BR_DECC_CHK 0x00000200 -#define BR_DECC_CHK_GEN 0x00000400 -#define BR_WP 0x00000100 -#define BR_WP_SHIFT 8 -#define BR_MSEL 0x000000E0 -#define BR_MSEL_SHIFT 5 -#define BR_MS_GPCM 0x00000000 /* GPCM */ -#define BR_MS_FCM 0x00000020 /* FCM */ -#ifdef CONFIG_MPC83xx -#define BR_MS_SDRAM 0x00000060 /* SDRAM */ -#elif defined(CONFIG_MPC85xx) -#define BR_MS_SDRAM 0x00000000 /* SDRAM */ -#endif -#define BR_MS_UPMA 0x00000080 /* UPMA */ -#define BR_MS_UPMB 0x000000A0 /* UPMB */ -#define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if !defined(CONFIG_MPC834x) -#define BR_ATOM 0x0000000C -#define BR_ATOM_SHIFT 2 -#endif -#define BR_V 0x00000001 -#define BR_V_SHIFT 0 - -#define UPMA 0 -#define UPMB 1 -#define UPMC 2 - -#if defined(CONFIG_MPC834x) -#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) -#else -#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) -#endif - -/* Convert an address into the right format for the BR registers */ -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC) -#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ - ((x & 0x300000000ULL) >> 19))) -#else -#define BR_PHYS_ADDR(x) (x & 0xffff8000) -#endif - -/* OR - Option Registers - */ -#define OR0 0x5004 /* Register offset to immr */ -#define OR1 0x500C -#define OR2 0x5014 -#define OR3 0x501C -#define OR4 0x5024 -#define OR5 0x502C -#define OR6 0x5034 -#define OR7 0x503C - -#define OR_GPCM_AM 0xFFFF8000 -#define OR_GPCM_AM_SHIFT 15 -#define OR_GPCM_XAM 0x00006000 -#define OR_GPCM_XAM_SHIFT 13 -#define OR_GPCM_BCTLD 0x00001000 -#define OR_GPCM_BCTLD_SHIFT 12 -#define OR_GPCM_CSNT 0x00000800 -#define OR_GPCM_CSNT_SHIFT 11 -#define OR_GPCM_ACS 0x00000600 -#define OR_GPCM_ACS_SHIFT 9 -#define OR_GPCM_ACS_DIV2 0x00000600 -#define OR_GPCM_ACS_DIV4 0x00000400 -#define OR_GPCM_XACS 0x00000100 -#define OR_GPCM_XACS_SHIFT 8 -#define OR_GPCM_SCY 0x000000F0 -#define OR_GPCM_SCY_SHIFT 4 -#define OR_GPCM_SCY_1 0x00000010 -#define OR_GPCM_SCY_2 0x00000020 -#define OR_GPCM_SCY_3 0x00000030 -#define OR_GPCM_SCY_4 0x00000040 -#define OR_GPCM_SCY_5 0x00000050 -#define OR_GPCM_SCY_6 0x00000060 -#define OR_GPCM_SCY_7 0x00000070 -#define OR_GPCM_SCY_8 0x00000080 -#define OR_GPCM_SCY_9 0x00000090 -#define OR_GPCM_SCY_10 0x000000a0 -#define OR_GPCM_SCY_11 0x000000b0 -#define OR_GPCM_SCY_12 0x000000c0 -#define OR_GPCM_SCY_13 0x000000d0 -#define OR_GPCM_SCY_14 0x000000e0 -#define OR_GPCM_SCY_15 0x000000f0 -#define OR_GPCM_SETA 0x00000008 -#define OR_GPCM_SETA_SHIFT 3 -#define OR_GPCM_TRLX 0x00000004 -#define OR_GPCM_TRLX_SHIFT 2 -#define OR_GPCM_EHTR 0x00000002 -#define OR_GPCM_EHTR_SHIFT 1 -#define OR_GPCM_EAD 0x00000001 -#define OR_GPCM_EAD_SHIFT 0 - -/* helpers to convert values into an OR address mask (GPCM mode) */ -#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ -#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) - -#define OR_FCM_AM 0xFFFF8000 -#define OR_FCM_AM_SHIFT 15 -#define OR_FCM_XAM 0x00006000 -#define OR_FCM_XAM_SHIFT 13 -#define OR_FCM_BCTLD 0x00001000 -#define OR_FCM_BCTLD_SHIFT 12 -#define OR_FCM_PGS 0x00000400 -#define OR_FCM_PGS_SHIFT 10 -#define OR_FCM_CSCT 0x00000200 -#define OR_FCM_CSCT_SHIFT 9 -#define OR_FCM_CST 0x00000100 -#define OR_FCM_CST_SHIFT 8 -#define OR_FCM_CHT 0x00000080 -#define OR_FCM_CHT_SHIFT 7 -#define OR_FCM_SCY 0x00000070 -#define OR_FCM_SCY_SHIFT 4 -#define OR_FCM_SCY_1 0x00000010 -#define OR_FCM_SCY_2 0x00000020 -#define OR_FCM_SCY_3 0x00000030 -#define OR_FCM_SCY_4 0x00000040 -#define OR_FCM_SCY_5 0x00000050 -#define OR_FCM_SCY_6 0x00000060 -#define OR_FCM_SCY_7 0x00000070 -#define OR_FCM_RST 0x00000008 -#define OR_FCM_RST_SHIFT 3 -#define OR_FCM_TRLX 0x00000004 -#define OR_FCM_TRLX_SHIFT 2 -#define OR_FCM_EHTR 0x00000002 -#define OR_FCM_EHTR_SHIFT 1 - -#define OR_UPM_AM 0xFFFF8000 -#define OR_UPM_AM_SHIFT 15 -#define OR_UPM_XAM 0x00006000 -#define OR_UPM_XAM_SHIFT 13 -#define OR_UPM_BCTLD 0x00001000 -#define OR_UPM_BCTLD_SHIFT 12 -#define OR_UPM_BI 0x00000100 -#define OR_UPM_BI_SHIFT 8 -#define OR_UPM_TRLX 0x00000004 -#define OR_UPM_TRLX_SHIFT 2 -#define OR_UPM_EHTR 0x00000002 -#define OR_UPM_EHTR_SHIFT 1 -#define OR_UPM_EAD 0x00000001 -#define OR_UPM_EAD_SHIFT 0 - -#define OR_SDRAM_AM 0xFFFF8000 -#define OR_SDRAM_AM_SHIFT 15 -#define OR_SDRAM_XAM 0x00006000 -#define OR_SDRAM_XAM_SHIFT 13 -#define OR_SDRAM_COLS 0x00001C00 -#define OR_SDRAM_COLS_SHIFT 10 -#define OR_SDRAM_ROWS 0x000001C0 -#define OR_SDRAM_ROWS_SHIFT 6 -#define OR_SDRAM_PMSEL 0x00000020 -#define OR_SDRAM_PMSEL_SHIFT 5 -#define OR_SDRAM_EAD 0x00000001 -#define OR_SDRAM_EAD_SHIFT 0 - -#define OR_AM_32KB 0xFFFF8000 -#define OR_AM_64KB 0xFFFF0000 -#define OR_AM_128KB 0xFFFE0000 -#define OR_AM_256KB 0xFFFC0000 -#define OR_AM_512KB 0xFFF80000 -#define OR_AM_1MB 0xFFF00000 -#define OR_AM_2MB 0xFFE00000 -#define OR_AM_4MB 0xFFC00000 -#define OR_AM_8MB 0xFF800000 -#define OR_AM_16MB 0xFF000000 -#define OR_AM_32MB 0xFE000000 -#define OR_AM_64MB 0xFC000000 -#define OR_AM_128MB 0xF8000000 -#define OR_AM_256MB 0xF0000000 -#define OR_AM_512MB 0xE0000000 -#define OR_AM_1GB 0xC0000000 -#define OR_AM_2GB 0x80000000 -#define OR_AM_4GB 0x00000000 - -/* MxMR - UPM Machine A/B/C Mode Registers - */ -#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */ -#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */ -#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */ -#define MxMR_WLFx_1X 0x00000400 /* executed 1 time */ -#define MxMR_WLFx_2X 0x00000800 /* executed 2 times */ -#define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */ -#define MxMR_WLFx_4X 0x00001000 /* executed 4 times */ -#define MxMR_WLFx_5X 0x00001400 /* executed 5 times */ -#define MxMR_WLFx_6X 0x00001800 /* executed 6 times */ -#define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */ -#define MxMR_WLFx_8X 0x00002000 /* executed 8 times */ -#define MxMR_WLFx_9X 0x00002400 /* executed 9 times */ -#define MxMR_WLFx_10X 0x00002800 /* executed 10 times */ -#define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */ -#define MxMR_WLFx_12X 0x00003000 /* executed 12 times */ -#define MxMR_WLFx_13X 0x00003400 /* executed 13 times */ -#define MxMR_WLFx_14X 0x00003800 /* executed 14 times */ -#define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */ -#define MxMR_WLFx_16X 0x00000000 /* executed 16 times */ -#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */ -#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */ -#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */ -#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */ -#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ -#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */ -#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */ -#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */ -#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */ -#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ -#define MxMR_OP_WARR 0x10000000 /* Write to Array */ -#define MxMR_OP_RARR 0x20000000 /* Read from Array */ -#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */ -#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */ -#define MxMR_RFEN 0x40000000 /* Refresh Enable */ -#define MxMR_BSEL 0x80000000 /* Bus Select */ - -#define LBLAWAR_EN 0x80000000 -#define LBLAWAR_4KB 0x0000000B -#define LBLAWAR_8KB 0x0000000C -#define LBLAWAR_16KB 0x0000000D -#define LBLAWAR_32KB 0x0000000E -#define LBLAWAR_64KB 0x0000000F -#define LBLAWAR_128KB 0x00000010 -#define LBLAWAR_256KB 0x00000011 -#define LBLAWAR_512KB 0x00000012 -#define LBLAWAR_1MB 0x00000013 -#define LBLAWAR_2MB 0x00000014 -#define LBLAWAR_4MB 0x00000015 -#define LBLAWAR_8MB 0x00000016 -#define LBLAWAR_16MB 0x00000017 -#define LBLAWAR_32MB 0x00000018 -#define LBLAWAR_64MB 0x00000019 -#define LBLAWAR_128MB 0x0000001A -#define LBLAWAR_256MB 0x0000001B -#define LBLAWAR_512MB 0x0000001C -#define LBLAWAR_1GB 0x0000001D -#define LBLAWAR_2GB 0x0000001E - -/* LBCR - Local Bus Configuration Register - */ -#define LBCR_LDIS 0x80000000 -#define LBCR_LDIS_SHIFT 31 -#define LBCR_BCTLC 0x00C00000 -#define LBCR_BCTLC_SHIFT 22 -#define LBCR_LPBSE 0x00020000 -#define LBCR_LPBSE_SHIFT 17 -#define LBCR_EPAR 0x00010000 -#define LBCR_EPAR_SHIFT 16 -#define LBCR_BMT 0x0000FF00 -#define LBCR_BMT_SHIFT 8 - -/* LCRR - Clock Ratio Register - */ -#define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 -#define LCRR_BUFCMDC 0x30000000 -#define LCRR_BUFCMDC_SHIFT 28 -#define LCRR_BUFCMDC_1 0x10000000 -#define LCRR_BUFCMDC_2 0x20000000 -#define LCRR_BUFCMDC_3 0x30000000 -#define LCRR_BUFCMDC_4 0x00000000 -#define LCRR_ECL 0x03000000 -#define LCRR_ECL_SHIFT 24 -#define LCRR_ECL_4 0x00000000 -#define LCRR_ECL_5 0x01000000 -#define LCRR_ECL_6 0x02000000 -#define LCRR_ECL_7 0x03000000 -#define LCRR_EADC 0x00030000 -#define LCRR_EADC_SHIFT 16 -#define LCRR_EADC_1 0x00010000 -#define LCRR_EADC_2 0x00020000 -#define LCRR_EADC_3 0x00030000 -#define LCRR_EADC_4 0x00000000 -/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit - * should always be zero on older parts that have a four bit CLKDIV. - */ -#define LCRR_CLKDIV 0x0000001F -#define LCRR_CLKDIV_SHIFT 0 -#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \ - defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \ - defined(CONFIG_MPC8560) -#define LCRR_CLKDIV_2 0x00000002 -#define LCRR_CLKDIV_4 0x00000004 -#define LCRR_CLKDIV_8 0x00000008 -#elif defined(CONFIG_FSL_CORENET) -#define LCRR_CLKDIV_8 0x00000002 -#define LCRR_CLKDIV_16 0x00000004 -#define LCRR_CLKDIV_32 0x00000008 -#else -#define LCRR_CLKDIV_4 0x00000002 -#define LCRR_CLKDIV_8 0x00000004 -#define LCRR_CLKDIV_16 0x00000008 -#endif - -/* LTEDR - Transfer Error Check Disable Register - */ -#define LTEDR_BMD 0x80000000 /* Bus monitor disable */ -#define LTEDR_PARD 0x20000000 /* Parity error checking disabled */ -#define LTEDR_WPD 0x04000000 /* Write protect error checking diable */ -#define LTEDR_WARA 0x00800000 /* Write-after-read-atomic error checking diable */ -#define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */ -#define LTEDR_CSD 0x00080000 /* Chip select error checking disable */ - -/* FMR - Flash Mode Register - */ -#define FMR_CWTO 0x0000F000 -#define FMR_CWTO_SHIFT 12 -#define FMR_BOOT 0x00000800 -#define FMR_ECCM 0x00000100 -#define FMR_AL 0x00000030 -#define FMR_AL_SHIFT 4 -#define FMR_OP 0x00000003 -#define FMR_OP_SHIFT 0 - -/* FIR - Flash Instruction Register - */ -#define FIR_OP0 0xF0000000 -#define FIR_OP0_SHIFT 28 -#define FIR_OP1 0x0F000000 -#define FIR_OP1_SHIFT 24 -#define FIR_OP2 0x00F00000 -#define FIR_OP2_SHIFT 20 -#define FIR_OP3 0x000F0000 -#define FIR_OP3_SHIFT 16 -#define FIR_OP4 0x0000F000 -#define FIR_OP4_SHIFT 12 -#define FIR_OP5 0x00000F00 -#define FIR_OP5_SHIFT 8 -#define FIR_OP6 0x000000F0 -#define FIR_OP6_SHIFT 4 -#define FIR_OP7 0x0000000F -#define FIR_OP7_SHIFT 0 -#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ -#define FIR_OP_CA 0x1 /* Issue current column address */ -#define FIR_OP_PA 0x2 /* Issue current block+page address */ -#define FIR_OP_UA 0x3 /* Issue user defined address */ -#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ -#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ -#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ -#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ -#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ -#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ -#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ -#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ -#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ -#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ -#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ -#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ - -/* FCR - Flash Command Register - */ -#define FCR_CMD0 0xFF000000 -#define FCR_CMD0_SHIFT 24 -#define FCR_CMD1 0x00FF0000 -#define FCR_CMD1_SHIFT 16 -#define FCR_CMD2 0x0000FF00 -#define FCR_CMD2_SHIFT 8 -#define FCR_CMD3 0x000000FF -#define FCR_CMD3_SHIFT 0 -/* FBAR - Flash Block Address Register - */ -#define FBAR_BLK 0x00FFFFFF - -/* FPAR - Flash Page Address Register - */ -#define FPAR_SP_PI 0x00007C00 -#define FPAR_SP_PI_SHIFT 10 -#define FPAR_SP_MS 0x00000200 -#define FPAR_SP_CI 0x000001FF -#define FPAR_SP_CI_SHIFT 0 -#define FPAR_LP_PI 0x0003F000 -#define FPAR_LP_PI_SHIFT 12 -#define FPAR_LP_MS 0x00000800 -#define FPAR_LP_CI 0x000007FF -#define FPAR_LP_CI_SHIFT 0 - -/* LSDMR - SDRAM Machine Mode Register - */ -#define LSDMR_RFEN (1 << (31 - 1)) -#define LSDMR_BSMA1516 (3 << (31 - 10)) -#define LSDMR_BSMA1617 (4 << (31 - 10)) -#define LSDMR_RFCR5 (3 << (31 - 16)) -#define LSDMR_RFCR16 (7 << (31 - 16)) -#define LSDMR_PRETOACT3 (3 << (31 - 19)) -#define LSDMR_PRETOACT7 (7 << (31 - 19)) -#define LSDMR_ACTTORW3 (3 << (31 - 22)) -#define LSDMR_ACTTORW7 (7 << (31 - 22)) -#define LSDMR_ACTTORW6 (6 << (31 - 22)) -#define LSDMR_BL8 (1 << (31 - 23)) -#define LSDMR_WRC2 (2 << (31 - 27)) -#define LSDMR_WRC4 (0 << (31 - 27)) -#define LSDMR_BUFCMD (1 << (31 - 29)) -#define LSDMR_CL3 (3 << (31 - 31)) - -#define LSDMR_OP_NORMAL (0 << (31 - 4)) -#define LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define LSDMR_OP_MRW (3 << (31 - 4)) -#define LSDMR_OP_PRECH (4 << (31 - 4)) -#define LSDMR_OP_PCHALL (5 << (31 - 4)) -#define LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define LSDMR_OP_RWINV (7 << (31 - 4)) - -/* LTESR - Transfer Error Status Register - */ -#define LTESR_BM 0x80000000 -#define LTESR_FCT 0x40000000 -#define LTESR_PAR 0x20000000 -#define LTESR_WP 0x04000000 -#define LTESR_ATMW 0x00800000 -#define LTESR_ATMR 0x00400000 -#define LTESR_CS 0x00080000 -#define LTESR_CC 0x00000001 - -#ifndef __ASSEMBLY__ -/* - * Local Bus Controller Registers. - */ -typedef struct lbus_bank { - u32 br; /* Base Register */ - u32 or; /* Option Register */ -} lbus_bank_t; - -typedef struct fsl_lbus { - lbus_bank_t bank[8]; - u8 res0[0x28]; - u32 mar; /* UPM Address Register */ - u8 res1[0x4]; - u32 mamr; /* UPMA Mode Register */ - u32 mbmr; /* UPMB Mode Register */ - u32 mcmr; /* UPMC Mode Register */ - u8 res2[0x8]; - u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ - u32 mdr; /* UPM Data Register */ - u8 res3[0x4]; - u32 lsor; /* Special Operation Initiation Register */ - u32 lsdmr; /* SDRAM Mode Register */ - u8 res4[0x8]; - u32 lurt; /* UPM Refresh Timer */ - u32 lsrt; /* SDRAM Refresh Timer */ - u8 res5[0x8]; - u32 ltesr; /* Transfer Error Status Register */ - u32 ltedr; /* Transfer Error Disable Register */ - u32 lteir; /* Transfer Error Interrupt Register */ - u32 lteatr; /* Transfer Error Attributes Register */ - u32 ltear; /* Transfer Error Address Register */ - u8 res6[0xC]; - u32 lbcr; /* Configuration Register */ - u32 lcrr; /* Clock Ratio Register */ - u8 res7[0x8]; - u32 fmr; /* Flash Mode Register */ - u32 fir; /* Flash Instruction Register */ - u32 fcr; /* Flash Command Register */ - u32 fbar; /* Flash Block Addr Register */ - u32 fpar; /* Flash Page Addr Register */ - u32 fbcr; /* Flash Byte Count Register */ - u8 res8[0xF08]; -} fsl_lbus_t; -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_PPC_FSL_LBC_H */ diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h deleted file mode 100644 index db61e7e..0000000 --- a/include/asm-ppc/fsl_pci.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright 2007,2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __FSL_PCI_H_ -#define __FSL_PCI_H_ - -#include - -int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel); - -int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); -int fsl_is_pci_agent(struct pci_controller *hose); -void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); -void fsl_pci_config_unlock(struct pci_controller *hose); -void ft_fsl_pci_setup(void *blob, const char *pci_alias, - struct pci_controller *hose); - -/* - * Common PCI/PCIE Register structure for mpc85xx and mpc86xx - */ - -/* - * PCI Translation Registers - */ -typedef struct pci_outbound_window { - u32 potar; /* 0x00 - Address */ - u32 potear; /* 0x04 - Address Extended */ - u32 powbar; /* 0x08 - Window Base Address */ - u32 res1; - u32 powar; /* 0x10 - Window Attributes */ -#define POWAR_EN 0x80000000 -#define POWAR_IO_READ 0x00080000 -#define POWAR_MEM_READ 0x00040000 -#define POWAR_IO_WRITE 0x00008000 -#define POWAR_MEM_WRITE 0x00004000 - u32 res2[3]; -} pot_t; - -typedef struct pci_inbound_window { - u32 pitar; /* 0x00 - Address */ - u32 res1; - u32 piwbar; /* 0x08 - Window Base Address */ - u32 piwbear; /* 0x0c - Window Base Address Extended */ - u32 piwar; /* 0x10 - Window Attributes */ -#define PIWAR_EN 0x80000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_LOCAL 0x00f00000 -#define PIWAR_READ_SNOOP 0x00050000 -#define PIWAR_WRITE_SNOOP 0x00005000 - u32 res2[3]; -} pit_t; - -/* PCI/PCI Express Registers */ -typedef struct ccsr_pci { - u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */ - u32 cfg_data; /* 0x004 - PCI Configuration Data Register */ - u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */ - u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ - u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ - u32 config; /* 0x014 - PCIE CONFIG Register */ - char res2[8]; - u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ - u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ - u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ - u32 pm_command; /* 0x02c - PCIE PM Command register */ - char res4[3016]; /* (- #xbf8 #x30)3016 */ - u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ - u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ - - pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ - u32 res5[64]; - pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ -#define PIT3 0 -#define PIT2 1 -#define PIT1 2 - -#if 0 - u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */ - u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */ - char res5[8]; - u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */ - char res6[12]; - u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */ - u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */ - u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */ - char res7[4]; - u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */ - char res8[12]; - u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */ - u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */ - u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */ - char res9[4]; - u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */ - char res10[12]; - u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */ - u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */ - u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */ - char res11[4]; - u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */ - char res12[12]; - u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */ - u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */ - u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */ - char res13[4]; - u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */ - char res14[268]; - u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */ - char res15[4]; - u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */ - u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */ - u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */ - char res16[12]; - u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */ - char res17[4]; - u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */ - u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */ - u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */ - char res18[12]; - u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */ - char res19[4]; - u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */ - char res20[4]; - u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */ - char res21[12]; -#endif - u32 pedr; /* 0xe00 - PCI Error Detect Register */ - u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */ - u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */ - u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */ - u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */ -/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */ - u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */ - u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */ - u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */ - u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */ -/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */ - char res22[4]; - u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */ - u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ - u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ - u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ - char res23[200]; - u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ - char res24[252]; -} ccsr_fsl_pci_t; - -struct fsl_pci_info { - unsigned long regs; - pci_addr_t mem_bus; - phys_size_t mem_phys; - pci_size_t mem_size; - pci_addr_t io_bus; - phys_size_t io_phys; - pci_size_t io_size; - int pci_num; -}; - -int fsl_pci_init_port(struct fsl_pci_info *pci_info, - struct pci_controller *hose, int busno); - -#define SET_STD_PCI_INFO(x, num) \ -{ \ - x.regs = CONFIG_SYS_PCI##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ - x.pci_num = num; \ -} - -#define SET_STD_PCIE_INFO(x, num) \ -{ \ - x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ - x.pci_num = num; \ -} - -#endif diff --git a/include/asm-ppc/fsl_serdes.h b/include/asm-ppc/fsl_serdes.h deleted file mode 100644 index 6da4b6f..0000000 --- a/include/asm-ppc/fsl_serdes.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __FSL_SERDES_H -#define __FSL_SERDES_H - -#include - -#define FSL_SERDES_CLK_100 (0 << 28) -#define FSL_SERDES_CLK_125 (1 << 28) -#define FSL_SERDES_CLK_150 (3 << 28) -#define FSL_SERDES_PROTO_SATA 0 -#define FSL_SERDES_PROTO_PEX 1 -#define FSL_SERDES_PROTO_PEX_X2 2 -#define FSL_SERDES_PROTO_SGMII 3 -#define FSL_SERDES_VDD_1V 1 - -#ifdef CONFIG_FSL_SERDES -extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd); -#else -static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {} -#endif /* CONFIG_FSL_SERDES */ - -#endif /* __FSL_SERDES_H */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h deleted file mode 100644 index d3dd44e..0000000 --- a/include/asm-ppc/global_data.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H - -#include "config.h" -#include "asm/types.h" - -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long bus_clk; -#if defined(CONFIG_8xx) - unsigned long brg_clk; -#endif -#if defined(CONFIG_CPM2) - /* There are many clocks on the MPC8260 - see page 9-5 */ - unsigned long vco_out; - unsigned long cpm_clk; - unsigned long scc_clk; - unsigned long brg_clk; -#ifdef CONFIG_PCI - unsigned long pci_clk; -#endif -#endif - unsigned long mem_clk; -#if defined(CONFIG_MPC83xx) - /* There are other clocks in the MPC83XX */ - u32 csb_clk; -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) - u32 tsec1_clk; - u32 tsec2_clk; - u32 usbdr_clk; -#endif -#if defined (CONFIG_MPC834x) - u32 usbmph_clk; -#endif /* CONFIG_MPC834x */ -#if defined(CONFIG_MPC8315) - u32 tdm_clk; -#endif - u32 core_clk; - u32 enc_clk; - u32 lbiu_clk; - u32 lclk_clk; - u32 pci_clk; -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x) - u32 pciexp1_clk; - u32 pciexp2_clk; -#endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) - u32 sata_clk; -#endif -#if defined(CONFIG_MPC8360) - u32 mem_sec_clk; -#endif /* CONFIG_MPC8360 */ -#endif -#if defined(CONFIG_FSL_ESDHC) - u32 sdhc_clk; -#endif -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) - u32 lbc_clk; - void *cpu; -#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */ -#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) - u32 i2c1_clk; - u32 i2c2_clk; -#endif -#if defined(CONFIG_QE) - u32 qe_clk; - u32 brg_clk; - uint mp_alloc_base; - uint mp_alloc_top; -#endif /* CONFIG_QE */ -#if defined(CONFIG_FSL_LAW) - u32 used_laws; -#endif -#if defined(CONFIG_E500) - u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32]; -#endif -#if defined(CONFIG_MPC5xxx) - unsigned long ipb_clk; - unsigned long pci_clk; -#endif -#if defined(CONFIG_MPC512X) - u32 ips_clk; - u32 csb_clk; - u32 pci_clk; -#endif /* CONFIG_MPC512X */ -#if defined(CONFIG_MPC8220) - unsigned long bExtUart; - unsigned long inp_clk; - unsigned long pci_clk; - unsigned long vco_clk; - unsigned long pev_clk; - unsigned long flb_clk; -#endif - phys_size_t ram_size; /* RAM size */ - unsigned long reset_status; /* reset status register at boot */ -#if defined(CONFIG_MPC83xx) - unsigned long arbiter_event_attributes; - unsigned long arbiter_event_address; -#endif - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long have_console; /* serial_init() was called */ -#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2) - unsigned int dp_alloc_base; - unsigned int dp_alloc_top; -#endif -#if defined(CONFIG_4xx) - u32 uart_clk; -#endif /* CONFIG_4xx */ -#if defined(CONFIG_SYS_GT_6426x) - unsigned int mirror_hack[16]; -#endif -#if defined(CONFIG_A3000) || \ - defined(CONFIG_HIDDEN_DRAGON) || \ - defined(CONFIG_MUSENKI) || \ - defined(CONFIG_SANDPOINT) - void * console_addr; -#endif - unsigned long relocaddr; /* Start address of U-Boot in RAM */ -#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) - unsigned long fb_base; /* Base address of framebuffer memory */ -#endif -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - unsigned long post_log_word; /* Record POST activities */ - unsigned long post_init_f_time; /* When post_init_f started */ -#endif -#ifdef CONFIG_BOARD_TYPES - unsigned long board_type; -#endif -#ifdef CONFIG_MODEM_SUPPORT - unsigned long do_mdm_init; - unsigned long be_quiet; -#endif -#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5) - unsigned long kbd_status; -#endif -#if defined(CONFIG_WD_MAX_RATE) - unsigned long long wdt_last; /* trace watch-dog triggering rate */ -#endif - void **jt; /* jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#if 1 -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") -#else /* We could use plain global data, but the resulting code is bigger */ -#define XTRN_DECLARE_GLOBAL_DATA_PTR extern -#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \ - gd_t *gd -#endif - -#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h deleted file mode 100644 index 23e29b1..0000000 --- a/include/asm-ppc/gpio.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_PPC_GPIO_H -#define __ASM_PPC_GPIO_H - -#include - -/* 4xx PPC's have 2 GPIO controllers */ -#if defined(CONFIG_405EZ) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define GPIO_GROUP_MAX 2 -#else -#define GPIO_GROUP_MAX 1 -#endif - -/* GPIO controller */ -struct ppc4xx_gpio { - u32 or; /* Output Control */ - u32 tcr; /* Tri-State Control */ - u32 osl; /* Output Select 16..31 */ - u32 osh; /* Output Select 0..15 */ - u32 tsl; /* Tri-State Select 16..31 */ - u32 tsh; /* Tri-State Select 0..15 */ - u32 odr; /* Open Drain */ - u32 ir; /* Input */ - u32 rr1; /* Receive Register 1 */ - u32 rr2; /* Receive Register 2 */ - u32 rr3; /* Receive Register 3 */ - u32 reserved; - u32 is1l; /* Input Select 1 16..31 */ - u32 is1h; /* Input Select 1 0..15 */ - u32 is2l; /* Input Select 2 16..31 */ - u32 is2h; /* Input Select 2 0..15 */ - u32 is3l; /* Input Select 3 16..31 */ - u32 is3h; /* Input Select 3 0..15 */ -}; - -/* Offsets */ -#define GPIOx_OR 0x00 /* GPIO Output Register */ -#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ -#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ -#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ -#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ -#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ -#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ -#define GPIOx_IR 0x1C /* GPIO Input Register */ -#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ -#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ -#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ -#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ -#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ -#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ -#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ -#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ -#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ - -#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */ -#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */ -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */ -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ -#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ -#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ - -#define GPIO0 0 -#define GPIO1 1 - -#define GPIO_MAX 32 -#define GPIO_ALT1_SEL 0x40000000 -#define GPIO_ALT2_SEL 0x80000000 -#define GPIO_ALT3_SEL 0xc0000000 -#define GPIO_IN_SEL 0x40000000 -#define GPIO_MASK 0xc0000000 - -#define GPIO_VAL(gpio) (0x80000000 >> (gpio)) - -#ifndef __ASSEMBLY__ -typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; -typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; -typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t; - -typedef struct { - unsigned long add; /* gpio core base address */ - gpio_driver_t in_out; /* Driver Setting */ - gpio_select_t alt_nb; /* Selected Alternate */ - gpio_out_t out_val;/* Default Output Value */ -} gpio_param_s; -#endif - -void gpio_config(int pin, int in_out, int gpio_alt, int out_val); -void gpio_write_bit(int pin, int val); -int gpio_read_out_bit(int pin); -int gpio_read_in_bit(int pin); -void gpio_set_chip_configuration(void); - -#endif /* __ASM_PPC_GPIO_H */ diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h deleted file mode 100644 index 95350fd..0000000 --- a/include/asm-ppc/immap_512x.h +++ /dev/null @@ -1,1246 +0,0 @@ -/* - * (C) Copyright 2007-2009 DENX Software Engineering - * - * MPC512x Internal Memory Map - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Based on the MPC83xx header. - */ - -#ifndef __IMMAP_512x__ -#define __IMMAP_512x__ - -#include -#if defined(CONFIG_E300) -#include -#endif - -/* - * System reset offset (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 -#define _START_OFFSET EXC_OFF_SYS_RESET - -#define SPR_5121E 0x80180000 - -/* - * IMMRBAR - Internal Memory Register Base Address - */ -#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ -#define IMMRBAR 0x0000 /* Register offset to immr */ -#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ -#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) - - -#ifndef __ASSEMBLY__ -typedef struct law512x { - u32 bar; /* Base Addr Register */ - u32 ar; /* Attributes Register */ -} law512x_t; - -/* - * System configuration registers - */ -typedef struct sysconf512x { - u32 immrbar; /* Internal memory map base address register */ - u8 res0[0x1c]; - u32 lpbaw; /* LP Boot Access Window */ - u32 lpcs0aw; /* LP CS0 Access Window */ - u32 lpcs1aw; /* LP CS1 Access Window */ - u32 lpcs2aw; /* LP CS2 Access Window */ - u32 lpcs3aw; /* LP CS3 Access Window */ - u32 lpcs4aw; /* LP CS4 Access Window */ - u32 lpcs5aw; /* LP CS5 Access Window */ - u32 lpcs6aw; /* LP CS6 Access Window */ - u32 lpcs7aw; /* LP CS7 Access Window */ - u8 res1[0x1c]; - law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ - u8 res2[0x28]; - law512x_t ddrlaw; /* DDR Local Access Window */ - u8 res3[0x18]; - u32 mbxbar; /* MBX Base Address */ - u32 srambar; /* SRAM Base Address */ - u32 nfcbar; /* NFC Base Address */ - u8 res4[0x34]; - u32 spridr; /* System Part and Revision ID Register */ - u32 spcr; /* System Priority Configuration Register */ - u8 res5[0xf8]; -} sysconf512x_t; - -#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ - -/* - * Watch Dog Timer (WDT) Registers - */ -typedef struct wdt512x { - u8 res0[4]; - u32 swcrr; /* System watchdog control register */ - u32 swcnr; /* System watchdog count register */ - u8 res1[2]; - u16 swsrr; /* System watchdog service register */ - u8 res2[0xF0]; -} wdt512x_t; - -/* - * RTC Module Registers - */ -typedef struct rtclk512x { - u8 fixme[0x100]; -} rtclk512x_t; - -/* - * General Purpose Timer - */ -typedef struct gpt512x { - u8 fixme[0x100]; -} gpt512x_t; - -/* - * Integrated Programmable Interrupt Controller - */ -typedef struct ipic512x { - u8 fixme[0x100]; -} ipic512x_t; - -/* - * System Arbiter Registers - */ -typedef struct arbiter512x { - u32 acr; /* Arbiter Configuration Register */ - u32 atr; /* Arbiter Timers Register */ - u32 ater; /* Arbiter Transfer Error Register */ - u32 aer; /* Arbiter Event Register */ - u32 aidr; /* Arbiter Interrupt Definition Register */ - u32 amr; /* Arbiter Mask Register */ - u32 aeatr; /* Arbiter Event Attributes Register */ - u32 aeadr; /* Arbiter Event Address Register */ - u32 aerr; /* Arbiter Event Response Register */ - u8 res1[0xDC]; -} arbiter512x_t; - -/* - * Reset Module - */ -typedef struct reset512x { - u32 rcwl; /* Reset Configuration Word Low Register */ - u32 rcwh; /* Reset Configuration Word High Register */ - u8 res0[8]; - u32 rsr; /* Reset Status Register */ - u32 rmr; /* Reset Mode Register */ - u32 rpr; /* Reset protection Register */ - u32 rcr; /* Reset Control Register */ - u32 rcer; /* Reset Control Enable Register */ - u8 res1[0xDC]; -} reset512x_t; - -/* RSR - Reset Status Register */ -#define RSR_SWSR 0x00002000 /* software soft reset */ -#define RSR_SWHR 0x00001000 /* software hard reset */ -#define RSR_JHRS 0x00000200 /* jtag hreset */ -#define RSR_JSRS 0x00000100 /* jtag sreset status */ -#define RSR_CSHR 0x00000010 /* checkstop reset status */ -#define RSR_SWRS 0x00000008 /* software watchdog reset status */ -#define RSR_BMRS 0x00000004 /* bus monitop reset status */ -#define RSR_SRS 0x00000002 /* soft reset status */ -#define RSR_HRS 0x00000001 /* hard reset status */ -#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\ - RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ - RSR_BMRS | RSR_SRS | RSR_HRS) - -/* RMR - Reset Mode Register */ -#define RMR_CSRE 0x00000001 /* checkstop reset enable */ -#define RMR_CSRE_SHIFT 0 -#define RMR_RES (~(RMR_CSRE)) - -/* RCR - Reset Control Register */ -#define RCR_SWHR 0x00000002 /* software hard reset */ -#define RCR_SWSR 0x00000001 /* software soft reset */ -#define RCR_RES (~(RCR_SWHR | RCR_SWSR)) - -/* RCER - Reset Control Enable Register */ -#define RCER_CRE 0x00000001 /* software hard reset */ -#define RCER_RES (~(RCER_CRE)) - -/* - * Clock Module - */ -typedef struct clk512x { - u32 spmr; /* System PLL Mode Register */ - u32 sccr[2]; /* System Clock Control Registers */ - u32 scfr[2]; /* System Clock Frequency Registers */ - u8 res0[4]; - u32 bcr; /* Bread Crumb Register */ - u32 pscccr[12]; /* PSC0-11 Clock Control Registers */ - u32 spccr; /* SPDIF Clock Control Register */ - u32 cccr; /* CFM Clock Control Register */ - u32 dccr; /* DIU Clock Control Register */ - u32 msccr[4]; /* MSCAN1-4 Clock Control Registers */ - u8 res1[0x98]; -} clk512x_t; - -/* SPMR - System PLL Mode Register */ -#define SPMR_SPMF 0x0F000000 -#define SPMR_SPMF_SHIFT 24 -#define SPMR_CPMF 0x000F0000 -#define SPMR_CPMF_SHIFT 16 - -/* System Clock Control Register 1 commands */ -#define CLOCK_SCCR1_CFG_EN 0x80000000 -#define CLOCK_SCCR1_LPC_EN 0x40000000 -#define CLOCK_SCCR1_NFC_EN 0x20000000 -#define CLOCK_SCCR1_PATA_EN 0x10000000 -#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) -#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 -#define CLOCK_SCCR1_SATA_EN 0x00004000 -#define CLOCK_SCCR1_FEC_EN 0x00002000 -#define CLOCK_SCCR1_TPR_EN 0x00001000 -#define CLOCK_SCCR1_PCI_EN 0x00000800 -#define CLOCK_SCCR1_DDR_EN 0x00000400 - -/* System Clock Control Register 2 commands */ -#define CLOCK_SCCR2_DIU_EN 0x80000000 -#define CLOCK_SCCR2_AXE_EN 0x40000000 -#define CLOCK_SCCR2_MEM_EN 0x20000000 -#define CLOCK_SCCR2_USB1_EN 0x10000000 -#define CLOCK_SCCR2_USB2_EN 0x08000000 -#define CLOCK_SCCR2_I2C_EN 0x04000000 -#define CLOCK_SCCR2_BDLC_EN 0x02000000 -#define CLOCK_SCCR2_SDHC_EN 0x01000000 -#define CLOCK_SCCR2_SPDIF_EN 0x00800000 -#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 -#define CLOCK_SCCR2_MBX_EN 0x00200000 -#define CLOCK_SCCR2_MBX_3D_EN 0x00100000 -#define CLOCK_SCCR2_IIM_EN 0x00080000 - -/* SCFR1 System Clock Frequency Register 1 */ -#define SCFR1_IPS_DIV 0x3 -#define SCFR1_IPS_DIV_MASK 0x03800000 -#define SCFR1_IPS_DIV_SHIFT 23 - -#define SCFR1_PCI_DIV 0x6 -#define SCFR1_PCI_DIV_MASK 0x00700000 -#define SCFR1_PCI_DIV_SHIFT 20 - -#define SCFR1_LPC_DIV_MASK 0x00003800 -#define SCFR1_LPC_DIV_SHIFT 11 - -/* SCFR2 System Clock Frequency Register 2 */ -#define SCFR2_SYS_DIV 0xFC000000 -#define SCFR2_SYS_DIV_SHIFT 26 - -/* SPCR - System Priority Configuration Register */ -#define SPCR_TBEN 0x00400000 /* E300 core time base unit enable */ - -/* - * Power Management Control Module - */ -typedef struct pmc512x { - u8 fixme[0x100]; -} pmc512x_t; - -/* - * General purpose I/O module - */ -typedef struct gpio512x { - u32 gpdir; - u32 gpodr; - u32 gpdat; - u32 gpier; - u32 gpimr; - u32 gpicr1; - u32 gpicr2; - u8 res0[0xE4]; -} gpio512x_t; - -/* - * DDR Memory Controller Memory Map - */ -typedef struct ddr512x { - u32 ddr_sys_config; /* System Configuration Register */ - u32 ddr_time_config0; /* Timing Configuration Register */ - u32 ddr_time_config1; /* Timing Configuration Register */ - u32 ddr_time_config2; /* Timing Configuration Register */ - u32 ddr_command; /* Command Register */ - u32 ddr_compact_command; /* Compact Command Register */ - u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ - u32 DQS_config_offset_count; /* DQS Config Offset Count */ - u32 DQS_config_offset_time; /* DQS Config Offset Time */ - u32 DQS_delay_status; /* DQS Delay Status */ - u32 res0[0xF]; - u32 prioman_config1; /* Priority Manager Configuration */ - u32 prioman_config2; /* Priority Manager Configuration */ - u32 hiprio_config; /* High Priority Configuration */ - u32 lut_table0_main_upper; /* LUT0 Main Upper */ - u32 lut_table1_main_upper; /* LUT1 Main Upper */ - u32 lut_table2_main_upper; /* LUT2 Main Upper */ - u32 lut_table3_main_upper; /* LUT3 Main Upper */ - u32 lut_table4_main_upper; /* LUT4 Main Upper */ - u32 lut_table0_main_lower; /* LUT0 Main Lower */ - u32 lut_table1_main_lower; /* LUT1 Main Lower */ - u32 lut_table2_main_lower; /* LUT2 Main Lower */ - u32 lut_table3_main_lower; /* LUT3 Main Lower */ - u32 lut_table4_main_lower; /* LUT4 Main Lower */ - u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */ - u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */ - u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */ - u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */ - u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */ - u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */ - u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */ - u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */ - u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */ - u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */ - u32 performance_monitor_config; - u32 event_time_counter; - u32 event_time_preset; - u32 performance_monitor1_address_low; - u32 performance_monitor2_address_low; - u32 performance_monitor1_address_hi; - u32 performance_monitor2_address_hi; - u32 res1[2]; - u32 performance_monitor1_read_counter; - u32 performance_monitor2_read_counter; - u32 performance_monitor1_write_counter; - u32 performance_monitor2_write_counter; - u32 granted_ack_counter0; - u32 granted_ack_counter1; - u32 granted_ack_counter2; - u32 granted_ack_counter3; - u32 granted_ack_counter4; - u32 cumulative_wait_counter0; - u32 cumulative_wait_counter1; - u32 cumulative_wait_counter2; - u32 cumulative_wait_counter3; - u32 cumulative_wait_counter4; - u32 summed_priority_counter0; - u32 summed_priority_counter1; - u32 summed_priority_counter2; - u32 summed_priority_counter3; - u32 summed_priority_counter4; - u32 res2[0x3AD]; -} ddr512x_t; - -/* MDDRC SYS CFG and Timing CFG0 Registers */ -#define MDDRC_SYS_CFG_EN 0xF0000000 -#define MDDRC_SYS_CFG_CMD_MASK 0x10000000 -#define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF - -/* - * DDR Memory Controller Configuration settings - */ -typedef struct ddr512x_config { - u32 ddr_sys_config; /* System Configuration Register */ - u32 ddr_time_config0; /* Timing Configuration Register */ - u32 ddr_time_config1; /* Timing Configuration Register */ - u32 ddr_time_config2; /* Timing Configuration Register */ -} ddr512x_config_t; - -/* - * DMA/Messaging Unit - */ -typedef struct dma512x { - u8 fixme[0x1800]; -} dma512x_t; - -/* - * PCI Software Configuration Registers - */ -typedef struct pciconf512x { - u32 config_address; - u32 config_data; - u32 int_ack; - u8 res[116]; -} pciconf512x_t; - -/* - * PCI Outbound Translation Register - */ -typedef struct pci_outbound_window { - u32 potar; - u8 res0[4]; - u32 pobar; - u8 res1[4]; - u32 pocmr; - u8 res2[4]; -} pot512x_t; - -/* POTAR - PCI Outbound Translation Address Register */ -#define POTAR_TA_MASK 0x000fffff - -/* POBAR - PCI Outbound Base Address Register */ -#define POBAR_BA_MASK 0x000fffff - -/* POCMR - PCI Outbound Comparision Mask Register */ -#define POCMR_EN 0x80000000 -#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ -#define POCMR_PRE 0x20000000 /* prefetch enable */ -#define POCMR_SBS 0x00100000 /* special byte swap enable */ -#define POCMR_CM_MASK 0x000fffff -#define POCMR_CM_4G 0x00000000 -#define POCMR_CM_2G 0x00080000 -#define POCMR_CM_1G 0x000C0000 -#define POCMR_CM_512M 0x000E0000 -#define POCMR_CM_256M 0x000F0000 -#define POCMR_CM_128M 0x000F8000 -#define POCMR_CM_64M 0x000FC000 -#define POCMR_CM_32M 0x000FE000 -#define POCMR_CM_16M 0x000FF000 -#define POCMR_CM_8M 0x000FF800 -#define POCMR_CM_4M 0x000FFC00 -#define POCMR_CM_2M 0x000FFE00 -#define POCMR_CM_1M 0x000FFF00 -#define POCMR_CM_512K 0x000FFF80 -#define POCMR_CM_256K 0x000FFFC0 -#define POCMR_CM_128K 0x000FFFE0 -#define POCMR_CM_64K 0x000FFFF0 -#define POCMR_CM_32K 0x000FFFF8 -#define POCMR_CM_16K 0x000FFFFC -#define POCMR_CM_8K 0x000FFFFE -#define POCMR_CM_4K 0x000FFFFF - -/* - * Sequencer - */ -typedef struct ios512x { - pot512x_t pot[6]; - u8 res0[0x60]; - u32 pmcr; - u8 res1[4]; - u32 dtcr; - u8 res2[4]; -} ios512x_t; - -/* - * PCI Controller - */ -typedef struct pcictrl512x { - u32 esr; - u32 ecdr; - u32 eer; - u32 eatcr; - u32 eacr; - u32 eeacr; - u32 edlcr; - u32 edhcr; - u32 gcr; - u32 ecr; - u32 gsr; - u8 res0[12]; - u32 pitar2; - u8 res1[4]; - u32 pibar2; - u32 piebar2; - u32 piwar2; - u8 res2[4]; - u32 pitar1; - u8 res3[4]; - u32 pibar1; - u32 piebar1; - u32 piwar1; - u8 res4[4]; - u32 pitar0; - u8 res5[4]; - u32 pibar0; - u8 res6[4]; - u32 piwar0; - u8 res7[132]; -} pcictrl512x_t; - - -/* PITAR - PCI Inbound Translation Address Register - */ -#define PITAR_TA_MASK 0x000fffff - -/* PIBAR - PCI Inbound Base/Extended Address Register - */ -#define PIBAR_MASK 0xffffffff -#define PIEBAR_EBA_MASK 0x000fffff - -/* PIWAR - PCI Inbound Windows Attributes Register - */ -#define PIWAR_EN 0x80000000 -#define PIWAR_SBS 0x40000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_RTT_MASK 0x000f0000 -#define PIWAR_RTT_NO_SNOOP 0x00040000 -#define PIWAR_RTT_SNOOP 0x00050000 -#define PIWAR_WTT_MASK 0x0000f000 -#define PIWAR_WTT_NO_SNOOP 0x00004000 -#define PIWAR_WTT_SNOOP 0x00005000 - -/* - * MSCAN - */ -typedef struct mscan512x { - u8 fixme[0x100]; -} mscan512x_t; - -/* - * BDLC - */ -typedef struct bdlc512x { - u8 fixme[0x100]; -} bdlc512x_t; - -/* - * SDHC - */ -typedef struct sdhc512x { - u8 fixme[0x100]; -} sdhc512x_t; - -/* - * SPDIF - */ -typedef struct spdif512x { - u8 fixme[0x100]; -} spdif512x_t; - -/* - * I2C - */ -typedef struct i2c512x_dev { - volatile u32 madr; /* I2Cn + 0x00 */ - volatile u32 mfdr; /* I2Cn + 0x04 */ - volatile u32 mcr; /* I2Cn + 0x08 */ - volatile u32 msr; /* I2Cn + 0x0C */ - volatile u32 mdr; /* I2Cn + 0x10 */ - u8 res0[0x0C]; -} i2c512x_dev_t; - -/* Number of I2C buses */ -#define I2C_BUS_CNT 3 - -typedef struct i2c512x { - i2c512x_dev_t dev[I2C_BUS_CNT]; - volatile u32 icr; - volatile u32 mifr; - u8 res0[0x98]; -} i2c512x_t; - -/* I2Cn control register bits */ -#define I2C_EN 0x80 -#define I2C_IEN 0x40 -#define I2C_STA 0x20 -#define I2C_TX 0x10 -#define I2C_TXAK 0x08 -#define I2C_RSTA 0x04 -#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) - -/* I2Cn status register bits */ -#define I2C_CF 0x80 -#define I2C_AAS 0x40 -#define I2C_BB 0x20 -#define I2C_AL 0x10 -#define I2C_SRW 0x04 -#define I2C_IF 0x02 -#define I2C_RXAK 0x01 - -/* - * AXE - */ -typedef struct axe512x { - u8 fixme[0x100]; -} axe512x_t; - -/* - * DIU - */ -typedef struct diu512x { - u8 fixme[0x100]; -} diu512x_t; - -/* - * CFM - */ -typedef struct cfm512x { - u8 fixme[0x100]; -} cfm512x_t; - -/* - * FEC - */ -typedef struct fec512x { - u32 fec_id; /* FEC_ID register */ - u32 ievent; /* Interrupt event register */ - u32 imask; /* Interrupt mask register */ - u32 reserved_01; - u32 r_des_active; /* Receive ring updated flag */ - u32 x_des_active; /* Transmit ring updated flag */ - u32 reserved_02[3]; - u32 ecntrl; /* Ethernet control register */ - u32 reserved_03[6]; - u32 mii_data; /* MII data register */ - u32 mii_speed; /* MII speed register */ - u32 reserved_04[7]; - u32 mib_control; /* MIB control/status register */ - u32 reserved_05[7]; - u32 r_cntrl; /* Receive control register */ - u32 r_hash; /* Receive hash */ - u32 reserved_06[14]; - u32 x_cntrl; /* Transmit control register */ - u32 reserved_07[7]; - u32 paddr1; /* Physical address low */ - u32 paddr2; /* Physical address high + type field */ - u32 op_pause; /* Opcode + pause duration */ - u32 reserved_08[10]; - u32 iaddr1; /* Upper 32 bits of individual hash table */ - u32 iaddr2; /* Lower 32 bits of individual hash table */ - u32 gaddr1; /* Upper 32 bits of group hash table */ - u32 gaddr2; /* Lower 32 bits of group hash table */ - u32 reserved_09[7]; - u32 x_wmrk; /* Transmit FIFO watermark */ - u32 reserved_10; - u32 r_bound; /* End of RAM */ - u32 r_fstart; /* Receive FIFO start address */ - u32 reserved_11[11]; - u32 r_des_start; /* Beginning of receive descriptor ring */ - u32 x_des_start; /* Pointer to beginning of transmit descriptor ring */ - u32 r_buff_size; /* Receive buffer size */ - u32 reserved_12[26]; - u32 dma_control; /* DMA control for IP bus, AMBA IF + DMA revision */ - u32 reserved_13[2]; - - u32 mib[128]; /* MIB Block Counters */ - - u32 fifo[256]; /* used by FEC, can only be accessed by DMA */ -} fec512x_t; - -/* - * ULPI - */ -typedef struct ulpi512x { - u8 fixme[0x600]; -} ulpi512x_t; - -/* - * UTMI - */ -typedef struct utmi512x { - u8 fixme[0x3000]; -} utmi512x_t; - -/* - * PCI DMA - */ -typedef struct pcidma512x { - u8 fixme[0x300]; -} pcidma512x_t; - -/* - * IO Control - */ -typedef struct ioctrl512x { - u32 io_control_mem; /* MEM pad ctrl reg */ - u32 io_control_gp; /* GP pad ctrl reg */ - u32 io_control_lpc_clk; /* LPC_CLK pad ctrl reg */ - u32 io_control_lpc_oe; /* LPC_OE pad ctrl reg */ - u32 io_control_lpc_rw; /* LPC_R/W pad ctrl reg */ - u32 io_control_lpc_ack; /* LPC_ACK pad ctrl reg */ - u32 io_control_lpc_cs0; /* LPC_CS0 pad ctrl reg */ - u32 io_control_nfc_ce0; /* NFC_CE0 pad ctrl reg */ - u32 io_control_lpc_cs1; /* LPC_CS1 pad ctrl reg */ - u32 io_control_lpc_cs2; /* LPC_CS2 pad ctrl reg */ - u32 io_control_lpc_ax03; /* LPC_AX03 pad ctrl reg */ - u32 io_control_emb_ax02; /* EMB_AX02 pad ctrl reg */ - u32 io_control_emb_ax01; /* EMB_AX01 pad ctrl reg */ - u32 io_control_emb_ax00; /* EMB_AX00 pad ctrl reg */ - u32 io_control_emb_ad31; /* EMB_AD31 pad ctrl reg */ - u32 io_control_emb_ad30; /* EMB_AD30 pad ctrl reg */ - u32 io_control_emb_ad29; /* EMB_AD29 pad ctrl reg */ - u32 io_control_emb_ad28; /* EMB_AD28 pad ctrl reg */ - u32 io_control_emb_ad27; /* EMB_AD27 pad ctrl reg */ - u32 io_control_emb_ad26; /* EMB_AD26 pad ctrl reg */ - u32 io_control_emb_ad25; /* EMB_AD25 pad ctrl reg */ - u32 io_control_emb_ad24; /* EMB_AD24 pad ctrl reg */ - u32 io_control_emb_ad23; /* EMB_AD23 pad ctrl reg */ - u32 io_control_emb_ad22; /* EMB_AD22 pad ctrl reg */ - u32 io_control_emb_ad21; /* EMB_AD21 pad ctrl reg */ - u32 io_control_emb_ad20; /* EMB_AD20 pad ctrl reg */ - u32 io_control_emb_ad19; /* EMB_AD19 pad ctrl reg */ - u32 io_control_emb_ad18; /* EMB_AD18 pad ctrl reg */ - u32 io_control_emb_ad17; /* EMB_AD17 pad ctrl reg */ - u32 io_control_emb_ad16; /* EMB_AD16 pad ctrl reg */ - u32 io_control_emb_ad15; /* EMB_AD15 pad ctrl reg */ - u32 io_control_emb_ad14; /* EMB_AD14 pad ctrl reg */ - u32 io_control_emb_ad13; /* EMB_AD13 pad ctrl reg */ - u32 io_control_emb_ad12; /* EMB_AD12 pad ctrl reg */ - u32 io_control_emb_ad11; /* EMB_AD11 pad ctrl reg */ - u32 io_control_emb_ad10; /* EMB_AD10 pad ctrl reg */ - u32 io_control_emb_ad09; /* EMB_AD09 pad ctrl reg */ - u32 io_control_emb_ad08; /* EMB_AD08 pad ctrl reg */ - u32 io_control_emb_ad07; /* EMB_AD07 pad ctrl reg */ - u32 io_control_emb_ad06; /* EMB_AD06 pad ctrl reg */ - u32 io_control_emb_ad05; /* EMB_AD05 pad ctrl reg */ - u32 io_control_emb_ad04; /* EMB_AD04 pad ctrl reg */ - u32 io_control_emb_ad03; /* EMB_AD03 pad ctrl reg */ - u32 io_control_emb_ad02; /* EMB_AD02 pad ctrl reg */ - u32 io_control_emb_ad01; /* EMB_AD01 pad ctrl reg */ - u32 io_control_emb_ad00; /* EMB_AD00 pad ctrl reg */ - u32 io_control_pata_ce1; /* PATA_CE1 pad ctrl reg */ - u32 io_control_pata_ce2; /* PATA_CE2 pad ctrl reg */ - u32 io_control_pata_isolate; /* PATA_ISOLATE pad ctrl reg */ - u32 io_control_pata_ior; /* PATA_IOR pad ctrl reg */ - u32 io_control_pata_iow; /* PATA_IOW pad ctrl reg */ - u32 io_control_pata_iochrdy; /* PATA_IOCHRDY pad ctrl reg */ - u32 io_control_pata_intrq; /* PATA_INTRQ pad ctrl reg */ - u32 io_control_pata_drq; /* PATA_DRQ pad ctrl reg */ - u32 io_control_pata_dack; /* PATA_DACK pad ctrl reg */ - u32 io_control_nfc_wp; /* NFC_WP pad ctrl reg */ - u32 io_control_nfc_rb; /* NFC_RB pad ctrl reg */ - u32 io_control_nfc_ale; /* NFC_ALE pad ctrl reg */ - u32 io_control_nfc_cle; /* NFC_CLE pad ctrl reg */ - u32 io_control_nfc_we; /* NFC_WE pad ctrl reg */ - u32 io_control_nfc_re; /* NFC_RE pad ctrl reg */ - u32 io_control_pci_ad31; /* PCI_AD31 pad ctrl reg */ - u32 io_control_pci_ad30; /* PCI_AD30 pad ctrl reg */ - u32 io_control_pci_ad29; /* PCI_AD29 pad ctrl reg */ - u32 io_control_pci_ad28; /* PCI_AD28 pad ctrl reg */ - u32 io_control_pci_ad27; /* PCI_AD27 pad ctrl reg */ - u32 io_control_pci_ad26; /* PCI_AD26 pad ctrl reg */ - u32 io_control_pci_ad25; /* PCI_AD25 pad ctrl reg */ - u32 io_control_pci_ad24; /* PCI_AD24 pad ctrl reg */ - u32 io_control_pci_ad23; /* PCI_AD23 pad ctrl reg */ - u32 io_control_pci_ad22; /* PCI_AD22 pad ctrl reg */ - u32 io_control_pci_ad21; /* PCI_AD21 pad ctrl reg */ - u32 io_control_pci_ad20; /* PCI_AD20 pad ctrl reg */ - u32 io_control_pci_ad19; /* PCI_AD19 pad ctrl reg */ - u32 io_control_pci_ad18; /* PCI_AD18 pad ctrl reg */ - u32 io_control_pci_ad17; /* PCI_AD17 pad ctrl reg */ - u32 io_control_pci_ad16; /* PCI_AD16 pad ctrl reg */ - u32 io_control_pci_ad15; /* PCI_AD15 pad ctrl reg */ - u32 io_control_pci_ad14; /* PCI_AD14 pad ctrl reg */ - u32 io_control_pci_ad13; /* PCI_AD13 pad ctrl reg */ - u32 io_control_pci_ad12; /* PCI_AD12 pad ctrl reg */ - u32 io_control_pci_ad11; /* PCI_AD11 pad ctrl reg */ - u32 io_control_pci_ad10; /* PCI_AD10 pad ctrl reg */ - u32 io_control_pci_ad09; /* PCI_AD09 pad ctrl reg */ - u32 io_control_pci_ad08; /* PCI_AD08 pad ctrl reg */ - u32 io_control_pci_ad07; /* PCI_AD07 pad ctrl reg */ - u32 io_control_pci_ad06; /* PCI_AD06 pad ctrl reg */ - u32 io_control_pci_ad05; /* PCI_AD05 pad ctrl reg */ - u32 io_control_pci_ad04; /* PCI_AD04 pad ctrl reg */ - u32 io_control_pci_ad03; /* PCI_AD03 pad ctrl reg */ - u32 io_control_pci_ad02; /* PCI_AD02 pad ctrl reg */ - u32 io_control_pci_ad01; /* PCI_AD01 pad ctrl reg */ - u32 io_control_pci_ad00; /* PCI_AD00 pad ctrl reg */ - u32 io_control_pci_cbe0; /* PCI_CBE0 pad ctrl reg */ - u32 io_control_pci_cbe1; /* PCI_CBE1 pad ctrl reg */ - u32 io_control_pci_cbe2; /* PCI_CBE2 pad ctrl reg */ - u32 io_control_pci_cbe3; /* PCI_CBE3 pad ctrl reg */ - u32 io_control_pci_grant2; /* PCI_GRANT2 pad ctrl reg */ - u32 io_control_pci_req2; /* PCI_REQ2 pad ctrl reg */ - u32 io_control_pci_grant1; /* PCI_GRANT1 pad ctrl reg */ - u32 io_control_pci_req1; /* PCI_REQ1 pad ctrl reg */ - u32 io_control_pci_grant0; /* PCI_GRANT0 pad ctrl reg */ - u32 io_control_pci_req0; /* PCI_REQ0 pad ctrl reg */ - u32 io_control_pci_inta; /* PCI_INTA pad ctrl reg */ - u32 io_control_pci_clk; /* PCI_CLK pad ctrl reg */ - u32 io_control_pci_rst; /* PCI_RST- pad ctrl reg */ - u32 io_control_pci_frame; /* PCI_FRAME pad ctrl reg */ - u32 io_control_pci_idsel; /* PCI_IDSEL pad ctrl reg */ - u32 io_control_pci_devsel; /* PCI_DEVSEL pad ctrl reg */ - u32 io_control_pci_irdy; /* PCI_IRDY pad ctrl reg */ - u32 io_control_pci_trdy; /* PCI_TRDY pad ctrl reg */ - u32 io_control_pci_stop; /* PCI_STOP pad ctrl reg */ - u32 io_control_pci_par; /* PCI_PAR pad ctrl reg */ - u32 io_control_pci_perr; /* PCI_PERR pad ctrl reg */ - u32 io_control_pci_serr; /* PCI_SERR pad ctrl reg */ - u32 io_control_spdif_txclk; /* SPDIF_TXCLK pad ctrl reg */ - u32 io_control_spdif_tx; /* SPDIF_TX pad ctrl reg */ - u32 io_control_spdif_rx; /* SPDIF_RX pad ctrl reg */ - u32 io_control_i2c0_scl; /* I2C0_SCL pad ctrl reg */ - u32 io_control_i2c0_sda; /* I2C0_SDA pad ctrl reg */ - u32 io_control_i2c1_scl; /* I2C1_SCL pad ctrl reg */ - u32 io_control_i2c1_sda; /* I2C1_SDA pad ctrl reg */ - u32 io_control_i2c2_scl; /* I2C2_SCL pad ctrl reg */ - u32 io_control_i2c2_sda; /* I2C2_SDA pad ctrl reg */ - u32 io_control_irq0; /* IRQ0 pad ctrl reg */ - u32 io_control_irq1; /* IRQ1 pad ctrl reg */ - u32 io_control_can1_tx; /* CAN1_TX pad ctrl reg */ - u32 io_control_can2_tx; /* CAN2_TX pad ctrl reg */ - u32 io_control_j1850_tx; /* J1850_TX pad ctrl reg */ - u32 io_control_j1850_rx; /* J1850_RX pad ctrl reg */ - u32 io_control_psc_mclk_in; /* PSC_MCLK_IN pad ctrl reg */ - u32 io_control_psc0_0; /* PSC0_0 pad ctrl reg */ - u32 io_control_psc0_1; /* PSC0_1 pad ctrl reg */ - u32 io_control_psc0_2; /* PSC0_2 pad ctrl reg */ - u32 io_control_psc0_3; /* PSC0_3 pad ctrl reg */ - u32 io_control_psc0_4; /* PSC0_4 pad ctrl reg */ - u32 io_control_psc1_0; /* PSC1_0 pad ctrl reg */ - u32 io_control_psc1_1; /* PSC1_1 pad ctrl reg */ - u32 io_control_psc1_2; /* PSC1_2 pad ctrl reg */ - u32 io_control_psc1_3; /* PSC1_3 pad ctrl reg */ - u32 io_control_psc1_4; /* PSC1_4 pad ctrl reg */ - u32 io_control_psc2_0; /* PSC2_0 pad ctrl reg */ - u32 io_control_psc2_1; /* PSC2_1 pad ctrl reg */ - u32 io_control_psc2_2; /* PSC2_2 pad ctrl reg */ - u32 io_control_psc2_3; /* PSC2_3 pad ctrl reg */ - u32 io_control_psc2_4; /* PSC2_4 pad ctrl reg */ - u32 io_control_psc3_0; /* PSC3_0 pad ctrl reg */ - u32 io_control_psc3_1; /* PSC3_1 pad ctrl reg */ - u32 io_control_psc3_2; /* PSC3_2 pad ctrl reg */ - u32 io_control_psc3_3; /* PSC3_3 pad ctrl reg */ - u32 io_control_psc3_4; /* PSC3_4 pad ctrl reg */ - u32 io_control_psc4_0; /* PSC4_0 pad ctrl reg */ - u32 io_control_psc4_1; /* PSC4_1 pad ctrl reg */ - u32 io_control_psc4_2; /* PSC4_2 pad ctrl reg */ - u32 io_control_psc4_3; /* PSC4_3 pad ctrl reg */ - u32 io_control_psc4_4; /* PSC4_4 pad ctrl reg */ - u32 io_control_psc5_0; /* PSC5_0 pad ctrl reg */ - u32 io_control_psc5_1; /* PSC5_1 pad ctrl reg */ - u32 io_control_psc5_2; /* PSC5_2 pad ctrl reg */ - u32 io_control_psc5_3; /* PSC5_3 pad ctrl reg */ - u32 io_control_psc5_4; /* PSC5_4 pad ctrl reg */ - u32 io_control_psc6_0; /* PSC6_0 pad ctrl reg */ - u32 io_control_psc6_1; /* PSC6_1 pad ctrl reg */ - u32 io_control_psc6_2; /* PSC6_2 pad ctrl reg */ - u32 io_control_psc6_3; /* PSC6_3 pad ctrl reg */ - u32 io_control_psc6_4; /* PSC6_4 pad ctrl reg */ - u32 io_control_psc7_0; /* PSC7_0 pad ctrl reg */ - u32 io_control_psc7_1; /* PSC7_1 pad ctrl reg */ - u32 io_control_psc7_2; /* PSC7_2 pad ctrl reg */ - u32 io_control_psc7_3; /* PSC7_3 pad ctrl reg */ - u32 io_control_psc7_4; /* PSC7_4 pad ctrl reg */ - u32 io_control_psc8_0; /* PSC8_0 pad ctrl reg */ - u32 io_control_psc8_1; /* PSC8_1 pad ctrl reg */ - u32 io_control_psc8_2; /* PSC8_2 pad ctrl reg */ - u32 io_control_psc8_3; /* PSC8_3 pad ctrl reg */ - u32 io_control_psc8_4; /* PSC8_4 pad ctrl reg */ - u32 io_control_psc9_0; /* PSC9_0 pad ctrl reg */ - u32 io_control_psc9_1; /* PSC9_1 pad ctrl reg */ - u32 io_control_psc9_2; /* PSC9_2 pad ctrl reg */ - u32 io_control_psc9_3; /* PSC9_3 pad ctrl reg */ - u32 io_control_psc9_4; /* PSC9_4 pad ctrl reg */ - u32 io_control_psc10_0; /* PSC10_0 pad ctrl reg */ - u32 io_control_psc10_1; /* PSC10_1 pad ctrl reg */ - u32 io_control_psc10_2; /* PSC10_2 pad ctrl reg */ - u32 io_control_psc10_3; /* PSC10_3 pad ctrl reg */ - u32 io_control_psc10_4; /* PSC10_4 pad ctrl reg */ - u32 io_control_psc11_0; /* PSC11_0 pad ctrl reg */ - u32 io_control_psc11_1; /* PSC11_1 pad ctrl reg */ - u32 io_control_psc11_2; /* PSC11_2 pad ctrl reg */ - u32 io_control_psc11_3; /* PSC11_3 pad ctrl reg */ - u32 io_control_psc11_4; /* PSC11_4 pad ctrl reg */ - u32 io_control_ckstp_out; /* CKSTP_OUT pad ctrl reg */ - u32 io_control_usb_phy_drvvbus; /* USB2_DRVVBUS pad ctrl reg */ - u8 reserved[0x0cfc]; /* fill to 4096 bytes size */ -} ioctrl512x_t; - -/* Indexes in regs array */ -/* Set for DDR */ -#define IOCTRL_MUX_DDR 0x00000036 - -/* IO pin fields */ -#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ -#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ -#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ -#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ -#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ -#define IO_PIN_DS(v) ((v)) /* slew rate */ - -typedef struct iopin_t { - int p_offset; /* offset from IOCTL_MEM_OFFSET */ - int nr_pins; /* number of pins to set this way */ - int bit_or; /* or in the value instead of overwrite */ - u_long val; /* value to write or or */ -}iopin_t; - -void iopin_initialize(iopin_t *,int); - -/* - * IIM - */ -typedef struct iim512x { - u32 stat; /* IIM status register */ - u32 statm; /* IIM status IRQ mask */ - u32 err; /* IIM errors register */ - u32 emask; /* IIM error IRQ mask */ - u32 fctl; /* IIM fuse control register */ - u32 ua; /* IIM upper address register */ - u32 la; /* IIM lower address register */ - u32 sdat; /* IIM explicit sense data */ - u8 res0[0x08]; - u32 prg_p; /* IIM program protection register */ - u8 res1[0x10]; - u32 divide; /* IIM divide factor register */ - u8 res2[0x7c0]; - u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */ - u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */ - u8 res3[0x380]; - u32 fbac1; /* IIM fuse bank 1 protection */ - u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */ - u8 res4[0x380]; -} iim512x_t; - -/* - * LPC - */ -typedef struct lpc512x { - u32 cs_cfg[8]; /* Chip Select N Configuration Registers - No dedicated entry for CS Boot as == CS0 */ - u32 cs_cr; /* Chip Select Control Register */ - u32 cs_sr; /* Chip Select Status Register */ - u32 cs_bcr; /* Chip Select Burst Control Register */ - u32 cs_dccr; /* Chip Select Deadcycle Control Register */ - u32 cs_hccr; /* Chip Select Holdcycle Control Register */ - u32 altr; /* Address Latch Timing Register */ - u8 res0[0xc8]; - u32 sclpc_psr; /* SCLPC Packet Size Register */ - u32 sclpc_sar; /* SCLPC Start Address Register */ - u32 sclpc_cr; /* SCLPC Control Register */ - u32 sclpc_er; /* SCLPC Enable Register */ - u32 sclpc_nar; /* SCLPC NextAddress Register */ - u32 sclpc_sr; /* SCLPC Status Register */ - u32 sclpc_bdr; /* SCLPC Bytes Done Register */ - u32 emb_scr; /* EMB Share Counter Register */ - u32 emb_pcr; /* EMB Pause Control Register */ - u8 res1[0x1c]; - u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */ - u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */ - u32 lpc_cr; /* LPC RX/TX FIFO Control Register */ - u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */ - u8 res2[0xb0]; -} lpc512x_t; - -/* - * PATA - */ -typedef struct pata512x { - /* LOCAL Registers */ - u32 pata_time1; /* Time register 1: PIO and tx timing parameter */ - u32 pata_time2; /* Time register 2: PIO timing parameter */ - u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */ - u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */ - u32 pata_time5; /* Time register 5: UDMA timing parameter */ - u32 pata_time6; /* Time register 6: UDMA timing parameter */ - u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */ - u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */ - u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/ - u32 pata_ata_control; /* ATA Interface control register */ - u32 pata_irq_pending; /* Interrupt pending register (READONLY) */ - u32 pata_irq_enable; /* Interrupt enable register */ - u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/ - u32 pata_fifo_alarm; /* fifo alarm threshold */ - u32 res1[0x1A]; - /* DRIVE Registers */ - u32 pata_drive_data; /* drive data register*/ - u32 pata_drive_features;/* drive features register */ - u32 pata_drive_sectcnt; /* drive sector count register */ - u32 pata_drive_sectnum; /* drive sector number register */ - u32 pata_drive_cyllow; /* drive cylinder low register */ - u32 pata_drive_cylhigh; /* drive cylinder high register */ - u32 pata_drive_dev_head;/* drive device head register */ - u32 pata_drive_command; /* write = drive command, read = drive status reg */ - u32 res2[0x06]; - u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */ - u32 res3[0x09]; -} pata512x_t; - -/* - * PSC - */ -typedef struct psc512x { - volatile u8 mode; /* PSC + 0x00 */ - volatile u8 res0[3]; - union { /* PSC + 0x04 */ - volatile u16 status; - volatile u16 clock_select; - } sr_csr; -#define psc_status sr_csr.status -#define psc_clock_select sr_csr.clock_select - volatile u16 res1; - volatile u8 command; /* PSC + 0x08 */ - volatile u8 res2[3]; - union { /* PSC + 0x0c */ - volatile u8 buffer_8; - volatile u16 buffer_16; - volatile u32 buffer_32; - } buffer; -#define psc_buffer_8 buffer.buffer_8 -#define psc_buffer_16 buffer.buffer_16 -#define psc_buffer_32 buffer.buffer_32 - union { /* PSC + 0x10 */ - volatile u8 ipcr; - volatile u8 acr; - } ipcr_acr; -#define psc_ipcr ipcr_acr.ipcr -#define psc_acr ipcr_acr.acr - volatile u8 res3[3]; - union { /* PSC + 0x14 */ - volatile u16 isr; - volatile u16 imr; - } isr_imr; -#define psc_isr isr_imr.isr -#define psc_imr isr_imr.imr - volatile u16 res4; - volatile u8 ctur; /* PSC + 0x18 */ - volatile u8 res5[3]; - volatile u8 ctlr; /* PSC + 0x1c */ - volatile u8 res6[3]; - volatile u32 ccr; /* PSC + 0x20 */ - volatile u8 res7[12]; - volatile u8 ivr; /* PSC + 0x30 */ - volatile u8 res8[3]; - volatile u8 ip; /* PSC + 0x34 */ - volatile u8 res9[3]; - volatile u8 op1; /* PSC + 0x38 */ - volatile u8 res10[3]; - volatile u8 op0; /* PSC + 0x3c */ - volatile u8 res11[3]; - volatile u32 sicr; /* PSC + 0x40 */ - volatile u8 res12[60]; - volatile u32 tfcmd; /* PSC + 0x80 */ - volatile u32 tfalarm; /* PSC + 0x84 */ - volatile u32 tfstat; /* PSC + 0x88 */ - volatile u32 tfintstat; /* PSC + 0x8C */ - volatile u32 tfintmask; /* PSC + 0x90 */ - volatile u32 tfcount; /* PSC + 0x94 */ - volatile u16 tfwptr; /* PSC + 0x98 */ - volatile u16 tfrptr; /* PSC + 0x9A */ - volatile u32 tfsize; /* PSC + 0x9C */ - volatile u8 res13[28]; - union { /* PSC + 0xBC */ - volatile u8 buffer_8; - volatile u16 buffer_16; - volatile u32 buffer_32; - } tfdata_buffer; -#define tfdata_8 tfdata_buffer.buffer_8 -#define tfdata_16 tfdata_buffer.buffer_16 -#define tfdata_32 tfdata_buffer.buffer_32 - - volatile u32 rfcmd; /* PSC + 0xC0 */ - volatile u32 rfalarm; /* PSC + 0xC4 */ - volatile u32 rfstat; /* PSC + 0xC8 */ - volatile u32 rfintstat; /* PSC + 0xCC */ - volatile u32 rfintmask; /* PSC + 0xD0 */ - volatile u32 rfcount; /* PSC + 0xD4 */ - volatile u16 rfwptr; /* PSC + 0xD8 */ - volatile u16 rfrptr; /* PSC + 0xDA */ - volatile u32 rfsize; /* PSC + 0xDC */ - volatile u8 res18[28]; - union { /* PSC + 0xFC */ - volatile u8 buffer_8; - volatile u16 buffer_16; - volatile u32 buffer_32; - } rfdata_buffer; -#define rfdata_8 rfdata_buffer.buffer_8 -#define rfdata_16 rfdata_buffer.buffer_16 -#define rfdata_32 rfdata_buffer.buffer_32 -} psc512x_t; - -/* PSC FIFO Command values */ -#define PSC_FIFO_RESET_SLICE 0x80 -#define PSC_FIFO_ENABLE_SLICE 0x01 - -/* PSC FIFO Controller Command values */ -#define FIFOC_ENABLE_CLOCK_GATE 0x01 -#define FIFOC_DISABLE_CLOCK_GATE 0x00 - -/* PSC FIFO status */ -#define PSC_FIFO_EMPTY 0x01 - -/* PSC Command values */ -#define PSC_RX_ENABLE 0x01 -#define PSC_RX_DISABLE 0x02 -#define PSC_TX_ENABLE 0x04 -#define PSC_TX_DISABLE 0x08 -#define PSC_SEL_MODE_REG_1 0x10 -#define PSC_RST_RX 0x20 -#define PSC_RST_TX 0x30 -#define PSC_RST_ERR_STAT 0x40 -#define PSC_RST_BRK_CHG_INT 0x50 -#define PSC_START_BRK 0x60 -#define PSC_STOP_BRK 0x70 - -/* PSC status register bits */ -#define PSC_SR_CDE 0x0080 -#define PSC_SR_TXEMP 0x0800 -#define PSC_SR_OE 0x1000 -#define PSC_SR_PE 0x2000 -#define PSC_SR_FE 0x4000 -#define PSC_SR_RB 0x8000 - -/* PSC mode fields */ -#define PSC_MODE_5_BITS 0x00 -#define PSC_MODE_6_BITS 0x01 -#define PSC_MODE_7_BITS 0x02 -#define PSC_MODE_8_BITS 0x03 -#define PSC_MODE_PAREVEN 0x00 -#define PSC_MODE_PARODD 0x04 -#define PSC_MODE_PARFORCE 0x08 -#define PSC_MODE_PARNONE 0x10 -#define PSC_MODE_ENTIMEOUT 0x20 -#define PSC_MODE_RXRTS 0x80 -#define PSC_MODE_1_STOPBIT 0x07 - -/* - * FIFOC - */ -typedef struct fifoc512x { - u32 fifoc_cmd; - u32 fifoc_int; - u32 fifoc_dma; - u32 fifoc_axe; - u32 fifoc_debug; - u8 fixme[0xEC]; -} fifoc512x_t; - -/* - * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs - * - * NOTE: individual PSC units are free to use whatever area (and size) of the - * FIFOC internal memory, so make sure memory areas for FIFO slices used by - * different PSCs do not overlap! - * - * Overall size of FIFOC memory is not documented in the MPC5121e RM, but - * tests indicate that it is 1024 words total. - */ -#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */ -#define FIFOC_PSC0_TX_ADDR 0x0 -#define FIFOC_PSC0_RX_SIZE 0x0 -#define FIFOC_PSC0_RX_ADDR 0x0 - -#define FIFOC_PSC1_TX_SIZE 0x0 -#define FIFOC_PSC1_TX_ADDR 0x0 -#define FIFOC_PSC1_RX_SIZE 0x0 -#define FIFOC_PSC1_RX_ADDR 0x0 - -#define FIFOC_PSC2_TX_SIZE 0x0 -#define FIFOC_PSC2_TX_ADDR 0x0 -#define FIFOC_PSC2_RX_SIZE 0x0 -#define FIFOC_PSC2_RX_ADDR 0x0 - -#define FIFOC_PSC3_TX_SIZE 0x04 -#define FIFOC_PSC3_TX_ADDR 0x0 -#define FIFOC_PSC3_RX_SIZE 0x04 -#define FIFOC_PSC3_RX_ADDR 0x10 - -#define FIFOC_PSC4_TX_SIZE 0x0 -#define FIFOC_PSC4_TX_ADDR 0x0 -#define FIFOC_PSC4_RX_SIZE 0x0 -#define FIFOC_PSC4_RX_ADDR 0x0 - -#define FIFOC_PSC5_TX_SIZE 0x0 -#define FIFOC_PSC5_TX_ADDR 0x0 -#define FIFOC_PSC5_RX_SIZE 0x0 -#define FIFOC_PSC5_RX_ADDR 0x0 - -#define FIFOC_PSC6_TX_SIZE 0x0 -#define FIFOC_PSC6_TX_ADDR 0x0 -#define FIFOC_PSC6_RX_SIZE 0x0 -#define FIFOC_PSC6_RX_ADDR 0x0 - -#define FIFOC_PSC7_TX_SIZE 0x0 -#define FIFOC_PSC7_TX_ADDR 0x0 -#define FIFOC_PSC7_RX_SIZE 0x0 -#define FIFOC_PSC7_RX_ADDR 0x0 - -#define FIFOC_PSC8_TX_SIZE 0x0 -#define FIFOC_PSC8_TX_ADDR 0x0 -#define FIFOC_PSC8_RX_SIZE 0x0 -#define FIFOC_PSC8_RX_ADDR 0x0 - -#define FIFOC_PSC9_TX_SIZE 0x0 -#define FIFOC_PSC9_TX_ADDR 0x0 -#define FIFOC_PSC9_RX_SIZE 0x0 -#define FIFOC_PSC9_RX_ADDR 0x0 - -#define FIFOC_PSC10_TX_SIZE 0x0 -#define FIFOC_PSC10_TX_ADDR 0x0 -#define FIFOC_PSC10_RX_SIZE 0x0 -#define FIFOC_PSC10_RX_ADDR 0x0 - -#define FIFOC_PSC11_TX_SIZE 0x0 -#define FIFOC_PSC11_TX_ADDR 0x0 -#define FIFOC_PSC11_RX_SIZE 0x0 -#define FIFOC_PSC11_RX_ADDR 0x0 - -/* - * SATA - */ -typedef struct sata512x { - u8 fixme[0x2000]; -} sata512x_t; - -typedef struct immap { - sysconf512x_t sysconf; /* System configuration */ - u8 res0[0x700]; - wdt512x_t wdt; /* Watch Dog Timer (WDT) */ - rtclk512x_t rtc; /* Real Time Clock Module */ - gpt512x_t gpt; /* General Purpose Timer */ - ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter512x_t arbiter; /* CSB Arbiter */ - reset512x_t reset; /* Reset Module */ - clk512x_t clk; /* Clock Module */ - pmc512x_t pmc; /* Power Management Control Module */ - gpio512x_t gpio; /* General purpose I/O module */ - u8 res1[0x100]; - mscan512x_t mscan; /* MSCAN */ - bdlc512x_t bdlc; /* BDLC */ - sdhc512x_t sdhc; /* SDHC */ - spdif512x_t spdif; /* SPDIF */ - i2c512x_t i2c; /* I2C Controllers */ - u8 res2[0x800]; - axe512x_t axe; /* AXE */ - diu512x_t diu; /* Display Interface Unit */ - cfm512x_t cfm; /* Clock Frequency Measurement */ - u8 res3[0x500]; - fec512x_t fec; /* Fast Ethernet Controller */ - ulpi512x_t ulpi; /* USB ULPI */ - u8 res4[0xa00]; - utmi512x_t utmi; /* USB UTMI */ - u8 res5[0x1000]; - pcidma512x_t pci_dma; /* PCI DMA */ - pciconf512x_t pci_conf; /* PCI Configuration */ - u8 res6[0x80]; - ios512x_t ios; /* PCI Sequencer */ - pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ - u8 res7[0xa00]; - ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ - ioctrl512x_t io_ctrl; /* IO Control */ - iim512x_t iim; /* IC Identification module */ - u8 res8[0x4000]; - lpc512x_t lpc; /* LocalPlus Controller */ - pata512x_t pata; /* Parallel ATA */ - u8 res9[0xd00]; - psc512x_t psc[12]; /* PSCs */ - u8 res10[0x300]; - fifoc512x_t fifoc; /* FIFO Controller */ - u8 res11[0x2000]; - dma512x_t dma; /* DMA */ - u8 res12[0xa800]; - sata512x_t sata; /* Serial ATA */ - u8 res13[0xde000]; -} immap_t; - -/* provide interface to get PATA base address */ -static inline u32 get_pata_base (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - return (u32)(&im->pata); -} -#endif /* __ASSEMBLY__ */ - -#endif /* __IMMAP_512x__ */ diff --git a/include/asm-ppc/immap_8220.h b/include/asm-ppc/immap_8220.h deleted file mode 100644 index f9595f4..0000000 --- a/include/asm-ppc/immap_8220.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * MPC8220 Internal Memory Map - * Copyright (c) 2004 TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * The Internal Memory Map of the 8220. - * - */ -#ifndef __IMMAP_MPC8220__ -#define __IMMAP_MPC8220__ - -/* - * System configuration registers. - */ -typedef struct sys_conf { - u16 mbar; /* 0x00 */ - u16 res1; - - u16 res2; /* 0x04 */ - u16 sdramds; - - u32 res3[6]; /* 0x08 */ - - u32 cscfg[6]; /* 0x20 */ - - u32 res4[2]; /* 0x38 */ - - u8 res5[3]; /* 0x40 */ - u8 rstctrl; - - u8 res6[3]; /* 0x44 */ - u8 rststat; - - u32 res7[2]; /* 0x48 */ - - u32 jtagid; /* 0x50 */ -} sysconf8220_t; - - -/* - * Memory controller registers. - */ -typedef struct mem_ctlr { - ushort mode; /* 0x100 */ - ushort res1; - u32 ctrl; /* 0x104 */ - u32 cfg1; /* 0x108 */ - u32 cfg2; /* 0x10c */ -} memctl8220_t; - -/* - * XLB Arbitration registers - */ -typedef struct xlb_arb -{ - uint res1[16]; /* 0x200 */ - uint config; /* 0x240 */ - uint version; /* 0x244 */ - uint status; /* 0x248 */ - uint intEnable; /* 0x24c */ - uint addrCap; /* 0x250 */ - uint busSigCap; /* 0x254 */ - uint addrTenTimeOut; /* 0x258 */ - uint dataTenTimeOut; /* 0x25c */ - uint busActTimeOut; /* 0x260 */ - uint mastPriEn; /* 0x264 */ - uint mastPriority; /* 0x268 */ - uint baseAddr; /* 0x26c */ -} xlbarb8220_t; - -/* - * Flexbus registers - */ -typedef struct flexbus -{ - ushort csar0; /* 0x00 */ - ushort res1; - uint csmr0; /* 0x04 */ - uint cscr0; /* 0x08 */ - - ushort csar1; /* 0x0c */ - ushort res2; - uint csmr1; /* 0x10 */ - uint cscr1; /* 0x14 */ - - ushort csar2; /* 0x18 */ - ushort res3; - uint csmr2; /* 0x1c */ - uint cscr2; /* 0x20 */ - - ushort csar3; /* 0x24 */ - ushort res4; - uint csmr3; /* 0x28 */ - uint cscr3; /* 0x2c */ - - ushort csar4; /* 0x30 */ - ushort res5; - uint csmr4; /* 0x34 */ - uint cscr4; /* 0x38 */ - - ushort csar5; /* 0x3c */ - ushort res6; - uint csmr5; /* 0x40 */ - uint cscr5; /* 0x44 */ -} flexbus8220_t; - -/* - * GPIO registers - */ -typedef struct gpio -{ - u32 out; /* 0x00 */ - u32 obs; /* 0x04 */ - u32 obc; /* 0x08 */ - u32 obt; /* 0x0c */ - u32 en; /* 0x10 */ - u32 ebs; /* 0x14 */ - u32 ebc; /* 0x18 */ - u32 ebt; /* 0x1c */ - u32 mc; /* 0x20 */ - u32 st; /* 0x24 */ - u32 intr; /* 0x28 */ -} gpio8220_t; - -/* - * General Purpose Timer registers - */ -typedef struct gptimer -{ - u8 OCPW; - u8 OctIct; - u8 Control; - u8 Mode; - - u16 Prescl; /* Prescale */ - u16 Count; /* Count */ - - u16 PwmWid; /* PWM Width */ - u8 PwmOp; /* Output Polarity */ - u8 PwmLd; /* Immediate Update */ - - u16 Capture; /* Capture internal counter */ - u8 OvfPin; /* Ovf and Pin */ - u8 Int; /* Interrupts */ -} gptmr8220_t; - -/* - * PSC registers - */ -typedef struct psc -{ - u32 mr1_2; /* 0x00 Mode reg 1 & 2 */ - u32 sr_csr; /* 0x04 Status/Clock Select reg */ - u32 cr; /* 0x08 Command reg */ - u8 xmitbuf[4]; /* 0x0c Receive/Transmit Buffer */ - u32 ipcr_acr; /* 0x10 Input Port Change/Auxiliary Control reg */ - u32 isr_imr; /* 0x14 Interrupt Status/Mask reg */ - u32 ctur; /* 0x18 Counter Timer Upper reg */ - u32 ctlr; /* 0x1c Counter Timer Lower reg */ - u32 rsvd1[4]; /* 0x20 ... 0x2c */ - u32 ivr; /* 0x30 Interrupt Vector reg */ - u32 ipr; /* 0x34 Input Port reg */ - u32 opsetr; /* 0x38 Output Port Set reg */ - u32 opresetr; /* 0x3c Output Port Reset reg */ - u32 sicr; /* 0x40 PSC/IrDA control reg */ - u32 ircr1; /* 0x44 IrDA control reg 1*/ - u32 ircr2; /* 0x48 IrDA control reg 2*/ - u32 irsdr; /* 0x4c IrDA SIR Divide reg */ - u32 irmdr; /* 0x50 IrDA MIR Divide reg */ - u32 irfdr; /* 0x54 PSC IrDA FIR Divide reg */ - u32 rfnum; /* 0x58 RX-FIFO counter */ - u32 txnum; /* 0x5c TX-FIFO counter */ - u32 rfdata; /* 0x60 RX-FIFO data */ - u32 rfstat; /* 0x64 RX-FIFO status */ - u32 rfcntl; /* 0x68 RX-FIFO control */ - u32 rfalarm; /* 0x6c RX-FIFO alarm */ - u32 rfrptr; /* 0x70 RX-FIFO read pointer */ - u32 rfwptr; /* 0x74 RX-FIFO write pointer */ - u32 rflfrptr; /* 0x78 RX-FIFO last read frame pointer */ - u32 rflfwptr; /* 0x7c RX-FIFO last write frame pointer */ - - u32 tfdata; /* 0x80 TX-FIFO data */ - u32 tfstat; /* 0x84 TX-FIFO status */ - u32 tfcntl; /* 0x88 TX-FIFO control */ - u32 tfalarm; /* 0x8c TX-FIFO alarm */ - u32 tfrptr; /* 0x90 TX-FIFO read pointer */ - u32 tfwptr; /* 0x94 TX-FIFO write pointer */ - u32 tflfrptr; /* 0x98 TX-FIFO last read frame pointer */ - u32 tflfwptr; /* 0x9c TX-FIFO last write frame pointer */ -} psc8220_t; - -/* - * Interrupt Controller registers - */ -typedef struct interrupt_controller { -} intctl8220_t; - - -/* Fast controllers -*/ - -/* - * I2C registers - */ -typedef struct i2c -{ - u8 adr; /* 0x00 */ - u8 res1[3]; - u8 fdr; /* 0x04 */ - u8 res2[3]; - u8 cr; /* 0x08 */ - u8 res3[3]; - u8 sr; /* 0x0C */ - u8 res4[3]; - u8 dr; /* 0x10 */ - u8 res5[3]; - u32 reserved0; /* 0x14 */ - u32 reserved1; /* 0x18 */ - u32 reserved2; /* 0x1c */ - u8 icr; /* 0x20 */ - u8 res6[3]; -} i2c8220_t; - -/* - * Port Configuration Registers - */ -typedef struct pcfg -{ - uint pcfg0; /* 0x00 */ - uint pcfg1; /* 0x04 */ - uint pcfg2; /* 0x08 */ - uint pcfg3; /* 0x0c */ -} pcfg8220_t; - -/* ...and the whole thing wrapped up.... -*/ -typedef struct immap { - sysconf8220_t im_sysconf; /* System Configuration */ - memctl8220_t im_memctl; /* Memory Controller */ - xlbarb8220_t im_xlbarb; /* XLB Arbitration */ - psc8220_t im_psc; /* PSC controller */ - flexbus8220_t im_fb; /* FlexBus Controller */ - i2c8220_t im_i2c; /* I2C control/status */ - pcfg8220_t im_pcfg; /* Port configuration */ -} immap_t; - -#endif /* __IMMAP_MPC8220__ */ diff --git a/include/asm-ppc/immap_8260.h b/include/asm-ppc/immap_8260.h deleted file mode 100644 index 4974ae5..0000000 --- a/include/asm-ppc/immap_8260.h +++ /dev/null @@ -1,599 +0,0 @@ -/* - * MPC8260 Internal Memory Map - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * - * The Internal Memory Map of the 8260. I don't know how generic - * this will be, as I don't have any knowledge of the subsequent - * parts at this time. I copied this from the 8xx_immap.h. - */ -#ifndef __IMMAP_82XX__ -#define __IMMAP_82XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - char res1[6]; - ushort sc_swsr; - char res2[20]; - uint sc_bcr; - u_char sc_ppc_acr; - char res3[3]; - uint sc_ppc_alrh; - uint sc_ppc_alrl; - u_char sc_lcl_acr; - char res4[3]; - uint sc_lcl_alrh; - uint sc_lcl_alrl; - uint sc_tescr1; - uint sc_tescr2; - uint sc_ltescr1; - uint sc_ltescr2; - uint sc_pdtea; - u_char sc_pdtem; - char res5[3]; - uint sc_ldtea; - u_char sc_ldtem; - char res6[163]; -} sysconf8260_t; - - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - uint memc_br4; - uint memc_or4; - uint memc_br5; - uint memc_or5; - uint memc_br6; - uint memc_or6; - uint memc_br7; - uint memc_or7; - uint memc_br8; - uint memc_or8; - uint memc_br9; - uint memc_or9; - uint memc_br10; - uint memc_or10; - uint memc_br11; - uint memc_or11; - char res1[8]; - uint memc_mar; - char res2[4]; - uint memc_mamr; - uint memc_mbmr; - uint memc_mcmr; - char res3[8]; - ushort memc_mptpr; - char res4[2]; - uint memc_mdr; - char res5[4]; - uint memc_psdmr; - uint memc_lsdmr; - u_char memc_purt; - char res6[3]; - u_char memc_psrt; - char res7[3]; - u_char memc_lurt; - char res8[3]; - u_char memc_lsrt; - char res9[3]; - uint memc_immr; - uint memc_pcibr0; - uint memc_pcibr1; - char res10[16]; - uint memc_pcimsk0; - uint memc_pcimsk1; - char res11[52]; -} memctl8260_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - char res1[32]; - ushort sit_tmcntsc; - char res2[2]; - uint sit_tmcnt; - char res3[4]; - uint sit_tmcntal; - char res4[16]; - ushort sit_piscr; - char res5[2]; - uint sit_pitc; - uint sit_pitr; - char res6[94]; - char res7[390]; -} sit8260_t; - -/* PCI - */ -typedef struct pci_config { - uint pci_omisr; - uint pci_ominr; - char res1[8]; - uint pci_ifqpr; - uint pci_ofqpr; - char res2[8]; - uint pci_imr0; - uint pci_imr1; - uint pci_omr0; - uint pci_omr1; - uint pci_odr; - char res3[4]; - uint pci_idr; - char res4[20]; - uint pci_imisr; - uint pci_imimr; - char res5[24]; - uint pci_ifhpr; - char res5_2[4]; - uint pci_iftpr; - char res6[4]; - uint pci_iphpr; - char res6_2[4]; - uint pci_iptpr; - char res7[4]; - uint pci_ofhpr; - char res7_2[4]; - uint pci_oftpr; - char res8[4]; - uint pci_ophpr; - char res8_2[4]; - uint pci_optpr; - char res9[8]; - uint pci_mucr; - char res10[8]; - uint pci_qbar; - char res11[12]; - uint pci_dmamr0; - uint pci_dmasr0; - uint pci_dmacdar0; - char res12[4]; - uint pci_dmasar0; - char res13[4]; - uint pci_dmadar0; - char res14[4]; - uint pci_dmabcr0; - uint pci_dmandar0; - char res15[88]; - uint pci_dmamr1; - uint pci_dmasr1; - uint pci_dmacdar1; - char res16[4]; - uint pci_dmasar1; - char res17[4]; - uint pci_dmadar1; - char res18[4]; - uint pci_dmabcr1; - uint pci_dmandar1; - char res19[88]; - uint pci_dmamr2; - uint pci_dmasr2; - uint pci_dmacdar2; - char res20[4]; - uint pci_dmasar2; - char res21[4]; - uint pci_dmadar2; - char res22[4]; - uint pci_dmabcr2; - uint pci_dmandar2; - char res23[88]; - uint pci_dmamr3; - uint pci_dmasr3; - uint pci_dmacdar3; - char res24[4]; - uint pci_dmasar3; - char res25[4]; - uint pci_dmadar3; - char res26[4]; - uint pci_dmabcr3; - uint pci_dmandar3; - char res27[344]; - uint pci_potar0; - char res28[4]; - uint pci_pobar0; - char res29[4]; - uint pci_pocmr0; - char res30[4]; - uint pci_potar1; - char res31[4]; - uint pci_pobar1; - char res32[4]; - uint pci_pocmr1; - char res33[4]; - uint pci_potar2; - char res34[4]; - uint pci_pobar2; - char res35[4]; - uint pci_pocmr2; - char res36[52]; - uint pci_ptcr; - uint pci_gpcr; - uint pci_gcr; - uint pci_esr; - uint pci_emr; - uint pci_ecr; - uint pci_eacr; - char res37[4]; - uint pci_edcr; - char res38[4]; - uint pci_eccr; - char res39[44]; - uint pci_pitar1; - char res40[4]; - uint pci_pibar1; - char res41[4]; - uint pci_picmr1; - char res42[4]; - uint pci_pitar0; - char res43[4]; - uint pci_pibar0; - char res44[4]; - uint pci_picmr0; - char res45[4]; - uint pci_cfg_addr; - uint pci_cfg_data; - uint pci_int_ack; - char res46[756]; -}pci8260_t; -#define PISCR_PIRQ_MASK ((ushort)0xff00) -#define PISCR_PS ((ushort)0x0080) -#define PISCR_PIE ((ushort)0x0004) -#define PISCR_PTF ((ushort)0x0002) -#define PISCR_PTE ((ushort)0x0001) - -/* Interrupt Controller. -*/ -typedef struct interrupt_controller { - ushort ic_sicr; - char res1[2]; - uint ic_sivec; - uint ic_sipnrh; - uint ic_sipnrl; - uint ic_siprr; - uint ic_scprrh; - uint ic_scprrl; - uint ic_simrh; - uint ic_simrl; - uint ic_siexr; - char res2[88]; -} intctl8260_t; - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - uint car_sccr; - char res1[4]; - uint car_scmr; - char res2[4]; - uint car_rsr; - uint car_rmr; - char res[104]; -} car8260_t; - -/* Input/Output Port control/status registers. - * Names consistent with processor manual, although they are different - * from the original 8xx names....... - */ -typedef struct io_port { - uint iop_pdira; - uint iop_ppara; - uint iop_psora; - uint iop_podra; - uint iop_pdata; - char res1[12]; - uint iop_pdirb; - uint iop_pparb; - uint iop_psorb; - uint iop_podrb; - uint iop_pdatb; - char res2[12]; - uint iop_pdirc; - uint iop_pparc; - uint iop_psorc; - uint iop_podrc; - uint iop_pdatc; - char res3[12]; - uint iop_pdird; - uint iop_ppard; - uint iop_psord; - uint iop_podrd; - uint iop_pdatd; - char res4[12]; -} iop8260_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - u_char cpmt_tgcr1; - char res1[3]; - u_char cpmt_tgcr2; - char res2[11]; - ushort cpmt_tmr1; - ushort cpmt_tmr2; - ushort cpmt_trr1; - ushort cpmt_trr2; - ushort cpmt_tcr1; - ushort cpmt_tcr2; - ushort cpmt_tcn1; - ushort cpmt_tcn2; - ushort cpmt_tmr3; - ushort cpmt_tmr4; - ushort cpmt_trr3; - ushort cpmt_trr4; - ushort cpmt_tcr3; - ushort cpmt_tcr4; - ushort cpmt_tcn3; - ushort cpmt_tcn4; - ushort cpmt_ter1; - ushort cpmt_ter2; - ushort cpmt_ter3; - ushort cpmt_ter4; - char res3[584]; -} cpmtimer8260_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res0[24]; - u_char sdma_sdsr; - char res1[3]; - u_char sdma_sdmr; - char res2[3]; - u_char sdma_idsr1; - char res3[3]; - u_char sdma_idmr1; - char res4[3]; - u_char sdma_idsr2; - char res5[3]; - u_char sdma_idmr2; - char res6[3]; - u_char sdma_idsr3; - char res7[3]; - u_char sdma_idmr3; - char res8[3]; - u_char sdma_idsr4; - char res9[3]; - u_char sdma_idmr4; - char res10[707]; -} sdma8260_t; - -/* Fast controllers -*/ -typedef struct fcc { - uint fcc_gfmr; - uint fcc_fpsmr; - ushort fcc_ftodr; - char res1[2]; - ushort fcc_fdsr; - char res2[2]; - ushort fcc_fcce; - char res3[2]; - ushort fcc_fccm; - char res4[2]; - u_char fcc_fccs; - char res5[3]; - u_char fcc_ftirr_phy[4]; -} fcc_t; - -/* Fast controllers continued - */ -typedef struct fcc_c { - uint fcc_firper; - uint fcc_firer; - uint fcc_firsr_hi; - uint fcc_firsr_lo; - u_char fcc_gfemr; - char res1[15]; -} fcc_c_t; - -/* TC Layer - */ -typedef struct tclayer { - ushort tc_tcmode; - ushort tc_cdsmr; - ushort tc_tcer; - ushort tc_rcc; - ushort tc_tcmr; - ushort tc_fcc; - ushort tc_ccc; - ushort tc_icc; - ushort tc_tcc; - ushort tc_ecc; - char res1[12]; -} tclayer_t; - -/* I2C -*/ -typedef struct i2c { - u_char i2c_i2mod; - char res1[3]; - u_char i2c_i2add; - char res2[3]; - u_char i2c_i2brg; - char res3[3]; - u_char i2c_i2com; - char res4[3]; - u_char i2c_i2cer; - char res5[3]; - u_char i2c_i2cmr; - char res6[331]; -} i2c8260_t; - -typedef struct scc { /* Serial communication channels */ - uint scc_gsmrl; - uint scc_gsmrh; - ushort scc_psmr; - char res1[2]; - ushort scc_todr; - ushort scc_dsr; - ushort scc_scce; - char res2[2]; - ushort scc_sccm; - char res3; - u_char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - ushort smc_smcmr; - char res2[2]; - u_char smc_smce; - char res3[3]; - u_char smc_smcm; - char res4[5]; -} smc_t; - -/* Serial Peripheral Interface. -*/ -typedef struct im_spi { - ushort spi_spmode; - char res1[4]; - u_char spi_spie; - char res2[3]; - u_char spi_spim; - char res3[2]; - u_char spi_spcom; - char res4[82]; -} im_spi_t; - -/* CPM Mux. -*/ -typedef struct cpmux { - u_char cmx_si1cr; - char res1; - u_char cmx_si2cr; - char res2; - uint cmx_fcr; - uint cmx_scr; - u_char cmx_smr; - char res3; - ushort cmx_uar; - char res4[16]; -} cpmux_t; - -/* SIRAM control -*/ -typedef struct siram { - ushort si_amr; - ushort si_bmr; - ushort si_cmr; - ushort si_dmr; - u_char si_gmr; - char res1; - u_char si_cmdr; - char res2; - u_char si_str; - char res3; - ushort si_rsr; -} siramctl_t; - -typedef struct mcc { - ushort mcc_mcce; - char res1[2]; - ushort mcc_mccm; - char res2[2]; - u_char mcc_mccf; - char res3[7]; -} mcc_t; - -typedef struct comm_proc { - uint cp_cpcr; - uint cp_rccr; - char res1[14]; - ushort cp_rter; - char res2[2]; - ushort cp_rtmr; - ushort cp_rtscr; - char res3[2]; - uint cp_rtsr; - char res4[12]; -} cpm8260_t; - -/* ...and the whole thing wrapped up.... -*/ -typedef struct immap { - /* Some references are into the unique and known dpram spaces, - * others are from the generic base. - */ -#define im_dprambase im_dpram1 - u_char im_dpram1[16*1024]; - char res1[16*1024]; - u_char im_dpram2[4*1024]; - char res2[8*1024]; - u_char im_dpram3[4*1024]; - char res3[16*1024]; - - sysconf8260_t im_siu_conf; /* SIU Configuration */ - memctl8260_t im_memctl; /* Memory Controller */ - sit8260_t im_sit; /* System Integration Timers */ - pci8260_t im_pci; /* PCI Configuration */ - intctl8260_t im_intctl; /* Interrupt Controller */ - car8260_t im_clkrst; /* Clocks and reset */ - iop8260_t im_ioport; /* IO Port control/status */ - cpmtimer8260_t im_cpmtimer; /* CPM timers */ - sdma8260_t im_sdma; /* SDMA control/status */ - - fcc_t im_fcc[3]; /* Three FCCs */ - - char res4[32]; - fcc_c_t im_fcc_c[3]; /* Continued FCCs */ - char res4a[32]; - - tclayer_t im_tclayer[8]; /* Eight TCLayers */ - ushort tc_tcgsr; - ushort tc_tcger; - - /* First set of baud rate generators. - */ - char res4b[236]; - uint im_brgc5; - uint im_brgc6; - uint im_brgc7; - uint im_brgc8; - - char res5[608]; - - i2c8260_t im_i2c; /* I2C control/status */ - cpm8260_t im_cpm; /* Communication processor */ - - /* Second set of baud rate generators. - */ - uint im_brgc1; - uint im_brgc2; - uint im_brgc3; - uint im_brgc4; - - scc_t im_scc[4]; /* Four SCCs */ - smc_t im_smc[2]; /* Couple of SMCs */ - im_spi_t im_spi; /* A SPI */ - cpmux_t im_cpmux; /* CPM clock route mux */ - siramctl_t im_siramctl1; /* First SI RAM Control */ - mcc_t im_mcc1; /* First MCC */ - siramctl_t im_siramctl2; /* Second SI RAM Control */ - mcc_t im_mcc2; /* Second MCC */ - - char res6[1184]; - - ushort im_si1txram[256]; - char res7[512]; - ushort im_si1rxram[256]; - char res8[512]; - ushort im_si2txram[256]; - char res9[512]; - ushort im_si2rxram[256]; - char res10[512]; - char res11[4096]; -} immap_t; - -#endif /* __IMMAP_82XX__ */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h deleted file mode 100644 index 6b42a73..0000000 --- a/include/asm-ppc/immap_83xx.h +++ /dev/null @@ -1,877 +0,0 @@ -/* - * Copyright 2004-2009 Freescale Semiconductor, Inc. - * - * MPC83xx Internal Memory Map - * - * Contributors: - * Dave Liu - * Tanya Jiang - * Mandy Lavi - * Eran Liberty - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#ifndef __IMMAP_83xx__ -#define __IMMAP_83xx__ - -#include -#include -#include -#include -#include - -/* - * Local Access Window - */ -typedef struct law83xx { - u32 bar; /* LBIU local access window base address register */ - u32 ar; /* LBIU local access window attribute register */ -} law83xx_t; - -/* - * System configuration registers - */ -typedef struct sysconf83xx { - u32 immrbar; /* Internal memory map base address register */ - u8 res0[0x04]; - u32 altcbar; /* Alternate configuration base address register */ - u8 res1[0x14]; - law83xx_t lblaw[4]; /* LBIU local access window */ - u8 res2[0x20]; - law83xx_t pcilaw[2]; /* PCI local access window */ - u8 res3[0x10]; - law83xx_t pcielaw[2]; /* PCI Express local access window */ - u8 res4[0x10]; - law83xx_t ddrlaw[2]; /* DDR local access window */ - u8 res5[0x50]; - u32 sgprl; /* System General Purpose Register Low */ - u32 sgprh; /* System General Purpose Register High */ - u32 spridr; /* System Part and Revision ID Register */ - u8 res6[0x04]; - u32 spcr; /* System Priority Configuration Register */ - u32 sicrl; /* System I/O Configuration Register Low */ - u32 sicrh; /* System I/O Configuration Register High */ - u8 res7[0x04]; - u32 sidcr0; /* System I/O Delay Configuration Register 0 */ - u32 sidcr1; /* System I/O Delay Configuration Register 1 */ - u32 ddrcdr; /* DDR Control Driver Register */ - u32 ddrdsr; /* DDR Debug Status Register */ - u32 obir; /* Output Buffer Impedance Register */ - u8 res8[0xC]; - u32 pecr1; /* PCI Express control register 1 */ - u32 pecr2; /* PCI Express control register 2 */ - u8 res9[0xB8]; -} sysconf83xx_t; - -/* - * Watch Dog Timer (WDT) Registers - */ -typedef struct wdt83xx { - u8 res0[4]; - u32 swcrr; /* System watchdog control register */ - u32 swcnr; /* System watchdog count register */ - u8 res1[2]; - u16 swsrr; /* System watchdog service register */ - u8 res2[0xF0]; -} wdt83xx_t; - -/* - * RTC/PIT Module Registers - */ -typedef struct rtclk83xx { - u32 cnr; /* control register */ - u32 ldr; /* load register */ - u32 psr; /* prescale register */ - u32 ctr; /* counter value field register */ - u32 evr; /* event register */ - u32 alr; /* alarm register */ - u8 res0[0xE8]; -} rtclk83xx_t; - -/* - * Global timer module - */ -typedef struct gtm83xx { - u8 cfr1; /* Timer1/2 Configuration */ - u8 res0[3]; - u8 cfr2; /* Timer3/4 Configuration */ - u8 res1[10]; - u16 mdr1; /* Timer1 Mode Register */ - u16 mdr2; /* Timer2 Mode Register */ - u16 rfr1; /* Timer1 Reference Register */ - u16 rfr2; /* Timer2 Reference Register */ - u16 cpr1; /* Timer1 Capture Register */ - u16 cpr2; /* Timer2 Capture Register */ - u16 cnr1; /* Timer1 Counter Register */ - u16 cnr2; /* Timer2 Counter Register */ - u16 mdr3; /* Timer3 Mode Register */ - u16 mdr4; /* Timer4 Mode Register */ - u16 rfr3; /* Timer3 Reference Register */ - u16 rfr4; /* Timer4 Reference Register */ - u16 cpr3; /* Timer3 Capture Register */ - u16 cpr4; /* Timer4 Capture Register */ - u16 cnr3; /* Timer3 Counter Register */ - u16 cnr4; /* Timer4 Counter Register */ - u16 evr1; /* Timer1 Event Register */ - u16 evr2; /* Timer2 Event Register */ - u16 evr3; /* Timer3 Event Register */ - u16 evr4; /* Timer4 Event Register */ - u16 psr1; /* Timer1 Prescaler Register */ - u16 psr2; /* Timer2 Prescaler Register */ - u16 psr3; /* Timer3 Prescaler Register */ - u16 psr4; /* Timer4 Prescaler Register */ - u8 res[0xC0]; -} gtm83xx_t; - -/* - * Integrated Programmable Interrupt Controller - */ -typedef struct ipic83xx { - u32 sicfr; /* System Global Interrupt Configuration Register */ - u32 sivcr; /* System Global Interrupt Vector Register */ - u32 sipnr_h; /* System Internal Interrupt Pending Register - High */ - u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */ - u32 siprr_a; /* System Internal Interrupt Group A Priority Register */ - u8 res0[8]; - u32 siprr_d; /* System Internal Interrupt Group D Priority Register */ - u32 simsr_h; /* System Internal Interrupt Mask Register - High */ - u32 simsr_l; /* System Internal Interrupt Mask Register - Low */ - u8 res1[4]; - u32 sepnr; /* System External Interrupt Pending Register */ - u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */ - u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */ - u32 semsr; /* System External Interrupt Mask Register */ - u32 secnr; /* System External Interrupt Control Register */ - u32 sersr; /* System Error Status Register */ - u32 sermr; /* System Error Mask Register */ - u32 sercr; /* System Error Control Register */ - u8 res2[4]; - u32 sifcr_h; /* System Internal Interrupt Force Register - High */ - u32 sifcr_l; /* System Internal Interrupt Force Register - Low */ - u32 sefcr; /* System External Interrupt Force Register */ - u32 serfr; /* System Error Force Register */ - u32 scvcr; /* System Critical Interrupt Vector Register */ - u32 smvcr; /* System Management Interrupt Vector Register */ - u8 res3[0x98]; -} ipic83xx_t; - -/* - * System Arbiter Registers - */ -typedef struct arbiter83xx { - u32 acr; /* Arbiter Configuration Register */ - u32 atr; /* Arbiter Timers Register */ - u8 res[4]; - u32 aer; /* Arbiter Event Register */ - u32 aidr; /* Arbiter Interrupt Definition Register */ - u32 amr; /* Arbiter Mask Register */ - u32 aeatr; /* Arbiter Event Attributes Register */ - u32 aeadr; /* Arbiter Event Address Register */ - u32 aerr; /* Arbiter Event Response Register */ - u8 res1[0xDC]; -} arbiter83xx_t; - -/* - * Reset Module - */ -typedef struct reset83xx { - u32 rcwl; /* Reset Configuration Word Low Register */ - u32 rcwh; /* Reset Configuration Word High Register */ - u8 res0[8]; - u32 rsr; /* Reset Status Register */ - u32 rmr; /* Reset Mode Register */ - u32 rpr; /* Reset protection Register */ - u32 rcr; /* Reset Control Register */ - u32 rcer; /* Reset Control Enable Register */ - u8 res1[0xDC]; -} reset83xx_t; - -/* - * Clock Module - */ -typedef struct clk83xx { - u32 spmr; /* system PLL mode Register */ - u32 occr; /* output clock control Register */ - u32 sccr; /* system clock control Register */ - u8 res0[0xF4]; -} clk83xx_t; - -/* - * Power Management Control Module - */ -typedef struct pmc83xx { - u32 pmccr; /* PMC Configuration Register */ - u32 pmcer; /* PMC Event Register */ - u32 pmcmr; /* PMC Mask Register */ - u32 pmccr1; /* PMC Configuration Register 1 */ - u32 pmccr2; /* PMC Configuration Register 2 */ - u8 res0[0xEC]; -} pmc83xx_t; - -/* - * General purpose I/O module - */ -typedef struct gpio83xx { - u32 dir; /* direction register */ - u32 odr; /* open drain register */ - u32 dat; /* data register */ - u32 ier; /* interrupt event register */ - u32 imr; /* interrupt mask register */ - u32 icr; /* external interrupt control register */ - u8 res0[0xE8]; -} gpio83xx_t; - -/* - * QE Ports Interrupts Registers - */ -typedef struct qepi83xx { - u8 res0[0xC]; - u32 qepier; /* QE Ports Interrupt Event Register */ - u32 qepimr; /* QE Ports Interrupt Mask Register */ - u32 qepicr; /* QE Ports Interrupt Control Register */ - u8 res1[0xE8]; -} qepi83xx_t; - -/* - * QE Parallel I/O Ports - */ -typedef struct gpio_n { - u32 podr; /* Open Drain Register */ - u32 pdat; /* Data Register */ - u32 dir1; /* direction register 1 */ - u32 dir2; /* direction register 2 */ - u32 ppar1; /* Pin Assignment Register 1 */ - u32 ppar2; /* Pin Assignment Register 2 */ -} gpio_n_t; - -typedef struct qegpio83xx { - gpio_n_t ioport[0x7]; - u8 res0[0x358]; -} qepio83xx_t; - -/* - * QE Secondary Bus Access Windows - */ -typedef struct qesba83xx { - u32 lbmcsar; /* Local bus memory controller start address */ - u32 sdmcsar; /* Secondary DDR memory controller start address */ - u8 res0[0x38]; - u32 lbmcear; /* Local bus memory controller end address */ - u32 sdmcear; /* Secondary DDR memory controller end address */ - u8 res1[0x38]; - u32 lbmcar; /* Local bus memory controller attributes */ - u32 sdmcar; /* Secondary DDR memory controller attributes */ - u8 res2[0x378]; -} qesba83xx_t; - -/* - * DDR Memory Controller Memory Map - */ -typedef struct ddr_cs_bnds { - u32 csbnds; - u8 res0[4]; -} ddr_cs_bnds_t; - -typedef struct ddr83xx { - ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ - u8 res0[0x60]; - u32 cs_config[4]; /* Chip Select x Configuration */ - u8 res1[0x70]; - u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ - u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ - u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ - u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ - u32 sdram_cfg; /* SDRAM Control Configuration */ - u32 sdram_cfg2; /* SDRAM Control Configuration 2 */ - u32 sdram_mode; /* SDRAM Mode Configuration */ - u32 sdram_mode2; /* SDRAM Mode Configuration 2 */ - u32 sdram_md_cntl; /* SDRAM Mode Control */ - u32 sdram_interval; /* SDRAM Interval Configuration */ - u32 ddr_data_init; /* SDRAM Data Initialization */ - u8 res2[4]; - u32 sdram_clk_cntl; /* SDRAM Clock Control */ - u8 res3[0x14]; - u32 ddr_init_addr; /* DDR training initialization address */ - u32 ddr_init_ext_addr; /* DDR training initialization extended address */ - u8 res4[0xAA8]; - u32 ddr_ip_rev1; /* DDR IP block revision 1 */ - u32 ddr_ip_rev2; /* DDR IP block revision 2 */ - u8 res5[0x200]; - u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ - u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ - u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ - u8 res6[0x14]; - u32 capture_data_hi; /* Memory Data Path Read Capture High */ - u32 capture_data_lo; /* Memory Data Path Read Capture Low */ - u32 capture_ecc; /* Memory Data Path Read Capture ECC */ - u8 res7[0x14]; - u32 err_detect; /* Memory Error Detect */ - u32 err_disable; /* Memory Error Disable */ - u32 err_int_en; /* Memory Error Interrupt Enable */ - u32 capture_attributes; /* Memory Error Attributes Capture */ - u32 capture_address; /* Memory Error Address Capture */ - u32 capture_ext_address;/* Memory Error Extended Address Capture */ - u32 err_sbe; /* Memory Single-Bit ECC Error Management */ - u8 res8[0xA4]; - u32 debug_reg; - u8 res9[0xFC]; -} ddr83xx_t; - -/* - * DUART - */ -typedef struct duart83xx { - u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */ - u8 uier_udmb; /* combined register for UIER and UDMB */ - u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */ - u8 ulcr; /* line control register */ - u8 umcr; /* MODEM control register */ - u8 ulsr; /* line status register */ - u8 umsr; /* MODEM status register */ - u8 uscr; /* scratch register */ - u8 res0[8]; - u8 udsr; /* DMA status register */ - u8 res1[3]; - u8 res2[0xEC]; -} duart83xx_t; - -/* - * DMA/Messaging Unit - */ -typedef struct dma83xx { - u32 res0[0xC]; /* 0x0-0x29 reseverd */ - u32 omisr; /* 0x30 Outbound message interrupt status register */ - u32 omimr; /* 0x34 Outbound message interrupt mask register */ - u32 res1[0x6]; /* 0x38-0x49 reserved */ - u32 imr0; /* 0x50 Inbound message register 0 */ - u32 imr1; /* 0x54 Inbound message register 1 */ - u32 omr0; /* 0x58 Outbound message register 0 */ - u32 omr1; /* 0x5C Outbound message register 1 */ - u32 odr; /* 0x60 Outbound doorbell register */ - u32 res2; /* 0x64-0x67 reserved */ - u32 idr; /* 0x68 Inbound doorbell register */ - u32 res3[0x5]; /* 0x6C-0x79 reserved */ - u32 imisr; /* 0x80 Inbound message interrupt status register */ - u32 imimr; /* 0x84 Inbound message interrupt mask register */ - u32 res4[0x1E]; /* 0x88-0x99 reserved */ - struct fsl_dma dma[4]; -} dma83xx_t; - -/* - * PCI Software Configuration Registers - */ -typedef struct pciconf83xx { - u32 config_address; - u32 config_data; - u32 int_ack; - u8 res[116]; -} pciconf83xx_t; - -/* - * PCI Outbound Translation Register - */ -typedef struct pci_outbound_window { - u32 potar; - u8 res0[4]; - u32 pobar; - u8 res1[4]; - u32 pocmr; - u8 res2[4]; -} pot83xx_t; - -/* - * Sequencer - */ -typedef struct ios83xx { - pot83xx_t pot[6]; - u8 res0[0x60]; - u32 pmcr; - u8 res1[4]; - u32 dtcr; - u8 res2[4]; -} ios83xx_t; - -/* - * PCI Controller Control and Status Registers - */ -typedef struct pcictrl83xx { - u32 esr; - u32 ecdr; - u32 eer; - u32 eatcr; - u32 eacr; - u32 eeacr; - u32 edlcr; - u32 edhcr; - u32 gcr; - u32 ecr; - u32 gsr; - u8 res0[12]; - u32 pitar2; - u8 res1[4]; - u32 pibar2; - u32 piebar2; - u32 piwar2; - u8 res2[4]; - u32 pitar1; - u8 res3[4]; - u32 pibar1; - u32 piebar1; - u32 piwar1; - u8 res4[4]; - u32 pitar0; - u8 res5[4]; - u32 pibar0; - u8 res6[4]; - u32 piwar0; - u8 res7[132]; -} pcictrl83xx_t; - -/* - * USB - */ -typedef struct usb83xx { - u8 fixme[0x1000]; -} usb83xx_t; - -/* - * TSEC - */ -typedef struct tsec83xx { - u8 fixme[0x1000]; -} tsec83xx_t; - -/* - * Security - */ -typedef struct security83xx { - u8 fixme[0x10000]; -} security83xx_t; - -/* - * PCI Express - */ -struct pex_inbound_window { - u32 ar; - u32 tar; - u32 barl; - u32 barh; -}; - -struct pex_outbound_window { - u32 ar; - u32 bar; - u32 tarl; - u32 tarh; -}; - -struct pex_csb_bridge { - u32 pex_csb_ver; - u32 pex_csb_cab; - u32 pex_csb_ctrl; - u8 res0[8]; - u32 pex_dms_dstmr; - u8 res1[4]; - u32 pex_cbs_stat; - u8 res2[0x20]; - u32 pex_csb_obctrl; - u32 pex_csb_obstat; - u8 res3[0x98]; - u32 pex_csb_ibctrl; - u32 pex_csb_ibstat; - u8 res4[0xb8]; - u32 pex_wdma_ctrl; - u32 pex_wdma_addr; - u32 pex_wdma_stat; - u8 res5[0x94]; - u32 pex_rdma_ctrl; - u32 pex_rdma_addr; - u32 pex_rdma_stat; - u8 res6[0xd4]; - u32 pex_ombcr; - u32 pex_ombdr; - u8 res7[0x38]; - u32 pex_imbcr; - u32 pex_imbdr; - u8 res8[0x38]; - u32 pex_int_enb; - u32 pex_int_stat; - u32 pex_int_apio_vec1; - u32 pex_int_apio_vec2; - u8 res9[0x10]; - u32 pex_int_ppio_vec1; - u32 pex_int_ppio_vec2; - u32 pex_int_wdma_vec1; - u32 pex_int_wdma_vec2; - u32 pex_int_rdma_vec1; - u32 pex_int_rdma_vec2; - u32 pex_int_misc_vec; - u8 res10[4]; - u32 pex_int_axi_pio_enb; - u32 pex_int_axi_wdma_enb; - u32 pex_int_axi_rdma_enb; - u32 pex_int_axi_misc_enb; - u32 pex_int_axi_pio_stat; - u32 pex_int_axi_wdma_stat; - u32 pex_int_axi_rdma_stat; - u32 pex_int_axi_misc_stat; - u8 res11[0xa0]; - struct pex_outbound_window pex_outbound_win[4]; - u8 res12[0x100]; - u32 pex_epiwtar0; - u32 pex_epiwtar1; - u32 pex_epiwtar2; - u32 pex_epiwtar3; - u8 res13[0x70]; - struct pex_inbound_window pex_inbound_win[4]; -}; - -typedef struct pex83xx { - u8 pex_cfg_header[0x404]; - u32 pex_ltssm_stat; - u8 res0[0x30]; - u32 pex_ack_replay_timeout; - u8 res1[4]; - u32 pex_gclk_ratio; - u8 res2[0xc]; - u32 pex_pm_timer; - u32 pex_pme_timeout; - u8 res3[4]; - u32 pex_aspm_req_timer; - u8 res4[0x18]; - u32 pex_ssvid_update; - u8 res5[0x34]; - u32 pex_cfg_ready; - u8 res6[0x24]; - u32 pex_bar_sizel; - u8 res7[4]; - u32 pex_bar_sel; - u8 res8[0x20]; - u32 pex_bar_pf; - u8 res9[0x88]; - u32 pex_pme_to_ack_tor; - u8 res10[0xc]; - u32 pex_ss_intr_mask; - u8 res11[0x25c]; - struct pex_csb_bridge bridge; - u8 res12[0x160]; -} pex83xx_t; - -/* - * SATA - */ -typedef struct sata83xx { - u8 fixme[0x1000]; -} sata83xx_t; - -/* - * eSDHC - */ -typedef struct sdhc83xx { - u8 fixme[0x1000]; -} sdhc83xx_t; - -/* - * SerDes - */ -typedef struct serdes83xx { - u8 fixme[0x100]; -} serdes83xx_t; - -/* - * On Chip ROM - */ -typedef struct rom83xx { - u8 mem[0x10000]; -} rom83xx_t; - -/* - * TDM - */ -typedef struct tdm83xx { - u8 fixme[0x200]; -} tdm83xx_t; - -/* - * TDM DMAC - */ -typedef struct tdmdmac83xx { - u8 fixme[0x2000]; -} tdmdmac83xx_t; - -#if defined(CONFIG_MPC834x) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[2]; /* General purpose I/O module */ - u8 res0[0x200]; - u8 dll_ddr[0x100]; - u8 dll_lbc[0x100]; - u8 res1[0xE00]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res2[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res3[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ - u8 res4[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ - u8 res5[0x19900]; - usb83xx_t usb[2]; - tsec83xx_t tsec[2]; - u8 res6[0xA000]; - security83xx_t security; - u8 res7[0xC0000]; -} immap_t; - -#ifdef CONFIG_HAS_FSL_MPH_USB -#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */ -#else -#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */ -#endif - -#elif defined(CONFIG_MPC8313) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[1]; /* General purpose I/O module */ - u8 res0[0x1300]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res1[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res2[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ - u8 res3[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res4[0x80]; - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res5[0x1aa00]; - usb83xx_t usb[1]; - tsec83xx_t tsec[2]; - u8 res6[0xA000]; - security83xx_t security; - u8 res7[0xC0000]; -} immap_t; - -#elif defined(CONFIG_MPC8315) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[1]; /* General purpose I/O module */ - u8 res0[0x1300]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res1[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res2[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ - u8 res3[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res4[0x80]; - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res5[0xa00]; - pex83xx_t pciexp[2]; /* PCI Express Controller */ - u8 res6[0xb000]; - tdm83xx_t tdm; /* TDM Controller */ - u8 res7[0x1e00]; - sata83xx_t sata[2]; /* SATA Controller */ - u8 res8[0x9000]; - usb83xx_t usb[1]; /* USB DR Controller */ - tsec83xx_t tsec[2]; - u8 res9[0x6000]; - tdmdmac83xx_t tdmdmac; /* TDM DMAC */ - u8 res10[0x2000]; - security83xx_t security; - u8 res11[0xA3000]; - serdes83xx_t serdes[1]; /* SerDes Registers */ - u8 res12[0x1CF00]; -} immap_t; - -#elif defined(CONFIG_MPC837x) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[2]; /* General purpose I/O module */ - u8 res0[0x1200]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res1[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res2[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ - u8 res3[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res4[0x80]; - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res5[0xa00]; - pex83xx_t pciexp[2]; /* PCI Express Controller */ - u8 res6[0xd000]; - sata83xx_t sata[4]; /* SATA Controller */ - u8 res7[0x7000]; - usb83xx_t usb[1]; /* USB DR Controller */ - tsec83xx_t tsec[2]; - u8 res8[0x8000]; - sdhc83xx_t sdhc; /* SDHC Controller */ - u8 res9[0x1000]; - security83xx_t security; - u8 res10[0xA3000]; - serdes83xx_t serdes[2]; /* SerDes Registers */ - u8 res11[0xCE00]; - rom83xx_t rom; /* On Chip ROM */ -} immap_t; - -#elif defined(CONFIG_MPC8360) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - u8 res0[0x200]; - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - qepi83xx_t qepi; /* QE Ports Interrupts Registers */ - u8 res1[0x300]; - u8 dll_ddr[0x100]; - u8 dll_lbc[0x100]; - u8 res2[0x200]; - qepio83xx_t qepio; /* QE Parallel I/O ports */ - qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ - u8 res3[0x400]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res4[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res5[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ - u8 res6[0x2000]; - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res7[128]; - ios83xx_t ios; /* Sequencer (IOS) */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res8[0x4A00]; - ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ - u8 res9[0x22000]; - security83xx_t security; - u8 res10[0xC0000]; - u8 qe[0x100000]; /* QE block */ -} immap_t; - -#elif defined(CONFIG_MPC832x) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - qepi83xx_t qepi; /* QE Ports Interrupts Registers */ - u8 res0[0x300]; - u8 dll_ddr[0x100]; - u8 dll_lbc[0x100]; - u8 res1[0x200]; - qepio83xx_t qepio; /* QE Parallel I/O ports */ - u8 res2[0x800]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res3[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res4[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ - u8 res5[0x2000]; - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res6[128]; - ios83xx_t ios; /* Sequencer (IOS) */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res7[0x27A00]; - security83xx_t security; - u8 res8[0xC0000]; - u8 qe[0x100000]; /* QE block */ -} immap_t; -#endif - -#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000) -#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET) -#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) -#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) - -#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET -#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 -#endif -#define CONFIG_SYS_MPC83xx_USB_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET) - -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 - -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) -#endif /* __IMMAP_83xx__ */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h deleted file mode 100644 index 957ad76..0000000 --- a/include/asm-ppc/immap_85xx.h +++ /dev/null @@ -1,2106 +0,0 @@ -/* - * MPC85xx Internal Memory Map - * - * Copyright 2007-2009 Freescale Semiconductor, Inc. - * - * Copyright(c) 2002,2003 Motorola Inc. - * Xianghua Xiao (x.xiao@motorola.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __IMMAP_85xx__ -#define __IMMAP_85xx__ - -#include -#include -#include -#include - -typedef struct ccsr_local { - u32 ccsrbarh; /* CCSR Base Addr High */ - u32 ccsrbarl; /* CCSR Base Addr Low */ - u32 ccsrar; /* CCSR Attr */ -#define CCSRAR_C 0x80000000 /* Commit */ - u8 res1[4]; - u32 altcbarh; /* Alternate Configuration Base Addr High */ - u32 altcbarl; /* Alternate Configuration Base Addr Low */ - u32 altcar; /* Alternate Configuration Attr */ - u8 res2[4]; - u32 bstrh; /* Boot space translation high */ - u32 bstrl; /* Boot space translation Low */ - u32 bstrar; /* Boot space translation attributes */ - u8 res3[0xbd4]; - struct { - u32 lawbarh; /* LAWn base addr high */ - u32 lawbarl; /* LAWn base addr low */ - u32 lawar; /* LAWn attributes */ - u8 res4[4]; - } law[32]; - u8 res35[0x204]; -} ccsr_local_t; - -/* Local-Access Registers & ECM Registers */ -typedef struct ccsr_local_ecm { - u32 ccsrbar; /* CCSR Base Addr */ - u8 res1[4]; - u32 altcbar; /* Alternate Configuration Base Addr */ - u8 res2[4]; - u32 altcar; /* Alternate Configuration Attr */ - u8 res3[12]; - u32 bptr; /* Boot Page Translation */ - u8 res4[3044]; - u32 lawbar0; /* Local Access Window 0 Base Addr */ - u8 res5[4]; - u32 lawar0; /* Local Access Window 0 Attrs */ - u8 res6[20]; - u32 lawbar1; /* Local Access Window 1 Base Addr */ - u8 res7[4]; - u32 lawar1; /* Local Access Window 1 Attrs */ - u8 res8[20]; - u32 lawbar2; /* Local Access Window 2 Base Addr */ - u8 res9[4]; - u32 lawar2; /* Local Access Window 2 Attrs */ - u8 res10[20]; - u32 lawbar3; /* Local Access Window 3 Base Addr */ - u8 res11[4]; - u32 lawar3; /* Local Access Window 3 Attrs */ - u8 res12[20]; - u32 lawbar4; /* Local Access Window 4 Base Addr */ - u8 res13[4]; - u32 lawar4; /* Local Access Window 4 Attrs */ - u8 res14[20]; - u32 lawbar5; /* Local Access Window 5 Base Addr */ - u8 res15[4]; - u32 lawar5; /* Local Access Window 5 Attrs */ - u8 res16[20]; - u32 lawbar6; /* Local Access Window 6 Base Addr */ - u8 res17[4]; - u32 lawar6; /* Local Access Window 6 Attrs */ - u8 res18[20]; - u32 lawbar7; /* Local Access Window 7 Base Addr */ - u8 res19[4]; - u32 lawar7; /* Local Access Window 7 Attrs */ - u8 res19_8a[20]; - u32 lawbar8; /* Local Access Window 8 Base Addr */ - u8 res19_8b[4]; - u32 lawar8; /* Local Access Window 8 Attrs */ - u8 res19_9a[20]; - u32 lawbar9; /* Local Access Window 9 Base Addr */ - u8 res19_9b[4]; - u32 lawar9; /* Local Access Window 9 Attrs */ - u8 res19_10a[20]; - u32 lawbar10; /* Local Access Window 10 Base Addr */ - u8 res19_10b[4]; - u32 lawar10; /* Local Access Window 10 Attrs */ - u8 res19_11a[20]; - u32 lawbar11; /* Local Access Window 11 Base Addr */ - u8 res19_11b[4]; - u32 lawar11; /* Local Access Window 11 Attrs */ - u8 res20[652]; - u32 eebacr; /* ECM CCB Addr Configuration */ - u8 res21[12]; - u32 eebpcr; /* ECM CCB Port Configuration */ - u8 res22[3564]; - u32 eedr; /* ECM Error Detect */ - u8 res23[4]; - u32 eeer; /* ECM Error Enable */ - u32 eeatr; /* ECM Error Attrs Capture */ - u32 eeadr; /* ECM Error Addr Capture */ - u8 res24[492]; -} ccsr_local_ecm_t; - -/* DDR memory controller registers */ -typedef struct ccsr_ddr { - u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ - u8 res1[4]; - u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ - u8 res2[4]; - u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ - u8 res3[4]; - u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ - u8 res4[100]; - u32 cs0_config; /* Chip Select Configuration */ - u32 cs1_config; /* Chip Select Configuration */ - u32 cs2_config; /* Chip Select Configuration */ - u32 cs3_config; /* Chip Select Configuration */ - u8 res4a[48]; - u32 cs0_config_2; /* Chip Select Configuration 2 */ - u32 cs1_config_2; /* Chip Select Configuration 2 */ - u32 cs2_config_2; /* Chip Select Configuration 2 */ - u32 cs3_config_2; /* Chip Select Configuration 2 */ - u8 res5[48]; - u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ - u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ - u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ - u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ - u32 sdram_cfg; /* SDRAM Control Configuration */ - u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ - u32 sdram_mode; /* SDRAM Mode Configuration */ - u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ - u32 sdram_md_cntl; /* SDRAM Mode Control */ - u32 sdram_interval; /* SDRAM Interval Configuration */ - u32 sdram_data_init; /* SDRAM Data initialization */ - u8 res6[4]; - u32 sdram_clk_cntl; /* SDRAM Clock Control */ - u8 res7[20]; - u32 init_addr; /* training init addr */ - u32 init_ext_addr; /* training init extended addr */ - u8 res8_1[16]; - u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ - u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ - u8 reg8_1a[8]; - u32 ddr_zq_cntl; /* ZQ calibration control*/ - u32 ddr_wrlvl_cntl; /* write leveling control*/ - u8 reg8_1aa[4]; - u32 ddr_sr_cntr; /* self refresh counter */ - u32 ddr_sdram_rcw_1; /* Control Words 1 */ - u32 ddr_sdram_rcw_2; /* Control Words 2 */ - u8 res8_1b[2456]; - u32 ddr_dsr1; /* Debug Status 1 */ - u32 ddr_dsr2; /* Debug Status 2 */ - u32 ddr_cdr1; /* Control Driver 1 */ - u32 ddr_cdr2; /* Control Driver 2 */ - u8 res8_1c[200]; - u32 ip_rev1; /* IP Block Revision 1 */ - u32 ip_rev2; /* IP Block Revision 2 */ - u8 res8_2[512]; - u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ - u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ - u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ - u8 res9[20]; - u32 capture_data_hi; /* Data Path Read Capture High */ - u32 capture_data_lo; /* Data Path Read Capture Low */ - u32 capture_ecc; /* Data Path Read Capture ECC */ - u8 res10[20]; - u32 err_detect; /* Error Detect */ - u32 err_disable; /* Error Disable */ - u32 err_int_en; - u32 capture_attributes; /* Error Attrs Capture */ - u32 capture_address; /* Error Addr Capture */ - u32 capture_ext_address; /* Error Extended Addr Capture */ - u32 err_sbe; /* Single-Bit ECC Error Management */ - u8 res11[164]; - u32 debug_1; - u32 debug_2; - u32 debug_3; - u32 debug_4; - u32 debug_5; - u32 debug_6; - u32 debug_7; - u32 debug_8; - u32 debug_9; - u32 debug_10; - u32 debug_11; - u32 debug_12; - u32 debug_13; - u32 debug_14; - u32 debug_15; - u32 debug_16; - u32 debug_17; - u32 debug_18; - u8 res12[184]; -} ccsr_ddr_t; - -/* I2C Registers */ -typedef struct ccsr_i2c { - struct fsl_i2c i2c[1]; - u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; -} ccsr_i2c_t; - -#if defined(CONFIG_MPC8540) \ - || defined(CONFIG_MPC8541) \ - || defined(CONFIG_MPC8548) \ - || defined(CONFIG_MPC8555) -/* DUART Registers */ -typedef struct ccsr_duart { - u8 res1[1280]; -/* URBR1, UTHR1, UDLB1 with the same addr */ - u8 urbr1_uthr1_udlb1; -/* UIER1, UDMB1 with the same addr01 */ - u8 uier1_udmb1; -/* UIIR1, UFCR1, UAFR1 with the same addr */ - u8 uiir1_ufcr1_uafr1; - u8 ulcr1; /* UART1 Line Control */ - u8 umcr1; /* UART1 Modem Control */ - u8 ulsr1; /* UART1 Line Status */ - u8 umsr1; /* UART1 Modem Status */ - u8 uscr1; /* UART1 Scratch */ - u8 res2[8]; - u8 udsr1; /* UART1 DMA Status */ - u8 res3[239]; -/* URBR2, UTHR2, UDLB2 with the same addr */ - u8 urbr2_uthr2_udlb2; -/* UIER2, UDMB2 with the same addr */ - u8 uier2_udmb2; -/* UIIR2, UFCR2, UAFR2 with the same addr */ - u8 uiir2_ufcr2_uafr2; - u8 ulcr2; /* UART2 Line Control */ - u8 umcr2; /* UART2 Modem Control */ - u8 ulsr2; /* UART2 Line Status */ - u8 umsr2; /* UART2 Modem Status */ - u8 uscr2; /* UART2 Scratch */ - u8 res4[8]; - u8 udsr2; /* UART2 DMA Status */ - u8 res5[2543]; -} ccsr_duart_t; -#else /* MPC8560 uses UART on its CPM */ -typedef struct ccsr_duart { - u8 res[4096]; -} ccsr_duart_t; -#endif - -/* Local Bus Controller Registers */ -typedef struct ccsr_lbc { - u32 br0; /* LBC Base 0 */ - u32 or0; /* LBC Options 0 */ - u32 br1; /* LBC Base 1 */ - u32 or1; /* LBC Options 1 */ - u32 br2; /* LBC Base 2 */ - u32 or2; /* LBC Options 2 */ - u32 br3; /* LBC Base 3 */ - u32 or3; /* LBC Options 3 */ - u32 br4; /* LBC Base 4 */ - u32 or4; /* LBC Options 4 */ - u32 br5; /* LBC Base 5 */ - u32 or5; /* LBC Options 5 */ - u32 br6; /* LBC Base 6 */ - u32 or6; /* LBC Options 6 */ - u32 br7; /* LBC Base 7 */ - u32 or7; /* LBC Options 7 */ - u8 res1[40]; - u32 mar; /* LBC UPM Addr */ - u8 res2[4]; - u32 mamr; /* LBC UPMA Mode */ - u32 mbmr; /* LBC UPMB Mode */ - u32 mcmr; /* LBC UPMC Mode */ - u8 res3[8]; - u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */ - u32 mdr; /* LBC UPM Data */ - u8 res4[8]; - u32 lsdmr; /* LBC SDRAM Mode */ - u8 res5[8]; - u32 lurt; /* LBC UPM Refresh Timer */ - u32 lsrt; /* LBC SDRAM Refresh Timer */ - u8 res6[8]; - u32 ltesr; /* LBC Transfer Error Status */ - u32 ltedr; /* LBC Transfer Error Disable */ - u32 lteir; /* LBC Transfer Error IRQ */ - u32 lteatr; /* LBC Transfer Error Attrs */ - u32 ltear; /* LBC Transfer Error Addr */ - u8 res7[12]; - u32 lbcr; /* LBC Configuration */ - u32 lcrr; /* LBC Clock Ratio */ - u8 res8[3880]; -} ccsr_lbc_t; - -/* eSPI Registers */ -typedef struct ccsr_espi { - u32 mode; /* eSPI mode */ - u32 event; /* eSPI event */ - u32 mask; /* eSPI mask */ - u32 com; /* eSPI command */ - u32 tx; /* eSPI transmit FIFO access */ - u32 rx; /* eSPI receive FIFO access */ - u8 res1[8]; /* reserved */ - u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ - u8 res2[4048]; /* fill up to 0x1000 */ -} ccsr_espi_t; - -/* PCI Registers */ -typedef struct ccsr_pcix { - u32 cfg_addr; /* PCIX Configuration Addr */ - u32 cfg_data; /* PCIX Configuration Data */ - u32 int_ack; /* PCIX IRQ Acknowledge */ - u8 res1[3060]; - u32 potar0; /* PCIX Outbound Transaction Addr 0 */ - u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ - u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ - u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */ - u32 powar0; /* PCIX Outbound Window Attrs 0 */ - u8 res2[12]; - u32 potar1; /* PCIX Outbound Transaction Addr 1 */ - u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */ - u32 powbar1; /* PCIX Outbound Window Base Addr 1 */ - u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */ - u32 powar1; /* PCIX Outbound Window Attrs 1 */ - u8 res3[12]; - u32 potar2; /* PCIX Outbound Transaction Addr 2 */ - u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */ - u32 powbar2; /* PCIX Outbound Window Base Addr 2 */ - u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */ - u32 powar2; /* PCIX Outbound Window Attrs 2 */ - u8 res4[12]; - u32 potar3; /* PCIX Outbound Transaction Addr 3 */ - u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */ - u32 powbar3; /* PCIX Outbound Window Base Addr 3 */ - u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */ - u32 powar3; /* PCIX Outbound Window Attrs 3 */ - u8 res5[12]; - u32 potar4; /* PCIX Outbound Transaction Addr 4 */ - u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */ - u32 powbar4; /* PCIX Outbound Window Base Addr 4 */ - u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */ - u32 powar4; /* PCIX Outbound Window Attrs 4 */ - u8 res6[268]; - u32 pitar3; /* PCIX Inbound Translation Addr 3 */ - u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */ - u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */ - u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */ - u32 piwar3; /* PCIX Inbound Window Attrs 3 */ - u8 res7[12]; - u32 pitar2; /* PCIX Inbound Translation Addr 2 */ - u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */ - u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */ - u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */ - u32 piwar2; /* PCIX Inbound Window Attrs 2 */ - u8 res8[12]; - u32 pitar1; /* PCIX Inbound Translation Addr 1 */ - u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */ - u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */ - u8 res9[4]; - u32 piwar1; /* PCIX Inbound Window Attrs 1 */ - u8 res10[12]; - u32 pedr; /* PCIX Error Detect */ - u32 pecdr; /* PCIX Error Capture Disable */ - u32 peer; /* PCIX Error Enable */ - u32 peattrcr; /* PCIX Error Attrs Capture */ - u32 peaddrcr; /* PCIX Error Addr Capture */ - u32 peextaddrcr; /* PCIX Error Extended Addr Capture */ - u32 pedlcr; /* PCIX Error Data Low Capture */ - u32 pedhcr; /* PCIX Error Error Data High Capture */ - u32 gas_timr; /* PCIX Gasket Timer */ - u8 res11[476]; -} ccsr_pcix_t; - -#define PCIX_COMMAND 0x62 -#define POWAR_EN 0x80000000 -#define POWAR_IO_READ 0x00080000 -#define POWAR_MEM_READ 0x00040000 -#define POWAR_IO_WRITE 0x00008000 -#define POWAR_MEM_WRITE 0x00004000 -#define POWAR_MEM_512M 0x0000001c -#define POWAR_IO_1M 0x00000013 - -#define PIWAR_EN 0x80000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_LOCAL 0x00f00000 -#define PIWAR_READ_SNOOP 0x00050000 -#define PIWAR_WRITE_SNOOP 0x00005000 -#define PIWAR_MEM_2G 0x0000001e - -typedef struct ccsr_gpio { - u32 gpdir; - u32 gpodr; - u32 gpdat; - u32 gpier; - u32 gpimr; - u32 gpicr; -} ccsr_gpio_t; - -/* L2 Cache Registers */ -typedef struct ccsr_l2cache { - u32 l2ctl; /* L2 configuration 0 */ - u8 res1[12]; - u32 l2cewar0; /* L2 cache external write addr 0 */ - u8 res2[4]; - u32 l2cewcr0; /* L2 cache external write control 0 */ - u8 res3[4]; - u32 l2cewar1; /* L2 cache external write addr 1 */ - u8 res4[4]; - u32 l2cewcr1; /* L2 cache external write control 1 */ - u8 res5[4]; - u32 l2cewar2; /* L2 cache external write addr 2 */ - u8 res6[4]; - u32 l2cewcr2; /* L2 cache external write control 2 */ - u8 res7[4]; - u32 l2cewar3; /* L2 cache external write addr 3 */ - u8 res8[4]; - u32 l2cewcr3; /* L2 cache external write control 3 */ - u8 res9[180]; - u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */ - u8 res10[4]; - u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */ - u8 res11[3316]; - u32 l2errinjhi; /* L2 error injection mask high */ - u32 l2errinjlo; /* L2 error injection mask low */ - u32 l2errinjctl; /* L2 error injection tag/ECC control */ - u8 res12[20]; - u32 l2captdatahi; /* L2 error data high capture */ - u32 l2captdatalo; /* L2 error data low capture */ - u32 l2captecc; /* L2 error ECC capture */ - u8 res13[20]; - u32 l2errdet; /* L2 error detect */ - u32 l2errdis; /* L2 error disable */ - u32 l2errinten; /* L2 error interrupt enable */ - u32 l2errattr; /* L2 error attributes capture */ - u32 l2erraddr; /* L2 error addr capture */ - u8 res14[4]; - u32 l2errctl; /* L2 error control */ - u8 res15[420]; -} ccsr_l2cache_t; - -#define MPC85xx_L2CTL_L2E 0x80000000 -#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 -#define MPC85xx_L2ERRDIS_MBECC 0x00000008 -#define MPC85xx_L2ERRDIS_SBECC 0x00000004 - -/* DMA Registers */ -typedef struct ccsr_dma { - u8 res1[256]; - struct fsl_dma dma[4]; - u32 dgsr; /* DMA General Status */ - u8 res2[11516]; -} ccsr_dma_t; - -/* tsec */ -typedef struct ccsr_tsec { - u8 res1[16]; - u32 ievent; /* IRQ Event */ - u32 imask; /* IRQ Mask */ - u32 edis; /* Error Disabled */ - u8 res2[4]; - u32 ecntrl; /* Ethernet Control */ - u32 minflr; /* Minimum Frame Len */ - u32 ptv; /* Pause Time Value */ - u32 dmactrl; /* DMA Control */ - u32 tbipa; /* TBI PHY Addr */ - u8 res3[88]; - u32 fifo_tx_thr; /* FIFO transmit threshold */ - u8 res4[8]; - u32 fifo_tx_starve; /* FIFO transmit starve */ - u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */ - u8 res5[96]; - u32 tctrl; /* TX Control */ - u32 tstat; /* TX Status */ - u8 res6[4]; - u32 tbdlen; /* TX Buffer Desc Data Len */ - u8 res7[16]; - u32 ctbptrh; /* Current TX Buffer Desc Ptr High */ - u32 ctbptr; /* Current TX Buffer Desc Ptr */ - u8 res8[88]; - u32 tbptrh; /* TX Buffer Desc Ptr High */ - u32 tbptr; /* TX Buffer Desc Ptr Low */ - u8 res9[120]; - u32 tbaseh; /* TX Desc Base Addr High */ - u32 tbase; /* TX Desc Base Addr */ - u8 res10[168]; - u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */ - u32 ostbdp; /* OOS TX Data Buffer Ptr */ - u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */ - u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */ - u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */ - u32 os32tbdr; /* OOS 32 Bytes TX Reserved */ - u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */ - u8 res11[52]; - u32 rctrl; /* RX Control */ - u32 rstat; /* RX Status */ - u8 res12[4]; - u32 rbdlen; /* RxBD Data Len */ - u8 res13[16]; - u32 crbptrh; /* Current RX Buffer Desc Ptr High */ - u32 crbptr; /* Current RX Buffer Desc Ptr */ - u8 res14[24]; - u32 mrblr; /* Maximum RX Buffer Len */ - u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */ - u8 res15[56]; - u32 rbptrh; /* RX Buffer Desc Ptr High 0 */ - u32 rbptr; /* RX Buffer Desc Ptr */ - u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */ - u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */ - u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */ - u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */ - u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */ - u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */ - u8 res16[96]; - u32 rbaseh; /* RX Desc Base Addr High 0 */ - u32 rbase; /* RX Desc Base Addr */ - u32 rbaseh1; /* RX Desc Base Addr High 1 */ - u32 rbasel1; /* RX Desc Base Addr Low 1 */ - u32 rbaseh2; /* RX Desc Base Addr High 2 */ - u32 rbasel2; /* RX Desc Base Addr Low 2 */ - u32 rbaseh3; /* RX Desc Base Addr High 3 */ - u32 rbasel3; /* RX Desc Base Addr Low 3 */ - u8 res17[224]; - u32 maccfg1; /* MAC Configuration 1 */ - u32 maccfg2; /* MAC Configuration 2 */ - u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ - u32 hafdup; /* Half Duplex */ - u32 maxfrm; /* Maximum Frame Len */ - u8 res18[12]; - u32 miimcfg; /* MII Management Configuration */ - u32 miimcom; /* MII Management Cmd */ - u32 miimadd; /* MII Management Addr */ - u32 miimcon; /* MII Management Control */ - u32 miimstat; /* MII Management Status */ - u32 miimind; /* MII Management Indicator */ - u8 res19[4]; - u32 ifstat; /* Interface Status */ - u32 macstnaddr1; /* Station Addr Part 1 */ - u32 macstnaddr2; /* Station Addr Part 2 */ - u8 res20[312]; - u32 tr64; /* TX & RX 64-byte Frame Counter */ - u32 tr127; /* TX & RX 65-127 byte Frame Counter */ - u32 tr255; /* TX & RX 128-255 byte Frame Counter */ - u32 tr511; /* TX & RX 256-511 byte Frame Counter */ - u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */ - u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */ - u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */ - u32 rbyt; /* RX Byte Counter */ - u32 rpkt; /* RX Packet Counter */ - u32 rfcs; /* RX FCS Error Counter */ - u32 rmca; /* RX Multicast Packet Counter */ - u32 rbca; /* RX Broadcast Packet Counter */ - u32 rxcf; /* RX Control Frame Packet Counter */ - u32 rxpf; /* RX Pause Frame Packet Counter */ - u32 rxuo; /* RX Unknown OP Code Counter */ - u32 raln; /* RX Alignment Error Counter */ - u32 rflr; /* RX Frame Len Error Counter */ - u32 rcde; /* RX Code Error Counter */ - u32 rcse; /* RX Carrier Sense Error Counter */ - u32 rund; /* RX Undersize Packet Counter */ - u32 rovr; /* RX Oversize Packet Counter */ - u32 rfrg; /* RX Fragments Counter */ - u32 rjbr; /* RX Jabber Counter */ - u32 rdrp; /* RX Drop Counter */ - u32 tbyt; /* TX Byte Counter Counter */ - u32 tpkt; /* TX Packet Counter */ - u32 tmca; /* TX Multicast Packet Counter */ - u32 tbca; /* TX Broadcast Packet Counter */ - u32 txpf; /* TX Pause Control Frame Counter */ - u32 tdfr; /* TX Deferral Packet Counter */ - u32 tedf; /* TX Excessive Deferral Packet Counter */ - u32 tscl; /* TX Single Collision Packet Counter */ - u32 tmcl; /* TX Multiple Collision Packet Counter */ - u32 tlcl; /* TX Late Collision Packet Counter */ - u32 txcl; /* TX Excessive Collision Packet Counter */ - u32 tncl; /* TX Total Collision Counter */ - u8 res21[4]; - u32 tdrp; /* TX Drop Frame Counter */ - u32 tjbr; /* TX Jabber Frame Counter */ - u32 tfcs; /* TX FCS Error Counter */ - u32 txcf; /* TX Control Frame Counter */ - u32 tovr; /* TX Oversize Frame Counter */ - u32 tund; /* TX Undersize Frame Counter */ - u32 tfrg; /* TX Fragments Frame Counter */ - u32 car1; /* Carry One */ - u32 car2; /* Carry Two */ - u32 cam1; /* Carry Mask One */ - u32 cam2; /* Carry Mask Two */ - u8 res22[192]; - u32 iaddr0; /* Indivdual addr 0 */ - u32 iaddr1; /* Indivdual addr 1 */ - u32 iaddr2; /* Indivdual addr 2 */ - u32 iaddr3; /* Indivdual addr 3 */ - u32 iaddr4; /* Indivdual addr 4 */ - u32 iaddr5; /* Indivdual addr 5 */ - u32 iaddr6; /* Indivdual addr 6 */ - u32 iaddr7; /* Indivdual addr 7 */ - u8 res23[96]; - u32 gaddr0; /* Global addr 0 */ - u32 gaddr1; /* Global addr 1 */ - u32 gaddr2; /* Global addr 2 */ - u32 gaddr3; /* Global addr 3 */ - u32 gaddr4; /* Global addr 4 */ - u32 gaddr5; /* Global addr 5 */ - u32 gaddr6; /* Global addr 6 */ - u32 gaddr7; /* Global addr 7 */ - u8 res24[96]; - u32 pmd0; /* Pattern Match Data */ - u8 res25[4]; - u32 pmask0; /* Pattern Mask */ - u8 res26[4]; - u32 pcntrl0; /* Pattern Match Control */ - u8 res27[4]; - u32 pattrb0; /* Pattern Match Attrs */ - u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd1; /* Pattern Match Data */ - u8 res28[4]; - u32 pmask1; /* Pattern Mask */ - u8 res29[4]; - u32 pcntrl1; /* Pattern Match Control */ - u8 res30[4]; - u32 pattrb1; /* Pattern Match Attrs */ - u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd2; /* Pattern Match Data */ - u8 res31[4]; - u32 pmask2; /* Pattern Mask */ - u8 res32[4]; - u32 pcntrl2; /* Pattern Match Control */ - u8 res33[4]; - u32 pattrb2; /* Pattern Match Attrs */ - u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd3; /* Pattern Match Data */ - u8 res34[4]; - u32 pmask3; /* Pattern Mask */ - u8 res35[4]; - u32 pcntrl3; /* Pattern Match Control */ - u8 res36[4]; - u32 pattrb3; /* Pattern Match Attrs */ - u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd4; /* Pattern Match Data */ - u8 res37[4]; - u32 pmask4; /* Pattern Mask */ - u8 res38[4]; - u32 pcntrl4; /* Pattern Match Control */ - u8 res39[4]; - u32 pattrb4; /* Pattern Match Attrs */ - u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd5; /* Pattern Match Data */ - u8 res40[4]; - u32 pmask5; /* Pattern Mask */ - u8 res41[4]; - u32 pcntrl5; /* Pattern Match Control */ - u8 res42[4]; - u32 pattrb5; /* Pattern Match Attrs */ - u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd6; /* Pattern Match Data */ - u8 res43[4]; - u32 pmask6; /* Pattern Mask */ - u8 res44[4]; - u32 pcntrl6; /* Pattern Match Control */ - u8 res45[4]; - u32 pattrb6; /* Pattern Match Attrs */ - u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd7; /* Pattern Match Data */ - u8 res46[4]; - u32 pmask7; /* Pattern Mask */ - u8 res47[4]; - u32 pcntrl7; /* Pattern Match Control */ - u8 res48[4]; - u32 pattrb7; /* Pattern Match Attrs */ - u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd8; /* Pattern Match Data */ - u8 res49[4]; - u32 pmask8; /* Pattern Mask */ - u8 res50[4]; - u32 pcntrl8; /* Pattern Match Control */ - u8 res51[4]; - u32 pattrb8; /* Pattern Match Attrs */ - u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd9; /* Pattern Match Data */ - u8 res52[4]; - u32 pmask9; /* Pattern Mask */ - u8 res53[4]; - u32 pcntrl9; /* Pattern Match Control */ - u8 res54[4]; - u32 pattrb9; /* Pattern Match Attrs */ - u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd10; /* Pattern Match Data */ - u8 res55[4]; - u32 pmask10; /* Pattern Mask */ - u8 res56[4]; - u32 pcntrl10; /* Pattern Match Control */ - u8 res57[4]; - u32 pattrb10; /* Pattern Match Attrs */ - u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd11; /* Pattern Match Data */ - u8 res58[4]; - u32 pmask11; /* Pattern Mask */ - u8 res59[4]; - u32 pcntrl11; /* Pattern Match Control */ - u8 res60[4]; - u32 pattrb11; /* Pattern Match Attrs */ - u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd12; /* Pattern Match Data */ - u8 res61[4]; - u32 pmask12; /* Pattern Mask */ - u8 res62[4]; - u32 pcntrl12; /* Pattern Match Control */ - u8 res63[4]; - u32 pattrb12; /* Pattern Match Attrs */ - u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd13; /* Pattern Match Data */ - u8 res64[4]; - u32 pmask13; /* Pattern Mask */ - u8 res65[4]; - u32 pcntrl13; /* Pattern Match Control */ - u8 res66[4]; - u32 pattrb13; /* Pattern Match Attrs */ - u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd14; /* Pattern Match Data */ - u8 res67[4]; - u32 pmask14; /* Pattern Mask */ - u8 res68[4]; - u32 pcntrl14; /* Pattern Match Control */ - u8 res69[4]; - u32 pattrb14; /* Pattern Match Attrs */ - u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */ - u32 pmd15; /* Pattern Match Data */ - u8 res70[4]; - u32 pmask15; /* Pattern Mask */ - u8 res71[4]; - u32 pcntrl15; /* Pattern Match Control */ - u8 res72[4]; - u32 pattrb15; /* Pattern Match Attrs */ - u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */ - u8 res73[248]; - u32 attr; /* Attrs */ - u32 attreli; /* Attrs Extract Len & Idx */ - u8 res74[1024]; -} ccsr_tsec_t; - -/* PIC Registers */ -typedef struct ccsr_pic { - u8 res1[64]; - u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */ - u8 res2[12]; - u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */ - u8 res3[12]; - u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */ - u8 res4[12]; - u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */ - u8 res5[12]; - u32 ctpr; /* Current Task Priority */ - u8 res6[12]; - u32 whoami; /* Who Am I */ - u8 res7[12]; - u32 iack; /* IRQ Acknowledge */ - u8 res8[12]; - u32 eoi; /* End Of IRQ */ - u8 res9[3916]; - u32 frr; /* Feature Reporting */ - u8 res10[28]; - u32 gcr; /* Global Configuration */ -#define MPC85xx_PICGCR_RST 0x80000000 -#define MPC85xx_PICGCR_M 0x20000000 - u8 res11[92]; - u32 vir; /* Vendor Identification */ - u8 res12[12]; - u32 pir; /* Processor Initialization */ - u8 res13[12]; - u32 ipivpr0; /* IPI Vector/Priority 0 */ - u8 res14[12]; - u32 ipivpr1; /* IPI Vector/Priority 1 */ - u8 res15[12]; - u32 ipivpr2; /* IPI Vector/Priority 2 */ - u8 res16[12]; - u32 ipivpr3; /* IPI Vector/Priority 3 */ - u8 res17[12]; - u32 svr; /* Spurious Vector */ - u8 res18[12]; - u32 tfrr; /* Timer Frequency Reporting */ - u8 res19[12]; - u32 gtccr0; /* Global Timer Current Count 0 */ - u8 res20[12]; - u32 gtbcr0; /* Global Timer Base Count 0 */ - u8 res21[12]; - u32 gtvpr0; /* Global Timer Vector/Priority 0 */ - u8 res22[12]; - u32 gtdr0; /* Global Timer Destination 0 */ - u8 res23[12]; - u32 gtccr1; /* Global Timer Current Count 1 */ - u8 res24[12]; - u32 gtbcr1; /* Global Timer Base Count 1 */ - u8 res25[12]; - u32 gtvpr1; /* Global Timer Vector/Priority 1 */ - u8 res26[12]; - u32 gtdr1; /* Global Timer Destination 1 */ - u8 res27[12]; - u32 gtccr2; /* Global Timer Current Count 2 */ - u8 res28[12]; - u32 gtbcr2; /* Global Timer Base Count 2 */ - u8 res29[12]; - u32 gtvpr2; /* Global Timer Vector/Priority 2 */ - u8 res30[12]; - u32 gtdr2; /* Global Timer Destination 2 */ - u8 res31[12]; - u32 gtccr3; /* Global Timer Current Count 3 */ - u8 res32[12]; - u32 gtbcr3; /* Global Timer Base Count 3 */ - u8 res33[12]; - u32 gtvpr3; /* Global Timer Vector/Priority 3 */ - u8 res34[12]; - u32 gtdr3; /* Global Timer Destination 3 */ - u8 res35[268]; - u32 tcr; /* Timer Control */ - u8 res36[12]; - u32 irqsr0; /* IRQ_OUT Summary 0 */ - u8 res37[12]; - u32 irqsr1; /* IRQ_OUT Summary 1 */ - u8 res38[12]; - u32 cisr0; /* Critical IRQ Summary 0 */ - u8 res39[12]; - u32 cisr1; /* Critical IRQ Summary 1 */ - u8 res40[188]; - u32 msgr0; /* Message 0 */ - u8 res41[12]; - u32 msgr1; /* Message 1 */ - u8 res42[12]; - u32 msgr2; /* Message 2 */ - u8 res43[12]; - u32 msgr3; /* Message 3 */ - u8 res44[204]; - u32 mer; /* Message Enable */ - u8 res45[12]; - u32 msr; /* Message Status */ - u8 res46[60140]; - u32 eivpr0; /* External IRQ Vector/Priority 0 */ - u8 res47[12]; - u32 eidr0; /* External IRQ Destination 0 */ - u8 res48[12]; - u32 eivpr1; /* External IRQ Vector/Priority 1 */ - u8 res49[12]; - u32 eidr1; /* External IRQ Destination 1 */ - u8 res50[12]; - u32 eivpr2; /* External IRQ Vector/Priority 2 */ - u8 res51[12]; - u32 eidr2; /* External IRQ Destination 2 */ - u8 res52[12]; - u32 eivpr3; /* External IRQ Vector/Priority 3 */ - u8 res53[12]; - u32 eidr3; /* External IRQ Destination 3 */ - u8 res54[12]; - u32 eivpr4; /* External IRQ Vector/Priority 4 */ - u8 res55[12]; - u32 eidr4; /* External IRQ Destination 4 */ - u8 res56[12]; - u32 eivpr5; /* External IRQ Vector/Priority 5 */ - u8 res57[12]; - u32 eidr5; /* External IRQ Destination 5 */ - u8 res58[12]; - u32 eivpr6; /* External IRQ Vector/Priority 6 */ - u8 res59[12]; - u32 eidr6; /* External IRQ Destination 6 */ - u8 res60[12]; - u32 eivpr7; /* External IRQ Vector/Priority 7 */ - u8 res61[12]; - u32 eidr7; /* External IRQ Destination 7 */ - u8 res62[12]; - u32 eivpr8; /* External IRQ Vector/Priority 8 */ - u8 res63[12]; - u32 eidr8; /* External IRQ Destination 8 */ - u8 res64[12]; - u32 eivpr9; /* External IRQ Vector/Priority 9 */ - u8 res65[12]; - u32 eidr9; /* External IRQ Destination 9 */ - u8 res66[12]; - u32 eivpr10; /* External IRQ Vector/Priority 10 */ - u8 res67[12]; - u32 eidr10; /* External IRQ Destination 10 */ - u8 res68[12]; - u32 eivpr11; /* External IRQ Vector/Priority 11 */ - u8 res69[12]; - u32 eidr11; /* External IRQ Destination 11 */ - u8 res70[140]; - u32 iivpr0; /* Internal IRQ Vector/Priority 0 */ - u8 res71[12]; - u32 iidr0; /* Internal IRQ Destination 0 */ - u8 res72[12]; - u32 iivpr1; /* Internal IRQ Vector/Priority 1 */ - u8 res73[12]; - u32 iidr1; /* Internal IRQ Destination 1 */ - u8 res74[12]; - u32 iivpr2; /* Internal IRQ Vector/Priority 2 */ - u8 res75[12]; - u32 iidr2; /* Internal IRQ Destination 2 */ - u8 res76[12]; - u32 iivpr3; /* Internal IRQ Vector/Priority 3 */ - u8 res77[12]; - u32 iidr3; /* Internal IRQ Destination 3 */ - u8 res78[12]; - u32 iivpr4; /* Internal IRQ Vector/Priority 4 */ - u8 res79[12]; - u32 iidr4; /* Internal IRQ Destination 4 */ - u8 res80[12]; - u32 iivpr5; /* Internal IRQ Vector/Priority 5 */ - u8 res81[12]; - u32 iidr5; /* Internal IRQ Destination 5 */ - u8 res82[12]; - u32 iivpr6; /* Internal IRQ Vector/Priority 6 */ - u8 res83[12]; - u32 iidr6; /* Internal IRQ Destination 6 */ - u8 res84[12]; - u32 iivpr7; /* Internal IRQ Vector/Priority 7 */ - u8 res85[12]; - u32 iidr7; /* Internal IRQ Destination 7 */ - u8 res86[12]; - u32 iivpr8; /* Internal IRQ Vector/Priority 8 */ - u8 res87[12]; - u32 iidr8; /* Internal IRQ Destination 8 */ - u8 res88[12]; - u32 iivpr9; /* Internal IRQ Vector/Priority 9 */ - u8 res89[12]; - u32 iidr9; /* Internal IRQ Destination 9 */ - u8 res90[12]; - u32 iivpr10; /* Internal IRQ Vector/Priority 10 */ - u8 res91[12]; - u32 iidr10; /* Internal IRQ Destination 10 */ - u8 res92[12]; - u32 iivpr11; /* Internal IRQ Vector/Priority 11 */ - u8 res93[12]; - u32 iidr11; /* Internal IRQ Destination 11 */ - u8 res94[12]; - u32 iivpr12; /* Internal IRQ Vector/Priority 12 */ - u8 res95[12]; - u32 iidr12; /* Internal IRQ Destination 12 */ - u8 res96[12]; - u32 iivpr13; /* Internal IRQ Vector/Priority 13 */ - u8 res97[12]; - u32 iidr13; /* Internal IRQ Destination 13 */ - u8 res98[12]; - u32 iivpr14; /* Internal IRQ Vector/Priority 14 */ - u8 res99[12]; - u32 iidr14; /* Internal IRQ Destination 14 */ - u8 res100[12]; - u32 iivpr15; /* Internal IRQ Vector/Priority 15 */ - u8 res101[12]; - u32 iidr15; /* Internal IRQ Destination 15 */ - u8 res102[12]; - u32 iivpr16; /* Internal IRQ Vector/Priority 16 */ - u8 res103[12]; - u32 iidr16; /* Internal IRQ Destination 16 */ - u8 res104[12]; - u32 iivpr17; /* Internal IRQ Vector/Priority 17 */ - u8 res105[12]; - u32 iidr17; /* Internal IRQ Destination 17 */ - u8 res106[12]; - u32 iivpr18; /* Internal IRQ Vector/Priority 18 */ - u8 res107[12]; - u32 iidr18; /* Internal IRQ Destination 18 */ - u8 res108[12]; - u32 iivpr19; /* Internal IRQ Vector/Priority 19 */ - u8 res109[12]; - u32 iidr19; /* Internal IRQ Destination 19 */ - u8 res110[12]; - u32 iivpr20; /* Internal IRQ Vector/Priority 20 */ - u8 res111[12]; - u32 iidr20; /* Internal IRQ Destination 20 */ - u8 res112[12]; - u32 iivpr21; /* Internal IRQ Vector/Priority 21 */ - u8 res113[12]; - u32 iidr21; /* Internal IRQ Destination 21 */ - u8 res114[12]; - u32 iivpr22; /* Internal IRQ Vector/Priority 22 */ - u8 res115[12]; - u32 iidr22; /* Internal IRQ Destination 22 */ - u8 res116[12]; - u32 iivpr23; /* Internal IRQ Vector/Priority 23 */ - u8 res117[12]; - u32 iidr23; /* Internal IRQ Destination 23 */ - u8 res118[12]; - u32 iivpr24; /* Internal IRQ Vector/Priority 24 */ - u8 res119[12]; - u32 iidr24; /* Internal IRQ Destination 24 */ - u8 res120[12]; - u32 iivpr25; /* Internal IRQ Vector/Priority 25 */ - u8 res121[12]; - u32 iidr25; /* Internal IRQ Destination 25 */ - u8 res122[12]; - u32 iivpr26; /* Internal IRQ Vector/Priority 26 */ - u8 res123[12]; - u32 iidr26; /* Internal IRQ Destination 26 */ - u8 res124[12]; - u32 iivpr27; /* Internal IRQ Vector/Priority 27 */ - u8 res125[12]; - u32 iidr27; /* Internal IRQ Destination 27 */ - u8 res126[12]; - u32 iivpr28; /* Internal IRQ Vector/Priority 28 */ - u8 res127[12]; - u32 iidr28; /* Internal IRQ Destination 28 */ - u8 res128[12]; - u32 iivpr29; /* Internal IRQ Vector/Priority 29 */ - u8 res129[12]; - u32 iidr29; /* Internal IRQ Destination 29 */ - u8 res130[12]; - u32 iivpr30; /* Internal IRQ Vector/Priority 30 */ - u8 res131[12]; - u32 iidr30; /* Internal IRQ Destination 30 */ - u8 res132[12]; - u32 iivpr31; /* Internal IRQ Vector/Priority 31 */ - u8 res133[12]; - u32 iidr31; /* Internal IRQ Destination 31 */ - u8 res134[4108]; - u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */ - u8 res135[12]; - u32 midr0; /* Messaging IRQ Destination 0 */ - u8 res136[12]; - u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */ - u8 res137[12]; - u32 midr1; /* Messaging IRQ Destination 1 */ - u8 res138[12]; - u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */ - u8 res139[12]; - u32 midr2; /* Messaging IRQ Destination 2 */ - u8 res140[12]; - u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */ - u8 res141[12]; - u32 midr3; /* Messaging IRQ Destination 3 */ - u8 res142[59852]; - u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */ - u8 res143[12]; - u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */ - u8 res144[12]; - u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */ - u8 res145[12]; - u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */ - u8 res146[12]; - u32 ctpr0; /* Current Task Priority for Processor 0 */ - u8 res147[12]; - u32 whoami0; /* Who Am I for Processor 0 */ - u8 res148[12]; - u32 iack0; /* IRQ Acknowledge for Processor 0 */ - u8 res149[12]; - u32 eoi0; /* End Of IRQ for Processor 0 */ - u8 res150[130892]; -} ccsr_pic_t; - -/* CPM Block */ -#ifndef CONFIG_CPM2 -typedef struct ccsr_cpm { - u8 res[262144]; -} ccsr_cpm_t; -#else -/* - * DPARM - * General SIU - */ -typedef struct ccsr_cpm_siu { - u8 res1[80]; - u32 smaer; - u32 smser; - u32 smevr; - u8 res2[4]; - u32 lmaer; - u32 lmser; - u32 lmevr; - u8 res3[2964]; -} ccsr_cpm_siu_t; - -/* IRQ Controller */ -typedef struct ccsr_cpm_intctl { - u16 sicr; - u8 res1[2]; - u32 sivec; - u32 sipnrh; - u32 sipnrl; - u32 siprr; - u32 scprrh; - u32 scprrl; - u32 simrh; - u32 simrl; - u32 siexr; - u8 res2[88]; - u32 sccr; - u8 res3[124]; -} ccsr_cpm_intctl_t; - -/* input/output port */ -typedef struct ccsr_cpm_iop { - u32 pdira; - u32 ppara; - u32 psora; - u32 podra; - u32 pdata; - u8 res1[12]; - u32 pdirb; - u32 pparb; - u32 psorb; - u32 podrb; - u32 pdatb; - u8 res2[12]; - u32 pdirc; - u32 pparc; - u32 psorc; - u32 podrc; - u32 pdatc; - u8 res3[12]; - u32 pdird; - u32 ppard; - u32 psord; - u32 podrd; - u32 pdatd; - u8 res4[12]; -} ccsr_cpm_iop_t; - -/* CPM timers */ -typedef struct ccsr_cpm_timer { - u8 tgcr1; - u8 res1[3]; - u8 tgcr2; - u8 res2[11]; - u16 tmr1; - u16 tmr2; - u16 trr1; - u16 trr2; - u16 tcr1; - u16 tcr2; - u16 tcn1; - u16 tcn2; - u16 tmr3; - u16 tmr4; - u16 trr3; - u16 trr4; - u16 tcr3; - u16 tcr4; - u16 tcn3; - u16 tcn4; - u16 ter1; - u16 ter2; - u16 ter3; - u16 ter4; - u8 res3[608]; -} ccsr_cpm_timer_t; - -/* SDMA */ -typedef struct ccsr_cpm_sdma { - u8 sdsr; - u8 res1[3]; - u8 sdmr; - u8 res2[739]; -} ccsr_cpm_sdma_t; - -/* FCC1 */ -typedef struct ccsr_cpm_fcc1 { - u32 gfmr; - u32 fpsmr; - u16 ftodr; - u8 res1[2]; - u16 fdsr; - u8 res2[2]; - u16 fcce; - u8 res3[2]; - u16 fccm; - u8 res4[2]; - u8 fccs; - u8 res5[3]; - u8 ftirr_phy[4]; -} ccsr_cpm_fcc1_t; - -/* FCC2 */ -typedef struct ccsr_cpm_fcc2 { - u32 gfmr; - u32 fpsmr; - u16 ftodr; - u8 res1[2]; - u16 fdsr; - u8 res2[2]; - u16 fcce; - u8 res3[2]; - u16 fccm; - u8 res4[2]; - u8 fccs; - u8 res5[3]; - u8 ftirr_phy[4]; -} ccsr_cpm_fcc2_t; - -/* FCC3 */ -typedef struct ccsr_cpm_fcc3 { - u32 gfmr; - u32 fpsmr; - u16 ftodr; - u8 res1[2]; - u16 fdsr; - u8 res2[2]; - u16 fcce; - u8 res3[2]; - u16 fccm; - u8 res4[2]; - u8 fccs; - u8 res5[3]; - u8 res[36]; -} ccsr_cpm_fcc3_t; - -/* FCC1 extended */ -typedef struct ccsr_cpm_fcc1_ext { - u32 firper; - u32 firer; - u32 firsr_h; - u32 firsr_l; - u8 gfemr; - u8 res[15]; - -} ccsr_cpm_fcc1_ext_t; - -/* FCC2 extended */ -typedef struct ccsr_cpm_fcc2_ext { - u32 firper; - u32 firer; - u32 firsr_h; - u32 firsr_l; - u8 gfemr; - u8 res[31]; -} ccsr_cpm_fcc2_ext_t; - -/* FCC3 extended */ -typedef struct ccsr_cpm_fcc3_ext { - u8 gfemr; - u8 res[47]; -} ccsr_cpm_fcc3_ext_t; - -/* TC layers */ -typedef struct ccsr_cpm_tmp1 { - u8 res[496]; -} ccsr_cpm_tmp1_t; - -/* BRGs:5,6,7,8 */ -typedef struct ccsr_cpm_brg2 { - u32 brgc5; - u32 brgc6; - u32 brgc7; - u32 brgc8; - u8 res[608]; -} ccsr_cpm_brg2_t; - -/* I2C */ -typedef struct ccsr_cpm_i2c { - u8 i2mod; - u8 res1[3]; - u8 i2add; - u8 res2[3]; - u8 i2brg; - u8 res3[3]; - u8 i2com; - u8 res4[3]; - u8 i2cer; - u8 res5[3]; - u8 i2cmr; - u8 res6[331]; -} ccsr_cpm_i2c_t; - -/* CPM core */ -typedef struct ccsr_cpm_cp { - u32 cpcr; - u32 rccr; - u8 res1[14]; - u16 rter; - u8 res2[2]; - u16 rtmr; - u16 rtscr; - u8 res3[2]; - u32 rtsr; - u8 res4[12]; -} ccsr_cpm_cp_t; - -/* BRGs:1,2,3,4 */ -typedef struct ccsr_cpm_brg1 { - u32 brgc1; - u32 brgc2; - u32 brgc3; - u32 brgc4; -} ccsr_cpm_brg1_t; - -/* SCC1-SCC4 */ -typedef struct ccsr_cpm_scc { - u32 gsmrl; - u32 gsmrh; - u16 psmr; - u8 res1[2]; - u16 todr; - u16 dsr; - u16 scce; - u8 res2[2]; - u16 sccm; - u8 res3; - u8 sccs; - u8 res4[8]; -} ccsr_cpm_scc_t; - -typedef struct ccsr_cpm_tmp2 { - u8 res[32]; -} ccsr_cpm_tmp2_t; - -/* SPI */ -typedef struct ccsr_cpm_spi { - u16 spmode; - u8 res1[4]; - u8 spie; - u8 res2[3]; - u8 spim; - u8 res3[2]; - u8 spcom; - u8 res4[82]; -} ccsr_cpm_spi_t; - -/* CPM MUX */ -typedef struct ccsr_cpm_mux { - u8 cmxsi1cr; - u8 res1; - u8 cmxsi2cr; - u8 res2; - u32 cmxfcr; - u32 cmxscr; - u8 res3[2]; - u16 cmxuar; - u8 res4[16]; -} ccsr_cpm_mux_t; - -/* SI,MCC,etc */ -typedef struct ccsr_cpm_tmp3 { - u8 res[58592]; -} ccsr_cpm_tmp3_t; - -typedef struct ccsr_cpm_iram { - u32 iram[8192]; - u8 res[98304]; -} ccsr_cpm_iram_t; - -typedef struct ccsr_cpm { - /* Some references are into the unique & known dpram spaces, - * others are from the generic base. - */ -#define im_dprambase im_dpram1 - u8 im_dpram1[16*1024]; - u8 res1[16*1024]; - u8 im_dpram2[16*1024]; - u8 res2[16*1024]; - ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ - ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ - ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ - ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ - ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ - ccsr_cpm_fcc1_t im_cpm_fcc1; - ccsr_cpm_fcc2_t im_cpm_fcc2; - ccsr_cpm_fcc3_t im_cpm_fcc3; - ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; - ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; - ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; - ccsr_cpm_tmp1_t im_cpm_tmp1; - ccsr_cpm_brg2_t im_cpm_brg2; - ccsr_cpm_i2c_t im_cpm_i2c; - ccsr_cpm_cp_t im_cpm_cp; - ccsr_cpm_brg1_t im_cpm_brg1; - ccsr_cpm_scc_t im_cpm_scc[4]; - ccsr_cpm_tmp2_t im_cpm_tmp2; - ccsr_cpm_spi_t im_cpm_spi; - ccsr_cpm_mux_t im_cpm_mux; - ccsr_cpm_tmp3_t im_cpm_tmp3; - ccsr_cpm_iram_t im_cpm_iram; -} ccsr_cpm_t; -#endif - -/* RapidIO Registers */ -typedef struct ccsr_rio { - u32 didcar; /* Device Identity Capability */ - u32 dicar; /* Device Information Capability */ - u32 aidcar; /* Assembly Identity Capability */ - u32 aicar; /* Assembly Information Capability */ - u32 pefcar; /* Processing Element Features Capability */ - u32 spicar; /* Switch Port Information Capability */ - u32 socar; /* Source Operations Capability */ - u32 docar; /* Destination Operations Capability */ - u8 res1[32]; - u32 msr; /* Mailbox Cmd And Status */ - u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ - u8 res2[4]; - u32 pellccsr; /* Processing Element Logic Layer CCSR */ - u8 res3[12]; - u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ - u32 bdidcsr; /* Base Device ID Cmd & Status */ - u8 res4[4]; - u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ - u32 ctcsr; /* Component Tag Cmd & Status */ - u8 res5[144]; - u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ - u8 res6[28]; - u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ - u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ - u8 res7[20]; - u32 pgccsr; /* Port General Cmd & Status */ - u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ - u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ - u32 plascsr; /* Port Local Ackid Status Cmd & Status */ - u8 res8[12]; - u32 pescsr; /* Port Error & Status Cmd & Status */ - u32 pccsr; /* Port Control Cmd & Status */ - u8 res9[65184]; - u32 cr; /* Port Control Cmd & Status */ - u8 res10[12]; - u32 pcr; /* Port Configuration */ - u32 peir; /* Port Error Injection */ - u8 res11[3048]; - u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ - u8 res12[12]; - u32 rowar0; /* RIO Outbound Attrs 0 */ - u8 res13[12]; - u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ - u8 res14[4]; - u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ - u8 res15[4]; - u32 rowar1; /* RIO Outbound Attrs 1 */ - u8 res16[12]; - u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ - u8 res17[4]; - u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ - u8 res18[4]; - u32 rowar2; /* RIO Outbound Attrs 2 */ - u8 res19[12]; - u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ - u8 res20[4]; - u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ - u8 res21[4]; - u32 rowar3; /* RIO Outbound Attrs 3 */ - u8 res22[12]; - u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ - u8 res23[4]; - u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ - u8 res24[4]; - u32 rowar4; /* RIO Outbound Attrs 4 */ - u8 res25[12]; - u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ - u8 res26[4]; - u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ - u8 res27[4]; - u32 rowar5; /* RIO Outbound Attrs 5 */ - u8 res28[12]; - u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ - u8 res29[4]; - u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ - u8 res30[4]; - u32 rowar6; /* RIO Outbound Attrs 6 */ - u8 res31[12]; - u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ - u8 res32[4]; - u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ - u8 res33[4]; - u32 rowar7; /* RIO Outbound Attrs 7 */ - u8 res34[12]; - u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ - u8 res35[4]; - u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ - u8 res36[4]; - u32 rowar8; /* RIO Outbound Attrs 8 */ - u8 res37[76]; - u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ - u8 res38[4]; - u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ - u8 res39[4]; - u32 riwar4; /* RIO Inbound Attrs 4 */ - u8 res40[12]; - u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ - u8 res41[4]; - u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ - u8 res42[4]; - u32 riwar3; /* RIO Inbound Attrs 3 */ - u8 res43[12]; - u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ - u8 res44[4]; - u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ - u8 res45[4]; - u32 riwar2; /* RIO Inbound Attrs 2 */ - u8 res46[12]; - u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ - u8 res47[4]; - u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ - u8 res48[4]; - u32 riwar1; /* RIO Inbound Attrs 1 */ - u8 res49[12]; - u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ - u8 res50[12]; - u32 riwar0; /* RIO Inbound Attrs 0 */ - u8 res51[12]; - u32 pnfedr; /* Port Notification/Fatal Error Detect */ - u32 pnfedir; /* Port Notification/Fatal Error Detect */ - u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ - u32 pecr; /* Port Error Control */ - u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ - u32 pepr1; /* Port Error Packet 1 */ - u32 pepr2; /* Port Error Packet 2 */ - u8 res52[4]; - u32 predr; /* Port Recoverable Error Detect */ - u8 res53[4]; - u32 pertr; /* Port Error Recovery Threshold */ - u32 prtr; /* Port Retry Threshold */ - u8 res54[464]; - u32 omr; /* Outbound Mode */ - u32 osr; /* Outbound Status */ - u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ - u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ - u32 eosar; /* Extended Outbound Unit Source Addr */ - u32 osar; /* Outbound Unit Source Addr */ - u32 odpr; /* Outbound Destination Port */ - u32 odatr; /* Outbound Destination Attrs */ - u32 odcr; /* Outbound Doubleword Count */ - u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ - u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ - u8 res55[52]; - u32 imr; /* Outbound Mode */ - u32 isr; /* Inbound Status */ - u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ - u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ - u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ - u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ - u8 res56[1000]; - u32 dmr; /* Doorbell Mode */ - u32 dsr; /* Doorbell Status */ - u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ - u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ - u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ - u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ - u8 res57[104]; - u32 pwmr; /* Port-Write Mode */ - u32 pwsr; /* Port-Write Status */ - u32 epwqbar; /* Extended Port-Write Queue Base Addr */ - u32 pwqbar; /* Port-Write Queue Base Addr */ - u8 res58[60176]; -} ccsr_rio_t; - -/* Quick Engine Block Pin Muxing Registers */ -typedef struct par_io { - u32 cpodr; - u32 cpdat; - u32 cpdir1; - u32 cpdir2; - u32 cppar1; - u32 cppar2; - u8 res[8]; -} par_io_t; - -#ifdef CONFIG_SYS_FSL_CPC -/* - * Define a single offset that is the start of all the CPC register - * blocks - if there is more than one CPC, we expect these to be - * contiguous 4k regions - */ - -typedef struct cpc_corenet { - u32 cpccsr0; /* Config/status reg */ - u32 res1; - u32 cpccfg0; /* Configuration register */ - u32 res2; - u32 cpcewcr0; /* External Write reg 0 */ - u32 cpcewabr0; /* External write base reg 0 */ - u32 res3[2]; - u32 cpcewcr1; /* External Write reg 1 */ - u32 cpcewabr1; /* External write base reg 1 */ - u32 res4[54]; - u32 cpcsrcr1; /* SRAM control reg 1 */ - u32 cpcsrcr0; /* SRAM control reg 0 */ - u32 res5[62]; - struct { - u32 id; /* partition ID */ - u32 res; - u32 alloc; /* partition allocation */ - u32 way; /* partition way */ - } partition_regs[16]; - u32 res6[704]; - u32 cpcerrinjhi; /* Error injection high */ - u32 cpcerrinjlo; /* Error injection lo */ - u32 cpcerrinjctl; /* Error injection control */ - u32 res7[5]; - u32 cpccaptdatahi; /* capture data high */ - u32 cpccaptdatalo; /* capture data low */ - u32 cpcaptecc; /* capture ECC */ - u32 res8[5]; - u32 cpcerrdet; /* error detect */ - u32 cpcerrdis; /* error disable */ - u32 cpcerrinten; /* errir interrupt enable */ - u32 cpcerrattr; /* error attribute */ - u32 cpcerreaddr; /* error extended address */ - u32 cpcerraddr; /* error address */ - u32 cpcerrctl; /* error control */ - u32 res9[105]; /* pad out to 4k */ -} cpc_corenet_t; - -#define CPC_CSR0_CE 0x80000000 /* Cache Enable */ -#define CPC_CSR0_PE 0x40000000 /* Enable ECC */ -#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ -#define CPC_CSR0_WT 0x00080000 /* Write-through mode */ -#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ -#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ -#define CPC_CFG0_SZ_MASK 0x00003fff -#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) -#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) -#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) -#define CPC_SRCR1_SRBARU_MASK 0x0000ffff -#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ - & CPC_SRCR1_SRBARU_MASK) -#define CPC_SRCR0_SRBARL_MASK 0xffff8000 -#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) -#define CPC_SRCR0_INTLVEN 0x00000100 -#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 -#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 -#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 -#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 -#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 -#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a -#define CPC_SRCR0_SRAMEN 0x00000001 -#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ -#endif /* CONFIG_SYS_FSL_CPC */ - -/* Global Utilities Block */ -#ifdef CONFIG_FSL_CORENET -typedef struct ccsr_gur { - u32 porsr1; /* POR status */ - u8 res1[28]; - u32 gpporcr1; /* General-purpose POR configuration */ - u8 res2[12]; - u32 gpiocr; /* GPIO control */ - u8 res3[12]; - u32 gpoutdr; /* General-purpose output data */ - u8 res4[12]; - u32 gpindr; /* General-purpose input data */ - u8 res5[12]; - u32 pmuxcr; /* Alt function signal multiplex control */ - u8 res6[12]; - u32 devdisr; /* Device disable control */ -#define FSL_CORENET_DEVDISR_PCIE1 0x80000000 -#define FSL_CORENET_DEVDISR_PCIE2 0x40000000 -#define FSL_CORENET_DEVDISR_PCIE3 0x20000000 -#define FSL_CORENET_DEVDISR_RMU 0x08000000 -#define FSL_CORENET_DEVDISR_SRIO1 0x04000000 -#define FSL_CORENET_DEVDISR_SRIO2 0x02000000 -#define FSL_CORENET_DEVDISR_DMA1 0x00400000 -#define FSL_CORENET_DEVDISR_DMA2 0x00200000 -#define FSL_CORENET_DEVDISR_DDR1 0x00100000 -#define FSL_CORENET_DEVDISR_DDR2 0x00080000 -#define FSL_CORENET_DEVDISR_DBG 0x00010000 -#define FSL_CORENET_DEVDISR_NAL 0x00008000 -#define FSL_CORENET_DEVDISR_ELBC 0x00001000 -#define FSL_CORENET_DEVDISR_USB1 0x00000800 -#define FSL_CORENET_DEVDISR_USB2 0x00000400 -#define FSL_CORENET_DEVDISR_ESDHC 0x00000100 -#define FSL_CORENET_DEVDISR_GPIO 0x00000080 -#define FSL_CORENET_DEVDISR_ESPI 0x00000040 -#define FSL_CORENET_DEVDISR_I2C1 0x00000020 -#define FSL_CORENET_DEVDISR_I2C2 0x00000010 -#define FSL_CORENET_DEVDISR_DUART1 0x00000002 -#define FSL_CORENET_DEVDISR_DUART2 0x00000001 - u8 res7[12]; - u32 powmgtcsr; /* Power management status & control */ - u8 res8[12]; - u32 coredisru; /* uppper portion for support of 64 cores */ - u32 coredisrl; /* lower portion for support of 64 cores */ - u8 res9[8]; - u32 pvr; /* Processor version */ - u32 svr; /* System version */ - u8 res10[8]; - u32 rstcr; /* Reset control */ - u32 rstrqpblsr; /* Reset request preboot loader status */ - u8 res11[8]; - u32 rstrqmr1; /* Reset request mask */ - u8 res12[4]; - u32 rstrqsr1; /* Reset request status */ - u8 res13[4]; - u8 res14[4]; - u32 rstrqwdtmrl; /* Reset request WDT mask */ - u8 res15[4]; - u32 rstrqwdtsrl; /* Reset request WDT status */ - u8 res16[4]; - u32 brrl; /* Boot release */ - u8 res17[24]; - u32 rcwsr[16]; /* Reset control word status */ -#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 -#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000 -#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15 -#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 -#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 -#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 - u8 res18[192]; - u32 scratchrw[4]; /* Scratch Read/Write */ - u8 res19[240]; - u32 scratchw1r[4]; /* Scratch Read (Write once) */ - u8 res20[240]; - u32 scrtsr[8]; /* Core reset status */ - u8 res21[224]; - u32 pex1liodnr; /* PCI Express 1 LIODN */ - u32 pex2liodnr; /* PCI Express 2 LIODN */ - u32 pex3liodnr; /* PCI Express 3 LIODN */ - u32 pex4liodnr; /* PCI Express 4 LIODN */ - u32 rio1liodnr; /* RIO 1 LIODN */ - u32 rio2liodnr; /* RIO 2 LIODN */ - u32 rio3liodnr; /* RIO 3 LIODN */ - u32 rio4liodnr; /* RIO 4 LIODN */ - u32 usb1liodnr; /* USB 1 LIODN */ - u32 usb2liodnr; /* USB 2 LIODN */ - u32 usb3liodnr; /* USB 3 LIODN */ - u32 usb4liodnr; /* USB 4 LIODN */ - u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */ - u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ - u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ - u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ - u32 rmuliodnr; /* RIO Message Unit LIODN */ - u32 rduliodnr; /* RIO Doorbell Unit LIODN */ - u32 rpwuliodnr; /* RIO Port Write Unit LIODN */ - u8 res22[52]; - u32 dma1liodnr; /* DMA 1 LIODN */ - u32 dma2liodnr; /* DMA 2 LIODN */ - u32 dma3liodnr; /* DMA 3 LIODN */ - u32 dma4liodnr; /* DMA 4 LIODN */ - u8 res23[48]; - u8 res24[64]; - u32 pblsr; /* Preboot loader status */ - u32 pamubypenr; /* PAMU bypass enable */ - u32 dmacr1; /* DMA control */ - u8 res25[4]; - u32 gensr1; /* General status */ - u8 res26[12]; - u32 gencr1; /* General control */ - u8 res27[12]; - u8 res28[4]; - u32 cgensrl; /* Core general status */ - u8 res29[8]; - u8 res30[4]; - u32 cgencrl; /* Core general control */ - u8 res31[184]; - u32 sriopstecr; /* SRIO prescaler timer enable control */ - u8 res32[2300]; -} ccsr_gur_t; - -typedef struct ccsr_clk { - u32 clkc0csr; /* Core 0 Clock control/status */ - u8 res1[0x1c]; - u32 clkc1csr; /* Core 1 Clock control/status */ - u8 res2[0x1c]; - u32 clkc2csr; /* Core 2 Clock control/status */ - u8 res3[0x1c]; - u32 clkc3csr; /* Core 3 Clock control/status */ - u8 res4[0x1c]; - u32 clkc4csr; /* Core 4 Clock control/status */ - u8 res5[0x1c]; - u32 clkc5csr; /* Core 5 Clock control/status */ - u8 res6[0x1c]; - u32 clkc6csr; /* Core 6 Clock control/status */ - u8 res7[0x1c]; - u32 clkc7csr; /* Core 7 Clock control/status */ - u8 res8[0x71c]; - u32 pllc1gsr; /* Cluster PLL 1 General Status */ - u8 res10[0x1c]; - u32 pllc2gsr; /* Cluster PLL 2 General Status */ - u8 res11[0x1c]; - u32 pllc3gsr; /* Cluster PLL 3 General Status */ - u8 res12[0x1c]; - u32 pllc4gsr; /* Cluster PLL 4 General Status */ - u8 res13[0x39c]; - u32 pllpgsr; /* Platform PLL General Status */ - u8 res14[0x1c]; - u32 plldgsr; /* DDR PLL General Status */ - u8 res15[0x3dc]; -} ccsr_clk_t; - -typedef struct ccsr_rcpm { - u8 res1[4]; - u32 cdozsrl; /* Core Doze Status */ - u8 res2[4]; - u32 cdozcrl; /* Core Doze Control */ - u8 res3[4]; - u32 cnapsrl; /* Core Nap Status */ - u8 res4[4]; - u32 cnapcrl; /* Core Nap Control */ - u8 res5[4]; - u32 cdozpsrl; /* Core Doze Previous Status */ - u8 res6[4]; - u32 cdozpcrl; /* Core Doze Previous Control */ - u8 res7[4]; - u32 cwaitsrl; /* Core Wait Status */ - u8 res8[8]; - u32 powmgtcsr; /* Power Mangement Control & Status */ - u8 res9[12]; - u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */ - u8 res10[12]; - u8 res11[4]; - u32 cpmimrl; /* Core PM IRQ Masking */ - u8 res12[4]; - u32 cpmcimrl; /* Core PM Critical IRQ Masking */ - u8 res13[4]; - u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */ - u8 res14[4]; - u32 cpmnmimrl; /* Core PM NMI Masking */ - u8 res15[4]; - u32 ctbenrl; /* Core Time Base Enable */ - u8 res16[4]; - u32 ctbclkselrl; /* Core Time Base Clock Select */ - u8 res17[4]; - u32 ctbhltcrl; /* Core Time Base Halt Control */ - u8 res18[0xf68]; -} ccsr_rcpm_t; - -#else -typedef struct ccsr_gur { - u32 porpllsr; /* POR PLL ratio status */ -#ifdef CONFIG_MPC8536 -#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 -#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 -#else -#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 -#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 -#endif -#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 -#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 -#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e -#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 - u32 porbmsr; /* POR boot mode status */ -#define MPC85xx_PORBMSR_HA 0x00070000 -#define MPC85xx_PORBMSR_HA_SHIFT 16 - u32 porimpscr; /* POR I/O impedance status & control */ - u32 pordevsr; /* POR I/O device status regsiter */ -#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 -#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 -#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 -#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 -#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 -#define MPC85xx_PORDEVSR_PCI1 0x00800000 -#define MPC85xx_PORDEVSR_IO_SEL 0x00780000 -#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 -#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 -#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 -#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 -#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 -#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 -#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 -#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 -#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 - u32 pordbgmsr; /* POR debug mode status */ - u32 pordevsr2; /* POR I/O device status 2 */ -/* The 8544 RM says this is bit 26, but it's really bit 24 */ -#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 - u8 res1[8]; - u32 gpporcr; /* General-purpose POR configuration */ - u8 res2[12]; - u32 gpiocr; /* GPIO control */ - u8 res3[12]; -#if defined(CONFIG_MPC8569) - u32 plppar1; /* Platform port pin assignment 1 */ - u32 plppar2; /* Platform port pin assignment 2 */ - u32 plpdir1; /* Platform port pin direction 1 */ - u32 plpdir2; /* Platform port pin direction 2 */ -#else - u32 gpoutdr; /* General-purpose output data */ - u8 res4[12]; -#endif - u32 gpindr; /* General-purpose input data */ - u8 res5[12]; - u32 pmuxcr; /* Alt. function signal multiplex control */ -#define MPC85xx_PMUXCR_SD_DATA 0x80000000 -#define MPC85xx_PMUXCR_SDHC_CD 0x40000000 -#define MPC85xx_PMUXCR_SDHC_WP 0x20000000 - u8 res6[12]; - u32 devdisr; /* Device disable control */ -#define MPC85xx_DEVDISR_PCI1 0x80000000 -#define MPC85xx_DEVDISR_PCI2 0x40000000 -#define MPC85xx_DEVDISR_PCIE 0x20000000 -#define MPC85xx_DEVDISR_LBC 0x08000000 -#define MPC85xx_DEVDISR_PCIE2 0x04000000 -#define MPC85xx_DEVDISR_PCIE3 0x02000000 -#define MPC85xx_DEVDISR_SEC 0x01000000 -#define MPC85xx_DEVDISR_SRIO 0x00080000 -#define MPC85xx_DEVDISR_RMSG 0x00040000 -#define MPC85xx_DEVDISR_DDR 0x00010000 -#define MPC85xx_DEVDISR_CPU 0x00008000 -#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU -#define MPC85xx_DEVDISR_TB 0x00004000 -#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB -#define MPC85xx_DEVDISR_CPU1 0x00002000 -#define MPC85xx_DEVDISR_TB1 0x00001000 -#define MPC85xx_DEVDISR_DMA 0x00000400 -#define MPC85xx_DEVDISR_TSEC1 0x00000080 -#define MPC85xx_DEVDISR_TSEC2 0x00000040 -#define MPC85xx_DEVDISR_TSEC3 0x00000020 -#define MPC85xx_DEVDISR_TSEC4 0x00000010 -#define MPC85xx_DEVDISR_I2C 0x00000004 -#define MPC85xx_DEVDISR_DUART 0x00000002 - u8 res7[12]; - u32 powmgtcsr; /* Power management status & control */ - u8 res8[12]; - u32 mcpsumr; /* Machine check summary */ - u8 res9[12]; - u32 pvr; /* Processor version */ - u32 svr; /* System version */ - u8 res10a[8]; - u32 rstcr; /* Reset control */ -#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) - u8 res10b[76]; - par_io_t qe_par_io[7]; - u8 res10c[3136]; -#else - u8 res10b[3404]; -#endif - u32 clkocr; /* Clock out select */ - u8 res11[12]; - u32 ddrdllcr; /* DDR DLL control */ - u8 res12[12]; - u32 lbcdllcr; /* LBC DLL control */ - u8 res13[248]; - u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ - u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ - u32 ddrioovcr; /* DDR IO Override Control */ - u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ - u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ - u8 res15[61648]; -} ccsr_gur_t; -#endif - -typedef struct serdes_corenet { - struct { - u32 rstctl; /* Reset Control Register */ -#define SRDS_RSTCTL_RST 0x80000000 -#define SRDS_RSTCTL_RSTDONE 0x40000000 -#define SRDS_RSTCTL_RSTERR 0x20000000 - u32 pllcr0; /* PLL Control Register 0 */ - u32 pllcr1; /* PLL Control Register 1 */ -#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 - u32 res[5]; - } bank[3]; - u32 res1[12]; - u32 srdstcalcr; /* TX Calibration Control */ - u32 res2[3]; - u32 srdsrcalcr; /* RX Calibration Control */ - u32 res3[3]; - u32 srdsgr0; /* General Register 0 */ - u32 res4[11]; - u32 srdspccr0; /* Protocol Converter Config 0 */ - u32 srdspccr1; /* Protocol Converter Config 1 */ - u32 srdspccr2; /* Protocol Converter Config 2 */ -#define SRDS_PCCR2_RST_XGMII1 0x00800000 -#define SRDS_PCCR2_RST_XGMII2 0x00400000 - u32 res5[197]; - struct { - u32 gcr0; /* General Control Register 0 */ -#define SRDS_GCR0_RRST 0x00400000 -#define SRDS_GCR0_1STLANE 0x00010000 - u32 gcr1; /* General Control Register 1 */ -#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 -#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 -#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 -#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 -#define SRDS_GCR1_OPAD_CTL 0x04000000 - u32 res1[4]; - u32 tecr0; /* TX Equalization Control Reg 0 */ -#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 -#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 - u32 res3; - u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ - u32 res4[7]; - } lane[24]; - u32 res6[384]; -} serdes_corenet_t; - -enum { - FSL_SRDS_B1_LANE_A = 0, - FSL_SRDS_B1_LANE_B = 1, - FSL_SRDS_B1_LANE_C = 2, - FSL_SRDS_B1_LANE_D = 3, - FSL_SRDS_B1_LANE_E = 4, - FSL_SRDS_B1_LANE_F = 5, - FSL_SRDS_B1_LANE_G = 6, - FSL_SRDS_B1_LANE_H = 7, - FSL_SRDS_B1_LANE_I = 8, - FSL_SRDS_B1_LANE_J = 9, - FSL_SRDS_B2_LANE_A = 16, - FSL_SRDS_B2_LANE_B = 17, - FSL_SRDS_B2_LANE_C = 18, - FSL_SRDS_B2_LANE_D = 19, - FSL_SRDS_B3_LANE_A = 20, - FSL_SRDS_B3_LANE_B = 21, - FSL_SRDS_B3_LANE_C = 22, - FSL_SRDS_B3_LANE_D = 23, -}; - -#ifdef CONFIG_FSL_CORENET -#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 -#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 -#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 -#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 -#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 -#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 -#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 -#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 -#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 -#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 -#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 -#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 -#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 -#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 -#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 -#else -#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 -#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 -#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 -#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000 -#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 -#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 -#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 -#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 -#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 -#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 -#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 -#ifdef CONFIG_TSECV2 -#define CONFIG_SYS_TSEC1_OFFSET 0xB0000 -#else -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#endif -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 -#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 -#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 -#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 -#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 -#endif - -#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 -#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 - -#define CONFIG_SYS_FSL_CPC_ADDR \ - (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) -#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) -#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) -#define CONFIG_SYS_MPC85xx_GUTS_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) -#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) -#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) -#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) -#define CONFIG_SYS_MPC85xx_ECM_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC85xx_LBC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_MPC85xx_ESPI_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) -#define CONFIG_SYS_MPC85xx_GPIO_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) -#define CONFIG_SYS_MPC85xx_L2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) -#define CONFIG_SYS_MPC85xx_DMA_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) -#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) -#define CONFIG_SYS_MPC85xx_CPM_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) -#define CONFIG_SYS_MPC85xx_USB_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) - -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) - -#endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h deleted file mode 100644 index fd7acdb..0000000 --- a/include/asm-ppc/immap_86xx.h +++ /dev/null @@ -1,1310 +0,0 @@ -/* - * MPC86xx Internal Memory Map - * - * Copyright 2004 Freescale Semiconductor - * Jeff Brown (Jeffrey@freescale.com) - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - * - */ - -#ifndef __IMMAP_86xx__ -#define __IMMAP_86xx__ - -#include -#include -#include - -/* Local-Access Registers and MCM Registers(0x0000-0x2000) */ -typedef struct ccsr_local_mcm { - uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ - char res1[4]; - uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ - char res2[4]; - uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ - char res3[12]; - uint bptr; /* 0x20 - Boot Page Translation Register */ - char res4[3044]; - uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ - char res5[4]; - uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ - char res6[20]; - uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ - char res7[4]; - uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ - char res8[20]; - uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ - char res9[4]; - uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ - char res10[20]; - uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ - char res11[4]; - uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ - char res12[20]; - uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ - char res13[4]; - uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ - char res14[20]; - uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ - char res15[4]; - uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ - char res16[20]; - uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ - char res17[4]; - uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ - char res18[20]; - uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ - char res19[4]; - uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[20]; - uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ - char res21[4]; - uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ - char res22[20]; - uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ - char res23[4]; - uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ - char res24[716]; - uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ - char res25[4]; - uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ - char res26[4]; - uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ - char res27[44]; - uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ - uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ - uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ - uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ - char res28[16]; - uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ - uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ - uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ - char res29[3476]; - uint edr; /* 0x1e00 - MCM Error Detect Register */ - char res30[4]; - uint eer; /* 0x1e08 - MCM Error Enable Register */ - uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */ - uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */ - uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ - char res31[488]; -} ccsr_local_mcm_t; - -/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */ - -typedef struct ccsr_ddr { - uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ - char res1[4]; - uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ - char res2[4]; - uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ - char res3[4]; - uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ - char res4[4]; - uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */ - char res5[4]; - uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */ - char res6[84]; - uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ - uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ - uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ - uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ - uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ - uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ - char res7[104]; - uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ - uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ - uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ - uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ - uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */ - uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ - uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ - uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ - uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ - uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ - uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ - char res8[4]; - uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ - char res9[12]; - uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ - uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ - uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */ - char res10[2728]; - uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ - uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ - char res11[512]; - uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ - uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ - uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ - char res12[20]; - uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ - uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ - uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ - char res13[20]; - uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ - uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ - uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ - uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ - uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ - uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ - uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ - char res14[164]; - uint debug_1; /* 0x2f00 */ - uint debug_2; - uint debug_3; - uint debug_4; - uint debug_5; - char res15[236]; -} ccsr_ddr_t; - - -/* Daul I2C Registers(0x3000-0x4000) */ -typedef struct ccsr_i2c { - struct fsl_i2c i2c[2]; - u8 res[4096 - 2 * sizeof(struct fsl_i2c)]; -} ccsr_i2c_t; - -/* DUART Registers(0x4000-0x5000) */ -typedef struct ccsr_duart { - char res1[1280]; - u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ - u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ - u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ - u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ - u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ - u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ - u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ - u_char uscr1; /* 0x4507 - UART1 Scratch Register */ - char res2[8]; - u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ - char res3[239]; - u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ - u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ - u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ - u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ - u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ - u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ - u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ - u_char uscr2; /* 0x4607 - UART2 Scratch Register */ - char res4[8]; - u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ - char res5[2543]; -} ccsr_duart_t; - - -/* Local Bus Controller Registers(0x5000-0x6000) */ -typedef struct ccsr_lbc { - uint br0; /* 0x5000 - LBC Base Register 0 */ - uint or0; /* 0x5004 - LBC Options Register 0 */ - uint br1; /* 0x5008 - LBC Base Register 1 */ - uint or1; /* 0x500c - LBC Options Register 1 */ - uint br2; /* 0x5010 - LBC Base Register 2 */ - uint or2; /* 0x5014 - LBC Options Register 2 */ - uint br3; /* 0x5018 - LBC Base Register 3 */ - uint or3; /* 0x501c - LBC Options Register 3 */ - uint br4; /* 0x5020 - LBC Base Register 4 */ - uint or4; /* 0x5024 - LBC Options Register 4 */ - uint br5; /* 0x5028 - LBC Base Register 5 */ - uint or5; /* 0x502c - LBC Options Register 5 */ - uint br6; /* 0x5030 - LBC Base Register 6 */ - uint or6; /* 0x5034 - LBC Options Register 6 */ - uint br7; /* 0x5038 - LBC Base Register 7 */ - uint or7; /* 0x503c - LBC Options Register 7 */ - char res1[40]; - uint mar; /* 0x5068 - LBC UPM Address Register */ - char res2[4]; - uint mamr; /* 0x5070 - LBC UPMA Mode Register */ - uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ - uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ - char res3[8]; - uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ - uint mdr; /* 0x5088 - LBC UPM Data Register */ - char res4[8]; - uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ - char res5[8]; - uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ - uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ - char res6[8]; - uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ - uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ - uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ - uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ - uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ - char res7[12]; - uint lbcr; /* 0x50d0 - LBC Configuration Register */ - uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ - char res8[3880]; -} ccsr_lbc_t; - -/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */ -typedef struct ccsr_pex { - uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ - uint cfg_data; /* 0x8004 - PEX Configuration Data Register */ - char res1[4]; - uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */ - char res2[16]; - uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ - uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */ - uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */ - uint pm_command; /* 0x802c - PEX PM Command register */ - char res3[3016]; - uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ - uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ - uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */ - uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */ - char res4[8]; - uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */ - char res5[12]; - uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */ - uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */ - uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */ - char res6[4]; - uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */ - char res7[12]; - uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */ - uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */ - uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */ - char res8[4]; - uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */ - char res9[12]; - uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */ - uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */ - uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */ - char res10[4]; - uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */ - char res11[12]; - uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */ - uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */ - uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */ - char res12[4]; - uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */ - char res13[12]; - char res14[256]; - uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */ - char res15[4]; - uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */ - uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */ - uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */ - char res16[12]; - uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */ - char res17[4]; - uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */ - uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */ - uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ - char res18[12]; - uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */ - char res19[4]; - uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */ - uint piwbear1; - uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */ - char res20[12]; - uint pedr; /* 0x8e00 - PEX Error Detect Register */ - char res21[4]; - uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */ - char res22[4]; - uint pecdr; /* 0x8e10 - PEX Error Disable Register */ - char res23[12]; - uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */ - char res24[4]; - uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */ - uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */ - uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */ - uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */ - char res25[452]; - char res26[4]; -} ccsr_pex_t; - -/* Hyper Transport Register Block (0xA000-0xB000) */ -typedef struct ccsr_ht { - uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ - uint hcfg_data; /* 0xa004 - HT Configuration Data register */ - char res1[3064]; - uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ - char res2[12]; - uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ - char res3[12]; - uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ - char res4[4]; - uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ - char res5[4]; - uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ - char res6[12]; - uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ - char res7[4]; - uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ - char res8[4]; - uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ - char res9[12]; - uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ - char res10[4]; - uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ - char res11[4]; - uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ - char res12[12]; - uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ - char res13[4]; - uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ - char res14[4]; - uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ - char res15[236]; - uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ - char res16[4]; - uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ - char res17[4]; - uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ - char res18[12]; - uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ - char res19[4]; - uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ - char res20[4]; - uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ - char res21[12]; - uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ - char res22[4]; - uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ - char res23[4]; - uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ - char res24[12]; - uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ - char res25[4]; - uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ - char res26[4]; - uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ - char res27[12]; - uint hedr; /* 0xae00 - HT Error Detect register */ - char res28[4]; - uint heier; /* 0xae08 - HT Error Interrupt Enable register */ - char res29[4]; - uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ - char res30[12]; - uint hecsr; /* 0xae20 - HT Error Capture Status register */ - char res31[4]; - uint hec0; /* 0xae28 - HT Error Capture 0 register */ - uint hec1; /* 0xae2c - HT Error Capture 1 register */ - uint hec2; /* 0xae30 - HT Error Capture 2 register */ - char res32[460]; -} ccsr_ht_t; - -/* DMA Registers(0x2_1000-0x2_2000) */ -typedef struct ccsr_dma { - char res1[256]; - struct fsl_dma dma[4]; - uint dgsr; /* 0x21300 - DMA General Status Register */ - char res2[3324]; -} ccsr_dma_t; - -/* tsec1-4: 24000-28000 */ -typedef struct ccsr_tsec { - uint id; /* 0x24000 - Controller ID Register */ - char res1[12]; - uint ievent; /* 0x24010 - Interrupt Event Register */ - uint imask; /* 0x24014 - Interrupt Mask Register */ - uint edis; /* 0x24018 - Error Disabled Register */ - char res2[4]; - uint ecntrl; /* 0x24020 - Ethernet Control Register */ - char res2_1[4]; - uint ptv; /* 0x24028 - Pause Time Value Register */ - uint dmactrl; /* 0x2402c - DMA Control Register */ - uint tbipa; /* 0x24030 - TBI PHY Address Register */ - char res3[88]; - uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ - char res4[8]; - uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ - uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */ - char res4_1[4]; - uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ - uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ - char res5[84]; - uint tctrl; /* 0x24100 - Transmit Control Register */ - uint tstat; /* 0x24104 - Transmit Status Register */ - uint dfvlan; /* 0x24108 - Default VLAN control word */ - char res6[4]; - uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ - uint tqueue; /* 0x24114 - Transmit Queue Control Register */ - char res7[40]; - uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ - uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ - char res8[52]; - uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ - char res9[4]; - uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ - char res10[4]; - uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ - char res11[4]; - uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ - char res12[4]; - uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ - char res13[4]; - uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ - char res14[4]; - uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ - char res15[4]; - uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ - char res16[4]; - uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ - char res17[64]; - uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ - uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */ - char res18[4]; - uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ - char res19[4]; - uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ - char res20[4]; - uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ - char res21[4]; - uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ - char res22[4]; - uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ - char res23[4]; - uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ - char res24[4]; - uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ - char res25[192]; - uint rctrl; /* 0x24300 - Receive Control Register */ - uint rstat; /* 0x24304 - Receive Status Register */ - char res26[8]; - uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ - uint rqueue; /* 0x24314 - Receive queue control register */ - char res27[24]; - uint rbifx; /* 0x24330 - Receive bit field extract control Register */ - uint rqfar; /* 0x24334 - Receive queue filing table address Register */ - uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ - uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ - uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ - char res28[56]; - uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ - char res29[4]; - uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ - char res30[4]; - uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ - char res31[4]; - uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ - char res32[4]; - uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ - char res33[4]; - uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ - char res34[4]; - uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ - char res35[4]; - uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ - char res36[4]; - uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ - char res37[64]; - uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ - uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */ - char res38[4]; - uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */ - char res39[4]; - uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */ - char res40[4]; - uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */ - char res41[4]; - uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */ - char res42[4]; - uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */ - char res43[4]; - uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */ - char res44[4]; - uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */ - char res45[192]; - uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ - uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ - uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ - uint hafdup; /* 0x2450c - Half Duplex Register */ - uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ - char res46[12]; - uint miimcfg; /* 0x24520 - MII Management Configuration Register */ - uint miimcom; /* 0x24524 - MII Management Command Register */ - uint miimadd; /* 0x24528 - MII Management Address Register */ - uint miimcon; /* 0x2452c - MII Management Control Register */ - uint miimstat; /* 0x24530 - MII Management Status Register */ - uint miimind; /* 0x24534 - MII Management Indicator Register */ - uint ifctrl; /* 0x24538 - Interface Contrl Register */ - uint ifstat; /* 0x2453c - Interface Status Register */ - uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ - uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ - uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ - uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ - uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ - uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ - uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ - uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ - uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ - uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ - uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ - uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ - uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ - uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ - uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ - uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ - uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ - uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ - uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ - uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ - uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ - uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ - uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ - uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ - uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ - uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ - uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ - uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ - uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ - uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ - uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ - uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ - char res48[192]; - uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ - uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ - uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ - uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ - uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ - uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ - uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ - uint rbyt; /* 0x2469c - Receive Byte Counter */ - uint rpkt; /* 0x246a0 - Receive Packet Counter */ - uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ - uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ - uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ - uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ - uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ - uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ - uint raln; /* 0x246bc - Receive Alignment Error Counter */ - uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ - uint rcde; /* 0x246c4 - Receive Code Error Counter */ - uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ - uint rund; /* 0x246cc - Receive Undersize Packet Counter */ - uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ - uint rfrg; /* 0x246d4 - Receive Fragments Counter */ - uint rjbr; /* 0x246d8 - Receive Jabber Counter */ - uint rdrp; /* 0x246dc - Receive Drop Counter */ - uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ - uint tpkt; /* 0x246e4 - Transmit Packet Counter */ - uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ - uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ - uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ - uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ - uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ - uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ - uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ - uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ - uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ - uint tncl; /* 0x2470c - Transmit Total Collision Counter */ - char res49[4]; - uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ - uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ - uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ - uint txcf; /* 0x24720 - Transmit Control Frame Counter */ - uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ - uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ - uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ - uint car1; /* 0x24730 - Carry Register One */ - uint car2; /* 0x24734 - Carry Register Two */ - uint cam1; /* 0x24738 - Carry Mask Register One */ - uint cam2; /* 0x2473c - Carry Mask Register Two */ - uint rrej; /* 0x24740 - Receive filer rejected packet counter */ - char res50[188]; - uint iaddr0; /* 0x24800 - Indivdual address register 0 */ - uint iaddr1; /* 0x24804 - Indivdual address register 1 */ - uint iaddr2; /* 0x24808 - Indivdual address register 2 */ - uint iaddr3; /* 0x2480c - Indivdual address register 3 */ - uint iaddr4; /* 0x24810 - Indivdual address register 4 */ - uint iaddr5; /* 0x24814 - Indivdual address register 5 */ - uint iaddr6; /* 0x24818 - Indivdual address register 6 */ - uint iaddr7; /* 0x2481c - Indivdual address register 7 */ - char res51[96]; - uint gaddr0; /* 0x24880 - Global address register 0 */ - uint gaddr1; /* 0x24884 - Global address register 1 */ - uint gaddr2; /* 0x24888 - Global address register 2 */ - uint gaddr3; /* 0x2488c - Global address register 3 */ - uint gaddr4; /* 0x24890 - Global address register 4 */ - uint gaddr5; /* 0x24894 - Global address register 5 */ - uint gaddr6; /* 0x24898 - Global address register 6 */ - uint gaddr7; /* 0x2489c - Global address register 7 */ - char res52[352]; - uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ - char res53[500]; - uint attr; /* 0x24BF8 - DMA Attribute register */ - uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ - char res54[1024]; -} ccsr_tsec_t; - -/* PIC Registers(0x4_0000-0x6_1000) */ - -typedef struct ccsr_pic { - char res1[64]; - uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ - char res2[12]; - uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ - char res3[12]; - uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ - char res4[12]; - uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ - char res5[12]; - uint ctpr; /* 0x40080 - Current Task Priority Register */ - char res6[12]; - uint whoami; /* 0x40090 - Who Am I Register */ - char res7[12]; - uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ - char res8[12]; - uint eoi; /* 0x400b0 - End Of Interrupt Register */ - char res9[3916]; - uint frr; /* 0x41000 - Feature Reporting Register */ - char res10[28]; - uint gcr; /* 0x41020 - Global Configuration Register */ -#define MPC86xx_PICGCR_RST 0x80000000 -#define MPC86xx_PICGCR_MODE 0x20000000 - char res11[92]; - uint vir; /* 0x41080 - Vendor Identification Register */ - char res12[12]; - uint pir; /* 0x41090 - Processor Initialization Register */ - char res13[12]; - uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ - char res14[12]; - uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ - char res15[12]; - uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ - char res16[12]; - uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ - char res17[12]; - uint svr; /* 0x410e0 - Spurious Vector Register */ - char res18[12]; - uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ - char res19[12]; - uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ - char res20[12]; - uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ - char res21[12]; - uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ - char res22[12]; - uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ - char res23[12]; - uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ - char res24[12]; - uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ - char res25[12]; - uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ - char res26[12]; - uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ - char res27[12]; - uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ - char res28[12]; - uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ - char res29[12]; - uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ - char res30[12]; - uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ - char res31[12]; - uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ - char res32[12]; - uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ - char res33[12]; - uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ - char res34[12]; - uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ - char res35[268]; - uint tcr; /* 0x41300 - Timer Control Register */ - char res36[12]; - uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ - char res37[12]; - uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ - char res38[12]; - uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ - char res39[12]; - uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ - char res40[12]; - uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */ - char res41[12]; - uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */ - char res42[12]; - uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */ - char res43[12]; - uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */ - char res44[12]; - uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */ - char res45[12]; - uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */ - char res46[12]; - uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ - char res47[12]; - uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */ - char res48[60]; - uint msgr0; /* 0x41400 - Message Register 0 */ - char res49[12]; - uint msgr1; /* 0x41410 - Message Register 1 */ - char res50[12]; - uint msgr2; /* 0x41420 - Message Register 2 */ - char res51[12]; - uint msgr3; /* 0x41430 - Message Register 3 */ - char res52[204]; - uint mer; /* 0x41500 - Message Enable Register */ - char res53[12]; - uint msr; /* 0x41510 - Message Status Register */ - char res54[60140]; - uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ - char res55[12]; - uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ - char res56[12]; - uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ - char res57[12]; - uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ - char res58[12]; - uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ - char res59[12]; - uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ - char res60[12]; - uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ - char res61[12]; - uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ - char res62[12]; - uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ - char res63[12]; - uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ - char res64[12]; - uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ - char res65[12]; - uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ - char res66[12]; - uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ - char res67[12]; - uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ - char res68[12]; - uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ - char res69[12]; - uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ - char res70[12]; - uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ - char res71[12]; - uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ - char res72[12]; - uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ - char res73[12]; - uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ - char res74[12]; - uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ - char res75[12]; - uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ - char res76[12]; - uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ - char res77[12]; - uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ - char res78[140]; - uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ - char res79[12]; - uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ - char res80[12]; - uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ - char res81[12]; - uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ - char res82[12]; - uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ - char res83[12]; - uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ - char res84[12]; - uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ - char res85[12]; - uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ - char res86[12]; - uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ - char res87[12]; - uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ - char res88[12]; - uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ - char res89[12]; - uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ - char res90[12]; - uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ - char res91[12]; - uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ - char res92[12]; - uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ - char res93[12]; - uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ - char res94[12]; - uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ - char res95[12]; - uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ - char res96[12]; - uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ - char res97[12]; - uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ - char res98[12]; - uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ - char res99[12]; - uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ - char res100[12]; - uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ - char res101[12]; - uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ - char res102[12]; - uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ - char res103[12]; - uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ - char res104[12]; - uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ - char res105[12]; - uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ - char res106[12]; - uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ - char res107[12]; - uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ - char res108[12]; - uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ - char res109[12]; - uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ - char res110[12]; - uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ - char res111[12]; - uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ - char res112[12]; - uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ - char res113[12]; - uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ - char res114[12]; - uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ - char res115[12]; - uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ - char res116[12]; - uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ - char res117[12]; - uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ - char res118[12]; - uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ - char res119[12]; - uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ - char res120[12]; - uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ - char res121[12]; - uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ - char res122[12]; - uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ - char res123[12]; - uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ - char res124[12]; - uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ - char res125[12]; - uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ - char res126[12]; - uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ - char res127[12]; - uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ - char res128[12]; - uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ - char res129[12]; - uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ - char res130[12]; - uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ - char res131[12]; - uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ - char res132[12]; - uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ - char res133[12]; - uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ - char res134[12]; - uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ - char res135[12]; - uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ - char res136[12]; - uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ - char res137[12]; - uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ - char res138[12]; - uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ - char res139[12]; - uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ - char res140[12]; - uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ - char res141[12]; - uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ - char res142[4108]; - uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ - char res143[12]; - uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ - char res144[12]; - uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ - char res145[12]; - uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ - char res146[12]; - uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ - char res147[12]; - uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ - char res148[12]; - uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ - char res149[12]; - uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ - char res150[59852]; - uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ - char res151[12]; - uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ - char res152[12]; - uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ - char res153[12]; - uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ - char res154[12]; - uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ - char res155[12]; - uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ - char res156[12]; - uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ - char res157[12]; - uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ - char res158[3916]; -} ccsr_pic_t; - -/* RapidIO Registers(0xc_0000-0xe_0000) */ - -typedef struct ccsr_rio { - uint didcar; /* 0xc0000 - Device Identity Capability Register */ - uint dicar; /* 0xc0004 - Device Information Capability Register */ - uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ - uint aicar; /* 0xc000c - Assembly Information Capability Register */ - uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ - uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ - uint socar; /* 0xc0018 - Source Operations Capability Register */ - uint docar; /* 0xc001c - Destination Operations Capability Register */ - char res1[32]; - uint msr; /* 0xc0040 - Mailbox Command And Status Register */ - uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ - char res2[4]; - uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ - char res3[12]; - uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ - uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ - char res4[4]; - uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ - uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ - char res5[144]; - uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ - char res6[28]; - uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ - uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ - char res7[20]; - uint pgccsr; /* 0xc013c - Port General Command and Status Register */ - uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ - uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ - uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ - char res8[12]; - uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ - uint pccsr; /* 0xc015c - Port Control Command and Status Register */ - char res9[1184]; - uint erbh; /* 0xc0600 - Error Reporting Block Header Register */ - char res10[4]; - uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */ - uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */ - char res11[4]; - uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */ - uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */ - uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */ - char res12[32]; - uint edcsr; /* 0xc0640 - Port 0 error detect status register */ - uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */ - uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ - uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ - uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ - uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ - uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ - char res13[12]; - uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ - uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/ - char res14[63892]; - uint llcr; /* 0xd0004 - Logical Layer Configuration Register */ - char res15[12]; - uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */ - char res16[12]; - uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */ - char res17[92]; - uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */ - char res18[124]; - uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */ - char res19[28]; - uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */ - char res20[12]; - uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */ - char res21[12]; - uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */ - char res22[20]; - uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ - char res23[4]; - uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ - char res24[2716]; - uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ - uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ - char res25[8]; - uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ - char res26[12]; - uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ - uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */ - uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ - char res27[4]; - uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ - uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */ - uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */ - uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */ - uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ - uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */ - uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ - char res28[4]; - uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ - uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */ - uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */ - uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */ - uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ - uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */ - uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ - char res29[4]; - uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ - uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */ - uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */ - uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */ - uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ - uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */ - uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ - char res30[4]; - uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ - uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */ - uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */ - uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */ - uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ - uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */ - uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ - char res31[4]; - uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ - uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */ - uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */ - uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */ - uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ - uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */ - uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ - char res32[4]; - uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ - uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */ - uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */ - uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */ - uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ - uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */ - uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ - char res33[4]; - uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ - uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */ - uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */ - uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */ - uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ - uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */ - uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ - char res34[4]; - uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ - uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */ - uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */ - uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */ - char res35[64]; - uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ - uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ - char res36[4]; - uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ - char res37[12]; - uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ - char res38[4]; - uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ - char res39[4]; - uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ - char res40[12]; - uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ - char res41[4]; - uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ - char res42[4]; - uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ - char res43[12]; - uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ - char res44[4]; - uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ - char res45[4]; - uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ - char res46[12]; - uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ - char res47[12]; - uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ - char res48[12]; - uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ - uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ - uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ - uint pecr; /* 0xd0e0c - Port Error Control Register */ - uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ - uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ - uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ - char res49[4]; - uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ - char res50[4]; - uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ - uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ - char res51[8656]; - uint omr; /* 0xd3000 - Outbound Mode Register */ - uint osr; /* 0xd3004 - Outbound Status Register */ - uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ - uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */ - uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */ - uint osar; /* 0xd3014 - Outbound Unit Source Address Register */ - uint odpr; /* 0xd3018 - Outbound Destination Port Register */ - uint odatr; /* 0xd301c - Outbound Destination Attributes Register */ - uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */ - uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ - uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */ - uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ - uint omgr; /* 0xd3030 - Outbound Multicast Group Register */ - uint omlr; /* 0xd3034 - Outbound Multicast List Register */ - char res52[40]; - uint imr; /* 0xd3060 - Outbound Mode Register */ - uint isr; /* 0xd3064 - Inbound Status Register */ - uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ - uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */ - uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */ - uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */ - uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */ - char res53[900]; - uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ - uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ - char res54[16]; - uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */ - uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */ - char res55[12]; - uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */ - char res56[48]; - uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ - uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */ - uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */ - uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ - uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ - uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ - uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ - char res57[100]; - uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ - uint pwsr; /* 0xd34e4 - Port-Write Status Register */ - uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ - uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ - char res58[51984]; -} ccsr_rio_t; - -/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ -typedef struct ccsr_gur { - uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ - uint porbmsr; /* 0xe0004 - POR boot mode status register */ - uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ - uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ - uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ - char res1[12]; - uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ - char res2[12]; - uint gpiocr; /* 0xe0030 - GPIO control register */ - char res3[12]; - uint gpoutdr; /* 0xe0040 - General-purpose output data register */ - char res4[12]; - uint gpindr; /* 0xe0050 - General-purpose input data register */ - char res5[12]; - uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ - char res6[12]; - uint devdisr; /* 0xe0070 - Device disable control */ - char res7[12]; - uint powmgtcsr; /* 0xe0080 - Power management status and control register */ - char res8[12]; - uint mcpsumr; /* 0xe0090 - Machine check summary register */ - uint rstrscr; /* 0xe0094 - Reset request status and control register */ - char res9[8]; - uint pvr; /* 0xe00a0 - Processor version register */ - uint svr; /* 0xe00a4 - System version register */ - char res10a[8]; - uint rstcr; /* 0xe00b0 - Reset control register */ - char res10b[1868]; - uint clkdvdr; /* 0xe0800 - Clock Divide register */ - char res10c[796]; - uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */ - char res10d[4]; - uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */ - char res10e[724]; - uint clkocr; /* 0xe0e00 - Clock out select register */ - char res11[12]; - uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ - char res12[12]; - uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ - char res13a[224]; - uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */ - char res13b[4]; - uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */ - char res14[24]; - uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ - char res15a[24]; - uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */ - uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */ - char res16[184]; -} ccsr_gur_t; - -#define MPC8610_PORBMSR_HA 0x00070000 -#define MPC8610_PORBMSR_HA_SHIFT 16 -#define MPC8641_PORBMSR_HA 0x00060000 -#define MPC8641_PORBMSR_HA_SHIFT 17 -#define MPC8610_PORDEVSR_IO_SEL 0x00380000 -#define MPC8610_PORDEVSR_IO_SEL_SHIFT 19 -#define MPC8641_PORDEVSR_IO_SEL 0x000F0000 -#define MPC8641_PORDEVSR_IO_SEL_SHIFT 16 -#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */ -#define MPC86xx_DEVDISR_PCIEX1 0x80000000 -#define MPC86xx_DEVDISR_PCIEX2 0x40000000 -#define MPC86xx_DEVDISR_PCI1 0x80000000 -#define MPC86xx_DEVDISR_PCIE1 0x40000000 -#define MPC86xx_DEVDISR_PCIE2 0x20000000 -#define MPC86xx_DEVDISR_CPU0 0x00008000 -#define MPC86xx_DEVDISR_CPU1 0x00004000 -#define MPC86xx_RSTCR_HRST_REQ 0x00000002 - -/* - * Watchdog register block(0xe_4000-0xe_4fff) - */ -typedef struct ccsr_wdt { - uint res0; - uint swcrr; /* System watchdog control register */ - uint swcnr; /* System watchdog count register */ - char res1[2]; - ushort swsrr; /* System watchdog service register */ - char res2[4080]; -} ccsr_wdt_t; - -typedef struct immap { - ccsr_local_mcm_t im_local_mcm; - ccsr_ddr_t im_ddr1; - ccsr_i2c_t im_i2c; - ccsr_duart_t im_duart; - ccsr_lbc_t im_lbc; - ccsr_ddr_t im_ddr2; - char res1[4096]; - ccsr_pex_t im_pex1; - ccsr_pex_t im_pex2; - ccsr_ht_t im_ht; - char res2[90112]; - ccsr_dma_t im_dma; - char res3[8192]; - ccsr_tsec_t im_tsec1; - ccsr_tsec_t im_tsec2; - ccsr_tsec_t im_tsec3; - ccsr_tsec_t im_tsec4; - char res4[98304]; - ccsr_pic_t im_pic; - char res5[389120]; - ccsr_rio_t im_rio; - ccsr_gur_t im_gur; - char res6[12288]; - ccsr_wdt_t im_wdt; -} immap_t; - -extern immap_t *immr; - -#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000) -#define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET) -#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000) -#define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000) -#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) - -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 - -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) - -#endif /*__IMMAP_86xx__*/ diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h deleted file mode 100644 index 531cfc8..0000000 --- a/include/asm-ppc/immap_qe.h +++ /dev/null @@ -1,621 +0,0 @@ -/* - * QUICC Engine (QE) Internal Memory Map. - * The Internal Memory Map for devices with QE on them. This - * is the superset of all QE devices (8360, etc.). - * - * Copyright (c) 2006-2009 Freescale Semiconductor, Inc. - * Author: Shlomi Gridih - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __IMMAP_QE_H__ -#define __IMMAP_QE_H__ - -/* QE I-RAM -*/ -typedef struct qe_iram { - u32 iadd; /* I-RAM Address Register */ - u32 idata; /* I-RAM Data Register */ - u8 res0[0x4]; - u32 iready; - u8 res1[0x70]; -} __attribute__ ((packed)) qe_iram_t; - -/* QE Interrupt Controller -*/ -typedef struct qe_ic { - u32 qicr; - u32 qivec; - u32 qripnr; - u32 qipnr; - u32 qipxcc; - u32 qipycc; - u32 qipwcc; - u32 qipzcc; - u32 qimr; - u32 qrimr; - u32 qicnr; - u8 res0[0x4]; - u32 qiprta; - u32 qiprtb; - u8 res1[0x4]; - u32 qricr; - u8 res2[0x20]; - u32 qhivec; - u8 res3[0x1C]; -} __attribute__ ((packed)) qe_ic_t; - -/* Communications Processor -*/ -typedef struct cp_qe { - u32 cecr; /* QE command register */ - u32 ceccr; /* QE controller configuration register */ - u32 cecdr; /* QE command data register */ - u8 res0[0xA]; - u16 ceter; /* QE timer event register */ - u8 res1[0x2]; - u16 cetmr; /* QE timers mask register */ - u32 cetscr; /* QE time-stamp timer control register */ - u32 cetsr1; /* QE time-stamp register 1 */ - u32 cetsr2; /* QE time-stamp register 2 */ - u8 res2[0x8]; - u32 cevter; /* QE virtual tasks event register */ - u32 cevtmr; /* QE virtual tasks mask register */ - u16 cercr; /* QE RAM control register */ - u8 res3[0x2]; - u8 res4[0x24]; - u16 ceexe1; /* QE external request 1 event register */ - u8 res5[0x2]; - u16 ceexm1; /* QE external request 1 mask register */ - u8 res6[0x2]; - u16 ceexe2; /* QE external request 2 event register */ - u8 res7[0x2]; - u16 ceexm2; /* QE external request 2 mask register */ - u8 res8[0x2]; - u16 ceexe3; /* QE external request 3 event register */ - u8 res9[0x2]; - u16 ceexm3; /* QE external request 3 mask register */ - u8 res10[0x2]; - u16 ceexe4; /* QE external request 4 event register */ - u8 res11[0x2]; - u16 ceexm4; /* QE external request 4 mask register */ - u8 res12[0x2]; - u8 res13[0x280]; -} __attribute__ ((packed)) cp_qe_t; - -/* QE Multiplexer -*/ -typedef struct qe_mux { - u32 cmxgcr; /* CMX general clock route register */ - u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ - u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ - u32 cmxsi1syr; /* CMX SI1 SYNC route register */ - u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ - u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ - u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ - u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ - u32 cmxupcr; /* CMX UPC clock route register */ - u8 res0[0x1C]; -} __attribute__ ((packed)) qe_mux_t; - -/* QE Timers -*/ -typedef struct qe_timers { - u8 gtcfr1; /* Timer 1 2 global configuration register */ - u8 res0[0x3]; - u8 gtcfr2; /* Timer 3 4 global configuration register */ - u8 res1[0xB]; - u16 gtmdr1; /* Timer 1 mode register */ - u16 gtmdr2; /* Timer 2 mode register */ - u16 gtrfr1; /* Timer 1 reference register */ - u16 gtrfr2; /* Timer 2 reference register */ - u16 gtcpr1; /* Timer 1 capture register */ - u16 gtcpr2; /* Timer 2 capture register */ - u16 gtcnr1; /* Timer 1 counter */ - u16 gtcnr2; /* Timer 2 counter */ - u16 gtmdr3; /* Timer 3 mode register */ - u16 gtmdr4; /* Timer 4 mode register */ - u16 gtrfr3; /* Timer 3 reference register */ - u16 gtrfr4; /* Timer 4 reference register */ - u16 gtcpr3; /* Timer 3 capture register */ - u16 gtcpr4; /* Timer 4 capture register */ - u16 gtcnr3; /* Timer 3 counter */ - u16 gtcnr4; /* Timer 4 counter */ - u16 gtevr1; /* Timer 1 event register */ - u16 gtevr2; /* Timer 2 event register */ - u16 gtevr3; /* Timer 3 event register */ - u16 gtevr4; /* Timer 4 event register */ - u16 gtps; /* Timer 1 prescale register */ - u8 res2[0x46]; -} __attribute__ ((packed)) qe_timers_t; - -/* BRG -*/ -typedef struct qe_brg { - u32 brgc1; /* BRG1 configuration register */ - u32 brgc2; /* BRG2 configuration register */ - u32 brgc3; /* BRG3 configuration register */ - u32 brgc4; /* BRG4 configuration register */ - u32 brgc5; /* BRG5 configuration register */ - u32 brgc6; /* BRG6 configuration register */ - u32 brgc7; /* BRG7 configuration register */ - u32 brgc8; /* BRG8 configuration register */ - u32 brgc9; /* BRG9 configuration register */ - u32 brgc10; /* BRG10 configuration register */ - u32 brgc11; /* BRG11 configuration register */ - u32 brgc12; /* BRG12 configuration register */ - u32 brgc13; /* BRG13 configuration register */ - u32 brgc14; /* BRG14 configuration register */ - u32 brgc15; /* BRG15 configuration register */ - u32 brgc16; /* BRG16 configuration register */ - u8 res0[0x40]; -} __attribute__ ((packed)) qe_brg_t; - -/* SPI -*/ -typedef struct spi { - u8 res0[0x20]; - u32 spmode; /* SPI mode register */ - u8 res1[0x2]; - u8 spie; /* SPI event register */ - u8 res2[0x1]; - u8 res3[0x2]; - u8 spim; /* SPI mask register */ - u8 res4[0x1]; - u8 res5[0x1]; - u8 spcom; /* SPI command register */ - u8 res6[0x2]; - u32 spitd; /* SPI transmit data register (cpu mode) */ - u32 spird; /* SPI receive data register (cpu mode) */ - u8 res7[0x8]; -} __attribute__ ((packed)) spi_t; - -/* SI -*/ -typedef struct si1 { - u16 siamr1; /* SI1 TDMA mode register */ - u16 sibmr1; /* SI1 TDMB mode register */ - u16 sicmr1; /* SI1 TDMC mode register */ - u16 sidmr1; /* SI1 TDMD mode register */ - u8 siglmr1_h; /* SI1 global mode register high */ - u8 res0[0x1]; - u8 sicmdr1_h; /* SI1 command register high */ - u8 res2[0x1]; - u8 sistr1_h; /* SI1 status register high */ - u8 res3[0x1]; - u16 sirsr1_h; /* SI1 RAM shadow address register high */ - u8 sitarc1; /* SI1 RAM counter Tx TDMA */ - u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ - u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ - u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ - u8 sirarc1; /* SI1 RAM counter Rx TDMA */ - u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ - u8 sircrc1; /* SI1 RAM counter Rx TDMC */ - u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ - u8 res4[0x8]; - u16 siemr1; /* SI1 TDME mode register 16 bits */ - u16 sifmr1; /* SI1 TDMF mode register 16 bits */ - u16 sigmr1; /* SI1 TDMG mode register 16 bits */ - u16 sihmr1; /* SI1 TDMH mode register 16 bits */ - u8 siglmg1_l; /* SI1 global mode register low 8 bits */ - u8 res5[0x1]; - u8 sicmdr1_l; /* SI1 command register low 8 bits */ - u8 res6[0x1]; - u8 sistr1_l; /* SI1 status register low 8 bits */ - u8 res7[0x1]; - u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ - u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ - u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ - u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ - u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ - u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ - u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ - u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ - u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ - u8 res8[0x8]; - u32 siml1; /* SI1 multiframe limit register */ - u8 siedm1; /* SI1 extended diagnostic mode register */ - u8 res9[0xBB]; -} __attribute__ ((packed)) si1_t; - -/* SI Routing Tables -*/ -typedef struct sir { - u8 tx[0x400]; - u8 rx[0x400]; - u8 res0[0x800]; -} __attribute__ ((packed)) sir_t; - -/* USB Controller. -*/ -typedef struct usb_ctlr { - u8 usb_usmod; - u8 usb_usadr; - u8 usb_uscom; - u8 res1[1]; - u16 usb_usep1; - u16 usb_usep2; - u16 usb_usep3; - u16 usb_usep4; - u8 res2[4]; - u16 usb_usber; - u8 res3[2]; - u16 usb_usbmr; - u8 res4[1]; - u8 usb_usbs; - u16 usb_ussft; - u8 res5[2]; - u16 usb_usfrn; - u8 res6[0x22]; -} __attribute__ ((packed)) usb_t; - -/* MCC -*/ -typedef struct mcc { - u32 mcce; /* MCC event register */ - u32 mccm; /* MCC mask register */ - u32 mccf; /* MCC configuration register */ - u32 merl; /* MCC emergency request level register */ - u8 res0[0xF0]; -} __attribute__ ((packed)) mcc_t; - -/* QE UCC Slow -*/ -typedef struct ucc_slow { - u32 gumr_l; /* UCCx general mode register (low) */ - u32 gumr_h; /* UCCx general mode register (high) */ - u16 upsmr; /* UCCx protocol-specific mode register */ - u8 res0[0x2]; - u16 utodr; /* UCCx transmit on demand register */ - u16 udsr; /* UCCx data synchronization register */ - u16 ucce; /* UCCx event register */ - u8 res1[0x2]; - u16 uccm; /* UCCx mask register */ - u8 res2[0x1]; - u8 uccs; /* UCCx status register */ - u8 res3[0x24]; - u16 utpt; - u8 guemr; /* UCC general extended mode register */ - u8 res4[0x200 - 0x091]; -} __attribute__ ((packed)) ucc_slow_t; - -typedef struct ucc_mii_mng { - u32 miimcfg; /* MII management configuration reg */ - u32 miimcom; /* MII management command reg */ - u32 miimadd; /* MII management address reg */ - u32 miimcon; /* MII management control reg */ - u32 miimstat; /* MII management status reg */ - u32 miimind; /* MII management indication reg */ - u32 ifctl; /* interface control reg */ - u32 ifstat; /* interface statux reg */ -} __attribute__ ((packed))uec_mii_t; - -typedef struct ucc_ethernet { - u32 maccfg1; /* mac configuration reg. 1 */ - u32 maccfg2; /* mac configuration reg. 2 */ - u32 ipgifg; /* interframe gap reg. */ - u32 hafdup; /* half-duplex reg. */ - u8 res1[0x10]; - u32 miimcfg; /* MII management configuration reg */ - u32 miimcom; /* MII management command reg */ - u32 miimadd; /* MII management address reg */ - u32 miimcon; /* MII management control reg */ - u32 miimstat; /* MII management status reg */ - u32 miimind; /* MII management indication reg */ - u32 ifctl; /* interface control reg */ - u32 ifstat; /* interface statux reg */ - u32 macstnaddr1; /* mac station address part 1 reg */ - u32 macstnaddr2; /* mac station address part 2 reg */ - u8 res2[0x8]; - u32 uempr; /* UCC Ethernet Mac parameter reg */ - u32 utbipar; /* UCC tbi address reg */ - u16 uescr; /* UCC Ethernet statistics control reg */ - u8 res3[0x180 - 0x15A]; - u32 tx64; /* Total number of frames (including bad - * frames) transmitted that were exactly - * of the minimal length (64 for un tagged, - * 68 for tagged, or with length exactly - * equal to the parameter MINLength */ - u32 tx127; /* Total number of frames (including bad - * frames) transmitted that were between - * MINLength (Including FCS length==4) - * and 127 octets */ - u32 tx255; /* Total number of frames (including bad - * frames) transmitted that were between - * 128 (Including FCS length==4) and 255 - * octets */ - u32 rx64; /* Total number of frames received including - * bad frames that were exactly of the - * mninimal length (64 bytes) */ - u32 rx127; /* Total number of frames (including bad - * frames) received that were between - * MINLength (Including FCS length==4) - * and 127 octets */ - u32 rx255; /* Total number of frames (including - * bad frames) received that were between - * 128 (Including FCS length==4) and 255 - * octets */ - u32 txok; /* Total number of octets residing in frames - * that where involved in succesfull - * transmission */ - u16 txcf; /* Total number of PAUSE control frames - * transmitted by this MAC */ - u8 res4[0x2]; - u32 tmca; /* Total number of frames that were transmitted - * succesfully with the group address bit set - * that are not broadcast frames */ - u32 tbca; /* Total number of frames transmitted - * succesfully that had destination address - * field equal to the broadcast address */ - u32 rxfok; /* Total number of frames received OK */ - u32 rxbok; /* Total number of octets received OK */ - u32 rbyt; /* Total number of octets received including - * octets in bad frames. Must be implemented - * in HW because it includes octets in frames - * that never even reach the UCC */ - u32 rmca; /* Total number of frames that were received - * succesfully with the group address bit set - * that are not broadcast frames */ - u32 rbca; /* Total number of frames received succesfully - * that had destination address equal to the - * broadcast address */ - u32 scar; /* Statistics carry register */ - u32 scam; /* Statistics caryy mask register */ - u8 res5[0x200 - 0x1c4]; -} __attribute__ ((packed)) uec_t; - -/* QE UCC Fast -*/ -typedef struct ucc_fast { - u32 gumr; /* UCCx general mode register */ - u32 upsmr; /* UCCx protocol-specific mode register */ - u16 utodr; /* UCCx transmit on demand register */ - u8 res0[0x2]; - u16 udsr; /* UCCx data synchronization register */ - u8 res1[0x2]; - u32 ucce; /* UCCx event register */ - u32 uccm; /* UCCx mask register. */ - u8 uccs; /* UCCx status register */ - u8 res2[0x7]; - u32 urfb; /* UCC receive FIFO base */ - u16 urfs; /* UCC receive FIFO size */ - u8 res3[0x2]; - u16 urfet; /* UCC receive FIFO emergency threshold */ - u16 urfset; /* UCC receive FIFO special emergency - * threshold */ - u32 utfb; /* UCC transmit FIFO base */ - u16 utfs; /* UCC transmit FIFO size */ - u8 res4[0x2]; - u16 utfet; /* UCC transmit FIFO emergency threshold */ - u8 res5[0x2]; - u16 utftt; /* UCC transmit FIFO transmit threshold */ - u8 res6[0x2]; - u16 utpt; /* UCC transmit polling timer */ - u8 res7[0x2]; - u32 urtry; /* UCC retry counter register */ - u8 res8[0x4C]; - u8 guemr; /* UCC general extended mode register */ - u8 res9[0x100 - 0x091]; - uec_t ucc_eth; -} __attribute__ ((packed)) ucc_fast_t; - -/* QE UCC -*/ -typedef struct ucc_common { - u8 res1[0x90]; - u8 guemr; - u8 res2[0x200 - 0x091]; -} __attribute__ ((packed)) ucc_common_t; - -typedef struct ucc { - union { - ucc_slow_t slow; - ucc_fast_t fast; - ucc_common_t common; - }; -} __attribute__ ((packed)) ucc_t; - -/* MultiPHY UTOPIA POS Controllers (UPC) -*/ -typedef struct upc { - u32 upgcr; /* UTOPIA/POS general configuration register */ - u32 uplpa; /* UTOPIA/POS last PHY address */ - u32 uphec; /* ATM HEC register */ - u32 upuc; /* UTOPIA/POS UCC configuration */ - u32 updc1; /* UTOPIA/POS device 1 configuration */ - u32 updc2; /* UTOPIA/POS device 2 configuration */ - u32 updc3; /* UTOPIA/POS device 3 configuration */ - u32 updc4; /* UTOPIA/POS device 4 configuration */ - u32 upstpa; /* UTOPIA/POS STPA threshold */ - u8 res0[0xC]; - u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ - u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ - u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ - u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ - u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ - u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ - u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ - u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ - u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ - u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ - u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ - u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ - u32 upde1; /* UTOPIA/POS device 1 event */ - u32 upde2; /* UTOPIA/POS device 2 event */ - u32 upde3; /* UTOPIA/POS device 3 event */ - u32 upde4; /* UTOPIA/POS device 4 event */ - u16 uprp1; - u16 uprp2; - u16 uprp3; - u16 uprp4; - u8 res1[0x8]; - u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ - u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ - u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ - u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ - u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ - u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ - u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ - u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ - u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ - u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ - u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ - u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ - u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ - u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ - u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ - u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ - u32 uper1; /* Device 1 port enable register */ - u32 uper2; /* Device 2 port enable register */ - u32 uper3; /* Device 3 port enable register */ - u32 uper4; /* Device 4 port enable register */ - u8 res2[0x150]; -} __attribute__ ((packed)) upc_t; - -/* SDMA -*/ -typedef struct sdma { - u32 sdsr; /* Serial DMA status register */ - u32 sdmr; /* Serial DMA mode register */ - u32 sdtr1; /* SDMA system bus threshold register */ - u32 sdtr2; /* SDMA secondary bus threshold register */ - u32 sdhy1; /* SDMA system bus hysteresis register */ - u32 sdhy2; /* SDMA secondary bus hysteresis register */ - u32 sdta1; /* SDMA system bus address register */ - u32 sdta2; /* SDMA secondary bus address register */ - u32 sdtm1; /* SDMA system bus MSNUM register */ - u32 sdtm2; /* SDMA secondary bus MSNUM register */ - u8 res0[0x10]; - u32 sdaqr; /* SDMA address bus qualify register */ - u32 sdaqmr; /* SDMA address bus qualify mask register */ - u8 res1[0x4]; - u32 sdwbcr; /* SDMA CAM entries base register */ - u8 res2[0x38]; -} __attribute__ ((packed)) sdma_t; - -/* Debug Space -*/ -typedef struct dbg { - u32 bpdcr; /* Breakpoint debug command register */ - u32 bpdsr; /* Breakpoint debug status register */ - u32 bpdmr; /* Breakpoint debug mask register */ - u32 bprmrr0; /* Breakpoint request mode risc register 0 */ - u32 bprmrr1; /* Breakpoint request mode risc register 1 */ - u8 res0[0x8]; - u32 bprmtr0; /* Breakpoint request mode trb register 0 */ - u32 bprmtr1; /* Breakpoint request mode trb register 1 */ - u8 res1[0x8]; - u32 bprmir; /* Breakpoint request mode immediate register */ - u32 bprmsr; /* Breakpoint request mode serial register */ - u32 bpemr; /* Breakpoint exit mode register */ - u8 res2[0x48]; -} __attribute__ ((packed)) dbg_t; - -/* - * RISC Special Registers (Trap and Breakpoint). These are described in - * the QE Developer's Handbook. -*/ -typedef struct rsp { - u32 tibcr[16]; /* Trap/instruction breakpoint control regs */ - u8 res0[64]; - u32 ibcr0; - u32 ibs0; - u32 ibcnr0; - u8 res1[4]; - u32 ibcr1; - u32 ibs1; - u32 ibcnr1; - u32 npcr; - u32 dbcr; - u32 dbar; - u32 dbamr; - u32 dbsr; - u32 dbcnr; - u8 res2[12]; - u32 dbdr_h; - u32 dbdr_l; - u32 dbdmr_h; - u32 dbdmr_l; - u32 bsr; - u32 bor; - u32 bior; - u8 res3[4]; - u32 iatr[4]; - u32 eccr; /* Exception control configuration register */ - u32 eicr; - u8 res4[0x100-0xf8]; -} __attribute__ ((packed)) rsp_t; - -typedef struct qe_immap { - qe_iram_t iram; /* I-RAM */ - qe_ic_t ic; /* Interrupt Controller */ - cp_qe_t cp; /* Communications Processor */ - qe_mux_t qmx; /* QE Multiplexer */ - qe_timers_t qet; /* QE Timers */ - spi_t spi[0x2]; /* spi */ - mcc_t mcc; /* mcc */ - qe_brg_t brg; /* brg */ - usb_t usb; /* USB */ - si1_t si1; /* SI */ - u8 res11[0x800]; - sir_t sir; /* SI Routing Tables */ - ucc_t ucc1; /* ucc1 */ - ucc_t ucc3; /* ucc3 */ - ucc_t ucc5; /* ucc5 */ - ucc_t ucc7; /* ucc7 */ - u8 res12[0x600]; - upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ - ucc_t ucc2; /* ucc2 */ - ucc_t ucc4; /* ucc4 */ - ucc_t ucc6; /* ucc6 */ - ucc_t ucc8; /* ucc8 */ - u8 res13[0x600]; - upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ - sdma_t sdma; /* SDMA */ - dbg_t dbg; /* Debug Space */ - rsp_t rsp[0x2]; /* RISC Special Registers - * (Trap and Breakpoint) */ - u8 res14[0x300]; - u8 res15[0x3A00]; - u8 res16[0x8000]; /* 0x108000 - 0x110000 */ -#if defined(CONFIG_MPC8568) - u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */ - u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */ -#elif defined(CONFIG_MPC8569) - u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */ - u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */ -#else - u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ - u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ - u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ -#endif -} __attribute__ ((packed)) qe_map_t; - -extern qe_map_t *qe_immr; - -#if defined(CONFIG_MPC8568) -#define QE_MURAM_SIZE 0x10000UL -#elif defined(CONFIG_MPC8569) -#define QE_MURAM_SIZE 0x20000UL -#elif defined(CONFIG_MPC8360) -#define QE_MURAM_SIZE 0xc000UL -#elif defined(CONFIG_MPC832x) -#define QE_MURAM_SIZE 0x4000UL -#endif - -#if defined(CONFIG_MPC8323) -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC8569) -#define MAX_QE_RISC 4 -#define QE_NUM_OF_SNUM 46 -#else -#define MAX_QE_RISC 2 -#define QE_NUM_OF_SNUM 28 -#endif - -#endif /* __IMMAP_QE_H__ */ diff --git a/include/asm-ppc/interrupt.h b/include/asm-ppc/interrupt.h deleted file mode 100644 index 792836b..0000000 --- a/include/asm-ppc/interrupt.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . -*/ -#ifndef INTERRUPT_H -#define INTERRUPT_H - -#if defined(CONFIG_XILINX_440) -#include -#else -#include -#endif - -void pic_enable(void); -void pic_irq_enable(unsigned int irq); -void pic_irq_disable(unsigned int irq); -void pic_irq_ack(unsigned int irq); -void external_interrupt(struct pt_regs *regs); -void interrupt_run_handler(int vec); - -#endif diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h deleted file mode 100644 index 4ddad26..0000000 --- a/include/asm-ppc/io.h +++ /dev/null @@ -1,318 +0,0 @@ -/* originally from linux source. - * removed the dependencies on CONFIG_ values - * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__) - * Modified By Rob Taylor, Flying Pig Systems, 2000 - */ - -#ifndef _PPC_IO_H -#define _PPC_IO_H - -#include -#include - -#ifdef CONFIG_ADDR_MAP -#include -#endif - -#define SIO_CONFIG_RA 0x398 -#define SIO_CONFIG_RD 0x399 - -#ifndef _IO_BASE -#define _IO_BASE 0 -#endif - -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) -#if !defined(__BIG_ENDIAN) -#define readw(addr) (*(volatile u16 *) (addr)) -#define readl(addr) (*(volatile u32 *) (addr)) -#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) -#else -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) -#endif - -/* - * The insw/outsw/insl/outsl macros don't do byte-swapping. - * They are only used in practice for transferring buffers which - * are arrays of bytes, and byte-swapping is not appropriate in - * that case. - paulus - */ -#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - -#define inb(port) in_8((u8 *)((port)+_IO_BASE)) -#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) -#if !defined(__BIG_ENDIAN) -#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) -#else -#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) -#endif - -#define inb_p(port) in_8((u8 *)((port)+_IO_BASE)) -#define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) -#define inw_p(port) in_le16((u16 *)((port)+_IO_BASE)) -#define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) -#define inl_p(port) in_le32((u32 *)((port)+_IO_BASE)) -#define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) - -extern void _insb(volatile u8 *port, void *buf, int ns); -extern void _outsb(volatile u8 *port, const void *buf, int ns); -extern void _insw(volatile u16 *port, void *buf, int ns); -extern void _outsw(volatile u16 *port, const void *buf, int ns); -extern void _insl(volatile u32 *port, void *buf, int nl); -extern void _outsl(volatile u32 *port, const void *buf, int nl); -extern void _insw_ns(volatile u16 *port, void *buf, int ns); -extern void _outsw_ns(volatile u16 *port, const void *buf, int ns); -extern void _insl_ns(volatile u32 *port, void *buf, int nl); -extern void _outsl_ns(volatile u32 *port, const void *buf, int nl); - -/* - * The *_ns versions below don't do byte-swapping. - * Neither do the standard versions now, these are just here - * for older code. - */ -#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - - -#define IO_SPACE_LIMIT ~0 - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -/* - * Enforce In-order Execution of I/O: - * Acts as a barrier to ensure all previous I/O accesses have - * completed before any further ones are issued. - */ -static inline void eieio(void) -{ - __asm__ __volatile__ ("eieio" : : : "memory"); -} - -static inline void sync(void) -{ - __asm__ __volatile__ ("sync" : : : "memory"); -} - -static inline void isync(void) -{ - __asm__ __volatile__ ("isync" : : : "memory"); -} - -/* Enforce in-order execution of data I/O. - * No distinction between read/write on PPC; use eieio for all three. - */ -#define iobarrier_rw() eieio() -#define iobarrier_r() eieio() -#define iobarrier_w() eieio() - -/* - * Non ordered and non-swapping "raw" accessors - */ -#define __iomem -#define PCI_FIX_ADDR(addr) (addr) - -static inline unsigned char __raw_readb(const volatile void __iomem *addr) -{ - return *(volatile unsigned char *)PCI_FIX_ADDR(addr); -} -static inline unsigned short __raw_readw(const volatile void __iomem *addr) -{ - return *(volatile unsigned short *)PCI_FIX_ADDR(addr); -} -static inline unsigned int __raw_readl(const volatile void __iomem *addr) -{ - return *(volatile unsigned int *)PCI_FIX_ADDR(addr); -} -static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) -{ - *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v; -} -static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) -{ - *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v; -} -static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) -{ - *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v; -} - -/* - * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - * - * Read operations have additional twi & isync to make sure the read - * is actually performed (i.e. the data has come back) before we start - * executing any following instructions. - */ -extern inline int in_8(const volatile unsigned char __iomem *addr) -{ - int ret; - - __asm__ __volatile__( - "sync; lbz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_8(volatile unsigned char __iomem *addr, int val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -extern inline int in_le16(const volatile unsigned short __iomem *addr) -{ - int ret; - - __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline int in_be16(const volatile unsigned short __iomem *addr) -{ - int ret; - - __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le16(volatile unsigned short __iomem *addr, int val) -{ - __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be16(volatile unsigned short __iomem *addr, int val) -{ - __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); -} - -extern inline unsigned in_le32(const volatile unsigned __iomem *addr) -{ - unsigned ret; - - __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline unsigned in_be32(const volatile unsigned __iomem *addr) -{ - unsigned ret; - - __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le32(volatile unsigned __iomem *addr, int val) -{ - __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be32(volatile unsigned __iomem *addr, int val) -{ - __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); -} - -/* Clear and set bits in one shot. These macros can be used to clear and - * set multiple bits in a register using a single call. These macros can - * also be used to set a multiple-bit bit pattern using a mask, by - * specifying the mask in the 'clear' parameter and the new bit pattern - * in the 'set' parameter. - */ - -#define clrbits(type, addr, clear) \ - out_##type((addr), in_##type(addr) & ~(clear)) - -#define setbits(type, addr, set) \ - out_##type((addr), in_##type(addr) | (set)) - -#define clrsetbits(type, addr, clear, set) \ - out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) - -#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) -#define setbits_be32(addr, set) setbits(be32, addr, set) -#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) - -#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) -#define setbits_le32(addr, set) setbits(le32, addr, set) -#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) - -#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) -#define setbits_be16(addr, set) setbits(be16, addr, set) -#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) - -#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) -#define setbits_le16(addr, set) setbits(le16, addr, set) -#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) - -#define clrbits_8(addr, clear) clrbits(8, addr, clear) -#define setbits_8(addr, set) setbits(8, addr, set) -#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ -#ifdef CONFIG_ADDR_MAP - return (void *)(addrmap_phys_to_virt(paddr)); -#else - return (void *)((unsigned long)paddr); -#endif -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ -#ifdef CONFIG_ADDR_MAP - return addrmap_virt_to_phys(vaddr); -#else - return (phys_addr_t)((unsigned long)vaddr); -#endif -} - -#endif diff --git a/include/asm-ppc/iopin_8260.h b/include/asm-ppc/iopin_8260.h deleted file mode 100644 index 619f3a8..0000000 --- a/include/asm-ppc/iopin_8260.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * MPC8260 I/O port pin manipulation functions - */ - -#ifndef _ASM_IOPIN_8260_H_ -#define _ASM_IOPIN_8260_H_ - -#include -#include - -#ifdef __KERNEL__ - -typedef - struct { - u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ - u_char pin:5; /* port pin (0-31) */ - u_char flag:1; /* for whatever */ - } -iopin_t; - -#define IOPIN_PORTA 0 -#define IOPIN_PORTB 1 -#define IOPIN_PORTC 2 -#define IOPIN_PORTD 3 - -extern __inline__ void -iopin_set_high(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void -iopin_set_low(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint -iopin_is_high(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint -iopin_is_low(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void -iopin_set_out(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void -iopin_set_in(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint -iopin_is_out(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint -iopin_is_in(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void -iopin_set_odr(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void -iopin_set_act(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint -iopin_is_odr(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint -iopin_is_act(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void -iopin_set_ded(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void -iopin_set_gen(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint -iopin_is_ded(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint -iopin_is_gen(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void -iopin_set_opt2(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void -iopin_set_opt1(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint -iopin_is_opt2(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint -iopin_is_opt1(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IOPIN_8260_H_ */ diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h deleted file mode 100644 index 0f07ba3..0000000 --- a/include/asm-ppc/iopin_85xx.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * MPC85xx I/O port pin manipulation functions - */ - -#ifndef _ASM_IOPIN_85xx_H_ -#define _ASM_IOPIN_85xx_H_ - -#include -#include - -#ifdef __KERNEL__ - -typedef struct { - u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ - u_char pin:5; /* port pin (0-31) */ - u_char flag:1; /* for whatever */ -} iopin_t; - -#define IOPIN_PORTA 0 -#define IOPIN_PORTB 1 -#define IOPIN_PORTC 2 -#define IOPIN_PORTD 3 - -extern __inline__ void iopin_set_high (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_low (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_high (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_low (iopin_t * iopin) -{ - volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; - return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_out (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_in (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_out (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_in (iopin_t * iopin) -{ - volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; - return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_odr (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_act (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_odr (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_act (iopin_t * iopin) -{ - volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; - return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_ded (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_gen (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_ded (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_gen (iopin_t * iopin) -{ - volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; - return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -extern __inline__ void iopin_set_opt2 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -extern __inline__ void iopin_set_opt1 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -extern __inline__ uint iopin_is_opt2 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -extern __inline__ uint iopin_is_opt1 (iopin_t * iopin) -{ - volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; - return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IOPIN_85xx_H_ */ diff --git a/include/asm-ppc/iopin_8xx.h b/include/asm-ppc/iopin_8xx.h deleted file mode 100644 index 3a2a682..0000000 --- a/include/asm-ppc/iopin_8xx.h +++ /dev/null @@ -1,395 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MPC8xx I/O port pin manipulation functions - * Roughly based on iopin_8260.h - */ - -#ifndef _ASM_IOPIN_8XX_H_ -#define _ASM_IOPIN_8XX_H_ - -#include -#include - -#ifdef __KERNEL__ - -typedef struct { - u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ - u_char pin:5; /* port pin (0-31) */ - u_char flag:1; /* for whatever */ -} iopin_t; - -#define IOPIN_PORTA 0 -#define IOPIN_PORTB 1 -#define IOPIN_PORTC 2 -#define IOPIN_PORTD 3 - -extern __inline__ void -iopin_set_high(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - *datp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - *datp |= (1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - *datp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - *datp |= (1 << (15 - iopin->pin)); - } -} - -extern __inline__ void -iopin_set_low(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - *datp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - *datp &= ~(1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - *datp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - *datp &= ~(1 << (15 - iopin->pin)); - } -} - -extern __inline__ uint -iopin_is_high(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - return (*datp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - return (*datp >> (31 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - return (*datp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - return (*datp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -extern __inline__ uint -iopin_is_low(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - return ((*datp >> (31 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -extern __inline__ void -iopin_set_out(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - *dirp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - *dirp |= (1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - *dirp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - *dirp |= (1 << (15 - iopin->pin)); - } -} - -extern __inline__ void -iopin_set_in(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - *dirp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - *dirp &= ~(1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - *dirp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - *dirp &= ~(1 << (15 - iopin->pin)); - } -} - -extern __inline__ uint -iopin_is_out(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - return (*dirp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - return (*dirp >> (31 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - return (*dirp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - return (*dirp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -extern __inline__ uint -iopin_is_in(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -extern __inline__ void -iopin_set_odr(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - *odrp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - *odrp |= (1 << (31 - iopin->pin)); - } -} - -extern __inline__ void -iopin_set_act(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - *odrp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - *odrp &= ~(1 << (31 - iopin->pin)); - } -} - -extern __inline__ uint -iopin_is_odr(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - return (*odrp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - return (*odrp >> (31 - iopin->pin)) & 1; - } - return 0; -} - -extern __inline__ uint -iopin_is_act(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -extern __inline__ void -iopin_set_ded(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - *parp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - *parp |= (1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - *parp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - *parp |= (1 << (15 - iopin->pin)); - } -} - -extern __inline__ void -iopin_set_gen(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - *parp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - *parp &= ~(1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - *parp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - *parp &= ~(1 << (15 - iopin->pin)); - } -} - -extern __inline__ uint -iopin_is_ded(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - return (*parp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - return (*parp >> (31 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - return (*parp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - return (*parp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -extern __inline__ uint -iopin_is_gen(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - return ((*parp >> (31 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -extern __inline__ void -iopin_set_opt2(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - *sorp |= (1 << (15 - iopin->pin)); - } -} - -extern __inline__ void -iopin_set_opt1(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - *sorp &= ~(1 << (15 - iopin->pin)); - } -} - -extern __inline__ uint -iopin_is_opt2(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - return (*sorp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -extern __inline__ uint -iopin_is_opt1(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -extern __inline__ void -iopin_set_falledge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - *intp |= (1 << (15 - iopin->pin)); - } -} - -extern __inline__ void -iopin_set_anyedge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - *intp &= ~(1 << (15 - iopin->pin)); - } -} - -extern __inline__ uint -iopin_is_falledge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - return (*intp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -extern __inline__ uint -iopin_is_anyedge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - return ((*intp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IOPIN_8XX_H_ */ diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h deleted file mode 100644 index 45f01de..0000000 --- a/include/asm-ppc/m8260_pci.h +++ /dev/null @@ -1,166 +0,0 @@ - -#ifndef _PPC_KERNEL_M8260_PCI_H -#define _PPC_KERNEL_M8260_PCI_H - -#define M8265_PCIBR0 0x101ac -#define M8265_PCIBR1 0x101b0 -#define M8265_PCIMSK0 0x101c4 -#define M8265_PCIMSK1 0x101c8 - -/* Bit definitions for PCIBR registers */ - -#define PCIBR_ENABLE 0x00000001 - -/* Bit definitions for PCIMSK registers */ - -#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */ -#define PCIMSK_64KB 0xFFFF0000 -#define PCIMSK_128KB 0xFFFE0000 -#define PCIMSK_256KB 0xFFFC0000 -#define PCIMSK_512KB 0xFFF80000 -#define PCIMSK_1MB 0xFFF00000 -#define PCIMSK_2MB 0xFFE00000 -#define PCIMSK_4MB 0xFFC00000 -#define PCIMSK_8MB 0xFF800000 -#define PCIMSK_16MB 0xFF000000 -#define PCIMSK_32MB 0xFE000000 -#define PCIMSK_64MB 0xFC000000 -#define PCIMSK_128MB 0xF8000000 -#define PCIMSK_256MB 0xF0000000 -#define PCIMSK_512MB 0xE0000000 -#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */ - - -#define M826X_SCCR_PCI_MODE_EN 0x100 - - -/* - * Outbound ATU registers (3 sets). These registers control how 60x bus (local) - * addresses are translated to PCI addresses when the MPC826x is a PCI bus - * master (initiator). - */ - -#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ -#define POTAR_REG1 0x10818 -#define POTAR_REG2 0x10830 - -#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ -#define POBAR_REG1 0x10820 -#define POBAR_REG2 0x10838 - -#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ -#define POCMR_REG1 0x10828 -#define POCMR_REG2 0x10840 - -/* Bit definitions for POMCR registers */ - -#define POCMR_MASK_4KB 0x000FFFFF -#define POCMR_MASK_8KB 0x000FFFFE -#define POCMR_MASK_16KB 0x000FFFFC -#define POCMR_MASK_32KB 0x000FFFF8 -#define POCMR_MASK_64KB 0x000FFFF0 -#define POCMR_MASK_128KB 0x000FFFE0 -#define POCMR_MASK_256KB 0x000FFFC0 -#define POCMR_MASK_512KB 0x000FFF80 -#define POCMR_MASK_1MB 0x000FFF00 -#define POCMR_MASK_2MB 0x000FFE00 -#define POCMR_MASK_4MB 0x000FFC00 -#define POCMR_MASK_8MB 0x000FF800 -#define POCMR_MASK_16MB 0x000FF000 -#define POCMR_MASK_32MB 0x000FE000 -#define POCMR_MASK_64MB 0x000FC000 -#define POCMR_MASK_128MB 0x000F8000 -#define POCMR_MASK_256MB 0x000F0000 -#define POCMR_MASK_512MB 0x000E0000 -#define POCMR_MASK_1GB 0x000C0000 - -#define POCMR_ENABLE 0x80000000 -#define POCMR_PCI_IO 0x40000000 -#define POCMR_PREFETCH_EN 0x20000000 - -/* Soft PCI reset */ - -#define PCI_GCR_REG 0x10880 - -/* Bit definitions for PCI_GCR registers */ - -#define PCIGCR_PCI_BUS_EN 0x1 - -/* - * Inbound ATU registers (2 sets). These registers control how PCI addresses - * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target. - */ - -#define PITAR_REG1 0x108D0 -#define PIBAR_REG1 0x108D8 -#define PICMR_REG1 0x108E0 -#define PITAR_REG0 0x108E8 -#define PIBAR_REG0 0x108F0 -#define PICMR_REG0 0x108F8 - -/* Bit definitions for PCI Inbound Comparison Mask registers */ - -#define PICMR_MASK_4KB 0x000FFFFF -#define PICMR_MASK_8KB 0x000FFFFE -#define PICMR_MASK_16KB 0x000FFFFC -#define PICMR_MASK_32KB 0x000FFFF8 -#define PICMR_MASK_64KB 0x000FFFF0 -#define PICMR_MASK_128KB 0x000FFFE0 -#define PICMR_MASK_256KB 0x000FFFC0 -#define PICMR_MASK_512KB 0x000FFF80 -#define PICMR_MASK_1MB 0x000FFF00 -#define PICMR_MASK_2MB 0x000FFE00 -#define PICMR_MASK_4MB 0x000FFC00 -#define PICMR_MASK_8MB 0x000FF800 -#define PICMR_MASK_16MB 0x000FF000 -#define PICMR_MASK_32MB 0x000FE000 -#define PICMR_MASK_64MB 0x000FC000 -#define PICMR_MASK_128MB 0x000F8000 -#define PICMR_MASK_256MB 0x000F0000 -#define PICMR_MASK_512MB 0x000E0000 -#define PICMR_MASK_1GB 0x000C0000 - -#define PICMR_ENABLE 0x80000000 -#define PICMR_NO_SNOOP_EN 0x40000000 -#define PICMR_PREFETCH_EN 0x20000000 - -/* PCI error Registers */ - -#define PCI_ERROR_STATUS_REG 0x10884 -#define PCI_ERROR_MASK_REG 0x10888 -#define PCI_ERROR_CONTROL_REG 0x1088C -#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 -#define PCI_ERROR_DATA_CAPTURE_REG 0x10898 -#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 - -/* PCI error Register bit defines */ - -#define PCI_ERROR_PCI_ADDR_PAR 0x00000001 -#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 -#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 -#define PCI_ERROR_PCI_NO_RSP 0x00000008 -#define PCI_ERROR_PCI_TAR_ABT 0x00000010 -#define PCI_ERROR_PCI_SERR 0x00000020 -#define PCI_ERROR_PCI_PERR_RD 0x00000040 -#define PCI_ERROR_PCI_PERR_WR 0x00000080 -#define PCI_ERROR_I2O_OFQO 0x00000100 -#define PCI_ERROR_I2O_IPQO 0x00000200 -#define PCI_ERROR_IRA 0x00000400 -#define PCI_ERROR_NMI 0x00000800 -#define PCI_ERROR_I2O_DBMC 0x00001000 - -/* - * Register pair used to generate configuration cycles on the PCI bus - * and access the MPC826x's own PCI configuration registers. - */ - -#define PCI_CFG_ADDR_REG 0x10900 -#define PCI_CFG_DATA_REG 0x10904 - -/* Bus parking decides where the bus control sits when idle */ -/* If modifying memory controllers for PCI park on the core */ - -#define PPC_ACR_BUS_PARK_CORE 0x6 -#define PPC_ACR_BUS_PARK_PCI 0x3 - -#endif /* _PPC_KERNEL_M8260_PCI_H */ diff --git a/include/asm-ppc/mc146818rtc.h b/include/asm-ppc/mc146818rtc.h deleted file mode 100644 index 5f806c4..0000000 --- a/include/asm-ppc/mc146818rtc.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Machine dependent access functions for RTC registers. - */ -#ifndef __ASM_PPC_MC146818RTC_H -#define __ASM_PPC_MC146818RTC_H - -#include - -#ifndef RTC_PORT -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ -#endif - -/* - * The yet supported machines all access the RTC index register via - * an ISA port access but the way to access the date register differs ... - */ -#define CMOS_READ(addr) ({ \ -outb_p((addr),RTC_PORT(0)); \ -inb_p(RTC_PORT(1)); \ -}) -#define CMOS_WRITE(val, addr) ({ \ -outb_p((addr),RTC_PORT(0)); \ -outb_p((val),RTC_PORT(1)); \ -}) - -#endif /* __ASM_PPC_MC146818RTC_H */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h deleted file mode 100644 index ce7f081..0000000 --- a/include/asm-ppc/mmu.h +++ /dev/null @@ -1,763 +0,0 @@ -/* - * PowerPC memory management structures - */ - -#ifndef _PPC_MMU_H_ -#define _PPC_MMU_H_ - -#include - -#ifndef __ASSEMBLY__ -/* Hardware Page Table Entry */ -typedef struct _PTE { -#ifdef CONFIG_PPC64BRIDGE - unsigned long long vsid:52; - unsigned long api:5; - unsigned long :5; - unsigned long h:1; - unsigned long v:1; - unsigned long long rpn:52; -#else /* CONFIG_PPC64BRIDGE */ - unsigned long v:1; /* Entry is valid */ - unsigned long vsid:24; /* Virtual segment identifier */ - unsigned long h:1; /* Hash algorithm indicator */ - unsigned long api:6; /* Abbreviated page index */ - unsigned long rpn:20; /* Real (physical) page number */ -#endif /* CONFIG_PPC64BRIDGE */ - unsigned long :3; /* Unused */ - unsigned long r:1; /* Referenced */ - unsigned long c:1; /* Changed */ - unsigned long w:1; /* Write-thru cache mode */ - unsigned long i:1; /* Cache inhibited */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page protection */ -} PTE; - -/* Values for PP (assumes Ks=0, Kp=1) */ -#define PP_RWXX 0 /* Supervisor read/write, User none */ -#define PP_RWRX 1 /* Supervisor read/write, User read */ -#define PP_RWRW 2 /* Supervisor read/write, User read/write */ -#define PP_RXRX 3 /* Supervisor read, User read */ - -/* Segment Register */ -typedef struct _SEGREG { - unsigned long t:1; /* Normal or I/O type */ - unsigned long ks:1; /* Supervisor 'key' (normally 0) */ - unsigned long kp:1; /* User 'key' (normally 1) */ - unsigned long n:1; /* No-execute */ - unsigned long :4; /* Unused */ - unsigned long vsid:24; /* Virtual Segment Identifier */ -} SEGREG; - -/* Block Address Translation (BAT) Registers */ -typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :8; /* unused */ - unsigned long w:1; - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long ks:1; /* Supervisor key (normally 0) */ - unsigned long kp:1; /* User key (normally 1) */ - unsigned long pp:2; /* Page access protections */ -} P601_BATU; - -typedef struct _BATU { /* Upper part of BAT (all except 601) */ -#ifdef CONFIG_PPC64BRIDGE - unsigned long long bepi:47; -#else /* CONFIG_PPC64BRIDGE */ - unsigned long bepi:15; /* Effective page index (virtual address) */ -#endif /* CONFIG_PPC64BRIDGE */ - unsigned long :4; /* Unused */ - unsigned long bl:11; /* Block size mask */ - unsigned long vs:1; /* Supervisor valid */ - unsigned long vp:1; /* User valid */ -} BATU; - -typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long v:1; /* Valid bit */ - unsigned long bl:6; /* Block size mask */ -} P601_BATL; - -typedef struct _BATL { /* Lower part of BAT (all except 601) */ -#ifdef CONFIG_PPC64BRIDGE - unsigned long long brpn:47; -#else /* CONFIG_PPC64BRIDGE */ - unsigned long brpn:15; /* Real page index (physical address) */ -#endif /* CONFIG_PPC64BRIDGE */ - unsigned long :10; /* Unused */ - unsigned long w:1; /* Write-thru cache */ - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded (MBZ in IBAT) */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page access protections */ -} BATL; - -typedef struct _BAT { - BATU batu; /* Upper register */ - BATL batl; /* Lower register */ -} BAT; - -typedef struct _P601_BAT { - P601_BATU batu; /* Upper register */ - P601_BATL batl; /* Lower register */ -} P601_BAT; - -/* - * Simulated two-level MMU. This structure is used by the kernel - * to keep track of MMU mappings and is used to update/maintain - * the hardware HASH table which is really a cache of mappings. - * - * The simulated structures mimic the hardware available on other - * platforms, notably the 80x86 and 680x0. - */ - -typedef struct _pte { - unsigned long page_num:20; - unsigned long flags:12; /* Page flags (some unused bits) */ -} pte; - -#define PD_SHIFT (10+12) /* Page directory */ -#define PD_MASK 0x02FF -#define PT_SHIFT (12) /* Page Table */ -#define PT_MASK 0x02FF -#define PG_SHIFT (12) /* Page Entry */ - - -/* MMU context */ - -typedef struct _MMU_context { - SEGREG segs[16]; /* Segment registers */ - pte **pmap; /* Two-level page-map structure */ -} MMU_context; - -extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ -extern void _tlbia(void); /* invalidate all TLB entries */ - -#ifdef CONFIG_ADDR_MAP -extern void init_addr_map(void); -#endif - -typedef enum { - IBAT0 = 0, IBAT1, IBAT2, IBAT3, - DBAT0, DBAT1, DBAT2, DBAT3, -#ifdef CONFIG_HIGH_BATS - IBAT4, IBAT5, IBAT6, IBAT7, - DBAT4, DBAT5, DBAT6, DBAT7 -#endif -} ppc_bat_t; - -extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); -extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); -extern void print_bats(void); - -#endif /* __ASSEMBLY__ */ - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 -#define BATU_INVALID 0x00000000 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 -#define BATL_NO_ACCESS 0x00000000 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -#define BATL_PP_NO_ACCESS BATL_PP_00 -#define BATL_PP_RO BATL_PP_01 -#define BATL_PP_RW BATL_PP_10 - -/* BAT Block size values */ -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -/* Block lengths for processors that support extended block length */ -#ifdef HID0_XBSEN -#define BATU_BL_512M 0x00003ffc -#define BATU_BL_1G 0x00007ffc -#define BATU_BL_2G 0x0000fffc -#define BATU_BL_4G 0x0001fffc -#define BATU_BL_MAX BATU_BL_4G -#else -#define BATU_BL_MAX BATU_BL_256M -#endif - -/* BAT Access Protection */ -#define BPP_XX 0x00 /* No access */ -#define BPP_RX 0x01 /* Read only */ -#define BPP_RW 0x02 /* Read/write */ - -/* Macros to get values from BATs, once data is in the BAT register format */ -#define BATU_VALID(x) (x & 0x3) -#define BATU_VADDR(x) (x & 0xfffe0000) -#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \ - | ((x & 0x0e00ULL) << 24) \ - | ((x & 0x04ULL) << 30))) -#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17)) - -/* bytes into BATU_BL */ -#define TO_BATU_BL(x) \ - (u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4) - -/* Used to set up SDR1 register */ -#define HASH_TABLE_SIZE_64K 0x00010000 -#define HASH_TABLE_SIZE_128K 0x00020000 -#define HASH_TABLE_SIZE_256K 0x00040000 -#define HASH_TABLE_SIZE_512K 0x00080000 -#define HASH_TABLE_SIZE_1M 0x00100000 -#define HASH_TABLE_SIZE_2M 0x00200000 -#define HASH_TABLE_SIZE_4M 0x00400000 -#define HASH_TABLE_MASK_64K 0x000 -#define HASH_TABLE_MASK_128K 0x001 -#define HASH_TABLE_MASK_256K 0x003 -#define HASH_TABLE_MASK_512K 0x007 -#define HASH_TABLE_MASK_1M 0x00F -#define HASH_TABLE_MASK_2M 0x01F -#define HASH_TABLE_MASK_4M 0x03F - -/* Control/status registers for the MPC8xx. - * A write operation to these registers causes serialized access. - * During software tablewalk, the registers used perform mask/shift-add - * operations when written/read. A TLB entry is created when the Mx_RPN - * is written, and the contents of several registers are used to - * create the entry. - */ -#define MI_CTR 784 /* Instruction TLB control register */ -#define MI_GPM 0x80000000 /* Set domain manager mode */ -#define MI_PPM 0x40000000 /* Set subpage protection */ -#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MI_RESETVAL 0x00000000 /* Value of register at reset */ - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define MI_AP 786 -#define MI_Ks 0x80000000 /* Should not be set */ -#define MI_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MI_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define MI_EPN 787 -#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MI_EVALID 0x00000200 /* Entry is valid */ -#define MI_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the instruction TLB, it contains bits that get loaded into the - * TLB entry when the MI_RPN is written. - */ -#define MI_TWC 789 -#define MI_APG 0x000001e0 /* Access protection group (0) */ -#define MI_GUARDED 0x00000010 /* Guarded storage */ -#define MI_PSMASK 0x0000000c /* Mask of page size bits */ -#define MI_PS8MEG 0x0000000c /* 8M page size */ -#define MI_PS512K 0x00000004 /* 512K page size */ -#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MI_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the instruction TLB, using - * additional information from the MI_EPN, and MI_TWC registers. - */ -#define MI_RPN 790 - -/* Define an RPN value for mapping kernel memory to large virtual - * pages for boot initialization. This has real page number of 0, - * large page size, shared page, cache enabled, and valid. - * Also mark all subpages valid and write access. - */ -#define MI_BOOTINIT 0x000001fd - -#define MD_CTR 792 /* Data TLB control register */ -#define MD_GPM 0x80000000 /* Set domain manager mode */ -#define MD_PPM 0x40000000 /* Set subpage protection */ -#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ -#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ -#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MD_RESETVAL 0x04000000 /* Value of register at reset */ - -#define M_CASID 793 /* Address space ID (context) to match */ -#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ - - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define MD_AP 794 -#define MD_Ks 0x80000000 /* Should not be set */ -#define MD_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MD_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define MD_EPN 795 -#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MD_EVALID 0x00000200 /* Entry is valid */ -#define MD_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* The pointer to the base address of the first level page table. - * During a software tablewalk, reading this register provides the address - * of the entry associated with MD_EPN. - */ -#define M_TWB 796 -#define M_L1TB 0xfffff000 /* Level 1 table base address */ -#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the data TLB, it contains bits that get loaded into the TLB entry - * when the MD_RPN is written. It is also provides the hardware assist - * for finding the PTE address during software tablewalk. - */ -#define MD_TWC 797 -#define MD_L2TB 0xfffff000 /* Level 2 table base address */ -#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ -#define MD_APG 0x000001e0 /* Access protection group (0) */ -#define MD_GUARDED 0x00000010 /* Guarded storage */ -#define MD_PSMASK 0x0000000c /* Mask of page size bits */ -#define MD_PS8MEG 0x0000000c /* 8M page size */ -#define MD_PS512K 0x00000004 /* 512K page size */ -#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MD_WT 0x00000002 /* Use writethrough page attribute */ -#define MD_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the data TLB, using - * additional information from the MD_EPN, and MD_TWC registers. - */ -#define MD_RPN 798 - -/* This is a temporary storage register that could be used to save - * a processor working register during a tablewalk. - */ -#define M_TW 799 - -/* - * At present, all PowerPC 400-class processors share a similar TLB - * architecture. The instruction and data sides share a unified, - * 64-entry, fully-associative TLB which is maintained totally under - * software control. In addition, the instruction side has a - * hardware-managed, 4-entry, fully- associative TLB which serves as a - * first level to the shared TLB. These two TLBs are known as the UTLB - * and ITLB, respectively. - */ - -#define PPC4XX_TLB_SIZE 64 - -/* - * TLB entries are defined by a "high" tag portion and a "low" data - * portion. On all architectures, the data portion is 32-bits. - * - * TLB entries are managed entirely under software control by reading, - * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx - * instructions. - */ - -/* - * FSL Book-E support - */ - -#define MAS0_TLBSEL_MSK 0x30000000 -#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK) -#define MAS0_ESEL_MSK 0x0FFF0000 -#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK) -#define MAS0_NV(x) ((x) & 0x00000FFF) - -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 -#define MAS1_TID(x) ((x << 16) & 0x3FFF0000) -#define MAS1_TS 0x00001000 -#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) - -#define MAS2_EPN 0xFFFFF000 -#define MAS2_X0 0x00000040 -#define MAS2_X1 0x00000020 -#define MAS2_W 0x00000010 -#define MAS2_I 0x00000008 -#define MAS2_M 0x00000004 -#define MAS2_G 0x00000002 -#define MAS2_E 0x00000001 - -#define MAS3_RPN 0xFFFFF000 -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 - -#define MAS4_TLBSELD(x) MAS0_TLBSEL(x) -#define MAS4_TIDDSEL 0x000F0000 -#define MAS4_TSIZED(x) MAS1_TSIZE(x) -#define MAS4_X0D 0x00000040 -#define MAS4_X1D 0x00000020 -#define MAS4_WD 0x00000010 -#define MAS4_ID 0x00000008 -#define MAS4_MD 0x00000004 -#define MAS4_GD 0x00000002 -#define MAS4_ED 0x00000001 - -#define MAS6_SPID0 0x3FFF0000 -#define MAS6_SPID1 0x00007FFE -#define MAS6_SAS 0x00000001 -#define MAS6_SPID MAS6_SPID0 - -#define MAS7_RPN 0xFFFFFFFF - -#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \ - (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv)) -#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \ - ((((v) << 31) & MAS1_VALID) |\ - (((iprot) << 30) & MAS1_IPROT) |\ - (MAS1_TID(tid)) |\ - (((ts) << 12) & MAS1_TS) |\ - (MAS1_TSIZE(tsize))) -#define FSL_BOOKE_MAS2(epn, wimge) \ - (((epn) & MAS3_RPN) | (wimge)) -#define FSL_BOOKE_MAS3(rpn, user, perms) \ - (((rpn) & MAS3_RPN) | (user) | (perms)) -#define FSL_BOOKE_MAS7(rpn) \ - (((u64)(rpn)) >> 32) - -#define BOOKE_PAGESZ_1K 0 -#define BOOKE_PAGESZ_4K 1 -#define BOOKE_PAGESZ_16K 2 -#define BOOKE_PAGESZ_64K 3 -#define BOOKE_PAGESZ_256K 4 -#define BOOKE_PAGESZ_1M 5 -#define BOOKE_PAGESZ_4M 6 -#define BOOKE_PAGESZ_16M 7 -#define BOOKE_PAGESZ_64M 8 -#define BOOKE_PAGESZ_256M 9 -#define BOOKE_PAGESZ_1G 10 -#define BOOKE_PAGESZ_4G 11 -#define BOOKE_PAGESZ_16GB 12 -#define BOOKE_PAGESZ_64GB 13 -#define BOOKE_PAGESZ_256GB 14 -#define BOOKE_PAGESZ_1TB 15 - -#ifdef CONFIG_E500 -#ifndef __ASSEMBLY__ -extern void set_tlb(u8 tlb, u32 epn, u64 rpn, - u8 perms, u8 wimge, - u8 ts, u8 esel, u8 tsize, u8 iprot); -extern void disable_tlb(u8 esel); -extern void invalidate_tlb(u8 tlb); -extern void init_tlbs(void); -extern int find_tlb_idx(void *addr, u8 tlbsel); -extern void init_used_tlb_cams(void); -extern int find_free_tlbcam(void); - -extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); - -extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); - -#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ - { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \ - .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \ - .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \ - .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \ - .mas7 = FSL_BOOKE_MAS7(_rpn), } - -struct fsl_e_tlb_entry { - u32 mas0; - u32 mas1; - u32 mas2; - u32 mas3; - u32 mas7; -}; - -extern struct fsl_e_tlb_entry tlb_table[]; -extern int num_tlb_entries; -#endif -#endif - -#ifdef CONFIG_E300 -#define LAWAR_EN 0x80000000 -#define LAWAR_SIZE 0x0000003F - -#define LAWAR_TRGT_IF_PCI 0x00000000 -#define LAWAR_TRGT_IF_PCI1 0x00000000 -#define LAWAR_TRGT_IF_PCIX 0x00000000 -#define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_PCIE1 0x00200000 -#define LAWAR_TRGT_IF_PCIE2 0x00100000 -#define LAWAR_TRGT_IF_PCIE3 0x00300000 -#define LAWAR_TRGT_IF_LBC 0x00400000 -#define LAWAR_TRGT_IF_CCSR 0x00800000 -#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 -#define LAWAR_TRGT_IF_RIO 0x00c00000 -#define LAWAR_TRGT_IF_DDR 0x00f00000 -#define LAWAR_TRGT_IF_DDR1 0x00f00000 -#define LAWAR_TRGT_IF_DDR2 0x01600000 - -#define LAWAR_SIZE_BASE 0xa -#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) -#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2) -#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3) -#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4) -#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5) -#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6) -#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7) -#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8) -#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9) -#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10) -#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11) -#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12) -#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13) -#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14) -#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15) -#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16) -#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17) -#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) -#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) -#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) -#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) -#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) -#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) -#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) -#endif - -#ifdef CONFIG_440 -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID )) -#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn)) -#define TLB2(a) ((a) & 0x00000fbf) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ;\ -0: mflr r0 ;\ - mtlr r1 ;\ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - -/*----------------------------------------------------------------------------+ -| TLB specific defines. -+----------------------------------------------------------------------------*/ -#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL -#define TLB_16MB_ALIGN_MASK 0xFFF000000ULL -#define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL -#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL -#define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL -#define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL -#define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL -#define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL -#define TLB_256MB_SIZE 0x10000000 -#define TLB_16MB_SIZE 0x01000000 -#define TLB_1MB_SIZE 0x00100000 -#define TLB_256KB_SIZE 0x00040000 -#define TLB_64KB_SIZE 0x00010000 -#define TLB_16KB_SIZE 0x00004000 -#define TLB_4KB_SIZE 0x00001000 -#define TLB_1KB_SIZE 0x00000400 - -#define TLB_WORD0_EPN_MASK 0xFFFFFC00 -#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD0_V_MASK 0x00000200 -#define TLB_WORD0_V_ENABLE 0x00000200 -#define TLB_WORD0_V_DISABLE 0x00000000 -#define TLB_WORD0_TS_MASK 0x00000100 -#define TLB_WORD0_TS_1 0x00000100 -#define TLB_WORD0_TS_0 0x00000000 -#define TLB_WORD0_SIZE_MASK 0x000000F0 -#define TLB_WORD0_SIZE_1KB 0x00000000 -#define TLB_WORD0_SIZE_4KB 0x00000010 -#define TLB_WORD0_SIZE_16KB 0x00000020 -#define TLB_WORD0_SIZE_64KB 0x00000030 -#define TLB_WORD0_SIZE_256KB 0x00000040 -#define TLB_WORD0_SIZE_1MB 0x00000050 -#define TLB_WORD0_SIZE_16MB 0x00000070 -#define TLB_WORD0_SIZE_256MB 0x00000090 -#define TLB_WORD0_TPAR_MASK 0x0000000F -#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) -#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) - -#define TLB_WORD1_RPN_MASK 0xFFFFFC00 -#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD1_PAR1_MASK 0x00000300 -#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) -#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03) -#define TLB_WORD1_PAR1_0 0x00000000 -#define TLB_WORD1_PAR1_1 0x00000100 -#define TLB_WORD1_PAR1_2 0x00000200 -#define TLB_WORD1_PAR1_3 0x00000300 -#define TLB_WORD1_ERPN_MASK 0x0000000F -#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) -#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) - -#define TLB_WORD2_PAR2_MASK 0xC0000000 -#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30) -#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03) -#define TLB_WORD2_PAR2_0 0x00000000 -#define TLB_WORD2_PAR2_1 0x40000000 -#define TLB_WORD2_PAR2_2 0x80000000 -#define TLB_WORD2_PAR2_3 0xC0000000 -#define TLB_WORD2_U0_MASK 0x00008000 -#define TLB_WORD2_U0_ENABLE 0x00008000 -#define TLB_WORD2_U0_DISABLE 0x00000000 -#define TLB_WORD2_U1_MASK 0x00004000 -#define TLB_WORD2_U1_ENABLE 0x00004000 -#define TLB_WORD2_U1_DISABLE 0x00000000 -#define TLB_WORD2_U2_MASK 0x00002000 -#define TLB_WORD2_U2_ENABLE 0x00002000 -#define TLB_WORD2_U2_DISABLE 0x00000000 -#define TLB_WORD2_U3_MASK 0x00001000 -#define TLB_WORD2_U3_ENABLE 0x00001000 -#define TLB_WORD2_U3_DISABLE 0x00000000 -#define TLB_WORD2_W_MASK 0x00000800 -#define TLB_WORD2_W_ENABLE 0x00000800 -#define TLB_WORD2_W_DISABLE 0x00000000 -#define TLB_WORD2_I_MASK 0x00000400 -#define TLB_WORD2_I_ENABLE 0x00000400 -#define TLB_WORD2_I_DISABLE 0x00000000 -#define TLB_WORD2_M_MASK 0x00000200 -#define TLB_WORD2_M_ENABLE 0x00000200 -#define TLB_WORD2_M_DISABLE 0x00000000 -#define TLB_WORD2_G_MASK 0x00000100 -#define TLB_WORD2_G_ENABLE 0x00000100 -#define TLB_WORD2_G_DISABLE 0x00000000 -#define TLB_WORD2_E_MASK 0x00000080 -#define TLB_WORD2_E_ENABLE 0x00000080 -#define TLB_WORD2_E_DISABLE 0x00000000 -#define TLB_WORD2_UX_MASK 0x00000020 -#define TLB_WORD2_UX_ENABLE 0x00000020 -#define TLB_WORD2_UX_DISABLE 0x00000000 -#define TLB_WORD2_UW_MASK 0x00000010 -#define TLB_WORD2_UW_ENABLE 0x00000010 -#define TLB_WORD2_UW_DISABLE 0x00000000 -#define TLB_WORD2_UR_MASK 0x00000008 -#define TLB_WORD2_UR_ENABLE 0x00000008 -#define TLB_WORD2_UR_DISABLE 0x00000000 -#define TLB_WORD2_SX_MASK 0x00000004 -#define TLB_WORD2_SX_ENABLE 0x00000004 -#define TLB_WORD2_SX_DISABLE 0x00000000 -#define TLB_WORD2_SW_MASK 0x00000002 -#define TLB_WORD2_SW_ENABLE 0x00000002 -#define TLB_WORD2_SW_DISABLE 0x00000000 -#define TLB_WORD2_SR_MASK 0x00000001 -#define TLB_WORD2_SR_ENABLE 0x00000001 -#define TLB_WORD2_SR_DISABLE 0x00000000 - -/*----------------------------------------------------------------------------+ -| Following instructions are not available in Book E mode of the GNU assembler. -+----------------------------------------------------------------------------*/ -#define DCCCI(ra,rb) .long 0x7c000000|\ - (ra<<16)|(rb<<11)|(454<<1) - -#define ICCCI(ra,rb) .long 0x7c000000|\ - (ra<<16)|(rb<<11)|(966<<1) - -#define DCREAD(rt,ra,rb) .long 0x7c000000|\ - (rt<<21)|(ra<<16)|(rb<<11)|(486<<1) - -#define ICREAD(ra,rb) .long 0x7c000000|\ - (ra<<16)|(rb<<11)|(998<<1) - -#define TLBSX(rt,ra,rb) .long 0x7c000000|\ - (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) - -#define TLBWE(rs,ra,ws) .long 0x7c000000|\ - (rs<<21)|(ra<<16)|(ws<<11)|(978<<1) - -#define TLBRE(rt,ra,ws) .long 0x7c000000|\ - (rt<<21)|(ra<<16)|(ws<<11)|(946<<1) - -#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\ - (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) - -#define MSYNC .long 0x7c000000|\ - (598<<1) - -#define MBAR_INST .long 0x7c000000|\ - (854<<1) - -#ifndef __ASSEMBLY__ -/* Prototypes */ -void mttlb1(unsigned long index, unsigned long value); -void mttlb2(unsigned long index, unsigned long value); -void mttlb3(unsigned long index, unsigned long value); -unsigned long mftlb1(unsigned long index); -unsigned long mftlb2(unsigned long index); -unsigned long mftlb3(unsigned long index); - -void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); -void remove_tlb(u32 vaddr, u32 size); -void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value); -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_440 */ -#endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/mp.h b/include/asm-ppc/mp.h deleted file mode 100644 index 5388c95..0000000 --- a/include/asm-ppc/mp.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_MP_H_ -#define _ASM_MP_H_ - -#include - -void setup_mp(void); -void cpu_mp_lmb_reserve(struct lmb *lmb); -u32 determine_mp_bootpg(void); - -#endif diff --git a/include/asm-ppc/mpc512x.h b/include/asm-ppc/mpc512x.h deleted file mode 100644 index 960e229..0000000 --- a/include/asm-ppc/mpc512x.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * include/asm-ppc/mpc512x.h - * - * Prototypes, etc. for the Freescale MPC512x embedded cpu chips - * - * 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASMPPC_MPC512X_H -#define __ASMPPC_MPC512X_H - -/* - * macros for manipulating CSx_START/STOP - */ -#define CSAW_START(start) ((start) & 0xFFFF0000) -#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) - -/* - * Inlines - */ - -/* - * According to MPC5121e RM, configuring local access windows should - * be followed by a dummy read of the config register that was - * modified last and an isync. - */ -static inline void sync_law(volatile void *addr) -{ - in_be32(addr); - __asm__ __volatile__ ("isync"); -} - -/* - * Prototypes - */ -extern long int fixed_sdram(ddr512x_config_t *mddrc_config, - u32 *dram_init_seq, int seq_sz); -extern int mpc5121_diu_init(void); -extern void ide_set_reset(int idereset); - -#endif /* __ASMPPC_MPC512X_H */ diff --git a/include/asm-ppc/mpc8349_pci.h b/include/asm-ppc/mpc8349_pci.h deleted file mode 100644 index 7a1adba..0000000 --- a/include/asm-ppc/mpc8349_pci.h +++ /dev/null @@ -1,168 +0,0 @@ -#ifndef _PPC_KERNEL_MPC8349_PCI_H -#define _PPC_KERNEL_MPC8349_PCI_H - - -#define M8265_PCIBR0 0x101ac -#define M8265_PCIBR1 0x101b0 -#define M8265_PCIMSK0 0x101c4 -#define M8265_PCIMSK1 0x101c8 - -/* Bit definitions for PCIBR registers */ - -#define PCIBR_ENABLE 0x00000001 - -/* Bit definitions for PCIMSK registers */ - -#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */ -#define PCIMSK_64KB 0xFFFF0000 -#define PCIMSK_128KB 0xFFFE0000 -#define PCIMSK_256KB 0xFFFC0000 -#define PCIMSK_512KB 0xFFF80000 -#define PCIMSK_1MB 0xFFF00000 -#define PCIMSK_2MB 0xFFE00000 -#define PCIMSK_4MB 0xFFC00000 -#define PCIMSK_8MB 0xFF800000 -#define PCIMSK_16MB 0xFF000000 -#define PCIMSK_32MB 0xFE000000 -#define PCIMSK_64MB 0xFC000000 -#define PCIMSK_128MB 0xF8000000 -#define PCIMSK_256MB 0xF0000000 -#define PCIMSK_512MB 0xE0000000 -#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */ - - -#define M826X_SCCR_PCI_MODE_EN 0x100 - - -/* - * Outbound ATU registers (3 sets). These registers control how 60x bus - * (local) addresses are translated to PCI addresses when the MPC826x is - * a PCI bus master (initiator). - */ - -#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ -#define POTAR_REG1 0x10818 -#define POTAR_REG2 0x10830 - -#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ -#define POBAR_REG1 0x10820 -#define POBAR_REG2 0x10838 - -#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ -#define POCMR_REG1 0x10828 -#define POCMR_REG2 0x10840 - -/* Bit definitions for POMCR registers */ - -#define POCMR_MASK_4KB 0x000FFFFF -#define POCMR_MASK_8KB 0x000FFFFE -#define POCMR_MASK_16KB 0x000FFFFC -#define POCMR_MASK_32KB 0x000FFFF8 -#define POCMR_MASK_64KB 0x000FFFF0 -#define POCMR_MASK_128KB 0x000FFFE0 -#define POCMR_MASK_256KB 0x000FFFC0 -#define POCMR_MASK_512KB 0x000FFF80 -#define POCMR_MASK_1MB 0x000FFF00 -#define POCMR_MASK_2MB 0x000FFE00 -#define POCMR_MASK_4MB 0x000FFC00 -#define POCMR_MASK_8MB 0x000FF800 -#define POCMR_MASK_16MB 0x000FF000 -#define POCMR_MASK_32MB 0x000FE000 -#define POCMR_MASK_64MB 0x000FC000 -#define POCMR_MASK_128MB 0x000F8000 -#define POCMR_MASK_256MB 0x000F0000 -#define POCMR_MASK_512MB 0x000E0000 -#define POCMR_MASK_1GB 0x000C0000 - -#define POCMR_ENABLE 0x80000000 -#define POCMR_PCI_IO 0x40000000 -#define POCMR_PREFETCH_EN 0x20000000 -#define POCMR_PCI2 0x10000000 - -/* Soft PCI reset */ - -#define PCI_GCR_REG 0x10880 - -/* Bit definitions for PCI_GCR registers */ - -#define PCIGCR_PCI_BUS_EN 0x1 - -/* - * Inbound ATU registers (2 sets). These registers control how PCI - * addresses are translated to 60x bus (local) addresses when the - * MPC826x is a PCI bus target. - */ - -#define PITAR_REG1 0x108D0 -#define PIBAR_REG1 0x108D8 -#define PICMR_REG1 0x108E0 -#define PITAR_REG0 0x108E8 -#define PIBAR_REG0 0x108F0 -#define PICMR_REG0 0x108F8 - -/* Bit definitions for PCI Inbound Comparison Mask registers */ - -#define PICMR_MASK_4KB 0x000FFFFF -#define PICMR_MASK_8KB 0x000FFFFE -#define PICMR_MASK_16KB 0x000FFFFC -#define PICMR_MASK_32KB 0x000FFFF8 -#define PICMR_MASK_64KB 0x000FFFF0 -#define PICMR_MASK_128KB 0x000FFFE0 -#define PICMR_MASK_256KB 0x000FFFC0 -#define PICMR_MASK_512KB 0x000FFF80 -#define PICMR_MASK_1MB 0x000FFF00 -#define PICMR_MASK_2MB 0x000FFE00 -#define PICMR_MASK_4MB 0x000FFC00 -#define PICMR_MASK_8MB 0x000FF800 -#define PICMR_MASK_16MB 0x000FF000 -#define PICMR_MASK_32MB 0x000FE000 -#define PICMR_MASK_64MB 0x000FC000 -#define PICMR_MASK_128MB 0x000F8000 -#define PICMR_MASK_256MB 0x000F0000 -#define PICMR_MASK_512MB 0x000E0000 -#define PICMR_MASK_1GB 0x000C0000 - -#define PICMR_ENABLE 0x80000000 -#define PICMR_NO_SNOOP_EN 0x40000000 -#define PICMR_PREFETCH_EN 0x20000000 - -/* PCI error Registers */ - -#define PCI_ERROR_STATUS_REG 0x10884 -#define PCI_ERROR_MASK_REG 0x10888 -#define PCI_ERROR_CONTROL_REG 0x1088C -#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 -#define PCI_ERROR_DATA_CAPTURE_REG 0x10898 -#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 - -/* PCI error Register bit defines */ - -#define PCI_ERROR_PCI_ADDR_PAR 0x00000001 -#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 -#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 -#define PCI_ERROR_PCI_NO_RSP 0x00000008 -#define PCI_ERROR_PCI_TAR_ABT 0x00000010 -#define PCI_ERROR_PCI_SERR 0x00000020 -#define PCI_ERROR_PCI_PERR_RD 0x00000040 -#define PCI_ERROR_PCI_PERR_WR 0x00000080 -#define PCI_ERROR_I2O_OFQO 0x00000100 -#define PCI_ERROR_I2O_IPQO 0x00000200 -#define PCI_ERROR_IRA 0x00000400 -#define PCI_ERROR_NMI 0x00000800 -#define PCI_ERROR_I2O_DBMC 0x00001000 - -/* - * Register pair used to generate configuration cycles on the PCI bus - * and access the MPC826x's own PCI configuration registers. - */ - -#define PCI_CFG_ADDR_REG 0x10900 -#define PCI_CFG_DATA_REG 0x10904 - -/* Bus parking decides where the bus control sits when idle */ -/* If modifying memory controllers for PCI park on the core */ - -#define PPC_ACR_BUS_PARK_CORE 0x6 -#define PPC_ACR_BUS_PARK_PCI 0x3 - -#endif /* _PPC_KERNEL_M8260_PCI_H */ diff --git a/include/asm-ppc/mpc8xxx_spi.h b/include/asm-ppc/mpc8xxx_spi.h deleted file mode 100644 index 41737d3..0000000 --- a/include/asm-ppc/mpc8xxx_spi.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Freescale non-CPM SPI Controller - * - * Copyright 2008 Qstreams Networks, Inc. - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_MPC8XXX_SPI_H_ -#define _ASM_MPC8XXX_SPI_H_ - -#include - -#if defined(CONFIG_MPC834x) || \ - defined(CONFIG_MPC8313) || \ - defined(CONFIG_MPC8315) || \ - defined(CONFIG_MPC837x) - -typedef struct spi8xxx { - u8 res0[0x20]; /* 0x0-0x01f reserved */ - u32 mode; /* mode register */ - u32 event; /* event register */ - u32 mask; /* mask register */ - u32 com; /* command register */ - u32 tx; /* transmit register */ - u32 rx; /* receive register */ - u8 res1[0xFC8]; /* fill up to 0x1000 */ -} spi8xxx_t; - -#endif - -#endif /* _ASM_MPC8XXX_SPI_H_ */ diff --git a/include/asm-ppc/pci_io.h b/include/asm-ppc/pci_io.h deleted file mode 100644 index 9b738c3..0000000 --- a/include/asm-ppc/pci_io.h +++ /dev/null @@ -1,43 +0,0 @@ -/* originally from linux source (asm-ppc/io.h). - * Sanity added by Rob Taylor, Flying Pig Systems, 2000 - */ -#ifndef _PCI_IO_H_ -#define _PCI_IO_H_ - -#include "io.h" - - -#define pci_read_le16(addr, dest) \ - __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \ - "r" (addr), "m" (*addr)); - -#define pci_write_le16(addr, val) \ - __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \ - "r" (val), "r" (addr)); - - -#define pci_read_le32(addr, dest) \ - __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \ - "r" (addr), "m" (*addr)); - -#define pci_write_le32(addr, val) \ -__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \ - "r" (val), "r" (addr)); - -#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr)) -#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) - -#if !defined(__BIG_ENDIAN) -#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr)) -#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr)) -#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) -#else -#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b)) -#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b)) -#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b)) -#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b)) -#endif - - -#endif /* _PCI_IO_H_ */ diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h deleted file mode 100644 index 22ceba2..0000000 --- a/include/asm-ppc/pnp.h +++ /dev/null @@ -1,643 +0,0 @@ -/* 11/02/95 */ -/*----------------------------------------------------------------------------*/ -/* Plug and Play header definitions */ -/*----------------------------------------------------------------------------*/ - -/* Structure map for PnP on PowerPC Reference Platform */ -/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ -/* (or later versions) is available on Compuserve in the PLUGPLAY area. */ -/* This code has extensions to that specification, namely new short and */ -/* long tag types for platform dependent information */ - -/* Warning: LE notation used throughout this file */ - -/* For enum's: if given in hex then they are bit significant, i.e. */ -/* only one bit is on for each enum */ - -#ifndef _PNP_ -#define _PNP_ - -#ifndef __ASSEMBLY__ -#define MAX_MEM_REGISTERS 9 -#define MAX_IO_PORTS 20 -#define MAX_IRQS 7 -/*#define MAX_DMA_CHANNELS 7*/ - -/* Interrupt controllers */ - -#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ -#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ -#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ -#define PNPinterrupt3 "PNP0003" /* APIC */ -#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ - -/* Timers */ - -#define PNPtimer0 "PNP0100" /* AT Timer */ -#define PNPtimer1 "PNP0101" /* EISA Timer */ -#define PNPtimer2 "PNP0102" /* MCA Timer */ - -/* DMA controllers */ - -#define PNPdma0 "PNP0200" /* AT DMA Controller */ -#define PNPdma1 "PNP0201" /* EISA DMA Controller */ -#define PNPdma2 "PNP0202" /* MCA DMA Controller */ - -/* start of August 15, 1994 additions */ -/* CMOS */ -#define PNPCMOS "IBM0009" /* CMOS */ - -/* L2 Cache */ -#define PNPL2 "IBM0007" /* L2 Cache */ - -/* NVRAM */ -#define PNPNVRAM "IBM0008" /* NVRAM */ - -/* Power Management */ -#define PNPPM "IBM0005" /* Power Management */ -/* end of August 15, 1994 additions */ - -/* Keyboards */ - -#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ -#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ -#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ -#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ -#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ -#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ -#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ -#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ - -/* Parallel port controllers */ - -#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ -#define PNPparallel1 "PNP0401" /* ECP Parallel Port */ -#define PNPepp "IBM001C" /* EPP Parallel Port */ - -/* Serial port controllers */ - -#define PNPserial0 "PNP0500" /* Standard PC Serial port */ -#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ - -/* Disk controllers */ - -#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ -#define PNPdisk1 "PNP0601" /* Plus Hardcard II */ -#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ - -/* Diskette controllers */ - -#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ - -/* Display controllers */ - -#define PNPdisplay0 "PNP0900" /* VGA Compatible */ -#define PNPdisplay1 "PNP0901" /* Video Seven VGA */ -#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ -#define PNPdisplay3 "PNP0903" /* Trident VGA */ -#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ -#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ -#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ -#define PNPdisplay7 "PNP0907" /* Western Digital VGA */ -#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ -#define PNPdisplay9 "PNP0909" /* S3 */ -#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ -#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ -#define PNPdisplayC "PNP090C" /* XGA Compatible */ -#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ -#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ -#define PNPdisplayF "PNP090F" /* Oak Technology VGA */ - -/* Peripheral busses */ - -#define PNPbuses0 "PNP0A00" /* ISA Bus */ -#define PNPbuses1 "PNP0A01" /* EISA Bus */ -#define PNPbuses2 "PNP0A02" /* MCA Bus */ -#define PNPbuses3 "PNP0A03" /* PCI Bus */ -#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ - -/* RTC, BIOS, planar devices */ - -#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ -#define PNPrtc0 "PNP0B00" /* AT RTC */ -#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ -#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ -#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ -#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ - -/* PCMCIA controller */ - -#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ - -/* Mice */ - -#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ -#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ -#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ -#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ -#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ -#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ -#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ -#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ -#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ -#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ -#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ -#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ - -/* Modems */ - -#define PNPmodem0 "PNP9000" /* Specific IDs TBD */ - -/* Network controllers */ - -#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ -#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ -#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ -#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ -#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ -#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ -#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ -#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ - -/* SCSI controllers */ - -#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ -#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ -#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ -#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ -#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ -#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ -#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ - -/* Sound/Video, Multimedia */ - -#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ -#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ -#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ -#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ -#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ -#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ -#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ -#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ - -/* Operator Panel */ -#define PNPopctl "IBM000B" /* Operator's panel */ - -/* Service Processor */ -#define PNPsp "IBM0011" /* IBM Service Processor */ -#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ -#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ - -/* Memory Controller */ -#define PNPmemctl "IBM000A" /* Memory controller */ - -/* Graphics Assist */ -#define PNPg_assist "IBM0014" /* Graphics Assist */ - -/* Miscellaneous Device Controllers */ -#define PNPtablet "IBM0019" /* IBM Tablet Controller */ - -/* PNP Packet Handles */ - -#define S1_Packet 0x0A /* Version resource */ -#define S2_Packet 0x15 /* Logical DEVID (without flags) */ -#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ -#define S3_Packet 0x1C /* Compatible device ID */ -#define S4_Packet 0x22 /* IRQ resource (without flags) */ -#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ -#define S5_Packet 0x2A /* DMA resource */ -#define S6_Packet 0x30 /* Depend funct start (w/o priority) */ -#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ -#define S7_Packet 0x38 /* Depend funct end */ -#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ -#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ -#define S14_Packet 0x71 /* Vendor defined */ -#define S15_Packet 0x78 /* End of resource (w/o checksum) */ -#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ -#define L1_Packet 0x81 /* Memory range */ -#define L1_Shadow 0x20 /* Memory is shadowable */ -#define L1_32bit_mem 0x18 /* 32-bit memory only */ -#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ -#define L1_Decode_Hi 0x04 /* decode supports high address */ -#define L1_Cache 0x02 /* read cacheable, write-through */ -#define L1_Writeable 0x01 /* Memory is writeable */ -#define L2_Packet 0x82 /* ANSI ID string */ -#define L3_Packet 0x83 /* Unicode ID string */ -#define L4_Packet 0x84 /* Vendor defined */ -#define L5_Packet 0x85 /* Large I/O */ -#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ -#define END_TAG 0x78 /* End of resource */ -#define DF_START_TAG 0x30 /* Dependent function start */ -#define DF_START_TAG_priority 0x31 /* Dependent function start */ -#define DF_END_TAG 0x38 /* Dependent function end */ -#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ - -/* Device Base Type Codes */ - -typedef enum _PnP_BASE_TYPE { - Reserved = 0, - MassStorageDevice = 1, - NetworkInterfaceController = 2, - DisplayController = 3, - MultimediaController = 4, - MemoryController = 5, - BridgeController = 6, - CommunicationsDevice = 7, - SystemPeripheral = 8, - InputDevice = 9, - ServiceProcessor = 0x0A, /* 11/2/95 */ - } PnP_BASE_TYPE; - -/* Device Sub Type Codes */ - -typedef enum _PnP_SUB_TYPE { - SCSIController = 0, - IDEController = 1, - FloppyController = 2, - IPIController = 3, - OtherMassStorageController = 0x80, - - EthernetController = 0, - TokenRingController = 1, - FDDIController = 2, - OtherNetworkController = 0x80, - - VGAController= 0, - SVGAController= 1, - XGAController= 2, - OtherDisplayController = 0x80, - - VideoController = 0, - AudioController = 1, - OtherMultimediaController = 0x80, - - RAM = 0, - FLASH = 1, - OtherMemoryDevice = 0x80, - - HostProcessorBridge = 0, - ISABridge = 1, - EISABridge = 2, - MicroChannelBridge = 3, - PCIBridge = 4, - PCMCIABridge = 5, - VMEBridge = 6, - OtherBridgeDevice = 0x80, - - RS232Device = 0, - ATCompatibleParallelPort = 1, - OtherCommunicationsDevice = 0x80, - - ProgrammableInterruptController = 0, - DMAController = 1, - SystemTimer = 2, - RealTimeClock = 3, - L2Cache = 4, - NVRAM = 5, - PowerManagement = 6, - CMOS = 7, - OperatorPanel = 8, - ServiceProcessorClass1 = 9, - ServiceProcessorClass2 = 0xA, - ServiceProcessorClass3 = 0xB, - GraphicAssist = 0xC, - SystemPlanar = 0xF, /* 10/5/95 */ - OtherSystemPeripheral = 0x80, - - KeyboardController = 0, - Digitizer = 1, - MouseController = 2, - TabletController = 3, /* 10/27/95 */ - OtherInputController = 0x80, - - GeneralMemoryController = 0, - } PnP_SUB_TYPE; - -/* Device Interface Type Codes */ - -typedef enum _PnP_INTERFACE { - General = 0, - GeneralSCSI = 0, - GeneralIDE = 0, - ATACompatible = 1, - - GeneralFloppy = 0, - Compatible765 = 1, - NS398_Floppy = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26E_Floppy = 3, /* Ports 26E and 26F */ - NS15C_Floppy = 4, /* Ports 15C and 15D */ - NS2E_Floppy = 5, /* Ports 2E and 2F */ - CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ - - GeneralIPI = 0, - - GeneralEther = 0, - GeneralToken = 0, - GeneralFDDI = 0, - - GeneralVGA = 0, - GeneralSVGA = 0, - GeneralXGA = 0, - - GeneralVideo = 0, - GeneralAudio = 0, - CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ - - GeneralRAM = 0, - GeneralFLASH = 0, - PCIMemoryController = 0, /* PCI Config Method */ - RS6KMemoryController = 1, /* RS6K Config Method */ - - GeneralHostBridge = 0, - GeneralISABridge = 0, - GeneralEISABridge = 0, - GeneralMCABridge = 0, - GeneralPCIBridge = 0, - PCIBridgeDirect = 0, - PCIBridgeIndirect = 1, - PCIBridgeRS6K = 2, - GeneralPCMCIABridge = 0, - GeneralVMEBridge = 0, - - GeneralRS232 = 0, - COMx = 1, - Compatible16450 = 2, - Compatible16550 = 3, - NS398SerPort = 4, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26ESerPort = 5, /* Ports 26E and 26F */ - NS15CSerPort = 6, /* Ports 15C and 15D */ - NS2ESerPort = 7, /* Ports 2E and 2F */ - - GeneralParPort = 0, - LPTx = 1, - NS398ParPort = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26EParPort = 3, /* Ports 26E and 26F */ - NS15CParPort = 4, /* Ports 15C and 15D */ - NS2EParPort = 5, /* Ports 2E and 2F */ - - GeneralPIC = 0, - ISA_PIC = 1, - EISA_PIC = 2, - MPIC = 3, - RS6K_PIC = 4, - - GeneralDMA = 0, - ISA_DMA = 1, - EISA_DMA = 2, - - GeneralTimer = 0, - ISA_Timer = 1, - EISA_Timer = 2, - GeneralRTC = 0, - ISA_RTC = 1, - - StoreThruOnly = 1, - StoreInEnabled = 2, - RS6KL2Cache = 3, - - IndirectNVRAM = 0, /* Indirectly addressed */ - DirectNVRAM = 1, /* Memory Mapped */ - IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ - - GeneralPowerManagement = 0, - EPOWPowerManagement = 1, - PowerControl = 2, /* d1378 */ - - GeneralCMOS = 0, - - GeneralOPPanel = 0, - HarddiskLight = 1, - CDROMLight = 2, - PowerLight = 3, - KeyLock = 4, - ANDisplay = 5, /* AlphaNumeric Display */ - SystemStatusLED = 6, /* 3 digit 7 segment LED */ - CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ - - GeneralServiceProcessor = 0, - - TransferData = 1, - IGMC32 = 2, - IGMC64 = 3, - - GeneralSystemPlanar = 0, /* 10/5/95 */ - - } PnP_INTERFACE; - -/* PnP resources */ - -/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ - -typedef struct _SERIAL_ID { - unsigned char VendorID0; /* Bit(7)=0 */ - /* Bits(6:2)=1st character in */ - /* compressed ASCII */ - /* Bits(1:0)=2nd character in */ - /* compressed ASCII bits(4:3) */ - unsigned char VendorID1; /* Bits(7:5)=2nd character in */ - /* compressed ASCII bits(2:0) */ - /* Bits(4:0)=3rd character in */ - /* compressed ASCII */ - unsigned char VendorID2; /* Product number - vendor assigned */ - unsigned char VendorID3; /* Product number - vendor assigned */ - -/* Serial number is to provide uniqueness if more than one board of same */ -/* type is in system. Must be "FFFFFFFF" if feature not supported. */ - - unsigned char Serial0; /* Unique serial number bits (7:0) */ - unsigned char Serial1; /* Unique serial number bits (15:8) */ - unsigned char Serial2; /* Unique serial number bits (23:16) */ - unsigned char Serial3; /* Unique serial number bits (31:24) */ - unsigned char Checksum; - } SERIAL_ID; - -typedef enum _PnPItemName { - Unused = 0, - PnPVersion = 1, - LogicalDevice = 2, - CompatibleDevice = 3, - IRQFormat = 4, - DMAFormat = 5, - StartDepFunc = 6, - EndDepFunc = 7, - IOPort = 8, - FixedIOPort = 9, - Res1 = 10, - Res2 = 11, - Res3 = 12, - SmallVendorItem = 14, - EndTag = 15, - MemoryRange = 1, - ANSIIdentifier = 2, - UnicodeIdentifier = 3, - LargeVendorItem = 4, - MemoryRange32 = 5, - MemoryRangeFixed32 = 6, - } PnPItemName; - -/* Define a bunch of access functions for the bits in the tag field */ - -/* Tag type - 0 = small; 1 = large */ -#define tag_type(t) (((t) & 0x80)>>7) -#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) - -/* Small item name is 4 bits - one of PnPItemName enum above */ -#define tag_small_item_name(t) (((t) & 0x78)>>3) -#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) - -/* Small item count is 3 bits - count of further bytes in packet */ -#define tag_small_count(t) ((t) & 0x07) -#define set_tag_count(t,v) (t = (t & 0x78) | (v)) - -/* Large item name is 7 bits - one of PnPItemName enum above */ -#define tag_large_item_name(t) ((t) & 0x7f) -#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) - -/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ - -typedef union _PnP_TAG_PACKET { - struct _S1_Pack{ /* VERSION PACKET */ - unsigned char Tag; /* small tag = 0x0a */ - unsigned char Version[2]; /* PnP version, Vendor version */ - } S1_Pack; - - struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ - unsigned char Tag; /* small tag = 0x15 or 0x16 */ - unsigned char DevId[4]; /* Logical device id */ - unsigned char Flags[2]; /* bit(0) boot device; */ - /* bit(7:1) cmd in range x31-x37 */ - /* bit(7:0) cmd in range x28-x3f (opt)*/ - } S2_Pack; - - struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ - unsigned char Tag; /* small tag = 0x1c */ - unsigned char CompatId[4]; /* Compatible device id */ - } S3_Pack; - - struct _S4_Pack{ /* IRQ PACKET */ - unsigned char Tag; /* small tag = 0x22 or 0x23 */ - unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ - /* bit(0) is IRQ8 ... */ - unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ - /* bit(0) - high true edge sensitive */ - /* bit(1) - low true edge sensitive */ - /* bit(2) - high true level sensitive*/ - /* bit(3) - low true level sensitive */ - /* bit(7:4) - must be 0 */ - } S4_Pack; - - struct _S5_Pack{ /* DMA PACKET */ - unsigned char Tag; /* small tag = 0x2a */ - unsigned char DMAMask; /* bit(0) is channel 0 ... */ - unsigned char DMAInfo; - } S5_Pack; - - struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ - unsigned char Tag; /* small tag = 0x30 or 0x31 */ - unsigned char Priority; /* Optional; if missing then x01; else*/ - /* x00 = best possible */ - /* x01 = acceptible */ - /* x02 = sub-optimal but functional */ - } S6_Pack; - - struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ - unsigned char Tag; /* small tag = 0x38 */ - } S7_Pack; - - struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ - unsigned char Tag; /* small tag x47 */ - unsigned char IOInfo; /* x0 = decode only bits(9:0); */ -#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ - unsigned char RangeMin[2]; /* Min base address */ - unsigned char RangeMax[2]; /* Max base address */ - unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ - unsigned char IONum; /* number of contiguous I/O ports */ - } S8_Pack; - - struct _S9_Pack{ /* FIXED I/O PORT PACKET */ - unsigned char Tag; /* small tag = 0x4b */ - unsigned char Range[2]; /* base address 10 bits */ - unsigned char IONum; /* number of contiguous I/O ports */ - } S9_Pack; - - struct _S14_Pack{ /* VENDOR DEFINED PACKET */ - unsigned char Tag; /* small tag = 0x7m m = 1-7 */ - union _S14_Data{ - unsigned char Data[7]; /* Vendor defined */ - struct _S14_PPCPack{ /* Pr*p s14 pack */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[6]; /* Vendor defined */ - } S14_PPCPack; - } S14_Data; - } S14_Pack; - - struct _S15_Pack{ /* END PACKET */ - unsigned char Tag; /* small tag = 0x78 or 0x79 */ - unsigned char Check; /* optional - checksum */ - } S15_Pack; - - struct _L1_Pack{ /* MEMORY RANGE PACKET */ - unsigned char Tag; /* large tag = 0x81 */ - unsigned char Count0; /* x09 */ - unsigned char Count1; /* x00 */ - unsigned char Data[9]; /* a variable array of bytes, */ - /* count in tag */ - } L1_Pack; - - struct _L2_Pack{ /* ANSI ID STRING PACKET */ - unsigned char Tag; /* large tag = 0x82 */ - unsigned char Count0; /* Length of string */ - unsigned char Count1; - unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ - } L2_Pack; - - struct _L3_Pack{ /* UNICODE ID STRING PACKET */ - unsigned char Tag; /* large tag = 0x83 */ - unsigned char Count0; /* Length + 2 of string */ - unsigned char Count1; - unsigned char Country0; /* TBD */ - unsigned char Country1; /* TBD */ - unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ - } L3_Pack; - - struct _L4_Pack{ /* VENDOR DEFINED PACKET */ - unsigned char Tag; /* large tag = 0x84 */ - unsigned char Count0; - unsigned char Count1; - union _L4_Data{ - unsigned char Data[1]; /* a variable array of bytes, */ - /* count in tag */ - struct _L4_PPCPack{ /* Pr*p L4 packet */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[1]; /* a variable array of bytes, */ - /* count in tag */ - } L4_PPCPack; - } L4_Data; - } L4_Pack; - - struct _L5_Pack{ - unsigned char Tag; /* large tag = 0x85 */ - unsigned char Count0; /* Count = 17 */ - unsigned char Count1; - unsigned char Data[17]; - } L5_Pack; - - struct _L6_Pack{ - unsigned char Tag; /* large tag = 0x86 */ - unsigned char Count0; /* Count = 9 */ - unsigned char Count1; - unsigned char Data[9]; - } L6_Pack; - - } PnP_TAG_PACKET; - -#endif /* __ASSEMBLY__ */ -#endif /* ndef _PNP_ */ diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h deleted file mode 100644 index 9170728..0000000 --- a/include/asm-ppc/posix_types.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef _PPC_POSIX_TYPES_H -#define _PPC_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned int __kernel_dev_t; -typedef unsigned int __kernel_ino_t; -typedef unsigned int __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned int __kernel_uid_t; -typedef unsigned int __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef long __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned int __kernel_old_uid_t; -typedef unsigned int __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { - int val[2]; -} __kernel_fsid_t; - -#ifndef __GNUC__ - -#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) -#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) -#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) -#define __FD_ZERO(set) \ - ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set))) - -#else /* __GNUC__ */ - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ - || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) -/* With GNU C, use inline functions instead so args are evaluated only once: */ - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - fdsetp->fds_bits[_tmp] |= (1UL<<_rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem); -} - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *p) -{ - unsigned int *tmp = (unsigned int *)p->fds_bits; - int i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 8: - tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0; - tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0; - return; - } - } - i = __FDSET_LONGS; - while (i) { - i--; - *tmp = 0; - tmp++; - } -} - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ -#endif /* __GNUC__ */ -#endif /* _PPC_POSIX_TYPES_H */ diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h deleted file mode 100644 index 9c17e46..0000000 --- a/include/asm-ppc/ppc4xx-ebc.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PPC4xx_EBC_H_ -#define _PPC4xx_EBC_H_ - -/* - * Currently there are two register layout versions for the IBM EBC core - * used on 4xx PPC's. The following grouping lists the first layout. - * Within this group there is a slight variation concerning the bit field - * position of the EMPL and EMPH fields: - */ -#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ - defined(CONFIG_405EP) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define CONFIG_EBC_PPC4xx_IBM_VER1 -#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ - defined(CONFIG_405EP) -#define EBC_CFG_EMPH_POS 8 -#define EBC_CFG_EMPL_POS 6 -#else -#define EBC_CFG_EMPH_POS 6 -#define EBC_CFG_EMPL_POS 8 -#endif -#endif - -/* - * Define the max number of EBC banks (chip selects) - */ -#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ - defined(CONFIG_405EZ) || \ - defined(CONFIG_440GP) || defined(CONFIG_440GX) -#define EBC_NUM_BANKS 8 -#endif - -#if defined(CONFIG_405EP) -#define EBC_NUM_BANKS 5 -#endif - -#if defined(CONFIG_405EX) || \ - defined(CONFIG_460SX) -#define EBC_NUM_BANKS 4 -#endif - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define EBC_NUM_BANKS 6 -#endif - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define EBC_NUM_BANKS 3 -#endif - -/* Bank Configuration Register */ -#define EBC_BXCR(n) (n) -#define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17)) - -#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) -#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK)) -#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) -#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) -#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) -#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) -#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) -#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) -#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) -#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) -#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) -#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) -#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) -#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) -#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) -#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) -#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) -#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) -#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) -#if defined(CONFIG_EBC_PPC4xx_IBM_VER1) -#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x2) -#else -#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) -#endif - -/* Bank Access Parameter Register */ -#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) -#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) -#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF) -#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F) -#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7) -#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) -#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) -#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) -#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) -#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) -#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) -#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) -#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3) -#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3) -#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3) -#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3) -#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7) -#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) -#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) -#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) -#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) -#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) -#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) -#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) -#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) - -/* Common fields in EBC0_CFG register */ -#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) -#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) -#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) -#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) -#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) -#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) -#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) -#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) -#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) -#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) -#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) -#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) -#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) -#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) -#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) -#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) -#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F) - -/* Now the two versions of the other bits */ -#if defined(CONFIG_EBC_PPC4xx_IBM_VER1) -#define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1) -#define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0) -#define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1) -#define EBC_CFG_EMPH_MASK PPC_REG_VAL(EBC_CFG_EMPH_POS, 0x3) -#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \ - (static_cast(u32, n)) & 0x3) -#define EBC_CFG_EMPL_MASK PPC_REG_VAL(EBC_CFG_EMPL_POS, 0x3) -#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(EBC_CFG_EMPH_POS, \ - (static_cast(u32, n)) & 0x3) -#define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1) -#define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0) -#define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1) -#define EBC_CFG_BPR_MASK PPC_REG_VAL(11, 0x3) -#define EBC_CFG_BPR_1DW PPC_REG_VAL(11, 0x0) -#define EBC_CFG_BPR_2DW PPC_REG_VAL(11, 0x1) -#define EBC_CFG_BPR_4DW PPC_REG_VAL(11, 0x2) -#define EBC_CFG_EMS_MASK PPC_REG_VAL(13, 0x3) -#define EBC_CFG_EMS_8BIT PPC_REG_VAL(13, 0x0) -#define EBC_CFG_EMS_16BIT PPC_REG_VAL(13, 0x1) -#define EBC_CFG_EMS_32BIT PPC_REG_VAL(13, 0x2) -#else -#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) -#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) -#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) -#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) -#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) -#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) -#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) -#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) -#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) -#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) -#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) -#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) -#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) -#define EBC_CFG_OEO_HI PPC_REG_VAL(8, 0x0) -#define EBC_CFG_OEO_PREVIOUS PPC_REG_VAL(8, 0x1) -#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) -#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) -#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) -#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) -#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) -#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) -#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) -#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) -#endif - -#endif /* _PPC4xx_EBC_H_ */ diff --git a/include/asm-ppc/ppc4xx-isram.h b/include/asm-ppc/ppc4xx-isram.h deleted file mode 100644 index d6d17ac..0000000 --- a/include/asm-ppc/ppc4xx-isram.h +++ /dev/null @@ -1,75 +0,0 @@ - -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PPC4xx_ISRAM_H_ -#define _PPC4xx_ISRAM_H_ - -/* - * Internal SRAM - */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define ISRAM0_DCR_BASE 0x380 -#else -#define ISRAM0_DCR_BASE 0x020 -#endif -#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ -#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ -#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ -#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ -#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ -#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ -#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ -#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ -#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ -#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ -#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define ISRAM1_DCR_BASE 0x0B0 -#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ -#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ -#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */ -#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */ -#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */ -#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */ -#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */ -#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */ -#endif /* CONFIG_460EX || CONFIG_460GT */ - -/* - * L2 Cache - */ -#if defined (CONFIG_440GX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) -#define L2_CACHE_BASE 0x030 -#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ -#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ -#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */ -#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */ -#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */ -#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ -#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ -#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ -#endif /* CONFIG_440GX */ - -#endif /* _PPC4xx_ISRAM_H_ */ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h deleted file mode 100644 index 92be514..0000000 --- a/include/asm-ppc/ppc4xx-sdram.h +++ /dev/null @@ -1,1411 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PPC4xx_SDRAM_H_ -#define _PPC4xx_SDRAM_H_ - -#if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM) - -/* - * SDRAM Controller - */ - -#ifndef CONFIG_405EP -#define SDRAM0_BESR0 0x00 /* bus error syndrome reg a */ -#define SDRAM0_BESRS0 0x04 /* bus error syndrome reg set a */ -#define SDRAM0_BESR1 0x08 /* bus error syndrome reg b */ -#define SDRAM0_BESRS1 0x0c /* bus error syndrome reg set b */ -#define SDRAM0_BEAR 0x10 /* bus error address reg */ -#endif -#define SDRAM0_CFG 0x20 /* memory controller options 1 */ -#define SDRAM0_STATUS 0x24 /* memory status */ -#define SDRAM0_RTR 0x30 /* refresh timer reg */ -#define SDRAM0_PMIT 0x34 /* power management idle timer */ -#define SDRAM0_B0CR 0x40 /* memory bank 0 configuration */ -#define SDRAM0_B1CR 0x44 /* memory bank 1 configuration */ -#ifndef CONFIG_405EP -#define SDRAM0_B2CR 0x48 /* memory bank 2 configuration */ -#define SDRAM0_B3CR 0x4c /* memory bank 3 configuration */ -#endif -#define SDRAM0_TR 0x80 /* timing reg 1 */ -#ifndef CONFIG_405EP -#define SDRAM0_ECCCFG 0x94 /* ECC configuration */ -#define SDRAM0_ECCESR 0x98 /* ECC error status */ -#endif - -#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */ - -#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) - -/* - * Memory controller registers - */ -#define SDRAM_CFG0 0x20 /* memory controller options 0 */ -#define SDRAM_CFG1 0x21 /* memory controller options 1 */ - -#define SDRAM0_BEAR 0x0010 /* bus error address reg */ -#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */ -#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */ -#define SDRAM0_CFG1 0x0021 /* ddr sdram options 1 */ -#define SDRAM0_DEVOPT 0x0022 /* ddr sdram device options */ -#define SDRAM0_MCSTS 0x0024 /* memory controller status */ -#define SDRAM0_RTR 0x0030 /* refresh timer register */ -#define SDRAM0_PMIT 0x0034 /* power management idle timer */ -#define SDRAM0_UABBA 0x0038 /* plb UABus base address */ -#define SDRAM0_B0CR 0x0040 /* ddr sdram bank 0 configuration */ -#define SDRAM0_B1CR 0x0044 /* ddr sdram bank 1 configuration */ -#define SDRAM0_B2CR 0x0048 /* ddr sdram bank 2 configuration */ -#define SDRAM0_B3CR 0x004c /* ddr sdram bank 3 configuration */ -#define SDRAM0_TR0 0x0080 /* sdram timing register 0 */ -#define SDRAM0_TR1 0x0081 /* sdram timing register 1 */ -#define SDRAM0_CLKTR 0x0082 /* ddr clock timing register */ -#define SDRAM0_WDDCTR 0x0083 /* write data/dm/dqs clock timing reg */ -#define SDRAM0_DLYCAL 0x0084 /* delay line calibration register */ -#define SDRAM0_ECCESR 0x0098 /* ECC error status */ - -/* - * Memory Controller Options 0 - */ -#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ -#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ -#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ -#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ -#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ -#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ -#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ -#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ -#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ -#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ -#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ -#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ - -/* - * Memory Controller Options 1 - */ -#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ -#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ - -/* - * SDRAM DEVPOT Options - */ -#define SDRAM_DEVOPT_DLL 0x80000000 -#define SDRAM_DEVOPT_DS 0x40000000 - -/* - * SDRAM MCSTS Options - */ -#define SDRAM_MCSTS_MRSC 0x80000000 -#define SDRAM_MCSTS_SRMS 0x40000000 -#define SDRAM_MCSTS_CIS 0x20000000 -#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */ - -/* - * SDRAM Refresh Timer Register - */ -#define SDRAM_RTR_RINT_MASK 0xFFFF0000 -#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) - -/* - * SDRAM UABus Base Address Reg - */ -#define SDRAM_UABBA_UBBA_MASK 0x0000000F - -/* - * Memory Bank 0-7 configuration - */ -#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ -#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ -#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ -#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ -#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ -#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ -#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ -#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ -#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ -#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ -#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ -#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ -#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ -#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ -#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ - -/* - * SDRAM TR0 Options - */ -#define SDRAM_TR0_SDWR_MASK 0x80000000 -#define SDRAM_TR0_SDWR_2_CLK 0x00000000 -#define SDRAM_TR0_SDWR_3_CLK 0x80000000 -#define SDRAM_TR0_SDWD_MASK 0x40000000 -#define SDRAM_TR0_SDWD_0_CLK 0x00000000 -#define SDRAM_TR0_SDWD_1_CLK 0x40000000 -#define SDRAM_TR0_SDCL_MASK 0x01800000 -#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 -#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 -#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 -#define SDRAM_TR0_SDPA_MASK 0x000C0000 -#define SDRAM_TR0_SDPA_2_CLK 0x00040000 -#define SDRAM_TR0_SDPA_3_CLK 0x00080000 -#define SDRAM_TR0_SDPA_4_CLK 0x000C0000 -#define SDRAM_TR0_SDCP_MASK 0x00030000 -#define SDRAM_TR0_SDCP_2_CLK 0x00000000 -#define SDRAM_TR0_SDCP_3_CLK 0x00010000 -#define SDRAM_TR0_SDCP_4_CLK 0x00020000 -#define SDRAM_TR0_SDCP_5_CLK 0x00030000 -#define SDRAM_TR0_SDLD_MASK 0x0000C000 -#define SDRAM_TR0_SDLD_1_CLK 0x00000000 -#define SDRAM_TR0_SDLD_2_CLK 0x00004000 -#define SDRAM_TR0_SDRA_MASK 0x0000001C -#define SDRAM_TR0_SDRA_6_CLK 0x00000000 -#define SDRAM_TR0_SDRA_7_CLK 0x00000004 -#define SDRAM_TR0_SDRA_8_CLK 0x00000008 -#define SDRAM_TR0_SDRA_9_CLK 0x0000000C -#define SDRAM_TR0_SDRA_10_CLK 0x00000010 -#define SDRAM_TR0_SDRA_11_CLK 0x00000014 -#define SDRAM_TR0_SDRA_12_CLK 0x00000018 -#define SDRAM_TR0_SDRA_13_CLK 0x0000001C -#define SDRAM_TR0_SDRD_MASK 0x00000003 -#define SDRAM_TR0_SDRD_2_CLK 0x00000001 -#define SDRAM_TR0_SDRD_3_CLK 0x00000002 -#define SDRAM_TR0_SDRD_4_CLK 0x00000003 - -/* - * SDRAM TR1 Options - */ -#define SDRAM_TR1_RDSS_MASK 0xC0000000 -#define SDRAM_TR1_RDSS_TR0 0x00000000 -#define SDRAM_TR1_RDSS_TR1 0x40000000 -#define SDRAM_TR1_RDSS_TR2 0x80000000 -#define SDRAM_TR1_RDSS_TR3 0xC0000000 -#define SDRAM_TR1_RDSL_MASK 0x00C00000 -#define SDRAM_TR1_RDSL_STAGE1 0x00000000 -#define SDRAM_TR1_RDSL_STAGE2 0x00400000 -#define SDRAM_TR1_RDSL_STAGE3 0x00800000 -#define SDRAM_TR1_RDCD_MASK 0x00000800 -#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 -#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 -#define SDRAM_TR1_RDCT_MASK 0x000001FF -#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) -#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) -#define SDRAM_TR1_RDCT_MIN 0x00000000 -#define SDRAM_TR1_RDCT_MAX 0x000001FF - -/* - * SDRAM WDDCTR Options - */ -#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 -#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 -#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 -#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 -#define SDRAM_WDDCTR_DCD_MASK 0x000001FF - -/* - * SDRAM CLKTR Options - */ -#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 -#define SDRAM_CLKTR_CLKP_0DEG 0x00000000 -#define SDRAM_CLKTR_CLKP_90DEG 0x40000000 -#define SDRAM_CLKTR_CLKP_180DEG 0x80000000 -#define SDRAM_CLKTR_DCDT_MASK 0x000001FF - -/* - * SDRAM DLYCAL Options - */ -#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC -#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) -#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) - -#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */ - -#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) - -#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC -#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) -#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) - -#if !defined(CONFIG_405EX) -/* - * Memory queue defines - */ -#define SDRAMQ_DCR_BASE 0x040 - -#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ -#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ -#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ -#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ -#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ -#define SDRAM_CONF1HB_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */ -#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ -#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ -#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ -#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ -#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ -#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ -#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */ -#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */ - -#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ -#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ -#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ -#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ -#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ -#define SDRAM_CONF1LL_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */ -#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ -#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ -#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ -#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ -#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ -#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ -#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */ - -#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ -#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ -#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ -#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ -#define SDRAM_CONFPATHB_TPEN 0x08000000 /* Transaction Passing Enable - Bit 4 */ - -#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ - -/* - * Memory Bank 0-7 configuration - */ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) -#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ -#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) -#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) -#endif /* CONFIG_440SPE */ -#if defined(CONFIG_440SP) -#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ -#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFF800000)) -#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFF800000)) -#endif /* CONFIG_440SP */ -#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */ -#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((u32)(n))&0x3FF)<<6) -#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((u32)(n))>>6)&0x3FF) -#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */ -#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */ -#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */ -#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */ -#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */ -#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */ -#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */ -#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */ -#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */ -#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */ -#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */ -#else /* CONFIG_405EX */ -/* - * XXX - ToDo: - * Revisit this file to check if all these 405EX defines are correct and - * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02 - */ -#define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF) -#define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0) -#define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1) -#define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2) -#define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3) -#define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4) -#define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5) -#define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6) -#define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7) -#define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8) -#define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9) -#define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA) -#define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB) -#define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB -#define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB -#define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB -#define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB -#define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB -#define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB -#define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB -#define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB -#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB -#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB -#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB -#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0) -#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1) -#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2) -#define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3) -#define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4) -#define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5) -#define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6) -#define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7) -#define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8) -#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9) -#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0) -#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1) -#endif /* CONFIG_405EX */ - -/* - * Memory controller registers - */ -#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ -#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ -#define SDRAM_BEARL 0x02 /* PLB bus error address low */ -#define SDRAM_BEARH 0x03 /* PLB bus error address high */ -#define SDRAM_WMIRQ 0x06 /* PLB write master interrupt (read/clear) */ -#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */ -#define SDRAM_PLBOPT 0x08 /* PLB slave options */ -#define SDRAM_PUABA 0x09 /* PLB upper address base */ -#ifndef CONFIG_405EX -#define SDRAM_MCSTAT 0x14 /* memory controller status */ -#else -#define SDRAM_MCSTAT 0x1F /* memory controller status */ -#endif -#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ -#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ -#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ -#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ -#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ -#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ -#define SDRAM_CODT 0x26 /* on die termination for controller */ -#define SDRAM_VVPR 0x27 /* variable VRef programmming */ -#define SDRAM_OPARS 0x28 /* on chip driver control setup */ -#define SDRAM_OPART 0x29 /* on chip driver control trigger */ -#define SDRAM_RTR 0x30 /* refresh timer */ -#define SDRAM_PMIT 0x34 /* power management idle timer */ -#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ -#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ -#define SDRAM_MB2CF 0x48 -#define SDRAM_MB3CF 0x4C -#define SDRAM_INITPLR0 0x50 /* manual initialization control */ -#define SDRAM_INITPLR1 0x51 /* manual initialization control */ -#define SDRAM_INITPLR2 0x52 /* manual initialization control */ -#define SDRAM_INITPLR3 0x53 /* manual initialization control */ -#define SDRAM_INITPLR4 0x54 /* manual initialization control */ -#define SDRAM_INITPLR5 0x55 /* manual initialization control */ -#define SDRAM_INITPLR6 0x56 /* manual initialization control */ -#define SDRAM_INITPLR7 0x57 /* manual initialization control */ -#define SDRAM_INITPLR8 0x58 /* manual initialization control */ -#define SDRAM_INITPLR9 0x59 /* manual initialization control */ -#define SDRAM_INITPLR10 0x5a /* manual initialization control */ -#define SDRAM_INITPLR11 0x5b /* manual initialization control */ -#define SDRAM_INITPLR12 0x5c /* manual initialization control */ -#define SDRAM_INITPLR13 0x5d /* manual initialization control */ -#define SDRAM_INITPLR14 0x5e /* manual initialization control */ -#define SDRAM_INITPLR15 0x5f /* manual initialization control */ -#define SDRAM_RQDC 0x70 /* read DQS delay control */ -#define SDRAM_RFDC 0x74 /* read feedback delay control */ -#define SDRAM_RDCC 0x78 /* read data capture control */ -#define SDRAM_DLCR 0x7A /* delay line calibration */ -#define SDRAM_CLKTR 0x80 /* DDR clock timing */ -#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ -#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ -#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ -#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ -#define SDRAM_MMODE 0x88 /* memory mode */ -#define SDRAM_MEMODE 0x89 /* memory extended mode */ -#define SDRAM_ECCES 0x98 /* ECC error status */ -#define SDRAM_CID 0xA4 /* core ID */ -#ifndef CONFIG_405EX -#define SDRAM_RID 0xA8 /* revision ID */ -#endif -#define SDRAM_FCSR 0xB0 /* feedback calibration status */ -#define SDRAM_RTSR 0xB1 /* run time status tracking */ -#ifdef CONFIG_405EX -#define SDRAM_RID 0xF8 /* revision ID */ -#endif - -/* - * Memory Controller Bus Error Status - */ -#define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF) -#define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF) -#define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, 0x0) -#define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, 0x1) -#define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, 0x2) -#define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, 0x3) -#define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, 0x4) -#define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, 0x5) -#define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, 0x6) -#define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, 0x7) -#define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7) -#define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0x0) -#define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 0x1) -#define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0) -#define SDRAM_BESR_M0RW_READ PPC_REG_VAL(8, 1) - -/* - * Memory Controller Status - */ -#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ -#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ -#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ -#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */ -#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ -#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */ -#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */ -#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */ -#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */ - -/* - * Memory Controller Options 1 - */ -#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/ -#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ -#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ -#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ -#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ -#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((u32)(n))>>28)&0x3) -#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ -#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ -#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ -#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ -#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ -#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ -#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ -#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ -#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ -#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ -#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ -#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ -#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ -#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ -#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ -#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ -#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ -#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ -#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ -#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ -#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ -#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ -#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ -#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ -#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ -#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ -#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ -#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ -#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ - -/* - * Memory Controller Options 2 - */ -#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ -#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ -#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ -#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ -#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ -#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ -#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ -#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ -#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ -#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ -#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ -#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ -#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ -#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ -#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ -#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ - -/* - * SDRAM Refresh Timer Register - */ -#define SDRAM_RTR_RINT_MASK 0xFFF80000 -#define SDRAM_RTR_RINT_ENCODE(n) ((((u32)(n))&0xFFF8)<<16) -#define SDRAM_RTR_RINT_DECODE(n) ((((u32)(n))>>16)&0xFFF8) - -/* - * SDRAM Read DQS Delay Control Register - */ -#define SDRAM_RQDC_RQDE_MASK 0x80000000 -#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 -#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 -#define SDRAM_RQDC_RQFD_MASK 0x000001FF -#define SDRAM_RQDC_RQFD_ENCODE(n) ((((u32)(n))&0x1FF)<<0) - -#define SDRAM_RQDC_RQFD_MAX 0x1FF - -/* - * SDRAM Read Data Capture Control Register - */ -#define SDRAM_RDCC_RDSS_MASK 0xC0000000 -#define SDRAM_RDCC_RDSS_T1 0x00000000 -#define SDRAM_RDCC_RDSS_T2 0x40000000 -#define SDRAM_RDCC_RDSS_T3 0x80000000 -#define SDRAM_RDCC_RDSS_T4 0xC0000000 -#define SDRAM_RDCC_RSAE_MASK 0x00000001 -#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 -#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 -#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30) -#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03) - -/* - * SDRAM Read Feedback Delay Control Register - */ -#define SDRAM_RFDC_ARSE_MASK 0x80000000 -#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 -#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 -#define SDRAM_RFDC_RFOS_MASK 0x007F0000 -#define SDRAM_RFDC_RFOS_ENCODE(n) ((((u32)(n))&0x7F)<<16) -#define SDRAM_RFDC_RFFD_MASK 0x000007FF -#define SDRAM_RFDC_RFFD_ENCODE(n) ((((u32)(n))&0x7FF)<<0) - -#define SDRAM_RFDC_RFFD_MAX 0x7FF - -/* - * SDRAM Delay Line Calibration Register - */ -#define SDRAM_DLCR_DCLM_MASK 0x80000000 -#define SDRAM_DLCR_DCLM_MANUAL 0x80000000 -#define SDRAM_DLCR_DCLM_AUTO 0x00000000 -#define SDRAM_DLCR_DLCR_MASK 0x08000000 -#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 -#define SDRAM_DLCR_DLCR_IDLE 0x00000000 -#define SDRAM_DLCR_DLCS_MASK 0x07000000 -#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 -#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 -#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 -#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 -#define SDRAM_DLCR_DLCS_ERROR 0x04000000 -#define SDRAM_DLCR_DLCV_MASK 0x000001FF -#define SDRAM_DLCR_DLCV_ENCODE(n) ((((u32)(n))&0x1FF)<<0) -#define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF) - -/* - * SDRAM Memory On Die Terimination Control Register - */ -#define SDRAM_MODT_ODTON_DISABLE PPC_REG_VAL(0, 0) -#define SDRAM_MODT_ODTON_ENABLE PPC_REG_VAL(0, 1) -#define SDRAM_MODT_EB1W_DISABLE PPC_REG_VAL(1, 0) -#define SDRAM_MODT_EB1W_ENABLE PPC_REG_VAL(1, 1) -#define SDRAM_MODT_EB1R_DISABLE PPC_REG_VAL(2, 0) -#define SDRAM_MODT_EB1R_ENABLE PPC_REG_VAL(2, 1) -#define SDRAM_MODT_EB0W_DISABLE PPC_REG_VAL(7, 0) -#define SDRAM_MODT_EB0W_ENABLE PPC_REG_VAL(7, 1) -#define SDRAM_MODT_EB0R_DISABLE PPC_REG_VAL(8, 0) -#define SDRAM_MODT_EB0R_ENABLE PPC_REG_VAL(8, 1) - -/* - * SDRAM Controller On Die Termination Register - */ -#define SDRAM_CODT_ODT_ON PPC_REG_VAL(0, 1) -#define SDRAM_CODT_ODT_OFF PPC_REG_VAL(0, 0) -#define SDRAM_CODT_RK1W_ON PPC_REG_VAL(1, 1) -#define SDRAM_CODT_RK1W_OFF PPC_REG_VAL(1, 0) -#define SDRAM_CODT_RK1R_ON PPC_REG_VAL(2, 1) -#define SDRAM_CODT_RK1R_OFF PPC_REG_VAL(2, 0) -#define SDRAM_CODT_RK0W_ON PPC_REG_VAL(7, 1) -#define SDRAM_CODT_RK0W_OFF PPC_REG_VAL(7, 0) -#define SDRAM_CODT_RK0R_ON PPC_REG_VAL(8, 1) -#define SDRAM_CODT_RK0R_OFF PPC_REG_VAL(8, 0) -#define SDRAM_CODT_ODTSH_NORMAL PPC_REG_VAL(10, 0) -#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END PPC_REG_VAL(10, 1) -#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START PPC_REG_VAL(10, 2) -#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER PPC_REG_VAL(10, 3) -#define SDRAM_CODT_CODTZ_75OHM PPC_REG_VAL(11, 0) -#define SDRAM_CODT_CKEG_ON PPC_REG_VAL(12, 1) -#define SDRAM_CODT_CKEG_OFF PPC_REG_VAL(12, 0) -#define SDRAM_CODT_CTLG_ON PPC_REG_VAL(13, 1) -#define SDRAM_CODT_CTLG_OFF PPC_REG_VAL(13, 0) -#define SDRAM_CODT_FBDG_ON PPC_REG_VAL(14, 1) -#define SDRAM_CODT_FBDG_OFF PPC_REG_VAL(14, 0) -#define SDRAM_CODT_FBRG_ON PPC_REG_VAL(15, 1) -#define SDRAM_CODT_FBRG_OFF PPC_REG_VAL(15, 0) -#define SDRAM_CODT_CKLZ_36OHM PPC_REG_VAL(18, 1) -#define SDRAM_CODT_CKLZ_18OHM PPC_REG_VAL(18, 0) -#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK PPC_REG_VAL(26, 1) -#define SDRAM_CODT_DQS_2_5_V_DDR1 PPC_REG_VAL(26, 0) -#define SDRAM_CODT_DQS_1_8_V_DDR2 PPC_REG_VAL(26, 1) -#define SDRAM_CODT_DQS_MASK PPC_REG_VAL(27, 1) -#define SDRAM_CODT_DQS_DIFFERENTIAL PPC_REG_VAL(27, 0) -#define SDRAM_CODT_DQS_SINGLE_END PPC_REG_VAL(27, 1) -#define SDRAM_CODT_CKSE_DIFFERENTIAL PPC_REG_VAL(28, 0) -#define SDRAM_CODT_CKSE_SINGLE_END PPC_REG_VAL(28, 1) -#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END PPC_REG_VAL(29, 1) -#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END PPC_REG_VAL(30, 1) -#define SDRAM_CODT_IO_HIZ PPC_REG_VAL(31, 0) -#define SDRAM_CODT_IO_NMODE PPC_REG_VAL(31, 1) - -/* - * SDRAM Initialization Preload Register - */ -#define SDRAM_INITPLR_ENABLE PPC_REG_VAL(0, 1) -#define SDRAM_INITPLR_DISABLE PPC_REG_VAL(0, 0) -#define SDRAM_INITPLR_IMWT_MASK PPC_REG_VAL(8, 0xFF) -#define SDRAM_INITPLR_IMWT_ENCODE(n) PPC_REG_VAL(8, \ - (static_cast(u32, \ - n)) \ - & 0xFF) -#define SDRAM_INITPLR_ICMD_MASK PPC_REG_VAL(12, 0x7) -#define SDRAM_INITPLR_ICMD_ENCODE(n) PPC_REG_VAL(12, \ - (static_cast(u32, \ - n)) \ - & 0x7) -#define SDRAM_INITPLR_IBA_MASK PPC_REG_VAL(15, 0x7) -#define SDRAM_INITPLR_IBA_ENCODE(n) PPC_REG_VAL(15, \ - (static_cast(u32, \ - n)) \ - & 0x7) -#define SDRAM_INITPLR_IMA_MASK PPC_REG_VAL(31, 0x7FFF) -#define SDRAM_INITPLR_IMA_ENCODE(n) PPC_REG_VAL(31, \ - (static_cast(u32, \ - n)) \ - & 0x7FFF) - -/* - * JEDEC DDR Initialization Commands - */ -#define JEDEC_CMD_NOP 7 -#define JEDEC_CMD_PRECHARGE 2 -#define JEDEC_CMD_REFRESH 1 -#define JEDEC_CMD_EMR 0 -#define JEDEC_CMD_READ 5 -#define JEDEC_CMD_WRITE 4 - -/* - * JEDEC Precharge Command Memory Address Arguments - */ -#define JEDEC_MA_PRECHARGE_ONE (0 << 10) -#define JEDEC_MA_PRECHARGE_ALL (1 << 10) - -/* - * JEDEC DDR EMR Command Bank Address Arguments - */ -#define JEDEC_BA_MR 0 -#define JEDEC_BA_EMR 1 -#define JEDEC_BA_EMR2 2 -#define JEDEC_BA_EMR3 3 - -/* - * JEDEC DDR Mode Register - */ -#define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12) -#define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12) -#define JEDEC_MA_MR_WR_MASK (0x7 << 9) -#define JEDEC_MA_MR_WR_DDR1 (0x0 << 9) -#define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9) -#define JEDEC_MA_MR_WR_DDR2_3_CYC (0x2 << 9) -#define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9) -#define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9) -#define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9) -#define JEDEC_MA_MR_DLL_RESET (1 << 8) -#define JEDEC_MA_MR_MODE_NORMAL (0 << 8) -#define JEDEC_MA_MR_MODE_TEST (1 << 8) -#define JEDEC_MA_MR_CL_MASK (0x7 << 4) -#define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4) -#define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4) -#define JEDEC_MA_MR_CL_DDR1_3_0_CLK (0x3 << 4) -#define JEDEC_MA_MR_CL_DDR2_2_0_CLK (0x2 << 4) -#define JEDEC_MA_MR_CL_DDR2_3_0_CLK (0x3 << 4) -#define JEDEC_MA_MR_CL_DDR2_4_0_CLK (0x4 << 4) -#define JEDEC_MA_MR_CL_DDR2_5_0_CLK (0x5 << 4) -#define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4) -#define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4) -#define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3) -#define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3) -#define JEDEC_MA_MR_BLEN_MASK (0x7 << 0) -#define JEDEC_MA_MR_BLEN_4 (2 << 0) -#define JEDEC_MA_MR_BLEN_8 (3 << 0) - -/* - * JEDEC DDR Extended Mode Register - */ -#define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12) -#define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12) -#define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12) -#define JEDEC_MA_EMR_RQDS_MASK (1 << 11) -#define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11) -#define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11) -#define JEDEC_MA_EMR_DQS_MASK (1 << 10) -#define JEDEC_MA_EMR_DQS_DISABLE (1 << 10) -#define JEDEC_MA_EMR_DQS_ENABLE (0 << 10) -#define JEDEC_MA_EMR_OCD_MASK (0x7 << 7) -#define JEDEC_MA_EMR_OCD_EXIT (0 << 7) -#define JEDEC_MA_EMR_OCD_ENTER (7 << 7) -#define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3) -#define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3) -#define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3) -#define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3) -#define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3) -#define JEDEC_MA_EMR_RTT_MASK (0x11 << 2) -#define JEDEC_MA_EMR_RTT_DISABLED (0x00 << 2) -#define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2) -#define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2) -#define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2) -#define JEDEC_MA_EMR_ODS_MASK (1 << 1) -#define JEDEC_MA_EMR_ODS_NORMAL (0 << 1) -#define JEDEC_MA_EMR_ODS_WEAK (1 << 1) -#define JEDEC_MA_EMR_DLL_MASK (1 << 0) -#define JEDEC_MA_EMR_DLL_ENABLE (0 << 0) -#define JEDEC_MA_EMR_DLL_DISABLE (1 << 0) - -/* - * JEDEC DDR Extended Mode Register 2 - */ -#define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7) -#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7) - -/* - * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register) - */ -#define SDRAM_MMODE_WR_MASK JEDEC_MA_MR_WR_MASK -#define SDRAM_MMODE_WR_DDR1 JEDEC_MA_MR_WR_DDR1 -#define SDRAM_MMODE_WR_DDR2_2_CYC JEDEC_MA_MR_WR_DDR2_2_CYC -#define SDRAM_MMODE_WR_DDR2_3_CYC JEDEC_MA_MR_WR_DDR2_3_CYC -#define SDRAM_MMODE_WR_DDR2_4_CYC JEDEC_MA_MR_WR_DDR2_4_CYC -#define SDRAM_MMODE_WR_DDR2_5_CYC JEDEC_MA_MR_WR_DDR2_5_CYC -#define SDRAM_MMODE_WR_DDR2_6_CYC JEDEC_MA_MR_WR_DDR2_6_CYC -#define SDRAM_MMODE_DCL_MASK JEDEC_MA_MR_CL_MASK -#define SDRAM_MMODE_DCL_DDR1_2_0_CLK JEDEC_MA_MR_CL_DDR1_2_0_CLK -#define SDRAM_MMODE_DCL_DDR1_2_5_CLK JEDEC_MA_MR_CL_DDR1_2_5_CLK -#define SDRAM_MMODE_DCL_DDR1_3_0_CLK JEDEC_MA_MR_CL_DDR1_3_0_CLK -#define SDRAM_MMODE_DCL_DDR2_2_0_CLK JEDEC_MA_MR_CL_DDR2_2_0_CLK -#define SDRAM_MMODE_DCL_DDR2_3_0_CLK JEDEC_MA_MR_CL_DDR2_3_0_CLK -#define SDRAM_MMODE_DCL_DDR2_4_0_CLK JEDEC_MA_MR_CL_DDR2_4_0_CLK -#define SDRAM_MMODE_DCL_DDR2_5_0_CLK JEDEC_MA_MR_CL_DDR2_5_0_CLK -#define SDRAM_MMODE_DCL_DDR2_6_0_CLK JEDEC_MA_MR_CL_DDR2_6_0_CLK -#define SDRAM_MMODE_DCL_DDR2_7_0_CLK JEDEC_MA_MR_CL_DDR2_7_0_CLK -#define SDRAM_MMODE_BTYP_SEQUENTIAL JEDEC_MA_MR_BTYP_SEQUENTIAL -#define SDRAM_MMODE_BTYP_INTERLEAVED JEDEC_MA_MR_BTYP_INTERLEAVED -#define SDRAM_MMODE_BLEN_MASK JEDEC_MA_MR_BLEN_MASK -#define SDRAM_MMODE_BLEN_4 JEDEC_MA_MR_BLEN_4 -#define SDRAM_MMODE_BLEN_8 JEDEC_MA_MR_BLEN_8 - -/* - * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended - * Mode Register) - */ -#define SDRAM_MEMODE_QOFF_MASK JEDEC_MA_EMR_OUTPUT_MASK -#define SDRAM_MEMODE_QOFF_DISABLE JEDEC_MA_EMR_OUTPUT_DISABLE -#define SDRAM_MEMODE_QOFF_ENABLE JEDEC_MA_EMR_OUTPUT_ENABLE -#define SDRAM_MEMODE_RDQS_MASK JEDEC_MA_EMR_RQDS_MASK -#define SDRAM_MEMODE_RDQS_DISABLE JEDEC_MA_EMR_RDQS_DISABLE -#define SDRAM_MEMODE_RDQS_ENABLE JEDEC_MA_EMR_RDQS_ENABLE -#define SDRAM_MEMODE_DQS_MASK JEDEC_MA_EMR_DQS_MASK -#define SDRAM_MEMODE_DQS_DISABLE JEDEC_MA_EMR_DQS_DISABLE -#define SDRAM_MEMODE_DQS_ENABLE JEDEC_MA_EMR_DQS_ENABLE -#define SDRAM_MEMODE_AL_DDR1_0_CYC JEDEC_MA_EMR_AL_DDR1_0_CYC -#define SDRAM_MEMODE_AL_DDR2_1_CYC JEDEC_MA_EMR_AL_DDR2_1_CYC -#define SDRAM_MEMODE_AL_DDR2_2_CYC JEDEC_MA_EMR_AL_DDR2_2_CYC -#define SDRAM_MEMODE_AL_DDR2_3_CYC JEDEC_MA_EMR_AL_DDR2_3_CYC -#define SDRAM_MEMODE_AL_DDR2_4_CYC JEDEC_MA_EMR_AL_DDR2_4_CYC -#define SDRAM_MEMODE_RTT_MASK JEDEC_MA_EMR_RTT_MASK -#define SDRAM_MEMODE_RTT_DISABLED JEDEC_MA_EMR_RTT_DISABLED -#define SDRAM_MEMODE_RTT_75OHM JEDEC_MA_EMR_RTT_75OHM -#define SDRAM_MEMODE_RTT_150OHM JEDEC_MA_EMR_RTT_150OHM -#define SDRAM_MEMODE_RTT_50OHM JEDEC_MA_EMR_RTT_50OHM -#define SDRAM_MEMODE_DIC_MASK JEDEC_MA_EMR_ODS_MASK -#define SDRAM_MEMODE_DIC_NORMAL JEDEC_MA_EMR_ODS_NORMAL -#define SDRAM_MEMODE_DIC_WEAK JEDEC_MA_EMR_ODS_WEAK -#define SDRAM_MEMODE_DLL_MASK JEDEC_MA_EMR_DLL_MASK -#define SDRAM_MEMODE_DLL_DISABLE JEDEC_MA_EMR_DLL_DISABLE -#define SDRAM_MEMODE_DLL_ENABLE JEDEC_MA_EMR_DLL_ENABLE - -/* - * SDRAM Clock Timing Register - */ -#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 -#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 -#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 -#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000 -#define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000 - -/* - * SDRAM Write Timing Register - */ -#define SDRAM_WRDTR_LLWP_MASK 0x10000000 -#define SDRAM_WRDTR_LLWP_DIS 0x10000000 -#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 -#define SDRAM_WRDTR_WTR_MASK 0x0E000000 -#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 -#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000 -#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 -#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 - -/* - * SDRAM SDTR1 Options - */ -#define SDRAM_SDTR1_LDOF_MASK 0x80000000 -#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 -#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 -#define SDRAM_SDTR1_RTW_MASK 0x00F00000 -#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 -#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 -#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 -#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 -#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 -#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 -#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000 -#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 - -/* - * SDRAM SDTR2 Options - */ -#define SDRAM_SDTR2_RCD_MASK 0xF0000000 -#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 -#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 -#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 -#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 -#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 -#define SDRAM_SDTR2_WTR_MASK 0x0F000000 -#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 -#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 -#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 -#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 -#define SDRAM_SDTR3_WTR_ENCODE(n) ((((u32)(n))&0xF)<<24) -#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 -#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 -#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 -#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 -#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 -#define SDRAM_SDTR2_WPC_MASK 0x0000F000 -#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 -#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 -#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 -#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 -#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 -#define SDRAM_SDTR3_WPC_ENCODE(n) ((((u32)(n))&0xF)<<12) -#define SDRAM_SDTR2_RPC_MASK 0x00000F00 -#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 -#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 -#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 -#define SDRAM_SDTR2_RP_MASK 0x000000F0 -#define SDRAM_SDTR2_RP_3_CLK 0x00000030 -#define SDRAM_SDTR2_RP_4_CLK 0x00000040 -#define SDRAM_SDTR2_RP_5_CLK 0x00000050 -#define SDRAM_SDTR2_RP_6_CLK 0x00000060 -#define SDRAM_SDTR2_RP_7_CLK 0x00000070 -#define SDRAM_SDTR2_RRD_MASK 0x0000000F -#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 -#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 - -/* - * SDRAM SDTR3 Options - */ -#define SDRAM_SDTR3_RAS_MASK 0x1F000000 -#define SDRAM_SDTR3_RAS_ENCODE(n) ((((u32)(n))&0x1F)<<24) -#define SDRAM_SDTR3_RC_MASK 0x001F0000 -#define SDRAM_SDTR3_RC_ENCODE(n) ((((u32)(n))&0x1F)<<16) -#define SDRAM_SDTR3_XCS_MASK 0x00001F00 -#define SDRAM_SDTR3_XCS 0x00000D00 -#define SDRAM_SDTR3_RFC_MASK 0x0000003F -#define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0) - -/* - * ECC Error Status - */ -#define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF) -#define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF) -#define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1) -#define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3) -#define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0) -#define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2) -#define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1) -#define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2) -#define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3) -#define SDRAM_ECCES_CE PPC_REG_VAL(18, 1) -#define SDRAM_ECCES_UE PPC_REG_VAL(19, 1) -#define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3) -#define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1) -#define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1) - -/* - * Memory Bank 0-1 configuration - */ -#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ -#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ -#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ -#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ -#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ -#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ -#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ -#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ -#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ -#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ -#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ -#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ -#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ -#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ - -#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/ -#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */ -#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */ -#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */ -#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */ - -#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ - -#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */ - -#if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2) -/* - * SDRAM Controller - */ -#define DDR0_00 0x00 -#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ -#define DDR0_00_INT_ACK_ALL 0x7F000000 -#define DDR0_00_INT_ACK_ENCODE(n) ((((u32)(n))&0x7F)<<24) -#define DDR0_00_INT_ACK_DECODE(n) ((((u32)(n))>>24)&0x7F) -/* Status */ -#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ -/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT0 0x00010000 -/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ -#define DDR0_00_INT_STATUS_BIT1 0x00020000 -/* Bit2. Single correctable ECC event detected */ -#define DDR0_00_INT_STATUS_BIT2 0x00040000 -/* Bit3. Multiple correctable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT3 0x00080000 -/* Bit4. Single uncorrectable ECC event detected. */ -#define DDR0_00_INT_STATUS_BIT4 0x00100000 -/* Bit5. Multiple uncorrectable ECC events detected. */ -#define DDR0_00_INT_STATUS_BIT5 0x00200000 -/* Bit6. DRAM initialization complete. */ -#define DDR0_00_INT_STATUS_BIT6 0x00400000 -/* Bit7. Logical OR of all lower bits. */ -#define DDR0_00_INT_STATUS_BIT7 0x00800000 - -#define DDR0_00_INT_STATUS_ENCODE(n) ((((u32)(n))&0xFF)<<16) -#define DDR0_00_INT_STATUS_DECODE(n) ((((u32)(n))>>16)&0xFF) -#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 -#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((u32)(n))&0x7F)<<8) -#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((u32)(n))>>8)&0x7F) -#define DDR0_00_DLL_START_POINT_MASK 0x0000007F -#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0) -#define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F) - -#define DDR0_01 0x01 -#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 -#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24) -#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F) -#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 -#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16) -#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F) -#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ -#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8) -#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7) -#define DDR0_01_INT_MASK_MASK 0x000000FF -#define DDR0_01_INT_MASK_ENCODE(n) ((((u32)(n))&0xFF)<<0) -#define DDR0_01_INT_MASK_DECODE(n) ((((u32)(n))>>0)&0xFF) -#define DDR0_01_INT_MASK_ALL_ON 0x000000FF -#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 - -#define DDR0_02 0x02 -#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ -#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((u32)(n))&0x2)<<24) -#define DDR0_02_MAX_CS_REG_DECODE(n) ((((u32)(n))>>24)&0x2) -#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ -#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((u32)(n))&0xF)<<16) -#define DDR0_02_MAX_COL_REG_DECODE(n) ((((u32)(n))>>16)&0xF) -#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ -#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((u32)(n))&0xF)<<8) -#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((u32)(n))>>8)&0xF) -#define DDR0_02_START_MASK 0x00000001 -#define DDR0_02_START_ENCODE(n) ((((u32)(n))&0x1)<<0) -#define DDR0_02_START_DECODE(n) ((((u32)(n))>>0)&0x1) -#define DDR0_02_START_OFF 0x00000000 -#define DDR0_02_START_ON 0x00000001 - -#define DDR0_03 0x03 -#define DDR0_03_BSTLEN_MASK 0x07000000 -#define DDR0_03_BSTLEN_ENCODE(n) ((((u32)(n))&0x7)<<24) -#define DDR0_03_BSTLEN_DECODE(n) ((((u32)(n))>>24)&0x7) -#define DDR0_03_CASLAT_MASK 0x00070000 -#define DDR0_03_CASLAT_ENCODE(n) ((((u32)(n))&0x7)<<16) -#define DDR0_03_CASLAT_DECODE(n) ((((u32)(n))>>16)&0x7) -#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 -#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((u32)(n))&0xF)<<8) -#define DDR0_03_CASLAT_LIN_DECODE(n) ((((u32)(n))>>8)&0xF) -#define DDR0_03_INITAREF_MASK 0x0000000F -#define DDR0_03_INITAREF_ENCODE(n) ((((u32)(n))&0xF)<<0) -#define DDR0_03_INITAREF_DECODE(n) ((((u32)(n))>>0)&0xF) - -#define DDR0_04 0x04 -#define DDR0_04_TRC_MASK 0x1F000000 -#define DDR0_04_TRC_ENCODE(n) ((((u32)(n))&0x1F)<<24) -#define DDR0_04_TRC_DECODE(n) ((((u32)(n))>>24)&0x1F) -#define DDR0_04_TRRD_MASK 0x00070000 -#define DDR0_04_TRRD_ENCODE(n) ((((u32)(n))&0x7)<<16) -#define DDR0_04_TRRD_DECODE(n) ((((u32)(n))>>16)&0x7) -#define DDR0_04_TRTP_MASK 0x00000700 -#define DDR0_04_TRTP_ENCODE(n) ((((u32)(n))&0x7)<<8) -#define DDR0_04_TRTP_DECODE(n) ((((u32)(n))>>8)&0x7) - -#define DDR0_05 0x05 -#define DDR0_05_TMRD_MASK 0x1F000000 -#define DDR0_05_TMRD_ENCODE(n) ((((u32)(n))&0x1F)<<24) -#define DDR0_05_TMRD_DECODE(n) ((((u32)(n))>>24)&0x1F) -#define DDR0_05_TEMRS_MASK 0x00070000 -#define DDR0_05_TEMRS_ENCODE(n) ((((u32)(n))&0x7)<<16) -#define DDR0_05_TEMRS_DECODE(n) ((((u32)(n))>>16)&0x7) -#define DDR0_05_TRP_MASK 0x00000F00 -#define DDR0_05_TRP_ENCODE(n) ((((u32)(n))&0xF)<<8) -#define DDR0_05_TRP_DECODE(n) ((((u32)(n))>>8)&0xF) -#define DDR0_05_TRAS_MIN_MASK 0x000000FF -#define DDR0_05_TRAS_MIN_ENCODE(n) ((((u32)(n))&0xFF)<<0) -#define DDR0_05_TRAS_MIN_DECODE(n) ((((u32)(n))>>0)&0xFF) - -#define DDR0_06 0x06 -#define DDR0_06_WRITEINTERP_MASK 0x01000000 -#define DDR0_06_WRITEINTERP_ENCODE(n) ((((u32)(n))&0x1)<<24) -#define DDR0_06_WRITEINTERP_DECODE(n) ((((u32)(n))>>24)&0x1) -#define DDR0_06_TWTR_MASK 0x00070000 -#define DDR0_06_TWTR_ENCODE(n) ((((u32)(n))&0x7)<<16) -#define DDR0_06_TWTR_DECODE(n) ((((u32)(n))>>16)&0x7) -#define DDR0_06_TDLL_MASK 0x0000FF00 -#define DDR0_06_TDLL_ENCODE(n) ((((u32)(n))&0xFF)<<8) -#define DDR0_06_TDLL_DECODE(n) ((((u32)(n))>>8)&0xFF) -#define DDR0_06_TRFC_MASK 0x0000007F -#define DDR0_06_TRFC_ENCODE(n) ((((u32)(n))&0x7F)<<0) -#define DDR0_06_TRFC_DECODE(n) ((((u32)(n))>>0)&0x7F) - -#define DDR0_07 0x07 -#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 -#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((u32)(n))&0x1)<<24) -#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((u32)(n))>>24)&0x1) -#define DDR0_07_TFAW_MASK 0x001F0000 -#define DDR0_07_TFAW_ENCODE(n) ((((u32)(n))&0x1F)<<16) -#define DDR0_07_TFAW_DECODE(n) ((((u32)(n))>>16)&0x1F) -#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 -#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8) -#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1) -#define DDR0_07_AREFRESH_MASK 0x00000001 -#define DDR0_07_AREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<0) -#define DDR0_07_AREFRESH_DECODE(n) ((((u32)(n))>>0)&0x1) - -#define DDR0_08 0x08 -#define DDR0_08_WRLAT_MASK 0x07000000 -#define DDR0_08_WRLAT_ENCODE(n) ((((u32)(n))&0x7)<<24) -#define DDR0_08_WRLAT_DECODE(n) ((((u32)(n))>>24)&0x7) -#define DDR0_08_TCPD_MASK 0x00FF0000 -#define DDR0_08_TCPD_ENCODE(n) ((((u32)(n))&0xFF)<<16) -#define DDR0_08_TCPD_DECODE(n) ((((u32)(n))>>16)&0xFF) -#define DDR0_08_DQS_N_EN_MASK 0x00000100 -#define DDR0_08_DQS_N_EN_ENCODE(n) ((((u32)(n))&0x1)<<8) -#define DDR0_08_DQS_N_EN_DECODE(n) ((((u32)(n))>>8)&0x1) -#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 -#define DDR0_08_DDRII_ENCODE(n) ((((u32)(n))&0x1)<<0) -#define DDR0_08_DDRII_DECODE(n) ((((u32)(n))>>0)&0x1) - -#define DDR0_09 0x09 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 -#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24) -#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F) -#define DDR0_09_RTT_0_MASK 0x00030000 -#define DDR0_09_RTT_0_ENCODE(n) ((((u32)(n))&0x3)<<16) -#define DDR0_09_RTT_0_DECODE(n) ((((u32)(n))>>16)&0x3) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 -#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8) -#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F) -#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F -#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<0) -#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((u32)(n))>>0)&0x7F) - -#define DDR0_10 0x0A -#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ -#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((u32)(n))&0x1)<<16) -#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((u32)(n))>>16)&0x1) -#define DDR0_10_CS_MAP_MASK 0x00000300 -#define DDR0_10_CS_MAP_NO_MEM 0x00000000 -#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 -#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 -#define DDR0_10_CS_MAP_ENCODE(n) ((((u32)(n))&0x3)<<8) -#define DDR0_10_CS_MAP_DECODE(n) ((((u32)(n))>>8)&0x3) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F -#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<0) -#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((u32)(n))>>0)&0x1F) - -#define DDR0_11 0x0B -#define DDR0_11_SREFRESH_MASK 0x01000000 -#define DDR0_11_SREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<24) -#define DDR0_11_SREFRESH_DECODE(n) ((((u32)(n))>>24)&0x1F) -#define DDR0_11_TXSNR_MASK 0x00FF0000 -#define DDR0_11_TXSNR_ENCODE(n) ((((u32)(n))&0xFF)<<16) -#define DDR0_11_TXSNR_DECODE(n) ((((u32)(n))>>16)&0xFF) -#define DDR0_11_TXSR_MASK 0x0000FF00 -#define DDR0_11_TXSR_ENCODE(n) ((((u32)(n))&0xFF)<<8) -#define DDR0_11_TXSR_DECODE(n) ((((u32)(n))>>8)&0xFF) - -#define DDR0_12 0x0C -#define DDR0_12_TCKE_MASK 0x0000007 -#define DDR0_12_TCKE_ENCODE(n) ((((u32)(n))&0x7)<<0) -#define DDR0_12_TCKE_DECODE(n) ((((u32)(n))>>0)&0x7) - -#define DDR0_14 0x0E -#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 -#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((u32)(n))&0x1)<<24) -#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((u32)(n))>>24)&0x1) -#define DDR0_14_REDUC_MASK 0x00010000 -#define DDR0_14_REDUC_64BITS 0x00000000 -#define DDR0_14_REDUC_32BITS 0x00010000 -#define DDR0_14_REDUC_ENCODE(n) ((((u32)(n))&0x1)<<16) -#define DDR0_14_REDUC_DECODE(n) ((((u32)(n))>>16)&0x1) -#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 -#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((u32)(n))&0x1)<<8) -#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((u32)(n))>>8)&0x1) - -#define DDR0_17 0x11 -#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 -#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((u32)(n))&0x7F)<<24) -#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((u32)(n))>>24)&0x7F) -#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ -#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 -#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 -#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((u32)(n))&0x1)<<16) -#define DDR0_17_DLLLOCKREG_DECODE(n) ((((u32)(n))>>16)&0x1) -#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ -#define DDR0_17_DLL_LOCK_ENCODE(n) ((((u32)(n))&0x7F)<<8) -#define DDR0_17_DLL_LOCK_DECODE(n) ((((u32)(n))>>8)&0x7F) - -#define DDR0_18 0x12 -#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 -#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((u32)(n))&0x7F)<<24) -#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((u32)(n))>>24)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 -#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((u32)(n))&0x7F)<<16) -#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((u32)(n))>>16)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 -#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((u32)(n))&0x7F)<<8) -#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((u32)(n))>>8)&0x7F) -#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F -#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((u32)(n))&0x7F)<<0) -#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((u32)(n))>>0)&0x7F) - -#define DDR0_19 0x13 -#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F -#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 -#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((u32)(n))&0x7F)<<24) -#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((u32)(n))>>24)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 -#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((u32)(n))&0x7F)<<16) -#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((u32)(n))>>16)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 -#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((u32)(n))&0x7F)<<8) -#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((u32)(n))>>8)&0x7F) -#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F -#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((u32)(n))&0x7F)<<0) -#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((u32)(n))>>0)&0x7F) - -#define DDR0_20 0x14 -#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 -#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((u32)(n))&0x7F)<<24) -#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((u32)(n))>>24)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 -#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((u32)(n))&0x7F)<<16) -#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((u32)(n))>>16)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 -#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((u32)(n))&0x7F)<<8) -#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((u32)(n))>>8)&0x7F) -#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F -#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((u32)(n))&0x7F)<<0) -#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((u32)(n))>>0)&0x7F) - -#define DDR0_21 0x15 -#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 -#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((u32)(n))&0x7F)<<24) -#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((u32)(n))>>24)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 -#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((u32)(n))&0x7F)<<16) -#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((u32)(n))>>16)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 -#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((u32)(n))&0x7F)<<8) -#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((u32)(n))>>8)&0x7F) -#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F -#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((u32)(n))&0x7F)<<0) -#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((u32)(n))>>0)&0x7F) - -#define DDR0_22 0x16 -#define DDR0_22_CTRL_RAW_MASK 0x03000000 -#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 -#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 -#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 -#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 -#define DDR0_22_CTRL_RAW_ENCODE(n) ((((u32)(n))&0x3)<<24) -#define DDR0_22_CTRL_RAW_DECODE(n) ((((u32)(n))>>24)&0x3) -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<16) -#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>16)&0x7F) -#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 -#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<8) -#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((u32)(n))>>8)&0x7F) -#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F -#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((u32)(n))&0x7F)<<0) -#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((u32)(n))>>0)&0x7F) - -#define DDR0_23 0x17 -#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 -#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<24) -#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((u32)(n))>>24)&0x3) -#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ -#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<16) -#define DDR0_23_ECC_C_SYND_DECODE(n) ((((u32)(n))>>16)&0xFF) -#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ -#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<8) -#define DDR0_23_ECC_U_SYND_DECODE(n) ((((u32)(n))>>8)&0xFF) -#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ -#define DDR0_23_FWC_ENCODE(n) ((((u32)(n))&0x1)<<0) -#define DDR0_23_FWC_DECODE(n) ((((u32)(n))>>0)&0x1) - -#define DDR0_24 0x18 -#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 -#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((u32)(n))&0x3)<<24) -#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((u32)(n))>>24)&0x3) -#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 -#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<16) -#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((u32)(n))>>16)&0x3) -#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 -#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<8) -#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((u32)(n))>>8)&0x3) -#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 -#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<0) -#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((u32)(n))>>0)&0x3) - -#define DDR0_25 0x19 -#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ -#define DDR0_25_VERSION_ENCODE(n) ((((u32)(n))&0xFFFF)<<16) -#define DDR0_25_VERSION_DECODE(n) ((((u32)(n))>>16)&0xFFFF) -#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ -#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((u32)(n))&0x3FF)<<0) -#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((u32)(n))>>0)&0x3FF) - -#define DDR0_26 0x1A -#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 -#define DDR0_26_TRAS_MAX_ENCODE(n) ((((u32)(n))&0xFFFF)<<16) -#define DDR0_26_TRAS_MAX_DECODE(n) ((((u32)(n))>>16)&0xFFFF) -#define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((u32)(n))&0x3FFF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((u32)(n))>>0)&0x3FFF) - -#define DDR0_27 0x1B -#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 -#define DDR0_27_EMRS_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16) -#define DDR0_27_EMRS_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF) -#define DDR0_27_TINIT_MASK 0x0000FFFF -#define DDR0_27_TINIT_ENCODE(n) ((((u32)(n))&0xFFFF)<<0) -#define DDR0_27_TINIT_DECODE(n) ((((u32)(n))>>0)&0xFFFF) - -#define DDR0_28 0x1C -#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 -#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16) -#define DDR0_28_EMRS3_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF) -#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF -#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<0) -#define DDR0_28_EMRS2_DATA_DECODE(n) ((((u32)(n))>>0)&0x3FFF) - -#define DDR0_31 0x1F -#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF -#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((u32)(n))&0xFFFF)<<0) -#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((u32)(n))>>0)&0xFFFF) - -#define DDR0_32 0x20 -#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) -#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) - -#define DDR0_33 0x21 -#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0) -#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1) - -#define DDR0_34 0x22 -#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) -#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) - -#define DDR0_35 0x23 -#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0) -#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1) - -#define DDR0_36 0x24 -#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) -#define DDR0_36_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) - -#define DDR0_37 0x25 -#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) -#define DDR0_37_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) - -#define DDR0_38 0x26 -#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) -#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) - -#define DDR0_39 0x27 -#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ -#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0) -#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1) - -#define DDR0_40 0x28 -#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) -#define DDR0_40_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) - -#define DDR0_41 0x29 -#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ -#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0) -#define DDR0_41_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF) - -#define DDR0_42 0x2A -#define DDR0_42_ADDR_PINS_MASK 0x07000000 -#define DDR0_42_ADDR_PINS_ENCODE(n) ((((u32)(n))&0x7)<<24) -#define DDR0_42_ADDR_PINS_DECODE(n) ((((u32)(n))>>24)&0x7) -#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F -#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((u32)(n))&0xF)<<0) -#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((u32)(n))>>0)&0xF) - -#define DDR0_43 0x2B -#define DDR0_43_TWR_MASK 0x07000000 -#define DDR0_43_TWR_ENCODE(n) ((((u32)(n))&0x7)<<24) -#define DDR0_43_TWR_DECODE(n) ((((u32)(n))>>24)&0x7) -#define DDR0_43_APREBIT_MASK 0x000F0000 -#define DDR0_43_APREBIT_ENCODE(n) ((((u32)(n))&0xF)<<16) -#define DDR0_43_APREBIT_DECODE(n) ((((u32)(n))>>16)&0xF) -#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 -#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((u32)(n))&0x7)<<8) -#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((u32)(n))>>8)&0x7) -#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 -#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 -#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((u32)(n))&0x1)<<0) -#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((u32)(n))>>0)&0x1) - -#define DDR0_44 0x2C -#define DDR0_44_TRCD_MASK 0x000000FF -#define DDR0_44_TRCD_ENCODE(n) ((((u32)(n))&0xFF)<<0) -#define DDR0_44_TRCD_DECODE(n) ((((u32)(n))>>0)&0xFF) - -#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */ - -#ifndef __ASSEMBLY__ -/* - * Prototypes - */ -inline void ppc4xx_ibm_ddr2_register_dump(void); -u32 mfdcr_any(u32); -void mtdcr_any(u32, u32); -u32 ddr_wrdtr(u32); -u32 ddr_clktr(u32); -void spd_ddr_init_hang(void); -u32 DQS_autocalibration(void); -phys_size_t sdram_memsize(void); -void dcbz_area(u32 start_address, u32 num_bytes); -#endif /* __ASSEMBLY__ */ - -#endif /* _PPC4xx_SDRAM_H_ */ diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h deleted file mode 100644 index 782d045..0000000 --- a/include/asm-ppc/ppc4xx-uic.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (C) 2002 Scott McNutt - * - * (C) Copyright 2008-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PPC4xx_UIC_H_ -#define _PPC4xx_UIC_H_ - -/* - * Define the number of UIC's - */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) -#define UIC_MAX 4 -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) -#define UIC_MAX 3 -#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define UIC_MAX 2 -#else -#define UIC_MAX 1 -#endif - -#define IRQ_MAX (UIC_MAX * 32) - -/* - * UIC register - */ -#define UIC_SR 0x0 /* UIC status */ -#define UIC_ER 0x2 /* UIC enable */ -#define UIC_CR 0x3 /* UIC critical */ -#define UIC_PR 0x4 /* UIC polarity */ -#define UIC_TR 0x5 /* UIC triggering */ -#define UIC_MSR 0x6 /* UIC masked status */ -#define UIC_VR 0x7 /* UIC vector */ -#define UIC_VCR 0x8 /* UIC vector configuration */ - -/* - * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's - * are cascaded on. With this trick we can use the common UIC code for 440GX - * too. - */ -#if defined(CONFIG_440GX) -#define UIC0_DCR_BASE 0x200 -#define UIC1_DCR_BASE 0xc0 -#define UIC2_DCR_BASE 0xd0 -#define UIC3_DCR_BASE 0x210 -#else -#define UIC0_DCR_BASE 0xc0 -#define UIC1_DCR_BASE 0xd0 -#define UIC2_DCR_BASE 0xe0 -#define UIC3_DCR_BASE 0xf0 -#endif - -#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */ -#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */ -#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */ -#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ -#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ -#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ -#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */ -#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ - -#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */ -#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */ -#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */ -#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ -#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ -#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ -#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */ -#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ - -#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ -#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */ -#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */ -#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ -#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ -#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ -#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */ -#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ - -#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ -#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */ -#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */ -#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ -#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ -#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ -#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */ -#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ - -/* - * Now the interrupt vector definitions. They are different for most of - * the 4xx variants, so we need some more #ifdef's here. No mask - * definitions anymore here. For this please use the UIC_MASK macro below. - * - * Note: Please only define the interrupts really used in U-Boot here. - * Those are the cascading and EMAC/MAL related interrupt. - */ - -#if defined(CONFIG_405EP) || defined(CONFIG_405GP) -#define VECNUM_MAL_SERR 10 -#define VECNUM_MAL_TXEOB 11 -#define VECNUM_MAL_RXEOB 12 -#define VECNUM_MAL_TXDE 13 -#define VECNUM_MAL_RXDE 14 -#define VECNUM_ETH0 15 -#define VECNUM_ETH1_OFFS 2 -#define VECNUM_EIRQ6 29 -#endif /* defined(CONFIG_405EP) */ - -#if defined(CONFIG_405EZ) -#define VECNUM_USBDEV 15 -#define VECNUM_ETH0 16 -#define VECNUM_MAL_SERR 18 -#define VECNUM_MAL_TXDE 18 -#define VECNUM_MAL_RXDE 18 -#define VECNUM_MAL_TXEOB 19 -#define VECNUM_MAL_RXEOB 21 -#endif /* CONFIG_405EX */ - -#if defined(CONFIG_405EX) -/* UIC 0 */ -#define VECNUM_MAL_TXEOB 10 -#define VECNUM_MAL_RXEOB 11 -#define VECNUM_ETH0 24 -#define VECNUM_ETH1_OFFS 1 -#define VECNUM_UIC2NCI 28 -#define VECNUM_UIC2CI 29 -#define VECNUM_UIC1NCI 30 -#define VECNUM_UIC1CI 31 - -/* UIC 1 */ -#define VECNUM_MAL_SERR (32 + 0) -#define VECNUM_MAL_TXDE (32 + 1) -#define VECNUM_MAL_RXDE (32 + 2) -#endif /* CONFIG_405EX */ - -#if defined(CONFIG_440GP) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) -/* UIC 0 */ -#define VECNUM_MAL_TXEOB 10 -#define VECNUM_MAL_RXEOB 11 -#define VECNUM_UIC1NCI 30 -#define VECNUM_UIC1CI 31 - -/* UIC 1 */ -#define VECNUM_MAL_SERR (32 + 0) -#define VECNUM_MAL_TXDE (32 + 1) -#define VECNUM_MAL_RXDE (32 + 2) -#define VECNUM_USBDEV (32 + 23) -#define VECNUM_ETH0 (32 + 28) -#define VECNUM_ETH1_OFFS 2 -#endif /* CONFIG_440GP */ - -#if defined(CONFIG_440GX) -/* UICB 0 (440GX only) */ -/* - * All those defines below are off-by-one, so that the common UIC code - * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc. - */ -#define VECNUM_UIC1CI 0 -#define VECNUM_UIC1NCI 1 -#define VECNUM_UIC2CI 2 -#define VECNUM_UIC2NCI 3 -#define VECNUM_UIC3CI 4 -#define VECNUM_UIC3NCI 5 - -/* UIC 0, used as UIC1 on 440GX because of UICB0 */ -#define VECNUM_MAL_TXEOB (32 + 10) -#define VECNUM_MAL_RXEOB (32 + 11) - -/* UIC 1, used as UIC2 on 440GX because of UICB0 */ -#define VECNUM_MAL_SERR (64 + 0) -#define VECNUM_MAL_TXDE (64 + 1) -#define VECNUM_MAL_RXDE (64 + 2) -#define VECNUM_ETH0 (64 + 28) -#define VECNUM_ETH1_OFFS 2 -#endif /* CONFIG_440GX */ - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -/* UIC 0 */ -#define VECNUM_MAL_TXEOB 10 -#define VECNUM_MAL_RXEOB 11 -#define VECNUM_USBDEV 20 -#define VECNUM_ETH0 24 -#define VECNUM_ETH1_OFFS 1 -#define VECNUM_UIC2NCI 28 -#define VECNUM_UIC2CI 29 -#define VECNUM_UIC1NCI 30 -#define VECNUM_UIC1CI 31 - -/* UIC 1 */ -#define VECNUM_MAL_SERR (32 + 0) -#define VECNUM_MAL_TXDE (32 + 1) -#define VECNUM_MAL_RXDE (32 + 2) - -/* UIC 2 */ -#define VECNUM_EIRQ2 (64 + 3) -#endif /* CONFIG_440EPX */ - -#if defined(CONFIG_440SP) -/* UIC 0 */ -#define VECNUM_UIC1NCI 30 -#define VECNUM_UIC1CI 31 - -/* UIC 1 */ -#define VECNUM_MAL_SERR (32 + 1) -#define VECNUM_MAL_TXDE (32 + 2) -#define VECNUM_MAL_RXDE (32 + 3) -#define VECNUM_MAL_TXEOB (32 + 6) -#define VECNUM_MAL_RXEOB (32 + 7) -#define VECNUM_ETH0 (32 + 28) -#endif /* CONFIG_440SP */ - -#if defined(CONFIG_440SPE) -/* UIC 0 */ -#define VECNUM_UIC2NCI 10 -#define VECNUM_UIC2CI 11 -#define VECNUM_UIC3NCI 16 -#define VECNUM_UIC3CI 17 -#define VECNUM_UIC1NCI 30 -#define VECNUM_UIC1CI 31 - -/* UIC 1 */ -#define VECNUM_MAL_SERR (32 + 1) -#define VECNUM_MAL_TXDE (32 + 2) -#define VECNUM_MAL_RXDE (32 + 3) -#define VECNUM_MAL_TXEOB (32 + 6) -#define VECNUM_MAL_RXEOB (32 + 7) -#define VECNUM_ETH0 (32 + 28) -#endif /* CONFIG_440SPE */ - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -/* UIC 0 */ -#define VECNUM_UIC2NCI 10 -#define VECNUM_UIC2CI 11 -#define VECNUM_UIC3NCI 16 -#define VECNUM_UIC3CI 17 -#define VECNUM_UIC1NCI 30 -#define VECNUM_UIC1CI 31 - -/* UIC 2 */ -#define VECNUM_MAL_SERR (64 + 3) -#define VECNUM_MAL_TXDE (64 + 4) -#define VECNUM_MAL_RXDE (64 + 5) -#define VECNUM_MAL_TXEOB (64 + 6) -#define VECNUM_MAL_RXEOB (64 + 7) -#define VECNUM_ETH0 (64 + 16) -#define VECNUM_ETH1_OFFS 1 -#endif /* CONFIG_460EX */ - -#if defined(CONFIG_460SX) -/* UIC 0 */ -#define VECNUM_UIC2NCI 10 -#define VECNUM_UIC2CI 11 -#define VECNUM_UIC3NCI 16 -#define VECNUM_UIC3CI 17 -#define VECNUM_ETH0 19 -#define VECNUM_ETH1_OFFS 1 -#define VECNUM_UIC1NCI 30 -#define VECNUM_UIC1CI 31 - -/* UIC 1 */ -#define VECNUM_MAL_SERR (32 + 1) -#define VECNUM_MAL_TXDE (32 + 2) -#define VECNUM_MAL_RXDE (32 + 3) -#define VECNUM_MAL_TXEOB (32 + 6) -#define VECNUM_MAL_RXEOB (32 + 7) -#endif /* CONFIG_460EX */ - -#if !defined(VECNUM_ETH1_OFFS) -#define VECNUM_ETH1_OFFS 1 -#endif - -/* - * Mask definitions (used for example in 4xx_enet.c) - */ -#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) -/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ -#define UIC_NR(vec) ((vec) >> 5) - -#endif /* _PPC4xx_UIC_H_ */ diff --git a/include/asm-ppc/ppc4xx_config.h b/include/asm-ppc/ppc4xx_config.h deleted file mode 100644 index 49acb60..0000000 --- a/include/asm-ppc/ppc4xx_config.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2009 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __PPC4xx_CONFIG_H -#define __PPC4xx_CONFIG_H - -#include - -struct ppc4xx_config { - char label[16]; - char description[64]; - u8 val[CONFIG_4xx_CONFIG_BLOCKSIZE]; -}; - -extern struct ppc4xx_config ppc4xx_config_val[]; -extern int ppc4xx_config_count; - -#endif /* __PPC4xx_CONFIG_H */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h deleted file mode 100644 index 9ec319a..0000000 --- a/include/asm-ppc/processor.h +++ /dev/null @@ -1,1285 +0,0 @@ -#ifndef __ASM_PPC_PROCESSOR_H -#define __ASM_PPC_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#include - -#include -#include - -/* Machine State Register (MSR) Fields */ - -#ifdef CONFIG_PPC64BRIDGE -#define MSR_SF (1<<63) -#define MSR_ISF (1<<61) -#endif /* CONFIG_PPC64BRIDGE */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ -#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ -#define MSR_SPE (1<<25) /* Enable SPE(e500) */ -#define MSR_POW (1<<18) /* Enable Power Management */ -#define MSR_WE (1<<18) /* Wait State Enable */ -#define MSR_TGPR (1<<17) /* TLB Update registers in use */ -#define MSR_CE (1<<17) /* Critical Interrupt Enable */ -#define MSR_ILE (1<<16) /* Interrupt Little Endian */ -#define MSR_EE (1<<15) /* External Interrupt Enable */ -#define MSR_PR (1<<14) /* Problem State / Privilege Level */ -#define MSR_FP (1<<13) /* Floating Point enable */ -#define MSR_ME (1<<12) /* Machine Check Enable */ -#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ -#define MSR_SE (1<<10) /* Single Step */ -#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ -#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ -#define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* Debug Exception Enable */ -#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ -#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction Relocate */ -#define MSR_IS (1<<5) /* Book E Instruction space */ -#define MSR_DR (1<<4) /* Data Relocate */ -#define MSR_DS (1<<4) /* Book E Data space */ -#define MSR_PE (1<<3) /* Protection Enable */ -#define MSR_PX (1<<2) /* Protection Exclusive Mode */ -#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ -#define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little Endian */ - -#ifdef CONFIG_APUS_FAST_EXCEPT -#define MSR_ MSR_ME|MSR_IP|MSR_RI -#else -#define MSR_ MSR_ME|MSR_RI -#endif -#ifndef CONFIG_E500 -#define MSR_KERNEL MSR_|MSR_IR|MSR_DR -#else -#define MSR_KERNEL MSR_ME -#endif - -/* Floating Point Status and Control Register (FPSCR) Fields */ - -#define FPSCR_FX 0x80000000 /* FPU exception summary */ -#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ -#define FPSCR_VX 0x20000000 /* Invalid operation summary */ -#define FPSCR_OX 0x10000000 /* Overflow exception summary */ -#define FPSCR_UX 0x08000000 /* Underflow exception summary */ -#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ -#define FPSCR_XX 0x02000000 /* Inexact exception summary */ -#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ -#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ -#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ -#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ -#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ -#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ -#define FPSCR_FR 0x00040000 /* Fraction rounded */ -#define FPSCR_FI 0x00020000 /* Fraction inexact */ -#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ -#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ -#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ -#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ -#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ -#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ -#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ -#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ -#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ -#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ -#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ -#define FPSCR_RN 0x00000003 /* FPU rounding control */ - -/* Special Purpose Registers (SPRNs)*/ - -/* PPC440 Architecture is BOOK-E */ -#ifdef CONFIG_440 -#define CONFIG_BOOKE -#endif - -#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ -#ifdef CONFIG_BOOKE -#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ -#endif -#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ -#define SPRN_CTR 0x009 /* Count Register */ -#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ -#ifndef CONFIG_BOOKE -#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ -#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ -#else -#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ -#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DAR 0x013 /* Data Address Register */ -#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ -#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ -#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ -#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ -#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ -#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ -#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ -#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ -#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ -#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ -#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ -#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ -#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ -#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ -#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ -#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ -#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ -#define DBCR_EDM 0x80000000 -#define DBCR_IDM 0x40000000 -#define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 -#define DBCR_RST_SYSTEM 3 -#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ -#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ -#define DBCR_EDE 0x02000000 /* Exception Debug Event */ -#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ -#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ -#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ -#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ -#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ -#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ -#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ -#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ -#define DAC_BYTE 0 -#define DAC_HALF 1 -#define DAC_WORD 2 -#define DAC_QUAD 3 -#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ -#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ -#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ -#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ -#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ -#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ -#define DBCR_SIA 0x00000008 /* Second IAC Enable */ -#define DBCR_SDA 0x00000004 /* Second DAC Enable */ -#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ -#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ -#ifndef CONFIG_BOOKE -#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ -#else -#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ -#endif /* CONFIG_BOOKE */ -#ifndef CONFIG_BOOKE -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ -#else -#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ -#ifdef CONFIG_BOOKE -#define SPRN_DBDR 0x3f3 /* Debug Data Register */ -#endif -#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ -#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ -#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ -#define DCCR_NOCACHE 0 /* Noncacheable */ -#define DCCR_CACHE 1 /* Cacheable */ -#ifndef CONFIG_BOOKE -#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ -#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ -#endif -#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ -#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ -#define DCWR_COPY 0 /* Copy-back */ -#define DCWR_WRITE 1 /* Write-through */ -#ifndef CONFIG_BOOKE -#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ -#else -#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DEC 0x016 /* Decrement Register */ -#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ -#ifdef CONFIG_BOOKE -#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ -#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ -#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ -#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ -#endif -#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ -#ifdef CONFIG_BOOKE -#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ -#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ -#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ -#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ -#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ -#endif -#define SPRN_EAR 0x11A /* External Address Register */ -#ifndef CONFIG_BOOKE -#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ -#else -#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ -#endif /* CONFIG_BOOKE */ -#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ -#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ -#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ -#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ -#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ -#define ESR_PTR 0x02000000 /* Program Exception - Trap */ -#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ -#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ -#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ -#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ -#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ -#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ - -#define HID0_ICE_SHIFT 15 -#define HID0_DCE_SHIFT 14 -#define HID0_DLOCK_SHIFT 12 - -#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ -#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ -#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ -#define HID0_SBCLK (1<<27) -#define HID0_EICE (1<<26) -#define HID0_ECLK (1<<25) -#define HID0_PAR (1<<24) -#define HID0_DOZE (1<<23) -#define HID0_NAP (1<<22) -#define HID0_SLEEP (1<<21) -#define HID0_DPM (1<<20) -#define HID0_ICE (1<> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ - -#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ -#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ -#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ -#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ -#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ -#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ -#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ - -/* Processor Version Register */ - -/* Processor Version Register (PVR) field extraction */ - -#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ -#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ - -/* - * AMCC has further subdivided the standard PowerPC 16-bit version and - * revision subfields of the PVR for the PowerPC 403s into the following: - */ - -#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ -#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ -#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ -#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ -#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ -#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ - -/* e600 core PVR fields */ - -#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ -#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ -#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ -#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ - -/* Processor Version Numbers */ - -#define PVR_403GA 0x00200000 -#define PVR_403GB 0x00200100 -#define PVR_403GC 0x00200200 -#define PVR_403GCX 0x00201400 -#define PVR_405GP 0x40110000 -#define PVR_405GP_RB 0x40110040 -#define PVR_405GP_RC 0x40110082 -#define PVR_405GP_RD 0x401100C4 -#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ -#define PVR_405CR_RA 0x40110041 -#define PVR_405CR_RB 0x401100C5 -#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ -#define PVR_405EP_RA 0x51210950 -#define PVR_405GPR_RB 0x50910951 -#define PVR_405EZ_RA 0x41511460 -#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ -#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ -#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ -#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ -#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ -#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ -#define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */ -#define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */ -#define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */ -#define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */ -#define PVR_440GP_RB 0x40120440 -#define PVR_440GP_RC 0x40120481 -#define PVR_440EP_RA 0x42221850 -#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ -#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ -#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ -#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ -#define PVR_440GX_RA 0x51B21850 -#define PVR_440GX_RB 0x51B21851 -#define PVR_440GX_RC 0x51B21892 -#define PVR_440GX_RF 0x51B21894 -#define PVR_405EP_RB 0x51210950 -#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ -#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ -#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ -#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ -#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ -#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ -#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ -#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ -#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ -#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ -#define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/ -#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ -#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ -#define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/ -#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ -#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ -#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ -#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ -#define PVR_601 0x00010000 -#define PVR_602 0x00050000 -#define PVR_603 0x00030000 -#define PVR_603e 0x00060000 -#define PVR_603ev 0x00070000 -#define PVR_603r 0x00071000 -#define PVR_604 0x00040000 -#define PVR_604e 0x00090000 -#define PVR_604r 0x000A0000 -#define PVR_620 0x00140000 -#define PVR_740 0x00080000 -#define PVR_750 PVR_740 -#define PVR_740P 0x10080000 -#define PVR_750P PVR_740P -#define PVR_7400 0x000C0000 -#define PVR_7410 0x800C0000 -#define PVR_7450 0x80000000 - -#define PVR_85xx 0x80200000 -#define PVR_85xx_REV1 (PVR_85xx | 0x0010) -#define PVR_85xx_REV2 (PVR_85xx | 0x0020) - -#define PVR_86xx 0x80040000 - -#define PVR_VIRTEX5 0x7ff21912 - -/* - * For the 8xx processors, all of them report the same PVR family for - * the PowerPC core. The various versions of these processors must be - * differentiated by the version number in the Communication Processor - * Module (CPM). - */ -#define PVR_821 0x00500000 -#define PVR_823 PVR_821 -#define PVR_850 PVR_821 -#define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 -#define PVR_8240 0x00810100 - -/* - * PowerQUICC II family processors report different PVR values depending - * on silicon process (HiP3, HiP4, HiP7, etc.) - */ -#define PVR_8260 PVR_8240 -#define PVR_8260_HIP3 0x00810101 -#define PVR_8260_HIP4 0x80811014 -#define PVR_8260_HIP7 0x80822011 -#define PVR_8260_HIP7R1 0x80822013 -#define PVR_8260_HIP7RA 0x80822014 - -/* - * MPC 52xx - */ -#define PVR_5200 0x80822011 -#define PVR_5200B 0x80822014 - -/* - * System Version Register - */ - -/* System Version Register (SVR) field extraction */ - -#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ - -#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ - -#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ -#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ - -#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ -#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ - -/* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ - -/* whether MPC8xxxE (i.e. has SEC) */ -#if defined(CONFIG_MPC85xx) -#define IS_E_PROCESSOR(svr) (svr & 0x80000) -#else -#if defined(CONFIG_MPC83xx) -#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) -#endif -#endif - -#define IS_SVR_REV(svr, maj, min) \ - ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) - -/* - * SVR_SOC_VER() Version Values - */ - -#define SVR_8533 0x803400 -#define SVR_8533_E 0x803C00 -#define SVR_8535 0x803701 -#define SVR_8535_E 0x803F01 -#define SVR_8536 0x803700 -#define SVR_8536_E 0x803F00 -#define SVR_8540 0x803000 -#define SVR_8541 0x807200 -#define SVR_8541_E 0x807A00 -#define SVR_8543 0x803200 -#define SVR_8543_E 0x803A00 -#define SVR_8544 0x803401 -#define SVR_8544_E 0x803C01 -#define SVR_8545 0x803102 -#define SVR_8545_E 0x803902 -#define SVR_8547_E 0x803901 -#define SVR_8548 0x803100 -#define SVR_8548_E 0x803900 -#define SVR_8555 0x807100 -#define SVR_8555_E 0x807900 -#define SVR_8560 0x807000 -#define SVR_8567 0x807600 -#define SVR_8567_E 0x807E00 -#define SVR_8568 0x807500 -#define SVR_8568_E 0x807D00 -#define SVR_8569 0x808000 -#define SVR_8569_E 0x808800 -#define SVR_8572 0x80E000 -#define SVR_8572_E 0x80E800 -#define SVR_P1011 0x80E500 -#define SVR_P1011_E 0x80ED00 -#define SVR_P1012 0x80E501 -#define SVR_P1012_E 0x80ED01 -#define SVR_P1013 0x80E700 -#define SVR_P1013_E 0x80EF00 -#define SVR_P1020 0x80E400 -#define SVR_P1020_E 0x80EC00 -#define SVR_P1021 0x80E401 -#define SVR_P1021_E 0x80EC01 -#define SVR_P1022 0x80E600 -#define SVR_P1022_E 0x80EE00 -#define SVR_P2010 0x80E300 -#define SVR_P2010_E 0x80EB00 -#define SVR_P2020 0x80E200 -#define SVR_P2020_E 0x80EA00 -#define SVR_P4040 0x820100 -#define SVR_P4040_E 0x820900 -#define SVR_P4080 0x820000 -#define SVR_P4080_E 0x820800 - -#define SVR_8610 0x80A000 -#define SVR_8641 0x809000 -#define SVR_8641D 0x809001 - -#define SVR_Unknown 0xFFFFFF - -#define _GLOBAL(n)\ - .globl n;\ -n: - -/* Macros for setting and retrieving special purpose registers */ - -#define stringify(s) tostring(s) -#define tostring(s) #s - -#define mfdcr(rn) ({unsigned int rval; \ - asm volatile("mfdcr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) - -#define mfmsr() ({unsigned int rval; \ - asm volatile("mfmsr %0" : "=r" (rval)); rval;}) -#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) - -#define mfspr(rn) ({unsigned int rval; \ - asm volatile("mfspr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) - -#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) - -/* Segment Registers */ - -#define SR0 0 -#define SR1 1 -#define SR2 2 -#define SR3 3 -#define SR4 4 -#define SR5 5 -#define SR6 6 -#define SR7 7 -#define SR8 8 -#define SR9 9 -#define SR10 10 -#define SR11 11 -#define SR12 12 -#define SR13 13 -#define SR14 14 -#define SR15 15 - -#ifndef __ASSEMBLY__ - -struct cpu_type { - char name[15]; - u32 soc_ver; - u32 num_cores; -}; - -struct cpu_type *identify_cpu(u32 ver); - -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) -#define CPU_TYPE_ENTRY(n, v, nc) \ - { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), } -#else -#if defined(CONFIG_MPC83xx) -#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} -#endif -#endif - - -#ifndef CONFIG_MACH_SPECIFIC -extern int _machine; -extern int have_of; -#endif /* CONFIG_MACH_SPECIFIC */ - -/* what kind of prep workstation we are */ -extern int _prep_type; -/* - * This is used to identify the board type from a given PReP board - * vendor. Board revision is also made available. - */ -extern unsigned char ucSystemType; -extern unsigned char ucBoardRev; -extern unsigned char ucBoardRevMaj, ucBoardRevMin; - -struct task_struct; -void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); -void release_thread(struct task_struct *); - -/* - * Create a new kernel thread. - */ -extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -/* - * Bus types - */ -#define EISA_bus 0 -#define EISA_bus__is_a_macro /* for versions in ksyms.c */ -#define MCA_bus 0 -#define MCA_bus__is_a_macro /* for versions in ksyms.c */ - -/* Lazy FPU handling on uni-processor */ -extern struct task_struct *last_task_used_math; -extern struct task_struct *last_task_used_altivec; - -/* - * this is the minimum allowable io space due to the location - * of the io areas on prep (first one at 0x80000000) but - * as soon as I get around to remapping the io areas with the BATs - * to match the mac we can raise this. -- Cort - */ -#define TASK_SIZE (0x80000000UL) - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) - -typedef struct { - unsigned long seg; -} mm_segment_t; - -struct thread_struct { - unsigned long ksp; /* Kernel stack pointer */ - unsigned long wchan; /* Event task is sleeping on */ - struct pt_regs *regs; /* Pointer to saved register state */ - mm_segment_t fs; /* for get_fs() validation */ - void *pgdir; /* root of page-table tree */ - signed long last_syscall; - double fpr[32]; /* Complete floating point set */ - unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ - unsigned long fpscr; /* Floating point status */ -#ifdef CONFIG_ALTIVEC - vector128 vr[32]; /* Complete AltiVec set */ - vector128 vscr; /* AltiVec status */ - unsigned long vrsave; -#endif /* CONFIG_ALTIVEC */ -}; - -#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) - -#define INIT_THREAD { \ - INIT_SP, /* ksp */ \ - 0, /* wchan */ \ - (struct pt_regs *)INIT_SP - 1, /* regs */ \ - KERNEL_DS, /*fs*/ \ - swapper_pg_dir, /* pgdir */ \ - 0, /* last_syscall */ \ - {0}, 0, 0 \ -} - -/* - * Note: the vm_start and vm_end fields here should *not* - * be in kernel space. (Could vm_end == vm_start perhaps?) - */ -#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ - PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ - 1, NULL, NULL } - -/* - * Return saved PC of a blocked thread. For now, this is the "user" PC - */ -static inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - return (t->regs) ? t->regs->nip : 0; -} - -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) -#define forget_segments() do { } while (0) - -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) -#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) - -/* - * NOTE! The task struct and the stack go together - */ -#define THREAD_SIZE (2*PAGE_SIZE) -#define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) - -/* in process.c - for early bootup debug -- Cort */ -int ll_printk(const char *, ...); -void ll_puts(const char *); - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -/* In misc.c */ -void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); - -#endif /* ndef ASSEMBLY*/ - -#ifdef CONFIG_MACH_SPECIFIC -#if defined(CONFIG_8xx) -#define _machine _MACH_8xx -#define have_of 0 -#elif defined(CONFIG_OAK) -#define _machine _MACH_oak -#define have_of 0 -#elif defined(CONFIG_WALNUT) -#define _machine _MACH_walnut -#define have_of 0 -#elif defined(CONFIG_APUS) -#define _machine _MACH_apus -#define have_of 0 -#elif defined(CONFIG_GEMINI) -#define _machine _MACH_gemini -#define have_of 0 -#elif defined(CONFIG_8260) -#define _machine _MACH_8260 -#define have_of 0 -#elif defined(CONFIG_SANDPOINT) -#define _machine _MACH_sandpoint -#elif defined(CONFIG_HIDDEN_DRAGON) -#define _machine _MACH_hidden_dragon -#define have_of 0 -#else -#error "Machine not defined correctly" -#endif -#endif /* CONFIG_MACH_SPECIFIC */ - -#endif /* __ASM_PPC_PROCESSOR_H */ diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h deleted file mode 100644 index 196613b..0000000 --- a/include/asm-ppc/ptrace.h +++ /dev/null @@ -1,107 +0,0 @@ -#ifndef _PPC_PTRACE_H -#define _PPC_PTRACE_H - -/* - * This struct defines the way the registers are stored on the - * kernel stack during a system call or other kernel entry. - * - * this should only contain volatile regs - * since we can keep non-volatile in the thread_struct - * should set this up when only volatiles are saved - * by intr code. - * - * Since this is going on the stack, *CARE MUST BE TAKEN* to insure - * that the overall structure is a multiple of 16 bytes in length. - * - * Note that the offsets of the fields in this struct correspond with - * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. - */ - -#include - -#ifndef __ASSEMBLY__ -#ifdef CONFIG_PPC64BRIDGE -#define PPC_REG unsigned long /*long*/ -#else -#define PPC_REG unsigned long -#endif -struct pt_regs { - PPC_REG gpr[32]; - PPC_REG nip; - PPC_REG msr; - PPC_REG orig_gpr3; /* Used for restarting system calls */ - PPC_REG ctr; - PPC_REG link; - PPC_REG xer; - PPC_REG ccr; - PPC_REG mq; /* 601 only (not used at present) */ - /* Used on APUS to hold IPL value. */ - PPC_REG trap; /* Reason for being here */ - PPC_REG dar; /* Fault registers */ - PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ -}; -#endif - -#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ - -/* Size of stack frame allocated when calling signal handler. */ -#define __SIGNAL_FRAMESIZE 64 - -#define instruction_pointer(regs) ((regs)->nip) -#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) - -/* - * Offsets used by 'ptrace' system call interface. - * These can't be changed without breaking binary compatibility - * with MkLinux, etc. - */ -#define PT_R0 0 -#define PT_R1 1 -#define PT_R2 2 -#define PT_R3 3 -#define PT_R4 4 -#define PT_R5 5 -#define PT_R6 6 -#define PT_R7 7 -#define PT_R8 8 -#define PT_R9 9 -#define PT_R10 10 -#define PT_R11 11 -#define PT_R12 12 -#define PT_R13 13 -#define PT_R14 14 -#define PT_R15 15 -#define PT_R16 16 -#define PT_R17 17 -#define PT_R18 18 -#define PT_R19 19 -#define PT_R20 20 -#define PT_R21 21 -#define PT_R22 22 -#define PT_R23 23 -#define PT_R24 24 -#define PT_R25 25 -#define PT_R26 26 -#define PT_R27 27 -#define PT_R28 28 -#define PT_R29 29 -#define PT_R30 30 -#define PT_R31 31 - -#define PT_NIP 32 -#define PT_MSR 33 -#ifdef __KERNEL__ -#define PT_ORIG_R3 34 -#endif -#define PT_CTR 35 -#define PT_LNK 36 -#define PT_XER 37 -#define PT_CCR 38 -#define PT_MQ 39 - -#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ -#define PT_FPR31 (PT_FPR0 + 2*31) -#define PT_FPSCR (PT_FPR0 + 2*32 + 1) - -#endif diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h deleted file mode 100644 index dc85edb..0000000 --- a/include/asm-ppc/residual.h +++ /dev/null @@ -1,331 +0,0 @@ -/* 7/18/95 */ -/*----------------------------------------------------------------------------*/ -/* Residual Data header definitions and prototypes */ -/*----------------------------------------------------------------------------*/ - -/* Structure map for RESIDUAL on PowerPC Reference Platform */ -/* residual.h - Residual data structure passed in r3. */ -/* Load point passed in r4 to boot image. */ -/* For enum's: if given in hex then they are bit significant, */ -/* i.e. only one bit is on for each enum */ -/* Reserved fields must be filled with zeros. */ - -#ifndef _RESIDUAL_ -#define _RESIDUAL_ - -#ifndef __ASSEMBLY__ - -#define MAX_CPUS 32 /* These should be set to the maximum */ -#define MAX_MEMS 64 /* number possible for this system. */ -#define MAX_DEVICES 256 /* Changing these will change the */ -#define AVE_PNP_SIZE 32 /* structure, hence the version of */ -#define MAX_MEM_SEGS 64 /* this header file. */ - -/*----------------------------------------------------------------------------*/ -/* Public structures... */ -/*----------------------------------------------------------------------------*/ - -#include "pnp.h" - -typedef enum _L1CACHE_TYPE { - NoneCAC = 0, - SplitCAC = 1, - CombinedCAC = 2 - } L1CACHE_TYPE; - -typedef enum _TLB_TYPE { - NoneTLB = 0, - SplitTLB = 1, - CombinedTLB = 2 - } TLB_TYPE; - -typedef enum _FIRMWARE_SUPPORT { - Conventional = 0x01, - OpenFirmware = 0x02, - Diagnostics = 0x04, - LowDebug = 0x08, - Multiboot = 0x10, - LowClient = 0x20, - Hex41 = 0x40, - FAT = 0x80, - ISO9660 = 0x0100, - SCSI_InitiatorID_Override = 0x0200, - Tape_Boot = 0x0400, - FW_Boot_Path = 0x0800 - } FIRMWARE_SUPPORT; - -typedef enum _FIRMWARE_SUPPLIERS { - IBMFirmware = 0x00, - MotoFirmware = 0x01, /* 7/18/95 */ - FirmWorks = 0x02, /* 10/5/95 */ - Bull = 0x03, /* 04/03/96 */ - } FIRMWARE_SUPPLIERS; - -typedef enum _ENDIAN_SWITCH_METHODS { - UsePort92 = 0x01, - UsePCIConfigA8 = 0x02, - UseFF001030 = 0x03, - } ENDIAN_SWITCH_METHODS; - -typedef enum _SPREAD_IO_METHODS { - UsePort850 = 0x00, -/*UsePCIConfigA8 = 0x02,*/ - } SPREAD_IO_METHODS; - -typedef struct _VPD { - - /* Box dependent stuff */ - unsigned char PrintableModel[32]; /* Null terminated string. - Must be of the form: - vvv,<20h>,,<0x0> - where vvv is the vendor ID - e.g. IBM PPS MODEL 6015<0x0> */ - unsigned char Serial[16]; /* 12/94: - Serial Number; must be of the form: - vvv where vvv is the - vendor ID. - e.g. IBM60151234567<20h><20h> */ - unsigned char Reserved[48]; - unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ - unsigned long FirmwareSupports; /* See FirmwareSupport enum */ - unsigned long NvramSize; /* Size of nvram in bytes */ - unsigned long NumSIMMSlots; - unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ - unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ - unsigned long SmpIar; - unsigned long RAMErrLogOffset; /* Heap offset to error log */ - unsigned long Reserved5; - unsigned long Reserved6; - unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ - unsigned long ProcessorBusHz; /* Processor bus clock frequency */ - unsigned long Reserved7; - unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ - unsigned long WordWidth; /* Word width in bits */ - unsigned long PageSize; /* Page size in bytes */ - unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache - for which coherency is maintained; - normally <= CacheLineSize. */ - unsigned long GranuleSize; /* Unit of lock allocation to avoid */ - /* false sharing of locks. */ - - /* L1 Cache variables */ - unsigned long CacheSize; /* L1 Cache size in KB. This is the */ - /* total size of the L1, whether */ - /* combined or split */ - unsigned long CacheAttrib; /* L1CACHE_TYPE */ - unsigned long CacheAssoc; /* L1 Cache associativity. Use this - for combined cache. If split, put - zeros here. */ - unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use - for combined cache. If split, put - zeros here. */ - /* For split L1 Cache: (= combined if combined cache) */ - unsigned long I_CacheSize; - unsigned long I_CacheAssoc; - unsigned long I_CacheLineSize; - unsigned long D_CacheSize; - unsigned long D_CacheAssoc; - unsigned long D_CacheLineSize; - - /* Translation Lookaside Buffer variables */ - unsigned long TLBSize; /* Total number of TLBs on the system */ - unsigned long TLBAttrib; /* Combined I+D or split TLB */ - unsigned long TLBAssoc; /* TLB Associativity. Use this for - combined TLB. If split, put zeros - here. */ - /* For split TLB: (= combined if combined TLB) */ - unsigned long I_TLBSize; - unsigned long I_TLBAssoc; - unsigned long D_TLBSize; - unsigned long D_TLBAssoc; - - unsigned long ExtendedVPD; /* Offset to extended VPD area; - null if unused */ - } VPD; - -typedef enum _DEVICE_FLAGS { - Enabled = 0x4000, /* 1 - PCI device is enabled */ - Integrated = 0x2000, - Failed = 0x1000, /* 1 - device failed POST code tests */ - Static = 0x0800, /* 0 - dynamically configurable - 1 - static */ - Dock = 0x0400, /* 0 - not a docking station device - 1 - is a docking station device */ - Boot = 0x0200, /* 0 - device cannot be used for BOOT - 1 - can be a BOOT device */ - Configurable = 0x0100, /* 1 - device is configurable */ - Disableable = 0x80, /* 1 - device can be disabled */ - PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ - ReadOnly = 0x20, /* 1 - device is read only */ - Removable = 0x10, /* 1 - device is removable */ - ConsoleIn = 0x08, - ConsoleOut = 0x04, - Input = 0x02, - Output = 0x01 - } DEVICE_FLAGS; - -typedef enum _BUS_ID { - ISADEVICE = 0x01, - EISADEVICE = 0x02, - PCIDEVICE = 0x04, - PCMCIADEVICE = 0x08, - PNPISADEVICE = 0x10, - MCADEVICE = 0x20, - MXDEVICE = 0x40, /* Devices on mezzanine bus */ - PROCESSORDEVICE = 0x80, /* Devices on processor bus */ - VMEDEVICE = 0x100, - } BUS_ID; - -typedef struct _DEVICE_ID { - unsigned long BusId; /* See BUS_ID enum above */ - unsigned long DevId; /* Big Endian format */ - unsigned long SerialNum; /* For multiple usage of a single - DevId */ - unsigned long Flags; /* See DEVICE_FLAGS enum above */ - unsigned char BaseType; /* See pnp.h for bit definitions */ - unsigned char SubType; /* See pnp.h for bit definitions */ - unsigned char Interface; /* See pnp.h for bit definitions */ - unsigned char Spare; - } DEVICE_ID; - -typedef union _BUS_ACCESS { - struct _PnPAccess{ - unsigned char CSN; - unsigned char LogicalDevNumber; - unsigned short ReadDataPort; - } PnPAccess; - struct _ISAAccess{ - unsigned char SlotNumber; /* ISA Slot Number generally not - available; 0 if unknown */ - unsigned char LogicalDevNumber; - unsigned short ISAReserved; - } ISAAccess; - struct _MCAAccess{ - unsigned char SlotNumber; - unsigned char LogicalDevNumber; - unsigned short MCAReserved; - } MCAAccess; - struct _PCMCIAAccess{ - unsigned char SlotNumber; - unsigned char LogicalDevNumber; - unsigned short PCMCIAReserved; - } PCMCIAAccess; - struct _EISAAccess{ - unsigned char SlotNumber; - unsigned char FunctionNumber; - unsigned short EISAReserved; - } EISAAccess; - struct _PCIAccess{ - unsigned char BusNumber; - unsigned char DevFuncNumber; - unsigned short PCIReserved; - } PCIAccess; - struct _ProcBusAccess{ - unsigned char BusNumber; - unsigned char BUID; - unsigned short ProcBusReserved; - } ProcBusAccess; - } BUS_ACCESS; - -/* Per logical device information */ -typedef struct _PPC_DEVICE { - DEVICE_ID DeviceId; - BUS_ACCESS BusAccess; - - /* The following three are offsets into the DevicePnPHeap */ - /* All are in PnP compressed format */ - unsigned long AllocatedOffset; /* Allocated resource description */ - unsigned long PossibleOffset; /* Possible resource description */ - unsigned long CompatibleOffset; /* Compatible device identifiers */ - } PPC_DEVICE; - -typedef enum _CPU_STATE { - CPU_GOOD = 0, /* CPU is present, and active */ - CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ - CPU_OFF = 2, /* CPU is present, but inactive */ - CPU_FAILED = 3, /* CPU is present, but failed POST */ - CPU_NOT_PRESENT = 255 /* CPU not present */ - } CPU_STATE; - -typedef struct _PPC_CPU { - unsigned long CpuType; /* Result of mfspr from Processor - Version Register (PVR). - PVR(0-15) = Version (e.g. 601) - PVR(16-31 = EC Level */ - unsigned char CpuNumber; /* CPU Number for this processor */ - unsigned char CpuState; /* CPU State, see CPU_STATE enum */ - unsigned short Reserved; - } PPC_CPU; - -typedef struct _PPC_MEM { - unsigned long SIMMSize; /* 0 - absent or bad - 8M, 32M (in MB) */ - } PPC_MEM; - -typedef enum _MEM_USAGE { - Other = 0x8000, - ResumeBlock = 0x4000, /* for use by power management */ - SystemROM = 0x2000, /* Flash memory (populated) */ - UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ - IOMemory = 0x0800, - SystemIO = 0x0400, - SystemRegs = 0x0200, - PCIAddr = 0x0100, - PCIConfig = 0x80, - ISAAddr = 0x40, - Unpopulated = 0x20, /* Unpopulated part of System Memory */ - Free = 0x10, /* Free part of System Memory */ - BootImage = 0x08, /* BootImage part of System Memory */ - FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ - FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ - FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ - } MEM_USAGE; - -typedef struct _MEM_MAP { - unsigned long Usage; /* See MEM_USAGE above */ - unsigned long BasePage; /* Page number measured in 4KB pages */ - unsigned long PageCount; /* Page count measured in 4KB pages */ - } MEM_MAP; - -typedef struct _RESIDUAL { - unsigned long ResidualLength; /* Length of Residual */ - unsigned char Version; /* of this data structure */ - unsigned char Revision; /* of this data structure */ - unsigned short EC; /* of this data structure */ - /* VPD */ - VPD VitalProductData; - /* CPU */ - unsigned short MaxNumCpus; /* Max CPUs in this system */ - unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ - /* that there are unpopulated or */ - /* otherwise unusable cpu locations */ - PPC_CPU Cpus[MAX_CPUS]; - /* Memory */ - unsigned long TotalMemory; /* Total amount of memory installed */ - unsigned long GoodMemory; /* Total amount of good memory */ - unsigned long ActualNumMemSegs; - MEM_MAP Segs[MAX_MEM_SEGS]; - unsigned long ActualNumMemories; - PPC_MEM Memories[MAX_MEMS]; - /* Devices */ - unsigned long ActualNumDevices; - PPC_DEVICE Devices[MAX_DEVICES]; - unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; - } RESIDUAL; - - -extern RESIDUAL *res; -extern void print_residual_device_info(void); -extern PPC_DEVICE *residual_find_device(unsigned long BusMask, - unsigned char * DevID, int BaseType, - int SubType, int Interface, int n); -extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, - int n); -extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, - unsigned packet_type, - int n); -extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, - unsigned packet_type, - int n); -#endif /* __ASSEMBLY__ */ -#endif /* ndef _RESIDUAL_ */ diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h deleted file mode 100644 index 715c868..0000000 --- a/include/asm-ppc/sigcontext.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _ASM_PPC_SIGCONTEXT_H -#define _ASM_PPC_SIGCONTEXT_H - -#include - - -struct sigcontext_struct { - unsigned long _unused[4]; - int signal; - unsigned long handler; - unsigned long oldmask; - struct pt_regs *regs; -}; - -#endif diff --git a/include/asm-ppc/signal.h b/include/asm-ppc/signal.h deleted file mode 100644 index b11a28e..0000000 --- a/include/asm-ppc/signal.h +++ /dev/null @@ -1,154 +0,0 @@ -#ifndef _ASMPPC_SIGNAL_H -#define _ASMPPC_SIGNAL_H - -#include - -/* Avoid too many header ordering problems. */ -struct siginfo; - -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ - -#define _NSIG 64 -#define _NSIG_BPW 32 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) - -/* - * SA_FLAGS values: - * - * SA_ONSTACK is not currently supported, but will allow sigaltstack(2). - * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 /* not supported yet */ -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND -#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */ - -#define SA_RESTORER 0x04000000 - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ - -struct old_sigaction { - __sighandler_t sa_handler; - old_sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -struct sigaction { - __sighandler_t sa_handler; - unsigned long sa_flags; - void (*sa_restorer)(void); - sigset_t sa_mask; /* mask last for extensibility */ -}; - -struct k_sigaction { - struct sigaction sa; -}; - -typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - -#ifdef __KERNEL__ -#include - -#endif - -#endif diff --git a/include/asm-ppc/status_led.h b/include/asm-ppc/status_led.h deleted file mode 100644 index 0375709..0000000 --- a/include/asm-ppc/status_led.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * asm/status_led.h - * - * MPC8xx/MPC8260/MPC5xx based status led support functions - */ - -#ifndef __ASM_STATUS_LED_H__ -#define __ASM_STATUS_LED_H__ - -/* if not overriden */ -#ifndef CONFIG_BOARD_SPECIFIC_LED -# if defined(CONFIG_8xx) -# include -# elif defined(CONFIG_8260) -# include -# elif defined(CONFIG_5xx) -# include -# else -# error CPU specific Status LED header file missing. -#endif - -/* led_id_t is unsigned long mask */ -typedef unsigned long led_id_t; - -static inline void __led_init (led_id_t mask, int state) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#ifdef STATUS_LED_PAR - immr->STATUS_LED_PAR &= ~mask; -#endif -#ifdef STATUS_LED_ODR - immr->STATUS_LED_ODR &= ~mask; -#endif - -#if (STATUS_LED_ACTIVE == 0) - if (state == STATUS_LED_ON) - immr->STATUS_LED_DAT &= ~mask; - else - immr->STATUS_LED_DAT |= mask; -#else - if (state == STATUS_LED_ON) - immr->STATUS_LED_DAT |= mask; - else - immr->STATUS_LED_DAT &= ~mask; -#endif -#ifdef STATUS_LED_DIR - immr->STATUS_LED_DIR |= mask; -#endif -} - -static inline void __led_toggle (led_id_t mask) -{ - ((immap_t *) CONFIG_SYS_IMMR)->STATUS_LED_DAT ^= mask; -} - -static inline void __led_set (led_id_t mask, int state) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#if (STATUS_LED_ACTIVE == 0) - if (state == STATUS_LED_ON) - immr->STATUS_LED_DAT &= ~mask; - else - immr->STATUS_LED_DAT |= mask; -#else - if (state == STATUS_LED_ON) - immr->STATUS_LED_DAT |= mask; - else - immr->STATUS_LED_DAT &= ~mask; -#endif - -} - -#endif - -#endif /* __ASM_STATUS_LED_H__ */ diff --git a/include/asm-ppc/string.h b/include/asm-ppc/string.h deleted file mode 100644 index d912a6b..0000000 --- a/include/asm-ppc/string.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef _PPC_STRING_H_ -#define _PPC_STRING_H_ - -#define __HAVE_ARCH_STRCPY -#define __HAVE_ARCH_STRNCPY -#define __HAVE_ARCH_STRLEN -#define __HAVE_ARCH_STRCMP -#define __HAVE_ARCH_STRCAT -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_BCOPY -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMMOVE -#define __HAVE_ARCH_MEMCMP -#define __HAVE_ARCH_MEMCHR - -extern int strcasecmp(const char *, const char *); -extern int strncasecmp(const char *, const char *, int); -extern char * strcpy(char *,const char *); -extern char * strncpy(char *,const char *, __kernel_size_t); -extern __kernel_size_t strlen(const char *); -extern int strcmp(const char *,const char *); -extern char * strcat(char *, const char *); -extern void * memset(void *,int,__kernel_size_t); -extern void * memcpy(void *,const void *,__kernel_size_t); -extern void * memmove(void *,const void *,__kernel_size_t); -extern int memcmp(const void *,const void *,__kernel_size_t); -extern void * memchr(const void *,int,__kernel_size_t); - -#endif diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h deleted file mode 100644 index b27a6b7..0000000 --- a/include/asm-ppc/types.h +++ /dev/null @@ -1,58 +0,0 @@ -#ifndef _PPC_TYPES_H -#define _PPC_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -typedef struct { - __u32 u[4]; -} __attribute__((aligned(16))) vector128; - -#ifdef __KERNEL__ -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* DMA addresses are 32-bits wide */ -typedef u32 dma_addr_t; - -#ifdef CONFIG_PHYS_64BIT -typedef unsigned long long phys_addr_t; -typedef unsigned long long phys_size_t; -#else -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; -#endif - -#endif /* __KERNEL__ */ -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h deleted file mode 100644 index ea2d22d..0000000 --- a/include/asm-ppc/u-boot.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2000 - 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef __U_BOOT_H__ -#define __U_BOOT_H__ - -/* - * Board information passed to Linux kernel from U-Boot - * - * include/asm-ppc/u-boot.h - */ - -#ifndef __ASSEMBLY__ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ - || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) - unsigned long bi_immr_base; /* base of IMMR register */ -#endif -#if defined(CONFIG_MPC5xxx) - unsigned long bi_mbar_base; /* base of internal registers */ -#endif -#if defined(CONFIG_MPC83xx) - unsigned long bi_immrbar; -#endif -#if defined(CONFIG_MPC8220) - unsigned long bi_mbar_base; /* base of internal registers */ - unsigned long bi_inpfreq; /* Input Freq, In MHz */ - unsigned long bi_pcifreq; /* PCI Freq, in MHz */ - unsigned long bi_pevfreq; /* PEV Freq, in MHz */ - unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */ - unsigned long bi_vcofreq; /* VCO Freq, in MHz */ -#endif - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ -#if defined(CONFIG_CPM2) - unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ - unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ - unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ - unsigned long bi_vco; /* VCO Out from PLL, in MHz */ -#endif -#if defined(CONFIG_MPC512X) - unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ -#endif /* CONFIG_MPC512X */ -#if defined(CONFIG_MPC5xxx) - unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ - unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ -#endif - unsigned long bi_baudrate; /* Console Baudrate */ -#if defined(CONFIG_405) || \ - defined(CONFIG_405GP) || \ - defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || \ - defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || \ - defined(CONFIG_440) - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ - unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ - unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ - unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ -#endif -#if defined(CONFIG_HYMOD) - hymod_conf_t bi_hymod_conf; /* hymod configuration information */ -#endif - -#ifdef CONFIG_HAS_ETH1 - unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH2 - unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH3 - unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH4 - unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH5 - unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ -#endif - -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ - defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) - unsigned int bi_opbfreq; /* OPB clock in Hz */ - int bi_iic_fast[2]; /* Use fast i2c mode */ -#endif -#if defined(CONFIG_NX823) - unsigned char bi_sernum[8]; -#endif -#if defined(CONFIG_4xx) -#if defined(CONFIG_440GX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) - int bi_phynum[4]; /* Determines phy mapping */ - int bi_phymode[4]; /* Determines phy mode */ -#elif defined(CONFIG_405EP) || defined(CONFIG_440) - int bi_phynum[2]; /* Determines phy mapping */ - int bi_phymode[2]; /* Determines phy mode */ -#else - int bi_phynum[1]; /* Determines phy mapping */ - int bi_phymode[1]; /* Determines phy mode */ -#endif -#endif /* defined(CONFIG_4xx) */ -} bd_t; - -#endif /* __ASSEMBLY__ */ -#endif /* __U_BOOT_H__ */ diff --git a/include/asm-ppc/unaligned.h b/include/asm-ppc/unaligned.h deleted file mode 100644 index 5f1b1e3..0000000 --- a/include/asm-ppc/unaligned.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _ASM_POWERPC_UNALIGNED_H -#define _ASM_POWERPC_UNALIGNED_H - -#ifdef __KERNEL__ - -/* - * The PowerPC can do unaligned accesses itself in big endian mode. - */ -#include -#include - -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#endif /* __KERNEL__ */ -#endif /* _ASM_POWERPC_UNALIGNED_H */ diff --git a/include/asm-ppc/xilinx_irq.h b/include/asm-ppc/xilinx_irq.h deleted file mode 100644 index 61171c2..0000000 --- a/include/asm-ppc/xilinx_irq.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . -*/ -#ifndef XILINX_IRQ_H -#define XILINX_IRQ_H - -#define intc XPAR_INTC_0_BASEADDR -#define ISR (intc + (0 * 4)) /* Interrupt Status Register */ -#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */ -#define IER (intc + (2 * 4)) /* Interrupt Enable Register */ -#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */ -#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */ -#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */ -#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */ -#define MER (intc + (7 * 4)) /* Master Enable Register */ - -#define IRQ_MASK(irq) (1 << (irq & 0x1f)) - -#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS - -#endif diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h deleted file mode 100644 index c57d628..0000000 --- a/include/asm-sh/bitops.h +++ /dev/null @@ -1,153 +0,0 @@ -#ifndef __ASM_SH_BITOPS_H -#define __ASM_SH_BITOPS_H - -#ifdef __KERNEL__ -#include -/* For __swab32 */ -#include - -static inline void set_bit(int nr, volatile void * addr) -{ - int mask; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - *a |= mask; - local_irq_restore(flags); -} - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() -static inline void clear_bit(int nr, volatile void * addr) -{ - int mask; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - *a &= ~mask; - local_irq_restore(flags); -} - -static inline void change_bit(int nr, volatile void * addr) -{ - int mask; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - *a ^= mask; - local_irq_restore(flags); -} - -static inline int test_and_set_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - retval = (mask & *a) != 0; - *a |= mask; - local_irq_restore(flags); - - return retval; -} - -static inline int test_and_clear_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - retval = (mask & *a) != 0; - *a &= ~mask; - local_irq_restore(flags); - - return retval; -} - -static inline int test_and_change_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - retval = (mask & *a) != 0; - *a ^= mask; - local_irq_restore(flags); - - return retval; -} - -static inline unsigned long ffz(unsigned long word) -{ - unsigned long result; - - __asm__("1:\n\t" - "shlr %1\n\t" - "bt/s 1b\n\t" - " add #1, %0" - : "=r" (result), "=r" (word) - : "0" (~0L), "1" (word) - : "t"); - return result; -} - -/** - * ffs - find first bit in word. - * @word: The word to search - * - * Undefined if no bit exists, so code should check against 0 first. - */ -static inline int ffs (int x) -{ - int r = 1; - - if (!x) - return 0; - if (!(x & 0xffff)) { - x >>= 16; - r += 16; - } - if (!(x & 0xff)) { - x >>= 8; - r += 8; - } - if (!(x & 0xf)) { - x >>= 4; - r += 4; - } - if (!(x & 3)) { - x >>= 2; - r += 2; - } - if (!(x & 1)) { - x >>= 1; - r += 1; - } - return r; -} -#define PLATFORM_FFS - -#endif /* __KERNEL__ */ - -#endif /* __ASM_SH_BITOPS_H */ diff --git a/include/asm-sh/byteorder.h b/include/asm-sh/byteorder.h deleted file mode 100644 index 25626a0..0000000 --- a/include/asm-sh/byteorder.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_SH_BYTEORDER_H_ -#define __ASM_SH_BYTEORDER_H_ - -#include -#include - -#ifdef __LITTLE_ENDIAN__ -#include -#else -#include -#endif - -#endif diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h deleted file mode 100644 index 2cfc0a7..0000000 --- a/include/asm-sh/cache.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __ASM_SH_CACHE_H -#define __ASM_SH_CACHE_H - -#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) - -int cache_control(unsigned int cmd); - -#define L1_CACHE_BYTES 32 -struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct *)(x)) - -void dcache_wback_range(u32 start, u32 end) -{ - u32 v; - - start &= ~(L1_CACHE_BYTES - 1); - for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbwb %0" : /* no output */ - : "m" (__m(v))); - } -} - -void dcache_invalid_range(u32 start, u32 end) -{ - u32 v; - - start &= ~(L1_CACHE_BYTES - 1); - for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbi %0" : /* no output */ - : "m" (__m(v))); - } -} -#endif /* CONFIG_SH4 || CONFIG_SH4A */ - -#endif /* __ASM_SH_CACHE_H */ diff --git a/include/asm-sh/clk.h b/include/asm-sh/clk.h deleted file mode 100644 index 9cac6b0..0000000 --- a/include/asm-sh/clk.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_SH_CLK_H__ -#define __ASM_SH_CLK_H__ - -static inline unsigned long get_peripheral_clk_rate(void) -{ - return CONFIG_SYS_CLK_FREQ; -} - -static inline unsigned long get_tmu0_clk_rate(void) -{ - return CONFIG_SYS_CLK_FREQ; -} - -#endif /* __ASM_SH_CLK_H__ */ diff --git a/include/asm-sh/config.h b/include/asm-sh/config.h deleted file mode 100644 index 978cc92..0000000 --- a/include/asm-sh/config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -/* Relocation to SDRAM works on all sh boards */ -#define CONFIG_RELOC_FIXUP_WORKS - -#endif diff --git a/include/asm-sh/cpu_sh2.h b/include/asm-sh/cpu_sh2.h deleted file mode 100644 index 8bc9bc6..0000000 --- a/include/asm-sh/cpu_sh2.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH2_H_ -#define _ASM_CPU_SH2_H_ - -/* cache control */ -#define CCR_CACHE_STOP 0x00000008 -#define CCR_CACHE_ENABLE 0x00000005 -#define CCR_CACHE_ICI 0x00000008 - -#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 -#define CACHE_OC_WAY_SHIFT 13 -#define CACHE_OC_NUM_ENTRIES 256 -#define CACHE_OC_ENTRY_SHIFT 4 - -#if defined(CONFIG_CPU_SH7203) -# include -#else -# error "Unknown SH2 variant" -#endif - -#endif /* _ASM_CPU_SH2_H_ */ diff --git a/include/asm-sh/cpu_sh3.h b/include/asm-sh/cpu_sh3.h deleted file mode 100644 index 6db38a2..0000000 --- a/include/asm-sh/cpu_sh3.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2007 Nobuhiro Iwamatsu - * (C) Copyright 2007 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH3_H_ -#define _ASM_CPU_SH3_H_ - -/* cache control */ -#define CCR_CACHE_STOP 0x00000008 -#define CCR_CACHE_ENABLE 0x00000005 -#define CCR_CACHE_ICI 0x00000008 - -#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 -#define CACHE_OC_WAY_SHIFT 13 -#define CACHE_OC_NUM_ENTRIES 256 -#define CACHE_OC_ENTRY_SHIFT 4 - -#if defined(CONFIG_CPU_SH7710) -#include -#elif defined(CONFIG_CPU_SH7720) -#include -#else -#error "Unknown SH3 variant" -#endif - -#endif /* _ASM_CPU_SH3_H_ */ diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h deleted file mode 100644 index fdcebd6..0000000 --- a/include/asm-sh/cpu_sh4.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2007,2008 Nobuhiro Iwamatsu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH4_H_ -#define _ASM_CPU_SH4_H_ - -/* cache control */ -#define CCR_CACHE_STOP 0x00000808 -#define CCR_CACHE_ENABLE 0x00000101 -#define CCR_CACHE_ICI 0x00000800 - -#define CACHE_OC_ADDRESS_ARRAY 0xf4000000 - -#if defined (CONFIG_CPU_SH7750) || \ - defined(CONFIG_CPU_SH7751) -#define CACHE_OC_WAY_SHIFT 14 -#define CACHE_OC_NUM_ENTRIES 512 -#else -#define CACHE_OC_WAY_SHIFT 13 -#define CACHE_OC_NUM_ENTRIES 256 -#endif -#define CACHE_OC_ENTRY_SHIFT 5 - -#if defined (CONFIG_CPU_SH7750) || \ - defined(CONFIG_CPU_SH7751) -# include -#elif defined (CONFIG_CPU_SH7722) -# include -#elif defined (CONFIG_CPU_SH7723) -# include -#elif defined (CONFIG_CPU_SH7763) -# include -#elif defined (CONFIG_CPU_SH7780) -# include -#elif defined (CONFIG_CPU_SH7785) -# include -#else -# error "Unknown SH4 variant" -#endif - -#if defined(CONFIG_SH_32BIT) -#define PMB_ADDR_ARRAY 0xf6100000 -#define PMB_ADDR_ENTRY 8 -#define PMB_VPN 24 - -#define PMB_DATA_ARRAY 0xf7100000 -#define PMB_DATA_ENTRY 8 -#define PMB_PPN 24 -#define PMB_UB 9 /* Buffered write */ -#define PMB_V 8 /* Valid */ -#define PMB_SZ1 7 /* Page size (upper bit) */ -#define PMB_SZ0 4 /* Page size (lower bit) */ -#define PMB_C 3 /* Cacheability */ -#define PMB_WT 0 /* Write-through */ - -#define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY)) -#define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY)) -#define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN)) -#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \ - ((ppn << PMB_PPN) | (ub << PMB_UB) | \ - (v << PMB_V) | (sz1 << PMB_SZ1) | \ - (sz0 << PMB_SZ0) | (c << PMB_C) | \ - (wt << PMB_WT)) -#endif - -#endif /* _ASM_CPU_SH4_H_ */ diff --git a/include/asm-sh/cpu_sh7203.h b/include/asm-sh/cpu_sh7203.h deleted file mode 100644 index 77dcac4..0000000 --- a/include/asm-sh/cpu_sh7203.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _ASM_CPU_SH7203_H_ -#define _ASM_CPU_SH7203_H_ - -/* Cache */ -#define CCR1 0xFFFC1000 -#define CCR CCR1 - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PETCR 0xA4050106 - -/* Port Data Registers */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 - -/* BSC */ - -/* SDRAM controller */ - -/* SCIF */ -#define SCSMR_0 0xFFFE8000 -#define SCIF0_BASE SCSMR_0 - -/* Timer(CMT) */ -#define CMSTR 0xFFFEC000 -#define CMCSR_0 0xFFFEC002 -#define CMCNT_0 0xFFFEC004 -#define CMCOR_0 0xFFFEC006 -#define CMCSR_1 0xFFFEC008 -#define CMCNT_1 0xFFFEC00A -#define CMCOR_1 0xFFFEC00C - -/* On chip oscillator circuits */ -#define FRQCR 0xA415FF80 -#define WTCNT 0xA415FF84 -#define WTCSR 0xA415FF86 - -#endif /* _ASM_CPU_SH7203_H_ */ diff --git a/include/asm-sh/cpu_sh7710.h b/include/asm-sh/cpu_sh7710.h deleted file mode 100644 index e223f1c..0000000 --- a/include/asm-sh/cpu_sh7710.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef _ASM_CPU_SH7710_H_ -#define _ASM_CPU_SH7710_H_ - -#define CACHE_OC_NUM_WAYS 4 -#define CCR_CACHE_INIT 0x0000000D - -/* MMU and Cache control */ -#define MMUCR 0xFFFFFFE0 -#define CCR 0xFFFFFFEC - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PETCR 0xA4050106 - -/* Port Data Registers */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 - -/* BSC */ -#define CMNCR 0xA4FD0000 -#define CS0BCR 0xA4FD0004 -#define CS2BCR 0xA4FD0008 -#define CS3BCR 0xA4FD000C -#define CS4BCR 0xA4FD0010 -#define CS5ABCR 0xA4FD0014 -#define CS5BBCR 0xA4FD0018 -#define CS6ABCR 0xA4FD001C -#define CS6BBCR 0xA4FD0020 -#define CS0WCR 0xA4FD0024 -#define CS2WCR 0xA4FD0028 -#define CS3WCR 0xA4FD002C -#define CS4WCR 0xA4FD0030 -#define CS5AWCR 0xA4FD0034 -#define CS5BWCR 0xA4FD0038 -#define CS6AWCR 0xA4FD003C -#define CS6BWCR 0xA4FD0040 - -/* SDRAM controller */ -#define SDCR 0xA4FD0044 -#define RTCSR 0xA4FD0048 -#define RTCNT 0xA4FD004C -#define RTCOR 0xA4FD0050 - -/* SCIF */ -#define SCSMR_0 0xA4400000 -#define SCIF0_BASE SCSMR_0 -#define SCSMR_0 0xA4410000 -#define SCIF1_BASE SCSMR_1 - -/* Timer */ -#define TSTR0 0xA412FE92 -#define TSTR TSTR0 -#define TCNT0 0xa412FE98 -#define TCR0 0xa412FE9C - -/* On chip oscillator circuits */ -#define FRQCR 0xA415FF80 -#define WTCNT 0xA415FF84 -#define WTCSR 0xA415FF86 - -#endif /* _ASM_CPU_SH7710_H_ */ diff --git a/include/asm-sh/cpu_sh7720.h b/include/asm-sh/cpu_sh7720.h deleted file mode 100644 index 1b393b8..0000000 --- a/include/asm-sh/cpu_sh7720.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright 2007 (C) - * Yoshihiro Shimoda - * - * Copyright 2008 (C) - * Mark Jonas - * - * SH7720 Internal I/O register - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH7720_H_ -#define _ASM_CPU_SH7720_H_ - -#define CACHE_OC_NUM_WAYS 4 -#define CCR_CACHE_INIT 0x0000000B - -/* EXP */ -#define TRA 0xFFFFFFD0 -#define EXPEVT 0xFFFFFFD4 -#define INTEVT 0xFFFFFFD8 - -/* MMU */ -#define MMUCR 0xFFFFFFE0 -#define PTEH 0xFFFFFFF0 -#define PTEL 0xFFFFFFF4 -#define TTB 0xFFFFFFF8 - -/* CACHE */ -#define CCR 0xFFFFFFEC - -/* INTC */ -#define IPRF 0xA4080000 -#define IPRG 0xA4080002 -#define IPRH 0xA4080004 -#define IPRI 0xA4080006 -#define IPRJ 0xA4080008 -#define IRR5 0xA4080020 -#define IRR6 0xA4080022 -#define IRR7 0xA4080024 -#define IRR8 0xA4080026 -#define IRR9 0xA4080028 -#define IRR0 0xA4140004 -#define IRR1 0xA4140006 -#define IRR2 0xA4140008 -#define IRR3 0xA414000A -#define IRR4 0xA414000C -#define ICR1 0xA4140010 -#define ICR2 0xA4140012 -#define PINTER 0xA4140014 -#define IPRC 0xA4140016 -#define IPRD 0xA4140018 -#define IPRE 0xA414001A -#define ICR0 0xA414FEE0 -#define IPRA 0xA414FEE2 -#define IPRB 0xA414FEE4 - -/* BSC */ -#define BSC_BASE 0xA4FD0000 -#define CMNCR (BSC_BASE + 0x00) -#define CS0BCR (BSC_BASE + 0x04) -#define CS2BCR (BSC_BASE + 0x08) -#define CS3BCR (BSC_BASE + 0x0C) -#define CS4BCR (BSC_BASE + 0x10) -#define CS5ABCR (BSC_BASE + 0x14) -#define CS5BBCR (BSC_BASE + 0x18) -#define CS6ABCR (BSC_BASE + 0x1C) -#define CS6BBCR (BSC_BASE + 0x20) -#define CS0WCR (BSC_BASE + 0x24) -#define CS2WCR (BSC_BASE + 0x28) -#define CS3WCR (BSC_BASE + 0x2C) -#define CS4WCR (BSC_BASE + 0x30) -#define CS5AWCR (BSC_BASE + 0x34) -#define CS5BWCR (BSC_BASE + 0x38) -#define CS6AWCR (BSC_BASE + 0x3C) -#define CS6BWCR (BSC_BASE + 0x40) -#define SDCR (BSC_BASE + 0x44) -#define RTCSR (BSC_BASE + 0x48) -#define RTCNR (BSC_BASE + 0x4C) -#define RTCOR (BSC_BASE + 0x50) -#define SDMR2 (BSC_BASE + 0x4000) -#define SDMR3 (BSC_BASE + 0x5000) - -/* DMAC */ - -/* CPG */ -#define UCLKCR 0xA40A0008 -#define FRQCR 0xA415FF80 - -/* LOW POWER MODE */ - -/* TMU */ -#define TMU_BASE 0xA412FE90 -#define TSTR (TMU_BASE + 0x02) -#define TCOR0 (TMU_BASE + 0x04) -#define TCNT0 (TMU_BASE + 0x08) -#define TCR0 (TMU_BASE + 0x0C) -#define TCOR1 (TMU_BASE + 0x10) -#define TCNT1 (TMU_BASE + 0x14) -#define TCR1 (TMU_BASE + 0x18) -#define TCOR2 (TMU_BASE + 0x1C) -#define TCNT2 (TMU_BASE + 0x20) -#define TCR2 (TMU_BASE + 0x24) - -/* TPU */ -#define TPU_BASE 0xA4480000 -#define TPU_TSTR (TPU_BASE + 0x00) -#define TPU_TCR0 (TPU_BASE + 0x10) -#define TPU_TMDR0 (TPU_BASE + 0x14) -#define TPU_TIOR0 (TPU_BASE + 0x18) -#define TPU_TIER0 (TPU_BASE + 0x1C) -#define TPU_TSR0 (TPU_BASE + 0x20) -#define TPU_TCNT0 (TPU_BASE + 0x24) -#define TPU_TGRA0 (TPU_BASE + 0x28) -#define TPU_TGRB0 (TPU_BASE + 0x2C) -#define TPU_TGRC0 (TPU_BASE + 0x30) -#define TPU_TGRD0 (TPU_BASE + 0x34) -#define TPU_TCR1 (TPU_BASE + 0x50) -#define TPU_TMDR1 (TPU_BASE + 0x54) -#define TPU_TIOR1 (TPU_BASE + 0x58) -#define TPU_TIER1 (TPU_BASE + 0x5C) -#define TPU_TSR1 (TPU_BASE + 0x60) -#define TPU_TCNT1 (TPU_BASE + 0x64) -#define TPU_TGRA1 (TPU_BASE + 0x68) -#define TPU_TGRB1 (TPU_BASE + 0x6C) -#define TPU_TGRC1 (TPU_BASE + 0x70) -#define TPU_TGRD1 (TPU_BASE + 0x74) -#define TPU_TCR2 (TPU_BASE + 0x90) -#define TPU_TMDR2 (TPU_BASE + 0x94) -#define TPU_TIOR2 (TPU_BASE + 0x98) -#define TPU_TIER2 (TPU_BASE + 0x9C) -#define TPU_TSR2 (TPU_BASE + 0xB0) -#define TPU_TCNT2 (TPU_BASE + 0xB4) -#define TPU_TGRA2 (TPU_BASE + 0xB8) -#define TPU_TGRB2 (TPU_BASE + 0xBC) -#define TPU_TGRC2 (TPU_BASE + 0xC0) -#define TPU_TGRD2 (TPU_BASE + 0xC4) -#define TPU_TCR3 (TPU_BASE + 0xD0) -#define TPU_TMDR3 (TPU_BASE + 0xD4) -#define TPU_TIOR3 (TPU_BASE + 0xD8) -#define TPU_TIER3 (TPU_BASE + 0xDC) -#define TPU_TSR3 (TPU_BASE + 0xE0) -#define TPU_TCNT3 (TPU_BASE + 0xE4) -#define TPU_TGRA3 (TPU_BASE + 0xE8) -#define TPU_TGRB3 (TPU_BASE + 0xEC) -#define TPU_TGRC3 (TPU_BASE + 0xF0) -#define TPU_TGRD3 (TPU_BASE + 0xF4) - -/* CMT */ - -/* SIOF */ - -/* SCIF */ -#define SCIF0_BASE 0xA4430000 - -/* SIM */ - -/* IrDA */ - -/* IIC */ - -/* LCDC */ - -/* USBF */ - -/* MMCIF */ - -/* PFC */ -#define PFC_BASE 0xA4050100 -#define PACR (PFC_BASE + 0x00) -#define PBCR (PFC_BASE + 0x02) -#define PCCR (PFC_BASE + 0x04) -#define PDCR (PFC_BASE + 0x06) -#define PECR (PFC_BASE + 0x08) -#define PFCR (PFC_BASE + 0x0A) -#define PGCR (PFC_BASE + 0x0C) -#define PHCR (PFC_BASE + 0x0E) -#define PJCR (PFC_BASE + 0x10) -#define PKCR (PFC_BASE + 0x12) -#define PLCR (PFC_BASE + 0x14) -#define PMCR (PFC_BASE + 0x16) -#define PPCR (PFC_BASE + 0x18) -#define PRCR (PFC_BASE + 0x1A) -#define PSCR (PFC_BASE + 0x1C) -#define PTCR (PFC_BASE + 0x1E) -#define PUCR (PFC_BASE + 0x20) -#define PVCR (PFC_BASE + 0x22) -#define PSELA (PFC_BASE + 0x24) -#define PSELB (PFC_BASE + 0x26) -#define PSELC (PFC_BASE + 0x28) -#define PSELD (PFC_BASE + 0x2A) - -/* I/O Port */ -#define PORT_BASE 0xA4050100 -#define PADR (PORT_BASE + 0x40) -#define PBDR (PORT_BASE + 0x42) -#define PCDR (PORT_BASE + 0x44) -#define PDDR (PORT_BASE + 0x46) -#define PEDR (PORT_BASE + 0x48) -#define PFDR (PORT_BASE + 0x4A) -#define PGDR (PORT_BASE + 0x4C) -#define PHDR (PORT_BASE + 0x4E) -#define PJDR (PORT_BASE + 0x50) -#define PKDR (PORT_BASE + 0x52) -#define PLDR (PORT_BASE + 0x54) -#define PMDR (PORT_BASE + 0x56) -#define PPDR (PORT_BASE + 0x58) -#define PRDR (PORT_BASE + 0x5A) -#define PSDR (PORT_BASE + 0x5C) -#define PTDR (PORT_BASE + 0x5E) -#define PUDR (PORT_BASE + 0x60) -#define PVDR (PORT_BASE + 0x62) - -/* H-UDI */ - -#endif /* _ASM_CPU_SH7720_H_ */ diff --git a/include/asm-sh/cpu_sh7722.h b/include/asm-sh/cpu_sh7722.h deleted file mode 100644 index 0975b78..0000000 --- a/include/asm-sh/cpu_sh7722.h +++ /dev/null @@ -1,1337 +0,0 @@ -/* - * (C) Copyright 2007 Nobuhiro Iwamatsu - * - * SH7722 Internal I/O register - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH7722_H_ -#define _ASM_CPU_SH7722_H_ - -#define CACHE_OC_NUM_WAYS 4 -#define CCR_CACHE_INIT 0x0000090d - -/* EXP */ -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 - -/* MMU */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define PASCR 0xFF000070 -#define IRMCR 0xFF000078 - -/* CACHE */ -#define CCR 0xFF00001C -#define RAMCR 0xFF000074 - -/* XY MEMORY */ -#define XSA 0xFF000050 -#define YSA 0xFF000054 -#define XDA 0xFF000058 -#define YDA 0xFF00005C -#define XPR 0xFF000060 -#define YPR 0xFF000064 -#define XEA 0xFF000068 -#define YEA 0xFF00006C - -/* INTC */ -#define ICR0 0xA4140000 -#define ICR1 0xA414001C -#define INTPRI0 0xA4140010 -#define INTREQ0 0xA4140024 -#define INTMSK0 0xA4140044 -#define INTMSKCLR0 0xA4140064 -#define NMIFCR 0xA41400C0 -#define USERIMASK 0xA4700000 -#define IPRA 0xA4080000 -#define IPRB 0xA4080004 -#define IPRC 0xA4080008 -#define IPRD 0xA408000C -#define IPRE 0xA4080010 -#define IPRF 0xA4080014 -#define IPRG 0xA4080018 -#define IPRH 0xA408001C -#define IPRI 0xA4080020 -#define IPRJ 0xA4080024 -#define IPRK 0xA4080028 -#define IPRL 0xA408002C -#define IMR0 0xA4080080 -#define IMR1 0xA4080084 -#define IMR2 0xA4080088 -#define IMR3 0xA408008C -#define IMR4 0xA4080090 -#define IMR5 0xA4080094 -#define IMR6 0xA4080098 -#define IMR7 0xA408009C -#define IMR8 0xA40800A0 -#define IMR9 0xA40800A4 -#define IMR10 0xA40800A8 -#define IMR11 0xA40800AC -#define IMCR0 0xA40800C0 -#define IMCR1 0xA40800C4 -#define IMCR2 0xA40800C8 -#define IMCR3 0xA40800CC -#define IMCR4 0xA40800D0 -#define IMCR5 0xA40800D4 -#define IMCR6 0xA40800D8 -#define IMCR7 0xA40800DC -#define IMCR8 0xA40800E0 -#define IMCR9 0xA40800E4 -#define IMCR10 0xA40800E8 -#define IMCR11 0xA40800EC -#define MFI_IPRA 0xA40B0000 -#define MFI_IPRB 0xA40B0004 -#define MFI_IPRC 0xA40B0008 -#define MFI_IPRD 0xA40B000C -#define MFI_IPRE 0xA40B0010 -#define MFI_IPRF 0xA40B0014 -#define MFI_IPRG 0xA40B0018 -#define MFI_IPRH 0xA40B001C -#define MFI_IPRI 0xA40B0020 -#define MFI_IPRJ 0xA40B0024 -#define MFI_IPRK 0xA40B0028 -#define MFI_IPRL 0xA40B002C -#define MFI_IMR0 0xA40B0080 -#define MFI_IMR1 0xA40B0084 -#define MFI_IMR2 0xA40B0088 -#define MFI_IMR3 0xA40B008C -#define MFI_IMR4 0xA40B0090 -#define MFI_IMR5 0xA40B0094 -#define MFI_IMR6 0xA40B0098 -#define MFI_IMR7 0xA40B009C -#define MFI_IMR8 0xA40B00A0 -#define MFI_IMR9 0xA40B00A4 -#define MFI_IMR10 0xA40B00A8 -#define MFI_IMR11 0xA40B00AC -#define MFI_IMCR0 0xA40B00C0 -#define MFI_IMCR1 0xA40B00C4 -#define MFI_IMCR2 0xA40B00C8 -#define MFI_IMCR3 0xA40B00CC -#define MFI_IMCR4 0xA40B00D0 -#define MFI_IMCR5 0xA40B00D4 -#define MFI_IMCR6 0xA40B00D8 -#define MFI_IMCR7 0xA40B00DC -#define MFI_IMCR8 0xA40B00E0 -#define MFI_IMCR9 0xA40B00E4 -#define MFI_IMCR10 0xA40B00E8 -#define MFI_IMCR11 0xA40B00EC - -/* BSC */ -#define CMNCR 0xFEC10000 -#define CS0BCR 0xFEC10004 -#define CS2BCR 0xFEC10008 -#define CS4BCR 0xFEC10010 -#define CS5ABCR 0xFEC10014 -#define CS5BBCR 0xFEC10018 -#define CS6ABCR 0xFEC1001C -#define CS6BBCR 0xFEC10020 -#define CS0WCR 0xFEC10024 -#define CS2WCR 0xFEC10028 -#define CS4WCR 0xFEC10030 -#define CS5AWCR 0xFEC10034 -#define CS5BWCR 0xFEC10038 -#define CS6AWCR 0xFEC1003C -#define CS6BWCR 0xFEC10040 -#define RBWTCNT 0xFEC10054 - -/* SBSC */ -#define SBSC_SDCR 0xFE400008 -#define SBSC_SDWCR 0xFE40000C -#define SBSC_SDPCR 0xFE400010 -#define SBSC_RTCSR 0xFE400014 -#define SBSC_RTCNT 0xFE400018 -#define SBSC_RTCOR 0xFE40001C -#define SBSC_RFCR 0xFE400020 - -/* DMAC */ -#define SAR_0 0xFE008020 -#define DAR_0 0xFE008024 -#define TCR_0 0xFE008028 -#define CHCR_0 0xFE00802C -#define SAR_1 0xFE008030 -#define DAR_1 0xFE008034 -#define TCR_1 0xFE008038 -#define CHCR_1 0xFE00803C -#define SAR_2 0xFE008040 -#define DAR_2 0xFE008044 -#define TCR_2 0xFE008048 -#define CHCR_2 0xFE00804C -#define SAR_3 0xFE008050 -#define DAR_3 0xFE008054 -#define TCR_3 0xFE008058 -#define CHCR_3 0xFE00805C -#define SAR_4 0xFE008070 -#define DAR_4 0xFE008074 -#define TCR_4 0xFE008078 -#define CHCR_4 0xFE00807C -#define SAR_5 0xFE008080 -#define DAR_5 0xFE008084 -#define TCR_5 0xFE008088 -#define CHCR_5 0xFE00808C -#define SARB_0 0xFE008120 -#define DARB_0 0xFE008124 -#define TCRB_0 0xFE008128 -#define SARB_1 0xFE008130 -#define DARB_1 0xFE008134 -#define TCRB_1 0xFE008138 -#define SARB_2 0xFE008140 -#define DARB_2 0xFE008144 -#define TCRB_2 0xFE008148 -#define SARB_3 0xFE008150 -#define DARB_3 0xFE008154 -#define TCRB_3 0xFE008158 -#define DMAOR 0xFE008060 -#define DMARS_0 0xFE009000 -#define DMARS_1 0xFE009004 -#define DMARS_2 0xFE009008 - -/* CPG */ -#define FRQCR 0xA4150000 -#define VCLKCR 0xA4150004 -#define SCLKACR 0xA4150008 -#define SCLKBCR 0xA415000C -#define PLLCR 0xA4150024 -#define DLLFRQ 0xA4150050 - -/* LOW POWER MODE */ -#define STBCR 0xA4150020 -#define MSTPCR0 0xA4150030 -#define MSTPCR1 0xA4150034 -#define MSTPCR2 0xA4150038 -#define BAR 0xA4150040 - -/* RWDT */ -#define RWTCNT 0xA4520000 -#define RWTCSR 0xA4520004 -#define WTCNT RWTCNT - - -/* TMU */ -#define TSTR 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 - -/* TPU */ -#define TPU_TSTR 0xA4C90000 -#define TPU_TCR0 0xA4C90010 -#define TPU_TMDR0 0xA4C90014 -#define TPU_TIOR0 0xA4C90018 -#define TPU_TIER0 0xA4C9001C -#define TPU_TSR0 0xA4C90020 -#define TPU_TCNT0 0xA4C90024 -#define TPU_TGR0A 0xA4C90028 -#define TPU_TGR0B 0xA4C9002C -#define TPU_TGR0C 0xA4C90030 -#define TPU_TGR0D 0xA4C90034 -#define TPU_TCR1 0xA4C90050 -#define TPU_TMDR1 0xA4C90054 -#define TPU_TIER1 0xA4C9005C -#define TPU_TSR1 0xA4C90060 -#define TPU_TCNT1 0xA4C90064 -#define TPU_TGR1A 0xA4C90068 -#define TPU_TGR1B 0xA4C9006C -#define TPU_TGR1C 0xA4C90070 -#define TPU_TGR1D 0xA4C90074 -#define TPU_TCR2 0xA4C90090 -#define TPU_TMDR2 0xA4C90094 -#define TPU_TIER2 0xA4C9009C -#define TPU_TSR2 0xA4C900A0 -#define TPU_TCNT2 0xA4C900A4 -#define TPU_TGR2A 0xA4C900A8 -#define TPU_TGR2B 0xA4C900AC -#define TPU_TGR2C 0xA4C900B0 -#define TPU_TGR2D 0xA4C900B4 -#define TPU_TCR3 0xA4C900D0 -#define TPU_TMDR3 0xA4C900D4 -#define TPU_TIER3 0xA4C900DC -#define TPU_TSR3 0xA4C900E0 -#define TPU_TCNT3 0xA4C900E4 -#define TPU_TGR3A 0xA4C900E8 -#define TPU_TGR3B 0xA4C900EC -#define TPU_TGR3C 0xA4C900F0 -#define TPU_TGR3D 0xA4C900F4 - -/* CMT */ -#define CMSTR 0xA44A0000 -#define CMCSR 0xA44A0060 -#define CMCNT 0xA44A0064 -#define CMCOR 0xA44A0068 - -/* SIO */ -#define SIOMDR 0xA4500000 -#define SIOCTR 0xA4500004 -#define SIOSTBCR0 0xA4500008 -#define SIOSTBCR1 0xA450000C -#define SIOTDR 0xA4500014 -#define SIORDR 0xA4500018 -#define SIOSTR 0xA450001C -#define SIOIER 0xA4500020 -#define SIOSCR 0xA4500024 - -/* SIOF */ -#define SIMDR0 0xA4410000 -#define SISCR0 0xA4410002 -#define SITDAR0 0xA4410004 -#define SIRDAR0 0xA4410006 -#define SICDAR0 0xA4410008 -#define SICTR0 0xA441000C -#define SIFCTR0 0xA4410010 -#define SISTR0 0xA4410014 -#define SIIER0 0xA4410016 -#define SITDR0 0xA4410020 -#define SIRDR0 0xA4410024 -#define SITCR0 0xA4410028 -#define SIRCR0 0xA441002C -#define SPICR0 0xA4410030 -#define SIMDR1 0xA4420000 -#define SISCR1 0xA4420002 -#define SITDAR1 0xA4420004 -#define SIRDAR1 0xA4420006 -#define SICDAR1 0xA4420008 -#define SICTR1 0xA442000C -#define SIFCTR1 0xA4420010 -#define SISTR1 0xA4420014 -#define SIIER1 0xA4420016 -#define SITDR1 0xA4420020 -#define SIRDR1 0xA4420024 -#define SITCR1 0xA4420028 -#define SIRCR1 0xA442002C -#define SPICR1 0xA4420030 - -/* SCIF */ -/* -#define SCSMR 0xFFE00000 -#define SCBRR 0xFFE00004 -#define SCSCR 0xFFE00008 -#define SCFTDR 0xFFE0000C -#define SCFSR 0xFFE00010 -#define SCFRDR 0xFFE00014 -#define SCFCR 0xFFE00018 -#define SCFDR 0xFFE0001C -#define SCLSR 0xFFE00024 -#define SCSMR1 0xFFE10000 -#define SCBRR1 0xFFE10004 -#define SCSCR1 0xFFE10008 -#define SCFTDR1 0xFFE1000C -#define SCFSR1 0xFFE10010 -#define SCFRDR1 0xFFE10014 -#define SCFCR1 0xFFE10018 -#define SCFDR1 0xFFE1001C -#define SCLSR1 0xFFE10024 -#define SCSMR2 0xFFE20000 -#define SCBRR2 0xFFE20004 -#define SCSCR2 0xFFE20008 -#define SCFTDR2 0xFFE2000C -#define SCFSR2 0xFFE20010 -#define SCFRDR2 0xFFE20014 -#define SCFCR2 0xFFE20018 -#define SCFDR2 0xFFE2001C -#define SCLSR2 0xFFE20024 -#define SCSMR3 0xFFE30000 -#define SCBRR3 0xFFE30004 -#define SCSCR3 0xFFE30008 -#define SCFTDR3 0xFFE3000C -#define SCFSR3 0xFFE30010 -#define SCFRDR3 0xFFE30014 -#define SCFCR3 0xFFE30018 -#define SCFDR3 0xFFE3001C -#define SCLSR3 0xFFE30024 -*/ -#define SCIF0_BASE 0xFFE00000 - -/* SIM */ -#define SIM_SCSMR 0xA4490000 -#define SIM_SCBRR 0xA4490002 -#define SIM_SCSCR 0xA4490004 -#define SIM_SCTDR 0xA4490006 -#define SIM_SCSSR 0xA4490008 -#define SIM_SCRDR 0xA449000A -#define SIM_SCSCMR 0xA449000C -#define SIM_SCSC2R 0xA449000E -#define SIM_SCWAIT 0xA4490010 -#define SIM_SCGRD 0xA4490012 -#define SIM_SCSMPL 0xA4490014 -#define SIM_SCDMAEN 0xA4490016 - -/* IrDA */ -#define IRIF_INIT1 0xA45D0012 -#define IRIF_INIT2 0xA45D0014 -#define IRIF_RINTCLR 0xA45D0016 -#define IRIF_TINTCLR 0xA45D0018 -#define IRIF_SIR0 0xA45D0020 -#define IRIF_SIR1 0xA45D0022 -#define IRIF_SIR2 0xA45D0024 -#define IRIF_SIR3 0xA45D0026 -#define IRIF_SIR_FRM 0xA45D0028 -#define IRIF_SIR_EOF 0xA45D002A -#define IRIF_SIR_FLG 0xA45D002C -#define IRIF_SIR_STS2 0xA45D002E -#define IRIF_UART0 0xA45D0030 -#define IRIF_UART1 0xA45D0032 -#define IRIF_UART2 0xA45D0034 -#define IRIF_UART3 0xA45D0036 -#define IRIF_UART4 0xA45D0038 -#define IRIF_UART5 0xA45D003A -#define IRIF_UART6 0xA45D003C -#define IRIF_UART7 0xA45D003E -#define IRIF_CRC0 0xA45D0040 -#define IRIF_CRC1 0xA45D0042 -#define IRIF_CRC2 0xA45D0044 -#define IRIF_CRC3 0xA45D0046 -#define IRIF_CRC4 0xA45D0048 - -/* IIC */ -#define ICDR0 0xA4470000 -#define ICCR0 0xA4470004 -#define ICSR0 0xA4470008 -#define ICIC0 0xA447000C -#define ICCL0 0xA4470010 -#define ICCH0 0xA4470014 -#define ICDR1 0xA4750000 -#define ICCR1 0xA4750004 -#define ICSR1 0xA4750008 -#define ICIC1 0xA475000C -#define ICCL1 0xA4750010 -#define ICCH1 0xA4750014 - -/* FLCTL */ -#define FLCMNCR 0xA4530000 -#define FLCMDCR 0xA4530004 -#define FLCMCDR 0xA4530008 -#define FLADR 0xA453000C -#define FLDATAR 0xA4530010 -#define FLDTCNTR 0xA4530014 -#define FLINTDMACR 0xA4530018 -#define FLBSYTMR 0xA453001C -#define FLBSYCNT 0xA4530020 -#define FLDTFIFO 0xA4530024 -#define FLECFIFO 0xA4530028 -#define FLTRCR 0xA453002C -#define FLADR2 0xA453003C - -/* MFI */ -#define MFIIDX 0xA4C10000 -#define MFIGSR 0xA4C10004 -#define MFISCR 0xA4C10008 -#define MFIMCR 0xA4C1000C -#define MFIIICR 0xA4C10010 -#define MFIEICR 0xA4C10014 -#define MFIADR 0xA4C10018 -#define MFIDATA 0xA4C1001C -#define MFIRCR 0xA4C10020 -#define MFIINTEVT 0xA4C1002C -#define MFIIMASK 0xA4C10030 -#define MFIBCR 0xA4C10040 -#define MFIADRW 0xA4C10044 -#define MFIADRR 0xA4C10048 -#define MFIDATAW 0xA4C1004C -#define MFIDATAR 0xA4C10050 -#define MFIMCRW 0xA4C10054 -#define MFIMCRR 0xA4C10058 -#define MFIDNRW 0xA4C1005C -#define MFIDNRR 0xA4C10060 -#define MFISIZEW 0xA4C10064 -#define MFISIZER 0xA4C10068 -#define MFIDEVCR 0xA4C10038 -#define MFISM4 0xA4C10080 - -/* VPU */ -#define VP4_CTRL 0xFE900000 -#define VP4_VOL_CTRL 0xFE900004 -#define VP4_IMAGE_SIZE 0xFE900008 -#define VP4_MB_NUM 0xFE90000C -#define VP4_DWY_ADDR 0xFE900010 -#define VP4_DWC_ADDR 0xFE900014 -#define VP4_D2WY_ADDR 0xFE900018 -#define VP4_D2WC_ADDR 0xFE90001C -#define VP4_DP1_ADDR 0xFE900020 -#define VP4_DP2_ADDR 0xFE900024 -#define VP4_STRS_ADDR 0xFE900028 -#define VP4_STRE_ADDR 0xFE90002C -#define VP4_VOP_CTRL 0xFE900030 -#define VP4_VOP_TIME 0xFE900034 -#define VP4_263_CTRL 0xFE900038 -#define VP4_264_CTRL 0xFE90003C -#define VP4_VLC_CTRL 0xFE900040 -#define VP4_ENDIAN 0xFE900044 -#define VP4_CMD 0xFE900048 -#define VP4_ME_TH1 0xFE90004C -#define VP4_ME_TH2 0xFE900050 -#define VP4_ME_COSTMB 0xFE900054 -#define VP4_ME_SKIP 0xFE900058 -#define VP4_ME_CTRL 0xFE90005C -#define VP4_MBRF_CTRL 0xFE900060 -#define VP4_MC_CTRL 0xFE900064 -#define VP4_PRED_CTRL 0xFE900068 -#define VP4_SLC_SIZE 0xFE90006C -#define VP4_VOP_MINBIT 0xFE900070 -#define VP4_MB_MAXBIT 0xFE900074 -#define VP4_MB_TBIT 0xFE900078 -#define VP4_RCQNT 0xFE90007C -#define VP4_RCRP 0xFE900080 -#define VP4_RCDJ 0xFE900084 -#define VP4_RCWQ 0xFE900088 -#define VP4_FWD_TIME 0xFE900094 -#define VP4_BWD_TIME 0xFE900098 -#define VP4_PST_TIME 0xFE90009C -#define VP4_ILTFRAME 0xFE9000A0 -#define VP4_EC_REF 0xFE9000A4 -#define VP4_STATUS 0xFE900100 -#define VP4_IRQ_ENB 0xFE900104 -#define VP4_IRQ_STA 0xFE900108 -#define VP4_VOP_BIT 0xFE90010C -#define VP4_PRV_BIT 0xFE900110 -#define VP4_SLC_MB 0xFE900114 -#define VP4_QSUM 0xFE900118 -#define VP4_DEC_ERR 0xFE90011C -#define VP4_ERR_AREA 0xFE900120 -#define VP4_NEXT_CODE 0xFE900124 -#define VP4_MB_ATTR 0xFE900128 -#define VP4_DBMON 0xFE90012C -#define VP4_DEBUG 0xFE900130 -#define VP4_ERR_DET 0xFE900134 -#define VP4_CLK_STOP 0xFE900138 -#define VP4_MB_SADA 0xFE90013C -#define VP4_MB_SADR 0xFE900140 -#define VP4_MAT_RAM 0xFE901000 -#define VP4_NC_RAM 0xFE902000 -#define WT 0xFE9020CC -#define VP4_CPY_ADDR 0xFE902264 -#define VP4_CPC_ADDR 0xFE902268 -#define VP4_R0Y_ADDR 0xFE90226C -#define VP4_R0C_ADDR 0xFE902270 -#define VP4_R1Y_ADDR 0xFE902274 -#define VP4_R1C_ADDR 0xFE902278 -#define VP4_R2Y_ADDR 0xFE90227C -#define VP4_R2C_ADDR 0xFE902280 -#define VP4_R3Y_ADDR 0xFE902284 -#define VP4_R3C_ADDR 0xFE902288 -#define VP4_R4Y_ADDR 0xFE90228C -#define VP4_R4C_ADDR 0xFE902290 -#define VP4_R5Y_ADDR 0xFE902294 -#define VP4_R5C_ADDR 0xFE902298 -#define VP4_R6Y_ADDR 0xFE90229C -#define VP4_R6C_ADDR 0xFE9022A0 -#define VP4_R7Y_ADDR 0xFE9022A4 -#define VP4_R7C_ADDR 0xFE9022A8 -#define VP4_R8Y_ADDR 0xFE9022AC -#define VP4_R8C_ADDR 0xFE9022B0 -#define VP4_R9Y_ADDR 0xFE9022B4 -#define VP4_R9C_ADDR 0xFE9022B8 -#define VP4_RAY_ADDR 0xFE9022BC -#define VP4_RAC_ADDR 0xFE9022C0 -#define VP4_RBY_ADDR 0xFE9022C4 -#define VP4_RBC_ADDR 0xFE9022C8 -#define VP4_RCY_ADDR 0xFE9022CC -#define VP4_RCC_ADDR 0xFE9022D0 -#define VP4_RDY_ADDR 0xFE9022D4 -#define VP4_RDC_ADDR 0xFE9022D8 -#define VP4_REY_ADDR 0xFE9022DC -#define VP4_REC_ADDR 0xFE9022E0 -#define VP4_RFY_ADDR 0xFE9022E4 -#define VP4_RFC_ADDR 0xFE9022E8 - -/* VIO(CEU) */ -#define CAPSR 0xFE910000 -#define CAPCR 0xFE910004 -#define CAMCR 0xFE910008 -#define CMCYR 0xFE91000C -#define CAMOR 0xFE910010 -#define CAPWR 0xFE910014 -#define CAIFR 0xFE910018 -#define CSTCR 0xFE910020 -#define CSECR 0xFE910024 -#define CRCNTR 0xFE910028 -#define CRCMPR 0xFE91002C -#define CFLCR 0xFE910030 -#define CFSZR 0xFE910034 -#define CDWDR 0xFE910038 -#define CDAYR 0xFE91003C -#define CDACR 0xFE910040 -#define CDBYR 0xFE910044 -#define CDBCR 0xFE910048 -#define CBDSR 0xFE91004C -#define CLFCR 0xFE910060 -#define CDOCR 0xFE910064 -#define CDDCR 0xFE910068 -#define CDDAR 0xFE91006C -#define CEIER 0xFE910070 -#define CETCR 0xFE910074 -#define CSTSR 0xFE91007C -#define CSRTR 0xFE910080 -#define CDAYR2 0xFE910090 -#define CDACR2 0xFE910094 -#define CDBYR2 0xFE910098 -#define CDBCR2 0xFE91009C - -/* VIO(VEU) */ -#define VESTR 0xFE920000 -#define VESWR 0xFE920010 -#define VESSR 0xFE920014 -#define VSAYR 0xFE920018 -#define VSACR 0xFE92001C -#define VBSSR 0xFE920020 -#define VEDWR 0xFE920030 -#define VDAYR 0xFE920034 -#define VDACR 0xFE920038 -#define VTRCR 0xFE920050 -#define VRFCR 0xFE920054 -#define VRFSR 0xFE920058 -#define VENHR 0xFE92005C -#define VFMCR 0xFE920070 -#define VVTCR 0xFE920074 -#define VHTCR 0xFE920078 -#define VAPCR 0xFE920080 -#define VECCR 0xFE920084 -#define VAFXR 0xFE920090 -#define VSWPR 0xFE920094 -#define VEIER 0xFE9200A0 -#define VEVTR 0xFE9200A4 -#define VSTAR 0xFE9200B0 -#define VBSRR 0xFE9200B4 - -/* VIO(BEU) */ -#define BESTR 0xFE930000 -#define BSMWR1 0xFE930010 -#define BSSZR1 0xFE930014 -#define BSAYR1 0xFE930018 -#define BSACR1 0xFE93001C -#define BSAAR1 0xFE930020 -#define BSIFR1 0xFE930024 -#define BSMWR2 0xFE930028 -#define BSSZR2 0xFE93002C -#define BSAYR2 0xFE930030 -#define BSACR2 0xFE930034 -#define BSAAR2 0xFE930038 -#define BSIFR2 0xFE93003C -#define BSMWR3 0xFE930040 -#define BSSZR3 0xFE930044 -#define BSAYR3 0xFE930048 -#define BSACR3 0xFE93004C -#define BSAAR3 0xFE930050 -#define BSIFR3 0xFE930054 -#define BTPSR 0xFE930058 -#define BMSMWR1 0xFE930070 -#define BMSSZR1 0xFE930074 -#define BMSAYR1 0xFE930078 -#define BMSACR1 0xFE93007C -#define BMSMWR2 0xFE930080 -#define BMSSZR2 0xFE930084 -#define BMSAYR2 0xFE930088 -#define BMSACR2 0xFE93008C -#define BMSMWR3 0xFE930090 -#define BMSSZR3 0xFE930094 -#define BMSAYR3 0xFE930098 -#define BMSACR3 0xFE93009C -#define BMSMWR4 0xFE9300A0 -#define BMSSZR4 0xFE9300A4 -#define BMSAYR4 0xFE9300A8 -#define BMSACR4 0xFE9300AC -#define BMSIFR 0xFE9300F0 -#define BBLCR0 0xFE930100 -#define BBLCR1 0xFE930104 -#define BPROCR 0xFE930108 -#define BMWCR0 0xFE93010C -#define BLOCR1 0xFE930114 -#define BLOCR2 0xFE930118 -#define BLOCR3 0xFE93011C -#define BMLOCR1 0xFE930120 -#define BMLOCR2 0xFE930124 -#define BMLOCR3 0xFE930128 -#define BMLOCR4 0xFE93012C -#define BMPCCR1 0xFE930130 -#define BMPCCR2 0xFE930134 -#define BPKFR 0xFE930140 -#define BPCCR0 0xFE930144 -#define BPCCR11 0xFE930148 -#define BPCCR12 0xFE93014C -#define BPCCR21 0xFE930150 -#define BPCCR22 0xFE930154 -#define BPCCR31 0xFE930158 -#define BPCCR32 0xFE93015C -#define BDMWR 0xFE930160 -#define BDAYR 0xFE930164 -#define BDACR 0xFE930168 -#define BAFXR 0xFE930180 -#define BSWPR 0xFE930184 -#define BEIER 0xFE930188 -#define BEVTR 0xFE93018C -#define BRCNTR 0xFE930194 -#define BSTAR 0xFE930198 -#define BBRSTR 0xFE93019C -#define BRCHR 0xFE9301A0 -#define CLUT 0xFE933000 - -/* JPU */ -#define JCMOD 0xFEA00000 -#define JCCMD 0xFEA00004 -#define JCSTS 0xFEA00008 -#define JCQTN 0xFEA0000C -#define JCHTN 0xFEA00010 -#define JCDRIU 0xFEA00014 -#define JCDRID 0xFEA00018 -#define JCVSZU 0xFEA0001C -#define JCVSZD 0xFEA00020 -#define JCHSZU 0xFEA00024 -#define JCHSZD 0xFEA00028 -#define JCDTCU 0xFEA0002C -#define JCDTCM 0xFEA00030 -#define JCDTCD 0xFEA00034 -#define JINTE 0xFEA00038 -#define JINTS 0xFEA0003C -#define JCDERR 0xFEA00040 -#define JCRST 0xFEA00044 -#define JIFCNT 0xFEA00060 -#define JIFECNT 0xFEA00070 -#define JIFESYA1 0xFEA00074 -#define JIFESCA1 0xFEA00078 -#define JIFESYA2 0xFEA0007C -#define JIFESCA2 0xFEA00080 -#define JIFESMW 0xFEA00084 -#define JIFESVSZ 0xFEA00088 -#define JIFESHSZ 0xFEA0008C -#define JIFEDA1 0xFEA00090 -#define JIFEDA2 0xFEA00094 -#define JIFEDRSZ 0xFEA00098 -#define JIFDCNT 0xFEA000A0 -#define JIFDSA1 0xFEA000A4 -#define JIFDSA2 0xFEA000A8 -#define JIFDDRSZ 0xFEA000AC -#define JIFDDMW 0xFEA000B0 -#define JIFDDVSZ 0xFEA000B4 -#define JIFDDHSZ 0xFEA000B8 -#define JIFDDYA1 0xFEA000BC -#define JIFDDCA1 0xFEA000C0 -#define JIFDDYA2 0xFEA000C4 -#define JIFDDCA2 0xFEA000C8 -#define JCQTBL0 0xFEA10000 -#define JCQTBL1 0xFEA10040 -#define JCQTBL2 0xFEA10080 -#define JCQTBL3 0xFEA100C0 -#define JCHTBD0 0xFEA10100 -#define JCHTBA0 0xFEA10120 -#define JCHTBD1 0xFEA10200 -#define JCHTBA1 0xFEA10220 - -/* LCDC */ -#define MLDDCKPAT1R 0xFE940400 -#define MLDDCKPAT2R 0xFE940404 -#define SLDDCKPAT1R 0xFE940408 -#define SLDDCKPAT2R 0xFE94040C -#define LDDCKR 0xFE940410 -#define LDDCKSTPR 0xFE940414 -#define MLDMT1R 0xFE940418 -#define MLDMT2R 0xFE94041C -#define MLDMT3R 0xFE940420 -#define MLDDFR 0xFE940424 -#define MLDSM1R 0xFE940428 -#define MLDSM2R 0xFE94042C -#define MLDSA1R 0xFE940430 -#define MLDSA2R 0xFE940434 -#define MLDMLSR 0xFE940438 -#define MLDWBFR 0xFE94043C -#define MLDWBCNTR 0xFE940440 -#define MLDWBAR 0xFE940444 -#define MLDHCNR 0xFE940448 -#define MLDHSYNR 0xFE94044C -#define MLDVLNR 0xFE940450 -#define MLDVSYNR 0xFE940454 -#define MLDHPDR 0xFE940458 -#define MLDVPDR 0xFE94045C -#define MLDPMR 0xFE940460 -#define LDPALCR 0xFE940464 -#define LDINTR 0xFE940468 -#define LDSR 0xFE94046C -#define LDCNT1R 0xFE940470 -#define LDCNT2R 0xFE940474 -#define LDRCNTR 0xFE940478 -#define LDDDSR 0xFE94047C -#define LDRCR 0xFE940484 -#define LDCMRKRGBR 0xFE9404C4 -#define LDCMRKCMYR 0xFE9404C8 -#define LDCMRK1R 0xFE9404CC -#define LDCMRK2R 0xFE9404D0 -#define LDCMGKRGBR 0xFE9404D4 -#define LDCMGKCMYR 0xFE9404D8 -#define LDCMGK1R 0xFE9404DC -#define LDCMGK2R 0xFE9404E0 -#define LDCMBKRGBR 0xFE9404E4 -#define LDCMBKCMYR 0xFE9404E8 -#define LDCMBK1R 0xFE9404EC -#define LDCMBK2R 0xFE9404F0 -#define LDCMHKPR 0xFE9404F4 -#define LDCMHKQR 0xFE9404F8 -#define LDCMSELR 0xFE9404FC -#define LDCMTVR 0xFE940500 -#define LDCMTVSELR 0xFE940504 -#define LDCMDTHR 0xFE940508 -#define LDCMCNTR 0xFE94050C -#define SLDMT1R 0xFE940600 -#define SLDMT2R 0xFE940604 -#define SLDMT3R 0xFE940608 -#define SLDDFR 0xFE94060C -#define SLDSM1R 0xFE940610 -#define SLDSM2R 0xFE940614 -#define SLDSA1R 0xFE940618 -#define SLDSA2R 0xFE94061C -#define SLDMLSR 0xFE940620 -#define SLDHCNR 0xFE940624 -#define SLDHSYNR 0xFE940628 -#define SLDVLNR 0xFE94062C -#define SLDVSYNR 0xFE940630 -#define SLDHPDR 0xFE940634 -#define SLDVPDR 0xFE940638 -#define SLDPMR 0xFE94063C -#define LDDWD0R 0xFE940800 -#define LDDWD1R 0xFE940804 -#define LDDWD2R 0xFE940808 -#define LDDWD3R 0xFE94080C -#define LDDWD4R 0xFE940810 -#define LDDWD5R 0xFE940814 -#define LDDWD6R 0xFE940818 -#define LDDWD7R 0xFE94081C -#define LDDWD8R 0xFE940820 -#define LDDWD9R 0xFE940824 -#define LDDWDAR 0xFE940828 -#define LDDWDBR 0xFE94082C -#define LDDWDCR 0xFE940830 -#define LDDWDDR 0xFE940834 -#define LDDWDER 0xFE940838 -#define LDDWDFR 0xFE94083C -#define LDDRDR 0xFE940840 -#define LDDWAR 0xFE940900 -#define LDDRAR 0xFE940904 -#define LDPR00 0xFE940000 - -/* VOU */ -#define VOUER 0xFE960000 -#define VOUCR 0xFE960004 -#define VOUSTR 0xFE960008 -#define VOUVCR 0xFE96000C -#define VOUISR 0xFE960010 -#define VOUBCR 0xFE960014 -#define VOUDPR 0xFE960018 -#define VOUDSR 0xFE96001C -#define VOUVPR 0xFE960020 -#define VOUIR 0xFE960024 -#define VOUSRR 0xFE960028 -#define VOUMSR 0xFE96002C -#define VOUHIR 0xFE960030 -#define VOUDFR 0xFE960034 -#define VOUAD1R 0xFE960038 -#define VOUAD2R 0xFE96003C -#define VOUAIR 0xFE960040 -#define VOUSWR 0xFE960044 -#define VOURCR 0xFE960048 -#define VOURPR 0xFE960050 - -/* TSIF */ -#define TSCTLR 0xA4C80000 -#define TSPIDR 0xA4C80004 -#define TSCMDR 0xA4C80008 -#define TSSTR 0xA4C8000C -#define TSTSDR 0xA4C80010 -#define TSBUFCLRR 0xA4C80014 -#define TSINTER 0xA4C80018 -#define TSPSCALER 0xA4C80020 -#define TSPSCALERR 0xA4C80024 -#define TSPCRADCMDR 0xA4C80028 -#define TSPCRADCR 0xA4C8002C -#define TSTRPCRADCR 0xA4C80030 -#define TSDPCRADCR 0xA4C80034 - -/* SIU */ -#define IFCTL 0xA454C000 -#define SRCTL 0xA454C004 -#define SFORM 0xA454C008 -#define CKCTL 0xA454C00C -#define TRDAT 0xA454C010 -#define STFIFO 0xA454C014 -#define DPAK 0xA454C01C -#define CKREV 0xA454C020 -#define EVNTC 0xA454C028 -#define SBCTL 0xA454C040 -#define SBPSET 0xA454C044 -#define SBBUS 0xA454C048 -#define SBWFLG 0xA454C058 -#define SBRFLG 0xA454C05C -#define SBWDAT 0xA454C060 -#define SBRDAT 0xA454C064 -#define SBFSTS 0xA454C068 -#define SBDVCA 0xA454C06C -#define SBDVCB 0xA454C070 -#define SBACTIV 0xA454C074 -#define DMAIA 0xA454C090 -#define DMAIB 0xA454C094 -#define DMAOA 0xA454C098 -#define DMAOB 0xA454C09C -#define SPLRI 0xA454C0B8 -#define SPRRI 0xA454C0BC -#define SPURI 0xA454C0C4 -#define SPTIS 0xA454C0C8 -#define SPSTS 0xA454C0CC -#define SPCTL 0xA454C0D0 -#define SPIRI 0xA454C0D4 -#define SPQCF 0xA454C0D8 -#define SPQCS 0xA454C0DC -#define SPQCT 0xA454C0E0 -#define DPEAK 0xA454C0F0 -#define DSLPD 0xA454C0F4 -#define DSLLV 0xA454C0F8 -#define BRGASEL 0xA454C100 -#define BRRA 0xA454C104 -#define BRGBSEL 0xA454C108 -#define BRRB 0xA454C10C - -/* USB */ -#define IFR0 0xA4480000 -#define ISR0 0xA4480010 -#define IER0 0xA4480020 -#define EPDR0I 0xA4480030 -#define EPDR0O 0xA4480034 -#define EPDR0S 0xA4480038 -#define EPDR1 0xA448003C -#define EPDR2 0xA4480040 -#define EPDR3 0xA4480044 -#define EPDR4 0xA4480048 -#define EPDR5 0xA448004C -#define EPDR6 0xA4480050 -#define EPDR7 0xA4480054 -#define EPDR8 0xA4480058 -#define EPDR9 0xA448005C -#define EPSZ0O 0xA4480080 -#define EPSZ3 0xA4480084 -#define EPSZ6 0xA4480088 -#define EPSZ9 0xA448008C -#define TRG 0xA44800A0 -#define DASTS 0xA44800A4 -#define FCLR 0xA44800AA -#define DMA 0xA44800AC -#define EPSTL 0xA44800B2 -#define CVR 0xA44800B4 -#define TSR 0xA44800B8 -#define CTLR 0xA44800BC -#define EPIR 0xA44800C0 -#define XVERCR 0xA44800D0 -#define STLMR 0xA44800D4 - -/* KEYSC */ -#define KYCR1 0xA44B0000 -#define KYCR2 0xA44B0004 -#define KYINDR 0xA44B0008 -#define KYOUTDR 0xA44B000C - -/* MMCIF */ -#define CMDR0 0xA4448000 -#define CMDR1 0xA4448001 -#define CMDR2 0xA4448002 -#define CMDR3 0xA4448003 -#define CMDR4 0xA4448004 -#define CMDR5 0xA4448005 -#define CMDSTRT 0xA4448006 -#define OPCR 0xA444800A -#define CSTR 0xA444800B -#define INTCR0 0xA444800C -#define INTCR1 0xA444800D -#define INTSTR0 0xA444800E -#define INTSTR1 0xA444800F -#define CLKON 0xA4448010 -#define CTOCR 0xA4448011 -#define VDCNT 0xA4448012 -#define TBCR 0xA4448014 -#define MODER 0xA4448016 -#define CMDTYR 0xA4448018 -#define RSPTYR 0xA4448019 -#define TBNCR 0xA444801A -#define RSPR0 0xA4448020 -#define RSPR1 0xA4448021 -#define RSPR2 0xA4448022 -#define RSPR3 0xA4448023 -#define RSPR4 0xA4448024 -#define RSPR5 0xA4448025 -#define RSPR6 0xA4448026 -#define RSPR7 0xA4448027 -#define RSPR8 0xA4448028 -#define RSPR9 0xA4448029 -#define RSPR10 0xA444802A -#define RSPR11 0xA444802B -#define RSPR12 0xA444802C -#define RSPR13 0xA444802D -#define RSPR14 0xA444802E -#define RSPR15 0xA444802F -#define RSPR16 0xA4448030 -#define RSPRD 0xA4448031 -#define DTOUTR 0xA4448032 -#define DR 0xA4448040 -#define FIFOCLR 0xA4448042 -#define DMACR 0xA4448044 -#define INTCR2 0xA4448046 -#define INTSTR2 0xA4448048 - -/* Z3D3 */ -#define DLBI 0xFD980000 -#define DLBD0 0xFD980080 -#define DLBD1 0xFD980100 -#define GEWM 0xFD984000 -#define ICD0 0xFD988000 -#define ICD1 0xFD989000 -#define ICT 0xFD98A000 -#define ILM 0xFD98C000 -#define FLM0 0xFD98C800 -#define FLM1 0xFD98D000 -#define FLUT 0xFD98D800 -#define Z3D_PC 0xFD98E400 -#define Z3D_PCSP 0xFD98E404 -#define Z3D_PAR 0xFD98E408 -#define Z3D_IMADR 0xFD98E40C -#define Z3D_BTR0 0xFD98E410 -#define Z3D_BTR1 0xFD98E414 -#define Z3D_BTR2 0xFD98E418 -#define Z3D_BTR3 0xFD98E41C -#define Z3D_LC0 0xFD98E420 -#define Z3D_LC1 0xFD98E424 -#define Z3D_LC2 0xFD98E428 -#define Z3D_LC3 0xFD98E42C -#define Z3D_FR0 0xFD98E430 -#define Z3D_FR1 0xFD98E434 -#define Z3D_FR2 0xFD98E438 -#define Z3D_SR 0xFD98E440 -#define Z3D_SMDR 0xFD98E444 -#define Z3D_PBIR 0xFD98E448 -#define Z3D_DMDR 0xFD98E44C -#define Z3D_IREG 0xFD98E460 -#define Z3D_AR00 0xFD98E480 -#define Z3D_AR01 0xFD98E484 -#define Z3D_AR02 0xFD98E488 -#define Z3D_AR03 0xFD98E48C -#define Z3D_BR00 0xFD98E490 -#define Z3D_BR01 0xFD98E494 -#define Z3D_IXR00 0xFD98E4A0 -#define Z3D_IXR01 0xFD98E4A4 -#define Z3D_IXR02 0xFD98E4A8 -#define Z3D_IXR03 0xFD98E4AC -#define Z3D_AR10 0xFD98E4C0 -#define Z3D_AR11 0xFD98E4C4 -#define Z3D_AR12 0xFD98E4C8 -#define Z3D_AR13 0xFD98E4CC -#define Z3D_BR10 0xFD98E4D0 -#define Z3D_BR11 0xFD98E4D4 -#define Z3D_IXR10 0xFD98E4E0 -#define Z3D_IXR11 0xFD98E4E4 -#define Z3D_IXR12 0xFD98E4E8 -#define Z3D_IXR13 0xFD98E4EC -#define Z3D_AR20 0xFD98E500 -#define Z3D_AR21 0xFD98E504 -#define Z3D_AR22 0xFD98E508 -#define Z3D_AR23 0xFD98E50C -#define Z3D_BR20 0xFD98E510 -#define Z3D_BR21 0xFD98E514 -#define Z3D_IXR20 0xFD98E520 -#define Z3D_IXR21 0xFD98E524 -#define Z3D_IXR22 0xFD98E528 -#define Z3D_IXR23 0xFD98E52C -#define Z3D_MR0 0xFD98E540 -#define Z3D_MR1 0xFD98E544 -#define Z3D_MR2 0xFD98E548 -#define Z3D_MR3 0xFD98E54C -#define Z3D_WORKRST 0xFD98E558 -#define Z3D_WORKWST 0xFD98E55C -#define Z3D_DBADR 0xFD98E560 -#define Z3D_DLBPRST 0xFD98E564 -#define Z3D_DLBRST 0xFD98E568 -#define Z3D_DLBWST 0xFD98E56C -#define Z3D_UDR0 0xFD98E570 -#define Z3D_UDR1 0xFD98E574 -#define Z3D_UDR2 0xFD98E578 -#define Z3D_UDR3 0xFD98E57C -#define Z3D_CCR0 0xFD98E580 -#define Z3D_CCR1 0xFD98E584 -#define Z3D_EXPR 0xFD98E588 -#define Z3D_V0_X 0xFD9A0000 -#define Z3D_V0_Y 0xFD9A0004 -#define Z3D_V0_Z 0xFD9A0008 -#define Z3D_V0_W 0xFD9A000C -#define Z3D_V0_A 0xFD9A0010 -#define Z3D_V0_R 0xFD9A0014 -#define Z3D_V0_G 0xFD9A0018 -#define Z3D_V0_B 0xFD9A001C -#define Z3D_V0_F 0xFD9A0020 -#define Z3D_V0_SR 0xFD9A0024 -#define Z3D_V0_SG 0xFD9A0028 -#define Z3D_V0_SB 0xFD9A002C -#define Z3D_V0_U0 0xFD9A0030 -#define Z3D_V0_V0 0xFD9A0034 -#define Z3D_V0_U1 0xFD9A0038 -#define Z3D_V0_V1 0xFD9A003C -#define Z3D_V1_X 0xFD9A0080 -#define Z3D_V1_Y 0xFD9A0084 -#define Z3D_V1_Z 0xFD9A0088 -#define Z3D_V1_W 0xFD9A008C -#define Z3D_V1_A 0xFD9A0090 -#define Z3D_V1_R 0xFD9A0094 -#define Z3D_V1_G 0xFD9A0098 -#define Z3D_V1_B 0xFD9A009C -#define Z3D_V1_F 0xFD9A00A0 -#define Z3D_V1_SR 0xFD9A00A4 -#define Z3D_V1_SG 0xFD9A00A8 -#define Z3D_V1_SB 0xFD9A00AC -#define Z3D_V1_U0 0xFD9A00B0 -#define Z3D_V1_V0 0xFD9A00B4 -#define Z3D_V1_U1 0xFD9A00B8 -#define Z3D_V1_V1 0xFD9A00BC -#define Z3D_V2_X 0xFD9A0100 -#define Z3D_V2_Y 0xFD9A0104 -#define Z3D_V2_Z 0xFD9A0108 -#define Z3D_V2_W 0xFD9A010C -#define Z3D_V2_A 0xFD9A0110 -#define Z3D_V2_R 0xFD9A0114 -#define Z3D_V2_G 0xFD9A0118 -#define Z3D_V2_B 0xFD9A011C -#define Z3D_V2_F 0xFD9A0120 -#define Z3D_V2_SR 0xFD9A0124 -#define Z3D_V2_SG 0xFD9A0128 -#define Z3D_V2_SB 0xFD9A012C -#define Z3D_V2_U0 0xFD9A0130 -#define Z3D_V2_V0 0xFD9A0134 -#define Z3D_V2_U1 0xFD9A0138 -#define Z3D_V2_V1 0xFD9A013C -#define Z3D_RENDER 0xFD9A0180 -#define Z3D_POLYGON_OFFSET 0xFD9A0184 -#define Z3D_VERTEX_CONTROL 0xFD9A0200 -#define Z3D_STATE_MODE 0xFD9A0204 -#define Z3D_FPU_MODE 0xFD9A0318 -#define Z3D_SCISSOR_MIN 0xFD9A0400 -#define Z3D_SCISSOR_MAX 0xFD9A0404 -#define Z3D_TEXTURE_MODE_A 0xFD9A0408 -#define Z3D_TEXTURE_MODE_B 0xFD9A040C -#define Z3D_TEXTURE_BASE_HI_A 0xFD9A0418 -#define Z3D_TEXTURE_BASE_LO_A 0xFD9A041C -#define Z3D_TEXTURE_BASE_HI_B 0xFD9A0420 -#define Z3D_TEXTURE_BASE_LO_B 0xFD9A0424 -#define Z3D_TEXTURE_ALPHA_A0 0xFD9A0438 -#define Z3D_TEXTURE_ALPHA_A1 0xFD9A043C -#define Z3D_TEXTURE_ALPHA_A2 0xFD9A0440 -#define Z3D_TEXTURE_ALPHA_A3 0xFD9A0444 -#define Z3D_TEXTURE_ALPHA_A4 0xFD9A0448 -#define Z3D_TEXTURE_ALPHA_A5 0xFD9A044C -#define Z3D_TEXTURE_ALPHA_B0 0xFD9A0450 -#define Z3D_TEXTURE_ALPHA_B1 0xFD9A0454 -#define Z3D_TEXTURE_ALPHA_B2 0xFD9A0458 -#define Z3D_TEXTURE_ALPHA_B3 0xFD9A045C -#define Z3D_TEXTURE_ALPHA_B4 0xFD9A0460 -#define Z3D_TEXTURE_ALPHA_B5 0xFD9A0464 -#define Z3D_TEXTURE_FLUSH 0xFD9A0498 -#define Z3D_GAMMA_TABLE0 0xFD9A049C -#define Z3D_GAMMA_TABLE1 0xFD9A04A0 -#define Z3D_GAMMA_TABLE2 0xFD9A04A4 -#define Z3D_ALPHA_TEST 0xFD9A0800 -#define Z3D_STENCIL_TEST 0xFD9A0804 -#define Z3D_DEPTH_ROP_BLEND_DITHER 0xFD9A0808 -#define Z3D_MASK 0xFD9A080C -#define Z3D_FBUS_MODE 0xFD9A0810 -#define Z3D_GNT_SET 0xFD9A0814 -#define Z3D_BETWEEN_TEST 0xFD9A0818 -#define Z3D_FB_BASE 0xFD9A081C -#define Z3D_LCD_SIZE 0xFD9A0820 -#define Z3D_FB_FLUSH 0xFD9A0824 -#define Z3D_CACHE_INVALID 0xFD9A0828 -#define Z3D_SC_MODE 0xFD9A0830 -#define Z3D_SC0_MIN 0xFD9A0834 -#define Z3D_SC0_MAX 0xFD9A0838 -#define Z3D_SC1_MIN 0xFD9A083C -#define Z3D_SC1_MAX 0xFD9A0840 -#define Z3D_SC2_MIN 0xFD9A0844 -#define Z3D_SC2_MAX 0xFD9A0848 -#define Z3D_SC3_MIN 0xFD9A084C -#define Z3D_SC3_MAX 0xFD9A0850 -#define Z3D_READRESET 0xFD9A0854 -#define Z3D_DET_MIN 0xFD9A0858 -#define Z3D_DET_MAX 0xFD9A085C -#define Z3D_FB_BASE_SR 0xFD9A0860 -#define Z3D_LCD_SIZE_SR 0xFD9A0864 -#define Z3D_2D_CTRL_STATUS 0xFD9A0C00 -#define Z3D_2D_SIZE 0xFD9A0C04 -#define Z3D_2D_SRCLOC 0xFD9A0C08 -#define Z3D_2D_DSTLOC 0xFD9A0C0C -#define Z3D_2D_DMAPORT 0xFD9A0C10 -#define Z3D_2D_CONSTANT_SOURCE0 0xFD9A0C14 -#define Z3D_2D_CONSTANT_SOURCE1 0xFD9A0C18 -#define Z3D_2D_STPCOLOR0 0xFD9A0C1C -#define Z3D_2D_STPCOLOR1 0xFD9A0C20 -#define Z3D_2D_STPPARAMETER_SET0 0xFD9A0C24 -#define Z3D_2D_STPPARAMETER_SET1 0xFD9A0C28 -#define Z3D_2D_STPPAT_0 0xFD9A0C40 -#define Z3D_2D_STPPAT_1 0xFD9A0C44 -#define Z3D_2D_STPPAT_2 0xFD9A0C48 -#define Z3D_2D_STPPAT_3 0xFD9A0C4C -#define Z3D_2D_STPPAT_4 0xFD9A0C50 -#define Z3D_2D_STPPAT_5 0xFD9A0C54 -#define Z3D_2D_STPPAT_6 0xFD9A0C58 -#define Z3D_2D_STPPAT_7 0xFD9A0C5C -#define Z3D_2D_STPPAT_8 0xFD9A0C60 -#define Z3D_2D_STPPAT_9 0xFD9A0C64 -#define Z3D_2D_STPPAT_10 0xFD9A0C68 -#define Z3D_2D_STPPAT_11 0xFD9A0C6C -#define Z3D_2D_STPPAT_12 0xFD9A0C70 -#define Z3D_2D_STPPAT_13 0xFD9A0C74 -#define Z3D_2D_STPPAT_14 0xFD9A0C78 -#define Z3D_2D_STPPAT_15 0xFD9A0C7C -#define Z3D_2D_STPPAT_16 0xFD9A0C80 -#define Z3D_2D_STPPAT_17 0xFD9A0C84 -#define Z3D_2D_STPPAT_18 0xFD9A0C88 -#define Z3D_2D_STPPAT_19 0xFD9A0C8C -#define Z3D_2D_STPPAT_20 0xFD9A0C90 -#define Z3D_2D_STPPAT_21 0xFD9A0C94 -#define Z3D_2D_STPPAT_22 0xFD9A0C98 -#define Z3D_2D_STPPAT_23 0xFD9A0C9C -#define Z3D_2D_STPPAT_24 0xFD9A0CA0 -#define Z3D_2D_STPPAT_25 0xFD9A0CA4 -#define Z3D_2D_STPPAT_26 0xFD9A0CA8 -#define Z3D_2D_STPPAT_27 0xFD9A0CAC -#define Z3D_2D_STPPAT_28 0xFD9A0CB0 -#define Z3D_2D_STPPAT_29 0xFD9A0CB4 -#define Z3D_2D_STPPAT_30 0xFD9A0CB8 -#define Z3D_2D_STPPAT_31 0xFD9A0CBC -#define Z3D_WR_CTRL 0xFD9A1000 -#define Z3D_WR_P0 0xFD9A1004 -#define Z3D_WR_P1 0xFD9A1008 -#define Z3D_WR_P2 0xFD9A100C -#define Z3D_WR_FGC 0xFD9A1010 -#define Z3D_WR_BGC 0xFD9A1014 -#define Z3D_WR_SZ 0xFD9A1018 -#define Z3D_WR_PATPARAM 0xFD9A101C -#define Z3D_WR_PAT 0xFD9A1020 -#define Z3D_SYS_STATUS 0xFD9A1400 -#define Z3D_SYS_RESET 0xFD9A1404 -#define Z3D_SYS_CLK 0xFD9A1408 -#define Z3D_SYS_CONF 0xFD9A140C -#define Z3D_SYS_VERSION 0xFD9A1410 -#define Z3D_SYS_DBINV 0xFD9A1418 -#define Z3D_SYS_I2F_FMT 0xFD9A1420 -#define Z3D_SYS_I2F_SRC 0xFD9A1424 -#define Z3D_SYS_I2F_DST 0xFD9A1428 -#define Z3D_SYS_GBCNT 0xFD9A1430 -#define Z3D_SYS_BSYCNT 0xFD9A1434 -#define Z3D_SYS_INT_STATUS 0xFD9A1450 -#define Z3D_SYS_INT_MASK 0xFD9A1454 -#define Z3D_SYS_INT_CLEAR 0xFD9A1458 -#define TCD0 0xFD9C0000 -#define TCD1 0xFD9C0400 -#define TCD2 0xFD9C0800 -#define TCD3 0xFD9C0C00 -#define TCT0 0xFD9C1000 -#define TCT1 0xFD9C1400 -#define TCT2 0xFD9C1800 -#define TCT3 0xFD9C1C00 - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PDCR 0xA4050106 -#define PECR 0xA4050108 -#define PFCR 0xA405010A -#define PGCR 0xA405010C -#define PHCR 0xA405010E -#define PJCR 0xA4050110 -#define PKCR 0xA4050112 -#define PLCR 0xA4050114 -#define PMCR 0xA4050116 -#define PNCR 0xA4050118 -#define PQCR 0xA405011A -#define PRCR 0xA405011C -#define PSCR 0xA405011E -#define PTCR 0xA4050140 -#define PUCR 0xA4050142 -#define PVCR 0xA4050144 -#define PWCR 0xA4050146 -#define PXCR 0xA4050148 -#define PYCR 0xA405014A -#define PZCR 0xA405014C -#define PSELA 0xA405014E -#define PSELB 0xA4050150 -#define PSELC 0xA4050152 -#define PSELD 0xA4050154 -#define PSELE 0xA4050156 -#define HIZCRA 0xA4050158 -#define HIZCRB 0xA405015A -#define HIZCRC 0xA405015C -#define HIZCRC 0xA405015C -#define MSELCRA 0xA4050180 -#define MSELCRB 0xA4050182 -#define PULCR 0xA4050184 -#define SBSCR 0xA4050186 -#define DRVCR 0xA405018A - -/* I/O Port */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 -#define PDDR 0xA4050126 -#define PEDR 0xA4050128 -#define PFDR 0xA405012A -#define PGDR 0xA405012C -#define PHDR 0xA405012E -#define PJDR 0xA4050130 -#define PKDR 0xA4050132 -#define PLDR 0xA4050134 -#define PMDR 0xA4050136 -#define PNDR 0xA4050138 -#define PQDR 0xA405013A -#define PRDR 0xA405013C -#define PSDR 0xA405013E -#define PTDR 0xA4050160 -#define PUDR 0xA4050162 -#define PVDR 0xA4050164 -#define PWDR 0xA4050166 -#define PYDR 0xA4050168 -#define PZDR 0xA405016A - -/* UBC */ -#define CBR0 0xFF200000 -#define CRR0 0xFF200004 -#define CAR0 0xFF200008 -#define CAMR0 0xFF20000C -#define CBR1 0xFF200020 -#define CRR1 0xFF200024 -#define CAR1 0xFF200028 -#define CAMR1 0xFF20002C -#define CDR1 0xFF200030 -#define CDMR1 0xFF200034 -#define CETR1 0xFF200038 -#define CCMFR 0xFF200600 -#define CBCR 0xFF200620 - -/* H-UDI */ -#define SDIR 0xFC110000 -#define SDDRH 0xFC110008 -#define SDDRL 0xFC11000A -#define SDINT 0xFC110018 - -#endif /* _ASM_CPU_SH7722_H_ */ diff --git a/include/asm-sh/cpu_sh7723.h b/include/asm-sh/cpu_sh7723.h deleted file mode 100644 index 6dac6e9..0000000 --- a/include/asm-sh/cpu_sh7723.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * (C) Copyright 2008 Renesas Solutions Corp. - * - * SH7723 Internal I/O register - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH7723_H_ -#define _ASM_CPU_SH7723_H_ - -#define CACHE_OC_NUM_WAYS 4 -#define CCR_CACHE_INIT 0x0000090d - -/* EXP */ -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 - -/* MMU */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define PASCR 0xFF000070 -#define IRMCR 0xFF000078 - -/* CACHE */ -#define CCR 0xFF00001C -#define RAMCR 0xFF000074 - -/* INTC */ - -/* BSC */ -#define CMNCR 0xFEC10000 -#define CS0BCR 0xFEC10004 -#define CS2BCR 0xFEC10008 -#define CS4BCR 0xFEC10010 -#define CS5ABCR 0xFEC10014 -#define CS5BBCR 0xFEC10018 -#define CS6ABCR 0xFEC1001C -#define CS6BBCR 0xFEC10020 -#define CS0WCR 0xFEC10024 -#define CS2WCR 0xFEC10028 -#define CS4WCR 0xFEC10030 -#define CS5AWCR 0xFEC10034 -#define CS5BWCR 0xFEC10038 -#define CS6AWCR 0xFEC1003C -#define CS6BWCR 0xFEC10040 -#define RBWTCNT 0xFEC10054 - -/* SBSC */ -#define SBSC_SDCR 0xFE400008 -#define SBSC_SDWCR 0xFE40000C -#define SBSC_SDPCR 0xFE400010 -#define SBSC_RTCSR 0xFE400014 -#define SBSC_RTCNT 0xFE400018 -#define SBSC_RTCOR 0xFE40001C -#define SBSC_RFCR 0xFE400020 - -/* DMAC */ - -/* CPG */ -#define FRQCR 0xA4150000 -#define VCLKCR 0xA4150004 -#define SCLKACR 0xA4150008 -#define SCLKBCR 0xA415000C -#define IRDACLKCR 0xA4150018 -#define PLLCR 0xA4150024 -#define DLLFRQ 0xA4150050 - -/* LOW POWER MODE */ -#define STBCR 0xA4150020 -#define MSTPCR0 0xA4150030 -#define MSTPCR1 0xA4150034 -#define MSTPCR2 0xA4150038 - -/* RWDT */ -#define RWTCNT 0xA4520000 -#define RWTCSR 0xA4520004 -#define WTCNT RWTCNT - -/* TMU */ -#define TSTR 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 - -/* TPU */ - -/* CMT */ -#define CMSTR 0xA44A0000 -#define CMCSR 0xA44A0060 -#define CMCNT 0xA44A0064 -#define CMCOR 0xA44A0068 - -/* MSIOF */ - -/* SCIF */ -#define SCIF0_BASE 0xFFE00000 -#define SCIF1_BASE 0xFFE10000 -#define SCIF2_BASE 0xFFE20000 -#define SCIF3_BASE 0xa4e30000 -#define SCIF4_BASE 0xa4e40000 -#define SCIF5_BASE 0xa4e50000 - -/* RTC */ -/* IrDA */ -/* KEYSC */ -/* USB */ -/* IIC */ -/* FLCTL */ -/* VPU */ -/* VIO(CEU) */ -/* VIO(VEU) */ -/* VIO(BEU) */ -/* 2DG */ -/* LCDC */ -/* VOU */ -/* TSIF */ -/* SIU */ -/* ATAPI */ - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PDCR 0xA4050106 -#define PECR 0xA4050108 -#define PFCR 0xA405010A -#define PGCR 0xA405010C -#define PHCR 0xA405010E -#define PJCR 0xA4050110 -#define PKCR 0xA4050112 -#define PLCR 0xA4050114 -#define PMCR 0xA4050116 -#define PNCR 0xA4050118 -#define PQCR 0xA405011A -#define PRCR 0xA405011C -#define PSCR 0xA405011E -#define PTCR 0xA4050140 -#define PUCR 0xA4050142 -#define PVCR 0xA4050144 -#define PWCR 0xA4050146 -#define PXCR 0xA4050148 -#define PYCR 0xA405014A -#define PZCR 0xA405014C -#define PSELA 0xA405014E -#define PSELB 0xA4050150 -#define PSELC 0xA4050152 -#define PSELD 0xA4050154 -#define HIZCRA 0xA4050158 -#define HIZCRB 0xA405015A -#define HIZCRC 0xA405015C -#define HIZCRD 0xA405015E -#define MSELCRA 0xA4050180 -#define MSELCRB 0xA4050182 -#define PULCR 0xA4050184 -#define DRVCRA 0xA405018A -#define DRVCRB 0xA405018C - -/* I/O Port */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 -#define PDDR 0xA4050126 -#define PEDR 0xA4050128 -#define PFDR 0xA405012A -#define PGDR 0xA405012C -#define PHDR 0xA405012E -#define PJDR 0xA4050130 -#define PKDR 0xA4050132 -#define PLDR 0xA4050134 -#define PMDR 0xA4050136 -#define PNDR 0xA4050138 -#define PQDR 0xA405013A -#define PRDR 0xA405013C -#define PSDR 0xA405013E -#define PTDR 0xA4050160 -#define PUDR 0xA4050162 -#define PVDR 0xA4050164 -#define PWDR 0xA4050166 -#define PYDR 0xA4050168 -#define PZDR 0xA405016A - -/* UBC */ -/* H-UDI */ - -#endif /* _ASM_CPU_SH7723_H_ */ diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h deleted file mode 100644 index 4e43a46..0000000 --- a/include/asm-sh/cpu_sh7750.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2007 Nobuhiro Iwamatsu - * - * SH7750/SH7750S/SH7750R/SH7751/SH7751R - * Internal I/O register - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH7750_H_ -#define _ASM_CPU_SH7750_H_ - -#ifdef CONFIG_CPU_TYPE_R -#define CACHE_OC_NUM_WAYS 2 -#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ -#else -#define CACHE_OC_NUM_WAYS 1 -#define CCR_CACHE_INIT 0x0000090B -#endif - -/* OCN */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define BASRA 0xFF000014 -#define BASRB 0xFF000018 -#define CCR 0xFF00001C -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 -#define PTEA 0xFF000034 -#define QACR0 0xFF000038 -#define QACR1 0xFF00003C - -/* UBC */ -#define BARA 0xFF200000 -#define BAMRA 0xFF200004 -#define BBRA 0xFF200008 -#define BARB 0xFF20000C -#define BAMRB 0xFF200010 -#define BBRB 0xFF200014 -#define BDRB 0xFF200018 -#define BDMRB 0xFF20001C -#define BRCR 0xFF200020 - -/* BSC */ -#define BCR1 0xFF800000 -#define BCR2 0xFF800004 -#define BCR3 0xFF800050 -#define BCR4 0xFE0A00F0 -#define WCR1 0xFF800008 -#define WCR2 0xFF80000C -#define WCR3 0xFF800010 -#define MCR 0xFF800014 -#define PCR 0xFF800018 -#define RTCSR 0xFF80001C -#define RTCNT 0xFF800020 -#define RTCOR 0xFF800024 -#define RFCR 0xFF800028 -#define PCTRA 0xFF80002C -#define PDTRA 0xFF800030 -#define PCTRB 0xFF800040 -#define PDTRB 0xFF800044 -#define GPIOIC 0xFF800048 - -/* DMAC */ -#define SAR0 0xFFA00000 -#define DAR0 0xFFA00004 -#define DMATCR0 0xFFA00008 -#define CHCR0 0xFFA0000C -#define SAR1 0xFFA00010 -#define DAR1 0xFFA00014 -#define DMATCR1 0xFFA00018 -#define CHCR1 0xFFA0001C -#define SAR2 0xFFA00020 -#define DAR2 0xFFA00024 -#define DMATCR2 0xFFA00028 -#define CHCR2 0xFFA0002C -#define SAR3 0xFFA00030 -#define DAR3 0xFFA00034 -#define DMATCR3 0xFFA00038 -#define CHCR3 0xFFA0003C -#define DMAOR 0xFFA00040 -#define SAR4 0xFFA00050 -#define DAR4 0xFFA00054 -#define DMATCR4 0xFFA00058 - -/* CPG */ -#define FRQCR 0xFFC00000 -#define STBCR 0xFFC00004 -#define WTCNT 0xFFC00008 -#define WTCSR 0xFFC0000C -#define STBCR2 0xFFC00010 - -/* RTC */ -#define R64CNT 0xFFC80000 -#define RSECCNT 0xFFC80004 -#define RMINCNT 0xFFC80008 -#define RHRCNT 0xFFC8000C -#define RWKCNT 0xFFC80010 -#define RDAYCNT 0xFFC80014 -#define RMONCNT 0xFFC80018 -#define RYRCNT 0xFFC8001C -#define RSECAR 0xFFC80020 -#define RMINAR 0xFFC80024 -#define RHRAR 0xFFC80028 -#define RWKAR 0xFFC8002C -#define RDAYAR 0xFFC80030 -#define RMONAR 0xFFC80034 -#define RCR1 0xFFC80038 -#define RCR2 0xFFC8003C -#define RCR3 0xFFC80050 -#define RYRAR 0xFFC80054 - -/* ICR */ -#define ICR 0xFFD00000 -#define IPRA 0xFFD00004 -#define IPRB 0xFFD00008 -#define IPRC 0xFFD0000C -#define IPRD 0xFFD00010 -#define INTPRI 0xFE080000 -#define INTREQ 0xFE080020 -#define INTMSK 0xFE080040 -#define INTMSKCL 0xFE080060 - -/* CPG */ -#define CLKSTP 0xFE0A0000 -#define CLKSTPCLR 0xFE0A0008 - -/* TMU */ -#define TSTR2 0xFE100004 -#define TCOR3 0xFE100008 -#define TCNT3 0xFE10000C -#define TCR3 0xFE100010 -#define TCOR4 0xFE100014 -#define TCNT4 0xFE100018 -#define TCR4 0xFE10001C -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 -#define TCPR2 0xFFD8002C -#define TSTR TSTR0 - -/* SCI */ -#define SCSMR1 0xFFE00000 -#define SCBRR1 0xFFE00004 -#define SCSCR1 0xFFE00008 -#define SCTDR1 0xFFE0000C -#define SCSSR1 0xFFE00010 -#define SCRDR1 0xFFE00014 -#define SCSCMR1 0xFFE00018 -#define SCSPTR1 0xFFE0001C -#define SCF0_BASE SCSMR1 - -/* SCIF */ -#define SCSMR2 0xFFE80000 -#define SCBRR2 0xFFE80004 -#define SCSCR2 0xFFE80008 -#define SCFTDR2 0xFFE8000C -#define SCFSR2 0xFFE80010 -#define SCFRDR2 0xFFE80014 -#define SCFCR2 0xFFE80018 -#define SCFDR2 0xFFE8001C -#define SCSPTR2 0xFFE80020 -#define SCLSR2 0xFFE80024 -#define SCIF1_BASE SCSMR2 - -/* H-UDI */ -#define SDIR 0xFFF00000 -#define SDDR 0xFFF00008 -#define SDINT 0xFFF00014 - -#endif /* _ASM_CPU_SH7750_H_ */ diff --git a/include/asm-sh/cpu_sh7763.h b/include/asm-sh/cpu_sh7763.h deleted file mode 100644 index 78b456b..0000000 --- a/include/asm-sh/cpu_sh7763.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _ASM_CPU_SH7763_H_ -#define _ASM_CPU_SH7763_H_ - -/* CACHE */ -#define CACHE_OC_NUM_WAYS 1 -#define CCR 0xFF00001C -#define CCR_CACHE_INIT 0x0000090b - -/* SCIF */ -/* SCIF0 */ -#define SCIF0_BASE SCSMR0 -#define SCSMR0 0xFFE00000 - -/* SCIF1 */ -#define SCIF1_BASE SCSMR1 -#define SCSMR1 0xFFE08000 - -/* SCIF2 */ -#define SCIF2_BASE SCSMR2 -#define SCSMR2 0xFFE10000 - -/* Watchdog Timer */ -#define WTCNT WDTST -#define WDTST 0xFFCC0000 - -/* TMU */ -#define TSTR 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 - -#endif /* _ASM_CPU_SH7763_H_ */ diff --git a/include/asm-sh/cpu_sh7780.h b/include/asm-sh/cpu_sh7780.h deleted file mode 100644 index d4f824e..0000000 --- a/include/asm-sh/cpu_sh7780.h +++ /dev/null @@ -1,503 +0,0 @@ -#ifndef _ASM_CPU_SH7780_H_ -#define _ASM_CPU_SH7780_H_ - -/* - * Copyright (c) 2007,2008 Nobuhiro Iwamatsu - * Copyright (c) 2008 Yusuke Goda - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#define CACHE_OC_NUM_WAYS 1 -#define CCR_CACHE_INIT 0x0000090b - -/* Exceptions */ -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 - -/* Memory Management Unit */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define PASCR 0xFF000070 -#define IRMCR 0xFF000078 - -/* Cache Controller */ -#define CCR 0xFF00001C -#define QACR0 0xFF000038 -#define QACR1 0xFF00003C -#define RAMCR 0xFF000074 - -/* L Memory */ -#define RAMCR 0xFF000074 -#define LSA0 0xFF000050 -#define LSA1 0xFF000054 -#define LDA0 0xFF000058 -#define LDA1 0xFF00005C - -/* Interrupt Controller */ -#define ICR0 0xFFD00000 -#define ICR1 0xFFD0001C -#define INTPRI 0xFFD00010 -#define INTREQ 0xFFD00024 -#define INTMSK0 0xFFD00044 -#define INTMSK1 0xFFD00048 -#define INTMSK2 0xFFD40080 -#define INTMSKCLR0 0xFFD00064 -#define INTMSKCLR1 0xFFD00068 -#define INTMSKCLR2 0xFFD40084 -#define NMIFCR 0xFFD000C0 -#define USERIMASK 0xFFD30000 -#define INT2PRI0 0xFFD40000 -#define INT2PRI1 0xFFD40004 -#define INT2PRI2 0xFFD40008 -#define INT2PRI3 0xFFD4000C -#define INT2PRI4 0xFFD40010 -#define INT2PRI5 0xFFD40014 -#define INT2PRI6 0xFFD40018 -#define INT2PRI7 0xFFD4001C -#define INT2A0 0xFFD40030 -#define INT2A1 0xFFD40034 -#define INT2MSKR 0xFFD40038 -#define INT2MSKCR 0xFFD4003C -#define INT2B0 0xFFD40040 -#define INT2B1 0xFFD40044 -#define INT2B2 0xFFD40048 -#define INT2B3 0xFFD4004C -#define INT2B4 0xFFD40050 -#define INT2B5 0xFFD40054 -#define INT2B6 0xFFD40058 -#define INT2B7 0xFFD4005C -#define INT2GPIC 0xFFD40090 - -/* local Bus State Controller */ -#define MMSELR 0xFF400020 -#define BCR 0xFF801000 -#define CS0BCR 0xFF802000 -#define CS1BCR 0xFF802010 -#define CS2BCR 0xFF802020 -#define CS4BCR 0xFF802040 -#define CS5BCR 0xFF802050 -#define CS6BCR 0xFF802060 -#define CS0WCR 0xFF802008 -#define CS1WCR 0xFF802018 -#define CS2WCR 0xFF802028 -#define CS4WCR 0xFF802048 -#define CS5WCR 0xFF802058 -#define CS6WCR 0xFF802068 -#define CS5PCR 0xFF802070 -#define CS6PCR 0xFF802080 - -/* DDR-SDRAM I/F */ -#define MIM_1 0xFE800008 -#define MIM_2 0xFE80000C -#define SCR_1 0xFE800010 -#define SCR_2 0xFE800014 -#define STR_1 0xFE800018 -#define STR_2 0xFE80001C -#define SDR_1 0xFE800030 -#define SDR_2 0xFE800034 -#define DBK_1 0xFE800400 -#define DBK_2 0xFE800404 - -/* PCI Controller */ -#define SH7780_PCIECR 0xFE000008 -#define SH7780_PCIVID 0xFE040000 -#define SH7780_PCIDID 0xFE040002 -#define SH7780_PCICMD 0xFE040004 -#define SH7780_PCISTATUS 0xFE040006 -#define SH7780_PCIRID 0xFE040008 -#define SH7780_PCIPIF 0xFE040009 -#define SH7780_PCISUB 0xFE04000A -#define SH7780_PCIBCC 0xFE04000B -#define SH7780_PCICLS 0xFE04000C -#define SH7780_PCILTM 0xFE04000D -#define SH7780_PCIHDR 0xFE04000E -#define SH7780_PCIBIST 0xFE04000F -#define SH7780_PCIIBAR 0xFE040010 -#define SH7780_PCIMBAR0 0xFE040014 -#define SH7780_PCIMBAR1 0xFE040018 -#define SH7780_PCISVID 0xFE04002C -#define SH7780_PCISID 0xFE04002E -#define SH7780_PCICP 0xFE040034 -#define SH7780_PCIINTLINE 0xFE04003C -#define SH7780_PCIINTPIN 0xFE04003D -#define SH7780_PCIMINGNT 0xFE04003E -#define SH7780_PCIMAXLAT 0xFE04003F -#define SH7780_PCICID 0xFE040040 -#define SH7780_PCINIP 0xFE040041 -#define SH7780_PCIPMC 0xFE040042 -#define SH7780_PCIPMCSR 0xFE040044 -#define SH7780_PCIPMCSRBSE 0xFE040046 -#define SH7780_PCI_CDD 0xFE040047 -#define SH7780_PCICR 0xFE040100 -#define SH7780_PCILSR0 0xFE040104 -#define SH7780_PCILSR1 0xFE040108 -#define SH7780_PCILAR0 0xFE04010C -#define SH7780_PCILAR1 0xFE040110 -#define SH7780_PCIIR 0xFE040114 -#define SH7780_PCIIMR 0xFE040118 -#define SH7780_PCIAIR 0xFE04011C -#define SH7780_PCICIR 0xFE040120 -#define SH7780_PCIAINT 0xFE040130 -#define SH7780_PCIAINTM 0xFE040134 -#define SH7780_PCIBMIR 0xFE040138 -#define SH7780_PCIPAR 0xFE0401C0 -#define SH7780_PCIPINT 0xFE0401CC -#define SH7780_PCIPINTM 0xFE0401D0 -#define SH7780_PCIMBR0 0xFE0401E0 -#define SH7780_PCIMBMR0 0xFE0401E4 -#define SH7780_PCIMBR1 0xFE0401E8 -#define SH7780_PCIMBMR1 0xFE0401EC -#define SH7780_PCIMBR2 0xFE0401F0 -#define SH7780_PCIMBMR2 0xFE0401F4 -#define SH7780_PCIIOBR 0xFE0401F8 -#define SH7780_PCIIOBMR 0xFE0401FC -#define SH7780_PCICSCR0 0xFE040210 -#define SH7780_PCICSCR1 0xFE040214 -#define SH7780_PCICSAR0 0xFE040218 -#define SH7780_PCICSAR1 0xFE04021C -#define SH7780_PCIPDR 0xFE040220 - -/* DMAC */ -#define DMAC_SAR0 0xFC808020 -#define DMAC_DAR0 0xFC808024 -#define DMAC_TCR0 0xFC808028 -#define DMAC_CHCR0 0xFC80802C -#define DMAC_SAR1 0xFC808030 -#define DMAC_DAR1 0xFC808034 -#define DMAC_TCR1 0xFC808038 -#define DMAC_CHCR1 0xFC80803C -#define DMAC_SAR2 0xFC808040 -#define DMAC_DAR2 0xFC808044 -#define DMAC_TCR2 0xFC808048 -#define DMAC_CHCR2 0xFC80804C -#define DMAC_SAR3 0xFC808050 -#define DMAC_DAR3 0xFC808054 -#define DMAC_TCR3 0xFC808058 -#define DMAC_CHCR3 0xFC80805C -#define DMAC_DMAOR0 0xFC808060 -#define DMAC_SAR4 0xFC808070 -#define DMAC_DAR4 0xFC808074 -#define DMAC_TCR4 0xFC808078 -#define DMAC_CHCR4 0xFC80807C -#define DMAC_SAR5 0xFC808080 -#define DMAC_DAR5 0xFC808084 -#define DMAC_TCR5 0xFC808088 -#define DMAC_CHCR5 0xFC80808C -#define DMAC_SARB0 0xFC808120 -#define DMAC_DARB0 0xFC808124 -#define DMAC_TCRB0 0xFC808128 -#define DMAC_SARB1 0xFC808130 -#define DMAC_DARB1 0xFC808134 -#define DMAC_TCRB1 0xFC808138 -#define DMAC_SARB2 0xFC808140 -#define DMAC_DARB2 0xFC808144 -#define DMAC_TCRB2 0xFC808148 -#define DMAC_SARB3 0xFC808150 -#define DMAC_DARB3 0xFC808154 -#define DMAC_TCRB3 0xFC808158 -#define DMAC_DMARS0 0xFC809000 -#define DMAC_DMARS1 0xFC809004 -#define DMAC_DMARS2 0xFC809008 -#define DMAC_SAR6 0xFC818020 -#define DMAC_DAR6 0xFC818024 -#define DMAC_TCR6 0xFC818028 -#define DMAC_CHCR6 0xFC81802C -#define DMAC_SAR7 0xFC818030 -#define DMAC_DAR7 0xFC818034 -#define DMAC_TCR7 0xFC818038 -#define DMAC_CHCR7 0xFC81803C -#define DMAC_SAR8 0xFC818040 -#define DMAC_DAR8 0xFC818044 -#define DMAC_TCR8 0xFC818048 -#define DMAC_CHCR8 0xFC81804C -#define DMAC_SAR9 0xFC818050 -#define DMAC_DAR9 0xFC818054 -#define DMAC_TCR9 0xFC818058 -#define DMAC_CHCR9 0xFC81805C -#define DMAC_DMAOR1 0xFC818060 -#define DMAC_SAR10 0xFC818070 -#define DMAC_DAR10 0xFC818074 -#define DMAC_TCR10 0xFC818078 -#define DMAC_CHCR10 0xFC81807C -#define DMAC_SAR11 0xFC818080 -#define DMAC_DAR11 0xFC818084 -#define DMAC_TCR11 0xFC818088 -#define DMAC_CHCR11 0xFC81808C -#define DMAC_SARB6 0xFC818120 -#define DMAC_DARB6 0xFC818124 -#define DMAC_TCRB6 0xFC818128 -#define DMAC_SARB7 0xFC818130 -#define DMAC_DARB7 0xFC818134 -#define DMAC_TCRB7 0xFC818138 -#define DMAC_SARB8 0xFC818140 -#define DMAC_DARB8 0xFC818144 -#define DMAC_TCRB8 0xFC818148 -#define DMAC_SARB9 0xFC818150 -#define DMAC_DARB9 0xFC818154 -#define DMAC_TCRB9 0xFC818158 - -/* Clock Pulse Generator */ -#define FRQCR 0xFFC80000 -#define PLLCR 0xFFC80024 -#define MSTPCR 0xFFC80030 - -/* Watchdog Timer and Reset */ -#define WTCNT WDTCNT -#define WDTST 0xFFCC0000 -#define WDTCSR 0xFFCC0004 -#define WDTBST 0xFFCC0008 -#define WDTCNT 0xFFCC0010 -#define WDTBCNT 0xFFCC0018 - -/* System Control */ -#define MSTPCR 0xFFC80030 - -/* Timer Unit */ -#define TSTR TSTR0 -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 -#define TCPR2 0xFFD8002C -#define TSTR1 0xFFDC0004 -#define TCOR3 0xFFDC0008 -#define TCNT3 0xFFDC000C -#define TCR3 0xFFDC0010 -#define TCOR4 0xFFDC0014 -#define TCNT4 0xFFDC0018 -#define TCR4 0xFFDC001C -#define TCOR5 0xFFDC0020 -#define TCNT5 0xFFDC0024 -#define TCR5 0xFFDC0028 - -/* Timer/Counter */ -#define CMTCFG 0xFFE30000 -#define CMTFRT 0xFFE30004 -#define CMTCTL 0xFFE30008 -#define CMTIRQS 0xFFE3000C -#define CMTCH0T 0xFFE30010 -#define CMTCH0ST 0xFFE30020 -#define CMTCH0C 0xFFE30030 -#define CMTCH1T 0xFFE30014 -#define CMTCH1ST 0xFFE30024 -#define CMTCH1C 0xFFE30034 -#define CMTCH2T 0xFFE30018 -#define CMTCH2C 0xFFE30038 -#define CMTCH3T 0xFFE3001C -#define CMTCH3C 0xFFE3003C - -/* Realtime Clock */ -#define R64CNT 0xFFE80000 -#define RSECCNT 0xFFE80004 -#define RMINCNT 0xFFE80008 -#define RHRCNT 0xFFE8000C -#define RWKCNT 0xFFE80010 -#define RDAYCNT 0xFFE80014 -#define RMONCNT 0xFFE80018 -#define RYRCNT 0xFFE8001C -#define RSECAR 0xFFE80020 -#define RMINAR 0xFFE80024 -#define RHRAR 0xFFE80028 -#define RWKAR 0xFFE8002C -#define RDAYAR 0xFFE80030 -#define RMONAR 0xFFE80034 -#define RCR1 0xFFE80038 -#define RCR2 0xFFE8003C -#define RCR3 0xFFE80050 -#define RYRAR 0xFFE80054 - -/* Serial Communication Interface with FIFO */ -#define SCIF0_BASE SCSMR0 -#define SCSMR0 0xFFE00000 -#define SCBRR0 0xFFE00004 -#define SCSCR0 0xFFE00008 -#define SCFSR0 0xFFE00010 -#define SCFCR0 0xFFE00018 -#define SCTFDR0 0xFFE0001C -#define SCRFDR0 0xFFE00020 -#define SCSPTR0 0xFFE00024 -#define SCLSR0 0xFFE00028 -#define SCRER0 0xFFE0002C -#define SCSMR1 0xFFE10000 -#define SCBRR1 0xFFE10004 -#define SCSCR1 0xFFE10008 -#define SCFSR1 0xFFE10010 -#define SCFCR1 0xFFE10018 -#define SCTFDR1 0xFFE1001C -#define SCRFDR1 0xFFE10020 -#define SCSPTR1 0xFFE10024 -#define SCLSR1 0xFFE10028 -#define SCRER1 0xFFE1002C - -/* Serial I/O with FIFO */ -#define SIMDR 0xFFE20000 -#define SISCR 0xFFE20002 -#define SITDAR 0xFFE20004 -#define SIRDAR 0xFFE20006 -#define SICDAR 0xFFE20008 -#define SICTR 0xFFE2000C -#define SIFCTR 0xFFE20010 -#define SISTR 0xFFE20014 -#define SIIER 0xFFE20016 -#define SITCR 0xFFE20028 -#define SIRCR 0xFFE2002C -#define SPICR 0xFFE20030 - -/* Serial Protocol Interface */ -#define SPCR 0xFFE50000 -#define SPSR 0xFFE50004 -#define SPSCR 0xFFE50008 -#define SPTBR 0xFFE5000C -#define SPRBR 0xFFE50010 - -/* Multimedia Card Interface */ -#define CMDR0 0xFFE60000 -#define CMDR1 0xFFE60001 -#define CMDR2 0xFFE60002 -#define CMDR3 0xFFE60003 -#define CMDR4 0xFFE60004 -#define CMDR5 0xFFE60005 -#define CMDSTRT 0xFFE60006 -#define OPCR 0xFFE6000A -#define CSTR 0xFFE6000B -#define INTCR0 0xFFE6000C -#define INTCR1 0xFFE6000D -#define INTSTR0 0xFFE6000E -#define INTSTR1 0xFFE6000F -#define CLKON 0xFFE60010 -#define CTOCR 0xFFE60011 -#define TBCR 0xFFE60014 -#define MODER 0xFFE60016 -#define CMDTYR 0xFFE60018 -#define RSPTYR 0xFFE60019 -#define TBNCR 0xFFE6001A -#define RSPR0 0xFFE60020 -#define RSPR1 0xFFE60021 -#define RSPR2 0xFFE60022 -#define RSPR3 0xFFE60023 -#define RSPR4 0xFFE60024 -#define RSPR5 0xFFE60025 -#define RSPR6 0xFFE60026 -#define RSPR7 0xFFE60027 -#define RSPR8 0xFFE60028 -#define RSPR9 0xFFE60029 -#define RSPR10 0xFFE6002A -#define RSPR11 0xFFE6002B -#define RSPR12 0xFFE6002C -#define RSPR13 0xFFE6002D -#define RSPR14 0xFFE6002E -#define RSPR15 0xFFE6002F -#define RSPR16 0xFFE60030 -#define RSPRD 0xFFE60031 -#define DTOUTR 0xFFE60032 -#define DR 0xFFE60040 -#define DMACR 0xFFE60044 -#define INTCR2 0xFFE60046 -#define INTSTR2 0xFFE60048 - -/* Audio Codec Interface */ -#define HACCR 0xFFE40008 -#define HACCSAR 0xFFE40020 -#define HACCSDR 0xFFE40024 -#define HACPCML 0xFFE40028 -#define HACPCMR 0xFFE4002C -#define HACTIER 0xFFE40050 -#define HACTSR 0xFFE40054 -#define HACRIER 0xFFE40058 -#define HACRSR 0xFFE4005C -#define HACACR 0xFFE40060 - -/* Serial Sound Interface */ -#define SSICR 0xFFE70000 -#define SSISR 0xFFE70004 -#define SSITDR 0xFFE70008 -#define SSIRDR 0xFFE7000C - -/* Flash memory Controller */ -#define FLCMNCR 0xFFE90000 -#define FLCMDCR 0xFFE90004 -#define FLCMCDR 0xFFE90008 -#define FLADR 0xFFE9000C -#define FLDATAR 0xFFE90010 -#define FLDTCNTR 0xFFE90014 -#define FLINTDMACR 0xFFE90018 -#define FLBSYTMR 0xFFE9001C -#define FLBSYCNT 0xFFE90020 -#define FLTRCR 0xFFE9002C - -/* General Purpose I/O */ -#define PACR 0xFFEA0000 -#define PBCR 0xFFEA0002 -#define PCCR 0xFFEA0004 -#define PDCR 0xFFEA0006 -#define PECR 0xFFEA0008 -#define PFCR 0xFFEA000A -#define PGCR 0xFFEA000C -#define PHCR 0xFFEA000E -#define PJCR 0xFFEA0010 -#define PKCR 0xFFEA0012 -#define PLCR 0xFFEA0014 -#define PMCR 0xFFEA0016 -#define PADR 0xFFEA0020 -#define PBDR 0xFFEA0022 -#define PCDR 0xFFEA0024 -#define PDDR 0xFFEA0026 -#define PEDR 0xFFEA0028 -#define PFDR 0xFFEA002A -#define PGDR 0xFFEA002C -#define PHDR 0xFFEA002E -#define PJDR 0xFFEA0030 -#define PKDR 0xFFEA0032 -#define PLDR 0xFFEA0034 -#define PMDR 0xFFEA0036 -#define PEPUPR 0xFFEA0048 -#define PHPUPR 0xFFEA004E -#define PJPUPR 0xFFEA0050 -#define PKPUPR 0xFFEA0052 -#define PMPUPR 0xFFEA0056 -#define PPUPR1 0xFFEA0060 -#define PPUPR2 0xFFEA0062 -#define PMSELR 0xFFEA0080 - -/* User Break Controller */ -#define CBR0 0xFF200000 -#define CRR0 0xFF200004 -#define CAR0 0xFF200008 -#define CAMR0 0xFF20000C -#define CBR1 0xFF200020 -#define CRR1 0xFF200024 -#define CAR1 0xFF200028 -#define CAMR1 0xFF20002C -#define CDR1 0xFF200030 -#define CDMR1 0xFF200034 -#define CETR1 0xFF200038 -#define CCMFR 0xFF200600 -#define CBCR 0xFF200620 - -#endif /* _ASM_CPU_SH7780_H_ */ diff --git a/include/asm-sh/cpu_sh7785.h b/include/asm-sh/cpu_sh7785.h deleted file mode 100644 index 4a4dfc9..0000000 --- a/include/asm-sh/cpu_sh7785.h +++ /dev/null @@ -1,156 +0,0 @@ -#ifndef _ASM_CPU_SH7785_H_ -#define _ASM_CPU_SH7785_H_ - -/* - * Copyright (c) 2007,2008 Nobuhiro Iwamatsu - * Copyright (c) 2008 Yusuke Goda - * Copyright (c) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#define CACHE_OC_NUM_WAYS 1 -#define CCR_CACHE_INIT 0x0000090b - -/* Exceptions */ -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 - -/* Cache Controller */ -#define CCR 0xFF00001C -#define QACR0 0xFF000038 -#define QACR1 0xFF00003C -#define RAMCR 0xFF000074 - -/* Watchdog Timer and Reset */ -#define WTCNT WDTCNT -#define WDTST 0xFFCC0000 -#define WDTCSR 0xFFCC0004 -#define WDTBST 0xFFCC0008 -#define WDTCNT 0xFFCC0010 -#define WDTBCNT 0xFFCC0018 - -/* Timer Unit */ -#define TSTR TSTR0 -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 -#define TCPR2 0xFFD8002C -#define TSTR1 0xFFDC0004 -#define TCOR3 0xFFDC0008 -#define TCNT3 0xFFDC000C -#define TCR3 0xFFDC0010 -#define TCOR4 0xFFDC0014 -#define TCNT4 0xFFDC0018 -#define TCR4 0xFFDC001C -#define TCOR5 0xFFDC0020 -#define TCNT5 0xFFDC0024 -#define TCR5 0xFFDC0028 - -/* Serial Communication Interface with FIFO */ -#define SCIF1_BASE 0xffeb0000 - -/* LBSC */ -#define MMSELR 0xfc400020 -#define LBSC_BASE 0xff800000 -#define BCR (LBSC_BASE + 0x1000) -#define CS0BCR (LBSC_BASE + 0x2000) -#define CS1BCR (LBSC_BASE + 0x2010) -#define CS2BCR (LBSC_BASE + 0x2020) -#define CS3BCR (LBSC_BASE + 0x2030) -#define CS4BCR (LBSC_BASE + 0x2040) -#define CS5BCR (LBSC_BASE + 0x2050) -#define CS6BCR (LBSC_BASE + 0x2060) -#define CS0WCR (LBSC_BASE + 0x2008) -#define CS1WCR (LBSC_BASE + 0x2018) -#define CS2WCR (LBSC_BASE + 0x2028) -#define CS3WCR (LBSC_BASE + 0x2038) -#define CS4WCR (LBSC_BASE + 0x2048) -#define CS5WCR (LBSC_BASE + 0x2058) -#define CS6WCR (LBSC_BASE + 0x2068) -#define CS5PCR (LBSC_BASE + 0x2070) -#define CS6PCR (LBSC_BASE + 0x2080) - -/* PCI Controller */ -#define SH7780_PCIECR 0xFE000008 -#define SH7780_PCIVID 0xFE040000 -#define SH7780_PCIDID 0xFE040002 -#define SH7780_PCICMD 0xFE040004 -#define SH7780_PCISTATUS 0xFE040006 -#define SH7780_PCIRID 0xFE040008 -#define SH7780_PCIPIF 0xFE040009 -#define SH7780_PCISUB 0xFE04000A -#define SH7780_PCIBCC 0xFE04000B -#define SH7780_PCICLS 0xFE04000C -#define SH7780_PCILTM 0xFE04000D -#define SH7780_PCIHDR 0xFE04000E -#define SH7780_PCIBIST 0xFE04000F -#define SH7780_PCIIBAR 0xFE040010 -#define SH7780_PCIMBAR0 0xFE040014 -#define SH7780_PCIMBAR1 0xFE040018 -#define SH7780_PCISVID 0xFE04002C -#define SH7780_PCISID 0xFE04002E -#define SH7780_PCICP 0xFE040034 -#define SH7780_PCIINTLINE 0xFE04003C -#define SH7780_PCIINTPIN 0xFE04003D -#define SH7780_PCIMINGNT 0xFE04003E -#define SH7780_PCIMAXLAT 0xFE04003F -#define SH7780_PCICID 0xFE040040 -#define SH7780_PCINIP 0xFE040041 -#define SH7780_PCIPMC 0xFE040042 -#define SH7780_PCIPMCSR 0xFE040044 -#define SH7780_PCIPMCSRBSE 0xFE040046 -#define SH7780_PCI_CDD 0xFE040047 -#define SH7780_PCICR 0xFE040100 -#define SH7780_PCILSR0 0xFE040104 -#define SH7780_PCILSR1 0xFE040108 -#define SH7780_PCILAR0 0xFE04010C -#define SH7780_PCILAR1 0xFE040110 -#define SH7780_PCIIR 0xFE040114 -#define SH7780_PCIIMR 0xFE040118 -#define SH7780_PCIAIR 0xFE04011C -#define SH7780_PCICIR 0xFE040120 -#define SH7780_PCIAINT 0xFE040130 -#define SH7780_PCIAINTM 0xFE040134 -#define SH7780_PCIBMIR 0xFE040138 -#define SH7780_PCIPAR 0xFE0401C0 -#define SH7780_PCIPINT 0xFE0401CC -#define SH7780_PCIPINTM 0xFE0401D0 -#define SH7780_PCIMBR0 0xFE0401E0 -#define SH7780_PCIMBMR0 0xFE0401E4 -#define SH7780_PCIMBR1 0xFE0401E8 -#define SH7780_PCIMBMR1 0xFE0401EC -#define SH7780_PCIMBR2 0xFE0401F0 -#define SH7780_PCIMBMR2 0xFE0401F4 -#define SH7780_PCIIOBR 0xFE0401F8 -#define SH7780_PCIIOBMR 0xFE0401FC -#define SH7780_PCICSCR0 0xFE040210 -#define SH7780_PCICSCR1 0xFE040214 -#define SH7780_PCICSAR0 0xFE040218 -#define SH7780_PCICSAR1 0xFE04021C -#define SH7780_PCIPDR 0xFE040220 - -#endif /* _ASM_CPU_SH7780_H_ */ diff --git a/include/asm-sh/errno.h b/include/asm-sh/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/include/asm-sh/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h deleted file mode 100644 index c12b855..0000000 --- a/include/asm-sh/global_data.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 - * Nobuhiro Iwamatsu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_SH_GLOBALDATA_H_ -#define __ASM_SH_GLOBALDATA_H_ - -typedef struct global_data -{ - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid */ - void **jt; /* Standalone app jump table */ -}gd_t; - -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13") - -#endif /* __ASM_SH_GLOBALDATA_H_ */ diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h deleted file mode 100644 index ca598a6..0000000 --- a/include/asm-sh/io.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - * linux/include/asm-sh/io.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions - */ -#ifndef __ASM_SH_IO_H -#define __ASM_SH_IO_H - -#ifdef __KERNEL__ - -#include -#include - -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v)) - -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v, a) __arch_putb(v, a) -#define __raw_writew(v, a) __arch_putw(v, a) -#define __raw_writel(v, a) __arch_putl(v, a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off) -#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off) -#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off) - -#define __raw_base_readb(base, off) __arch_base_getb(base, off) -#define __raw_base_readw(base, off) __arch_base_getw(base, off) -#define __raw_base_readl(base, off) __arch_base_getl(base, off) - -/* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include -#endif /* XXX###XXX */ - -/* - * IO port access primitives - * ------------------------- - * - * The SH doesn't have special IO access instructions; all IO is memory - * mapped. Note that these are defined to perform little endian accesses - * only. Their primary purpose is to access PCI and ISA peripherals. - * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * - * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. - * - * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. - */ -#define outb(v, p) __raw_writeb(v, p) -#define outw(v, p) __raw_writew(cpu_to_le16(v), p) -#define outl(v, p) __raw_writel(cpu_to_le32(v), p) - -#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) -#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) -#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) - -#define outsb(p, d, l) __raw_writesb(p, d, l) -#define outsw(p, d, l) __raw_writesw(p, d, l) -#define outsl(p, d, l) __raw_writesl(p, d, l) - -#define insb(p, d, l) __raw_readsb(p, d, l) -#define insw(p, d, l) __raw_readsw(p, d, l) -#define insl(p, d, l) __raw_readsl(p, d, l) - -#define outb_p(val, port) outb((val), (port)) -#define outw_p(val, port) outw((val), (port)) -#define outl_p(val, port) outl((val), (port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port, from, len) outsb(port, from, len) -#define outsw_p(port, from, len) outsw(port, from, len) -#define outsl_p(port, from, len) outsl(port, from, len) -#define insb_p(port, to, len) insb(port, to, len) -#define insw_p(port, to, len) insw(port, to, len) -#define insl_p(port, to, len) insl(port, to, len) - -/* for U-Boot PCI */ -#define out_8(port, val) outb(val, port) -#define out_le16(port, val) outw(val, port) -#define out_le32(port, val) outl(val, port) -#define in_8(port) inb(port) -#define in_le16(port) inw(port) -#define in_le32(port) inl(port) -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off, sz, nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off), _size, 0); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off, sz) __arch_ioremap((off), (sz), 0) -#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); - -/* - * String version of IO memory access ops: - */ -extern void _memcpy_fromio(void *, unsigned long, size_t); -extern void _memcpy_toio(unsigned long, const void *, size_t); -extern void _memset_io(unsigned long, int, size_t); - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c)\ - ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c)\ - ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v, c) __raw_writeb(v, __mem_pci(c)) -#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c)) -#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c)) - -#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l)) -#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l)) -#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l)) - -#define eth_io_copy_and_sum(s, c, l, b) \ - eth_copy_and_sum((s), __mem_pci(c), (l), (b)) - -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#elif !defined(readb) - -#define readb(addr) __raw_readb(addr) -#define readw(addr) __raw_readw(addr) -#define readl(addr) __raw_readl(addr) -#define writeb(v, addr) __raw_writeb(v, addr) -#define writew(v, addr) __raw_writew(v, addr) -#define writel(v, addr) __raw_writel(v, addr) - -#define check_signature(io, sig, len) (0) - -#endif /* __mem_pci */ - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -#endif /* __KERNEL__ */ -#endif /* __ASM_SH_IO_H */ diff --git a/include/asm-sh/irqflags.h b/include/asm-sh/irqflags.h deleted file mode 100644 index 830e548..0000000 --- a/include/asm-sh/irqflags.h +++ /dev/null @@ -1,126 +0,0 @@ -#ifndef __ASM_SH_IRQFLAGS_H -#define __ASM_SH_IRQFLAGS_H - -static inline void raw_local_irq_enable(void) -{ - unsigned long __dummy0, __dummy1; - - __asm__ __volatile__ ( - "stc sr, %0\n\t" - "and %1, %0\n\t" -#ifdef CONFIG_CPU_HAS_SR_RB - "stc r6_bank, %1\n\t" - "or %1, %0\n\t" -#endif - "ldc %0, sr\n\t" - : "=&r" (__dummy0), "=r" (__dummy1) - : "1" (~0x000000f0) - : "memory" - ); -} - -static inline void raw_local_irq_disable(void) -{ - unsigned long flags; - - __asm__ __volatile__ ( - "stc sr, %0\n\t" - "or #0xf0, %0\n\t" - "ldc %0, sr\n\t" - : "=&z" (flags) - : /* no inputs */ - : "memory" - ); -} - -static inline void set_bl_bit(void) -{ - unsigned long __dummy0, __dummy1; - - __asm__ __volatile__ ( - "stc sr, %0\n\t" - "or %2, %0\n\t" - "and %3, %0\n\t" - "ldc %0, sr\n\t" - : "=&r" (__dummy0), "=r" (__dummy1) - : "r" (0x10000000), "r" (0xffffff0f) - : "memory" - ); -} - -static inline void clear_bl_bit(void) -{ - unsigned long __dummy0, __dummy1; - - __asm__ __volatile__ ( - "stc sr, %0\n\t" - "and %2, %0\n\t" - "ldc %0, sr\n\t" - : "=&r" (__dummy0), "=r" (__dummy1) - : "1" (~0x10000000) - : "memory" - ); -} - -static inline unsigned long __raw_local_save_flags(void) -{ - unsigned long flags; - - __asm__ __volatile__ ( - "stc sr, %0\n\t" - "and #0xf0, %0\n\t" - : "=&z" (flags) - : /* no inputs */ - : "memory" - ); - - return flags; -} - -#define raw_local_save_flags(flags) \ - do { (flags) = __raw_local_save_flags(); } while (0) - -static inline int raw_irqs_disabled_flags(unsigned long flags) -{ - return (flags != 0); -} - -static inline int raw_irqs_disabled(void) -{ - unsigned long flags = __raw_local_save_flags(); - - return raw_irqs_disabled_flags(flags); -} - -static inline unsigned long __raw_local_irq_save(void) -{ - unsigned long flags, __dummy; - - __asm__ __volatile__ ( - "stc sr, %1\n\t" - "mov %1, %0\n\t" - "or #0xf0, %0\n\t" - "ldc %0, sr\n\t" - "mov %1, %0\n\t" - "and #0xf0, %0\n\t" - : "=&z" (flags), "=&r" (__dummy) - : /* no inputs */ - : "memory" - ); - - return flags; -} - -#define raw_local_irq_save(flags) \ - do { (flags) = __raw_local_irq_save(); } while (0) - -#define local_irq_save raw_local_irq_save - -static inline void raw_local_irq_restore(unsigned long flags) -{ - if ((flags & 0xf0) != 0xf0) - raw_local_irq_enable(); -} -#define local_irq_restore raw_local_irq_restore - -#endif /* __ASM_SH_IRQFLAGS_H */ diff --git a/include/asm-sh/macro.h b/include/asm-sh/macro.h deleted file mode 100644 index 2b273c3..0000000 --- a/include/asm-sh/macro.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MACRO_H__ -#define __MACRO_H__ -#ifdef __ASSEMBLY__ - -.macro write32, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.l r0, @r1 -.endm - -.macro write16, addr, data - mov.l \addr ,r1 - mov.w \data ,r0 - mov.w r0, @r1 -.endm - -.macro write8, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.b r0, @r1 -.endm - -.macro wait_timer, time - mov.l \time ,r3 -1: - nop - tst r3, r3 - bf/s 1b - dt r3 -.endm - -#endif /* __ASSEMBLY__ */ -#endif /* __MACRO_H__ */ diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h deleted file mode 100644 index 040c532..0000000 --- a/include/asm-sh/pci.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * SH4 PCI Controller (PCIC) for U-Boot. - * (C) Dustin McIntire (dustin@sensoria.com) - * (C) 2007,2008 Nobuhiro Iwamatsu - * (C) 2008 Yusuke Goda - * - * u-boot/include/asm-sh/pci.h - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _ASM_PCI_H_ -#define _ASM_PCI_H_ - -#include -#if defined(CONFIG_SH7751_PCI) -int pci_sh7751_init(struct pci_controller *hose); -#elif defined(CONFIG_SH7780_PCI) -int pci_sh7780_init(struct pci_controller *hose); -#else -#error "Not support PCI." -#endif - -int pci_sh4_init(struct pci_controller *hose); -/* PCI dword read for sh4 */ -int pci_sh4_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 *value); - -/* PCI dword write for sh4 */ -int pci_sh4_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value); - -#endif /* _ASM_PCI_H_ */ diff --git a/include/asm-sh/posix_types.h b/include/asm-sh/posix_types.h deleted file mode 100644 index c9d9fb8..0000000 --- a/include/asm-sh/posix_types.h +++ /dev/null @@ -1,123 +0,0 @@ -#ifndef __ASM_SH_POSIX_TYPES_H -#define __ASM_SH_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; -typedef unsigned short __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); -} - - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *__p) -{ - unsigned long *__tmp = __p->fds_bits; - int __i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 16: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - __tmp[ 8] = 0; __tmp[ 9] = 0; - __tmp[10] = 0; __tmp[11] = 0; - __tmp[12] = 0; __tmp[13] = 0; - __tmp[14] = 0; __tmp[15] = 0; - return; - - case 8: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - return; - - case 4: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - return; - } - } - __i = __FDSET_LONGS; - while (__i) { - __i--; - *__tmp = 0; - __tmp++; - } -} - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ - -#endif /* __ASM_SH_POSIX_TYPES_H */ diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h deleted file mode 100644 index 938a89c..0000000 --- a/include/asm-sh/processor.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_SH_PROCESSOR_H_ -#define _ASM_SH_PROCESSOR_H_ -#if defined(CONFIG_SH2) || \ - defined (CONFIG_SH2A) -# include -#elif defined (CONFIG_SH3) -# include -#elif defined (CONFIG_SH4) || \ - defined (CONFIG_SH4A) -# include -#endif -#endif diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h deleted file mode 100644 index 16252cc..0000000 --- a/include/asm-sh/ptrace.h +++ /dev/null @@ -1,112 +0,0 @@ -#ifndef __ASM_SH_PTRACE_H -#define __ASM_SH_PTRACE_H - -/* - * Copyright (C) 1999, 2000 Niibe Yutaka - * from linux kernel code. - */ - -/* - * GCC defines register number like this: - * ----------------------------- - * 0 - 15 are integer registers - * 17 - 22 are control/special registers - * 24 - 39 fp registers - * 40 - 47 xd registers - * 48 - fpscr register - * ----------------------------- - * - * We follows above, except: - * 16 --- program counter (PC) - * 22 --- syscall # - * 23 --- floating point communication register - */ -#define REG_REG0 0 -#define REG_REG15 15 - -#define REG_PC 16 - -#define REG_PR 17 -#define REG_SR 18 -#define REG_GBR 19 -#define REG_MACH 20 -#define REG_MACL 21 - -#define REG_SYSCALL 22 - -#define REG_FPREG0 23 -#define REG_FPREG15 38 -#define REG_XFREG0 39 -#define REG_XFREG15 54 - -#define REG_FPSCR 55 -#define REG_FPUL 56 - -/* options set using PTRACE_SETOPTIONS */ -#define PTRACE_O_TRACESYSGOOD 0x00000001 - -/* - * This struct defines the way the registers are stored on the - * kernel stack during a system call or other kernel entry. - */ -struct pt_regs { - unsigned long regs[16]; - unsigned long pc; - unsigned long pr; - unsigned long sr; - unsigned long gbr; - unsigned long mach; - unsigned long macl; - long tra; -}; - -/* - * This struct defines the way the DSP registers are stored on the - * kernel stack during a system call or other kernel entry. - */ -struct pt_dspregs { - unsigned long a1; - unsigned long a0g; - unsigned long a1g; - unsigned long m0; - unsigned long m1; - unsigned long a0; - unsigned long x0; - unsigned long x1; - unsigned long y0; - unsigned long y1; - unsigned long dsr; - unsigned long rs; - unsigned long re; - unsigned long mod; -}; - -#define PTRACE_GETDSPREGS 55 -#define PTRACE_SETDSPREGS 56 - -#ifdef __KERNEL__ -#define user_mode(regs) (((regs)->sr & 0x40000000)==0) -#define instruction_pointer(regs) ((regs)->pc) -extern void show_regs(struct pt_regs *); - -#ifdef CONFIG_SH_DSP -#define task_pt_regs(task) \ - ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ - - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1) -#else -#define task_pt_regs(task) \ - ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ - - sizeof(unsigned long)) - 1) -#endif - -static inline unsigned long profile_pc(struct pt_regs *regs) -{ - unsigned long pc = instruction_pointer(regs); - - if (pc >= 0xa0000000UL && pc < 0xc0000000UL) - pc -= 0x20000000; - return pc; -} -#endif - -#endif /* __ASM_SH_PTRACE_H */ diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h deleted file mode 100644 index 27d981b..0000000 --- a/include/asm-sh/string.h +++ /dev/null @@ -1,162 +0,0 @@ -#ifndef __ASM_SH_STRING_H -#define __ASM_SH_STRING_H - -/* - * Copyright (C) 1999 Niibe Yutaka - * But consider these trivial functions to be public domain. - * - * from linux kernel code. - */ - -#ifdef __KERNEL__ /* only set these up for kernel code */ - -#define __HAVE_ARCH_STRCPY -static inline char *strcpy(char *__dest, const char *__src) -{ - register char *__xdest = __dest; - unsigned long __dummy; - - __asm__ __volatile__("1:\n\t" - "mov.b @%1+, %2\n\t" - "mov.b %2, @%0\n\t" - "cmp/eq #0, %2\n\t" - "bf/s 1b\n\t" - " add #1, %0\n\t" - : "=r" (__dest), "=r" (__src), "=&z" (__dummy) - : "0" (__dest), "1" (__src) - : "memory", "t"); - - return __xdest; -} - -#define __HAVE_ARCH_STRNCPY -static inline char *strncpy(char *__dest, const char *__src, size_t __n) -{ - register char *__xdest = __dest; - unsigned long __dummy; - - if (__n == 0) - return __xdest; - - __asm__ __volatile__( - "1:\n" - "mov.b @%1+, %2\n\t" - "mov.b %2, @%0\n\t" - "cmp/eq #0, %2\n\t" - "bt/s 2f\n\t" - " cmp/eq %5,%1\n\t" - "bf/s 1b\n\t" - " add #1, %0\n" - "2:" - : "=r" (__dest), "=r" (__src), "=&z" (__dummy) - : "0" (__dest), "1" (__src), "r" (__src+__n) - : "memory", "t"); - - return __xdest; -} - -#define __HAVE_ARCH_STRCMP -static inline int strcmp(const char *__cs, const char *__ct) -{ - register int __res; - unsigned long __dummy; - - __asm__ __volatile__( - "mov.b @%1+, %3\n" - "1:\n\t" - "mov.b @%0+, %2\n\t" - "cmp/eq #0, %3\n\t" - "bt 2f\n\t" - "cmp/eq %2, %3\n\t" - "bt/s 1b\n\t" - " mov.b @%1+, %3\n\t" - "add #-2, %1\n\t" - "mov.b @%1, %3\n\t" - "sub %3, %2\n" - "2:" - : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) - : "0" (__cs), "1" (__ct) - : "t"); - - return __res; -} - -#define __HAVE_ARCH_STRNCMP -static inline int strncmp(const char *__cs, const char *__ct, size_t __n) -{ - register int __res; - unsigned long __dummy; - - if (__n == 0) - return 0; - - __asm__ __volatile__( - "mov.b @%1+, %3\n" - "1:\n\t" - "mov.b @%0+, %2\n\t" - "cmp/eq %6, %0\n\t" - "bt/s 2f\n\t" - " cmp/eq #0, %3\n\t" - "bt/s 3f\n\t" - " cmp/eq %3, %2\n\t" - "bt/s 1b\n\t" - " mov.b @%1+, %3\n\t" - "add #-2, %1\n\t" - "mov.b @%1, %3\n" - "2:\n\t" - "sub %3, %2\n" - "3:" - :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) - : "0" (__cs), "1" (__ct), "r" (__cs+__n) - : "t"); - - return __res; -} - -#undef __HAVE_ARCH_MEMSET -extern void *memset(void *__s, int __c, size_t __count); - -#undef __HAVE_ARCH_MEMCPY -extern void *memcpy(void *__to, __const__ void *__from, size_t __n); - -#undef __HAVE_ARCH_MEMMOVE -extern void *memmove(void *__dest, __const__ void *__src, size_t __n); - -#undef __HAVE_ARCH_MEMCHR -extern void *memchr(const void *__s, int __c, size_t __n); - -#undef __HAVE_ARCH_STRLEN -extern size_t strlen(const char *); - -/* arch/sh/lib/strcasecmp.c */ -extern int strcasecmp(const char *, const char *); - -#else /* KERNEL */ - -/* - * let user libraries deal with these, - * IMHO the kernel has no place defining these functions for user apps - */ - -#define __HAVE_ARCH_STRCPY 1 -#define __HAVE_ARCH_STRNCPY 1 -#define __HAVE_ARCH_STRCAT 1 -#define __HAVE_ARCH_STRNCAT 1 -#define __HAVE_ARCH_STRCMP 1 -#define __HAVE_ARCH_STRNCMP 1 -#define __HAVE_ARCH_STRNICMP 1 -#define __HAVE_ARCH_STRCHR 1 -#define __HAVE_ARCH_STRRCHR 1 -#define __HAVE_ARCH_STRSTR 1 -#define __HAVE_ARCH_STRLEN 1 -#define __HAVE_ARCH_STRNLEN 1 -#define __HAVE_ARCH_MEMSET 1 -#define __HAVE_ARCH_MEMCPY 1 -#define __HAVE_ARCH_MEMMOVE 1 -#define __HAVE_ARCH_MEMSCAN 1 -#define __HAVE_ARCH_MEMCMP 1 -#define __HAVE_ARCH_MEMCHR 1 -#define __HAVE_ARCH_STRTOK 1 - -#endif /* KERNEL */ -#endif /* __ASM_SH_STRING_H */ diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h deleted file mode 100644 index a62c422..0000000 --- a/include/asm-sh/system.h +++ /dev/null @@ -1,275 +0,0 @@ -#ifndef __ASM_SH_SYSTEM_H -#define __ASM_SH_SYSTEM_H - -/* - * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima - * Copyright (C) 2002 Paul Mundt - * - * from linux kernel code. - */ - -#include -#include - -/* - * switch_to() should switch tasks to task nr n, first - */ - -#define switch_to(prev, next, last) do { \ - struct task_struct *__last; \ - register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \ - register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \ - register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \ - register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \ - register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \ - register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \ - __asm__ __volatile__ (".balign 4\n\t" \ - "stc.l gbr, @-r15\n\t" \ - "sts.l pr, @-r15\n\t" \ - "mov.l r8, @-r15\n\t" \ - "mov.l r9, @-r15\n\t" \ - "mov.l r10, @-r15\n\t" \ - "mov.l r11, @-r15\n\t" \ - "mov.l r12, @-r15\n\t" \ - "mov.l r13, @-r15\n\t" \ - "mov.l r14, @-r15\n\t" \ - "mov.l r15, @r1 ! save SP\n\t" \ - "mov.l @r6, r15 ! change to new stack\n\t" \ - "mova 1f, %0\n\t" \ - "mov.l %0, @r2 ! save PC\n\t" \ - "mov.l 2f, %0\n\t" \ - "jmp @%0 ! call __switch_to\n\t" \ - " lds r7, pr ! with return to new PC\n\t" \ - ".balign 4\n" \ - "2:\n\t" \ - ".long __switch_to\n" \ - "1:\n\t" \ - "mov.l @r15+, r14\n\t" \ - "mov.l @r15+, r13\n\t" \ - "mov.l @r15+, r12\n\t" \ - "mov.l @r15+, r11\n\t" \ - "mov.l @r15+, r10\n\t" \ - "mov.l @r15+, r9\n\t" \ - "mov.l @r15+, r8\n\t" \ - "lds.l @r15+, pr\n\t" \ - "ldc.l @r15+, gbr\n\t" \ - : "=z" (__last) \ - : "r" (__ts1), "r" (__ts2), "r" (__ts4), \ - "r" (__ts5), "r" (__ts6), "r" (__ts7) \ - : "r3", "t"); \ - last = __last; \ -} while (0) - -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - -#ifdef CONFIG_CPU_SH4A -#define __icbi() \ -{ \ - unsigned long __addr; \ - __addr = 0xa8000000; \ - __asm__ __volatile__( \ - "icbi %0\n\t" \ - : /* no output */ \ - : "m" (__m(__addr))); \ -} -#endif - -static inline unsigned long tas(volatile int *m) -{ - unsigned long retval; - - __asm__ __volatile__ ("tas.b @%1\n\t" - "movt %0" - : "=r" (retval): "r" (m): "t", "memory"); - return retval; -} - -/* - * A brief note on ctrl_barrier(), the control register write barrier. - * - * Legacy SH cores typically require a sequence of 8 nops after - * modification of a control register in order for the changes to take - * effect. On newer cores (like the sh4a and sh5) this is accomplished - * with icbi. - * - * Also note that on sh4a in the icbi case we can forego a synco for the - * write barrier, as it's not necessary for control registers. - * - * Historically we have only done this type of barrier for the MMUCR, but - * it's also necessary for the CCR, so we make it generic here instead. - */ -#ifdef CONFIG_CPU_SH4A -#define mb() __asm__ __volatile__ ("synco": : :"memory") -#define rmb() mb() -#define wmb() __asm__ __volatile__ ("synco": : :"memory") -#define ctrl_barrier() __icbi() -#define read_barrier_depends() do { } while(0) -#else -#define mb() __asm__ __volatile__ ("": : :"memory") -#define rmb() mb() -#define wmb() __asm__ __volatile__ ("": : :"memory") -#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") -#define read_barrier_depends() do { } while(0) -#endif - -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_read_barrier_depends() read_barrier_depends() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) -#endif - -#define set_mb(var, value) do { xchg(&var, value); } while (0) - -/* - * Jump to P2 area. - * When handling TLB or caches, we need to do it from P2 area. - */ -#define jump_to_P2() \ -do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ -} while (0) - -/* - * Back to P1 area. - */ -#define back_to_P1() \ -do { \ - unsigned long __dummy; \ - ctrl_barrier(); \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ -} while (0) - -static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) -{ - unsigned long flags, retval; - - local_irq_save(flags); - retval = *m; - *m = val; - local_irq_restore(flags); - return retval; -} - -static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) -{ - unsigned long flags, retval; - - local_irq_save(flags); - retval = *m; - *m = val & 0xff; - local_irq_restore(flags); - return retval; -} - -extern void __xchg_called_with_bad_pointer(void); - -#define __xchg(ptr, x, size) \ -({ \ - unsigned long __xchg__res; \ - volatile void *__xchg_ptr = (ptr); \ - switch (size) { \ - case 4: \ - __xchg__res = xchg_u32(__xchg_ptr, x); \ - break; \ - case 1: \ - __xchg__res = xchg_u8(__xchg_ptr, x); \ - break; \ - default: \ - __xchg_called_with_bad_pointer(); \ - __xchg__res = x; \ - break; \ - } \ - \ - __xchg__res; \ -}) - -#define xchg(ptr,x) \ - ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr)))) - -static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, - unsigned long new) -{ - __u32 retval; - unsigned long flags; - - local_irq_save(flags); - retval = *m; - if (retval == old) - *m = new; - local_irq_restore(flags); /* implies memory barrier */ - return retval; -} - -/* This function doesn't exist, so you'll get a linker error - * if something tries to do an invalid cmpxchg(). */ -extern void __cmpxchg_called_with_bad_pointer(void); - -#define __HAVE_ARCH_CMPXCHG 1 - -static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, - unsigned long new, int size) -{ - switch (size) { - case 4: - return __cmpxchg_u32(ptr, old, new); - } - __cmpxchg_called_with_bad_pointer(); - return old; -} - -#define cmpxchg(ptr,o,n) \ - ({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ - (unsigned long)_n_, sizeof(*(ptr))); \ - }) - -extern void *set_exception_table_vec(unsigned int vec, void *handler); - -static inline void *set_exception_table_evt(unsigned int evt, void *handler) -{ - return set_exception_table_vec(evt >> 5, handler); -} - -/* XXX - * disable hlt during certain critical i/o operations - */ -#define HAVE_DISABLE_HLT -void disable_hlt(void); -void enable_hlt(void); - -#define arch_align_stack(x) (x) - -#endif diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h deleted file mode 100644 index aed4a6e..0000000 --- a/include/asm-sh/types.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef __ASM_SH_TYPES_H -#define __ASM_SH_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - - -typedef __signed__ char s8; -typedef unsigned char u8; - -typedef __signed__ short s16; -typedef unsigned short u16; - -typedef __signed__ int s32; -typedef unsigned int u32; - -typedef __signed__ long long s64; -typedef unsigned long long u64; - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* __ASM_SH_TYPES_H */ diff --git a/include/asm-sh/u-boot.h b/include/asm-sh/u-boot.h deleted file mode 100644 index 27d43b9..0000000 --- a/include/asm-sh/u-boot.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef __ASM_SH_U_BOOT_H_ -#define __ASM_SH_U_BOOT_H_ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned long bi_baudrate; /* Console Baudrate */ - unsigned long bi_boot_params; /* where this board expects params */ -} bd_t; - -#endif diff --git a/include/asm-sh/unaligned-sh4a.h b/include/asm-sh/unaligned-sh4a.h deleted file mode 100644 index 9f4dd25..0000000 --- a/include/asm-sh/unaligned-sh4a.h +++ /dev/null @@ -1,258 +0,0 @@ -#ifndef __ASM_SH_UNALIGNED_SH4A_H -#define __ASM_SH_UNALIGNED_SH4A_H - -/* - * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only. - * Support for 64-bit accesses are done through shifting and masking - * relative to the endianness. Unaligned stores are not supported by the - * instruction encoding, so these continue to use the packed - * struct. - * - * The same note as with the movli.l/movco.l pair applies here, as long - * as the load is gauranteed to be inlined, nothing else will hook in to - * r0 and we get the return value for free. - * - * NOTE: Due to the fact we require r0 encoding, care should be taken to - * avoid mixing these heavily with other r0 consumers, such as the atomic - * ops. Failure to adhere to this can result in the compiler running out - * of spill registers and blowing up when building at low optimization - * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777. - */ -#include -#include - -static __always_inline u32 __get_unaligned_cpu32(const u8 *p) -{ - unsigned long unaligned; - - __asm__ __volatile__ ( - "movua.l @%1, %0\n\t" - : "=z" (unaligned) - : "r" (p) - ); - - return unaligned; -} - -struct __una_u16 { u16 x __attribute__((packed)); }; -struct __una_u32 { u32 x __attribute__((packed)); }; -struct __una_u64 { u64 x __attribute__((packed)); }; - -static inline u16 __get_unaligned_cpu16(const u8 *p) -{ -#ifdef __LITTLE_ENDIAN - return p[0] | p[1] << 8; -#else - return p[0] << 8 | p[1]; -#endif -} - -/* - * Even though movua.l supports auto-increment on the read side, it can - * only store to r0 due to instruction encoding constraints, so just let - * the compiler sort it out on its own. - */ -static inline u64 __get_unaligned_cpu64(const u8 *p) -{ -#ifdef __LITTLE_ENDIAN - return (u64)__get_unaligned_cpu32(p + 4) << 32 | - __get_unaligned_cpu32(p); -#else - return (u64)__get_unaligned_cpu32(p) << 32 | - __get_unaligned_cpu32(p + 4); -#endif -} - -static inline u16 get_unaligned_le16(const void *p) -{ - return le16_to_cpu(__get_unaligned_cpu16(p)); -} - -static inline u32 get_unaligned_le32(const void *p) -{ - return le32_to_cpu(__get_unaligned_cpu32(p)); -} - -static inline u64 get_unaligned_le64(const void *p) -{ - return le64_to_cpu(__get_unaligned_cpu64(p)); -} - -static inline u16 get_unaligned_be16(const void *p) -{ - return be16_to_cpu(__get_unaligned_cpu16(p)); -} - -static inline u32 get_unaligned_be32(const void *p) -{ - return be32_to_cpu(__get_unaligned_cpu32(p)); -} - -static inline u64 get_unaligned_be64(const void *p) -{ - return be64_to_cpu(__get_unaligned_cpu64(p)); -} - -static inline void __put_le16_noalign(u8 *p, u16 val) -{ - *p++ = val; - *p++ = val >> 8; -} - -static inline void __put_le32_noalign(u8 *p, u32 val) -{ - __put_le16_noalign(p, val); - __put_le16_noalign(p + 2, val >> 16); -} - -static inline void __put_le64_noalign(u8 *p, u64 val) -{ - __put_le32_noalign(p, val); - __put_le32_noalign(p + 4, val >> 32); -} - -static inline void __put_be16_noalign(u8 *p, u16 val) -{ - *p++ = val >> 8; - *p++ = val; -} - -static inline void __put_be32_noalign(u8 *p, u32 val) -{ - __put_be16_noalign(p, val >> 16); - __put_be16_noalign(p + 2, val); -} - -static inline void __put_be64_noalign(u8 *p, u64 val) -{ - __put_be32_noalign(p, val >> 32); - __put_be32_noalign(p + 4, val); -} - -static inline void put_unaligned_le16(u16 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - ((struct __una_u16 *)p)->x = val; -#else - __put_le16_noalign(p, val); -#endif -} - -static inline void put_unaligned_le32(u32 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - ((struct __una_u32 *)p)->x = val; -#else - __put_le32_noalign(p, val); -#endif -} - -static inline void put_unaligned_le64(u64 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - ((struct __una_u64 *)p)->x = val; -#else - __put_le64_noalign(p, val); -#endif -} - -static inline void put_unaligned_be16(u16 val, void *p) -{ -#ifdef __BIG_ENDIAN - ((struct __una_u16 *)p)->x = val; -#else - __put_be16_noalign(p, val); -#endif -} - -static inline void put_unaligned_be32(u32 val, void *p) -{ -#ifdef __BIG_ENDIAN - ((struct __una_u32 *)p)->x = val; -#else - __put_be32_noalign(p, val); -#endif -} - -static inline void put_unaligned_be64(u64 val, void *p) -{ -#ifdef __BIG_ENDIAN - ((struct __una_u64 *)p)->x = val; -#else - __put_be64_noalign(p, val); -#endif -} - -/* - * Cause a link-time error if we try an unaligned access other than - * 1,2,4 or 8 bytes long - */ -extern void __bad_unaligned_access_size(void); - -#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({ \ - __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \ - __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)), \ - __bad_unaligned_access_size())))); \ - })) - -#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({ \ - __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \ - __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)), \ - __bad_unaligned_access_size())))); \ - })) - -#define __put_unaligned_le(val, ptr) ({ \ - void *__gu_p = (ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: \ - *(u8 *)__gu_p = (__force u8)(val); \ - break; \ - case 2: \ - put_unaligned_le16((__force u16)(val), __gu_p); \ - break; \ - case 4: \ - put_unaligned_le32((__force u32)(val), __gu_p); \ - break; \ - case 8: \ - put_unaligned_le64((__force u64)(val), __gu_p); \ - break; \ - default: \ - __bad_unaligned_access_size(); \ - break; \ - } \ - (void)0; }) - -#define __put_unaligned_be(val, ptr) ({ \ - void *__gu_p = (ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: \ - *(u8 *)__gu_p = (__force u8)(val); \ - break; \ - case 2: \ - put_unaligned_be16((__force u16)(val), __gu_p); \ - break; \ - case 4: \ - put_unaligned_be32((__force u32)(val), __gu_p); \ - break; \ - case 8: \ - put_unaligned_be64((__force u64)(val), __gu_p); \ - break; \ - default: \ - __bad_unaligned_access_size(); \ - break; \ - } \ - (void)0; }) - -#ifdef __LITTLE_ENDIAN -# define get_unaligned __get_unaligned_le -# define put_unaligned __put_unaligned_le -#else -# define get_unaligned __get_unaligned_be -# define put_unaligned __put_unaligned_be -#endif - -#endif /* __ASM_SH_UNALIGNED_SH4A_H */ diff --git a/include/asm-sh/unaligned.h b/include/asm-sh/unaligned.h deleted file mode 100644 index 2e0d164..0000000 --- a/include/asm-sh/unaligned.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _ASM_SH_UNALIGNED_H -#define _ASM_SH_UNALIGNED_H - -/* Copy from linux-kernel. */ - -#ifdef CONFIG_CPU_SH4A -/* SH-4A can handle unaligned loads in a relatively neutered fashion. */ -#include -#else -/* Otherwise, SH can't handle unaligned accesses. */ -#include -#if defined(__BIG_ENDIAN__) -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#elif defined(__LITTLE_ENDIAN__) -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#endif - -#include -#include -#include -#endif - -#endif /* _ASM_SH_UNALIGNED_H */ diff --git a/include/asm-sparc/arch-leon2/asi.h b/include/asm-sparc/arch-leon2/asi.h deleted file mode 100644 index 38fdd5c..0000000 --- a/include/asm-sparc/arch-leon2/asi.h +++ /dev/null @@ -1,36 +0,0 @@ -/* asi.h: Address Space Identifier values for the LEON2 sparc. - * - * Copyright (C) 2008 Daniel Hellstrom (daniel@gaisler.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _LEON2_ASI_H -#define _LEON2_ASI_H - -#define ASI_CACHEMISS 0x01 /* Force D-Cache miss on load (lda) */ -#define ASI_M_FLUSH_PROBE 0x03 /* MMU Flush/Probe */ -#define ASI_IFLUSH 0x05 /* Flush I-Cache */ -#define ASI_DFLUSH 0x06 /* Flush D-Cache */ -#define ASI_BYPASS 0x1c /* Bypass MMU (Physical address) */ -#define ASI_MMUFLUSH 0x18 /* FLUSH TLB */ -#define ASI_M_MMUREGS 0x19 /* READ/Write MMU Registers */ - -#endif /* _LEON2_ASI_H */ diff --git a/include/asm-sparc/arch-leon3/asi.h b/include/asm-sparc/arch-leon3/asi.h deleted file mode 100644 index 700b3ca..0000000 --- a/include/asm-sparc/arch-leon3/asi.h +++ /dev/null @@ -1,36 +0,0 @@ -/* asi.h: Address Space Identifier values for the LEON3 sparc. - * - * Copyright (C) 2008 Daniel Hellstrom (daniel@gaisler.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _LEON3_ASI_H -#define _LEON3_ASI_H - -#define ASI_CACHEMISS 0x01 /* Force D-Cache miss on load (lda) */ -#define ASI_M_FLUSH_PROBE 0x03 /* MMU Flush/Probe */ -#define ASI_IFLUSH 0x10 /* Flush I-Cache */ -#define ASI_DFLUSH 0x11 /* Flush D-Cache */ -#define ASI_BYPASS 0x1c /* Bypass MMU (Physical address) */ -#define ASI_MMUFLUSH 0x18 /* FLUSH TLB */ -#define ASI_M_MMUREGS 0x19 /* READ/Write MMU Registers */ - -#endif /* _LEON3_ASI_H */ diff --git a/include/asm-sparc/asi.h b/include/asm-sparc/asi.h deleted file mode 100644 index bf6d70f..0000000 --- a/include/asm-sparc/asi.h +++ /dev/null @@ -1,32 +0,0 @@ -/* Address Space Identifier (ASI) values for sparc processors. - * - * (C) Copyright 2008 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _SPARC_ASI_H -#define _SPARC_ASI_H - -/* ASI numbers are processor implementation specific */ -#include - -#endif /* _SPARC_ASI_H */ diff --git a/include/asm-sparc/asmmacro.h b/include/asm-sparc/asmmacro.h deleted file mode 100644 index aeb87ee..0000000 --- a/include/asm-sparc/asmmacro.h +++ /dev/null @@ -1,45 +0,0 @@ -/* Assembler macros for SPARC - * - * (C) Copyright 2007, taken from linux asm-sparc/asmmacro.h - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __SPARC_ASMMACRO_H__ -#define __SPARC_ASMMACRO_H__ - -#include - -/* All trap entry points _must_ begin with this macro or else you - * lose. It makes sure the kernel has a proper window so that - * c-code can be called. - */ -#define SAVE_ALL_HEAD \ - sethi %hi(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE)), %l4; \ - jmpl %l4 + %lo(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE)), %l6; -#define SAVE_ALL \ - SAVE_ALL_HEAD \ - nop; - -/* All traps low-level code here must end with this macro. */ -#define RESTORE_ALL b ret_trap_entry; clr %l6; - -#endif diff --git a/include/asm-sparc/atomic.h b/include/asm-sparc/atomic.h deleted file mode 100644 index 636498d..0000000 --- a/include/asm-sparc/atomic.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPARC atomic operations - * - * (C) Copyright 2008 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_SPARC_ATOMIC_H_ -#define _ASM_SPARC_ATOMIC_H_ - -#endif /* _ASM_SPARC_ATOMIC_H_ */ diff --git a/include/asm-sparc/bitops.h b/include/asm-sparc/bitops.h deleted file mode 100644 index ceb39f2..0000000 --- a/include/asm-sparc/bitops.h +++ /dev/null @@ -1,29 +0,0 @@ -/* Bit string operations on the SPARC - * - * (C) Copyright 2007, taken from asm-ppc/bitops.h - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _SPARC_BITOPS_H -#define _SPARC_BITOPS_H - -#endif /* _SPARC_BITOPS_H */ diff --git a/include/asm-sparc/byteorder.h b/include/asm-sparc/byteorder.h deleted file mode 100644 index b9fc656..0000000 --- a/include/asm-sparc/byteorder.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2008 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _SPARC_BYTEORDER_H -#define _SPARC_BYTEORDER_H - -#include - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -#define __BYTEORDER_HAS_U64__ -#endif -#include -#endif /* _SPARC_BYTEORDER_H */ diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h deleted file mode 100644 index 03e8d94..0000000 --- a/include/asm-sparc/cache.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2008, - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __SPARC_CACHE_H__ -#define __SPARC_CACHE_H__ - -#include -#include - -#endif diff --git a/include/asm-sparc/config.h b/include/asm-sparc/config.h deleted file mode 100644 index 36438be..0000000 --- a/include/asm-sparc/config.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -#define CONFIG_LMB - -#endif diff --git a/include/asm-sparc/errno.h b/include/asm-sparc/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/include/asm-sparc/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-sparc/global_data.h b/include/asm-sparc/global_data.h deleted file mode 100644 index dea2857..0000000 --- a/include/asm-sparc/global_data.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H - -#include "asm/types.h" - -/* - * The following data structure is placed in some memory wich is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct global_data { - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long bus_clk; - - phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ - unsigned long reset_status; /* reset status register at boot */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long have_console; /* serial_init() was called */ - -#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) - unsigned long fb_base; /* Base address of framebuffer memory */ -#endif -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - unsigned long post_log_word; /* Record POST activities */ - unsigned long post_init_f_time; /* When post_init_f started */ -#endif -#ifdef CONFIG_BOARD_TYPES - unsigned long board_type; -#endif -#ifdef CONFIG_MODEM_SUPPORT - unsigned long do_mdm_init; - unsigned long be_quiet; -#endif -#ifdef CONFIG_LWMON - unsigned long kbd_status; -#endif - void **jt; /* jump table */ -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("%g7") - -#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-sparc/io.h b/include/asm-sparc/io.h deleted file mode 100644 index 0c5d86c..0000000 --- a/include/asm-sparc/io.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPARC I/O definitions - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _SPARC_IO_H -#define _SPARC_IO_H - -/* Nothing to sync, total store ordering (TSO)... */ -#define sync() - -/* Forces a cache miss on read/load. - * On some architectures we need to bypass the cache when reading - * I/O registers so that we are not reading the same status word - * over and over again resulting in a hang (until an IRQ if lucky) - * - */ -#ifndef CONFIG_SYS_HAS_NO_CACHE -#define READ_BYTE(var) SPARC_NOCACHE_READ_BYTE((unsigned int)(var)) -#define READ_HWORD(var) SPARC_NOCACHE_READ_HWORD((unsigned int)(var)) -#define READ_WORD(var) SPARC_NOCACHE_READ((unsigned int)(var)) -#define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)(var)) -#else -#define READ_BYTE(var) (var) -#define READ_HWORD(var) (var) -#define READ_WORD(var) (var) -#define READ_DWORD(var) (var) -#endif - -/* - * Generic virtual read/write. - */ -#define __arch_getb(a) (READ_BYTE(a)) -#define __arch_getw(a) (READ_HWORD(a)) -#define __arch_getl(a) (READ_WORD(a)) -#define __arch_getq(a) (READ_DWORD(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) -#define __raw_readq(a) __arch_getq(a) - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ - -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void *map_physmem(phys_addr_t paddr, unsigned long len, - unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -#endif diff --git a/include/asm-sparc/irq.h b/include/asm-sparc/irq.h deleted file mode 100644 index c5538c0..0000000 --- a/include/asm-sparc/irq.h +++ /dev/null @@ -1,49 +0,0 @@ -/* IRQ functions - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __SPARC_IRQ_H__ -#define __SPARC_IRQ_H__ - -#include - -/* Set SPARC Processor Interrupt Level */ -extern inline void set_pil(unsigned int level) -{ - unsigned int psr = get_psr(); - - put_psr((psr & ~PSR_PIL) | ((level & 0xf) << PSR_PIL_OFS)); -} - -/* Get SPARC Processor Interrupt Level */ -extern inline unsigned int get_pil(void) -{ - unsigned int psr = get_psr(); - return (psr & PSR_PIL) >> PSR_PIL_OFS; -} - -/* Disables interrupts and return current PIL value */ -extern int intLock(void); - -/* Sets the PIL to oldLevel */ -extern void intUnlock(int oldLevel); - -#endif diff --git a/include/asm-sparc/leon.h b/include/asm-sparc/leon.h deleted file mode 100644 index f7175ee..0000000 --- a/include/asm-sparc/leon.h +++ /dev/null @@ -1,42 +0,0 @@ -/* LEON Header File select - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __ASM_LEON_H__ -#define __ASM_LEON_H__ - -#if defined(CONFIG_LEON3) - -#include - -#elif defined(CONFIG_LEON2) - -#include - -#else - -#error Unknown LEON processor - -#endif - -/* Common stuff */ - -#endif diff --git a/include/asm-sparc/leon2.h b/include/asm-sparc/leon2.h deleted file mode 100644 index fa55cad..0000000 --- a/include/asm-sparc/leon2.h +++ /dev/null @@ -1,236 +0,0 @@ -/* LEON2 header file. LEON2 is a SOC processor. - * - * (C) Copyright 2008 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __LEON2_H__ -#define __LEON2_H__ - -#ifdef CONFIG_LEON2 - -/* LEON 2 I/O register definitions */ -#define LEON2_PREGS 0x80000000 -#define LEON2_MCFG1 0x00 -#define LEON2_MCFG2 0x04 -#define LEON2_ECTRL 0x08 -#define LEON2_FADDR 0x0C -#define LEON2_MSTAT 0x10 -#define LEON2_CCTRL 0x14 -#define LEON2_PWDOWN 0x18 -#define LEON2_WPROT1 0x1C -#define LEON2_WPROT2 0x20 -#define LEON2_LCONF 0x24 -#define LEON2_TCNT0 0x40 -#define LEON2_TRLD0 0x44 -#define LEON2_TCTRL0 0x48 -#define LEON2_TCNT1 0x50 -#define LEON2_TRLD1 0x54 -#define LEON2_TCTRL1 0x58 -#define LEON2_SCNT 0x60 -#define LEON2_SRLD 0x64 -#define LEON2_UART0 0x70 -#define LEON2_UDATA0 0x70 -#define LEON2_USTAT0 0x74 -#define LEON2_UCTRL0 0x78 -#define LEON2_USCAL0 0x7C -#define LEON2_UART1 0x80 -#define LEON2_UDATA1 0x80 -#define LEON2_USTAT1 0x84 -#define LEON2_UCTRL1 0x88 -#define LEON2_USCAL1 0x8C -#define LEON2_IMASK 0x90 -#define LEON2_IPEND 0x94 -#define LEON2_IFORCE 0x98 -#define LEON2_ICLEAR 0x9C -#define LEON2_IOREG 0xA0 -#define LEON2_IODIR 0xA4 -#define LEON2_IOICONF 0xA8 -#define LEON2_IPEND2 0xB0 -#define LEON2_IMASK2 0xB4 -#define LEON2_ISTAT2 0xB8 -#define LEON2_ICLEAR2 0xBC - -#ifndef __ASSEMBLER__ -/* - * Structure for LEON memory mapped registers. - * - * Source: Section 6.1 - On-chip registers - * - * NOTE: There is only one of these structures per CPU, its base address - * is 0x80000000, and the variable LEON_REG is placed there by the - * linkcmds file. - */ -typedef struct { - volatile unsigned int Memory_Config_1; - volatile unsigned int Memory_Config_2; - volatile unsigned int Edac_Control; - volatile unsigned int Failed_Address; - volatile unsigned int Memory_Status; - volatile unsigned int Cache_Control; - volatile unsigned int Power_Down; - volatile unsigned int Write_Protection_1; - volatile unsigned int Write_Protection_2; - volatile unsigned int Leon_Configuration; - volatile unsigned int dummy2; - volatile unsigned int dummy3; - volatile unsigned int dummy4; - volatile unsigned int dummy5; - volatile unsigned int dummy6; - volatile unsigned int dummy7; - volatile unsigned int Timer_Counter_1; - volatile unsigned int Timer_Reload_1; - volatile unsigned int Timer_Control_1; - volatile unsigned int Watchdog; - volatile unsigned int Timer_Counter_2; - volatile unsigned int Timer_Reload_2; - volatile unsigned int Timer_Control_2; - volatile unsigned int dummy8; - volatile unsigned int Scaler_Counter; - volatile unsigned int Scaler_Reload; - volatile unsigned int dummy9; - volatile unsigned int dummy10; - volatile unsigned int UART_Channel_1; - volatile unsigned int UART_Status_1; - volatile unsigned int UART_Control_1; - volatile unsigned int UART_Scaler_1; - volatile unsigned int UART_Channel_2; - volatile unsigned int UART_Status_2; - volatile unsigned int UART_Control_2; - volatile unsigned int UART_Scaler_2; - volatile unsigned int Interrupt_Mask; - volatile unsigned int Interrupt_Pending; - volatile unsigned int Interrupt_Force; - volatile unsigned int Interrupt_Clear; - volatile unsigned int PIO_Data; - volatile unsigned int PIO_Direction; - volatile unsigned int PIO_Interrupt; -} LEON2_regs; - -typedef struct { - volatile unsigned int UART_Channel; - volatile unsigned int UART_Status; - volatile unsigned int UART_Control; - volatile unsigned int UART_Scaler; -} LEON2_Uart_regs; - -#endif - -/* - * The following constants are intended to be used ONLY in assembly - * language files. - * - * NOTE: The intended style of usage is to load the address of LEON REGS - * into a register and then use these as displacements from - * that register. - */ -#define LEON_REG_MEMCFG1_OFFSET 0x00 -#define LEON_REG_MEMCFG2_OFFSET 0x04 -#define LEON_REG_EDACCTRL_OFFSET 0x08 -#define LEON_REG_FAILADDR_OFFSET 0x0C -#define LEON_REG_MEMSTATUS_OFFSET 0x10 -#define LEON_REG_CACHECTRL_OFFSET 0x14 -#define LEON_REG_POWERDOWN_OFFSET 0x18 -#define LEON_REG_WRITEPROT1_OFFSET 0x1C -#define LEON_REG_WRITEPROT2_OFFSET 0x20 -#define LEON_REG_LEONCONF_OFFSET 0x24 -#define LEON_REG_UNIMPLEMENTED_2_OFFSET 0x28 -#define LEON_REG_UNIMPLEMENTED_3_OFFSET 0x2C -#define LEON_REG_UNIMPLEMENTED_4_OFFSET 0x30 -#define LEON_REG_UNIMPLEMENTED_5_OFFSET 0x34 -#define LEON_REG_UNIMPLEMENTED_6_OFFSET 0x38 -#define LEON_REG_UNIMPLEMENTED_7_OFFSET 0x3C -#define LEON_REG_TIMERCNT1_OFFSET 0x40 -#define LEON_REG_TIMERLOAD1_OFFSET 0x44 -#define LEON_REG_TIMERCTRL1_OFFSET 0x48 -#define LEON_REG_WDOG_OFFSET 0x4C -#define LEON_REG_TIMERCNT2_OFFSET 0x50 -#define LEON_REG_TIMERLOAD2_OFFSET 0x54 -#define LEON_REG_TIMERCTRL2_OFFSET 0x58 -#define LEON_REG_UNIMPLEMENTED_8_OFFSET 0x5C -#define LEON_REG_SCALERCNT_OFFSET 0x60 -#define LEON_REG_SCALER_LOAD_OFFSET 0x64 -#define LEON_REG_UNIMPLEMENTED_9_OFFSET 0x68 -#define LEON_REG_UNIMPLEMENTED_10_OFFSET 0x6C -#define LEON_REG_UARTDATA1_OFFSET 0x70 -#define LEON_REG_UARTSTATUS1_OFFSET 0x74 -#define LEON_REG_UARTCTRL1_OFFSET 0x78 -#define LEON_REG_UARTSCALER1_OFFSET 0x7C -#define LEON_REG_UARTDATA2_OFFSET 0x80 -#define LEON_REG_UARTSTATUS2_OFFSET 0x84 -#define LEON_REG_UARTCTRL2_OFFSET 0x88 -#define LEON_REG_UARTSCALER2_OFFSET 0x8C -#define LEON_REG_IRQMASK_OFFSET 0x90 -#define LEON_REG_IRQPEND_OFFSET 0x94 -#define LEON_REG_IRQFORCE_OFFSET 0x98 -#define LEON_REG_IRQCLEAR_OFFSET 0x9C -#define LEON_REG_PIODATA_OFFSET 0xA0 -#define LEON_REG_PIODIR_OFFSET 0xA4 -#define LEON_REG_PIOIRQ_OFFSET 0xA8 -#define LEON_REG_SIM_RAM_SIZE_OFFSET 0xF4 -#define LEON_REG_SIM_ROM_SIZE_OFFSET 0xF8 - -/* - * Interrupt Sources - * - * The interrupt source numbers directly map to the trap type and to - * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - */ -#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1 -#define LEON_INTERRUPT_UART_1_RX_TX 2 -#define LEON_INTERRUPT_UART_0_RX_TX 3 -#define LEON_INTERRUPT_EXTERNAL_0 4 -#define LEON_INTERRUPT_EXTERNAL_1 5 -#define LEON_INTERRUPT_EXTERNAL_2 6 -#define LEON_INTERRUPT_EXTERNAL_3 7 -#define LEON_INTERRUPT_TIMER1 8 -#define LEON_INTERRUPT_TIMER2 9 -#define LEON_INTERRUPT_EMPTY1 10 -#define LEON_INTERRUPT_EMPTY2 11 -#define LEON_INTERRUPT_OPEN_ETH 12 -#define LEON_INTERRUPT_EMPTY4 13 -#define LEON_INTERRUPT_EMPTY5 14 -#define LEON_INTERRUPT_EMPTY6 15 - -/* Timer Bits */ -#define LEON2_TIMER_CTRL_EN 0x1 /* Timer enable */ -#define LEON2_TIMER_CTRL_RS 0x2 /* Timer reStart */ -#define LEON2_TIMER_CTRL_LD 0x4 /* Timer reLoad */ -#define LEON2_TIMER1_IRQNO 8 /* Timer 1 IRQ number */ -#define LEON2_TIMER2_IRQNO 9 /* Timer 2 IRQ number */ -#define LEON2_TIMER1_IE (1< for GRLIB timers, interrupt - * ctrl, memory controllers etc. - */ - -#endif diff --git a/include/asm-sparc/machines.h b/include/asm-sparc/machines.h deleted file mode 100644 index 1e26195..0000000 --- a/include/asm-sparc/machines.h +++ /dev/null @@ -1,92 +0,0 @@ -/* machines.h: Defines for taking apart the machine type value in the - * idprom and determining the kind of machine we are on. - * - * Taken from the SPARC port of Linux. - * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __SPARC_MACHINES_H__ -#define __SPARC_MACHINES_H__ - -struct Sun_Machine_Models { - char *name; - unsigned char id_machtype; -}; - -/* Current number of machines we know about that has an IDPROM - * machtype entry including one entry for the 0x80 OBP machines. - */ -#define NUM_SUN_MACHINES 16 - -extern struct Sun_Machine_Models Sun_Machines[NUM_SUN_MACHINES]; - -/* The machine type in the idprom area looks like this: - * - * --------------- - * | ARCH | MACH | - * --------------- - * 7 4 3 0 - * - * The ARCH field determines the architecture line (sun4, sun4c, etc). - * The MACH field determines the machine make within that architecture. - */ - -#define SM_ARCH_MASK 0xf0 -#define SM_SUN4 0x20 -#define M_LEON2 0x30 -#define SM_SUN4C 0x50 -#define SM_SUN4M 0x70 -#define SM_SUN4M_OBP 0x80 - -#define SM_TYP_MASK 0x0f -/* Sun4 machines */ -#define SM_4_260 0x01 /* Sun 4/200 series */ -#define SM_4_110 0x02 /* Sun 4/100 series */ -#define SM_4_330 0x03 /* Sun 4/300 series */ -#define SM_4_470 0x04 /* Sun 4/400 series */ - -/* Leon machines */ -#define M_LEON2_SOC 0x01 /* Leon2 SoC */ - -/* Sun4c machines Full Name - PROM NAME */ -#define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */ -#define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */ -#define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */ -#define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */ -#define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */ -#define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */ -#define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */ - -/* Sun4m machines, these predate the OpenBoot. These values only mean - * something if the value in the ARCH field is SM_SUN4M, if it is - * SM_SUN4M_OBP then you have the following situation: - * 1) You either have a sun4d, a sun4e, or a recently made sun4m. - * 2) You have to consult OpenBoot to determine which machine this is. - */ -#define SM_4M_SS60 0x01 /* Sun4m SparcSystem 600 */ -#define SM_4M_SS50 0x02 /* Sun4m SparcStation 10 */ -#define SM_4M_SS40 0x03 /* Sun4m SparcStation 5 */ - -/* Sun4d machines -- N/A */ -/* Sun4e machines -- N/A */ -/* Sun4u machines -- N/A */ - -#endif /* !(_SPARC_MACHINES_H) */ diff --git a/include/asm-sparc/page.h b/include/asm-sparc/page.h deleted file mode 100644 index 484953a..0000000 --- a/include/asm-sparc/page.h +++ /dev/null @@ -1,43 +0,0 @@ -/* page.h: Various defines and such for MMU operations on the Sparc for - * the Linux kernel. - * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _SPARC_PAGE_H -#define _SPARC_PAGE_H - -#include -#ifdef CONFIG_SUN4 -#define PAGE_SHIFT 13 -#else -#define PAGE_SHIFT 12 -#endif - -#ifndef __ASSEMBLY__ -/* I have my suspicions... -DaveM */ -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#else -#define PAGE_SIZE (1 << PAGE_SHIFT) -#endif - -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#endif /* _SPARC_PAGE_H */ diff --git a/include/asm-sparc/posix_types.h b/include/asm-sparc/posix_types.h deleted file mode 100644 index 8d98b2a..0000000 --- a/include/asm-sparc/posix_types.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2000 - 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007, taken from asm-ppc/posix_types.h - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __SPARC_POSIX_TYPES_H__ -#define __SPARC_POSIX_TYPES_H__ - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned int __kernel_dev_t; -typedef unsigned int __kernel_ino_t; -typedef unsigned int __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned int __kernel_uid_t; -typedef unsigned int __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef long __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char *__kernel_caddr_t; -typedef short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned int __kernel_old_uid_t; -typedef unsigned int __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { - int val[2]; -} __kernel_fsid_t; - -#ifndef __GNUC__ - -#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) -#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) -#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) -#define __FD_ZERO(set) \ - ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set))) - -#else /* __GNUC__ */ - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ - || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) -/* With GNU C, use inline functions instead so args are evaluated only once: */ - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set * fdsetp) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - fdsetp->fds_bits[_tmp] |= (1UL << _rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set * fdsetp) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - fdsetp->fds_bits[_tmp] &= ~(1UL << _rem); -} - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set * p) -{ - unsigned long _tmp = fd / __NFDBITS; - unsigned long _rem = fd % __NFDBITS; - return (p->fds_bits[_tmp] & (1UL << _rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set * p) -{ - unsigned int *tmp = (unsigned int *)p->fds_bits; - int i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 8: - tmp[0] = 0; - tmp[1] = 0; - tmp[2] = 0; - tmp[3] = 0; - tmp[4] = 0; - tmp[5] = 0; - tmp[6] = 0; - tmp[7] = 0; - return; - } - } - i = __FDSET_LONGS; - while (i) { - i--; - *tmp = 0; - tmp++; - } -} - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ -#endif /* __GNUC__ */ -#endif /* _SPARC_POSIX_TYPES_H */ diff --git a/include/asm-sparc/processor.h b/include/asm-sparc/processor.h deleted file mode 100644 index d518389..0000000 --- a/include/asm-sparc/processor.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPARC Processor specifics - * taken from the SPARC port of Linux (ptrace.h). - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __ASM_SPARC_PROCESSOR_H -#define __ASM_SPARC_PROCESSOR_H - -#include - -#ifdef CONFIG_LEON - -/* All LEON processors supported */ -#include - -#else -/* other processors */ -#error Unknown SPARC Processor -#endif - -#ifndef __ASSEMBLY__ - -/* flush data cache */ -static __inline__ void sparc_dcache_flush_all(void) -{ - __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory"); -} - -/* flush instruction cache */ -static __inline__ void sparc_icache_flush_all(void) -{ - __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_IFLUSH):"memory"); -} - -/* do a cache miss load */ -static __inline__ unsigned long long sparc_load_reg_cachemiss_qword(unsigned - long paddr) -{ - unsigned long long retval; - __asm__ __volatile__("ldda [%1] %2, %0\n\t": - "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS)); - return retval; -} - -static __inline__ unsigned long sparc_load_reg_cachemiss(unsigned long paddr) -{ - unsigned long retval; - __asm__ __volatile__("lda [%1] %2, %0\n\t": - "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS)); - return retval; -} - -static __inline__ unsigned short sparc_load_reg_cachemiss_word(unsigned long - paddr) -{ - unsigned short retval; - __asm__ __volatile__("lduha [%1] %2, %0\n\t": - "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS)); - return retval; -} - -static __inline__ unsigned char sparc_load_reg_cachemiss_byte(unsigned long - paddr) -{ - unsigned char retval; - __asm__ __volatile__("lduba [%1] %2, %0\n\t": - "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS)); - return retval; -} - -/* do a physical address bypass write, i.e. for 0x80000000 */ -static __inline__ void sparc_store_reg_bypass(unsigned long paddr, - unsigned long value) -{ - __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(value), "r"(paddr), - "i"(ASI_BYPASS):"memory"); -} - -static __inline__ unsigned long sparc_load_reg_bypass(unsigned long paddr) -{ - unsigned long retval; - __asm__ __volatile__("lda [%1] %2, %0\n\t": - "=r"(retval):"r"(paddr), "i"(ASI_BYPASS)); - return retval; -} - -/* Macros for bypassing cache when reading */ -#define SPARC_NOCACHE_READ_DWORD(address) sparc_load_reg_cachemiss_qword((unsigned int)(address)) -#define SPARC_NOCACHE_READ(address) sparc_load_reg_cachemiss((unsigned int)(address)) -#define SPARC_NOCACHE_READ_HWORD(address) sparc_load_reg_cachemiss_word((unsigned int)(address)) -#define SPARC_NOCACHE_READ_BYTE(address) sparc_load_reg_cachemiss_byte((unsigned int)(address)) - -#define SPARC_BYPASS_READ(address) sparc_load_reg_bypass((unsigned int)(address)) -#define SPARC_BYPASS_WRITE(address,value) sparc_store_reg_bypass((unsigned int)(address),(unsigned int)(value)) - -#endif - -#endif /* __ASM_SPARC_PROCESSOR_H */ diff --git a/include/asm-sparc/prom.h b/include/asm-sparc/prom.h deleted file mode 100644 index d55cc86..0000000 --- a/include/asm-sparc/prom.h +++ /dev/null @@ -1,297 +0,0 @@ -/* OpenProm defines mainly taken from linux kernel header files - * - * openprom.h: Prom structures and defines for access to the OPENBOOT - * prom routines and data areas. - * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __SPARC_OPENPROM_H__ -#define __SPARC_OPENPROM_H__ - -/* Empirical constants... */ -#define LINUX_OPPROM_MAGIC 0x10010407 - -#ifndef __ASSEMBLY__ -/* V0 prom device operations. */ -struct linux_dev_v0_funcs { - int (*v0_devopen) (char *device_str); - int (*v0_devclose) (int dev_desc); - int (*v0_rdblkdev) (int dev_desc, int num_blks, int blk_st, char *buf); - int (*v0_wrblkdev) (int dev_desc, int num_blks, int blk_st, char *buf); - int (*v0_wrnetdev) (int dev_desc, int num_bytes, char *buf); - int (*v0_rdnetdev) (int dev_desc, int num_bytes, char *buf); - int (*v0_rdchardev) (int dev_desc, int num_bytes, int dummy, char *buf); - int (*v0_wrchardev) (int dev_desc, int num_bytes, int dummy, char *buf); - int (*v0_seekdev) (int dev_desc, long logical_offst, int from); -}; - -/* V2 and later prom device operations. */ -struct linux_dev_v2_funcs { - int (*v2_inst2pkg) (int d); /* Convert ihandle to phandle */ - char *(*v2_dumb_mem_alloc) (char *va, unsigned sz); - void (*v2_dumb_mem_free) (char *va, unsigned sz); - - /* To map devices into virtual I/O space. */ - char *(*v2_dumb_mmap) (char *virta, int which_io, unsigned paddr, - unsigned sz); - void (*v2_dumb_munmap) (char *virta, unsigned size); - - int (*v2_dev_open) (char *devpath); - void (*v2_dev_close) (int d); - int (*v2_dev_read) (int d, char *buf, int nbytes); - int (*v2_dev_write) (int d, char *buf, int nbytes); - int (*v2_dev_seek) (int d, int hi, int lo); - - /* Never issued (multistage load support) */ - void (*v2_wheee2) (void); - void (*v2_wheee3) (void); -}; - -struct linux_mlist_v0 { - struct linux_mlist_v0 *theres_more; - char *start_adr; - unsigned num_bytes; -}; - -struct linux_mem_v0 { - struct linux_mlist_v0 **v0_totphys; - struct linux_mlist_v0 **v0_prommap; - struct linux_mlist_v0 **v0_available; /* What we can use */ -}; - -/* Arguments sent to the kernel from the boot prompt. */ -struct linux_arguments_v0 { - char *argv[8]; - char args[100]; - char boot_dev[2]; - int boot_dev_ctrl; - int boot_dev_unit; - int dev_partition; - char *kernel_file_name; - void *aieee1; /* XXX */ -}; - -/* V2 and up boot things. */ -struct linux_bootargs_v2 { - char **bootpath; - char **bootargs; - int *fd_stdin; - int *fd_stdout; -}; - -/* The top level PROM vector. */ -struct linux_romvec { - /* Version numbers. */ - unsigned int pv_magic_cookie; - unsigned int pv_romvers; - unsigned int pv_plugin_revision; - unsigned int pv_printrev; - - /* Version 0 memory descriptors. */ - struct linux_mem_v0 pv_v0mem; - - /* Node operations. */ - struct linux_nodeops *pv_nodeops; - - char **pv_bootstr; - struct linux_dev_v0_funcs pv_v0devops; - - char *pv_stdin; - char *pv_stdout; -#define PROMDEV_KBD 0 /* input from keyboard */ -#define PROMDEV_SCREEN 0 /* output to screen */ -#define PROMDEV_TTYA 1 /* in/out to ttya */ -#define PROMDEV_TTYB 2 /* in/out to ttyb */ - - /* Blocking getchar/putchar. NOT REENTRANT! (grr) */ - int (*pv_getchar) (void); - void (*pv_putchar) (int ch); - - /* Non-blocking variants. */ - int (*pv_nbgetchar) (void); - int (*pv_nbputchar) (int ch); - - void (*pv_putstr) (char *str, int len); - - /* Miscellany. */ - void (*pv_reboot) (char *bootstr); - void (*pv_printf) (__const__ char *fmt, ...); - void (*pv_abort) (void); - __volatile__ int *pv_ticks; - void (*pv_halt) (void); - void (**pv_synchook) (void); - - /* Evaluate a forth string, not different proto for V0 and V2->up. */ - union { - void (*v0_eval) (int len, char *str); - void (*v2_eval) (char *str); - } pv_fortheval; - - struct linux_arguments_v0 **pv_v0bootargs; - - /* Get ether address. */ - unsigned int (*pv_enaddr) (int d, char *enaddr); - - struct linux_bootargs_v2 pv_v2bootargs; - struct linux_dev_v2_funcs pv_v2devops; - - int filler[15]; - - /* This one is sun4c/sun4 only. */ - void (*pv_setctxt) (int ctxt, char *va, int pmeg); - - /* Prom version 3 Multiprocessor routines. This stuff is crazy. - * No joke. Calling these when there is only one cpu probably - * crashes the machine, have to test this. :-) - */ - - /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context - * 'thiscontext' executing at address 'prog_counter' - */ - int (*v3_cpustart) (unsigned int whichcpu, int ctxtbl_ptr, - int thiscontext, char *prog_counter); - - /* v3_cpustop() will cause cpu 'whichcpu' to stop executing - * until a resume cpu call is made. - */ - int (*v3_cpustop) (unsigned int whichcpu); - - /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or - * resume cpu call is made. - */ - int (*v3_cpuidle) (unsigned int whichcpu); - - /* v3_cpuresume() will resume processor 'whichcpu' executing - * starting with whatever 'pc' and 'npc' were left at the - * last 'idle' or 'stop' call. - */ - int (*v3_cpuresume) (unsigned int whichcpu); -}; - -/* Routines for traversing the prom device tree. */ -struct linux_nodeops { - int (*no_nextnode) (int node); - int (*no_child) (int node); - int (*no_proplen) (int node, char *name); - int (*no_getprop) (int node, char *name, char *val); - int (*no_setprop) (int node, char *name, char *val, int len); - char *(*no_nextprop) (int node, char *name); -}; - -/* More fun PROM structures for device probing. */ -#define PROMREG_MAX 16 -#define PROMVADDR_MAX 16 -#define PROMINTR_MAX 15 - -struct linux_prom_registers { - unsigned int which_io; /* is this in OBIO space? */ - unsigned int phys_addr; /* The physical address of this register */ - unsigned int reg_size; /* How many bytes does this register take up? */ -}; - -struct linux_prom_irqs { - int pri; /* IRQ priority */ - int vector; /* This is foobar, what does it do? */ -}; - -/* Element of the "ranges" vector */ -struct linux_prom_ranges { - unsigned int ot_child_space; - unsigned int ot_child_base; /* Bus feels this */ - unsigned int ot_parent_space; - unsigned int ot_parent_base; /* CPU looks from here */ - unsigned int or_size; -}; - -/* Ranges and reg properties are a bit different for PCI. */ -struct linux_prom_pci_registers { - /* - * We don't know what information this field contain. - * We guess, PCI device function is in bits 15:8 - * So, ... - */ - unsigned int which_io; /* Let it be which_io */ - - unsigned int phys_hi; - unsigned int phys_lo; - - unsigned int size_hi; - unsigned int size_lo; -}; - -struct linux_prom_pci_ranges { - unsigned int child_phys_hi; /* Only certain bits are encoded here. */ - unsigned int child_phys_mid; - unsigned int child_phys_lo; - - unsigned int parent_phys_hi; - unsigned int parent_phys_lo; - - unsigned int size_hi; - unsigned int size_lo; -}; - -struct linux_prom_pci_assigned_addresses { - unsigned int which_io; - - unsigned int phys_hi; - unsigned int phys_lo; - - unsigned int size_hi; - unsigned int size_lo; -}; - -struct linux_prom_ebus_ranges { - unsigned int child_phys_hi; - unsigned int child_phys_lo; - - unsigned int parent_phys_hi; - unsigned int parent_phys_mid; - unsigned int parent_phys_lo; - - unsigned int size; -}; - -/* Offset into the EEPROM where the id PROM is located on the 4c */ -#define IDPROM_OFFSET 0x7d8 - -/* On sun4m; physical. */ -/* MicroSPARC(-II) does not decode 31rd bit, but it works. */ -#define IDPROM_OFFSET_M 0xfd8 - -struct idprom { - unsigned char id_format; /* Format identifier (always 0x01) */ - unsigned char id_machtype; /* Machine type */ - unsigned char id_ethaddr[6]; /* Hardware ethernet address */ - long id_date; /* Date of manufacture */ - unsigned int id_sernum:24; /* Unique serial number */ - unsigned char id_cksum; /* Checksum - xor of the data bytes */ - unsigned char reserved[16]; -}; - -extern struct idprom *idprom; -extern void idprom_init(void); - -#define IDPROM_SIZE (sizeof(struct idprom)) - -#endif /* !(__ASSEMBLY__) */ - -#endif diff --git a/include/asm-sparc/psr.h b/include/asm-sparc/psr.h deleted file mode 100644 index fc77947..0000000 --- a/include/asm-sparc/psr.h +++ /dev/null @@ -1,97 +0,0 @@ -/* psr.h: This file holds the macros for masking off various parts of - * the processor status register on the Sparc. This is valid - * for Version 8. On the V9 this is renamed to the PSTATE - * register and its members are accessed as fields like - * PSTATE.PRIV for the current CPU privilege level. - * - * taken from the SPARC port of Linux, - * - * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __SPARC_PSR_H__ -#define __SPARC_PSR_H__ - -/* The Sparc PSR fields are laid out as the following: - * - * ------------------------------------------------------------------------ - * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP | - * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 | - * ------------------------------------------------------------------------ - */ -#define PSR_CWP 0x0000001f /* current window pointer */ -#define PSR_ET 0x00000020 /* enable traps field */ -#define PSR_PS 0x00000040 /* previous privilege level */ -#define PSR_S 0x00000080 /* current privilege level */ -#define PSR_PIL 0x00000f00 /* processor interrupt level */ -#define PSR_EF 0x00001000 /* enable floating point */ -#define PSR_EC 0x00002000 /* enable co-processor */ -#define PSR_LE 0x00008000 /* SuperSparcII little-endian */ -#define PSR_ICC 0x00f00000 /* integer condition codes */ -#define PSR_C 0x00100000 /* carry bit */ -#define PSR_V 0x00200000 /* overflow bit */ -#define PSR_Z 0x00400000 /* zero bit */ -#define PSR_N 0x00800000 /* negative bit */ -#define PSR_VERS 0x0f000000 /* cpu-version field */ -#define PSR_IMPL 0xf0000000 /* cpu-implementation field */ - -#define PSR_PIL_OFS 8 - -#ifndef __ASSEMBLY__ -/* Get the %psr register. */ -extern __inline__ unsigned int get_psr(void) -{ - unsigned int psr; - __asm__ __volatile__("rd %%psr, %0\n\t" - "nop\n\t" "nop\n\t" "nop\n\t":"=r"(psr) - : /* no inputs */ - :"memory"); - - return psr; -} - -extern __inline__ void put_psr(unsigned int new_psr) -{ - __asm__ __volatile__("wr %0, 0x0, %%psr\n\t" "nop\n\t" "nop\n\t" "nop\n\t": /* no outputs */ - :"r"(new_psr) - :"memory", "cc"); -} - -/* Get the %fsr register. Be careful, make sure the floating point - * enable bit is set in the %psr when you execute this or you will - * incur a trap. - */ - -extern unsigned int fsr_storage; - -extern __inline__ unsigned int get_fsr(void) -{ - unsigned int fsr = 0; - - __asm__ __volatile__("st %%fsr, %1\n\t" - "ld %1, %0\n\t":"=r"(fsr) - :"m"(fsr_storage)); - - return fsr; -} - -#endif /* !(__ASSEMBLY__) */ - -#endif /* !(__SPARC_PSR_H__) */ diff --git a/include/asm-sparc/ptrace.h b/include/asm-sparc/ptrace.h deleted file mode 100644 index 12a9c56..0000000 --- a/include/asm-sparc/ptrace.h +++ /dev/null @@ -1,181 +0,0 @@ -/* Contain the Stack frame layout on interrupt. pt_regs. - * taken from the SPARC port of Linux (ptrace.h). - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __SPARC_PTRACE_H__ -#define __SPARC_PTRACE_H__ - -#include - -/* This struct defines the way the registers are stored on the - * stack during a system call and basically all traps. - */ - -#ifndef __ASSEMBLY__ - -struct pt_regs { - unsigned long psr; - unsigned long pc; - unsigned long npc; - unsigned long y; - unsigned long u_regs[16]; /* globals and ins */ -}; - -#define UREG_G0 0 -#define UREG_G1 1 -#define UREG_G2 2 -#define UREG_G3 3 -#define UREG_G4 4 -#define UREG_G5 5 -#define UREG_G6 6 -#define UREG_G7 7 -#define UREG_I0 8 -#define UREG_I1 9 -#define UREG_I2 10 -#define UREG_I3 11 -#define UREG_I4 12 -#define UREG_I5 13 -#define UREG_I6 14 -#define UREG_I7 15 -#define UREG_WIM UREG_G0 -#define UREG_FADDR UREG_G0 -#define UREG_FP UREG_I6 -#define UREG_RETPC UREG_I7 - -/* A register window */ -struct reg_window { - unsigned long locals[8]; - unsigned long ins[8]; -}; - -/* A Sparc stack frame */ -struct sparc_stackf { - unsigned long locals[8]; - unsigned long ins[6]; - struct sparc_stackf *fp; - unsigned long callers_pc; - char *structptr; - unsigned long xargs[6]; - unsigned long xxargs[1]; -}; - -#define TRACEREG_SZ sizeof(struct pt_regs) -#define STACKFRAME_SZ sizeof(struct sparc_stackf) - -#else /* __ASSEMBLY__ */ -/* For assembly code. */ -#define TRACEREG_SZ 0x50 -#define STACKFRAME_SZ 0x60 -#endif - -/* - * The asm_offsets.h is a generated file, so we cannot include it. - * It may be OK for glibc headers, but it's utterly pointless for C code. - * The assembly code using those offsets has to include it explicitly. - */ -/* #include */ - -/* These are for pt_regs. */ -#define PT_PSR 0x0 -#define PT_PC 0x4 -#define PT_NPC 0x8 -#define PT_Y 0xc -#define PT_G0 0x10 -#define PT_WIM PT_G0 -#define PT_G1 0x14 -#define PT_G2 0x18 -#define PT_G3 0x1c -#define PT_G4 0x20 -#define PT_G5 0x24 -#define PT_G6 0x28 -#define PT_G7 0x2c -#define PT_I0 0x30 -#define PT_I1 0x34 -#define PT_I2 0x38 -#define PT_I3 0x3c -#define PT_I4 0x40 -#define PT_I5 0x44 -#define PT_I6 0x48 -#define PT_FP PT_I6 -#define PT_I7 0x4c - -/* Reg_window offsets */ -#define RW_L0 0x00 -#define RW_L1 0x04 -#define RW_L2 0x08 -#define RW_L3 0x0c -#define RW_L4 0x10 -#define RW_L5 0x14 -#define RW_L6 0x18 -#define RW_L7 0x1c -#define RW_I0 0x20 -#define RW_I1 0x24 -#define RW_I2 0x28 -#define RW_I3 0x2c -#define RW_I4 0x30 -#define RW_I5 0x34 -#define RW_I6 0x38 -#define RW_I7 0x3c - -/* Stack_frame offsets */ -#define SF_L0 0x00 -#define SF_L1 0x04 -#define SF_L2 0x08 -#define SF_L3 0x0c -#define SF_L4 0x10 -#define SF_L5 0x14 -#define SF_L6 0x18 -#define SF_L7 0x1c -#define SF_I0 0x20 -#define SF_I1 0x24 -#define SF_I2 0x28 -#define SF_I3 0x2c -#define SF_I4 0x30 -#define SF_I5 0x34 -#define SF_FP 0x38 -#define SF_PC 0x3c -#define SF_RETP 0x40 -#define SF_XARG0 0x44 -#define SF_XARG1 0x48 -#define SF_XARG2 0x4c -#define SF_XARG3 0x50 -#define SF_XARG4 0x54 -#define SF_XARG5 0x58 -#define SF_XXARG 0x5c - -/* Stuff for the ptrace system call */ -#define PTRACE_SUNATTACH 10 -#define PTRACE_SUNDETACH 11 -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 -#define PTRACE_READDATA 16 -#define PTRACE_WRITEDATA 17 -#define PTRACE_READTEXT 18 -#define PTRACE_WRITETEXT 19 -#define PTRACE_GETFPAREGS 20 -#define PTRACE_SETFPAREGS 21 - -#define PTRACE_GETUCODE 29 /* stupid bsd-ism */ - -#endif /* !(_SPARC_PTRACE_H) */ diff --git a/include/asm-sparc/srmmu.h b/include/asm-sparc/srmmu.h deleted file mode 100644 index 5214d96..0000000 --- a/include/asm-sparc/srmmu.h +++ /dev/null @@ -1,301 +0,0 @@ -/* SRMMU page table defines and code, - * taken from the SPARC port of Linux - * - * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com) - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __SPARC_SRMMU_H__ -#define __SPARC_SRMMU_H__ - -#include -#include - -/* Number of contexts is implementation-dependent; 64k is the most we support */ -#define SRMMU_MAX_CONTEXTS 65536 - -/* PMD_SHIFT determines the size of the area a second-level page table entry can map */ -#define SRMMU_REAL_PMD_SHIFT 18 -#define SRMMU_REAL_PMD_SIZE (1UL << SRMMU_REAL_PMD_SHIFT) -#define SRMMU_REAL_PMD_MASK (~(SRMMU_REAL_PMD_SIZE-1)) -#define SRMMU_REAL_PMD_ALIGN(__addr) (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK) - -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define SRMMU_PGDIR_SHIFT 24 -#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT) -#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1)) -#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK) - -#define SRMMU_REAL_PTRS_PER_PTE 64 -#define SRMMU_REAL_PTRS_PER_PMD 64 -#define SRMMU_PTRS_PER_PGD 256 - -#define SRMMU_REAL_PTE_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PTE*4) -#define SRMMU_PMD_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PMD*4) -#define SRMMU_PGD_TABLE_SIZE (SRMMU_PTRS_PER_PGD*4) - -/* - * To support pagetables in highmem, Linux introduces APIs which - * return struct page* and generally manipulate page tables when - * they are not mapped into kernel space. Our hardware page tables - * are smaller than pages. We lump hardware tabes into big, page sized - * software tables. - * - * PMD_SHIFT determines the size of the area a second-level page table entry - * can map, and our pmd_t is 16 times larger than normal. The values which - * were once defined here are now generic for 4c and srmmu, so they're - * found in pgtable.h. - */ -#define SRMMU_PTRS_PER_PMD 4 - -/* Definition of the values in the ET field of PTD's and PTE's */ -#define SRMMU_ET_MASK 0x3 -#define SRMMU_ET_INVALID 0x0 -#define SRMMU_ET_PTD 0x1 -#define SRMMU_ET_PTE 0x2 -#define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */ - -/* Physical page extraction from PTP's and PTE's. */ -#define SRMMU_CTX_PMASK 0xfffffff0 -#define SRMMU_PTD_PMASK 0xfffffff0 -#define SRMMU_PTE_PMASK 0xffffff00 - -/* The pte non-page bits. Some notes: - * 1) cache, dirty, valid, and ref are frobbable - * for both supervisor and user pages. - * 2) exec and write will only give the desired effect - * on user pages - * 3) use priv and priv_readonly for changing the - * characteristics of supervisor ptes - */ -#define SRMMU_CACHE 0x80 -#define SRMMU_DIRTY 0x40 -#define SRMMU_REF 0x20 -#define SRMMU_NOREAD 0x10 -#define SRMMU_EXEC 0x08 -#define SRMMU_WRITE 0x04 -#define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */ -#define SRMMU_PRIV 0x1c -#define SRMMU_PRIV_RDONLY 0x18 - -#define SRMMU_FILE 0x40 /* Implemented in software */ - -#define SRMMU_PTE_FILE_SHIFT 8 /* == 32-PTE_FILE_MAX_BITS */ - -#define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY) - -/* SRMMU swap entry encoding - * - * We use 5 bits for the type and 19 for the offset. This gives us - * 32 swapfiles of 4GB each. Encoding looks like: - * - * oooooooooooooooooootttttRRRRRRRR - * fedcba9876543210fedcba9876543210 - * - * The bottom 8 bits are reserved for protection and status bits, especially - * FILE and PRESENT. - */ -#define SRMMU_SWP_TYPE_MASK 0x1f -#define SRMMU_SWP_TYPE_SHIFT SRMMU_PTE_FILE_SHIFT -#define SRMMU_SWP_OFF_MASK 0x7ffff -#define SRMMU_SWP_OFF_SHIFT (SRMMU_PTE_FILE_SHIFT + 5) - -/* Some day I will implement true fine grained access bits for - * user pages because the SRMMU gives us the capabilities to - * enforce all the protection levels that vma's can have. - * XXX But for now... - */ -#define SRMMU_PAGE_NONE __pgprot(SRMMU_CACHE | \ - SRMMU_PRIV | SRMMU_REF) -#define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \ - SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF) -#define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \ - SRMMU_EXEC | SRMMU_REF) -#define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \ - SRMMU_EXEC | SRMMU_REF) -#define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \ - SRMMU_DIRTY | SRMMU_REF) - -/* SRMMU Register addresses in ASI 0x4. These are valid for all - * current SRMMU implementations that exist. - */ -#define SRMMU_CTRL_REG 0x00000000 -#define SRMMU_CTXTBL_PTR 0x00000100 -#define SRMMU_CTX_REG 0x00000200 -#define SRMMU_FAULT_STATUS 0x00000300 -#define SRMMU_FAULT_ADDR 0x00000400 - -#define WINDOW_FLUSH(tmp1, tmp2) \ - mov 0, tmp1; \ -98: ld [%g6 + TI_UWINMASK], tmp2; \ - orcc %g0, tmp2, %g0; \ - add tmp1, 1, tmp1; \ - bne 98b; \ - save %sp, -64, %sp; \ -99: subcc tmp1, 1, tmp1; \ - bne 99b; \ - restore %g0, %g0, %g0; - -#ifndef __ASSEMBLY__ - -/* This makes sense. Honest it does - Anton */ -/* XXX Yes but it's ugly as sin. FIXME. -KMW */ -extern void *srmmu_nocache_pool; -#define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool)) -#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR) -#define __nocache_fix(VADDR) __va(__nocache_pa(VADDR)) - -/* Accessing the MMU control register. */ -extern __inline__ unsigned int srmmu_get_mmureg(void) -{ - unsigned int retval; - __asm__ __volatile__("lda [%%g0] %1, %0\n\t": - "=r"(retval):"i"(ASI_M_MMUREGS)); - return retval; -} - -extern __inline__ void srmmu_set_mmureg(unsigned long regval) -{ - __asm__ __volatile__("sta %0, [%%g0] %1\n\t"::"r"(regval), - "i"(ASI_M_MMUREGS):"memory"); - -} - -extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr) -{ - paddr = ((paddr >> 4) & SRMMU_CTX_PMASK); - __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(paddr), - "r"(SRMMU_CTXTBL_PTR), - "i"(ASI_M_MMUREGS):"memory"); -} - -extern __inline__ unsigned long srmmu_get_ctable_ptr(void) -{ - unsigned int retval; - - __asm__ __volatile__("lda [%1] %2, %0\n\t": - "=r"(retval): - "r"(SRMMU_CTXTBL_PTR), "i"(ASI_M_MMUREGS)); - return (retval & SRMMU_CTX_PMASK) << 4; -} - -extern __inline__ void srmmu_set_context(int context) -{ - __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(context), - "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS):"memory"); -} - -extern __inline__ int srmmu_get_context(void) -{ - register int retval; - __asm__ __volatile__("lda [%1] %2, %0\n\t": - "=r"(retval): - "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS)); - return retval; -} - -extern __inline__ unsigned int srmmu_get_fstatus(void) -{ - unsigned int retval; - - __asm__ __volatile__("lda [%1] %2, %0\n\t": - "=r"(retval): - "r"(SRMMU_FAULT_STATUS), "i"(ASI_M_MMUREGS)); - return retval; -} - -extern __inline__ unsigned int srmmu_get_faddr(void) -{ - unsigned int retval; - - __asm__ __volatile__("lda [%1] %2, %0\n\t": - "=r"(retval): - "r"(SRMMU_FAULT_ADDR), "i"(ASI_M_MMUREGS)); - return retval; -} - -/* This is guaranteed on all SRMMU's. */ -extern __inline__ void srmmu_flush_whole_tlb(void) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400), /* Flush entire TLB!! */ - "i"(ASI_M_FLUSH_PROBE):"memory"); - -} - -/* These flush types are not available on all chips... */ -extern __inline__ void srmmu_flush_tlb_ctx(void) -{ - __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x300), /* Flush TLB ctx.. */ - "i"(ASI_M_FLUSH_PROBE):"memory"); - -} - -extern __inline__ void srmmu_flush_tlb_region(unsigned long addr) -{ - addr &= SRMMU_PGDIR_MASK; - __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x200), /* Flush TLB region.. */ - "i"(ASI_M_FLUSH_PROBE):"memory"); - -} - -extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr) -{ - addr &= SRMMU_REAL_PMD_MASK; - __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x100), /* Flush TLB segment.. */ - "i"(ASI_M_FLUSH_PROBE):"memory"); - -} - -extern __inline__ void srmmu_flush_tlb_page(unsigned long page) -{ - page &= PAGE_MASK; - __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(page), /* Flush TLB page.. */ - "i"(ASI_M_FLUSH_PROBE):"memory"); - -} - -extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr) -{ - unsigned long retval; - - vaddr &= PAGE_MASK; - __asm__ __volatile__("lda [%1] %2, %0\n\t": - "=r"(retval): - "r"(vaddr | 0x400), "i"(ASI_M_FLUSH_PROBE)); - - return retval; -} - -extern __inline__ int srmmu_get_pte(unsigned long addr) -{ - register unsigned long entry; - - __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t": - "=r"(entry): - "r"((addr & 0xfffff000) | 0x400), - "i"(ASI_M_FLUSH_PROBE)); - return entry; -} - -extern unsigned long (*srmmu_read_physical) (unsigned long paddr); -extern void (*srmmu_write_physical) (unsigned long paddr, unsigned long word); - -#endif /* !(__ASSEMBLY__) */ - -#endif /* !(__SPARC_SRMMU_H__) */ diff --git a/include/asm-sparc/stack.h b/include/asm-sparc/stack.h deleted file mode 100644 index b40a9f3..0000000 --- a/include/asm-sparc/stack.h +++ /dev/null @@ -1,162 +0,0 @@ -/* SPARC stack layout Macros and structures, - * mainly taken from BCC (the Bare C compiler for - * SPARC LEON2/3) sources. - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __SPARC_STACK_H__ -#define __SPARC_STACK_H__ - -#include - -#ifndef __ASSEMBLER__ - -#ifdef __cplusplus -extern "C" { -#endif - -#define PT_REGS_SZ sizeof(struct pt_regs) - -/* A Sparc stack frame */ - struct sparc_stackframe_regs { - unsigned long sf_locals[8]; - unsigned long sf_ins[6]; - struct sparc_stackframe_regs *sf_fp; - unsigned long sf_callers_pc; - char *sf_structptr; - unsigned long sf_xargs[6]; - unsigned long sf_xxargs[1]; - }; -#define SF_REGS_SZ sizeof(struct sparc_stackframe_regs) - -/* A register window */ - struct sparc_regwindow_regs { - unsigned long locals[8]; - unsigned long ins[8]; - }; -#define RW_REGS_SZ sizeof(struct sparc_regwindow_regs) - -/* A fpu window */ - struct sparc_fpuwindow_regs { - unsigned long locals[32]; - unsigned long fsr; - unsigned long lastctx; - }; -#define FW_REGS_SZ sizeof(struct sparc_fpuwindow_regs) - -#ifdef __cplusplus -} -#endif -#else -#define PT_REGS_SZ 0x50 /* 20*4 */ -#define SF_REGS_SZ 0x60 /* 24*4 */ -#define RW_REGS_SZ 0x20 /* 16*4 */ -#define FW_REGS_SZ 0x88 /* 34*4 */ -#endif /* !ASM */ - -/* These are for pt_regs. */ -#define PT_PSR 0x0 -#define PT_PC 0x4 -#define PT_NPC 0x8 -#define PT_Y 0xc -#define PT_G0 0x10 -#define PT_WIM PT_G0 -#define PT_G1 0x14 -#define PT_G2 0x18 -#define PT_G3 0x1c -#define PT_G4 0x20 -#define PT_G5 0x24 -#define PT_G6 0x28 -#define PT_G7 0x2c -#define PT_I0 0x30 -#define PT_I1 0x34 -#define PT_I2 0x38 -#define PT_I3 0x3c -#define PT_I4 0x40 -#define PT_I5 0x44 -#define PT_I6 0x48 -#define PT_FP PT_I6 -#define PT_I7 0x4c - -/* Stack_frame offsets */ -#define SF_L0 0x00 -#define SF_L1 0x04 -#define SF_L2 0x08 -#define SF_L3 0x0c -#define SF_L4 0x10 -#define SF_L5 0x14 -#define SF_L6 0x18 -#define SF_L7 0x1c -#define SF_I0 0x20 -#define SF_I1 0x24 -#define SF_I2 0x28 -#define SF_I3 0x2c -#define SF_I4 0x30 -#define SF_I5 0x34 -#define SF_FP 0x38 -#define SF_PC 0x3c -#define SF_RETP 0x40 -#define SF_XARG0 0x44 -#define SF_XARG1 0x48 -#define SF_XARG2 0x4c -#define SF_XARG3 0x50 -#define SF_XARG4 0x54 -#define SF_XARG5 0x58 -#define SF_XXARG 0x5c - -/* Reg_window offsets */ -#define RW_L0 0x00 -#define RW_L1 0x04 -#define RW_L2 0x08 -#define RW_L3 0x0c -#define RW_L4 0x10 -#define RW_L5 0x14 -#define RW_L6 0x18 -#define RW_L7 0x1c -#define RW_I0 0x20 -#define RW_I1 0x24 -#define RW_I2 0x28 -#define RW_I3 0x2c -#define RW_I4 0x30 -#define RW_I5 0x34 -#define RW_I6 0x38 -#define RW_I7 0x3c - -/* Fpu_window offsets */ -#define FW_F0 0x00 -#define FW_F2 0x08 -#define FW_F4 0x10 -#define FW_F6 0x18 -#define FW_F8 0x20 -#define FW_F10 0x28 -#define FW_F12 0x30 -#define FW_F14 0x38 -#define FW_F16 0x40 -#define FW_F18 0x48 -#define FW_F20 0x50 -#define FW_F22 0x58 -#define FW_F24 0x60 -#define FW_F26 0x68 -#define FW_F28 0x70 -#define FW_F30 0x78 -#define FW_FSR 0x80 - -#endif diff --git a/include/asm-sparc/string.h b/include/asm-sparc/string.h deleted file mode 100644 index c6bbc20..0000000 --- a/include/asm-sparc/string.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2000 - 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _SPARC_STRING_H_ -#define _SPARC_STRING_H_ - -/* -#define __HAVE_ARCH_STRCPY -#define __HAVE_ARCH_STRNCPY -#define __HAVE_ARCH_STRLEN -#define __HAVE_ARCH_STRCMP -#define __HAVE_ARCH_STRCAT -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_BCOPY -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMMOVE -#define __HAVE_ARCH_MEMCMP -#define __HAVE_ARCH_MEMCHR -*/ - -extern int strcasecmp(const char *, const char *); -extern int strncasecmp(const char *, const char *, int); -extern char *strcpy(char *, const char *); -extern char *strncpy(char *, const char *, __kernel_size_t); -extern __kernel_size_t strlen(const char *); -extern int strcmp(const char *, const char *); -extern char *strcat(char *, const char *); -extern void *memset(void *, int, __kernel_size_t); -extern void *memcpy(void *, const void *, __kernel_size_t); -extern void *memmove(void *, const void *, __kernel_size_t); -extern int memcmp(const void *, const void *, __kernel_size_t); -extern void *memchr(const void *, int, __kernel_size_t); - -#endif diff --git a/include/asm-sparc/types.h b/include/asm-sparc/types.h deleted file mode 100644 index 0a8a26c..0000000 --- a/include/asm-sparc/types.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2000 - 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _SPARC_TYPES_H -#define _SPARC_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -typedef struct { - __u32 u[4]; -} __attribute__((aligned(16))) vector128; - -#ifdef __KERNEL__ -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* DMA addresses are 32-bits wide */ -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif /* __KERNEL__ */ -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-sparc/u-boot.h b/include/asm-sparc/u-boot.h deleted file mode 100644 index 209873f..0000000 --- a/include/asm-sparc/u-boot.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2000 - 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007, From asm-ppc/u-boot.h - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef __U_BOOT_H__ -#define __U_BOOT_H__ - -/* - * Currently, this Board information is not passed to - * Linux kernel from U-Boot, but may be passed to other - * Operating systems. This is because U-boot emulates - * a SUN PROM loader (from Linux point of view). - * - * include/asm-sparc/u-boot.h - */ - -#ifndef __ASSEMBLY__ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ - unsigned long bi_baudrate; /* Console Baudrate */ -} bd_t; - -#endif /* __ASSEMBLY__ */ -#endif /* __U_BOOT_H__ */ diff --git a/include/asm-sparc/winmacro.h b/include/asm-sparc/winmacro.h deleted file mode 100644 index 66fc639..0000000 --- a/include/asm-sparc/winmacro.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Added to U-boot, - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com - * Copyright (C) 2007 - * - * LEON2/3 LIBIO low-level routines - * Written by Jiri Gaisler. - * Copyright (C) 2004 Gaisler Research AB - - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - -*/ - -#ifndef __SPARC_WINMACRO_H__ -#define __SPARC_WINMACRO_H__ - -#include -#include - -/* Store the register window onto the 8-byte aligned area starting - * at %reg. It might be %sp, it might not, we don't care. - */ -#define RW_STORE(reg) \ - std %l0, [%reg + RW_L0]; \ - std %l2, [%reg + RW_L2]; \ - std %l4, [%reg + RW_L4]; \ - std %l6, [%reg + RW_L6]; \ - std %i0, [%reg + RW_I0]; \ - std %i2, [%reg + RW_I2]; \ - std %i4, [%reg + RW_I4]; \ - std %i6, [%reg + RW_I6]; - -/* Load a register window from the area beginning at %reg. */ -#define RW_LOAD(reg) \ - ldd [%reg + RW_L0], %l0; \ - ldd [%reg + RW_L2], %l2; \ - ldd [%reg + RW_L4], %l4; \ - ldd [%reg + RW_L6], %l6; \ - ldd [%reg + RW_I0], %i0; \ - ldd [%reg + RW_I2], %i2; \ - ldd [%reg + RW_I4], %i4; \ - ldd [%reg + RW_I6], %i6; - -/* Loading and storing struct pt_reg trap frames. */ -#define PT_LOAD_INS(base_reg) \ - ldd [%base_reg + SF_REGS_SZ + PT_I0], %i0; \ - ldd [%base_reg + SF_REGS_SZ + PT_I2], %i2; \ - ldd [%base_reg + SF_REGS_SZ + PT_I4], %i4; \ - ldd [%base_reg + SF_REGS_SZ + PT_I6], %i6; - -#define PT_LOAD_GLOBALS(base_reg) \ - ld [%base_reg + SF_REGS_SZ + PT_G1], %g1; \ - ldd [%base_reg + SF_REGS_SZ + PT_G2], %g2; \ - ldd [%base_reg + SF_REGS_SZ + PT_G4], %g4; \ - ldd [%base_reg + SF_REGS_SZ + PT_G6], %g6; - -#define PT_LOAD_YREG(base_reg, scratch) \ - ld [%base_reg + SF_REGS_SZ + PT_Y], %scratch; \ - wr %scratch, 0x0, %y; - -#define PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \ - ld [%base_reg + SF_REGS_SZ + PT_PSR], %pt_psr; \ - ld [%base_reg + SF_REGS_SZ + PT_PC], %pt_pc; \ - ld [%base_reg + SF_REGS_SZ + PT_NPC], %pt_npc; - -#define PT_LOAD_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \ - PT_LOAD_YREG(base_reg, scratch) \ - PT_LOAD_INS(base_reg) \ - PT_LOAD_GLOBALS(base_reg) \ - PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc) - -#define PT_STORE_INS(base_reg) \ - std %i0, [%base_reg + SF_REGS_SZ + PT_I0]; \ - std %i2, [%base_reg + SF_REGS_SZ + PT_I2]; \ - std %i4, [%base_reg + SF_REGS_SZ + PT_I4]; \ - std %i6, [%base_reg + SF_REGS_SZ + PT_I6]; - -#define PT_STORE_GLOBALS(base_reg) \ - st %g1, [%base_reg + SF_REGS_SZ + PT_G1]; \ - std %g2, [%base_reg + SF_REGS_SZ + PT_G2]; \ - std %g4, [%base_reg + SF_REGS_SZ + PT_G4]; \ - std %g6, [%base_reg + SF_REGS_SZ + PT_G6]; - -#define PT_STORE_YREG(base_reg, scratch) \ - rd %y, %scratch; \ - st %scratch, [%base_reg + SF_REGS_SZ + PT_Y]; - -#define PT_STORE_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \ - st %pt_psr, [%base_reg + SF_REGS_SZ + PT_PSR]; \ - st %pt_pc, [%base_reg + SF_REGS_SZ + PT_PC]; \ - st %pt_npc, [%base_reg + SF_REGS_SZ + PT_NPC]; - -#define PT_STORE_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \ - PT_STORE_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \ - PT_STORE_GLOBALS(base_reg) \ - PT_STORE_YREG(base_reg, g_scratch) \ - PT_STORE_INS(base_reg) - -/* Store the fpu register window*/ -#define FW_STORE(reg) \ - std %f0, [reg + FW_F0]; \ - std %f2, [reg + FW_F2]; \ - std %f4, [reg + FW_F4]; \ - std %f6, [reg + FW_F6]; \ - std %f8, [reg + FW_F8]; \ - std %f10, [reg + FW_F10]; \ - std %f12, [reg + FW_F12]; \ - std %f14, [reg + FW_F14]; \ - std %f16, [reg + FW_F16]; \ - std %f18, [reg + FW_F18]; \ - std %f20, [reg + FW_F20]; \ - std %f22, [reg + FW_F22]; \ - std %f24, [reg + FW_F24]; \ - std %f26, [reg + FW_F26]; \ - std %f28, [reg + FW_F28]; \ - std %f30, [reg + FW_F30]; \ - st %fsr, [reg + FW_FSR]; - -/* Load a fpu register window from the area beginning at reg. */ -#define FW_LOAD(reg) \ - ldd [reg + FW_F0], %f0; \ - ldd [reg + FW_F2], %f2; \ - ldd [reg + FW_F4], %f4; \ - ldd [reg + FW_F6], %f6; \ - ldd [reg + FW_F8], %f8; \ - ldd [reg + FW_F10], %f10; \ - ldd [reg + FW_F12], %f12; \ - ldd [reg + FW_F14], %f14; \ - ldd [reg + FW_F16], %f16; \ - ldd [reg + FW_F18], %f18; \ - ldd [reg + FW_F20], %f20; \ - ldd [reg + FW_F22], %f22; \ - ldd [reg + FW_F24], %f24; \ - ldd [reg + FW_F26], %f26; \ - ldd [reg + FW_F28], %f28; \ - ldd [reg + FW_F30], %f30; \ - ld [reg + FW_FSR], %fsr; - -#endif -- cgit v1.1 From 8d1f268204b07e172f3cb5cee0a3974d605b0b98 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 12 Apr 2010 22:28:09 -0500 Subject: ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU Signed-off-by: Peter Tyser --- include/configs/aria.h | 2 +- include/configs/galaxy5200.h | 2 +- include/configs/kilauea.h | 2 +- include/configs/linkstation.h | 2 +- include/configs/quad100hd.h | 6 +++--- include/configs/sc3.h | 4 ++-- 6 files changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/aria.h b/include/configs/aria.h index f89fc57..06763c5 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -190,7 +190,7 @@ /* * Backward compatible definitions, - * so we do not have to change cpu/mpc512x/fixed_sdram.c + * so we do not have to change arch/ppc/cpu/mpc512x/fixed_sdram.c */ #define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) #define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 4be28b2..44669ea 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -141,7 +141,7 @@ #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* - * The flash size is autoconfigured, but cpu/mpc5xxx/cpu_init.c needs this + * The flash size is autoconfigured, but arch/ppc/cpu/mpc5xxx/cpu_init.c needs this * variable defined */ #define CONFIG_SYS_FLASH_SIZE 0x02000000 diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index a79feec..e5537da 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -230,7 +230,7 @@ * SDRAM Controller DDR autocalibration values and takes a lot longer * to run than Method_B. * (See the Method_A and Method_B algorithm discription in the file: - * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) + * arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A * * DDR Autocalibration Method_B is the default. diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index 16b464c..3958d09 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -290,7 +290,7 @@ * taken from the orignal Linkstation boot code * * Most of the low level configuration setttings are normally used - * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation. + * in arch/ppc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation. * Low level initialisation is done in board/linkstation/early_init.S * The values below are included for reference purpose only */ diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index 403837e..2472187 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -233,7 +233,7 @@ * Definitions for initial stack pointer and data area (in data cache) */ /* use on chip memory (OCM) for temperary stack until sdram is tested */ -/* see ./cpu/ppc4xx/start.S */ +/* see ./arch/ppc/cpu/ppc4xx/start.S */ #define CONFIG_SYS_TEMP_STACK_OCM 1 /* On Chip Memory location */ @@ -251,7 +251,7 @@ * Taken from PPCBoot board/icecube/icecube.h */ -/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */ +/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */ #define CONFIG_SYS_EBC_PB0AP 0x04002480 /* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */ #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 @@ -269,7 +269,7 @@ * * Taken in part from PPCBoot board/icecube/icecube.h */ -/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ +/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ #define CONFIG_SYS_GPIO0_OSRH 0x55555550 #define CONFIG_SYS_GPIO0_OSRL 0x00000110 #define CONFIG_SYS_GPIO0_ISR1H 0x00000000 diff --git a/include/configs/sc3.h b/include/configs/sc3.h index d00f248..7423663 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -456,7 +456,7 @@ * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR * - Stackpointer will be located to * (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF) - * in cpu/ppc4xx/start.S + * in arch/ppc/cpu/ppc4xx/start.S */ #undef CONFIG_SYS_INIT_DCACHE_CS @@ -495,7 +495,7 @@ #define BOOTFLAG_WARM 0x02 /* Software reboot */ /* ################################################################################### */ -/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */ +/* These defines will be used in arch/ppc/cpu/ppc4xx/cpu_init.c to setup external chip selects */ /* They are currently undefined cause they are initiaized in board/solidcard3/init.S */ /* This chip select accesses the boot device */ -- cgit v1.1 From c6fb83d21729321426308c3acff2a3dfb20d250b Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 12 Apr 2010 22:28:13 -0500 Subject: blackfin: Move cpu/blackfin/* to arch/blackfin/cpu/* Signed-off-by: Peter Tyser --- include/configs/bf533-stamp.h | 6 +++--- include/configs/bf537-pnav.h | 6 +++--- include/configs/bf537-stamp.h | 6 +++--- include/configs/bf538f-ezkit.h | 6 +++--- include/configs/bf561-ezkit.h | 6 +++--- include/configs/cm-bf537e.h | 6 +++--- include/configs/cm-bf537u.h | 6 +++--- include/configs/ibf-dsp561.h | 6 +++--- include/configs/tcm-bf537.h | 6 +++--- 9 files changed, 27 insertions(+), 27 deletions(-) (limited to 'include') diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 0b94f55..80c4884 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -126,9 +126,9 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 8038c40..cf40d06 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -112,9 +112,9 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 0f8679b..92ceb38 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -122,9 +122,9 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index 696fe29..59e0565 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -119,9 +119,9 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index fca6e43..1e3fdef 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -96,9 +96,9 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ lib/crc32.o (.text .text.*); \ lib/zlib.o (.text .text.*); \ diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index d86409f..8d0bc12 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -104,9 +104,9 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index 6be9dba..bbea3ab 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -105,9 +105,9 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 6fa8cf7..2eef5ef 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -84,9 +84,9 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ lib/crc32.o (.text .text.*); \ lib/zlib.o (.text .text.*); \ diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index e9dfcc9..409a042 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -105,9 +105,9 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ common/dlmalloc.o (.text .text.*); \ lib/crc32.o (.text .text.*); \ . = DEFINED(env_offset) ? env_offset : .; \ -- cgit v1.1 From 288991c93fdd150ef3817e676c657cb487468d38 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 8 Apr 2010 09:33:13 +0200 Subject: ppc4xx: alpr: Remove some not needed commands to make image fit again The latest changes increased the size of the alpr image a bit more. Now it doesn't fit into the 256k reserved for it. This patch now removes the commands "loads" and "loadb" which are not needed in the production systems. Signed-off-by: Stefan Roese Cc: Pieter Voorthuijsen --- include/configs/alpr.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/alpr.h b/include/configs/alpr.h index f2392f6..ee0c14d 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -236,11 +236,13 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_FPGA #define CONFIG_CMD_I2C +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS #define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_NET -#define CONFIG_CMD_PCI #undef CONFIG_CMD_NFS +#define CONFIG_CMD_PCI #undef CONFIG_WATCHDOG /* watchdog disabled */ -- cgit v1.1 From 2a72e9ed18d2164eb7fe569119342eb631b568da Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 9 Apr 2010 14:03:59 +0200 Subject: ppc4xx: Add option for PPC440SPe ports without old Rev. A support The 440SPe Rev. A is quite old and newer 440SPe boards don't need support for this CPU revision. Since removing support for this older version simplifies the creation for newer U-Boot ports, this patch now enables 440SPe > Rev. A support by creating the CONFIG_440SPE_REVA define. By defining this in the board config header, Rev. A will still be supported. Otherwise (default for newer board ports), Rev. A will not be supported. Signed-off-by: Stefan Roese --- include/configs/katmai.h | 1 + include/configs/yucca.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index c013ac4..fb8ccae 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -37,6 +37,7 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ +#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 42f8807..0b4dfb8 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -37,6 +37,7 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_440SPE 1 /* Specifc SPe support */ +#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define EXTCLK_33_33 33333333 -- cgit v1.1 From 9428d2f83ce93e41fb24dbe01f46e8e6540cae3d Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Tue, 6 Apr 2010 16:18:04 +0300 Subject: pm9261 converted to at91 soc access Signed-off-by: Asen Dimov --- include/configs/pm9261.h | 68 +++++++++++++++++++++++------------------------- 1 file changed, 33 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 47bb8c0..b245761 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -28,8 +28,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY - /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" @@ -51,26 +49,26 @@ /* clocks */ /* CKGR_MOR - enable main osc. */ #define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ + (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ #define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ + (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_PLLXR_OUT(3) | \ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_SLOW | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2 | \ + AT91_PMC_MCKR_PLLADIV_1) /* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) + (AT91_PMC_MCKR_CSS_PLLA | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2 | \ + AT91_PMC_MCKR_PLLADIV_1) /* define PDC[31:16] as DATA[31:16] */ #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 @@ -79,7 +77,7 @@ /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ #define CONFIG_SYS_MATRIX_EBICSA_VAL \ - (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC) + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ @@ -122,32 +120,32 @@ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) #define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) #define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) #define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | \ + AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ #define CONFIG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) + AT91_RSTC_CR_PROCRST | \ + AT91_RSTC_MR_ERSTL(1) | \ + AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ #define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xfff) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 @@ -180,9 +178,9 @@ /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PC12 -#define CONFIG_GREEN_LED AT91_PIN_PC13 -#define CONFIG_YELLOW_LED AT91_PIN_PC15 +#define CONFIG_RED_LED AT91_PIO_PORTC, 12 +#define CONFIG_GREEN_LED AT91_PIO_PORTC, 13 +#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 15 #define CONFIG_BOOTDELAY 3 @@ -236,8 +234,8 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16 /* NOR flash */ #define CONFIG_SYS_FLASH_CFI 1 -- cgit v1.1 From 14f7f8be6b259eb8c2d875708a03df3b3a15ea09 Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Tue, 6 Apr 2010 16:17:34 +0300 Subject: pm9261: remove CONFIG_CMD_AUTOSCRIPT Signed-off-by: Asen Dimov --- include/configs/pm9261.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index b245761..a0b00e9 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -198,7 +198,6 @@ #include #undef CONFIG_CMD_BDI #undef CONFIG_CMD_IMI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -- cgit v1.1 From ed1a529ab55593260c4c19000724777cf8dd7102 Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Wed, 7 Apr 2010 12:33:11 +0300 Subject: pm9263: remove CONFIG_CMD_AUTOSCRIPT Signed-off-by: Asen Dimov --- include/configs/pm9263.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 807dba8..f854f38 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -215,7 +215,6 @@ #include #undef CONFIG_CMD_BDI #undef CONFIG_CMD_IMI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -- cgit v1.1 From 5aa02e4d6a0ef5995ded70dc37b7f06e35fa6e21 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Wed, 24 Mar 2010 16:59:30 +0900 Subject: SAMSUNG: serial: modify name from s5pc1xx to s5p Because of other s5p series SoC will use these serial functions, modify function's name and structure's name. Signed-off-by: Minkyu Kang --- include/serial.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/serial.h b/include/serial.h index f2638ec..4caf790 100644 --- a/include/serial.h +++ b/include/serial.h @@ -44,10 +44,10 @@ extern struct serial_device s3c24xx_serial2_device; #endif #if defined(CONFIG_S5PC1XX) -extern struct serial_device s5pc1xx_serial0_device; -extern struct serial_device s5pc1xx_serial1_device; -extern struct serial_device s5pc1xx_serial2_device; -extern struct serial_device s5pc1xx_serial3_device; +extern struct serial_device s5p_serial0_device; +extern struct serial_device s5p_serial1_device; +extern struct serial_device s5p_serial2_device; +extern struct serial_device s5p_serial3_device; #endif #if defined(CONFIG_OMAP3_ZOOM2) -- cgit v1.1 From e470955b64116c30dd0fe9893d6d813b929618d7 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 5 Mar 2010 07:36:33 +0100 Subject: arm, i.mx27: add support for magnesium board from projectiondesign This patch adds support for the magnesium board from projectiondesign. This board uses i.MX27 SoC and has 8MB NOR flash, 128MB NAND flash, FEC ethernet controller integrated into i.MX27. As this port is based on the imx27lite port, common config options are collected in include/configs/imx27lite-common.h Signed-off-by: Heiko Schocher --- include/configs/imx27lite-common.h | 237 +++++++++++++++++++++++++++++++++++++ include/configs/imx27lite.h | 200 +------------------------------ include/configs/magnesium.h | 71 +++++++++++ 3 files changed, 312 insertions(+), 196 deletions(-) create mode 100644 include/configs/imx27lite-common.h create mode 100644 include/configs/magnesium.h (limited to 'include') diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h new file mode 100644 index 0000000..1da8602 --- /dev/null +++ b/include/configs/imx27lite-common.h @@ -0,0 +1,237 @@ +/* + * Copyright (C) 2010 Heiko Schocher + * + * based on: + * Copyright (C) 2009 Ilya Yanok + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMX27LITE_COMMON_CONFIG_H +#define __IMX27LITE_COMMON_CONFIG_H + +/* + * SoC Configuration + */ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_MX27 +#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Lowlevel configuration + */ +#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ + (ESDCFG_TRC(10) | \ + ESDCFG_TRCD(3) | \ + ESDCFG_TCAS(cas) | \ + ESDCFG_TRRD(1) | \ + ESDCFG_TRAS(5) | \ + ESDCFG_TWR | \ + ESDCFG_TMRD(2) | \ + ESDCFG_TRP(2) | \ + ESDCFG_TXP(3)) + +#define SDRAM_ESDCTL_REGISTER_VAL \ + (ESDCTL_PRCT(0) | \ + ESDCTL_BL | \ + ESDCTL_PWDT(0) | \ + ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ_32 | \ + ESDCTL_COL10 | \ + ESDCTL_ROW13 | \ + ESDCTL_SDE) + +#define SDRAM_ALL_VAL 0xf00 + +#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ +#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 + +#define MPCTL0_VAL 0x1ef15d5 + +#define SPCTL0_VAL 0x043a1c09 + +#define CSCR_VAL 0x33f08107 + +#define PCDR0_VAL 0x120470c3 +#define PCDR1_VAL 0x03030303 +#define PCCR0_VAL 0xffffffff +#define PCCR1_VAL 0xfffffffc + +#define AIPI1_PSR0_VAL 0x20040304 +#define AIPI1_PSR1_VAL 0xdffbfcfb +#define AIPI2_PSR0_VAL 0x07ffc200 +#define AIPI2_PSR1_VAL 0xffffffff + +/* + * Memory Info + */ +/* malloc() len */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) +/* reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +/* memtest start address */ +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */ +#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ + +/* + * Serial Driver info + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX27_UART1 +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Flash & Environment + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +/* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* Use hardware sector protection */ +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +/* CS2 Base address */ +#define PHYS_FLASH_1 0xc0000000 +/* Flash Base for U-Boot */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ + CONFIG_SYS_FLASH_SECT_SZ) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x1f +#define CONFIG_MII +#define CONFIG_NET_MULTI + +/* + * MTD + */ +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_MTD_DEVICE + +/* + * NAND + */ +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0xd8000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +/* + * SD/MMC + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXC_MMC +#define CONFIG_DOS_PARTITION + +/* + * MTD partitions + */ +#define CONFIG_CMD_MTDPARTS + +/* + * U-Boot general configuration + */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print buffer sz */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +/* + * U-Boot commands + */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "kernel_addr_r=a0800000\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "rootpath=/opt/eldk-4.2-arm/arm\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm\0" \ + "bootcmd=run net_nfs\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};cp.b ${fileaddr} " \ + xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + +#endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h index ee749ec..72f6e80 100644 --- a/include/configs/imx27lite.h +++ b/include/configs/imx27lite.h @@ -20,158 +20,31 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* include common defines/options for all imx27lite related boards */ +#include "imx27lite-common.h" /* * SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_MX27 #define CONFIG_IMX27LITE -#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Lowlevel configuration - */ -#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ - (ESDCFG_TRC(10) | \ - ESDCFG_TRCD(3) | \ - ESDCFG_TCAS(cas) | \ - ESDCFG_TRRD(1) | \ - ESDCFG_TRAS(5) | \ - ESDCFG_TWR | \ - ESDCFG_TMRD(2) | \ - ESDCFG_TRP(2) | \ - ESDCFG_TXP(3)) - -#define SDRAM_ESDCTL_REGISTER_VAL \ - (ESDCTL_PRCT(0) | \ - ESDCTL_BL | \ - ESDCTL_PWDT(0) | \ - ESDCTL_SREFR(3) | \ - ESDCTL_DSIZ_32 | \ - ESDCTL_COL10 | \ - ESDCTL_ROW13 | \ - ESDCTL_SDE) - -#define SDRAM_ALL_VAL 0xf00 - -#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ -#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 - -#define MPCTL0_VAL 0x1ef15d5 - -#define SPCTL0_VAL 0x043a1c09 - -#define CSCR_VAL 0x33f08107 - -#define PCDR0_VAL 0x120470c3 -#define PCDR1_VAL 0x03030303 -#define PCCR0_VAL 0xffffffff -#define PCCR1_VAL 0xfffffffc - -#define AIPI1_PSR0_VAL 0x20040304 -#define AIPI1_PSR1_VAL 0xdffbfcfb -#define AIPI2_PSR0_VAL 0x07ffc200 -#define AIPI2_PSR1_VAL 0xffffffff - -/* - * Memory Info - */ -/* malloc() len */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) -/* reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 -/* memtest start address */ -#define CONFIG_SYS_MEMTEST_START 0xA0000000 -#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */ -#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ - -/* - * Serial Driver info - */ -#define CONFIG_MXC_UART -#define CONFIG_SYS_MX27_UART1 -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_HOSTNAME imx27 +#define CONFIG_BOARDNAME "LogicPD imx27lite\n" /* * Flash & Environment */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -/* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -/* Use hardware sector protection */ -#define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */ -/* end of flash */ #define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000) -/* CS2 Base address */ -#define PHYS_FLASH_1 0xc0000000 -/* Flash Base for U-Boot */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -/* Flash size 2MB */ #define PHYS_FLASH_SIZE 0x200000 -#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ - CONFIG_SYS_FLASH_SECT_SZ) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ #define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f -#define CONFIG_MII -#define CONFIG_NET_MULTI - -/* - * MTD - */ -#define CONFIG_FLASH_CFI_MTD -#define CONFIG_MTD_DEVICE - -/* - * NAND - */ -#define CONFIG_NAND_MXC -#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0xd8000000 -#define CONFIG_JFFS2_NAND -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ /* * SD/MMC */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_MXC_MMC #define CONFIG_MXC_MCI_REGS_BASE 0x10014000 -#define CONFIG_DOS_PARTITION /* * MTD partitions */ -#define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" #define MTDPARTS_DEFAULT \ "mtdparts=" \ @@ -186,69 +59,4 @@ "22m(rootfs)," \ "-(userfs)" -/* - * U-Boot general configuration - */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Print buffer sz */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP - -/* - * U-Boot commands - */ -#include -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define xstr(s) str(s) -#define str(s) #s - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "u-boot=imx27/u-boot.bin\0" \ - "kernel_addr_r=a0800000\0" \ - "hostname=imx27\0" \ - "bootfile=imx27/uImage\0" \ - "rootpath=/opt/eldk-4.2-arm/arm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run net_nfs\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};cp.b ${fileaddr} " \ - xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - #endif /* __CONFIG_H */ diff --git a/include/configs/magnesium.h b/include/configs/magnesium.h new file mode 100644 index 0000000..4fb7744 --- /dev/null +++ b/include/configs/magnesium.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010 Heiko Schocher + * + * based on: + * Copyright (C) 2009 Ilya Yanok + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* include common defines/options for all imx27lite related boards */ +#include "imx27lite-common.h" + +/* + * SoC Configuration + */ +#define CONFIG_MAGNESIUM +#define CONFIG_HOSTNAME magnesium +#define CONFIG_BOARDNAME "Projectiondesign magnesium\n" + +/* + * Flash & Environment + */ +#define CONFIG_SYS_FLASH_SECT_SZ 0x8000 /* 64KB sect size */ +#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x40000) +#define PHYS_FLASH_SIZE 0x800000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* Env sector Size */ + +/* + * NAND + */ +#define CONFIG_SYS_NAND_LARGEPAGE + +/* + * SD/MMC + */ +#define CONFIG_MXC_MCI_REGS_BASE 0x10013000 + +/* + * MTD partitions + */ +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=" \ + "physmap-flash.0:" \ + "256k(U-Boot)," \ + "7680k(user)," \ + "128k(env1)," \ + "128k(env2);" \ + "mxc_nand.0:" \ + "128k(IPL-SPL)," \ + "4m(kernel)," \ + "22m(rootfs)," \ + "-(userfs)" + +#endif /* __CONFIG_H */ -- cgit v1.1 From 07739bcef5da07cc4a4edef8b91014ccc332eda3 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 28 Mar 2010 13:43:26 +0200 Subject: Moved board specific values in config file The lowlevel_init file contained some hard-coded values to setup the RAM. These board related values are moved into the board configuration file. Signed-off-by: Stefano Babic --- include/configs/mx51evk.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 903fe6d..3626df7 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -160,6 +160,9 @@ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define CONFIG_SYS_DDR_CLKSEL 0 +#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 + /*----------------------------------------------------------------------- * FLASH and environment organization */ -- cgit v1.1