From 7ed45d3d0a1deec19dd44d3590b779fc128ced8c Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 28 Oct 2015 11:46:35 +0100 Subject: hrcon: Add support for the DH variant hrcon DH(dual head) has two video outputs per FPGA. Signed-off-by: Dirk Eibach --- include/configs/hrcon.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++++ include/gdsys_fpga.h | 30 ++++++++++++++++++-------- 2 files changed, 77 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 696af0a..16d5885 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -20,7 +20,11 @@ #define CONFIG_SYS_TEXT_BASE 0xFE000000 +#ifdef CONFIG_HRCON_DH +#define CONFIG_IDENT_STRING " hrcon dh 0.01" +#else #define CONFIG_IDENT_STRING " hrcon 0.01" +#endif #define CONFIG_BOARD_EARLY_INIT_F @@ -343,6 +347,22 @@ #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F +#ifdef CONFIG_HRCON_DH +#define CONFIG_SYS_I2C_IHS_DUAL +#define CONFIG_SYS_I2C_IHS_CH0_1 +#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH1_1 +#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH2_1 +#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH3_1 +#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F +#endif + /* * Software (bit-bang) I2C driver configuration */ @@ -359,16 +379,48 @@ #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F +#ifdef CONFIG_HRCON_DH +#define I2C_SOFT_DECLARATIONS5 +#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F +#define I2C_SOFT_DECLARATIONS6 +#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F +#define I2C_SOFT_DECLARATIONS7 +#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F +#define I2C_SOFT_DECLARATIONS8 +#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F +#endif + +#ifdef CONFIG_HRCON_DH +#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12, 13, 14, 15, 16} +#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} +#else #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} +#endif #ifndef __ASSEMBLY__ void fpga_gpio_set(unsigned int bus, int pin); void fpga_gpio_clear(unsigned int bus, int pin); int fpga_gpio_get(unsigned int bus, int pin); +void fpga_control_set(unsigned int bus, int pin); +void fpga_control_clear(unsigned int bus, int pin); #endif +#ifdef CONFIG_HRCON_DH +#define I2C_ACTIVE \ + do { \ + if (I2C_ADAP_HWNR > 3) \ + fpga_control_set(I2C_ADAP_HWNR, 0x0004); \ + else \ + fpga_control_clear(I2C_ADAP_HWNR, 0x0004); \ + } while (0) +#else #define I2C_ACTIVE { } +#endif #define I2C_TRISTATE { } #define I2C_READ \ (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0) @@ -401,6 +453,10 @@ int fpga_gpio_get(unsigned int bus, int pin); #define CONFIG_SYS_DP501_DIFFERENTIAL #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ +#ifdef CONFIG_HRCON_DH +#define CONFIG_SYS_OSD_DH +#endif + /* * General PCI * Addresses are mapped 1-1. diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 69d248f..3b8762d 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -157,9 +157,9 @@ struct ihs_fpga { u16 mc_rx_data; /* 0x0072 */ u16 reserved_5[69]; /* 0x0074 */ u16 reflection_high; /* 0x00fe */ - struct ihs_osd osd; /* 0x0100 */ + struct ihs_osd osd0; /* 0x0100 */ u16 reserved_6[889]; /* 0x010e */ - u16 videomem[31736]; /* 0x0800 */ + u16 videomem0[2048]; /* 0x0800 */ }; #endif @@ -171,7 +171,9 @@ struct ihs_fpga { u16 fpga_features; /* 0x0006 */ u16 reserved_0[1]; /* 0x0008 */ u16 top_interrupt; /* 0x000a */ - u16 reserved_1[4]; /* 0x000c */ + u16 reserved_1[2]; /* 0x000c */ + u16 control; /* 0x0010 */ + u16 extended_control; /* 0x0012 */ struct ihs_gpio gpio; /* 0x0014 */ u16 mpc3w_control; /* 0x001a */ u16 reserved_2[2]; /* 0x001c */ @@ -191,9 +193,19 @@ struct ihs_fpga { u16 mc_rx_data; /* 0x0072 */ u16 reserved_5[69]; /* 0x0074 */ u16 reflection_high; /* 0x00fe */ - struct ihs_osd osd; /* 0x0100 */ + struct ihs_osd osd0; /* 0x0100 */ +#ifdef CONFIG_SYS_OSD_DH + u16 reserved_6[57]; /* 0x010e */ + struct ihs_osd osd1; /* 0x0180 */ + u16 reserved_7[9]; /* 0x018e */ + struct ihs_i2c i2c1; /* 0x01a0 */ + u16 reserved_8[1834]; /* 0x01ac */ + u16 videomem0[2048]; /* 0x1000 */ + u16 videomem1[2048]; /* 0x2000 */ +#else u16 reserved_6[889]; /* 0x010e */ - u16 videomem[31736]; /* 0x0800 */ + u16 videomem0[2048]; /* 0x0800 */ +#endif }; #endif @@ -254,9 +266,9 @@ struct ihs_fpga { u16 mc_rx_cmd_status; /* 0x0070 */ u16 mc_rx_data; /* 0x0072 */ u16 reserved_5[70]; /* 0x0074 */ - struct ihs_osd osd; /* 0x0100 */ + struct ihs_osd osd0; /* 0x0100 */ u16 reserved_6[889]; /* 0x010e */ - u16 videomem[31736]; /* 0x0800 */ + u16 videomem0[2048]; /* 0x0800 */ }; #endif @@ -275,9 +287,9 @@ struct ihs_fpga { u16 reserved_3[2]; /* 0x006c */ struct ihs_i2c i2c1; /* 0x0070 */ u16 reserved_4[194]; /* 0x007c */ - struct ihs_osd osd; /* 0x0200 */ + struct ihs_osd osd0; /* 0x0200 */ u16 reserved_5[761]; /* 0x020e */ - u16 videomem[31736]; /* 0x0800 */ + u16 videomem0[2048]; /* 0x0800 */ }; #endif -- cgit v1.1