From 0b135cfc2e524dc249b75057b55dd4cc09842e27 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 13 May 2007 20:58:00 +0900 Subject: sh: First support code of SuperH. Signed-off-by: Nobuhiro Iwamatsu --- include/asm-sh/bitops.h | 13 ++ include/asm-sh/byteorder.h | 31 +++++ include/asm-sh/cpu_sh4.h | 10 ++ include/asm-sh/cpu_sh7750.h | 145 +++++++++++++++++++++ include/asm-sh/global_data.h | 50 ++++++++ include/asm-sh/io.h | 292 +++++++++++++++++++++++++++++++++++++++++++ include/asm-sh/posix_types.h | 123 ++++++++++++++++++ include/asm-sh/processor.h | 8 ++ include/asm-sh/ptrace.h | 112 +++++++++++++++++ include/asm-sh/string.h | 132 +++++++++++++++++++ include/asm-sh/system.h | 275 ++++++++++++++++++++++++++++++++++++++++ include/asm-sh/types.h | 59 +++++++++ include/asm-sh/u-boot.h | 44 +++++++ 13 files changed, 1294 insertions(+) create mode 100644 include/asm-sh/bitops.h create mode 100644 include/asm-sh/byteorder.h create mode 100644 include/asm-sh/cpu_sh4.h create mode 100644 include/asm-sh/cpu_sh7750.h create mode 100644 include/asm-sh/global_data.h create mode 100644 include/asm-sh/io.h create mode 100644 include/asm-sh/posix_types.h create mode 100644 include/asm-sh/processor.h create mode 100644 include/asm-sh/ptrace.h create mode 100644 include/asm-sh/string.h create mode 100644 include/asm-sh/system.h create mode 100644 include/asm-sh/types.h create mode 100644 include/asm-sh/u-boot.h (limited to 'include') diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h new file mode 100644 index 0000000..44dca9f --- /dev/null +++ b/include/asm-sh/bitops.h @@ -0,0 +1,13 @@ +#ifndef __ASM_SH_BITOPS_H_ +#define __ASM_SH_BITOPS_H_ + +extern void set_bit(int nr, volatile void * a); +extern void clear_bit(int nr, volatile void * a); +extern int test_and_clear_bit(int nr, volatile void * a); +extern void change_bit(unsigned long nr, volatile void *addr); +extern int test_and_set_bit(int nr, volatile void * a); +extern int test_and_change_bit(int nr, volatile void * addr); +extern int test_bit(int nr, volatile void * a); +extern int ffs(int i); + +#endif diff --git a/include/asm-sh/byteorder.h b/include/asm-sh/byteorder.h new file mode 100644 index 0000000..8836e65 --- /dev/null +++ b/include/asm-sh/byteorder.h @@ -0,0 +1,31 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_SH_BYTEORDER_H_ +#define __ASM_SH_BYTEORDER_H_ + +#include +#include + +#ifdef __LITTLE_ENDIAN__ +#include +#else +#include +#endif + +#endif + diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h new file mode 100644 index 0000000..e0275f3 --- /dev/null +++ b/include/asm-sh/cpu_sh4.h @@ -0,0 +1,10 @@ +#ifndef _ASM_CPU_SH4_H_ +#define _ASM_CPU_SH4_H_ +#if defined (CONFIG_CPU_SH7750) +#include +#elif defined (CONFIG_CPU_SH7780) +#include +#else +#error "Unknown SH4 variant" +#endif +#endif diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h new file mode 100644 index 0000000..eb4f1af --- /dev/null +++ b/include/asm-sh/cpu_sh7750.h @@ -0,0 +1,145 @@ +#ifndef _ASM_CPU_SH7750_H_ +#define _ASM_CPU_SH7750_H_ + +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define BASRA 0xFF000014 +#define BASRB 0xFF000018 +#define CCR 0xFF00001C +#define TRA 0xFF000020 +#define EXPEVT 0xFF000024 +#define INTEVT 0xFF000028 +#define PTEA 0xFF000034 +#define QACR0 0xFF000038 +#define QACR1 0xFF00003C +#define BARA 0xFF200000 +#define BAMRA 0xFF200004 +#define BBRA 0xFF200008 +#define BARB 0xFF20000C +#define BAMRB 0xFF200010 +#define BBRB 0xFF200014 +#define BDRB 0xFF200018 +#define BDMRB 0xFF20001C +#define BRCR 0xFF200020 + +#define BCR1 0xFF800000 +#define BCR2 0xFF800004 +#define BCR3 0xFF800050 +#define BCR4 0xFE0A00F0 +#define WCR1 0xFF800008 +#define WCR2 0xFF80000C +#define WCR3 0xFF800010 +#define MCR 0xFF800014 +#define PCR 0xFF800018 +#define RTCSR 0xFF80001C +#define RTCNT 0xFF800020 +#define RTCOR 0xFF800024 +#define RFCR 0xFF800028 +#define PCTRA 0xFF80002C +#define PDTRA 0xFF800030 +#define PCTRB 0xFF800040 +#define PDTRB 0xFF800044 +#define GPIOIC 0xFF800048 +#define SAR0 0xFFA00000 +#define DAR0 0xFFA00004 +#define DMATCR0 0xFFA00008 +#define CHCR0 0xFFA0000C +#define SAR1 0xFFA00010 +#define DAR1 0xFFA00014 +#define DMATCR1 0xFFA00018 +#define CHCR1 0xFFA0001C +#define SAR2 0xFFA00020 +#define DAR2 0xFFA00024 +#define DMATCR2 0xFFA00028 +#define CHCR2 0xFFA0002C +#define SAR3 0xFFA00030 +#define DAR3 0xFFA00034 +#define DMATCR3 0xFFA00038 +#define CHCR3 0xFFA0003C +#define DMAOR 0xFFA00040 +#define SAR4 0xFFA00050 +#define DAR4 0xFFA00054 +#define DMATCR4 0xFFA00058 + +#define FRQCR 0xFFC00000 +#define STBCR 0xFFC00004 +#define WTCNT 0xFFC00008 +#define WTCSR 0xFFC0000C +#define STBCR2 0xFFC00010 +#define R64CNT 0xFFC80000 +#define RSECCNT 0xFFC80004 +#define RMINCNT 0xFFC80008 +#define RHRCNT 0xFFC8000C +#define RWKCNT 0xFFC80010 +#define RDAYCNT 0xFFC80014 +#define RMONCNT 0xFFC80018 +#define RYRCNT 0xFFC8001C +#define RSECAR 0xFFC80020 +#define RMINAR 0xFFC80024 +#define RHRAR 0xFFC80028 +#define RWKAR 0xFFC8002C +#define RDAYAR 0xFFC80030 +#define RMONAR 0xFFC80034 +#define RCR1 0xFFC80038 +#define RCR2 0xFFC8003C +#define RCR3 0xFFC80050 +#define RYRAR 0xFFC80054 +#define ICR 0xFFD00000 +#define IPRA 0xFFD00004 +#define IPRB 0xFFD00008 +#define IPRC 0xFFD0000C +#define IPRD 0xFFD00010 +#define INTPRI 0xFE080000 +#define INTREQ 0xFE080020 +#define INTMSK 0xFE080040 +#define INTMSKCL 0xFE080060 +#define CLKSTP 0xFE0A0000 +#define CLKSTPCLR 0xFE0A0008 +#define TSTR2 0xFE100004 +#define TCOR3 0xFE100008 +#define TCNT3 0xFE10000C +#define TCR3 0xFE100010 +#define TCOR4 0xFE100014 +#define TCNT4 0xFE100018 +#define TCR4 0xFE10001C +#define TOCR 0xFFD80000 +#define TSTR0 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 +#define TCPR2 0xFFD8002C +#define SCSMR1 0xFFE00000 +#define SCBRR1 0xFFE00004 +#define SCSCR1 0xFFE00008 +#define SCTDR1 0xFFE0000C +#define SCSSR1 0xFFE00010 +#define SCRDR1 0xFFE00014 +#define SCSCMR1 0xFFE00018 +#define SCSPTR1 0xFFE0001C +#define SCF0_BASE SCSMR1 +#define SCSMR2 0xFFE80000 +#define SCBRR2 0xFFE80004 +#define SCSCR2 0xFFE80008 +#define SCFTDR2 0xFFE8000C +#define SCFSR2 0xFFE80010 +#define SCFRDR2 0xFFE80014 +#define SCFCR2 0xFFE80018 +#define SCFDR2 0xFFE8001C +#define SCSPTR2 0xFFE80020 +#define SCLSR2 0xFFE80024 +#define SCIF1_BASE SCSMR2 +#define SDIR 0xFFF00000 +#define SDDR 0xFFF00008 +#define SDINT 0xFFF00014 + +#endif /* _ASM_CPU_SH7750_H_ */ + diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h new file mode 100644 index 0000000..0a44a34 --- /dev/null +++ b/include/asm-sh/global_data.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 + * Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_SH_GLOBALDATA_H_ +#define __ASM_SH_GLOBALDATA_H_ + +typedef struct global_data +{ + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long have_console; /* serial_init() was called */ + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid */ + void **jt; /* Standalone app jump table */ +}gd_t; + +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13") + +#endif /* __ASM_SH_GLOBALDATA_H_ */ diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h new file mode 100644 index 0000000..70e60b1 --- /dev/null +++ b/include/asm-sh/io.h @@ -0,0 +1,292 @@ +/* + * linux/include/asm-sh/io.h + * + * Copyright (C) 1996-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + */ +#ifndef __ASM_SH_IO_H +#define __ASM_SH_IO_H + +#ifdef __KERNEL__ + +#include +#include + +/* + * Generic virtual read/write. Note that we don't support half-word + * read/writes. We define __arch_*[bl] here, and leave __arch_*w + * to the architecture specific code. + */ +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) + +#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) + +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v,a) __arch_putb(v,a) +#define __raw_writew(v,a) __arch_putw(v,a) +#define __raw_writel(v,a) __arch_putl(v,a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) + +/* + * The compiler seems to be incapable of optimising constants + * properly. Spell it out to the compiler in some cases. + * These are only valid for small values of "off" (< 1<<12) + */ +#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) +#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) +#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) + +#define __raw_base_readb(base,off) __arch_base_getb(base,off) +#define __raw_base_readw(base,off) __arch_base_getw(base,off) +#define __raw_base_readl(base,off) __arch_base_getl(base,off) + +/* + * Now, pick up the machine-defined IO definitions + */ +#if 0 /* XXX###XXX */ +#include +#endif /* XXX###XXX */ + +/* + * IO port access primitives + * ------------------------- + * + * The SH doesn't have special IO access instructions; all IO is memory + * mapped. Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. + * + * Note that we prevent GCC re-ordering or caching values in expressions + * by introducing sequence points into the in*() definitions. Note that + * __raw_* do not guarantee this behaviour. + * + * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. + */ +#ifdef __io +#define outb(v,p) __raw_writeb(v,__io(p)) +#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) + +#define outsb(p,d,l) __raw_writesb(__io(p),d,l) +#define outsw(p,d,l) __raw_writesw(__io(p),d,l) +#define outsl(p,d,l) __raw_writesl(__io(p),d,l) + +#define insb(p,d,l) __raw_readsb(__io(p),d,l) +#define insw(p,d,l) __raw_readsw(__io(p),d,l) +#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#endif + +#define outb_p(val,port) outb((val),(port)) +#define outw_p(val,port) outw((val),(port)) +#define outl_p(val,port) outl((val),(port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port,from,len) outsb(port,from,len) +#define outsw_p(port,from,len) outsw(port,from,len) +#define outsl_p(port,from,len) outsl(port,from,len) +#define insb_p(port,to,len) insb(port,to,len) +#define insw_p(port,to,len) insw(port,to,len) +#define insl_p(port,to,len) insl(port,to,len) + +/* + * ioremap and friends. + * + * ioremap takes a PCI memory address, as specified in + * linux/Documentation/IO-mapping.txt. If you want a + * physical address, use __ioremap instead. + */ +extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); +extern void __iounmap(void *addr); + +/* + * Generic ioremap support. + * + * Define: + * iomem_valid_addr(off,size) + * iomem_to_phys(off) + */ +#ifdef iomem_valid_addr +#define __arch_ioremap(off,sz,nocache) \ + ({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off),_size,0); \ + _ret; \ + }) + +#define __arch_iounmap __iounmap +#endif + +#define ioremap(off,sz) __arch_ioremap((off),(sz),0) +#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) +#define iounmap(_addr) __arch_iounmap(_addr) + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +extern void consistent_sync(void *vaddr, size_t size, int rw); + +/* + * String version of IO memory access ops: + */ +extern void _memcpy_fromio(void *, unsigned long, size_t); +extern void _memcpy_toio(unsigned long, const void *, size_t); +extern void _memset_io(unsigned long, int, size_t); + +extern void __readwrite_bug(const char *fn); + +/* + * If this architecture has PCI memory IO, then define the read/write + * macros. These should only be used with the cookie passed from + * ioremap. + */ +#ifdef __mem_pci + +#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) + +#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) +#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) + +#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) +#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) +#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) + +#define eth_io_copy_and_sum(s,c,l,b) \ + eth_copy_and_sum((s),__mem_pci(c),(l),(b)) + +static inline int +check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#elif !defined(readb) + +#define readb(addr) (__readwrite_bug("readb"),0) +#define readw(addr) (__readwrite_bug("readw"),0) +#define readl(addr) (__readwrite_bug("readl"),0) +#define writeb(v,addr) __readwrite_bug("writeb") +#define writew(v,addr) __readwrite_bug("writew") +#define writel(v,addr) __readwrite_bug("writel") + +#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") + +#define check_signature(io,sig,len) (0) + +#endif /* __mem_pci */ + +/* + * If this architecture has ISA IO, then define the isa_read/isa_write + * macros. + */ +#ifdef __mem_isa + +#define isa_readb(addr) __raw_readb(__mem_isa(addr)) +#define isa_readw(addr) __raw_readw(__mem_isa(addr)) +#define isa_readl(addr) __raw_readl(__mem_isa(addr)) +#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) +#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) +#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) +#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + eth_copy_and_sum((a),__mem_isa(b),(c),(d)) + +static inline int +isa_check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (isa_readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#else /* __mem_isa */ + +#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) +#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) +#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) +#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") +#define isa_writew(val,addr) __readwrite_bug("isa_writew") +#define isa_writel(val,addr) __readwrite_bug("isa_writel") +#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") +#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") +#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + __readwrite_bug("isa_eth_io_copy_and_sum") + +#define isa_check_signature(io,sig,len) (0) + +static inline void sync(void) +{ +} + +#endif /* __mem_isa */ +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_IO_H */ diff --git a/include/asm-sh/posix_types.h b/include/asm-sh/posix_types.h new file mode 100644 index 0000000..4bb9f7e --- /dev/null +++ b/include/asm-sh/posix_types.h @@ -0,0 +1,123 @@ +#ifndef __ASM_SH_POSIX_TYPES_H +#define __ASM_SH_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; +typedef unsigned short __kernel_old_dev_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); +} + + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *__p) +{ + unsigned long *__tmp = __p->fds_bits; + int __i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 16: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + __tmp[ 8] = 0; __tmp[ 9] = 0; + __tmp[10] = 0; __tmp[11] = 0; + __tmp[12] = 0; __tmp[13] = 0; + __tmp[14] = 0; __tmp[15] = 0; + return; + + case 8: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + return; + + case 4: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + return; + } + } + __i = __FDSET_LONGS; + while (__i) { + __i--; + *__tmp = 0; + __tmp++; + } +} + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* __ASM_SH_POSIX_TYPES_H */ diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h new file mode 100644 index 0000000..bb9a35f --- /dev/null +++ b/include/asm-sh/processor.h @@ -0,0 +1,8 @@ +#ifndef _ASM_SH_PROCESSOR_H_ +#define _ASM_SH_PROCESSOR_H_ +#if defined CONFIG_SH3 +# include +#elif defined (CONFIG_SH4) +# include +#endif +#endif diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h new file mode 100644 index 0000000..14cc1ac --- /dev/null +++ b/include/asm-sh/ptrace.h @@ -0,0 +1,112 @@ +#ifndef __ASM_SH_PTRACE_H +#define __ASM_SH_PTRACE_H + +/* + * Copyright (C) 1999, 2000 Niibe Yutaka + * from linux kernel code. + */ + +/* + * GCC defines register number like this: + * ----------------------------- + * 0 - 15 are integer registers + * 17 - 22 are control/special registers + * 24 - 39 fp registers + * 40 - 47 xd registers + * 48 - fpscr register + * ----------------------------- + * + * We follows above, except: + * 16 --- program counter (PC) + * 22 --- syscall # + * 23 --- floating point communication register + */ +#define REG_REG0 0 +#define REG_REG15 15 + +#define REG_PC 16 + +#define REG_PR 17 +#define REG_SR 18 +#define REG_GBR 19 +#define REG_MACH 20 +#define REG_MACL 21 + +#define REG_SYSCALL 22 + +#define REG_FPREG0 23 +#define REG_FPREG15 38 +#define REG_XFREG0 39 +#define REG_XFREG15 54 + +#define REG_FPSCR 55 +#define REG_FPUL 56 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_regs { + unsigned long regs[16]; + unsigned long pc; + unsigned long pr; + unsigned long sr; + unsigned long gbr; + unsigned long mach; + unsigned long macl; + long tra; +}; + +/* + * This struct defines the way the DSP registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_dspregs { + unsigned long a1; + unsigned long a0g; + unsigned long a1g; + unsigned long m0; + unsigned long m1; + unsigned long a0; + unsigned long x0; + unsigned long x1; + unsigned long y0; + unsigned long y1; + unsigned long dsr; + unsigned long rs; + unsigned long re; + unsigned long mod; +}; + +#define PTRACE_GETDSPREGS 55 +#define PTRACE_SETDSPREGS 56 + +#ifdef __KERNEL__ +#define user_mode(regs) (((regs)->sr & 0x40000000)==0) +#define instruction_pointer(regs) ((regs)->pc) +extern void show_regs(struct pt_regs *); + +#ifdef CONFIG_SH_DSP +#define task_pt_regs(task) \ + ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ + - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1) +#else +#define task_pt_regs(task) \ + ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ + - sizeof(unsigned long)) - 1) +#endif + +static inline unsigned long profile_pc(struct pt_regs *regs) +{ + unsigned long pc = instruction_pointer(regs); + + if (pc >= 0xa0000000UL && pc < 0xc0000000UL) + pc -= 0x20000000; + return pc; +} +#endif + +#endif /* __ASM_SH_PTRACE_H */ diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h new file mode 100644 index 0000000..a78ef81 --- /dev/null +++ b/include/asm-sh/string.h @@ -0,0 +1,132 @@ +#ifndef __ASM_SH_STRING_H +#define __ASM_SH_STRING_H + +/* + * Copyright (C) 1999 Niibe Yutaka + * But consider these trivial functions to be public domain. + * + * from linux kernel code. + */ + +#define __HAVE_ARCH_STRCPY +static inline char *strcpy(char *__dest, const char *__src) +{ + register char *__xdest = __dest; + unsigned long __dummy; + + __asm__ __volatile__("1:\n\t" + "mov.b @%1+, %2\n\t" + "mov.b %2, @%0\n\t" + "cmp/eq #0, %2\n\t" + "bf/s 1b\n\t" + " add #1, %0\n\t" + : "=r" (__dest), "=r" (__src), "=&z" (__dummy) + : "0" (__dest), "1" (__src) + : "memory", "t"); + + return __xdest; +} + +#define __HAVE_ARCH_STRNCPY +static inline char *strncpy(char *__dest, const char *__src, size_t __n) +{ + register char *__xdest = __dest; + unsigned long __dummy; + + if (__n == 0) + return __xdest; + + __asm__ __volatile__( + "1:\n" + "mov.b @%1+, %2\n\t" + "mov.b %2, @%0\n\t" + "cmp/eq #0, %2\n\t" + "bt/s 2f\n\t" + " cmp/eq %5,%1\n\t" + "bf/s 1b\n\t" + " add #1, %0\n" + "2:" + : "=r" (__dest), "=r" (__src), "=&z" (__dummy) + : "0" (__dest), "1" (__src), "r" (__src+__n) + : "memory", "t"); + + return __xdest; +} + +#define __HAVE_ARCH_STRCMP +static inline int strcmp(const char *__cs, const char *__ct) +{ + register int __res; + unsigned long __dummy; + + __asm__ __volatile__( + "mov.b @%1+, %3\n" + "1:\n\t" + "mov.b @%0+, %2\n\t" + "cmp/eq #0, %3\n\t" + "bt 2f\n\t" + "cmp/eq %2, %3\n\t" + "bt/s 1b\n\t" + " mov.b @%1+, %3\n\t" + "add #-2, %1\n\t" + "mov.b @%1, %3\n\t" + "sub %3, %2\n" + "2:" + : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) + : "0" (__cs), "1" (__ct) + : "t"); + + return __res; +} + +#define __HAVE_ARCH_STRNCMP +static inline int strncmp(const char *__cs, const char *__ct, size_t __n) +{ + register int __res; + unsigned long __dummy; + + if (__n == 0) + return 0; + + __asm__ __volatile__( + "mov.b @%1+, %3\n" + "1:\n\t" + "mov.b @%0+, %2\n\t" + "cmp/eq %6, %0\n\t" + "bt/s 2f\n\t" + " cmp/eq #0, %3\n\t" + "bt/s 3f\n\t" + " cmp/eq %3, %2\n\t" + "bt/s 1b\n\t" + " mov.b @%1+, %3\n\t" + "add #-2, %1\n\t" + "mov.b @%1, %3\n" + "2:\n\t" + "sub %3, %2\n" + "3:" + :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) + : "0" (__cs), "1" (__ct), "r" (__cs+__n) + : "t"); + + return __res; +} + +#undef __HAVE_ARCH_MEMSET +extern void *memset(void *__s, int __c, size_t __count); + +#undef __HAVE_ARCH_MEMCPY +extern void *memcpy(void *__to, __const__ void *__from, size_t __n); + +#undef __HAVE_ARCH_MEMMOVE +extern void *memmove(void *__dest, __const__ void *__src, size_t __n); + +#undef __HAVE_ARCH_MEMCHR +extern void *memchr(const void *__s, int __c, size_t __n); + +#undef __HAVE_ARCH_STRLEN +extern size_t strlen(const char *); + +/* arch/sh/lib/strcasecmp.c */ +extern int strcasecmp(const char *, const char *); + +#endif /* __ASM_SH_STRING_H */ diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h new file mode 100644 index 0000000..b353bc5 --- /dev/null +++ b/include/asm-sh/system.h @@ -0,0 +1,275 @@ +#ifndef __ASM_SH_SYSTEM_H +#define __ASM_SH_SYSTEM_H + +/* + * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima + * Copyright (C) 2002 Paul Mundt + * + * from linux kernel code. + */ + +#include +#include + +/* + * switch_to() should switch tasks to task nr n, first + */ + +#define switch_to(prev, next, last) do { \ + struct task_struct *__last; \ + register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \ + register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \ + register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \ + register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \ + register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \ + register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \ + __asm__ __volatile__ (".balign 4\n\t" \ + "stc.l gbr, @-r15\n\t" \ + "sts.l pr, @-r15\n\t" \ + "mov.l r8, @-r15\n\t" \ + "mov.l r9, @-r15\n\t" \ + "mov.l r10, @-r15\n\t" \ + "mov.l r11, @-r15\n\t" \ + "mov.l r12, @-r15\n\t" \ + "mov.l r13, @-r15\n\t" \ + "mov.l r14, @-r15\n\t" \ + "mov.l r15, @r1 ! save SP\n\t" \ + "mov.l @r6, r15 ! change to new stack\n\t" \ + "mova 1f, %0\n\t" \ + "mov.l %0, @r2 ! save PC\n\t" \ + "mov.l 2f, %0\n\t" \ + "jmp @%0 ! call __switch_to\n\t" \ + " lds r7, pr ! with return to new PC\n\t" \ + ".balign 4\n" \ + "2:\n\t" \ + ".long __switch_to\n" \ + "1:\n\t" \ + "mov.l @r15+, r14\n\t" \ + "mov.l @r15+, r13\n\t" \ + "mov.l @r15+, r12\n\t" \ + "mov.l @r15+, r11\n\t" \ + "mov.l @r15+, r10\n\t" \ + "mov.l @r15+, r9\n\t" \ + "mov.l @r15+, r8\n\t" \ + "lds.l @r15+, pr\n\t" \ + "ldc.l @r15+, gbr\n\t" \ + : "=z" (__last) \ + : "r" (__ts1), "r" (__ts2), "r" (__ts4), \ + "r" (__ts5), "r" (__ts6), "r" (__ts7) \ + : "r3", "t"); \ + last = __last; \ +} while (0) + +/* + * On SMP systems, when the scheduler does migration-cost autodetection, + * it needs a way to flush as much of the CPU's caches as possible. + * + * TODO: fill this in! + */ +static inline void sched_cacheflush(void) +{ +} + +#ifdef CONFIG_CPU_SH4A +#define __icbi() \ +{ \ + unsigned long __addr; \ + __addr = 0xa8000000; \ + __asm__ __volatile__( \ + "icbi %0\n\t" \ + : /* no output */ \ + : "m" (__m(__addr))); \ +} +#endif + +static inline unsigned long tas(volatile int *m) +{ + unsigned long retval; + + __asm__ __volatile__ ("tas.b @%1\n\t" + "movt %0" + : "=r" (retval): "r" (m): "t", "memory"); + return retval; +} + +/* + * A brief note on ctrl_barrier(), the control register write barrier. + * + * Legacy SH cores typically require a sequence of 8 nops after + * modification of a control register in order for the changes to take + * effect. On newer cores (like the sh4a and sh5) this is accomplished + * with icbi. + * + * Also note that on sh4a in the icbi case we can forego a synco for the + * write barrier, as it's not necessary for control registers. + * + * Historically we have only done this type of barrier for the MMUCR, but + * it's also necessary for the CCR, so we make it generic here instead. + */ +#ifdef CONFIG_CPU_SH4A +#define mb() __asm__ __volatile__ ("synco": : :"memory") +#define rmb() mb() +#define wmb() __asm__ __volatile__ ("synco": : :"memory") +#define ctrl_barrier() __icbi() +#define read_barrier_depends() do { } while(0) +#else +#define mb() __asm__ __volatile__ ("": : :"memory") +#define rmb() mb() +#define wmb() __asm__ __volatile__ ("": : :"memory") +#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") +#define read_barrier_depends() do { } while(0) +#endif + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#define smp_read_barrier_depends() read_barrier_depends() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() do { } while(0) +#endif + +#define set_mb(var, value) do { xchg(&var, value); } while (0) + +/* + * Jump to P2 area. + * When handling TLB or caches, we need to do it from P2 area. + */ +#define jump_to_P2() \ +do { \ + unsigned long __dummy; \ + __asm__ __volatile__( \ + "mov.l 1f, %0\n\t" \ + "or %1, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy) \ + : "r" (0x20000000)); \ +} while (0) + +/* + * Back to P1 area. + */ +#define back_to_P1() \ +do { \ + unsigned long __dummy; \ + ctrl_barrier(); \ + __asm__ __volatile__( \ + "mov.l 1f, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy)); \ +} while (0) + +static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) +{ + unsigned long flags, retval; + + local_irq_save(flags); + retval = *m; + *m = val; + local_irq_restore(flags); + return retval; +} + +static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) +{ + unsigned long flags, retval; + + local_irq_save(flags); + retval = *m; + *m = val & 0xff; + local_irq_restore(flags); + return retval; +} + +extern void __xchg_called_with_bad_pointer(void); + +#define __xchg(ptr, x, size) \ +({ \ + unsigned long __xchg__res; \ + volatile void *__xchg_ptr = (ptr); \ + switch (size) { \ + case 4: \ + __xchg__res = xchg_u32(__xchg_ptr, x); \ + break; \ + case 1: \ + __xchg__res = xchg_u8(__xchg_ptr, x); \ + break; \ + default: \ + __xchg_called_with_bad_pointer(); \ + __xchg__res = x; \ + break; \ + } \ + \ + __xchg__res; \ +}) + +#define xchg(ptr,x) \ + ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr)))) + +static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, + unsigned long new) +{ + __u32 retval; + unsigned long flags; + + local_irq_save(flags); + retval = *m; + if (retval == old) + *m = new; + local_irq_restore(flags); /* implies memory barrier */ + return retval; +} + +/* This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid cmpxchg(). */ +extern void __cmpxchg_called_with_bad_pointer(void); + +#define __HAVE_ARCH_CMPXCHG 1 + +static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, + unsigned long new, int size) +{ + switch (size) { + case 4: + return __cmpxchg_u32(ptr, old, new); + } + __cmpxchg_called_with_bad_pointer(); + return old; +} + +#define cmpxchg(ptr,o,n) \ + ({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ + (unsigned long)_n_, sizeof(*(ptr))); \ + }) + +extern void *set_exception_table_vec(unsigned int vec, void *handler); + +static inline void *set_exception_table_evt(unsigned int evt, void *handler) +{ + return set_exception_table_vec(evt >> 5, handler); +} + +/* XXX + * disable hlt during certain critical i/o operations + */ +#define HAVE_DISABLE_HLT +void disable_hlt(void); +void enable_hlt(void); + +#define arch_align_stack(x) (x) + +#endif diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h new file mode 100644 index 0000000..fd00dbb --- /dev/null +++ b/include/asm-sh/types.h @@ -0,0 +1,59 @@ +#ifndef __ASM_SH_TYPES_H +#define __ASM_SH_TYPES_H + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +#endif /* __ASSEMBLY__ */ + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +#define BITS_PER_LONG 32 + +#ifndef __ASSEMBLY__ + + +typedef __signed__ char s8; +typedef unsigned char u8; + +typedef __signed__ short s16; +typedef unsigned short u16; + +typedef __signed__ int s32; +typedef unsigned int u32; + +typedef __signed__ long long s64; +typedef unsigned long long u64; + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_TYPES_H */ diff --git a/include/asm-sh/u-boot.h b/include/asm-sh/u-boot.h new file mode 100644 index 0000000..c74e97c --- /dev/null +++ b/include/asm-sh/u-boot.h @@ -0,0 +1,44 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __ASM_SH_U_BOOT_H_ +#define __ASM_SH_U_BOOT_H_ + + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_baudrate; /* Console Baudrate */ + unsigned long bi_boot_params; /* where this board expects params */ +} bd_t; + +#endif + -- cgit v1.1 From 69df3c4da0c93017cceb25a366e794570bd0ed98 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 13 May 2007 21:01:03 +0900 Subject: sh: MS7750SE support. This adds support for the Hitachi MS7750SE. Signed-off-by: Nobuhiro Iwamatsu --- include/configs/ms7750se.h | 75 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 include/configs/ms7750se.h (limited to 'include') diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h new file mode 100644 index 0000000..0467a5e --- /dev/null +++ b/include/configs/ms7750se.h @@ -0,0 +1,75 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +#define CONFIG_SH 1 +#define CONFIG_SH4 1 +#define CONFIG_CPU_SH7750 1 +#define CONFIG_MS7750SE 1 +#define __LITTLE_ENDIAN__ 1 + +//#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NET |CFG_CMD_PING) +#define CONFIG_COMMANDS CONFIG_CMD_DFL & ~CFG_CMD_NET + +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_SCIF1 1 +#define BOARD_LATE_INIT 1 + +#include + +#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTARGS "console=ttySC0,115200" +#define CONFIG_ENV_OVERWRITE 1 + +#define CFG_SDRAM_BASE (0x8C000000) +#define CFG_SDRAM_SIZE (64 * 1024 * 1024) + +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +#define CFG_CBSIZE 256 +#define CFG_PBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_BARGSIZE 512 +#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } /* List of legal baudrate settings for this board */ + +#define CFG_MEMTEST_START (CFG_SDRAM_BASE) +#define CFG_MEMTEST_END (TEXT_BASE - 0x100000) + + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) +#define CFG_MONITOR_BASE (CFG_FLASH_BASE) /* Address of u-boot image in Flash */ +#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ + +#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) +#define CFG_RX_ETH_BUFFER (8) + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#undef CFG_FLASH_CFI_BROKEN_TABLE +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_BASE (0xA1000000) +#define CFG_MAX_FLASH_BANKS (1) /* Max number of + * Flash memory banks + */ +#define CFG_MAX_FLASH_SECT 142 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_FLASH_ERASE_TOUT 120000 +#define CFG_FLASH_WRITE_TOUT 500 + +#define CONFIG_SYS_CLK_FREQ 33333333 +#define TMU_CLK_DIVIDER 4 +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) +#define CFG_PLL_SETTLING_TIME 100 /* in us */ + +#endif /* __CONFIG_H */ -- cgit v1.1 From b02bad128669e567fce87d8df823b06a0144b8db Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 23 Sep 2007 02:12:30 +0900 Subject: sh: Update core code of SuperH. Signed-off-by: Nobuhiro Iwamatsu --- include/asm-sh/bitops.h | 175 +++++++++++++++++++++++++-- include/asm-sh/cpu_sh4.h | 44 ++++++- include/asm-sh/cpu_sh7750.h | 281 ++++++++++++++++++++++++++------------------ include/asm-sh/errno.h | 156 ++++++++++++++++++++++++ include/asm-sh/io.h | 103 ++++------------ include/asm-sh/irqflags.h | 126 ++++++++++++++++++++ include/asm-sh/string.h | 30 +++++ 7 files changed, 704 insertions(+), 211 deletions(-) create mode 100644 include/asm-sh/errno.h create mode 100644 include/asm-sh/irqflags.h (limited to 'include') diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h index 44dca9f..529d0f2 100644 --- a/include/asm-sh/bitops.h +++ b/include/asm-sh/bitops.h @@ -1,13 +1,166 @@ -#ifndef __ASM_SH_BITOPS_H_ -#define __ASM_SH_BITOPS_H_ - -extern void set_bit(int nr, volatile void * a); -extern void clear_bit(int nr, volatile void * a); -extern int test_and_clear_bit(int nr, volatile void * a); -extern void change_bit(unsigned long nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void * a); -extern int test_and_change_bit(int nr, volatile void * addr); -extern int test_bit(int nr, volatile void * a); -extern int ffs(int i); +#ifndef __ASM_SH_BITOPS_H +#define __ASM_SH_BITOPS_H +#ifdef __KERNEL__ +//#include +#include +/* For __swab32 */ +#include + +static inline void set_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a |= mask; + local_irq_restore(flags); +} + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() +static inline void clear_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a &= ~mask; + local_irq_restore(flags); +} + +static inline void change_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a ^= mask; + local_irq_restore(flags); +} + +static inline int test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a |= mask; + local_irq_restore(flags); + + return retval; +} + +static inline int test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + local_irq_restore(flags); + + return retval; +} + +static inline int test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a ^= mask; + local_irq_restore(flags); + + return retval; +} + +//#include + +static inline unsigned long ffz(unsigned long word) +{ + unsigned long result; + + __asm__("1:\n\t" + "shlr %1\n\t" + "bt/s 1b\n\t" + " add #1, %0" + : "=r" (result), "=r" (word) + : "0" (~0L), "1" (word) + : "t"); + return result; +} + +/** + * ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static inline int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +#if 0 +#include +#include +#include +#include +#include +#include +#include +#include +#include #endif +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_BITOPS_H */ diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h index e0275f3..dca61ca 100644 --- a/include/asm-sh/cpu_sh4.h +++ b/include/asm-sh/cpu_sh4.h @@ -1,10 +1,48 @@ +/* + * (C) Copyright 2007 Nobuhiro Iwamatsu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef _ASM_CPU_SH4_H_ #define _ASM_CPU_SH4_H_ + +/* cache control */ +#define CCR_CACHE_STOP 0x00000808 +#define CCR_CACHE_ENABLE 0x00000101 +#define CCR_CACHE_ICI 0x00000800 + +#define CACHE_OC_ADDRESS_ARRAY 0xf4000000 +#define CACHE_OC_WAY_SHIFT 14 +#define CACHE_OC_NUM_ENTRIES 512 +#define CACHE_OC_ENTRY_SHIFT 5 +//#define CACHE_OC_NUM_WAYS 1 + #if defined (CONFIG_CPU_SH7750) #include -#elif defined (CONFIG_CPU_SH7780) -#include +//#ifdef CONFIG_CPU_TYPE_R +//#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ +//#else +//#define CCR_CACHE_INIT 0x0000090b +//#endif +#elif defined (CONFIG_CPU_SH7722) +#include +//#define CCR_CACHE_INIT 0x0000090d #else #error "Unknown SH4 variant" #endif -#endif + +#endif /* _ASM_CPU_SH4_H_ */ diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h index eb4f1af..9993e63 100644 --- a/include/asm-sh/cpu_sh7750.h +++ b/include/asm-sh/cpu_sh7750.h @@ -1,13 +1,44 @@ +/* + * (C) Copyright 2007 Nobuhiro Iwamatsu + * + * SH7750/SH7750S/SH7750R/SH7751/SH7751R + * Internal I/O register + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef _ASM_CPU_SH7750_H_ #define _ASM_CPU_SH7750_H_ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define BASRA 0xFF000014 -#define BASRB 0xFF000018 +#ifdef CONFIG_CPU_TYPE_R +#define CACHE_OC_NUM_WAYS 2 +#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ +#else +#define CACHE_OC_NUM_WAYS 1 +#define CCR_CACHE_INIT 0x0000090b +#endif + +/* OCN */ +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define BASRA 0xFF000014 +#define BASRB 0xFF000018 #define CCR 0xFF00001C #define TRA 0xFF000020 #define EXPEVT 0xFF000024 @@ -15,6 +46,8 @@ #define PTEA 0xFF000034 #define QACR0 0xFF000038 #define QACR1 0xFF00003C + +/* UBC */ #define BARA 0xFF200000 #define BAMRA 0xFF200004 #define BBRA 0xFF200008 @@ -25,121 +58,139 @@ #define BDMRB 0xFF20001C #define BRCR 0xFF200020 +/* BSC */ #define BCR1 0xFF800000 -#define BCR2 0xFF800004 -#define BCR3 0xFF800050 -#define BCR4 0xFE0A00F0 -#define WCR1 0xFF800008 -#define WCR2 0xFF80000C -#define WCR3 0xFF800010 -#define MCR 0xFF800014 -#define PCR 0xFF800018 -#define RTCSR 0xFF80001C -#define RTCNT 0xFF800020 -#define RTCOR 0xFF800024 -#define RFCR 0xFF800028 -#define PCTRA 0xFF80002C -#define PDTRA 0xFF800030 -#define PCTRB 0xFF800040 -#define PDTRB 0xFF800044 -#define GPIOIC 0xFF800048 -#define SAR0 0xFFA00000 -#define DAR0 0xFFA00004 -#define DMATCR0 0xFFA00008 -#define CHCR0 0xFFA0000C -#define SAR1 0xFFA00010 -#define DAR1 0xFFA00014 -#define DMATCR1 0xFFA00018 -#define CHCR1 0xFFA0001C -#define SAR2 0xFFA00020 -#define DAR2 0xFFA00024 -#define DMATCR2 0xFFA00028 -#define CHCR2 0xFFA0002C -#define SAR3 0xFFA00030 -#define DAR3 0xFFA00034 -#define DMATCR3 0xFFA00038 -#define CHCR3 0xFFA0003C -#define DMAOR 0xFFA00040 -#define SAR4 0xFFA00050 -#define DAR4 0xFFA00054 -#define DMATCR4 0xFFA00058 +#define BCR2 0xFF800004 +#define BCR3 0xFF800050 +#define BCR4 0xFE0A00F0 +#define WCR1 0xFF800008 +#define WCR2 0xFF80000C +#define WCR3 0xFF800010 +#define MCR 0xFF800014 +#define PCR 0xFF800018 +#define RTCSR 0xFF80001C +#define RTCNT 0xFF800020 +#define RTCOR 0xFF800024 +#define RFCR 0xFF800028 +#define PCTRA 0xFF80002C +#define PDTRA 0xFF800030 +#define PCTRB 0xFF800040 +#define PDTRB 0xFF800044 +#define GPIOIC 0xFF800048 + +/* DMAC */ +#define SAR0 0xFFA00000 +#define DAR0 0xFFA00004 +#define DMATCR0 0xFFA00008 +#define CHCR0 0xFFA0000C +#define SAR1 0xFFA00010 +#define DAR1 0xFFA00014 +#define DMATCR1 0xFFA00018 +#define CHCR1 0xFFA0001C +#define SAR2 0xFFA00020 +#define DAR2 0xFFA00024 +#define DMATCR2 0xFFA00028 +#define CHCR2 0xFFA0002C +#define SAR3 0xFFA00030 +#define DAR3 0xFFA00034 +#define DMATCR3 0xFFA00038 +#define CHCR3 0xFFA0003C +#define DMAOR 0xFFA00040 +#define SAR4 0xFFA00050 +#define DAR4 0xFFA00054 +#define DMATCR4 0xFFA00058 + +/* CPG */ +#define FRQCR 0xFFC00000 +#define STBCR 0xFFC00004 +#define WTCNT 0xFFC00008 +#define WTCSR 0xFFC0000C +#define STBCR2 0xFFC00010 + +/* RTC */ +#define R64CNT 0xFFC80000 +#define RSECCNT 0xFFC80004 +#define RMINCNT 0xFFC80008 +#define RHRCNT 0xFFC8000C +#define RWKCNT 0xFFC80010 +#define RDAYCNT 0xFFC80014 +#define RMONCNT 0xFFC80018 +#define RYRCNT 0xFFC8001C +#define RSECAR 0xFFC80020 +#define RMINAR 0xFFC80024 +#define RHRAR 0xFFC80028 +#define RWKAR 0xFFC8002C +#define RDAYAR 0xFFC80030 +#define RMONAR 0xFFC80034 +#define RCR1 0xFFC80038 +#define RCR2 0xFFC8003C +#define RCR3 0xFFC80050 +#define RYRAR 0xFFC80054 -#define FRQCR 0xFFC00000 -#define STBCR 0xFFC00004 -#define WTCNT 0xFFC00008 -#define WTCSR 0xFFC0000C -#define STBCR2 0xFFC00010 -#define R64CNT 0xFFC80000 -#define RSECCNT 0xFFC80004 -#define RMINCNT 0xFFC80008 -#define RHRCNT 0xFFC8000C -#define RWKCNT 0xFFC80010 -#define RDAYCNT 0xFFC80014 -#define RMONCNT 0xFFC80018 -#define RYRCNT 0xFFC8001C -#define RSECAR 0xFFC80020 -#define RMINAR 0xFFC80024 -#define RHRAR 0xFFC80028 -#define RWKAR 0xFFC8002C -#define RDAYAR 0xFFC80030 -#define RMONAR 0xFFC80034 -#define RCR1 0xFFC80038 -#define RCR2 0xFFC8003C -#define RCR3 0xFFC80050 -#define RYRAR 0xFFC80054 -#define ICR 0xFFD00000 -#define IPRA 0xFFD00004 -#define IPRB 0xFFD00008 -#define IPRC 0xFFD0000C -#define IPRD 0xFFD00010 -#define INTPRI 0xFE080000 -#define INTREQ 0xFE080020 -#define INTMSK 0xFE080040 -#define INTMSKCL 0xFE080060 +/* ICR */ +#define ICR 0xFFD00000 +#define IPRA 0xFFD00004 +#define IPRB 0xFFD00008 +#define IPRC 0xFFD0000C +#define IPRD 0xFFD00010 +#define INTPRI 0xFE080000 +#define INTREQ 0xFE080020 +#define INTMSK 0xFE080040 +#define INTMSKCL 0xFE080060 + +/* CPG */ #define CLKSTP 0xFE0A0000 #define CLKSTPCLR 0xFE0A0008 -#define TSTR2 0xFE100004 -#define TCOR3 0xFE100008 -#define TCNT3 0xFE10000C -#define TCR3 0xFE100010 -#define TCOR4 0xFE100014 -#define TCNT4 0xFE100018 -#define TCR4 0xFE10001C -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 + +/* TMU */ +#define TSTR2 0xFE100004 +#define TCOR3 0xFE100008 +#define TCNT3 0xFE10000C +#define TCR3 0xFE100010 +#define TCOR4 0xFE100014 +#define TCNT4 0xFE100018 +#define TCR4 0xFE10001C +#define TOCR 0xFFD80000 +#define TSTR0 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 #define TCPR2 0xFFD8002C -#define SCSMR1 0xFFE00000 -#define SCBRR1 0xFFE00004 -#define SCSCR1 0xFFE00008 -#define SCTDR1 0xFFE0000C -#define SCSSR1 0xFFE00010 -#define SCRDR1 0xFFE00014 -#define SCSCMR1 0xFFE00018 -#define SCSPTR1 0xFFE0001C +#define TSTR TSTR0 + +/* SCI */ +#define SCSMR1 0xFFE00000 +#define SCBRR1 0xFFE00004 +#define SCSCR1 0xFFE00008 +#define SCTDR1 0xFFE0000C +#define SCSSR1 0xFFE00010 +#define SCRDR1 0xFFE00014 +#define SCSCMR1 0xFFE00018 +#define SCSPTR1 0xFFE0001C #define SCF0_BASE SCSMR1 + +/* SCIF */ #define SCSMR2 0xFFE80000 -#define SCBRR2 0xFFE80004 -#define SCSCR2 0xFFE80008 -#define SCFTDR2 0xFFE8000C -#define SCFSR2 0xFFE80010 -#define SCFRDR2 0xFFE80014 -#define SCFCR2 0xFFE80018 -#define SCFDR2 0xFFE8001C -#define SCSPTR2 0xFFE80020 -#define SCLSR2 0xFFE80024 +#define SCBRR2 0xFFE80004 +#define SCSCR2 0xFFE80008 +#define SCFTDR2 0xFFE8000C +#define SCFSR2 0xFFE80010 +#define SCFRDR2 0xFFE80014 +#define SCFCR2 0xFFE80018 +#define SCFDR2 0xFFE8001C +#define SCSPTR2 0xFFE80020 +#define SCLSR2 0xFFE80024 #define SCIF1_BASE SCSMR2 -#define SDIR 0xFFF00000 -#define SDDR 0xFFF00008 -#define SDINT 0xFFF00014 -#endif /* _ASM_CPU_SH7750_H_ */ +/* H-UDI */ +#define SDIR 0xFFF00000 +#define SDDR 0xFFF00008 +#define SDINT 0xFFF00014 +#endif /* _ASM_CPU_SH7750_H_ */ diff --git a/include/asm-sh/errno.h b/include/asm-sh/errno.h new file mode 100644 index 0000000..0d2c618 --- /dev/null +++ b/include/asm-sh/errno.h @@ -0,0 +1,156 @@ +/* + * U-boot - errno.h Error number defines + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _BLACKFIN_ERRNO_H +#define _BLACKFIN_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#endif diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index 70e60b1..03427ad 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -91,23 +91,21 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen); * * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. */ -#ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) -#endif +#define outb(v,p) __raw_writeb(v, p) +#define outw(v,p) __raw_writew(cpu_to_le16(v),p) +#define outl(v,p) __raw_writel(cpu_to_le32(v),p) + +#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) +#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) +#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) + +#define outsb(p,d,l) __raw_writesb(p,d,l) +#define outsw(p,d,l) __raw_writesw(p,d,l) +#define outsl(p,d,l) __raw_writesl(p,d,l) + +#define insb(p,d,l) __raw_readsb(p,d,l) +#define insw(p,d,l) __raw_readsw(p,d,l) +#define insl(p,d,l) __raw_readsl(p,d,l) #define outb_p(val,port) outb((val),(port)) #define outw_p(val,port) outw((val),(port)) @@ -174,8 +172,6 @@ extern void _memcpy_fromio(void *, unsigned long, size_t); extern void _memcpy_toio(unsigned long, const void *, size_t); extern void _memset_io(unsigned long, int, size_t); -extern void __readwrite_bug(const char *fn); - /* * If this architecture has PCI memory IO, then define the read/write * macros. These should only be used with the cookie passed from @@ -217,76 +213,19 @@ out: #elif !defined(readb) -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") +#define readb(addr) __raw_readb(addr) +#define readw(addr) __raw_readw(addr) +#define readl(addr) __raw_readl(addr) +#define writeb(v,addr) __raw_writeb(v, addr) +#define writew(v,addr) __raw_writew(v, addr) +#define writel(v,addr) __raw_writel(v, addr) #define check_signature(io,sig,len) (0) #endif /* __mem_pci */ -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) -#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) -#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_isa(b),(c),(d)) - -static inline int -isa_check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) -#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") -#define isa_writew(val,addr) __readwrite_bug("isa_writew") -#define isa_writel(val,addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io,sig,len) (0) - static inline void sync(void) { } - -#endif /* __mem_isa */ #endif /* __KERNEL__ */ #endif /* __ASM_SH_IO_H */ diff --git a/include/asm-sh/irqflags.h b/include/asm-sh/irqflags.h new file mode 100644 index 0000000..830e548 --- /dev/null +++ b/include/asm-sh/irqflags.h @@ -0,0 +1,126 @@ +#ifndef __ASM_SH_IRQFLAGS_H +#define __ASM_SH_IRQFLAGS_H + +static inline void raw_local_irq_enable(void) +{ + unsigned long __dummy0, __dummy1; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "and %1, %0\n\t" +#ifdef CONFIG_CPU_HAS_SR_RB + "stc r6_bank, %1\n\t" + "or %1, %0\n\t" +#endif + "ldc %0, sr\n\t" + : "=&r" (__dummy0), "=r" (__dummy1) + : "1" (~0x000000f0) + : "memory" + ); +} + +static inline void raw_local_irq_disable(void) +{ + unsigned long flags; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "or #0xf0, %0\n\t" + "ldc %0, sr\n\t" + : "=&z" (flags) + : /* no inputs */ + : "memory" + ); +} + +static inline void set_bl_bit(void) +{ + unsigned long __dummy0, __dummy1; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "or %2, %0\n\t" + "and %3, %0\n\t" + "ldc %0, sr\n\t" + : "=&r" (__dummy0), "=r" (__dummy1) + : "r" (0x10000000), "r" (0xffffff0f) + : "memory" + ); +} + +static inline void clear_bl_bit(void) +{ + unsigned long __dummy0, __dummy1; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "and %2, %0\n\t" + "ldc %0, sr\n\t" + : "=&r" (__dummy0), "=r" (__dummy1) + : "1" (~0x10000000) + : "memory" + ); +} + +static inline unsigned long __raw_local_save_flags(void) +{ + unsigned long flags; + + __asm__ __volatile__ ( + "stc sr, %0\n\t" + "and #0xf0, %0\n\t" + : "=&z" (flags) + : /* no inputs */ + : "memory" + ); + + return flags; +} + +#define raw_local_save_flags(flags) \ + do { (flags) = __raw_local_save_flags(); } while (0) + +static inline int raw_irqs_disabled_flags(unsigned long flags) +{ + return (flags != 0); +} + +static inline int raw_irqs_disabled(void) +{ + unsigned long flags = __raw_local_save_flags(); + + return raw_irqs_disabled_flags(flags); +} + +static inline unsigned long __raw_local_irq_save(void) +{ + unsigned long flags, __dummy; + + __asm__ __volatile__ ( + "stc sr, %1\n\t" + "mov %1, %0\n\t" + "or #0xf0, %0\n\t" + "ldc %0, sr\n\t" + "mov %1, %0\n\t" + "and #0xf0, %0\n\t" + : "=&z" (flags), "=&r" (__dummy) + : /* no inputs */ + : "memory" + ); + + return flags; +} + +#define raw_local_irq_save(flags) \ + do { (flags) = __raw_local_irq_save(); } while (0) + +#define local_irq_save raw_local_irq_save + +static inline void raw_local_irq_restore(unsigned long flags) +{ + if ((flags & 0xf0) != 0xf0) + raw_local_irq_enable(); +} +#define local_irq_restore raw_local_irq_restore + +#endif /* __ASM_SH_IRQFLAGS_H */ diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h index a78ef81..27d981b 100644 --- a/include/asm-sh/string.h +++ b/include/asm-sh/string.h @@ -8,6 +8,8 @@ * from linux kernel code. */ +#ifdef __KERNEL__ /* only set these up for kernel code */ + #define __HAVE_ARCH_STRCPY static inline char *strcpy(char *__dest, const char *__src) { @@ -129,4 +131,32 @@ extern size_t strlen(const char *); /* arch/sh/lib/strcasecmp.c */ extern int strcasecmp(const char *, const char *); +#else /* KERNEL */ + +/* + * let user libraries deal with these, + * IMHO the kernel has no place defining these functions for user apps + */ + +#define __HAVE_ARCH_STRCPY 1 +#define __HAVE_ARCH_STRNCPY 1 +#define __HAVE_ARCH_STRCAT 1 +#define __HAVE_ARCH_STRNCAT 1 +#define __HAVE_ARCH_STRCMP 1 +#define __HAVE_ARCH_STRNCMP 1 +#define __HAVE_ARCH_STRNICMP 1 +#define __HAVE_ARCH_STRCHR 1 +#define __HAVE_ARCH_STRRCHR 1 +#define __HAVE_ARCH_STRSTR 1 +#define __HAVE_ARCH_STRLEN 1 +#define __HAVE_ARCH_STRNLEN 1 +#define __HAVE_ARCH_MEMSET 1 +#define __HAVE_ARCH_MEMCPY 1 +#define __HAVE_ARCH_MEMMOVE 1 +#define __HAVE_ARCH_MEMSCAN 1 +#define __HAVE_ARCH_MEMCMP 1 +#define __HAVE_ARCH_MEMCHR 1 +#define __HAVE_ARCH_STRTOK 1 + +#endif /* KERNEL */ #endif /* __ASM_SH_STRING_H */ -- cgit v1.1 From 516ad760db3553766267ada01b7d5d727faa4bbd Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 23 Sep 2007 02:17:08 +0900 Subject: sh: Remove comment out code from include/asm-sh/cpu_sh4.h Signed-off-by: Nobuhiro Iwamatsu --- include/asm-sh/cpu_sh4.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'include') diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h index dca61ca..2658039 100644 --- a/include/asm-sh/cpu_sh4.h +++ b/include/asm-sh/cpu_sh4.h @@ -29,18 +29,11 @@ #define CACHE_OC_WAY_SHIFT 14 #define CACHE_OC_NUM_ENTRIES 512 #define CACHE_OC_ENTRY_SHIFT 5 -//#define CACHE_OC_NUM_WAYS 1 #if defined (CONFIG_CPU_SH7750) #include -//#ifdef CONFIG_CPU_TYPE_R -//#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ -//#else -//#define CCR_CACHE_INIT 0x0000090b -//#endif #elif defined (CONFIG_CPU_SH7722) #include -//#define CCR_CACHE_INIT 0x0000090d #else #error "Unknown SH4 variant" #endif -- cgit v1.1 From 047375bfa4c3052fa50a748da7ff89e9dad3b364 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 23 Sep 2007 02:19:24 +0900 Subject: sh: Update MS7750SE01 platform Signed-off-by: Nobuhiro Iwamatsu --- include/configs/ms7750se.h | 79 ++++++++++++++++++++++++++++++++-------------- 1 file changed, 56 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index 0467a5e..7925f20 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -1,50 +1,89 @@ -#ifndef __CONFIG_H -#define __CONFIG_H +/* + * Configuation settings for the Hitachi Solution Engine 7750 + * + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MS7750SE_H +#define __MS7750SE_H #undef DEBUG - #define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_CPU_SH7750 1 +/* #define CONFIG_CPU_SH7751 1 */ +/* #define CONFIG_CPU_TYPE_R 1 */ #define CONFIG_MS7750SE 1 #define __LITTLE_ENDIAN__ 1 -//#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NET |CFG_CMD_PING) -#define CONFIG_COMMANDS CONFIG_CMD_DFL & ~CFG_CMD_NET +/* + * Command line configuration. + */ +//#include + +#define CONFIG_CMD_DFL +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_ENV #define CFG_SCIF_CONSOLE 1 #define CONFIG_BAUDRATE 38400 #define CONFIG_CONS_SCIF1 1 #define BOARD_LATE_INIT 1 -#include - #define CONFIG_BOOTDELAY -1 -#define CONFIG_BOOTARGS "console=ttySC0,115200" +#define CONFIG_BOOTARGS "console=ttySC0,38400" #define CONFIG_ENV_OVERWRITE 1 +/* SDRAM */ #define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_SIZE (64 * 1024 * 1024) #define CFG_LONGHELP -#define CFG_PROMPT "=> " -#define CFG_CBSIZE 256 -#define CFG_PBSIZE 256 +#define CFG_PROMPT "=> " +#define CFG_CBSIZE 256 +#define CFG_PBSIZE 256 #define CFG_MAXARGS 16 -#define CFG_BARGSIZE 512 -#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } /* List of legal baudrate settings for this board */ +#define CFG_BARGSIZE 512 +/* List of legal baudrate settings for this board */ +#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } #define CFG_MEMTEST_START (CFG_SDRAM_BASE) #define CFG_MEMTEST_END (TEXT_BASE - 0x100000) +/* NOR Flash */ +/* #define CFG_FLASH_BASE (0xA1000000)*/ +#define CFG_FLASH_BASE (0xA0000000) +#define CFG_MAX_FLASH_BANKS (1) /* Max number of + * Flash memory banks + */ +#define CFG_MAX_FLASH_SECT 142 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) #define CFG_MONITOR_BASE (CFG_FLASH_BASE) /* Address of u-boot image in Flash */ -#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MONITOR_LEN (128 * 1024) #define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ -#define CFG_BOOTMAPSZ (8 * 1024 * 1024) +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) #define CFG_RX_ETH_BUFFER (8) #define CFG_FLASH_CFI @@ -53,12 +92,6 @@ #undef CFG_FLASH_QUIET_TEST #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_BASE (0xA1000000) -#define CFG_MAX_FLASH_BANKS (1) /* Max number of - * Flash memory banks - */ -#define CFG_MAX_FLASH_SECT 142 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_ENV_IS_IN_FLASH #define CFG_ENV_SECT_SIZE 0x20000 @@ -67,9 +100,9 @@ #define CFG_FLASH_ERASE_TOUT 120000 #define CFG_FLASH_WRITE_TOUT 500 +/* Board Clock */ #define CONFIG_SYS_CLK_FREQ 33333333 #define TMU_CLK_DIVIDER 4 #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) -#define CFG_PLL_SETTLING_TIME 100 /* in us */ -#endif /* __CONFIG_H */ +#endif /* __MS7750SE_H */ -- cgit v1.1 From 6c0bbdccd379f5c8702af9e0765294c2fb7472a6 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 23 Sep 2007 02:31:13 +0900 Subject: sh: Add support Renesas sh7722 processor and Hitachi MS7722SE01 board Signed-off-by: Nobuhiro Iwamatsu --- include/asm-sh/cpu_sh7722.h | 1337 +++++++++++++++++++++++++++++++++++++++++++ include/configs/ms7722se.h | 137 +++++ 2 files changed, 1474 insertions(+) create mode 100644 include/asm-sh/cpu_sh7722.h create mode 100644 include/configs/ms7722se.h (limited to 'include') diff --git a/include/asm-sh/cpu_sh7722.h b/include/asm-sh/cpu_sh7722.h new file mode 100644 index 0000000..fb63c6e --- /dev/null +++ b/include/asm-sh/cpu_sh7722.h @@ -0,0 +1,1337 @@ +/* + * (C) Copyright 2007 Nobuhiro Iwamatsu + * + * SH7722 Internal I/O register + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH7722_H_ +#define _ASM_CPU_SH7722_H_ + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000090d + +/* EXP */ +#define TRA 0xFF000020 +#define EXPEVT 0xFF000024 +#define INTEVT 0xFF000028 + +/* MMU */ +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define PASCR 0xFF000070 +#define IRMCR 0xFF000078 + +/* CACHE */ +#define CCR 0xFF00001C +#define RAMCR 0xFF000074 + +/* XY MEMORY */ +#define XSA 0xFF000050 +#define YSA 0xFF000054 +#define XDA 0xFF000058 +#define YDA 0xFF00005C +#define XPR 0xFF000060 +#define YPR 0xFF000064 +#define XEA 0xFF000068 +#define YEA 0xFF00006C + +/* INTC */ +#define ICR0 0xA4140000 +#define ICR1 0xA414001C +#define INTPRI0 0xA4140010 +#define INTREQ0 0xA4140024 +#define INTMSK0 0xA4140044 +#define INTMSKCLR0 0xA4140064 +#define NMIFCR 0xA41400C0 +#define USERIMASK 0xA4700000 +#define IPRA 0xA4080000 +#define IPRB 0xA4080004 +#define IPRC 0xA4080008 +#define IPRD 0xA408000C +#define IPRE 0xA4080010 +#define IPRF 0xA4080014 +#define IPRG 0xA4080018 +#define IPRH 0xA408001C +#define IPRI 0xA4080020 +#define IPRJ 0xA4080024 +#define IPRK 0xA4080028 +#define IPRL 0xA408002C +#define IMR0 0xA4080080 +#define IMR1 0xA4080084 +#define IMR2 0xA4080088 +#define IMR3 0xA408008C +#define IMR4 0xA4080090 +#define IMR5 0xA4080094 +#define IMR6 0xA4080098 +#define IMR7 0xA408009C +#define IMR8 0xA40800A0 +#define IMR9 0xA40800A4 +#define IMR10 0xA40800A8 +#define IMR11 0xA40800AC +#define IMCR0 0xA40800C0 +#define IMCR1 0xA40800C4 +#define IMCR2 0xA40800C8 +#define IMCR3 0xA40800CC +#define IMCR4 0xA40800D0 +#define IMCR5 0xA40800D4 +#define IMCR6 0xA40800D8 +#define IMCR7 0xA40800DC +#define IMCR8 0xA40800E0 +#define IMCR9 0xA40800E4 +#define IMCR10 0xA40800E8 +#define IMCR11 0xA40800EC +#define MFI_IPRA 0xA40B0000 +#define MFI_IPRB 0xA40B0004 +#define MFI_IPRC 0xA40B0008 +#define MFI_IPRD 0xA40B000C +#define MFI_IPRE 0xA40B0010 +#define MFI_IPRF 0xA40B0014 +#define MFI_IPRG 0xA40B0018 +#define MFI_IPRH 0xA40B001C +#define MFI_IPRI 0xA40B0020 +#define MFI_IPRJ 0xA40B0024 +#define MFI_IPRK 0xA40B0028 +#define MFI_IPRL 0xA40B002C +#define MFI_IMR0 0xA40B0080 +#define MFI_IMR1 0xA40B0084 +#define MFI_IMR2 0xA40B0088 +#define MFI_IMR3 0xA40B008C +#define MFI_IMR4 0xA40B0090 +#define MFI_IMR5 0xA40B0094 +#define MFI_IMR6 0xA40B0098 +#define MFI_IMR7 0xA40B009C +#define MFI_IMR8 0xA40B00A0 +#define MFI_IMR9 0xA40B00A4 +#define MFI_IMR10 0xA40B00A8 +#define MFI_IMR11 0xA40B00AC +#define MFI_IMCR0 0xA40B00C0 +#define MFI_IMCR1 0xA40B00C4 +#define MFI_IMCR2 0xA40B00C8 +#define MFI_IMCR3 0xA40B00CC +#define MFI_IMCR4 0xA40B00D0 +#define MFI_IMCR5 0xA40B00D4 +#define MFI_IMCR6 0xA40B00D8 +#define MFI_IMCR7 0xA40B00DC +#define MFI_IMCR8 0xA40B00E0 +#define MFI_IMCR9 0xA40B00E4 +#define MFI_IMCR10 0xA40B00E8 +#define MFI_IMCR11 0xA40B00EC + +/* BSC */ +#define CMNCR 0xFEC10000 +#define CS0BCR 0xFEC10004 +#define CS2BCR 0xFEC10008 +#define CS4BCR 0xFEC10010 +#define CS5ABCR 0xFEC10014 +#define CS5BBCR 0xFEC10018 +#define CS6ABCR 0xFEC1001C +#define CS6BBCR 0xFEC10020 +#define CS0WCR 0xFEC10024 +#define CS2WCR 0xFEC10028 +#define CS4WCR 0xFEC10030 +#define CS5AWCR 0xFEC10034 +#define CS5BWCR 0xFEC10038 +#define CS6AWCR 0xFEC1003C +#define CS6BWCR 0xFEC10040 +#define RBWTCNT 0xFEC10054 + +/* SBSC */ +#define SBSC_SDCR 0xFE400008 +#define SBSC_SDWCR 0xFE40000C +#define SBSC_SDPCR 0xFE400010 +#define SBSC_RTCSR 0xFE400014 +#define SBSC_RTCNT 0xFE400018 +#define SBSC_RTCOR 0xFE40001C +#define SBSC_RFCR 0xFE400020 + +/* DMAC */ +#define SAR_0 0xFE008020 +#define DAR_0 0xFE008024 +#define TCR_0 0xFE008028 +#define CHCR_0 0xFE00802C +#define SAR_1 0xFE008030 +#define DAR_1 0xFE008034 +#define TCR_1 0xFE008038 +#define CHCR_1 0xFE00803C +#define SAR_2 0xFE008040 +#define DAR_2 0xFE008044 +#define TCR_2 0xFE008048 +#define CHCR_2 0xFE00804C +#define SAR_3 0xFE008050 +#define DAR_3 0xFE008054 +#define TCR_3 0xFE008058 +#define CHCR_3 0xFE00805C +#define SAR_4 0xFE008070 +#define DAR_4 0xFE008074 +#define TCR_4 0xFE008078 +#define CHCR_4 0xFE00807C +#define SAR_5 0xFE008080 +#define DAR_5 0xFE008084 +#define TCR_5 0xFE008088 +#define CHCR_5 0xFE00808C +#define SARB_0 0xFE008120 +#define DARB_0 0xFE008124 +#define TCRB_0 0xFE008128 +#define SARB_1 0xFE008130 +#define DARB_1 0xFE008134 +#define TCRB_1 0xFE008138 +#define SARB_2 0xFE008140 +#define DARB_2 0xFE008144 +#define TCRB_2 0xFE008148 +#define SARB_3 0xFE008150 +#define DARB_3 0xFE008154 +#define TCRB_3 0xFE008158 +#define DMAOR 0xFE008060 +#define DMARS_0 0xFE009000 +#define DMARS_1 0xFE009004 +#define DMARS_2 0xFE009008 + +/* CPG */ +#define FRQCR 0xA4150000 +#define VCLKCR 0xA4150004 +#define SCLKACR 0xA4150008 +#define SCLKBCR 0xA415000C +#define PLLCR 0xA4150024 +#define DLLFRQ 0xA4150050 + +/* LOW POWER MODE */ +#define STBCR 0xA4150020 +#define MSTPCR0 0xA4150030 +#define MSTPCR1 0xA4150034 +#define MSTPCR2 0xA4150038 +#define BAR 0xA4150040 + +/* RWDT */ +#define RWTCNT 0xA4520000 +#define RWTCSR 0xA4520004 +#define WTCNT RWTCNT + + +/* TMU */ +#define TSTR 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 + +/* TPU */ +#define TPU_TSTR 0xA4C90000 +#define TPU_TCR0 0xA4C90010 +#define TPU_TMDR0 0xA4C90014 +#define TPU_TIOR0 0xA4C90018 +#define TPU_TIER0 0xA4C9001C +#define TPU_TSR0 0xA4C90020 +#define TPU_TCNT0 0xA4C90024 +#define TPU_TGR0A 0xA4C90028 +#define TPU_TGR0B 0xA4C9002C +#define TPU_TGR0C 0xA4C90030 +#define TPU_TGR0D 0xA4C90034 +#define TPU_TCR1 0xA4C90050 +#define TPU_TMDR1 0xA4C90054 +#define TPU_TIER1 0xA4C9005C +#define TPU_TSR1 0xA4C90060 +#define TPU_TCNT1 0xA4C90064 +#define TPU_TGR1A 0xA4C90068 +#define TPU_TGR1B 0xA4C9006C +#define TPU_TGR1C 0xA4C90070 +#define TPU_TGR1D 0xA4C90074 +#define TPU_TCR2 0xA4C90090 +#define TPU_TMDR2 0xA4C90094 +#define TPU_TIER2 0xA4C9009C +#define TPU_TSR2 0xA4C900A0 +#define TPU_TCNT2 0xA4C900A4 +#define TPU_TGR2A 0xA4C900A8 +#define TPU_TGR2B 0xA4C900AC +#define TPU_TGR2C 0xA4C900B0 +#define TPU_TGR2D 0xA4C900B4 +#define TPU_TCR3 0xA4C900D0 +#define TPU_TMDR3 0xA4C900D4 +#define TPU_TIER3 0xA4C900DC +#define TPU_TSR3 0xA4C900E0 +#define TPU_TCNT3 0xA4C900E4 +#define TPU_TGR3A 0xA4C900E8 +#define TPU_TGR3B 0xA4C900EC +#define TPU_TGR3C 0xA4C900F0 +#define TPU_TGR3D 0xA4C900F4 + +/* CMT */ +#define CMSTR 0xA44A0000 +#define CMCSR 0xA44A0060 +#define CMCNT 0xA44A0064 +#define CMCOR 0xA44A0068 + +/* SIO */ +#define SIOMDR 0xA4500000 +#define SIOCTR 0xA4500004 +#define SIOSTBCR0 0xA4500008 +#define SIOSTBCR1 0xA450000C +#define SIOTDR 0xA4500014 +#define SIORDR 0xA4500018 +#define SIOSTR 0xA450001C +#define SIOIER 0xA4500020 +#define SIOSCR 0xA4500024 + +/* SIOF */ +#define SIMDR0 0xA4410000 +#define SISCR0 0xA4410002 +#define SITDAR0 0xA4410004 +#define SIRDAR0 0xA4410006 +#define SICDAR0 0xA4410008 +#define SICTR0 0xA441000C +#define SIFCTR0 0xA4410010 +#define SISTR0 0xA4410014 +#define SIIER0 0xA4410016 +#define SITDR0 0xA4410020 +#define SIRDR0 0xA4410024 +#define SITCR0 0xA4410028 +#define SIRCR0 0xA441002C +#define SPICR0 0xA4410030 +#define SIMDR1 0xA4420000 +#define SISCR1 0xA4420002 +#define SITDAR1 0xA4420004 +#define SIRDAR1 0xA4420006 +#define SICDAR1 0xA4420008 +#define SICTR1 0xA442000C +#define SIFCTR1 0xA4420010 +#define SISTR1 0xA4420014 +#define SIIER1 0xA4420016 +#define SITDR1 0xA4420020 +#define SIRDR1 0xA4420024 +#define SITCR1 0xA4420028 +#define SIRCR1 0xA442002C +#define SPICR1 0xA4420030 + +/* SCIF */ +/* +#define SCSMR 0xFFE00000 +#define SCBRR 0xFFE00004 +#define SCSCR 0xFFE00008 +#define SCFTDR 0xFFE0000C +#define SCFSR 0xFFE00010 +#define SCFRDR 0xFFE00014 +#define SCFCR 0xFFE00018 +#define SCFDR 0xFFE0001C +#define SCLSR 0xFFE00024 +#define SCSMR1 0xFFE10000 +#define SCBRR1 0xFFE10004 +#define SCSCR1 0xFFE10008 +#define SCFTDR1 0xFFE1000C +#define SCFSR1 0xFFE10010 +#define SCFRDR1 0xFFE10014 +#define SCFCR1 0xFFE10018 +#define SCFDR1 0xFFE1001C +#define SCLSR1 0xFFE10024 +#define SCSMR2 0xFFE20000 +#define SCBRR2 0xFFE20004 +#define SCSCR2 0xFFE20008 +#define SCFTDR2 0xFFE2000C +#define SCFSR2 0xFFE20010 +#define SCFRDR2 0xFFE20014 +#define SCFCR2 0xFFE20018 +#define SCFDR2 0xFFE2001C +#define SCLSR2 0xFFE20024 +#define SCSMR3 0xFFE30000 +#define SCBRR3 0xFFE30004 +#define SCSCR3 0xFFE30008 +#define SCFTDR3 0xFFE3000C +#define SCFSR3 0xFFE30010 +#define SCFRDR3 0xFFE30014 +#define SCFCR3 0xFFE30018 +#define SCFDR3 0xFFE3001C +#define SCLSR3 0xFFE30024 +*/ +#define SCIF0_BASE 0xFFE00000 + +/* SIM */ +#define SIM_SCSMR 0xA4490000 +#define SIM_SCBRR 0xA4490002 +#define SIM_SCSCR 0xA4490004 +#define SIM_SCTDR 0xA4490006 +#define SIM_SCSSR 0xA4490008 +#define SIM_SCRDR 0xA449000A +#define SIM_SCSCMR 0xA449000C +#define SIM_SCSC2R 0xA449000E +#define SIM_SCWAIT 0xA4490010 +#define SIM_SCGRD 0xA4490012 +#define SIM_SCSMPL 0xA4490014 +#define SIM_SCDMAEN 0xA4490016 + +/* IrDA */ +#define IRIF_INIT1 0xA45D0012 +#define IRIF_INIT2 0xA45D0014 +#define IRIF_RINTCLR 0xA45D0016 +#define IRIF_TINTCLR 0xA45D0018 +#define IRIF_SIR0 0xA45D0020 +#define IRIF_SIR1 0xA45D0022 +#define IRIF_SIR2 0xA45D0024 +#define IRIF_SIR3 0xA45D0026 +#define IRIF_SIR_FRM 0xA45D0028 +#define IRIF_SIR_EOF 0xA45D002A +#define IRIF_SIR_FLG 0xA45D002C +#define IRIF_SIR_STS2 0xA45D002E +#define IRIF_UART0 0xA45D0030 +#define IRIF_UART1 0xA45D0032 +#define IRIF_UART2 0xA45D0034 +#define IRIF_UART3 0xA45D0036 +#define IRIF_UART4 0xA45D0038 +#define IRIF_UART5 0xA45D003A +#define IRIF_UART6 0xA45D003C +#define IRIF_UART7 0xA45D003E +#define IRIF_CRC0 0xA45D0040 +#define IRIF_CRC1 0xA45D0042 +#define IRIF_CRC2 0xA45D0044 +#define IRIF_CRC3 0xA45D0046 +#define IRIF_CRC4 0xA45D0048 + +/* IIC */ +#define ICDR0 0xA4470000 +#define ICCR0 0xA4470004 +#define ICSR0 0xA4470008 +#define ICIC0 0xA447000C +#define ICCL0 0xA4470010 +#define ICCH0 0xA4470014 +#define ICDR1 0xA4750000 +#define ICCR1 0xA4750004 +#define ICSR1 0xA4750008 +#define ICIC1 0xA475000C +#define ICCL1 0xA4750010 +#define ICCH1 0xA4750014 + +/* FLCTL */ +#define FLCMNCR 0xA4530000 +#define FLCMDCR 0xA4530004 +#define FLCMCDR 0xA4530008 +#define FLADR 0xA453000C +#define FLDATAR 0xA4530010 +#define FLDTCNTR 0xA4530014 +#define FLINTDMACR 0xA4530018 +#define FLBSYTMR 0xA453001C +#define FLBSYCNT 0xA4530020 +#define FLDTFIFO 0xA4530024 +#define FLECFIFO 0xA4530028 +#define FLTRCR 0xA453002C +#define FLADR2 0xA453003C + +/* MFI */ +#define MFIIDX 0xA4C10000 +#define MFIGSR 0xA4C10004 +#define MFISCR 0xA4C10008 +#define MFIMCR 0xA4C1000C +#define MFIIICR 0xA4C10010 +#define MFIEICR 0xA4C10014 +#define MFIADR 0xA4C10018 +#define MFIDATA 0xA4C1001C +#define MFIRCR 0xA4C10020 +#define MFIINTEVT 0xA4C1002C +#define MFIIMASK 0xA4C10030 +#define MFIBCR 0xA4C10040 +#define MFIADRW 0xA4C10044 +#define MFIADRR 0xA4C10048 +#define MFIDATAW 0xA4C1004C +#define MFIDATAR 0xA4C10050 +#define MFIMCRW 0xA4C10054 +#define MFIMCRR 0xA4C10058 +#define MFIDNRW 0xA4C1005C +#define MFIDNRR 0xA4C10060 +#define MFISIZEW 0xA4C10064 +#define MFISIZER 0xA4C10068 +#define MFIDEVCR 0xA4C10038 +#define MFISM4 0xA4C10080 + +/* VPU */ +#define VP4_CTRL 0xFE900000 +#define VP4_VOL_CTRL 0xFE900004 +#define VP4_IMAGE_SIZE 0xFE900008 +#define VP4_MB_NUM 0xFE90000C +#define VP4_DWY_ADDR 0xFE900010 +#define VP4_DWC_ADDR 0xFE900014 +#define VP4_D2WY_ADDR 0xFE900018 +#define VP4_D2WC_ADDR 0xFE90001C +#define VP4_DP1_ADDR 0xFE900020 +#define VP4_DP2_ADDR 0xFE900024 +#define VP4_STRS_ADDR 0xFE900028 +#define VP4_STRE_ADDR 0xFE90002C +#define VP4_VOP_CTRL 0xFE900030 +#define VP4_VOP_TIME 0xFE900034 +#define VP4_263_CTRL 0xFE900038 +#define VP4_264_CTRL 0xFE90003C +#define VP4_VLC_CTRL 0xFE900040 +#define VP4_ENDIAN 0xFE900044 +#define VP4_CMD 0xFE900048 +#define VP4_ME_TH1 0xFE90004C +#define VP4_ME_TH2 0xFE900050 +#define VP4_ME_COSTMB 0xFE900054 +#define VP4_ME_SKIP 0xFE900058 +#define VP4_ME_CTRL 0xFE90005C +#define VP4_MBRF_CTRL 0xFE900060 +#define VP4_MC_CTRL 0xFE900064 +#define VP4_PRED_CTRL 0xFE900068 +#define VP4_SLC_SIZE 0xFE90006C +#define VP4_VOP_MINBIT 0xFE900070 +#define VP4_MB_MAXBIT 0xFE900074 +#define VP4_MB_TBIT 0xFE900078 +#define VP4_RCQNT 0xFE90007C +#define VP4_RCRP 0xFE900080 +#define VP4_RCDJ 0xFE900084 +#define VP4_RCWQ 0xFE900088 +#define VP4_FWD_TIME 0xFE900094 +#define VP4_BWD_TIME 0xFE900098 +#define VP4_PST_TIME 0xFE90009C +#define VP4_ILTFRAME 0xFE9000A0 +#define VP4_EC_REF 0xFE9000A4 +#define VP4_STATUS 0xFE900100 +#define VP4_IRQ_ENB 0xFE900104 +#define VP4_IRQ_STA 0xFE900108 +#define VP4_VOP_BIT 0xFE90010C +#define VP4_PRV_BIT 0xFE900110 +#define VP4_SLC_MB 0xFE900114 +#define VP4_QSUM 0xFE900118 +#define VP4_DEC_ERR 0xFE90011C +#define VP4_ERR_AREA 0xFE900120 +#define VP4_NEXT_CODE 0xFE900124 +#define VP4_MB_ATTR 0xFE900128 +#define VP4_DBMON 0xFE90012C +#define VP4_DEBUG 0xFE900130 +#define VP4_ERR_DET 0xFE900134 +#define VP4_CLK_STOP 0xFE900138 +#define VP4_MB_SADA 0xFE90013C +#define VP4_MB_SADR 0xFE900140 +#define VP4_MAT_RAM 0xFE901000 +#define VP4_NC_RAM 0xFE902000 +#define WT 0xFE9020CC +#define VP4_CPY_ADDR 0xFE902264 +#define VP4_CPC_ADDR 0xFE902268 +#define VP4_R0Y_ADDR 0xFE90226C +#define VP4_R0C_ADDR 0xFE902270 +#define VP4_R1Y_ADDR 0xFE902274 +#define VP4_R1C_ADDR 0xFE902278 +#define VP4_R2Y_ADDR 0xFE90227C +#define VP4_R2C_ADDR 0xFE902280 +#define VP4_R3Y_ADDR 0xFE902284 +#define VP4_R3C_ADDR 0xFE902288 +#define VP4_R4Y_ADDR 0xFE90228C +#define VP4_R4C_ADDR 0xFE902290 +#define VP4_R5Y_ADDR 0xFE902294 +#define VP4_R5C_ADDR 0xFE902298 +#define VP4_R6Y_ADDR 0xFE90229C +#define VP4_R6C_ADDR 0xFE9022A0 +#define VP4_R7Y_ADDR 0xFE9022A4 +#define VP4_R7C_ADDR 0xFE9022A8 +#define VP4_R8Y_ADDR 0xFE9022AC +#define VP4_R8C_ADDR 0xFE9022B0 +#define VP4_R9Y_ADDR 0xFE9022B4 +#define VP4_R9C_ADDR 0xFE9022B8 +#define VP4_RAY_ADDR 0xFE9022BC +#define VP4_RAC_ADDR 0xFE9022C0 +#define VP4_RBY_ADDR 0xFE9022C4 +#define VP4_RBC_ADDR 0xFE9022C8 +#define VP4_RCY_ADDR 0xFE9022CC +#define VP4_RCC_ADDR 0xFE9022D0 +#define VP4_RDY_ADDR 0xFE9022D4 +#define VP4_RDC_ADDR 0xFE9022D8 +#define VP4_REY_ADDR 0xFE9022DC +#define VP4_REC_ADDR 0xFE9022E0 +#define VP4_RFY_ADDR 0xFE9022E4 +#define VP4_RFC_ADDR 0xFE9022E8 + +/* VIO(CEU) */ +#define CAPSR 0xFE910000 +#define CAPCR 0xFE910004 +#define CAMCR 0xFE910008 +#define CMCYR 0xFE91000C +#define CAMOR 0xFE910010 +#define CAPWR 0xFE910014 +#define CAIFR 0xFE910018 +#define CSTCR 0xFE910020 +#define CSECR 0xFE910024 +#define CRCNTR 0xFE910028 +#define CRCMPR 0xFE91002C +#define CFLCR 0xFE910030 +#define CFSZR 0xFE910034 +#define CDWDR 0xFE910038 +#define CDAYR 0xFE91003C +#define CDACR 0xFE910040 +#define CDBYR 0xFE910044 +#define CDBCR 0xFE910048 +#define CBDSR 0xFE91004C +#define CLFCR 0xFE910060 +#define CDOCR 0xFE910064 +#define CDDCR 0xFE910068 +#define CDDAR 0xFE91006C +#define CEIER 0xFE910070 +#define CETCR 0xFE910074 +#define CSTSR 0xFE91007C +#define CSRTR 0xFE910080 +#define CDAYR2 0xFE910090 +#define CDACR2 0xFE910094 +#define CDBYR2 0xFE910098 +#define CDBCR2 0xFE91009C + +/* VIO(VEU) */ +#define VESTR 0xFE920000 +#define VESWR 0xFE920010 +#define VESSR 0xFE920014 +#define VSAYR 0xFE920018 +#define VSACR 0xFE92001C +#define VBSSR 0xFE920020 +#define VEDWR 0xFE920030 +#define VDAYR 0xFE920034 +#define VDACR 0xFE920038 +#define VTRCR 0xFE920050 +#define VRFCR 0xFE920054 +#define VRFSR 0xFE920058 +#define VENHR 0xFE92005C +#define VFMCR 0xFE920070 +#define VVTCR 0xFE920074 +#define VHTCR 0xFE920078 +#define VAPCR 0xFE920080 +#define VECCR 0xFE920084 +#define VAFXR 0xFE920090 +#define VSWPR 0xFE920094 +#define VEIER 0xFE9200A0 +#define VEVTR 0xFE9200A4 +#define VSTAR 0xFE9200B0 +#define VBSRR 0xFE9200B4 + +/* VIO(BEU) */ +#define BESTR 0xFE930000 +#define BSMWR1 0xFE930010 +#define BSSZR1 0xFE930014 +#define BSAYR1 0xFE930018 +#define BSACR1 0xFE93001C +#define BSAAR1 0xFE930020 +#define BSIFR1 0xFE930024 +#define BSMWR2 0xFE930028 +#define BSSZR2 0xFE93002C +#define BSAYR2 0xFE930030 +#define BSACR2 0xFE930034 +#define BSAAR2 0xFE930038 +#define BSIFR2 0xFE93003C +#define BSMWR3 0xFE930040 +#define BSSZR3 0xFE930044 +#define BSAYR3 0xFE930048 +#define BSACR3 0xFE93004C +#define BSAAR3 0xFE930050 +#define BSIFR3 0xFE930054 +#define BTPSR 0xFE930058 +#define BMSMWR1 0xFE930070 +#define BMSSZR1 0xFE930074 +#define BMSAYR1 0xFE930078 +#define BMSACR1 0xFE93007C +#define BMSMWR2 0xFE930080 +#define BMSSZR2 0xFE930084 +#define BMSAYR2 0xFE930088 +#define BMSACR2 0xFE93008C +#define BMSMWR3 0xFE930090 +#define BMSSZR3 0xFE930094 +#define BMSAYR3 0xFE930098 +#define BMSACR3 0xFE93009C +#define BMSMWR4 0xFE9300A0 +#define BMSSZR4 0xFE9300A4 +#define BMSAYR4 0xFE9300A8 +#define BMSACR4 0xFE9300AC +#define BMSIFR 0xFE9300F0 +#define BBLCR0 0xFE930100 +#define BBLCR1 0xFE930104 +#define BPROCR 0xFE930108 +#define BMWCR0 0xFE93010C +#define BLOCR1 0xFE930114 +#define BLOCR2 0xFE930118 +#define BLOCR3 0xFE93011C +#define BMLOCR1 0xFE930120 +#define BMLOCR2 0xFE930124 +#define BMLOCR3 0xFE930128 +#define BMLOCR4 0xFE93012C +#define BMPCCR1 0xFE930130 +#define BMPCCR2 0xFE930134 +#define BPKFR 0xFE930140 +#define BPCCR0 0xFE930144 +#define BPCCR11 0xFE930148 +#define BPCCR12 0xFE93014C +#define BPCCR21 0xFE930150 +#define BPCCR22 0xFE930154 +#define BPCCR31 0xFE930158 +#define BPCCR32 0xFE93015C +#define BDMWR 0xFE930160 +#define BDAYR 0xFE930164 +#define BDACR 0xFE930168 +#define BAFXR 0xFE930180 +#define BSWPR 0xFE930184 +#define BEIER 0xFE930188 +#define BEVTR 0xFE93018C +#define BRCNTR 0xFE930194 +#define BSTAR 0xFE930198 +#define BBRSTR 0xFE93019C +#define BRCHR 0xFE9301A0 +#define CLUT 0xFE933000 + +/* JPU */ +#define JCMOD 0xFEA00000 +#define JCCMD 0xFEA00004 +#define JCSTS 0xFEA00008 +#define JCQTN 0xFEA0000C +#define JCHTN 0xFEA00010 +#define JCDRIU 0xFEA00014 +#define JCDRID 0xFEA00018 +#define JCVSZU 0xFEA0001C +#define JCVSZD 0xFEA00020 +#define JCHSZU 0xFEA00024 +#define JCHSZD 0xFEA00028 +#define JCDTCU 0xFEA0002C +#define JCDTCM 0xFEA00030 +#define JCDTCD 0xFEA00034 +#define JINTE 0xFEA00038 +#define JINTS 0xFEA0003C +#define JCDERR 0xFEA00040 +#define JCRST 0xFEA00044 +#define JIFCNT 0xFEA00060 +#define JIFECNT 0xFEA00070 +#define JIFESYA1 0xFEA00074 +#define JIFESCA1 0xFEA00078 +#define JIFESYA2 0xFEA0007C +#define JIFESCA2 0xFEA00080 +#define JIFESMW 0xFEA00084 +#define JIFESVSZ 0xFEA00088 +#define JIFESHSZ 0xFEA0008C +#define JIFEDA1 0xFEA00090 +#define JIFEDA2 0xFEA00094 +#define JIFEDRSZ 0xFEA00098 +#define JIFDCNT 0xFEA000A0 +#define JIFDSA1 0xFEA000A4 +#define JIFDSA2 0xFEA000A8 +#define JIFDDRSZ 0xFEA000AC +#define JIFDDMW 0xFEA000B0 +#define JIFDDVSZ 0xFEA000B4 +#define JIFDDHSZ 0xFEA000B8 +#define JIFDDYA1 0xFEA000BC +#define JIFDDCA1 0xFEA000C0 +#define JIFDDYA2 0xFEA000C4 +#define JIFDDCA2 0xFEA000C8 +#define JCQTBL0 0xFEA10000 +#define JCQTBL1 0xFEA10040 +#define JCQTBL2 0xFEA10080 +#define JCQTBL3 0xFEA100C0 +#define JCHTBD0 0xFEA10100 +#define JCHTBA0 0xFEA10120 +#define JCHTBD1 0xFEA10200 +#define JCHTBA1 0xFEA10220 + +/* LCDC */ +#define MLDDCKPAT1R 0xFE940400 +#define MLDDCKPAT2R 0xFE940404 +#define SLDDCKPAT1R 0xFE940408 +#define SLDDCKPAT2R 0xFE94040C +#define LDDCKR 0xFE940410 +#define LDDCKSTPR 0xFE940414 +#define MLDMT1R 0xFE940418 +#define MLDMT2R 0xFE94041C +#define MLDMT3R 0xFE940420 +#define MLDDFR 0xFE940424 +#define MLDSM1R 0xFE940428 +#define MLDSM2R 0xFE94042C +#define MLDSA1R 0xFE940430 +#define MLDSA2R 0xFE940434 +#define MLDMLSR 0xFE940438 +#define MLDWBFR 0xFE94043C +#define MLDWBCNTR 0xFE940440 +#define MLDWBAR 0xFE940444 +#define MLDHCNR 0xFE940448 +#define MLDHSYNR 0xFE94044C +#define MLDVLNR 0xFE940450 +#define MLDVSYNR 0xFE940454 +#define MLDHPDR 0xFE940458 +#define MLDVPDR 0xFE94045C +#define MLDPMR 0xFE940460 +#define LDPALCR 0xFE940464 +#define LDINTR 0xFE940468 +#define LDSR 0xFE94046C +#define LDCNT1R 0xFE940470 +#define LDCNT2R 0xFE940474 +#define LDRCNTR 0xFE940478 +#define LDDDSR 0xFE94047C +#define LDRCR 0xFE940484 +#define LDCMRKRGBR 0xFE9404C4 +#define LDCMRKCMYR 0xFE9404C8 +#define LDCMRK1R 0xFE9404CC +#define LDCMRK2R 0xFE9404D0 +#define LDCMGKRGBR 0xFE9404D4 +#define LDCMGKCMYR 0xFE9404D8 +#define LDCMGK1R 0xFE9404DC +#define LDCMGK2R 0xFE9404E0 +#define LDCMBKRGBR 0xFE9404E4 +#define LDCMBKCMYR 0xFE9404E8 +#define LDCMBK1R 0xFE9404EC +#define LDCMBK2R 0xFE9404F0 +#define LDCMHKPR 0xFE9404F4 +#define LDCMHKQR 0xFE9404F8 +#define LDCMSELR 0xFE9404FC +#define LDCMTVR 0xFE940500 +#define LDCMTVSELR 0xFE940504 +#define LDCMDTHR 0xFE940508 +#define LDCMCNTR 0xFE94050C +#define SLDMT1R 0xFE940600 +#define SLDMT2R 0xFE940604 +#define SLDMT3R 0xFE940608 +#define SLDDFR 0xFE94060C +#define SLDSM1R 0xFE940610 +#define SLDSM2R 0xFE940614 +#define SLDSA1R 0xFE940618 +#define SLDSA2R 0xFE94061C +#define SLDMLSR 0xFE940620 +#define SLDHCNR 0xFE940624 +#define SLDHSYNR 0xFE940628 +#define SLDVLNR 0xFE94062C +#define SLDVSYNR 0xFE940630 +#define SLDHPDR 0xFE940634 +#define SLDVPDR 0xFE940638 +#define SLDPMR 0xFE94063C +#define LDDWD0R 0xFE940800 +#define LDDWD1R 0xFE940804 +#define LDDWD2R 0xFE940808 +#define LDDWD3R 0xFE94080C +#define LDDWD4R 0xFE940810 +#define LDDWD5R 0xFE940814 +#define LDDWD6R 0xFE940818 +#define LDDWD7R 0xFE94081C +#define LDDWD8R 0xFE940820 +#define LDDWD9R 0xFE940824 +#define LDDWDAR 0xFE940828 +#define LDDWDBR 0xFE94082C +#define LDDWDCR 0xFE940830 +#define LDDWDDR 0xFE940834 +#define LDDWDER 0xFE940838 +#define LDDWDFR 0xFE94083C +#define LDDRDR 0xFE940840 +#define LDDWAR 0xFE940900 +#define LDDRAR 0xFE940904 +#define LDPR00 0xFE940000 + +/* VOU */ +#define VOUER 0xFE960000 +#define VOUCR 0xFE960004 +#define VOUSTR 0xFE960008 +#define VOUVCR 0xFE96000C +#define VOUISR 0xFE960010 +#define VOUBCR 0xFE960014 +#define VOUDPR 0xFE960018 +#define VOUDSR 0xFE96001C +#define VOUVPR 0xFE960020 +#define VOUIR 0xFE960024 +#define VOUSRR 0xFE960028 +#define VOUMSR 0xFE96002C +#define VOUHIR 0xFE960030 +#define VOUDFR 0xFE960034 +#define VOUAD1R 0xFE960038 +#define VOUAD2R 0xFE96003C +#define VOUAIR 0xFE960040 +#define VOUSWR 0xFE960044 +#define VOURCR 0xFE960048 +#define VOURPR 0xFE960050 + +/* TSIF */ +#define TSCTLR 0xA4C80000 +#define TSPIDR 0xA4C80004 +#define TSCMDR 0xA4C80008 +#define TSSTR 0xA4C8000C +#define TSTSDR 0xA4C80010 +#define TSBUFCLRR 0xA4C80014 +#define TSINTER 0xA4C80018 +#define TSPSCALER 0xA4C80020 +#define TSPSCALERR 0xA4C80024 +#define TSPCRADCMDR 0xA4C80028 +#define TSPCRADCR 0xA4C8002C +#define TSTRPCRADCR 0xA4C80030 +#define TSDPCRADCR 0xA4C80034 + +/* SIU */ +#define IFCTL 0xA454C000 +#define SRCTL 0xA454C004 +#define SFORM 0xA454C008 +#define CKCTL 0xA454C00C +#define TRDAT 0xA454C010 +#define STFIFO 0xA454C014 +#define DPAK 0xA454C01C +#define CKREV 0xA454C020 +#define EVNTC 0xA454C028 +#define SBCTL 0xA454C040 +#define SBPSET 0xA454C044 +#define SBBUS 0xA454C048 +#define SBWFLG 0xA454C058 +#define SBRFLG 0xA454C05C +#define SBWDAT 0xA454C060 +#define SBRDAT 0xA454C064 +#define SBFSTS 0xA454C068 +#define SBDVCA 0xA454C06C +#define SBDVCB 0xA454C070 +#define SBACTIV 0xA454C074 +#define DMAIA 0xA454C090 +#define DMAIB 0xA454C094 +#define DMAOA 0xA454C098 +#define DMAOB 0xA454C09C +#define SPLRI 0xA454C0B8 +#define SPRRI 0xA454C0BC +#define SPURI 0xA454C0C4 +#define SPTIS 0xA454C0C8 +#define SPSTS 0xA454C0CC +#define SPCTL 0xA454C0D0 +#define SPIRI 0xA454C0D4 +#define SPQCF 0xA454C0D8 +#define SPQCS 0xA454C0DC +#define SPQCT 0xA454C0E0 +#define DPEAK 0xA454C0F0 +#define DSLPD 0xA454C0F4 +#define DSLLV 0xA454C0F8 +#define BRGASEL 0xA454C100 +#define BRRA 0xA454C104 +#define BRGBSEL 0xA454C108 +#define BRRB 0xA454C10C + +/* USB */ +#define IFR0 0xA4480000 +#define ISR0 0xA4480010 +#define IER0 0xA4480020 +#define EPDR0I 0xA4480030 +#define EPDR0O 0xA4480034 +#define EPDR0S 0xA4480038 +#define EPDR1 0xA448003C +#define EPDR2 0xA4480040 +#define EPDR3 0xA4480044 +#define EPDR4 0xA4480048 +#define EPDR5 0xA448004C +#define EPDR6 0xA4480050 +#define EPDR7 0xA4480054 +#define EPDR8 0xA4480058 +#define EPDR9 0xA448005C +#define EPSZ0O 0xA4480080 +#define EPSZ3 0xA4480084 +#define EPSZ6 0xA4480088 +#define EPSZ9 0xA448008C +#define TRG 0xA44800A0 +#define DASTS 0xA44800A4 +#define FCLR 0xA44800AA +#define DMA 0xA44800AC +#define EPSTL 0xA44800B2 +#define CVR 0xA44800B4 +#define TSR 0xA44800B8 +#define CTLR 0xA44800BC +#define EPIR 0xA44800C0 +#define XVERCR 0xA44800D0 +#define STLMR 0xA44800D4 + +/* KEYSC */ +#define KYCR1 0xA44B0000 +#define KYCR2 0xA44B0004 +#define KYINDR 0xA44B0008 +#define KYOUTDR 0xA44B000C + +/* MMCIF */ +#define CMDR0 0xA4448000 +#define CMDR1 0xA4448001 +#define CMDR2 0xA4448002 +#define CMDR3 0xA4448003 +#define CMDR4 0xA4448004 +#define CMDR5 0xA4448005 +#define CMDSTRT 0xA4448006 +#define OPCR 0xA444800A +#define CSTR 0xA444800B +#define INTCR0 0xA444800C +#define INTCR1 0xA444800D +#define INTSTR0 0xA444800E +#define INTSTR1 0xA444800F +#define CLKON 0xA4448010 +#define CTOCR 0xA4448011 +#define VDCNT 0xA4448012 +#define TBCR 0xA4448014 +#define MODER 0xA4448016 +#define CMDTYR 0xA4448018 +#define RSPTYR 0xA4448019 +#define TBNCR 0xA444801A +#define RSPR0 0xA4448020 +#define RSPR1 0xA4448021 +#define RSPR2 0xA4448022 +#define RSPR3 0xA4448023 +#define RSPR4 0xA4448024 +#define RSPR5 0xA4448025 +#define RSPR6 0xA4448026 +#define RSPR7 0xA4448027 +#define RSPR8 0xA4448028 +#define RSPR9 0xA4448029 +#define RSPR10 0xA444802A +#define RSPR11 0xA444802B +#define RSPR12 0xA444802C +#define RSPR13 0xA444802D +#define RSPR14 0xA444802E +#define RSPR15 0xA444802F +#define RSPR16 0xA4448030 +#define RSPRD 0xA4448031 +#define DTOUTR 0xA4448032 +#define DR 0xA4448040 +#define FIFOCLR 0xA4448042 +#define DMACR 0xA4448044 +#define INTCR2 0xA4448046 +#define INTSTR2 0xA4448048 + +/* Z3D3 */ +#define DLBI 0xFD980000 +#define DLBD0 0xFD980080 +#define DLBD1 0xFD980100 +#define GEWM 0xFD984000 +#define ICD0 0xFD988000 +#define ICD1 0xFD989000 +#define ICT 0xFD98A000 +#define ILM 0xFD98C000 +#define FLM0 0xFD98C800 +#define FLM1 0xFD98D000 +#define FLUT 0xFD98D800 +#define Z3D_PC 0xFD98E400 +#define Z3D_PCSP 0xFD98E404 +#define Z3D_PAR 0xFD98E408 +#define Z3D_IMADR 0xFD98E40C +#define Z3D_BTR0 0xFD98E410 +#define Z3D_BTR1 0xFD98E414 +#define Z3D_BTR2 0xFD98E418 +#define Z3D_BTR3 0xFD98E41C +#define Z3D_LC0 0xFD98E420 +#define Z3D_LC1 0xFD98E424 +#define Z3D_LC2 0xFD98E428 +#define Z3D_LC3 0xFD98E42C +#define Z3D_FR0 0xFD98E430 +#define Z3D_FR1 0xFD98E434 +#define Z3D_FR2 0xFD98E438 +#define Z3D_SR 0xFD98E440 +#define Z3D_SMDR 0xFD98E444 +#define Z3D_PBIR 0xFD98E448 +#define Z3D_DMDR 0xFD98E44C +#define Z3D_IREG 0xFD98E460 +#define Z3D_AR00 0xFD98E480 +#define Z3D_AR01 0xFD98E484 +#define Z3D_AR02 0xFD98E488 +#define Z3D_AR03 0xFD98E48C +#define Z3D_BR00 0xFD98E490 +#define Z3D_BR01 0xFD98E494 +#define Z3D_IXR00 0xFD98E4A0 +#define Z3D_IXR01 0xFD98E4A4 +#define Z3D_IXR02 0xFD98E4A8 +#define Z3D_IXR03 0xFD98E4AC +#define Z3D_AR10 0xFD98E4C0 +#define Z3D_AR11 0xFD98E4C4 +#define Z3D_AR12 0xFD98E4C8 +#define Z3D_AR13 0xFD98E4CC +#define Z3D_BR10 0xFD98E4D0 +#define Z3D_BR11 0xFD98E4D4 +#define Z3D_IXR10 0xFD98E4E0 +#define Z3D_IXR11 0xFD98E4E4 +#define Z3D_IXR12 0xFD98E4E8 +#define Z3D_IXR13 0xFD98E4EC +#define Z3D_AR20 0xFD98E500 +#define Z3D_AR21 0xFD98E504 +#define Z3D_AR22 0xFD98E508 +#define Z3D_AR23 0xFD98E50C +#define Z3D_BR20 0xFD98E510 +#define Z3D_BR21 0xFD98E514 +#define Z3D_IXR20 0xFD98E520 +#define Z3D_IXR21 0xFD98E524 +#define Z3D_IXR22 0xFD98E528 +#define Z3D_IXR23 0xFD98E52C +#define Z3D_MR0 0xFD98E540 +#define Z3D_MR1 0xFD98E544 +#define Z3D_MR2 0xFD98E548 +#define Z3D_MR3 0xFD98E54C +#define Z3D_WORKRST 0xFD98E558 +#define Z3D_WORKWST 0xFD98E55C +#define Z3D_DBADR 0xFD98E560 +#define Z3D_DLBPRST 0xFD98E564 +#define Z3D_DLBRST 0xFD98E568 +#define Z3D_DLBWST 0xFD98E56C +#define Z3D_UDR0 0xFD98E570 +#define Z3D_UDR1 0xFD98E574 +#define Z3D_UDR2 0xFD98E578 +#define Z3D_UDR3 0xFD98E57C +#define Z3D_CCR0 0xFD98E580 +#define Z3D_CCR1 0xFD98E584 +#define Z3D_EXPR 0xFD98E588 +#define Z3D_V0_X 0xFD9A0000 +#define Z3D_V0_Y 0xFD9A0004 +#define Z3D_V0_Z 0xFD9A0008 +#define Z3D_V0_W 0xFD9A000C +#define Z3D_V0_A 0xFD9A0010 +#define Z3D_V0_R 0xFD9A0014 +#define Z3D_V0_G 0xFD9A0018 +#define Z3D_V0_B 0xFD9A001C +#define Z3D_V0_F 0xFD9A0020 +#define Z3D_V0_SR 0xFD9A0024 +#define Z3D_V0_SG 0xFD9A0028 +#define Z3D_V0_SB 0xFD9A002C +#define Z3D_V0_U0 0xFD9A0030 +#define Z3D_V0_V0 0xFD9A0034 +#define Z3D_V0_U1 0xFD9A0038 +#define Z3D_V0_V1 0xFD9A003C +#define Z3D_V1_X 0xFD9A0080 +#define Z3D_V1_Y 0xFD9A0084 +#define Z3D_V1_Z 0xFD9A0088 +#define Z3D_V1_W 0xFD9A008C +#define Z3D_V1_A 0xFD9A0090 +#define Z3D_V1_R 0xFD9A0094 +#define Z3D_V1_G 0xFD9A0098 +#define Z3D_V1_B 0xFD9A009C +#define Z3D_V1_F 0xFD9A00A0 +#define Z3D_V1_SR 0xFD9A00A4 +#define Z3D_V1_SG 0xFD9A00A8 +#define Z3D_V1_SB 0xFD9A00AC +#define Z3D_V1_U0 0xFD9A00B0 +#define Z3D_V1_V0 0xFD9A00B4 +#define Z3D_V1_U1 0xFD9A00B8 +#define Z3D_V1_V1 0xFD9A00BC +#define Z3D_V2_X 0xFD9A0100 +#define Z3D_V2_Y 0xFD9A0104 +#define Z3D_V2_Z 0xFD9A0108 +#define Z3D_V2_W 0xFD9A010C +#define Z3D_V2_A 0xFD9A0110 +#define Z3D_V2_R 0xFD9A0114 +#define Z3D_V2_G 0xFD9A0118 +#define Z3D_V2_B 0xFD9A011C +#define Z3D_V2_F 0xFD9A0120 +#define Z3D_V2_SR 0xFD9A0124 +#define Z3D_V2_SG 0xFD9A0128 +#define Z3D_V2_SB 0xFD9A012C +#define Z3D_V2_U0 0xFD9A0130 +#define Z3D_V2_V0 0xFD9A0134 +#define Z3D_V2_U1 0xFD9A0138 +#define Z3D_V2_V1 0xFD9A013C +#define Z3D_RENDER 0xFD9A0180 +#define Z3D_POLYGON_OFFSET 0xFD9A0184 +#define Z3D_VERTEX_CONTROL 0xFD9A0200 +#define Z3D_STATE_MODE 0xFD9A0204 +#define Z3D_FPU_MODE 0xFD9A0318 +#define Z3D_SCISSOR_MIN 0xFD9A0400 +#define Z3D_SCISSOR_MAX 0xFD9A0404 +#define Z3D_TEXTURE_MODE_A 0xFD9A0408 +#define Z3D_TEXTURE_MODE_B 0xFD9A040C +#define Z3D_TEXTURE_BASE_HI_A 0xFD9A0418 +#define Z3D_TEXTURE_BASE_LO_A 0xFD9A041C +#define Z3D_TEXTURE_BASE_HI_B 0xFD9A0420 +#define Z3D_TEXTURE_BASE_LO_B 0xFD9A0424 +#define Z3D_TEXTURE_ALPHA_A0 0xFD9A0438 +#define Z3D_TEXTURE_ALPHA_A1 0xFD9A043C +#define Z3D_TEXTURE_ALPHA_A2 0xFD9A0440 +#define Z3D_TEXTURE_ALPHA_A3 0xFD9A0444 +#define Z3D_TEXTURE_ALPHA_A4 0xFD9A0448 +#define Z3D_TEXTURE_ALPHA_A5 0xFD9A044C +#define Z3D_TEXTURE_ALPHA_B0 0xFD9A0450 +#define Z3D_TEXTURE_ALPHA_B1 0xFD9A0454 +#define Z3D_TEXTURE_ALPHA_B2 0xFD9A0458 +#define Z3D_TEXTURE_ALPHA_B3 0xFD9A045C +#define Z3D_TEXTURE_ALPHA_B4 0xFD9A0460 +#define Z3D_TEXTURE_ALPHA_B5 0xFD9A0464 +#define Z3D_TEXTURE_FLUSH 0xFD9A0498 +#define Z3D_GAMMA_TABLE0 0xFD9A049C +#define Z3D_GAMMA_TABLE1 0xFD9A04A0 +#define Z3D_GAMMA_TABLE2 0xFD9A04A4 +#define Z3D_ALPHA_TEST 0xFD9A0800 +#define Z3D_STENCIL_TEST 0xFD9A0804 +#define Z3D_DEPTH_ROP_BLEND_DITHER 0xFD9A0808 +#define Z3D_MASK 0xFD9A080C +#define Z3D_FBUS_MODE 0xFD9A0810 +#define Z3D_GNT_SET 0xFD9A0814 +#define Z3D_BETWEEN_TEST 0xFD9A0818 +#define Z3D_FB_BASE 0xFD9A081C +#define Z3D_LCD_SIZE 0xFD9A0820 +#define Z3D_FB_FLUSH 0xFD9A0824 +#define Z3D_CACHE_INVALID 0xFD9A0828 +#define Z3D_SC_MODE 0xFD9A0830 +#define Z3D_SC0_MIN 0xFD9A0834 +#define Z3D_SC0_MAX 0xFD9A0838 +#define Z3D_SC1_MIN 0xFD9A083C +#define Z3D_SC1_MAX 0xFD9A0840 +#define Z3D_SC2_MIN 0xFD9A0844 +#define Z3D_SC2_MAX 0xFD9A0848 +#define Z3D_SC3_MIN 0xFD9A084C +#define Z3D_SC3_MAX 0xFD9A0850 +#define Z3D_READRESET 0xFD9A0854 +#define Z3D_DET_MIN 0xFD9A0858 +#define Z3D_DET_MAX 0xFD9A085C +#define Z3D_FB_BASE_SR 0xFD9A0860 +#define Z3D_LCD_SIZE_SR 0xFD9A0864 +#define Z3D_2D_CTRL_STATUS 0xFD9A0C00 +#define Z3D_2D_SIZE 0xFD9A0C04 +#define Z3D_2D_SRCLOC 0xFD9A0C08 +#define Z3D_2D_DSTLOC 0xFD9A0C0C +#define Z3D_2D_DMAPORT 0xFD9A0C10 +#define Z3D_2D_CONSTANT_SOURCE0 0xFD9A0C14 +#define Z3D_2D_CONSTANT_SOURCE1 0xFD9A0C18 +#define Z3D_2D_STPCOLOR0 0xFD9A0C1C +#define Z3D_2D_STPCOLOR1 0xFD9A0C20 +#define Z3D_2D_STPPARAMETER_SET0 0xFD9A0C24 +#define Z3D_2D_STPPARAMETER_SET1 0xFD9A0C28 +#define Z3D_2D_STPPAT_0 0xFD9A0C40 +#define Z3D_2D_STPPAT_1 0xFD9A0C44 +#define Z3D_2D_STPPAT_2 0xFD9A0C48 +#define Z3D_2D_STPPAT_3 0xFD9A0C4C +#define Z3D_2D_STPPAT_4 0xFD9A0C50 +#define Z3D_2D_STPPAT_5 0xFD9A0C54 +#define Z3D_2D_STPPAT_6 0xFD9A0C58 +#define Z3D_2D_STPPAT_7 0xFD9A0C5C +#define Z3D_2D_STPPAT_8 0xFD9A0C60 +#define Z3D_2D_STPPAT_9 0xFD9A0C64 +#define Z3D_2D_STPPAT_10 0xFD9A0C68 +#define Z3D_2D_STPPAT_11 0xFD9A0C6C +#define Z3D_2D_STPPAT_12 0xFD9A0C70 +#define Z3D_2D_STPPAT_13 0xFD9A0C74 +#define Z3D_2D_STPPAT_14 0xFD9A0C78 +#define Z3D_2D_STPPAT_15 0xFD9A0C7C +#define Z3D_2D_STPPAT_16 0xFD9A0C80 +#define Z3D_2D_STPPAT_17 0xFD9A0C84 +#define Z3D_2D_STPPAT_18 0xFD9A0C88 +#define Z3D_2D_STPPAT_19 0xFD9A0C8C +#define Z3D_2D_STPPAT_20 0xFD9A0C90 +#define Z3D_2D_STPPAT_21 0xFD9A0C94 +#define Z3D_2D_STPPAT_22 0xFD9A0C98 +#define Z3D_2D_STPPAT_23 0xFD9A0C9C +#define Z3D_2D_STPPAT_24 0xFD9A0CA0 +#define Z3D_2D_STPPAT_25 0xFD9A0CA4 +#define Z3D_2D_STPPAT_26 0xFD9A0CA8 +#define Z3D_2D_STPPAT_27 0xFD9A0CAC +#define Z3D_2D_STPPAT_28 0xFD9A0CB0 +#define Z3D_2D_STPPAT_29 0xFD9A0CB4 +#define Z3D_2D_STPPAT_30 0xFD9A0CB8 +#define Z3D_2D_STPPAT_31 0xFD9A0CBC +#define Z3D_WR_CTRL 0xFD9A1000 +#define Z3D_WR_P0 0xFD9A1004 +#define Z3D_WR_P1 0xFD9A1008 +#define Z3D_WR_P2 0xFD9A100C +#define Z3D_WR_FGC 0xFD9A1010 +#define Z3D_WR_BGC 0xFD9A1014 +#define Z3D_WR_SZ 0xFD9A1018 +#define Z3D_WR_PATPARAM 0xFD9A101C +#define Z3D_WR_PAT 0xFD9A1020 +#define Z3D_SYS_STATUS 0xFD9A1400 +#define Z3D_SYS_RESET 0xFD9A1404 +#define Z3D_SYS_CLK 0xFD9A1408 +#define Z3D_SYS_CONF 0xFD9A140C +#define Z3D_SYS_VERSION 0xFD9A1410 +#define Z3D_SYS_DBINV 0xFD9A1418 +#define Z3D_SYS_I2F_FMT 0xFD9A1420 +#define Z3D_SYS_I2F_SRC 0xFD9A1424 +#define Z3D_SYS_I2F_DST 0xFD9A1428 +#define Z3D_SYS_GBCNT 0xFD9A1430 +#define Z3D_SYS_BSYCNT 0xFD9A1434 +#define Z3D_SYS_INT_STATUS 0xFD9A1450 +#define Z3D_SYS_INT_MASK 0xFD9A1454 +#define Z3D_SYS_INT_CLEAR 0xFD9A1458 +#define TCD0 0xFD9C0000 +#define TCD1 0xFD9C0400 +#define TCD2 0xFD9C0800 +#define TCD3 0xFD9C0C00 +#define TCT0 0xFD9C1000 +#define TCT1 0xFD9C1400 +#define TCT2 0xFD9C1800 +#define TCT3 0xFD9C1C00 + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PDCR 0xA4050106 +#define PECR 0xA4050108 +#define PFCR 0xA405010A +#define PGCR 0xA405010C +#define PHCR 0xA405010E +#define PJCR 0xA4050110 +#define PKCR 0xA4050112 +#define PLCR 0xA4050114 +#define PMCR 0xA4050116 +#define PNCR 0xA4050118 +#define PQCR 0xA405011A +#define PRCR 0xA405011C +#define PSCR 0xA405011E +#define PTCR 0xA4050140 +#define PUCR 0xA4050142 +#define PVCR 0xA4050144 +#define PWCR 0xA4050146 +#define PXCR 0xA4050148 +#define PYCR 0xA405014A +#define PZCR 0xA405014C +#define PSELA 0xA405014E +#define PSELB 0xA4050150 +#define PSELC 0xA4050152 +#define PSELD 0xA4050154 +#define PSELE 0xA4050156 +#define HIZCRA 0xA4050158 +#define HIZCRB 0xA405015A +#define HIZCRC 0xA405015C +#define MSELCR 0xA405015C +#define PULCR 0xA405015E +#define DRVCR 0xA4050180 +#define SBSCR 0xA4050182 +#define AUDTHCR 0xA4050184 +#define PSELF 0xA4050186 + +/* I/O Port */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 +#define PDDR 0xA4050126 +#define PEDR 0xA4050128 +#define PFDR 0xA405012A +#define PGDR 0xA405012C +#define PHDR 0xA405012E +#define PJDR 0xA4050130 +#define PKDR 0xA4050132 +#define PLDR 0xA4050134 +#define PMDR 0xA4050136 +#define PNDR 0xA4050138 +#define PQDR 0xA405013A +#define PRDR 0xA405013C +#define PSDR 0xA405013E +#define PTDR 0xA4050160 +#define PUDR 0xA4050162 +#define PVDR 0xA4050164 +#define PWDR 0xA4050166 +#define PYDR 0xA4050168 +#define PZDR 0xA405016A + +/* UBC */ +#define CBR0 0xFF200000 +#define CRR0 0xFF200004 +#define CAR0 0xFF200008 +#define CAMR0 0xFF20000C +#define CBR1 0xFF200020 +#define CRR1 0xFF200024 +#define CAR1 0xFF200028 +#define CAMR1 0xFF20002C +#define CDR1 0xFF200030 +#define CDMR1 0xFF200034 +#define CETR1 0xFF200038 +#define CCMFR 0xFF200600 +#define CBCR 0xFF200620 + +/* H-UDI */ +#define SDIR 0xFC110000 +#define SDDRH 0xFC110008 +#define SDDRL 0xFC11000A +#define SDINT 0xFC110018 + +#endif /* _ASM_CPU_SH7722_H_ */ diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h new file mode 100644 index 0000000..18e9851 --- /dev/null +++ b/include/configs/ms7722se.h @@ -0,0 +1,137 @@ +/* + * Configuation settings for the Hitachi Solution Engine 7722 + * + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MS7722SE_H +#define __MS7722SE_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH4 1 +#define CONFIG_CPU_SH7722 1 +#define CONFIG_MS7722SE 1 + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_ENV + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.0.22 +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_GATEWAYIP 192.168.0.1 + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* SMC9111 */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE (0xB8000000) + +/* MEMORY */ +#define MS7722SE_SDRAM_BASE (0x8C000000) +#define MS7722SE_FLASH_BASE_1 (0xA0000000) +//#define MS7722SE_FLASH_BASE_1 (0xA1000000) +#define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024) + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ +#define CFG_PBSIZE 256 /* Buffer size for Console output */ +#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ +#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ +#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ + +/* SCIF */ +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF0 1 +#undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */ +#undef CFG_CONSOLE_OVERWRITE_ROUTINE +#undef CFG_CONSOLE_ENV_OVERWRITE + +#define CFG_MEMTEST_START (MS7722SE_SDRAM_BASE) +#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) + +#undef CFG_ALT_MEMTEST /* Enable alternate, more extensive, memory test */ +#undef CFG_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */ + +#undef CFG_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */ + +#define CFG_SDRAM_BASE (MS7722SE_SDRAM_BASE) +#define CFG_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */ + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */ + +#define CFG_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image + in Flash (NOT run time address in SDRAM) ?!? */ +#define CFG_MONITOR_LEN (128 * 1024) /* */ +#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ +#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */ + +#define CFG_MAX_FLASH_SECT 150 /* Max number of sectors on each + Flash chip */ + +/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */ +#define CFG_MAX_FLASH_BANKS 2 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \ + CFG_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \ + } + +#define CFG_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */ +#define CFG_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */ +#define CFG_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */ + +#undef CFG_FLASH_PROTECTION /* Use hardware flash sectors protection instead of U-Boot software protection */ + +#undef CFG_DIRECT_FLASH_TFTP + +#define CFG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE 1 +#define CFG_ENV_SECT_SIZE (8 * 1024) +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE)) +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) /* Offset of env Flash sector relative to CFG_FLASH_BASE */ +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE)) + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 33333333 +#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +#endif /* __MS7722SE_H */ -- cgit v1.1 From 9553df86d3a319c3a1a7cde7e4edd6eeb5aa64c7 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 16 Oct 2007 15:26:51 -0500 Subject: Initial mpc8610hpcd cpu/, README and include/ files. Signed-off-by: Ed Swarthout Signed-off-by: Mahesh Jade Signed-off-by: Jason Jin Signed-off-by: Jon Loeliger --- include/asm-ppc/processor.h | 1 + include/configs/MPC8610HPCD.h | 660 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 661 insertions(+) create mode 100644 include/configs/MPC8610HPCD.h (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0a160e2..07c1de0 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -875,6 +875,7 @@ #define SVR_8544_E 0x803C #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 +#define SVR_8610 0x80A0 #define SVR_8641 0x8090 #define SVR_8568_E 0x807D diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h new file mode 100644 index 0000000..be3434a --- /dev/null +++ b/include/configs/MPC8610HPCD.h @@ -0,0 +1,660 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +/* + * MPC8610HPCD board configuration file + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8610 1 /* MPC8610 specific */ +#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ +#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ + +#ifdef RUN_DIAG +#define CFG_DIAG_ADDR 0xff800000 +#endif + +#define CFG_RESET_ADDRESS 0xfff00100 + +#define CONFIG_PCI 1 /* Enable PCI/PCIE*/ +#define CONFIG_PCI1 1 /* PCI controler 1 */ +#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ +#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SPD_EEPROM /* Use SPD for DDR */ +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ + +#define CONFIG_ALTIVEC 1 + +/* + * L2CR setup -- make sure this is right for your board! + */ +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 +#define CFG_ALT_MEMTEST + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) +#define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) + +#define CFG_DIU_ADDR (CFG_CCSRBAR+0x2c000) + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define MPC86xx_DDR_SDRAM_CLK_CNTL + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ +#else +/* + * Manually set up DDR1 parameters + */ + +#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ + +#if 0 /* TODO */ +#define CFG_DDR_CS0_BNDS 0x0000000F +#define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ +#define CFG_DDR_EXT_REFRESH 0x00000000 +#define CFG_DDR_TIMING_0 0x00260802 +#define CFG_DDR_TIMING_1 0x3935d322 +#define CFG_DDR_TIMING_2 0x14904cc8 +#define CFG_DDR_MODE_1 0x00480432 +#define CFG_DDR_MODE_2 0x00000000 +#define CFG_DDR_INTERVAL 0x06180100 +#define CFG_DDR_DATA_INIT 0xdeadbeef +#define CFG_DDR_CLK_CTRL 0x03800000 +#define CFG_DDR_OCD_CTRL 0x00000000 +#define CFG_DDR_OCD_STATUS 0x00000000 +#define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ +#define CFG_DDR_CONTROL2 0x04400010 + +#define CFG_DDR_ERR_INT_EN 0x00000000 +#define CFG_DDR_ERR_DIS 0x00000000 +#define CFG_DDR_SBE 0x000f0000 + /* Not used in fixed_sdram function */ +#define CFG_DDR_MODE 0x00000022 +#define CFG_DDR_CS1_BNDS 0x00000000 +#define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ +#define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ +#define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ +#define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ +#endif +#endif + +#define CFG_ID_EEPROM +#define ID_EEPROM_ADDR 0x57 + + +#define CFG_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ +#define CFG_FLASH_BASE2 0xf8000000 + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + +#define CFG_BR0_PRELIM 0xf8001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ + +#define CFG_BR1_PRELIM 0xf0001001 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ +#if 0 /* TODO */ +#define CFG_BR2_PRELIM 0xf0000000 +#define CFG_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ +#endif +#define CFG_BR3_PRELIM 0xe8000801 /* port size 8bit */ +#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ + + +#define PIXIS_BASE 0xe8000000 /* PIXIS registers */ +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#if defined(CFG_RAMBOOT) +#undef CONFIG_SPD_EEPROM +#define CFG_SDRAM_SIZE 256 +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#ifndef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#else +#define CFG_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ +#endif +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree to kernel + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8610@0" +#define OF_SOC "soc@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@e0000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe1000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +/* For RTL8139 */ +#define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) +#define _IO_BASE 0x00000000 + +/* controller 1, Base address 0xa000 */ +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe3000000 +#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ + +/* controller 2, Base Address 0x9000 */ +#define CFG_PCIE2_MEM_BASE 0x90000000 +#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE +#define CFG_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */ +#define CFG_PCIE2_IO_PHYS 0xe2000000 +#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ + + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#if 0 /* TODO */ +/* enable onboard uli network support */ +#endif + +#define CONFIG_RTL8139 +#define CONFIG_SK98 +#define CONFIG_EEPRO100 +#define CONFIG_TULIP + +#if 0 /* TODO */ +/************************************************************ + * USB support + ************************************************************/ +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_KEYBOARD 1 +#define CFG_DEVICE_DEREGISTER +#define CFG_USB_INTERRUPT_POLL 1 +#endif + +#if !defined(CONFIG_PCI_PNP) +#define PCI_ENET0_IOADDR 0xe0000000 +#define PCI_ENET0_MEMADDR 0xe0000000 +#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif + +#endif /* CONFIG_PCI */ + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) +#define CFG_IBAT0U CFG_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 256M PCI-1 Memory + * 0xa000_0000 256M PCI-Express 1 Memory + * 0x9000_0000 256M PCI-Express 2 Memory + */ + +#define CFG_DBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U CFG_DBAT1U + +/* + * BAT2 32M Cache-inhibited, guarded + * 0xe100_0000 1M PCI-1 I/O + * 0xe200_0000 1M PCI-Express 2 I/O + * + */ + +#define CFG_DBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U CFG_DBAT2U + +/* + * BAT3 1M Cache-inhibited, guarded + * 0xe300_0000 1M PCI-Express 1 I/O + * + */ + +#define CFG_DBAT3L (CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_PCIE1_IO_PHYS | BATU_BL_1M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U + +/* + * BAT4 4M Cache-inhibited, guarded + * 0xe000_0000 4M CCSR + */ +#define CFG_DBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U (CFG_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U CFG_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U + +/* + * BAT6 256M Cache-inhibited, guarded + * 0xf000_0000 256M FLASH + */ +#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U + +/* + * BAT7 4M Cache-inhibited, guarded + * 0xe800_0000 4M PIXIS + */ +#define CFG_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CFG_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) +#define CFG_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT7U CFG_DBAT7U + + +/* + * Environment + */ +#ifndef CFG_RAMBOOT +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ +#define CFG_ENV_SIZE 0x2000 +#else +#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +#define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII + +#if defined(CFG_RAMBOOT) +#undef CONFIG_CMD_ENV +#endif + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_EXT2 +#endif + + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_IPADDR 192.168.1.100 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#if defined(CONFIG_PCI1) +#define PCI_ENV \ + "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ + "echo e;md ${a}e00 9\0" \ + "pci1regs=setenv a e0008; run pcireg\0" \ + "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1\0" \ + "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ + "pci w.w $b.0 56 ffff\0" \ + "pci1err=setenv a e0008; run pcierr\0" \ + "pci1errc=setenv a e0008; run pcierrc\0" +#else +#define PCI_ENV "" +#endif + +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) +#define PCIE_ENV \ + "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ + "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ + "pcie1regs=setenv a e000a; run pciereg\0" \ + "pcie2regs=setenv a e0009; run pciereg\0" \ + "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ + "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ + "pci d $b.0 130 1\0" \ + "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ + "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ + "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ + "pcie1err=setenv a e000a; run pcieerr\0" \ + "pcie2err=setenv a e0009; run pcieerr\0" \ + "pcie1errc=setenv a e000a; run pcieerrc\0" \ + "pcie2errc=setenv a e0009; run pcieerrc\0" +#else +#define PCIE_ENV "" +#endif + +#define DMA_ENV \ + "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ + "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ + "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ + "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ + "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ + "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ + "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ + "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ + "dtbaddr=c00000\0" \ + "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0" \ + "bdev=sda3\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=1" \ + "eoi=mw e00400b0 0\0" \ + "iack=md e00400a0 1\0" \ + "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ + "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ + "md ${a}f00 5\0" \ + "ddr1regs=setenv a e0002; run ddrreg\0" \ + "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ + "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ + "md ${a}e60 1; md ${a}ef0 1d\0" \ + "guregs=setenv a e00e0; run gureg\0" \ + "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ + "mcmregs=setenv a e0001; run mcmreg\0" \ + "diuregs=md e002c000 1d\0" \ + "dium=mw e002c01c\0" \ + "diuerr=md e002c014 1\0" \ + "othbootargs=debug\0" \ + "pmregs=md e00e1000 2b\0" \ + "lawregs=md e0000c08 4b\0" \ + "lbcregs=md e0005000 36\0" \ + "dma0regs=md e0021100 12\0" \ + "dma1regs=md e0021180 12\0" \ + "dma2regs=md e0021200 12\0" \ + "dma3regs=md e0021280 12\0" \ + PCI_ENV \ + PCIE_ENV \ + DMA_ENV + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" + +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" + +#endif /* __CONFIG_H */ -- cgit v1.1 From 20d500d531a6b971ce6cc1bf191cb0092cdc0afc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 23 Oct 2007 10:17:42 +0200 Subject: ppc4xx: lwmon5: Some further GPIO config changes Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 00c34d5..52deab4 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -432,7 +432,7 @@ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ @@ -473,7 +473,7 @@ {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ -- cgit v1.1 From c7c6da23028f146d912514b95aefa3da7cf37699 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 3 Oct 2007 07:34:10 +0200 Subject: ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1) This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (1) This patch renames the files from 440spe_pcie to 4xx_pcie Signed-off-by: Stefan Roese --- include/asm-ppc/4xx_pcie.h | 174 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 174 insertions(+) create mode 100644 include/asm-ppc/4xx_pcie.h (limited to 'include') diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h new file mode 100644 index 0000000..38745eb --- /dev/null +++ b/include/asm-ppc/4xx_pcie.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#ifndef __440SPE_PCIE_H +#define __440SPE_PCIE_H + +#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) + +#define DCRN_SDR0_CFGADDR 0x00e +#define DCRN_SDR0_CFGDATA 0x00f + +#define DCRN_PCIE0_BASE 0x100 +#define DCRN_PCIE1_BASE 0x120 +#define DCRN_PCIE2_BASE 0x140 +#define PCIE0 DCRN_PCIE0_BASE +#define PCIE1 DCRN_PCIE1_BASE +#define PCIE2 DCRN_PCIE2_BASE + +#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) +#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) +#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) +#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) +#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) +#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) +#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) +#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) +#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) +#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) +#define DCRN_PEGPL_REGBAH(base) (base + 0x12) +#define DCRN_PEGPL_REGBAL(base) (base + 0x13) +#define DCRN_PEGPL_REGMSK(base) (base + 0x14) +#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) +#define DCRN_PEGPL_CFG(base) (base + 0x16) + +/* + * System DCRs (SDRs) + */ +#define PESDR0_PLLLCT1 0x03a0 +#define PESDR0_PLLLCT2 0x03a1 +#define PESDR0_PLLLCT3 0x03a2 + +#define PESDR0_UTLSET1 0x0300 +#define PESDR0_UTLSET2 0x0301 +#define PESDR0_DLPSET 0x0302 +#define PESDR0_LOOP 0x0303 +#define PESDR0_RCSSET 0x0304 +#define PESDR0_RCSSTS 0x0305 +#define PESDR0_HSSL0SET1 0x0306 +#define PESDR0_HSSL0SET2 0x0307 +#define PESDR0_HSSL0STS 0x0308 +#define PESDR0_HSSL1SET1 0x0309 +#define PESDR0_HSSL1SET2 0x030a +#define PESDR0_HSSL1STS 0x030b +#define PESDR0_HSSL2SET1 0x030c +#define PESDR0_HSSL2SET2 0x030d +#define PESDR0_HSSL2STS 0x030e +#define PESDR0_HSSL3SET1 0x030f +#define PESDR0_HSSL3SET2 0x0310 +#define PESDR0_HSSL3STS 0x0311 +#define PESDR0_HSSL4SET1 0x0312 +#define PESDR0_HSSL4SET2 0x0313 +#define PESDR0_HSSL4STS 0x0314 +#define PESDR0_HSSL5SET1 0x0315 +#define PESDR0_HSSL5SET2 0x0316 +#define PESDR0_HSSL5STS 0x0317 +#define PESDR0_HSSL6SET1 0x0318 +#define PESDR0_HSSL6SET2 0x0319 +#define PESDR0_HSSL6STS 0x031a +#define PESDR0_HSSL7SET1 0x031b +#define PESDR0_HSSL7SET2 0x031c +#define PESDR0_HSSL7STS 0x031d +#define PESDR0_HSSCTLSET 0x031e +#define PESDR0_LANE_ABCD 0x031f +#define PESDR0_LANE_EFGH 0x0320 + +#define PESDR1_UTLSET1 0x0340 +#define PESDR1_UTLSET2 0x0341 +#define PESDR1_DLPSET 0x0342 +#define PESDR1_LOOP 0x0343 +#define PESDR1_RCSSET 0x0344 +#define PESDR1_RCSSTS 0x0345 +#define PESDR1_HSSL0SET1 0x0346 +#define PESDR1_HSSL0SET2 0x0347 +#define PESDR1_HSSL0STS 0x0348 +#define PESDR1_HSSL1SET1 0x0349 +#define PESDR1_HSSL1SET2 0x034a +#define PESDR1_HSSL1STS 0x034b +#define PESDR1_HSSL2SET1 0x034c +#define PESDR1_HSSL2SET2 0x034d +#define PESDR1_HSSL2STS 0x034e +#define PESDR1_HSSL3SET1 0x034f +#define PESDR1_HSSL3SET2 0x0350 +#define PESDR1_HSSL3STS 0x0351 +#define PESDR1_HSSCTLSET 0x0352 +#define PESDR1_LANE_ABCD 0x0353 + +#define PESDR2_UTLSET1 0x0370 +#define PESDR2_UTLSET2 0x0371 +#define PESDR2_DLPSET 0x0372 +#define PESDR2_LOOP 0x0373 +#define PESDR2_RCSSET 0x0374 +#define PESDR2_RCSSTS 0x0375 +#define PESDR2_HSSL0SET1 0x0376 +#define PESDR2_HSSL0SET2 0x0377 +#define PESDR2_HSSL0STS 0x0378 +#define PESDR2_HSSL1SET1 0x0379 +#define PESDR2_HSSL1SET2 0x037a +#define PESDR2_HSSL1STS 0x037b +#define PESDR2_HSSL2SET1 0x037c +#define PESDR2_HSSL2SET2 0x037d +#define PESDR2_HSSL2STS 0x037e +#define PESDR2_HSSL3SET1 0x037f +#define PESDR2_HSSL3SET2 0x0380 +#define PESDR2_HSSL3STS 0x0381 +#define PESDR2_HSSCTLSET 0x0382 +#define PESDR2_LANE_ABCD 0x0383 + +/* + * UTL register offsets + */ +#define PEUTL_PBBSZ 0x20 +#define PEUTL_OPDBSZ 0x68 +#define PEUTL_IPHBSZ 0x70 +#define PEUTL_IPDBSZ 0x78 +#define PEUTL_OUTTR 0x90 +#define PEUTL_INTR 0x98 +#define PEUTL_PCTL 0xa0 +#define PEUTL_RCIRQEN 0xb8 + +/* + * Config space register offsets + */ +#define PECFG_BAR0LMPA 0x210 +#define PECFG_BAR0HMPA 0x214 +#define PECFG_BAR1MPA 0x218 +#define PECFG_BAR2MPA 0x220 + +#define PECFG_PIMEN 0x33c +#define PECFG_PIM0LAL 0x340 +#define PECFG_PIM0LAH 0x344 +#define PECFG_PIM1LAL 0x348 +#define PECFG_PIM1LAH 0x34c +#define PECFG_PIM01SAL 0x350 +#define PECFG_PIM01SAH 0x354 + +#define PECFG_POM0LAL 0x380 +#define PECFG_POM0LAH 0x384 + +#define SDR_READ(offset) ({\ + mtdcr(DCRN_SDR0_CFGADDR, offset); \ + mfdcr(DCRN_SDR0_CFGDATA);}) + +#define SDR_WRITE(offset, data) ({\ + mtdcr(DCRN_SDR0_CFGADDR, offset); \ + mtdcr(DCRN_SDR0_CFGDATA,data);}) + +#define GPL_DMER_MASK_DISA 0x02000000 + +int ppc440spe_init_pcie(void); +int ppc440spe_init_pcie_rootport(int port); +void yucca_setup_pcie_fpga_rootpoint(int port); +void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port); +int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port); +int yucca_pcie_card_present(int port); +int pcie_hose_scan(struct pci_controller *hose, int bus); +#endif /* __440SPE_PCIE_H */ -- cgit v1.1 From 026f71106871f31d17d0ea0db9a7547ff92934bc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 3 Oct 2007 07:48:09 +0200 Subject: ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2) This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (2) This patch renames the functions from 440spe_ to 4xx_ with a little additional cleanup Signed-off-by: Stefan Roese --- include/asm-ppc/4xx_pcie.h | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 38745eb..220c60c 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -9,8 +9,8 @@ */ #include -#ifndef __440SPE_PCIE_H -#define __440SPE_PCIE_H +#ifndef __4XX_PCIE_H +#define __4XX_PCIE_H #define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) @@ -164,11 +164,10 @@ #define GPL_DMER_MASK_DISA 0x02000000 -int ppc440spe_init_pcie(void); -int ppc440spe_init_pcie_rootport(int port); -void yucca_setup_pcie_fpga_rootpoint(int port); -void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port); -int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port); -int yucca_pcie_card_present(int port); +int ppc4xx_init_pcie(void); +int ppc4xx_init_pcie_rootport(int port); +void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port); +int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port); int pcie_hose_scan(struct pci_controller *hose, int bus); -#endif /* __440SPE_PCIE_H */ + +#endif /* __4XX_PCIE_H */ -- cgit v1.1 From 03d344bb6a5f082ea10ec9d753558ea7dfd1c626 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 3 Oct 2007 10:38:09 +0200 Subject: ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3) (3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access the SDR registers of the PCIe ports. This makes the overall design clearer, since it removed a lot of switch statements which are not needed anymore. Also, the functions ppc4xx_init_pcie_rootport() and ppc4xx_init_pcie_entport() are merged into a single function ppc4xx_init_pcie_port(), since most of the code was duplicated. This makes maintainance and porting to other 4xx platforms easier. Signed-off-by: Stefan Roese --- include/asm-ppc/4xx_pcie.h | 101 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 99 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 220c60c..1bb8fc7 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -12,14 +12,20 @@ #ifndef __4XX_PCIE_H #define __4XX_PCIE_H -#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) - #define DCRN_SDR0_CFGADDR 0x00e #define DCRN_SDR0_CFGDATA 0x00f +#if defined(CONFIG_440SPE) #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 #define DCRN_PCIE2_BASE 0x140 +#endif + +#if defined(CONFIG_405EX) +#define DCRN_PCIE0_BASE 0x040 +#define DCRN_PCIE1_BASE 0x060 +#endif + #define PCIE0 DCRN_PCIE0_BASE #define PCIE1 DCRN_PCIE1_BASE #define PCIE2 DCRN_PCIE2_BASE @@ -47,6 +53,39 @@ #define PESDR0_PLLLCT2 0x03a1 #define PESDR0_PLLLCT3 0x03a2 +#if defined(CONFIG_440SPE) +#define PCIE0_SDR 0x300 +#define PCIE1_SDR 0x340 +#define PCIE2_SDR 0x370 +#endif + +#if defined(CONFIG_405EX) +#define PCIE0_SDR 0x400 +#define PCIE1_SDR 0x440 +#endif + +/* common regs, at least for 405EX and 440SPe */ +#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00) +#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01) +#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02) +#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03) +#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04) +#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05) + +#if defined(CONFIG_440SPE) +#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06) +#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07) +#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08) +#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09) +#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a) +#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b) +#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c) +#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d) +#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e) +#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f) +#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10) +#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11) + #define PESDR0_UTLSET1 0x0300 #define PESDR0_UTLSET2 0x0301 #define PESDR0_DLPSET 0x0302 @@ -123,6 +162,40 @@ #define PESDR2_HSSCTLSET 0x0382 #define PESDR2_LANE_ABCD 0x0383 +#elif defined(CONFIG_405EX) + +#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06) +#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07) +#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08) +#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b) +#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c) + +#define PESDR0_UTLSET1 0x0400 +#define PESDR0_UTLSET2 0x0401 +#define PESDR0_DLPSET 0x0402 +#define PESDR0_LOOP 0x0403 +#define PESDR0_RCSSET 0x0404 +#define PESDR0_RCSSTS 0x0405 +#define PESDR0_PHYSET1 0x0406 +#define PESDR0_PHYSET2 0x0407 +#define PESDR0_BIST 0x0408 +#define PESDR0_LPB 0x040B +#define PESDR0_PHYSTA 0x040C + +#define PESDR1_UTLSET1 0x0440 +#define PESDR1_UTLSET2 0x0441 +#define PESDR1_DLPSET 0x0442 +#define PESDR1_LOOP 0x0443 +#define PESDR1_RCSSET 0x0444 +#define PESDR1_RCSSTS 0x0445 +#define PESDR1_PHYSET1 0x0446 +#define PESDR1_PHYSET2 0x0447 +#define PESDR1_BIST 0x0448 +#define PESDR1_LPB 0x044B +#define PESDR1_PHYSTA 0x044C + +#endif + /* * UTL register offsets */ @@ -166,8 +239,32 @@ int ppc4xx_init_pcie(void); int ppc4xx_init_pcie_rootport(int port); +int ppc4xx_init_pcie_endport(int port); void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port); int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port); int pcie_hose_scan(struct pci_controller *hose, int bus); +static inline void mdelay(int n) +{ + u32 ms = n; + + while (ms--) + udelay(1000); +} + +static inline u32 sdr_base(int port) +{ + switch (port) { + default: /* to satisfy compiler */ + case 0: + return PCIE0_SDR; + case 1: + return PCIE1_SDR; +#if defined(PCIE2_SDR) + case 2: + return PCIE2_SDR; +#endif + } +} + #endif /* __4XX_PCIE_H */ -- cgit v1.1 From 3048bcbf0bad262378c5af68f2bf6778fb7d829a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 3 Oct 2007 15:01:02 +0200 Subject: ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platforms These files were introduced with the IBM 405GP but are currently used on all 4xx PPC platforms. So the name doesn't match the content anymore. This patch renames the files to 4xx_pci.c/h. Signed-off-by: Stefan Roese --- include/405gp_pci.h | 52 ----------------------------------------------- include/asm-ppc/4xx_pci.h | 52 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 52 deletions(-) delete mode 100644 include/405gp_pci.h create mode 100644 include/asm-ppc/4xx_pci.h (limited to 'include') diff --git a/include/405gp_pci.h b/include/405gp_pci.h deleted file mode 100644 index 3c1adec..0000000 --- a/include/405gp_pci.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef _405GP_PCI_H -#define _405GP_PCI_H - -/*----------------------------------------------------------------------------+ -| 405GP PCI core memory map defines. -+----------------------------------------------------------------------------*/ -#define MIN_PCI_MEMADDR1 0x80000000 -#define MIN_PCI_MEMADDR2 0x00000000 -#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ -#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ -#define MAX_PCI_DEVICES 32 - -/*----------------------------------------------------------------------------+ -| Defines for the 405GP PCI Config address and data registers followed by -| defines for the standard PCI device configuration header. -+----------------------------------------------------------------------------*/ -#define PCICFGADR 0xEEC00000 -#define PCICFGDATA 0xEEC00004 - -#define PCIBUSNUM 0x40 /* 405GP specific parameters */ -#define PCISUBBUSNUM 0x41 -#define PCIDISCOUNT 0x42 -#define PCIBRDGOPT1 0x4A -#define PCIBRDGOPT2 0x60 - -/*----------------------------------------------------------------------------+ -| Defines for 405GP PCI Master local configuration regs. -+----------------------------------------------------------------------------*/ -#define PMM0LA 0xEF400000 -#define PMM0MA 0xEF400004 -#define PMM0PCILA 0xEF400008 -#define PMM0PCIHA 0xEF40000C -#define PMM1LA 0xEF400010 -#define PMM1MA 0xEF400014 -#define PMM1PCILA 0xEF400018 -#define PMM1PCIHA 0xEF40001C -#define PMM2LA 0xEF400020 -#define PMM2MA 0xEF400024 -#define PMM2PCILA 0xEF400028 -#define PMM2PCIHA 0xEF40002C - -/*----------------------------------------------------------------------------+ -| Defines for 405GP PCI Target local configuration regs. -+----------------------------------------------------------------------------*/ -#define PTM1MS 0xEF400030 -#define PTM1LA 0xEF400034 -#define PTM2MS 0xEF400038 -#define PTM2LA 0xEF40003C - -#define PCIDEVID_405GP 0x0 - -#endif diff --git a/include/asm-ppc/4xx_pci.h b/include/asm-ppc/4xx_pci.h new file mode 100644 index 0000000..3c1adec --- /dev/null +++ b/include/asm-ppc/4xx_pci.h @@ -0,0 +1,52 @@ +#ifndef _405GP_PCI_H +#define _405GP_PCI_H + +/*----------------------------------------------------------------------------+ +| 405GP PCI core memory map defines. ++----------------------------------------------------------------------------*/ +#define MIN_PCI_MEMADDR1 0x80000000 +#define MIN_PCI_MEMADDR2 0x00000000 +#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ +#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ +#define MAX_PCI_DEVICES 32 + +/*----------------------------------------------------------------------------+ +| Defines for the 405GP PCI Config address and data registers followed by +| defines for the standard PCI device configuration header. ++----------------------------------------------------------------------------*/ +#define PCICFGADR 0xEEC00000 +#define PCICFGDATA 0xEEC00004 + +#define PCIBUSNUM 0x40 /* 405GP specific parameters */ +#define PCISUBBUSNUM 0x41 +#define PCIDISCOUNT 0x42 +#define PCIBRDGOPT1 0x4A +#define PCIBRDGOPT2 0x60 + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Master local configuration regs. ++----------------------------------------------------------------------------*/ +#define PMM0LA 0xEF400000 +#define PMM0MA 0xEF400004 +#define PMM0PCILA 0xEF400008 +#define PMM0PCIHA 0xEF40000C +#define PMM1LA 0xEF400010 +#define PMM1MA 0xEF400014 +#define PMM1PCILA 0xEF400018 +#define PMM1PCIHA 0xEF40001C +#define PMM2LA 0xEF400020 +#define PMM2MA 0xEF400024 +#define PMM2PCILA 0xEF400028 +#define PMM2PCIHA 0xEF40002C + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Target local configuration regs. ++----------------------------------------------------------------------------*/ +#define PTM1MS 0xEF400030 +#define PTM1LA 0xEF400034 +#define PTM2MS 0xEF400038 +#define PTM2LA 0xEF40003C + +#define PCIDEVID_405GP 0x0 + +#endif -- cgit v1.1 From 4dbee8a90df613eb517aadbecebd70f168913d30 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 07:57:20 +0200 Subject: ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & Katmai 128MB seems to be the smallest possible value for the memory size for on PCIe port. With this change now the BAR's of the PCIe cards are accessible under U-Boot. One big note: This only works for PCIe port 0 & 1. For port 2 this currently doesn't work, since the base address is now 0xc0000000 (0xb0000000 + 2 * 0x08000000), and this is already occupied by CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean to change the base addresses completely and this change would have too much impact right now. This patch adds debug output to the 4xx pcie driver too. Signed-off-by: Stefan Roese --- include/configs/katmai.h | 2 +- include/configs/yucca.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 7908e5a..03c3cb3 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -62,7 +62,7 @@ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ -#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 74033b4..6caf21b 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -64,7 +64,7 @@ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ -#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -- cgit v1.1 From 97923770cb52b64d69eec958a11b2eda8d46e0f7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 09:18:23 +0200 Subject: ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support added Signed-off-by: Stefan Roese --- include/asm-ppc/4xx_pcie.h | 31 +++++++++++++++++++------------ include/configs/katmai.h | 3 +++ include/configs/yucca.h | 3 +++ 3 files changed, 25 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 1bb8fc7..17ac57b 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -16,14 +16,29 @@ #define DCRN_SDR0_CFGDATA 0x00f #if defined(CONFIG_440SPE) +#define CFG_PCIE_NR_PORTS 3 + +#define CFG_PCIE_ADDR_HIGH 0x0000000d + #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 #define DCRN_PCIE2_BASE 0x140 + +#define PCIE0_SDR 0x300 +#define PCIE1_SDR 0x340 +#define PCIE2_SDR 0x370 #endif #if defined(CONFIG_405EX) +#define CFG_PCIE_NR_PORTS 2 + +#define CFG_PCIE_ADDR_HIGH 0x00000000 + #define DCRN_PCIE0_BASE 0x040 #define DCRN_PCIE1_BASE 0x060 + +#define PCIE0_SDR 0x400 +#define PCIE1_SDR 0x440 #endif #define PCIE0 DCRN_PCIE0_BASE @@ -53,17 +68,6 @@ #define PESDR0_PLLLCT2 0x03a1 #define PESDR0_PLLLCT3 0x03a2 -#if defined(CONFIG_440SPE) -#define PCIE0_SDR 0x300 -#define PCIE1_SDR 0x340 -#define PCIE2_SDR 0x370 -#endif - -#if defined(CONFIG_405EX) -#define PCIE0_SDR 0x400 -#define PCIE1_SDR 0x440 -#endif - /* common regs, at least for 405EX and 440SPe */ #define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00) #define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01) @@ -237,6 +241,9 @@ #define GPL_DMER_MASK_DISA 0x02000000 +#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) +#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) + int ppc4xx_init_pcie(void); int ppc4xx_init_pcie_rootport(int port); int ppc4xx_init_pcie_endport(int port); @@ -260,7 +267,7 @@ static inline u32 sdr_base(int port) return PCIE0_SDR; case 1: return PCIE1_SDR; -#if defined(PCIE2_SDR) +#if CFG_PCIE_NR_PORTS > 2 case 2: return PCIE2_SDR; #endif diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 03c3cb3..8a96327 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -72,6 +72,9 @@ #define CFG_PCIE1_XCFGBASE 0xc3001000 #define CFG_PCIE2_XCFGBASE 0xc3002000 +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL + /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 6caf21b..ab7fb0a 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -74,6 +74,9 @@ #define CFG_PCIE1_XCFGBASE 0xc3001000 #define CFG_PCIE2_XCFGBASE 0xc3002000 +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL + /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE -- cgit v1.1 From 4f2e92c11f6e2392fc8187829211a5ca7f0c1e12 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 15:10:02 +0200 Subject: DTT: Prepare DS1775 driver for use of different I2C addresses Signed-off-by: Stefan Roese --- include/configs/taihu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/taihu.h b/include/configs/taihu.h index d623e56..6d204a9 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -244,6 +244,7 @@ unsigned char spi_read(void); /* standard dtt sensor configuration */ #define CONFIG_DTT_DS1775 1 #define CONFIG_DTT_SENSORS { 0 } +#define CFG_I2C_DTT_ADDR 0x49 /*----------------------------------------------------------------------- * PCI stuff -- cgit v1.1 From dbbd125721aea6645fdb962f36bd41f59e272f9d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 17:10:59 +0200 Subject: ppc4xx: Add PPC405EX support Signed-off-by: Stefan Roese --- include/405_mal.h | 4 +- include/4xx_i2c.h | 2 +- include/asm-ppc/processor.h | 4 + include/asm-ppc/u-boot.h | 1 + include/common.h | 4 +- include/ppc405.h | 675 ++++++++++++++++++++++++++++++++++++++++++-- include/ppc440.h | 2 +- include/ppc4xx_enet.h | 15 +- include/serial.h | 5 +- 9 files changed, 669 insertions(+), 43 deletions(-) (limited to 'include') diff --git a/include/405_mal.h b/include/405_mal.h index 2a42184..7ea4eb1 100644 --- a/include/405_mal.h +++ b/include/405_mal.h @@ -92,7 +92,9 @@ #define MAL_ESR_PBEI 0x00000001 /* ^^ ^^ */ /* Mal IER */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define MAL_IER_PT 0x00000080 #define MAL_IER_PRE 0x00000040 #define MAL_IER_PWE 0x00000020 diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h index 66b7997..7c79bd1 100644 --- a/include/4xx_i2c.h +++ b/include/4xx_i2c.h @@ -43,7 +43,7 @@ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS) -#elif defined(CONFIG_440) +#elif defined(CONFIG_440) || defined(CONFIG_405EX) /* all remaining 440 variants */ #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS) #else diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0a160e2..451ee94 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -765,6 +765,10 @@ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 #define PVR_405EZ_RA 0x41511460 +#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A with Security */ +#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A without Security */ +#define PVR_405EX1_RA 0x12911477 /* 405EX rev A with Security */ +#define PVR_405EX2_RA 0x12911475 /* 405EX rev A without Security */ #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_440EP_RA 0x42221850 diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 464f6b5..bd9b6f7 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -84,6 +84,7 @@ typedef struct bd_info { defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || \ defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || \ defined(CONFIG_440) unsigned char bi_s_version[4]; /* Version of this structure */ unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ diff --git a/include/common.h b/include/common.h index aca281b..9865591 100644 --- a/include/common.h +++ b/include/common.h @@ -266,7 +266,7 @@ void pciinfo (int, int); int pci_pre_init (struct pci_controller * ); #endif -#if defined(CONFIG_PCI) && defined(CONFIG_440) +#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX)) # if defined(CFG_PCI_TARGET_INIT) void pci_target_init (struct pci_controller *); # endif @@ -274,7 +274,7 @@ void pciinfo (int, int); void pci_master_init (struct pci_controller *); # endif int is_pci_host (struct pci_controller *); -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_405EX) void pcie_setup_hoses(int busno); #endif #endif diff --git a/include/ppc405.h b/include/ppc405.h index 0c7bf3e..82bc25e 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -123,6 +123,40 @@ #define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ #define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ +#if defined(CONFIG_405EX) +#define uic0sr uicsr /* UIC status */ +#define uic0srs uicsrs /* UIC status set */ +#define uic0er uicer /* UIC enable */ +#define uic0cr uiccr /* UIC critical */ +#define uic0pr uicpr /* UIC polarity */ +#define uic0tr uictr /* UIC triggering */ +#define uic0msr uicmsr /* UIC masked status */ +#define uic0vr uicvr /* UIC vector */ +#define uic0vcr uicvcr /* UIC vector configuration*/ + +#define UIC_DCR_BASE1 0xd0 +#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */ +#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */ +#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */ +#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */ +#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */ +#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */ +#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */ +#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */ +#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/ + +#define UIC_DCR_BASE2 0xe0 +#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */ +#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */ +#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */ +#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */ +#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */ +#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */ +#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */ +#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */ +#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/ +#endif + /*-----------------------------------------------------------------------------+ | Universal interrupt controller interrupts +-----------------------------------------------------------------------------*/ @@ -166,6 +200,116 @@ #define UIC_EXT3 0x00000002 /* External interrupt 3 */ #define UIC_EXT4 0x00000001 /* External interrupt 4 */ +#elif defined(CONFIG_405EX) + +/* UIC 0 */ +#define UIC_U0 0x80000000 /* */ +#define UIC_U1 0x40000000 /* */ +#define UIC_IIC0 0x20000000 /* */ +#define UIC_PKA 0x10000000 /* */ +#define UIC_TRNG 0x08000000 /* */ +#define UIC_EBM 0x04000000 /* */ +#define UIC_BGI 0x02000000 /* */ +#define UIC_IIC1 0x01000000 /* */ +#define UIC_SPI 0x00800000 /* */ +#define UIC_EIRQ0 0x00400000 /**/ +#define UIC_MTE 0x00200000 /*MAL Tx EOB */ +#define UIC_MRE 0x00100000 /*MAL Rx EOB */ +#define UIC_DMA0 0x00080000 /* */ +#define UIC_DMA1 0x00040000 /* */ +#define UIC_DMA2 0x00020000 /* */ +#define UIC_DMA3 0x00010000 /* */ +#define UIC_PCIE0AL 0x00008000 /* */ +#define UIC_PCIE0VPD 0x00004000 /* */ +#define UIC_RPCIE0HRST 0x00002000 /* */ +#define UIC_FPCIE0HRST 0x00001000 /* */ +#define UIC_PCIE0TCR 0x00000800 /* */ +#define UIC_PCIEMSI0 0x00000400 /* */ +#define UIC_PCIEMSI1 0x00000200 /* */ +#define UIC_SECURITY 0x00000100 /* */ +#define UIC_ENET 0x00000080 /* */ +#define UIC_ENET1 0x00000040 /* */ +#define UIC_PCIEMSI2 0x00000020 /* */ +#define UIC_EIRQ4 0x00000010 /**/ +#define UIC_UIC2NC 0x00000008 /* */ +#define UIC_UIC2C 0x00000004 /* */ +#define UIC_UIC1NC 0x00000002 /* */ +#define UIC_UIC1C 0x00000001 /* */ + +#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */ +#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */ +/* UIC 1 */ +#define UIC_MS 0x80000000 /* MAL SERR */ +#define UIC_MTDE 0x40000000 /* MAL TXDE */ +#define UIC_MRDE 0x20000000 /* MAL RXDE */ +#define UIC_PCIE0BMVC0 0x10000000 /* */ +#define UIC_PCIE0DCRERR 0x08000000 /* */ +#define UIC_EBC 0x04000000 /* */ +#define UIC_NDFC 0x02000000 /* */ +#define UIC_PCEI1DCRERR 0x01000000 /* */ +#define UIC_GPTCMPT8 0x00800000 /* */ +#define UIC_GPTCMPT9 0x00400000 /* */ +#define UIC_PCIE1AL 0x00200000 /* */ +#define UIC_PCIE1VPD 0x00100000 /* */ +#define UIC_RPCE1HRST 0x00080000 /* */ +#define UIC_FPCE1HRST 0x00040000 /* */ +#define UIC_PCIE1TCR 0x00020000 /* */ +#define UIC_PCIE1VC0 0x00010000 /* */ +#define UIC_GPTCMPT3 0x00008000 /* */ +#define UIC_GPTCMPT4 0x00004000 /* */ +#define UIC_EIRQ7 0x00002000 /* */ +#define UIC_EIRQ8 0x00001000 /* */ +#define UIC_EIRQ9 0x00000800 /* */ +#define UIC_GPTCMP5 0x00000400 /* */ +#define UIC_GPTCMP6 0x00000200 /* */ +#define UIC_GPTCMP7 0x00000100 /* */ +#define UIC_SROM 0x00000080 /* SERIAL ROM*/ +#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/ +#define UIC_EIRQ2 0x00000020 /* */ +#define UIC_EIRQ5 0x00000010 /* */ +#define UIC_EIRQ6 0x00000008 /* */ +#define UIC_EMAC0WAKE 0x00000004 /* */ +#define UIC_EIRQ1 0x00000002 /* */ +#define UIC_EMAC1WAKE 0x00000001 /* */ +#define UIC_MAL_SERR UIC_MS /* MAL SERR */ +#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */ +#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */ +/* UIC 2 */ +#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/ +#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/ +#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/ +#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/ +#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/ +#define UIC_DDRMCUE 0x04000000 /* */ +#define UIC_DDRMCCE 0x02000000 /* */ +#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/ +#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/ +#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/ +#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/ +#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/ +#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/ +#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/ +#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/ +#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/ +#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/ +#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/ +#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/ +#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/ +#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/ +#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/ +#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/ +#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/ +#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/ +#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/ +#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/ +#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/ +#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/ +#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/ +#define UIC_USBWAKE 0x00000002 /* USB wakup*/ +#define UIC_USBOTG 0x00000001 /* USB OTG*/ +#define UIC_ETH0 UIC_ENET +#define UIC_ETH1 UIC_ENET1 + #else /* !defined(CONFIG_405EZ) */ #define UIC_UART0 0x80000000 /* UART 0 */ @@ -256,7 +400,11 @@ /****************************************************************************** * Power Management ******************************************************************************/ +#ifdef CONFIG_405EX +#define POWERMAN_DCR_BASE 0xb0 +#else #define POWERMAN_DCR_BASE 0xb8 +#endif #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ @@ -561,16 +709,6 @@ #define VCO_MIN 500 #define VCO_MAX 1000 #elif defined(CONFIG_405EZ) -/****************************************************************************** - * SDR Registers - ******************************************************************************/ -#define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */ -#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */ - -#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) -#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) - #define sdrnand0 0x4000 #define sdrultra0 0x4040 #define sdrultra1 0x4050 @@ -1214,6 +1352,25 @@ #define GPIO1_ISR3L (GPIO1_BASE+0x40) #define GPIO1_ISR3H (GPIO1_BASE+0x44) +#elif defined(CONFIG_405EX) +#define GPIO_BASE 0xEF600800 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + #else /* !405EZ */ #define GPIO_BASE 0xEF600700 @@ -1234,33 +1391,489 @@ #endif /* CONFIG_405EZ */ -/* - * Macro for accessing the indirect EBC register - */ -#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) -#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) +#if defined(CONFIG_405EX) +#define SDR0_SRST 0x0200 + +#define SDRAM_BESR0 0x00 +#define SDRAM_BEARL 0x02 +#define SDRAM_BEARU 0x03 +#define SDRAM_WMIRQ 0x06 /**/ +#define SDRAM_PLBOPT 0x08 /**/ +#define SDRAM_PUABA 0x09 /**/ +#define SDRAM_MCSTAT 0x1F /* memory controller status */ +#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ +#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ +#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ +#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ +#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ +#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ +#define SDRAM_CODT 0x26 /* on die termination for controller */ +#define SDRAM_VVPR 0x27 /* variable VRef programmming */ +#define SDRAM_OPARS 0x28 /* on chip driver control setup */ +#define SDRAM_OPART 0x29 /* on chip driver control trigger */ +#define SDRAM_RTR 0x30 /* refresh timer */ +#define SDRAM_PMIT 0x34 /* power management idle timer */ +#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ +#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ +#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */ +#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */ +#define SDRAM_INITPLR0 0x50 /* manual initialization control */ +#define SDRAM_INITPLR1 0x51 /* manual initialization control */ +#define SDRAM_INITPLR2 0x52 /* manual initialization control */ +#define SDRAM_INITPLR3 0x53 /* manual initialization control */ +#define SDRAM_INITPLR4 0x54 /* manual initialization control */ +#define SDRAM_INITPLR5 0x55 /* manual initialization control */ +#define SDRAM_INITPLR6 0x56 /* manual initialization control */ +#define SDRAM_INITPLR7 0x57 /* manual initialization control */ +#define SDRAM_INITPLR8 0x58 /* manual initialization control */ +#define SDRAM_INITPLR9 0x59 /* manual initialization control */ +#define SDRAM_INITPLR10 0x5a /* manual initialization control */ +#define SDRAM_INITPLR11 0x5b /* manual initialization control */ +#define SDRAM_INITPLR12 0x5c /* manual initialization control */ +#define SDRAM_INITPLR13 0x5d /* manual initialization control */ +#define SDRAM_INITPLR14 0x5e /* manual initialization control */ +#define SDRAM_INITPLR15 0x5f /* manual initialization control */ +#define SDRAM_RQDC 0x70 /* read DQS delay control */ +#define SDRAM_RFDC 0x74 /* read feedback delay control */ +#define SDRAM_RDCC 0x78 /* read data capture control */ +#define SDRAM_DLCR 0x7A /* delay line calibration */ +#define SDRAM_CLKTR 0x80 /* DDR clock timing */ +#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ +#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ +#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ +#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ +#define SDRAM_MMODE 0x88 /* memory mode */ +#define SDRAM_MEMODE 0x89 /* memory extended mode */ +#define SDRAM_ECCCR 0x98 /* ECC error status */ +#define SDRAM_RID 0xF8 /* revision ID */ + +/*-----------------------------------------------------------------------------+ +| Memory Bank 0-7 configuration ++-----------------------------------------------------------------------------*/ +#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */ +#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */ +#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */ +#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */ +#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */ +#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */ +#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */ +#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */ +#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */ +#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */ +#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */ +#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Status ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ +#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ +#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ +#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ +#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Options 1 ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */ +#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ +#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ +#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ +#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ +#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) +#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ +#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ +#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ +#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ +#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ +#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ +#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ +#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ +#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ +#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ +#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ +#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ +#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ +#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ +#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ +#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ +#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ +#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ +#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ +#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ +#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ +#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ +#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ +#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ +#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ +#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ +#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Options 2 ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ +#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ +#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ +#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ +#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ +#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ +#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ +#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ +#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ +#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ +#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ +#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ +#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ + +/*-----------------------------------------------------------------------------+ +| SDRAM Refresh Timer Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RTR_RINT_MASK 0xFFF80000 +#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) +#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) + +/*-----------------------------------------------------------------------------+ +| SDRAM Read DQS Delay Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RQDC_RQDE_MASK 0x80000000 +#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 +#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 +#define SDRAM_RQDC_RQFD_MASK 0x000001FF +#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) + +#define SDRAM_RQDC_RQFD_MAX 0xFF + +/*-----------------------------------------------------------------------------+ +| SDRAM Read Data Capture Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RDCC_RDSS_MASK 0xC0000000 +#define SDRAM_RDCC_RDSS_T1 0x00000000 +#define SDRAM_RDCC_RDSS_T2 0x40000000 +#define SDRAM_RDCC_RDSS_T3 0x80000000 +#define SDRAM_RDCC_RDSS_T4 0xC0000000 +#define SDRAM_RDCC_RSAE_MASK 0x00000001 +#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 +#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Read Feedback Delay Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RFDC_ARSE_MASK 0x80000000 +#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 +#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 +#define SDRAM_RFDC_RFOS_MASK 0x007F0000 +#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define SDRAM_RFDC_RFFD_MASK 0x000003FF +#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) + +#define SDRAM_RFDC_RFFD_MAX 0x4FF + +/*-----------------------------------------------------------------------------+ +| SDRAM Delay Line Calibration Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_DLCR_DCLM_MASK 0x80000000 +#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 +#define SDRAM_DLCR_DCLM_AUTO 0x00000000 +#define SDRAM_DLCR_DLCR_MASK 0x08000000 +#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 +#define SDRAM_DLCR_DLCR_IDLE 0x00000000 +#define SDRAM_DLCR_DLCS_MASK 0x07000000 +#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 +#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 +#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 +#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 +#define SDRAM_DLCR_DLCS_ERROR 0x04000000 +#define SDRAM_DLCR_DLCV_MASK 0x000001FF +#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) +#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) + +/*-----------------------------------------------------------------------------+ +| SDRAM Controller On Die Termination Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_CODT_ODT_ON 0x80000000 +#define SDRAM_CODT_ODT_OFF 0x00000000 +#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 +#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 +#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 +#define SDRAM_CODT_DQS_MASK 0x00000010 +#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 +#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 +#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 +#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 +#define SDRAM_CODT_IO_HIZ 0x00000000 +#define SDRAM_CODT_IO_NMODE 0x00000001 + +/*-----------------------------------------------------------------------------+ +| SDRAM Mode Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_MMODE_WR_MASK 0x00000E00 +#define SDRAM_MMODE_WR_DDR1 0x00000000 +#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 +#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 +#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 +#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 +#define SDRAM_MMODE_DCL_MASK 0x00000070 +#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 +#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 +#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 + +/*-----------------------------------------------------------------------------+ +| SDRAM Extended Mode Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_MEMODE_DIC_MASK 0x00000002 +#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 +#define SDRAM_MEMODE_DIC_WEAK 0x00000002 +#define SDRAM_MEMODE_DLL_MASK 0x00000001 +#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 +#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 +#define SDRAM_MEMODE_RTT_MASK 0x00000044 +#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 +#define SDRAM_MEMODE_RTT_75OHM 0x00000004 +#define SDRAM_MEMODE_RTT_150OHM 0x00000040 +#define SDRAM_MEMODE_DQS_MASK 0x00000400 +#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 +#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Clock Timing Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 +#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 +#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Write Timing Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000 +#define SDRAM_WRDTR_LLWP_MASK 0x10000000 +#define SDRAM_WRDTR_LLWP_DIS 0x10000000 +#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 +#define SDRAM_WRDTR_WTR_MASK 0x0E000000 +#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 +#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 +#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR1 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR1_LDOF_MASK 0x80000000 +#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 +#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 +#define SDRAM_SDTR1_RTW_MASK 0x00F00000 +#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 +#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 +#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 +#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 +#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 +#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 +#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000 +#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR2 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR2_RCD_MASK 0xF0000000 +#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 +#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 +#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 +#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 +#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 +#define SDRAM_SDTR2_WTR_MASK 0x0F000000 +#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 +#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 +#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 +#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 +#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 +#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 +#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 +#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 +#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 +#define SDRAM_SDTR2_WPC_MASK 0x0000F000 +#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 +#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 +#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 +#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 +#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 +#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) +#define SDRAM_SDTR2_RPC_MASK 0x00000F00 +#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 +#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 +#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 +#define SDRAM_SDTR2_RP_MASK 0x000000F0 +#define SDRAM_SDTR2_RP_3_CLK 0x00000030 +#define SDRAM_SDTR2_RP_4_CLK 0x00000040 +#define SDRAM_SDTR2_RP_5_CLK 0x00000050 +#define SDRAM_SDTR2_RP_6_CLK 0x00000060 +#define SDRAM_SDTR2_RP_7_CLK 0x00000070 +#define SDRAM_SDTR2_RRD_MASK 0x0000000F +#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 +#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR3 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR3_RAS_MASK 0x1F000000 +#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define SDRAM_SDTR3_RC_MASK 0x001F0000 +#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define SDRAM_SDTR3_XCS_MASK 0x00001F00 +#define SDRAM_SDTR3_XCS 0x00000D00 +#define SDRAM_SDTR3_RFC_MASK 0x0000003F +#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) + +/*-----------------------------------------------------------------------------+ +| Memory Bank 0-1 configuration ++-----------------------------------------------------------------------------*/ +#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ +#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ +#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ +#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ +#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ +#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ +#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ +#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ +#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ +#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ +#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ +#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ + +#define sdr_uart0 0x0120 /* UART0 Config */ +#define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_mfr 0x4300 /* SDR0_MFR reg */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +#define cpr0_clkupd 0x020 +#define cpr0_pllc 0x040 +#define cpr0_plld 0x060 +#define cpr0_cpud 0x080 +#define cpr0_plbd 0x0a0 +#define cpr0_opbd 0x0c0 +#define cpr0_perd 0x0e0 +#define cpr0_ahbd 0x100 +#define cpr0_icfg 0x140 + +#define SDR_PINSTP 0x0040 +#define sdr_sdcs 0x0060 + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ +#endif + +/****************************************************************************** + * SDR Registers + ******************************************************************************/ +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) + +#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) + +#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) +#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) -#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) -#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) +#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) #ifndef __ASSEMBLY__ typedef struct { - unsigned long pllFwdDiv; - unsigned long pllFwdDivB; - unsigned long pllFbkDiv; - unsigned long pllPlbDiv; - unsigned long pllPciDiv; - unsigned long pllExtBusDiv; - unsigned long pllOpbDiv; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long freqProcessor; - unsigned long freqPLB; - unsigned long freqPCI; - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pciClkSync; /* PCI clock is synchronous */ - unsigned long freqVCOHz; + unsigned long pllFwdDiv; + unsigned long pllFwdDivB; + unsigned long pllFbkDiv; + unsigned long pllPlbDiv; + unsigned long pllPciDiv; + unsigned long pllExtBusDiv; + unsigned long pllOpbDiv; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long freqProcessor; + unsigned long freqPLB; + unsigned long freqPCI; + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long freqVCOHz; + unsigned long freqOPB; + unsigned long freqEBC; + unsigned long freqDDR; } PPC405_SYS_INFO; #endif /* _ASMLANGUAGE */ diff --git a/include/ppc440.h b/include/ppc440.h index 38809f3..e77c4c3 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3345,7 +3345,7 @@ typedef struct { unsigned long freqTmrClk; unsigned long freqPLB; unsigned long freqOPB; - unsigned long freqEPB; + unsigned long freqEBC; unsigned long freqPCI; #ifdef CONFIG_440SPE unsigned long freqDDR; diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 3d8ca09..76c1d12 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -146,11 +146,12 @@ typedef struct emac_4xx_hw_st { #endif #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define SDR0_PFC1_EM_1000 (0x00200000) #endif -/*ZMII Bridge Register addresses */ +/* ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) @@ -202,6 +203,8 @@ typedef struct emac_4xx_hw_st { /* RGMII Register Addresses */ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000) +#elif defined(CONFIG_405EX) +#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0xB00) #else #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790) #endif @@ -223,7 +226,8 @@ typedef struct emac_4xx_hw_st { #define RGMII_SSR_SP_100MBPS (0x02) #define RGMII_SSR_SP_1000MBPS (0x04) -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define RGMII_SSR_V(__x) ((__x) * 8) #else #define RGMII_SSR_V(__x) ((__x -2) * 8) @@ -304,7 +308,7 @@ typedef struct emac_4xx_hw_st { #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) #endif #else -#if defined(CONFIG_405EZ) +#if defined(CONFIG_405EZ) || defined(CONFIG_405EX) #define EMAC_BASE 0xEF600900 #else #define EMAC_BASE 0xEF600800 @@ -338,7 +342,8 @@ typedef struct emac_4xx_hw_st { /* on 440GX EMAC_MR1 has a different layout! */ #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) /* MODE Reg 1 */ #define EMAC_M1_FDE (0x80000000) #define EMAC_M1_ILE (0x40000000) diff --git a/include/serial.h b/include/serial.h index 30bfde3..e292f0c 100644 --- a/include/serial.h +++ b/include/serial.h @@ -22,8 +22,9 @@ extern struct serial_device serial_smc_device; extern struct serial_device serial_scc_device; extern struct serial_device * default_serial_console (void); -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ + defined(CONFIG_MPC5xxx) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CFG_NS16550_SERIAL) -- cgit v1.1 From 566806ca1a1bf4d895daaf0b2ba5494abbffebaf Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 17:11:30 +0200 Subject: ppc4xx: Add initial AMCC Kilauea 405EX support Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 486 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 486 insertions(+) create mode 100644 include/configs/kilauea.h (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h new file mode 100644 index 0000000..7858f83 --- /dev/null +++ b/include/configs/kilauea.h @@ -0,0 +1,486 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * kilauea.h - configuration for AMCC Kilauea (405EX) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_KILAUEA 1 /* Board is Kilauea */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EX 1 /* Specifc 405EX support*/ +#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFC000000 +#define CFG_NAND_ADDR 0xF8000000 +#define CFG_FPGA_BASE 0xF0000000 +#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (TEXT_BASE) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +/* reserve some memory for POST and BOOT limit info */ +#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) + +/* extra data in init-ram */ +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8) +#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12) +#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (256) /* 256MB */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ +#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ + +/* Standard DTT sensor configuration */ +#define CONFIG_DTT_DS1775 1 +#define CONFIG_DTT_SENSORS { 0 } +#define CFG_I2C_DTT_ADDR 0x48 + +/* RTC configuration */ +#define CONFIG_RTC_DS1338 1 +#define CFG_I2C_RTC_ADDR 0x68 + +/*----------------------------------------------------------------------- + * Ethernet + *----------------------------------------------------------------------*/ +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 1 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 2 + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#undef USE_LIBFDT +#ifdef USE_LIBFDT +/* + * LIBFDT support is disabled for now since first Linux port is still + * arch/ppc. + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "logversion=2\0" \ + "netdev=eth0\0" \ + "hostname=kilauea\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "net_nfs=tftp 200000 ${bootfile};" \ + "tftp ${fdt_addr} ${fdt_file};" \ + "run nfsargs addip addtty;" \ + "bootm 200000 - ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=kilauea/uImage\0" \ + "fdt_file=kilauea/kilauea.dtb\0" \ + "fdt_addr=400000\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc200000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 kilauea/u-boot.bin\0" \ + "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ + "cp.b ${fileaddr} fffa0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "nload=tftp 200000 kilauea/u-boot-nand.bin\0" \ + "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ + "setenv filesize;saveenv\0" \ + "nupd=run nload nupdate\0" \ + "" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "logversion=2\0" \ + "netdev=eth0\0" \ + "hostname=kilauea\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addtty;" \ + "bootm 200000\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=kilauea/uImage\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc200000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 kilauea/u-boot.bin\0" \ + "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ + "cp.b ${fileaddr} fffa0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "nload=tftp 200000 kilauea/u-boot-nand.bin\0" \ + "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ + "setenv filesize;saveenv\0" \ + "nupd=run nload nupdate\0" \ + "pciconfighost=1\0" \ + "" +#endif +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOG +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CACHE | \ + CFG_POST_CPU | \ + CFG_POST_ETHER | \ + CFG_POST_I2C | \ + CFG_POST_MEMORY | \ + CFG_POST_UART) + +/* Define here the base-addresses of the UARTs to test in POST */ +#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE} + +#define CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE + +/*----------------------------------------------------------------------- + * PCIe stuff + *----------------------------------------------------------------------*/ +#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */ + +#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */ +#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */ +#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */ + +#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */ +#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */ +#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */ + +#define CFG_PCIE0_UTLBASE 0xef502000 +#define CFG_PCIE1_UTLBASE 0xef503000 + +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE (16 << 10) /* For IBM 405EX */ +#define CFG_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_NAND_CS 1 /* NAND chip connected to CSx */ + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x05806500 +#define CFG_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 1 (NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x018003c0 +#define CFG_EBC_PB1CR (CFG_NAND_ADDR | 0x1e000) + +/* Memory Bank 2 (FPGA) initialization */ +#define CFG_EBC_PB2AP 0x9400C800 +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */ + +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + +/*----------------------------------------------------------------------- + * GPIO Setup + *----------------------------------------------------------------------*/ +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EX specific) + * + * GPIO0[0-3] - EBC data 0-3 inputs/outputs + * GPIO0[4-7] - USB data 4-7 inputs/outputs + * GPIO0[8-11] - NFCE# 1-3 inputs/outputs, GPIO11: IRQ6 inputs + * GPIO0[12-15] - USB data 0-3 inputs/outputs + * GPIO0[16-21] - UART0 control signal inputs/outputs + * + * GPIO0[22-25,27] - EBC control signal inputs/outputs + * GPIO0[26] - Instruction trace outputs + * GPIO0[28] - Float, N/C + * GPIO0[29-31] - DMA control signal inputs/outputs + */ +#define CFG_GPIO0_OSRL 0x00AA54AA +#define CFG_GPIO0_OSRH 0x21800000 +#define CFG_GPIO0_TSRL 0x00AA55AA +#define CFG_GPIO0_TSRH 0xA5A00000 + +#define CFG_GPIO0_ISR1L 0x00000100 +#define CFG_GPIO0_ISR1H 0x04000000 +#define CFG_GPIO0_ISR2L 0x00550055 +#define CFG_GPIO0_ISR2H 0x40100000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/*----------------------------------------------------------------------- + * Some Kilauea stuff..., mainly fpga registers + */ +#define CFG_FPGA_REG_BASE CFG_FPGA_BASE +#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 11)) + +/* interrupt */ +#define CFG_FPGA_SLIC0_R_DPRAM_INT 0x80000000 +#define CFG_FPGA_SLIC0_W_DPRAM_INT 0x40000000 +#define CFG_FPGA_SLIC1_R_DPRAM_INT 0x20000000 +#define CFG_FPGA_SLIC1_W_DPRAM_INT 0x10000000 +#define CFG_FPGA_PHY0_INT 0x08000000 +#define CFG_FPGA_PHY1_INT 0x04000000 +#define CFG_FPGA_SLIC0_INT 0x02000000 +#define CFG_FPGA_SLIC1_INT 0x01000000 + +/* DPRAM setting */ +/* 00: 32B; 01: 64B; 10: 128B; 11: 256B */ +#define CFG_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */ +#define CFG_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */ +#define CFG_FPGA_DPRAM_RW_TYPE 0x00080000 +#define CFG_FPGA_DPRAM_RST 0x00040000 +#define CFG_FPGA_UART0_FO 0x00020000 +#define CFG_FPGA_UART1_FO 0x00010000 + +/* loopback */ +#define CFG_FPGA_CHIPSIDE_LOOPBACK 0x00004000 +#define CFG_FPGA_LINESIDE_LOOPBACK 0x00008000 +#define CFG_FPGA_SLIC0_ENABLE 0x00002000 +#define CFG_FPGA_SLIC1_ENABLE 0x00001000 +#define CFG_FPGA_SLIC0_CS 0x00000800 +#define CFG_FPGA_SLIC1_CS 0x00000400 +#define CFG_FPGA_USER_LED0 0x00000200 +#define CFG_FPGA_USER_LED1 0x00000100 + +#endif /* __CONFIG_H */ + +#ifdef USE_LIBFDT +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,405EX@0" +#endif -- cgit v1.1 From db3232ddb058d0ed0bc31f7c5c296748a1afac67 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Oct 2007 21:28:58 +0200 Subject: ppc4xx: Fix small merge problems with CPCI440 and Acadia boards Signed-off-by: Stefan Roese --- include/ppc405.h | 256 ------------------------------------------------------- 1 file changed, 256 deletions(-) (limited to 'include') diff --git a/include/ppc405.h b/include/ppc405.h index 82bc25e..4d25144 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -742,10 +742,6 @@ /****************************************************************************** * Control ******************************************************************************/ -#define CNTRL_DCR_BASE 0x0C -#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */ -#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */ - /* CPR Registers */ #define cprclkupd 0x020 /* CPR_CLKUPD */ #define cprpllc 0x040 /* CPR_PLLC */ @@ -757,12 +753,6 @@ #define cprmisc0 0x181 /* CPR_MISC0 */ #define cprmisc1 0x182 /* CPR_MISC1 */ -/* - * Macro for accessing the indirect CPR register - */ -#define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0) -#define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0) - #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ @@ -783,252 +773,6 @@ #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ -#if 0 /* Deprecated */ -#define CNTRL_DCR_BASE 0x0f0 -#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ - -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - -/* Bit definitions */ -#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ -#define PLLMR0_CPU_DIV_BYPASS 0x00000000 -#define PLLMR0_CPU_DIV_2 0x00100000 -#define PLLMR0_CPU_DIV_3 0x00200000 -#define PLLMR0_CPU_DIV_4 0x00300000 - -#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ -#define PLLMR0_CPU_PLB_DIV_1 0x00000000 -#define PLLMR0_CPU_PLB_DIV_2 0x00010000 -#define PLLMR0_CPU_PLB_DIV_3 0x00020000 -#define PLLMR0_CPU_PLB_DIV_4 0x00030000 - -#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ -#define PLLMR0_OPB_PLB_DIV_1 0x00000000 -#define PLLMR0_OPB_PLB_DIV_2 0x00001000 -#define PLLMR0_OPB_PLB_DIV_3 0x00002000 -#define PLLMR0_OPB_PLB_DIV_4 0x00003000 - -#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ -#define PLLMR0_EXB_PLB_DIV_2 0x00000000 -#define PLLMR0_EXB_PLB_DIV_3 0x00000100 -#define PLLMR0_EXB_PLB_DIV_4 0x00000200 -#define PLLMR0_EXB_PLB_DIV_5 0x00000300 - -#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ -#define PLLMR0_MAL_PLB_DIV_1 0x00000000 -#define PLLMR0_MAL_PLB_DIV_2 0x00000010 -#define PLLMR0_MAL_PLB_DIV_3 0x00000020 -#define PLLMR0_MAL_PLB_DIV_4 0x00000030 - -#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ -#define PLLMR0_PCI_PLB_DIV_1 0x00000000 -#define PLLMR0_PCI_PLB_DIV_2 0x00000001 -#define PLLMR0_PCI_PLB_DIV_3 0x00000002 -#define PLLMR0_PCI_PLB_DIV_4 0x00000003 - -#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ -#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ -#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ -#define PLLMR1_FBMUL_DIV_16 0x00000000 -#define PLLMR1_FBMUL_DIV_1 0x00100000 -#define PLLMR1_FBMUL_DIV_2 0x00200000 -#define PLLMR1_FBMUL_DIV_3 0x00300000 -#define PLLMR1_FBMUL_DIV_4 0x00400000 -#define PLLMR1_FBMUL_DIV_5 0x00500000 -#define PLLMR1_FBMUL_DIV_6 0x00600000 -#define PLLMR1_FBMUL_DIV_7 0x00700000 -#define PLLMR1_FBMUL_DIV_8 0x00800000 -#define PLLMR1_FBMUL_DIV_9 0x00900000 -#define PLLMR1_FBMUL_DIV_10 0x00A00000 -#define PLLMR1_FBMUL_DIV_11 0x00B00000 -#define PLLMR1_FBMUL_DIV_12 0x00C00000 -#define PLLMR1_FBMUL_DIV_13 0x00D00000 -#define PLLMR1_FBMUL_DIV_14 0x00E00000 -#define PLLMR1_FBMUL_DIV_15 0x00F00000 - -#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ -#define PLLMR1_FWDVA_DIV_8 0x00000000 -#define PLLMR1_FWDVA_DIV_7 0x00010000 -#define PLLMR1_FWDVA_DIV_6 0x00020000 -#define PLLMR1_FWDVA_DIV_5 0x00030000 -#define PLLMR1_FWDVA_DIV_4 0x00040000 -#define PLLMR1_FWDVA_DIV_3 0x00050000 -#define PLLMR1_FWDVA_DIV_2 0x00060000 -#define PLLMR1_FWDVA_DIV_1 0x00070000 -#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ -#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ - -/* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 - -/* Defines for CPC0_BOOR Register */ -#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -/* - *------------------------------------------------------------------------------- - * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, - * assuming a 33.3MHz input clock to the 405EP. - *------------------------------------------------------------------------------- - */ -#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -/* - * PLL Voltage Controlled Oscillator (VCO) definitions - * Maximum and minimum values (in MHz) for correct PLL operation. - */ -#define VCO_MIN 500 -#define VCO_MAX 1000 -#endif /* #if 0 */ #else /* #ifdef CONFIG_405EP */ /****************************************************************************** * Control -- cgit v1.1 From fd671802b67a0ef37a06124fa2ce85f00aa22c6f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 11 Oct 2007 11:15:59 +0200 Subject: ppc4xx: Enable device tree support (fdt) on Kilauea per default This patch enables the fdt support on the AMCC Kilauea eval board. Additionally now EBC ranges fdt fixup is included to support NOR FLASH mapping via the Linux physmap_of driver. This Kilauea port now support booting arch/ppc and arch/powerpc Linux kernels. The default environment "net_nfs" is for arch/ppc and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc support will be removed. Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 46 +++------------------------------------------- 1 file changed, 3 insertions(+), 43 deletions(-) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 7858f83..461f8f0 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -166,12 +166,6 @@ #undef CONFIG_BOOTARGS -#undef USE_LIBFDT -#ifdef USE_LIBFDT -/* - * LIBFDT support is disabled for now since first Linux port is still - * arch/ppc. - */ #define CONFIG_EXTRA_ENV_SETTINGS \ "logversion=2\0" \ "netdev=eth0\0" \ @@ -184,6 +178,9 @@ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addtty;" \ + "bootm 200000\0" \ + "net_nfs_fdt=tftp 200000 ${bootfile};" \ "tftp ${fdt_addr} ${fdt_file};" \ "run nfsargs addip addtty;" \ "bootm 200000 - ${fdt_addr}\0" \ @@ -207,43 +204,8 @@ "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ "setenv filesize;saveenv\0" \ "nupd=run nload nupdate\0" \ - "" -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "logversion=2\0" \ - "netdev=eth0\0" \ - "hostname=kilauea\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addtty;" \ - "bootm 200000\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=kilauea/uImage\0" \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc200000\0" \ - "initrd_high=30000000\0" \ - "load=tftp 200000 kilauea/u-boot.bin\0" \ - "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ - "cp.b ${fileaddr} fffa0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "nload=tftp 200000 kilauea/u-boot-nand.bin\0" \ - "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ - "setenv filesize;saveenv\0" \ - "nupd=run nload nupdate\0" \ "pciconfighost=1\0" \ "" -#endif #define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -477,10 +439,8 @@ #endif /* __CONFIG_H */ -#ifdef USE_LIBFDT /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #define OF_CPU "PowerPC,405EX@0" -#endif -- cgit v1.1 From d4cb2d17946466740afeb195a57d6cb290bf4cc0 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 13 Oct 2007 16:43:23 +0200 Subject: ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri Signed-off-by: Stefan Roese --- include/asm-ppc/4xx_pcie.h | 52 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/katmai.h | 1 + include/configs/kilauea.h | 1 + include/configs/yucca.h | 1 + 4 files changed, 55 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 17ac57b..1830c6a 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -244,6 +244,9 @@ #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) +/* + * Prototypes + */ int ppc4xx_init_pcie(void); int ppc4xx_init_pcie_rootport(int port); int ppc4xx_init_pcie_endport(int port); @@ -251,6 +254,55 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port); int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port); int pcie_hose_scan(struct pci_controller *hose, int bus); +/* + * Function to determine root port or endport from env variable. + */ +static inline int is_end_point(int port) +{ + static char s[10], *tk; + + strcpy(s, getenv("pcie_mode")); + tk = strtok(s, ":"); + + switch (port) { + case 0: + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + + case 1: + tk = strtok(NULL, ":"); + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + + case 2: + tk = strtok(NULL, ":"); + if (tk != NULL) + tk = strtok(NULL, ":"); + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + } + + return 0; +} + static inline void mdelay(int n) { u32 ms = n; diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 8a96327..cccfc13 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -205,6 +205,7 @@ "upd=run load;run update\0" \ "kozio=bootm ffc60000\0" \ "pciconfighost=1\0" \ + "pcie_mode=RP:RP:RP\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 461f8f0..f5e2023 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -205,6 +205,7 @@ "setenv filesize;saveenv\0" \ "nupd=run nload nupdate\0" \ "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/yucca.h b/include/configs/yucca.h index ab7fb0a..2b4024d 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -186,6 +186,7 @@ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "pciconfighost=1\0" \ + "pcie_mode=RP:EP:EP\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" -- cgit v1.1 From 5cb4af4791f61843432155142b6cfac901f66c10 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 18 Oct 2007 07:39:38 +0200 Subject: ppc4xx: Add PCIe endpoint support on Kilauea (405EX) This patch adds endpoint support for the AMCC Kilauea eval board. It can be tested by connecting a reworked PCIe cable (only 1x lane singles connected) to another root-complex. In this test setup, a 64MB inbound window is configured at BAR0 which maps to 0 on the PLB side. So accessing this BAR0 from the root-complex will access the first 64MB of the SDRAM on the PPC side. Signed-off-by: Stefan Roese --- include/asm-ppc/4xx_pcie.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 1830c6a..ffe0770 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -218,7 +218,8 @@ #define PECFG_BAR0LMPA 0x210 #define PECFG_BAR0HMPA 0x214 #define PECFG_BAR1MPA 0x218 -#define PECFG_BAR2MPA 0x220 +#define PECFG_BAR2LMPA 0x220 +#define PECFG_BAR2HMPA 0x224 #define PECFG_PIMEN 0x33c #define PECFG_PIM0LAL 0x340 @@ -259,9 +260,13 @@ int pcie_hose_scan(struct pci_controller *hose, int bus); */ static inline int is_end_point(int port) { - static char s[10], *tk; + char s[10], *tk; + char *pcie_mode = getenv("pcie_mode"); - strcpy(s, getenv("pcie_mode")); + if (pcie_mode == NULL) + return 0; + + strcpy(s, pcie_mode); tk = strtok(s, ":"); switch (port) { -- cgit v1.1 From c36c68160333ac5fe41ec3db12a728b7075b3912 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 18 Oct 2007 07:42:27 +0200 Subject: ppc4xx: Change inbound PCIe location for endpoint tests on Katmai On Yucca & Katmai, the inbound memory map pointed to 0x4.0000.0000, which is the internal SRAM. Since I now ported and tested this endpoint mode on Kilauea successfully to map to 0 (SDRAM), I also changed this for Katmai. Yucca will stay at internal SRAM for now. Not sure if somebody relies on this setup. Signed-off-by: Stefan Roese --- include/configs/katmai.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index cccfc13..6bc8d02 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -73,7 +73,7 @@ #define CFG_PCIE2_XCFGBASE 0xc3002000 /* base address of inbound PCIe window */ -#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL +#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -- cgit v1.1 From f6ba9b56607d4b27550301c7c7f6b55b654fd62a Mon Sep 17 00:00:00 2001 From: Eugene O'Brien Date: Thu, 18 Oct 2007 17:29:04 +0200 Subject: ppc4xx: Define CONFIG_BOOKE for all PPC440 based processors CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR number is used to access system registers. Signed-off-by: Eugene O'Brien Signed-off-by: Stefan Roese --- include/asm-ppc/processor.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 451ee94..f58b38a 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -91,6 +91,11 @@ /* Special Purpose Registers (SPRNs)*/ +/* PPC440 Architecture is BOOK-E */ +#ifdef CONFIG_440 +#define CONFIG_BOOKE +#endif + #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ -- cgit v1.1 From 087dfdb79b5fd1ab99a26990c62a732c01a8c7f6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 21 Oct 2007 08:12:41 +0200 Subject: ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese --- include/common.h | 4 +-- include/ppc405.h | 58 ------------------------------------- include/ppc440.h | 87 -------------------------------------------------------- include/ppc4xx.h | 73 +++++++++++++++++++++++++++++++++++++++++++++-- 4 files changed, 71 insertions(+), 151 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 9865591..46ed6bd 100644 --- a/include/common.h +++ b/include/common.h @@ -513,15 +513,13 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) # if defined(CONFIG_440) - typedef PPC440_SYS_INFO sys_info_t; # if defined(CONFIG_440SPE) unsigned long determine_sysper(void); unsigned long determine_pci_clock_per(void); int ppc440spe_revB(void); # endif -# else - typedef PPC405_SYS_INFO sys_info_t; # endif +typedef PPC4xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); #endif diff --git a/include/ppc405.h b/include/ppc405.h index 4d25144..97528e8 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -344,9 +344,6 @@ /****************************************************************************** * SDRAM Controller ******************************************************************************/ -#define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ -#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ /* values for memcfga register - indirect addressing of these regs */ #ifndef CONFIG_405EP #define mem_besra 0x00 /* bus error syndrome reg a */ @@ -412,9 +409,6 @@ /****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ -#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ /* values for ebccfga register - indirect addressing of these regs */ #define pb0cr 0x00 /* periph bank 0 config reg */ #define pb1cr 0x01 /* periph bank 1 config reg */ @@ -1574,56 +1568,4 @@ #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ #endif -/****************************************************************************** - * SDR Registers - ******************************************************************************/ -#define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) - -#define CPR0_DCR_BASE 0x0C -#define cprcfga (CPR0_DCR_BASE+0x0) -#define cprcfgd (CPR0_DCR_BASE+0x1) - -#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) -#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) - -#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) -#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) - -#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) -#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) - -#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) -#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) - -#ifndef __ASSEMBLY__ - -typedef struct -{ - unsigned long pllFwdDiv; - unsigned long pllFwdDivB; - unsigned long pllFbkDiv; - unsigned long pllPlbDiv; - unsigned long pllPciDiv; - unsigned long pllExtBusDiv; - unsigned long pllOpbDiv; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long freqProcessor; - unsigned long freqPLB; - unsigned long freqPCI; - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pciClkSync; /* PCI clock is synchronous */ - unsigned long freqVCOHz; - unsigned long freqOPB; - unsigned long freqEBC; - unsigned long freqDDR; -} PPC405_SYS_INFO; - -#endif /* _ASMLANGUAGE */ - -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache - line aligned data. */ - #endif /* __PPC405_H__ */ diff --git a/include/ppc440.h b/include/ppc440.h index e77c4c3..dc5eb98 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -123,10 +123,6 @@ /*----------------------------------------------------------------------------- | Clocking Controller +----------------------------------------------------------------------------*/ -#define CLOCKING_DCR_BASE 0x0c -#define clkcfga (CLOCKING_DCR_BASE+0x0) -#define clkcfgd (CLOCKING_DCR_BASE+0x1) - /* values for clkcfga register - indirect addressing of these regs */ #define clk_clkukpd 0x0020 #define clk_pllc 0x0040 @@ -140,9 +136,6 @@ #define clk_icfg 0x0140 /* 440gx sdr register definations */ -#define SDR_DCR_BASE 0x0e -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) #define sdr_sdstp0 0x0020 /* */ #define sdr_sdstp1 0x0021 /* */ #define SDR_PINSTP 0x0040 @@ -242,10 +235,6 @@ /*----------------------------------------------------------------------------- | SDRAM Controller +----------------------------------------------------------------------------*/ -#define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ -#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ - /* values for memcfga register - indirect addressing of these regs */ #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ @@ -331,9 +320,6 @@ #define sdr_sdstp6 0x4005 #define sdr_sdstp7 0x4007 -#define SDR0_CFGADDR 0x00E -#define SDR0_CFGDATA 0x00F - /****************************************************************************** * PCI express defines ******************************************************************************/ @@ -480,10 +466,6 @@ /*----------------------------------------------------------------------------+ | Memory controller defines +----------------------------------------------------------------------------*/ -#define SDRAMC_DCR_BASE 0x010 -#define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */ -#define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */ - /* A REVOIR versus specs 4 bank - SG*/ #define SDRAM_MCSTAT 0x14 /* memory controller status */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ @@ -834,9 +816,6 @@ /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ -#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ /* values for ebccfga register - indirect addressing of these regs */ #define pb0cr 0x00 /* periph bank 0 config reg */ #define pb1cr 0x01 /* periph bank 1 config reg */ @@ -2207,9 +2186,6 @@ #define SDR0_CP440_NTO1_NTO1 0x00000002 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) -#define SDR0_CFGADDR 0x00E /*already defined line 277 */ -#define SDR0_CFGDATA 0x00F - #define SDR0_SDSTP0 0x0020 #define SDR0_SDSTP0_ENG_MASK 0x80000000 @@ -3289,71 +3265,8 @@ #define GPIO1_ISR3H (GPIO1_BASE+0x44) #endif -/* - * Macros for accessing the indirect EBC registers - */ -#define mtebc(reg, data) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } while (0) -#define mfebc(reg, data) do { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } while (0) - -/* - * Macros for accessing the indirect SDRAM controller registers - */ -#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) -#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) - -/* - * Macros for accessing the indirect clocking controller registers - */ -#define mtclk(reg, data) do { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } while (0) -#define mfclk(reg, data) do { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } while (0) - -/* - * Macros for accessing the sdr controller registers - */ -#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) -#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) - -/* - * All 44x except 440GP have CPR registers (indirect DCR) - */ -#if !defined(CONFIG_440GP) -#define CPR0_CFGADDR 0x00C -#define CPR0_CFGDATA 0x00D - -#define mtcpr(reg, data) do { \ - mtdcr(CPR0_CFGADDR, reg); \ - mtdcr(CPR0_CFGDATA, data); \ - } while (0) - -#define mfcpr(reg, data) do { \ - mtdcr(CPR0_CFGADDR, reg); \ - data = mfdcr(CPR0_CFGDATA); \ - } while (0) -#endif - #ifndef __ASSEMBLY__ -typedef struct { - unsigned long pllFwdDivA; - unsigned long pllFwdDivB; - unsigned long pllFbkDiv; - unsigned long pllOpbDiv; - unsigned long pllPciDiv; - unsigned long pllExtBusDiv; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long freqProcessor; - unsigned long freqTmrClk; - unsigned long freqPLB; - unsigned long freqOPB; - unsigned long freqEBC; - unsigned long freqPCI; -#ifdef CONFIG_440SPE - unsigned long freqDDR; -#endif - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pciClkSync; /* PCI clock is synchronous */ -} PPC440_SYS_INFO; - static inline u32 get_mcsr(void) { u32 val; diff --git a/include/ppc4xx.h b/include/ppc4xx.h index ca241d2..76fe872 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -22,13 +22,80 @@ #ifndef __PPC4XX_H__ #define __PPC4XX_H__ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) - #if defined(CONFIG_440) #include #else #include #endif +/* + * Common stuff for 4xx (405 and 440) + */ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) + +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache + line aligned data. */ + +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define SDRAM_DCR_BASE 0x10 +#define memcfga (SDRAM_DCR_BASE+0x0) +#define memcfgd (SDRAM_DCR_BASE+0x1) + +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) + +/* + * Macros for indirect DCR access + */ +#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) + +#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) +#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) + +#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) + +#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqDDR; + unsigned long freqEBC; + unsigned long freqOPB; + unsigned long freqPCI; + unsigned long freqPLB; + unsigned long freqTmrClk; + unsigned long freqUART; + unsigned long freqProcessor; + unsigned long freqVCOHz; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pllExtBusDiv; + unsigned long pllFbkDiv; + unsigned long pllFwdDiv; + unsigned long pllFwdDivA; + unsigned long pllFwdDivB; + unsigned long pllOpbDiv; + unsigned long pllPciDiv; + unsigned long pllPlbDiv; +} PPC4xx_SYS_INFO; + +#endif /* __ASSEMBLY__ */ + #endif /* __PPC4XX_H__ */ -- cgit v1.1 From 758c037aeead34b49631b8da3a90b1bba14c0410 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 21 Oct 2007 08:16:12 +0200 Subject: rtc: Add Xicor/Intersil X1205 RTC support This patch adds support for the Xicor/Intersil X1205 RTC used on the AMCC Makalu eval board. This driver is basically cloned from the Linux driver version (2.6.23). This patch also introduces the Linux bcd.h header for the BCD2BIN/ BIN2BCD conversions. In the future some of the other U-Boot RTC driver should be converted to also use this header instead of implementing their own local copy of these functions/macros. Signed-off-by: Stefan Roese --- include/bcd.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 include/bcd.h (limited to 'include') diff --git a/include/bcd.h b/include/bcd.h new file mode 100644 index 0000000..c545308 --- /dev/null +++ b/include/bcd.h @@ -0,0 +1,20 @@ +/* Permission is hereby granted to copy, modify and redistribute this code + * in terms of the GNU Library General Public License, Version 2 or later, + * at your option. + */ + +/* macros to translate to/from binary and binary-coded decimal (frequently + * found in RTC chips). + */ + +#ifndef _BCD_H +#define _BCD_H + +#define BCD2BIN(val) (((val) & 0x0f) + ((val)>>4)*10) +#define BIN2BCD(val) ((((val)/10)<<4) + (val)%10) + +/* backwards compat */ +#define BCD_TO_BIN(val) ((val)=BCD2BIN(val)) +#define BIN_TO_BCD(val) ((val)=BIN2BCD(val)) + +#endif /* _BCD_H */ -- cgit v1.1 From 837c730b4d7c6b1ddf3d1e247cb4445005d9bf0d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 21 Oct 2007 14:26:29 +0200 Subject: ppc: Small Kilauea cleanup of config file Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index f5e2023..74c9483 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -438,10 +438,10 @@ #define CFG_FPGA_USER_LED0 0x00000200 #define CFG_FPGA_USER_LED1 0x00000100 -#endif /* __CONFIG_H */ - /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #define OF_CPU "PowerPC,405EX@0" + +#endif /* __CONFIG_H */ -- cgit v1.1 From 211ea91ac6c225bec7e668a03d0ba7d7310679fa Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 22 Oct 2007 07:34:34 +0200 Subject: ppc4xx: Add initial AMCC Makalu 405EX support Signed-off-by: Stefan Roese --- include/configs/makalu.h | 387 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 387 insertions(+) create mode 100644 include/configs/makalu.h (limited to 'include') diff --git a/include/configs/makalu.h b/include/configs/makalu.h new file mode 100644 index 0000000..6c4d0b6 --- /dev/null +++ b/include/configs/makalu.h @@ -0,0 +1,387 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * makalu.h - configuration for AMCC Makalu (405EX) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_MAKALU 1 /* Board is Makalu */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EX 1 /* Specifc 405EX support*/ +#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FPGA_BASE 0xF0000000 +#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (TEXT_BASE) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +/* reserve some memory for POST and BOOT limit info */ +#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) + +/* extra data in init-ram */ +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8) +#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12) +#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* no ext. clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM 128 + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ +#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ + +/* Standard DTT sensor configuration */ +#define CONFIG_DTT_DS1775 1 +#define CONFIG_DTT_SENSORS { 0 } +#define CFG_I2C_DTT_ADDR 0x48 + +/* RTC configuration */ +#define CONFIG_RTC_X1205 1 +#define CFG_I2C_RTC_ADDR 0x6f + +/*----------------------------------------------------------------------- + * Ethernet + *----------------------------------------------------------------------*/ +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 1 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 2 + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "logversion=2\0" \ + "netdev=eth0\0" \ + "hostname=makalu\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm 200000\0" \ + "net_nfs_fdt=tftp 200000 ${bootfile};" \ + "tftp ${fdt_addr} ${fdt_file};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm 200000 - ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=makalu/uImage\0" \ + "fdt_file=makalu/makalu.dtb\0" \ + "fdt_addr=400000\0" \ + "kernel_addr=fe000000\0" \ + "ramdisk_addr=fe200000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 makalu/u-boot.bin\0" \ + "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ + "cp.b ${fileaddr} fffa0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOG +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CACHE | \ + CFG_POST_CPU | \ + CFG_POST_ETHER | \ + CFG_POST_I2C | \ + CFG_POST_MEMORY | \ + CFG_POST_UART) + +/* Define here the base-addresses of the UARTs to test in POST */ +#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE} + +#define CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE + +/*----------------------------------------------------------------------- + * PCIe stuff + *----------------------------------------------------------------------*/ +#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */ + +#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */ +#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */ +#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */ + +#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */ +#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */ +#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */ + +#define CFG_PCIE0_UTLBASE 0xef502000 +#define CFG_PCIE1_UTLBASE 0xef503000 + +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE (16 << 10) /* For IBM 405EX */ +#define CFG_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x04011000 +#define CFG_EBC_PB0CR 0xFE0BA000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x9400C800 +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */ + +/*----------------------------------------------------------------------- + * GPIO Setup + *----------------------------------------------------------------------*/ +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EX specific) + * + * GPIO0[0-3] - EBC data 0-3 inputs/outputs + * GPIO0[4-7] - USB data 4-7 inputs/outputs + * GPIO0[8-11] - NFCE# 1-3 inputs/outputs, GPIO11: IRQ6 inputs + * GPIO0[12-15] - USB data 0-3 inputs/outputs + * GPIO0[16-21] - UART0 control signal inputs/outputs + * + * GPIO0[22-25,27] - EBC control signal inputs/outputs + * GPIO0[26] - Instruction trace outputs + * GPIO0[28] - Float, N/C + * GPIO0[29-31] - DMA control signal inputs/outputs + */ +#define CFG_GPIO0_OSRL 0x00AA54AA +#define CFG_GPIO0_OSRH 0x55500000 +#define CFG_GPIO0_TSRL 0x00AA54AA +#define CFG_GPIO0_TSRH 0x55500000 +#define CFG_GPIO0_ISR1L 0x00005400 +#define CFG_GPIO0_ISR1H 0x55500000 +#define CFG_GPIO0_ISR2L 0x00550055 +#define CFG_GPIO0_ISR2H 0x00000000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,405EX@0" + +#endif /* __CONFIG_H */ -- cgit v1.1 From afe9fa59cb63b4f9d16bf01c93eb212f25a38c2a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 22 Oct 2007 16:24:44 +0200 Subject: ppc4xx: Add SNTP support to AMCC Katmai, Kilauea & Makalu boards Signed-off-by: Stefan Roese --- include/configs/katmai.h | 2 +- include/configs/kilauea.h | 1 + include/configs/makalu.h | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 6bc8d02..5da00fc 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -247,7 +247,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM - +#define CONFIG_CMD_SNTP #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 74c9483..90bdd69 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -244,6 +244,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP /* POST support */ #define CONFIG_POST (CFG_POST_MEMORY | \ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 6c4d0b6..3e3b008 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -234,6 +234,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP /* POST support */ #define CONFIG_POST (CFG_POST_MEMORY | \ -- cgit v1.1 From 353f2688b4e0fc7b969bc70a02be4b40bf0dd124 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 23 Oct 2007 10:10:08 +0200 Subject: ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board support The Haleakala is nearly identical with the Kilauea eval board. The only difference is that the 405EXr only supports one EMAC and one PCIe interface. This patch adds support for the Haleakala board by using the identical image for Kilauea and Haleakala. The distinction is done by comparing the PVR. Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 90bdd69..9a9f7ba 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -38,6 +38,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_EMAC_COUNT /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the -- cgit v1.1 From f10493c6d77a1e07a6c2ff4d772937a5e7359d6a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 23 Oct 2007 11:31:05 +0200 Subject: ppc4xx: Correct UART input clock calculation and passing to fdt We now use a value in the gd (global data) structure for the UART input frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely in get_sys_info(). Signed-off-by: Stefan Roese --- include/asm-ppc/global_data.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 4676e2c..05aee74 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -107,6 +107,9 @@ typedef struct global_data { unsigned int dp_alloc_base; unsigned int dp_alloc_top; #endif +#if defined(CONFIG_4xx) + u32 uart_clk; +#endif /* CONFIG_4xx */ #if defined(CFG_GT_6426x) unsigned int mirror_hack[16]; #endif -- cgit v1.1 From 9b94ac61d2176185c30adf0793e079ec30e68687 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 31 Oct 2007 17:55:58 +0100 Subject: ppc4xx: Rework 4xx cache support New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese --- include/asm-ppc/cache.h | 21 ++++++++++++++++----- include/ppc405.h | 6 ++++++ include/ppc440.h | 6 ++---- 3 files changed, 24 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 5befab4..e29bfc2 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -8,15 +8,24 @@ #include /* bytes per L1 cache line */ -#if !defined(CONFIG_8xx) || defined(CONFIG_8260) +#if !(defined(CONFIG_8xx) || defined(CONFIG_IOP480)) #if defined(CONFIG_PPC64BRIDGE) -#define L1_CACHE_BYTES 128 +#define L1_CACHE_SHIFT 7 #else -#define L1_CACHE_BYTES 32 +#define L1_CACHE_SHIFT 5 #endif /* PPC64 */ #else -#define L1_CACHE_BYTES 16 -#endif /* !8xx || 8260 */ +#define L1_CACHE_SHIFT 4 +#endif /* !(8xx || IOP480) */ + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +/* + * For compatibility reasons support the CFG_CACHELINE_SIZE too + */ +#ifndef CFG_CACHELINE_SIZE +#define CFG_CACHELINE_SIZE L1_CACHE_BYTES +#endif #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define L1_CACHE_PAGES 8 @@ -35,6 +44,8 @@ extern void flush_dcache_range(unsigned long start, unsigned long stop); extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); +extern void flush_dcache(void); +extern void invalidate_dcache(void); #ifdef CFG_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); #endif /* CFG_INIT_RAM_LOCK */ diff --git a/include/ppc405.h b/include/ppc405.h index 97528e8..2c55917 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -22,6 +22,12 @@ #ifndef __PPC405_H__ #define __PPC405_H__ +#ifndef CONFIG_IOP480 +#define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ +#else +#define CFG_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */ +#endif + /*--------------------------------------------------------------------- */ /* Special Purpose Registers */ /*--------------------------------------------------------------------- */ diff --git a/include/ppc440.h b/include/ppc440.h index dc5eb98..2f841fa 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -22,6 +22,8 @@ #ifndef __PPC440_H__ #define __PPC440_H__ +#define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ + /*--------------------------------------------------------------------- */ /* Special Purpose Registers */ /*--------------------------------------------------------------------- */ @@ -3282,8 +3284,4 @@ static inline void set_mcsr(u32 val) #endif /* _ASMLANGUAGE */ -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */ - /* cache line aligned data. */ - #endif /* __PPC440_H__ */ -- cgit v1.1 From d25dfe08fbd1220cb994e7e6b105049aa9aa8e79 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 31 Oct 2007 17:57:52 +0100 Subject: ppc4xx: Remove cache definition from 4xx board config files All 4xx board config files don't need the cache definitions anymore. These are now defined in common headers. Signed-off-by: Stefan Roese --- include/configs/ADCIOP.h | 9 --------- include/configs/AP1000.h | 8 -------- include/configs/AR405.h | 10 ---------- include/configs/ASH405.h | 10 ---------- include/configs/CANBT.h | 9 --------- include/configs/CMS700.h | 10 ---------- include/configs/CPCI2DP.h | 10 ---------- include/configs/CPCI405.h | 9 --------- include/configs/CPCI4052.h | 10 ---------- include/configs/CPCI405AB.h | 10 ---------- include/configs/CPCI405DT.h | 10 ---------- include/configs/CPCI440.h | 9 --------- include/configs/CPCIISER4.h | 9 --------- include/configs/CRAYL1.h | 6 ------ include/configs/DASA_SIM.h | 9 --------- include/configs/DP405.h | 10 ---------- include/configs/DU405.h | 9 --------- include/configs/ERIC.h | 8 -------- include/configs/EXBITGEN.h | 4 ---- include/configs/G2000.h | 10 ---------- include/configs/HH405.h | 10 ---------- include/configs/HUB405.h | 10 ---------- include/configs/JSE.h | 9 --------- include/configs/KAREF.h | 8 -------- include/configs/METROBOX.h | 8 -------- include/configs/MIP405.h | 9 --------- include/configs/ML2.h | 8 -------- include/configs/OCRTC.h | 9 --------- include/configs/ORSG.h | 9 --------- include/configs/PCI405.h | 9 --------- include/configs/PIP405.h | 9 --------- include/configs/PLU405.h | 10 ---------- include/configs/PMC405.h | 10 ---------- include/configs/PPChameleonEVB.h | 10 ---------- include/configs/VOH405.h | 10 ---------- include/configs/VOM405.h | 10 ---------- include/configs/W7OLMC.h | 9 --------- include/configs/W7OLMG.h | 9 --------- include/configs/WUH405.h | 10 ---------- include/configs/XPEDITE1K.h | 8 -------- include/configs/acadia.h | 9 --------- include/configs/alpr.h | 6 ------ include/configs/bamboo.h | 9 --------- include/configs/bubinga.h | 8 -------- include/configs/csb272.h | 8 -------- include/configs/csb472.h | 8 -------- include/configs/ebony.h | 8 -------- include/configs/hcu4.h | 7 ------- include/configs/hcu5.h | 7 ------- include/configs/katmai.h | 8 -------- include/configs/kilauea.h | 9 --------- include/configs/luan.h | 9 --------- include/configs/lwmon5.h | 9 --------- include/configs/makalu.h | 9 --------- include/configs/ml300.h | 6 ------ include/configs/ocotea.h | 8 -------- include/configs/p3p440.h | 8 -------- include/configs/pcs440ep.h | 9 --------- include/configs/sbc405.h | 10 ---------- include/configs/sc3.h | 18 ------------------ include/configs/sequoia.h | 17 ++++++++--------- include/configs/taihu.h | 7 ------- include/configs/taishan.h | 9 --------- include/configs/walnut.h | 10 ---------- include/configs/yosemite.h | 9 --------- include/configs/yucca.h | 8 -------- include/configs/zeus.h | 7 ------- 67 files changed, 8 insertions(+), 595 deletions(-) (limited to 'include') diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h index 4632991..5d28168 100644 --- a/include/configs/ADCIOP.h +++ b/include/configs/ADCIOP.h @@ -191,15 +191,6 @@ #define CFG_ETH_DEV_FN 0x0000 #define CFG_ETH_IOBASE 0x0fff0000 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ -#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h index d25aa74..d490b33 100644 --- a/include/configs/AP1000.h +++ b/include/configs/AP1000.h @@ -193,14 +193,6 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Init Memory Controller: diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 0f301ec..50f09b0 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -213,16 +213,6 @@ #define CFG_ENV_ADDR_REDUND 0xFFFA0000 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 9adbba9..85c6a99 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -258,16 +258,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index ae32f6b..7029dbd 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -181,15 +181,6 @@ /* mask of address bits that overflow into the "EEPROM chip address" */ #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 21cd9c1..285cd5c 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -273,16 +273,6 @@ #define CFG_EEPROM_WREN 1 /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ #define CFG_PLD_BASE 0xf0000000 diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index a3717b9..58900c3 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -223,16 +223,6 @@ #define CFG_EEPROM_WREN 1 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 1b948f6..bd43e1d 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -266,15 +266,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index fb71c5f..b248639 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -317,16 +317,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 4994319..1e9597d 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -288,16 +288,6 @@ #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ #define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 29f9292..a8029ea 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -319,16 +319,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h index 318ada1..eb47cd7 100644 --- a/include/configs/CPCI440.h +++ b/include/configs/CPCI440.h @@ -262,15 +262,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* Configuration Port location */ #define CONFIG_PORT_ADDR 0xF0000500 diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index c7b623a..78b754c 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -205,15 +205,6 @@ #define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ /* total size of a CAT24WC08 is 1024 bytes */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index a965c12..2356858 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -192,12 +192,6 @@ #define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE) /* END ENVIRONNEMENT FLASH */ -/*----------------------------------------------------------------------- - * Cache Configuration. Only used to ..?? clear it, I guess.. - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 - /* * Init Memory Controller: * diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h index 627ea14..117a136 100644 --- a/include/configs/DASA_SIM.h +++ b/include/configs/DASA_SIM.h @@ -182,15 +182,6 @@ #define CFG_PCI9054_DEV_FN 0x0800 #define CFG_PCI9054_IOBASE 0x0eff0000 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ -#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 2eadbea..912fb2a 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -242,16 +242,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/DU405.h b/include/configs/DU405.h index 5c595f5..c8bf67f 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -232,15 +232,6 @@ #define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ /* total size of a CAT24WC08 is 1024 bytes */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 5d48d2b..dc15b0c 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -323,14 +323,6 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Init Memory Controller: diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h index a3f38bb..251227c 100644 --- a/include/configs/EXBITGEN.h +++ b/include/configs/EXBITGEN.h @@ -205,10 +205,6 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -/* Cache configuration */ -#define CFG_DCACHE_SIZE 8192 -#define CFG_CACHELINE_SIZE 32 - /* * Internal Definitions * diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 9c713c6..c12ce48 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -331,16 +331,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 8967b3f..18e5b3c 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -363,16 +363,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 1ff7108..a389d58 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -257,16 +257,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/JSE.h b/include/configs/JSE.h index ea3b0b4..5b40ef6 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -279,15 +279,6 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 3644e43..816e63b 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -281,14 +281,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ -#endif /* * Internal Definitions diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 8d7ec59..d61b49e 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -346,14 +346,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ -#endif /* * Internal Definitions diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 5b526a0..9ddf82b 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -258,15 +258,6 @@ */ /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * Logbuffer Configuration */ #undef CONFIG_LOGBUFFER /* supported but not enabled */ diff --git a/include/configs/ML2.h b/include/configs/ML2.h index f488275..66dae21 100644 --- a/include/configs/ML2.h +++ b/include/configs/ML2.h @@ -201,14 +201,6 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Init Memory Controller: diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 5840ea2..94b5bc9 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -222,15 +222,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 937df22..4e03088 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -220,15 +220,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index d6e7082..e70c0d3 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -251,15 +251,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index efa0157..b83520d 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -231,15 +231,6 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 652210c..6b16654 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -300,16 +300,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index b29f368..adbe8a9 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -270,16 +270,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ #define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 8a74c4f..c2aa2cc 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -454,16 +454,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 14848ab..3a413f5 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -306,16 +306,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 5512f4b..ec6f205 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -248,16 +248,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index fc177fb..7017fff 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -290,15 +290,6 @@ */ #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ -#endif - /* * Init Memory Controller: */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 20d693f..bfb3156 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -293,15 +293,6 @@ */ #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ -#endif - /* * Init Memory Controller: */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 656784a..582d8cf 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -254,16 +254,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 611f5a6..38ea576 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -257,14 +257,6 @@ extern void out32(unsigned int, unsigned long); * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/acadia.h b/include/configs/acadia.h index e3f6e2c..dc322dd 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -385,15 +385,6 @@ #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) diff --git a/include/configs/alpr.h b/include/configs/alpr.h index d88c3ad..aff9823 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -355,12 +355,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ /* * Internal Definitions diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 14c5638..d577448 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -414,15 +414,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 7736a1e..eca195a 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -321,14 +321,6 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Init Memory Controller: diff --git a/include/configs/csb272.h b/include/configs/csb272.h index c43b497..a24478d 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -290,14 +290,6 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /* - * Cache configuration - * - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 - -/* * Miscellaneous board specific definitions * */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index a7120aa..064650c 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -289,14 +289,6 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /* - * Cache configuration - * - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 - -/* * Miscellaneous board specific definitions * */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 2c626a0..5faa9eb 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -293,14 +293,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 577f459..b43b228 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -321,13 +321,6 @@ #define CONFIG_PORT_ADDR 0xF0000500 -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ - /* * Internal Definitions * diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 9085881..1214bc3 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -364,13 +364,6 @@ #define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 ) #define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 ) -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ - /* * Internal Definitions * diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 5da00fc..2eed941 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -431,14 +431,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 9a9f7ba..caf8b52 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -330,15 +330,6 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE (16 << 10) /* For IBM 405EX */ -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ #define CFG_NAND_CS 1 /* NAND chip connected to CSx */ diff --git a/include/configs/luan.h b/include/configs/luan.h index a09dd74..cba7295 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -293,15 +293,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 52deab4..3180617 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -487,15 +487,6 @@ } \ } -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 3e3b008..3070779 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -319,15 +319,6 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE (16 << 10) /* For IBM 405EX */ -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ /* Memory Bank 0 (NOR-FLASH) initialization */ diff --git a/include/configs/ml300.h b/include/configs/ml300.h index 0183041..1945918 100644 --- a/include/configs/ml300.h +++ b/include/configs/ml300.h @@ -160,12 +160,6 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ - -/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index bc2fd33..fd4d3af 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -317,14 +317,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 51f19a1..255e072 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -311,14 +311,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 7653ba1..d467338 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -438,15 +438,6 @@ } \ } -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index dc906b1..60d401f 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -234,16 +234,6 @@ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ #define FLASH0_BA CFG_FLASH_BASE /* FLASH 0 Base Address */ diff --git a/include/configs/sc3.h b/include/configs/sc3.h index cb22536..0a03c0e 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -433,24 +433,6 @@ extern unsigned long offsetOfEnvironment; #define CONFIG_JFFS2_PART_SIZE 0x01000000 #define CONFIG_JFFS2_PART_OFFSET 0x00000000 -/*----------------------------------------------------------------------- - * Cache Configuration - * - * CFG_DCACHE_SIZE -> size of data cache: - * - 405GP 8k - * - 405GPr 16k - * How to handle the difference in chache size? - * CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes - * (used in cpu/ppc4xx/start.S) -*/ -#define CFG_DCACHE_SIZE 16384 - -#define CFG_CACHELINE_SIZE 32 - -#if defined(CONFIG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 600f98c..72f01d9 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -43,6 +43,14 @@ #define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \ 33333333 : 33000000) +#if 0 +/* + * 44x dcache supported is working now on sequoia, but we don't enable + * it yet since it needs further testing + */ +#define CONFIG_4xx_DCACHE /* enable dcache */ +#endif + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -460,15 +468,6 @@ #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/taihu.h b/include/configs/taihu.h index 6d204a9..c51468b 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -366,13 +366,6 @@ unsigned char spi_read(void); } \ } -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ -#define CFG_CACHELINE_SIZE 32 -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ - /* * Init Memory Controller: * diff --git a/include/configs/taishan.h b/include/configs/taishan.h index baa4fbd..ab3b0c1 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -319,15 +319,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 180549e..19b29e7 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -290,16 +290,6 @@ #endif /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 35bce4a..2dde9be 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -361,15 +361,6 @@ #define CFG_BCSR5_PCI66EN 0x80 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 2b4024d..db1d35b 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -324,14 +324,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 605755a..810a528 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -237,13 +237,6 @@ #endif /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ - -/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ /* use on chip memory (OCM) for temperary stack until sdram is tested */ -- cgit v1.1 From 483e09a223c666269ef81d3573a6591b1046b0ef Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 31 Oct 2007 17:59:22 +0100 Subject: ppc4xx: Add change_tlb function to modify I attribute of TLB(s) This function is used to either turn cache on or off in a specific memory area. Signed-off-by: Stefan Roese --- include/asm-ppc/mmu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index b3cfa9b..edcb3b9 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -648,6 +648,7 @@ unsigned long mftlb3(unsigned long index); void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void remove_tlb(u32 vaddr, u32 size); +void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_440 */ -- cgit v1.1 From ff768cb168d8157c24a25016dbfbeb465e47f420 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 31 Oct 2007 18:01:24 +0100 Subject: ppc4xx: Change 4xx ethernet driver to handle cached memory too This patch enables the 4xx EMAC driver to work too, when dcache is enabled. Signed-off-by: Stefan Roese --- include/ppc4xx_enet.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 76c1d12..f285500 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -102,6 +102,8 @@ typedef struct emac_4xx_hw_st { uint32_t emac_ier; volatile mal_desc_t *tx; volatile mal_desc_t *rx; + u32 tx_phys; + u32 rx_phys; bd_t *bis; /* for eth_init upon mal error */ mal_desc_t *alloc_tx_buf; mal_desc_t *alloc_rx_buf; -- cgit v1.1 From 3d6cb3b24add6415f86a0f013ea40f5639b90047 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 3 Nov 2007 12:08:28 +0100 Subject: ppc4xx: Add AMCC Kilauea/Haleakala NAND booting support This patch adds NAND booting support for the AMCC 405EX(r) eval boards. Again, only one image supports both targets. Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 88 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 79 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index caf8b52..07f7eff 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -50,7 +50,7 @@ #define CFG_FPGA_BASE 0xF0000000 #define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ #define CFG_MONITOR_BASE (TEXT_BASE) /*----------------------------------------------------------------------- @@ -117,6 +117,71 @@ #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif /* CFG_ENV_IS_IN_FLASH */ +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 4k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 4kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + * On 440EPx the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from cache, I experienced problems accessing + * the NAND controller. sr - 2006-08-25 + */ +#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ +#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ +#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ +#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ +#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ + +/* + * Now the NAND chip has to be defined (no autodetection used!) + */ +#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ +#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ + +#define CFG_NAND_ECCSIZE 256 +#define CFG_NAND_ECCBYTES 3 +#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) +#define CFG_NAND_OOBSIZE 16 +#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) +#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} + +#ifdef CFG_ENV_IS_IN_NAND +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/sequoia/u-boot-nand.lds for details. + */ +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ @@ -332,6 +397,18 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +/* booting from NAND, so NAND chips select has to be on CS 0 */ +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ + +/* Memory Bank 1 (NOR-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x05806500 +#define CFG_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 0 (NAND-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x018003c0 +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1e000) +#else #define CFG_NAND_CS 1 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ @@ -341,6 +418,7 @@ /* Memory Bank 1 (NAND-FLASH) initialization */ #define CFG_EBC_PB1AP 0x018003c0 #define CFG_EBC_PB1CR (CFG_NAND_ADDR | 0x1e000) +#endif /* Memory Bank 2 (FPGA) initialization */ #define CFG_EBC_PB2AP 0x9400C800 @@ -349,14 +427,6 @@ #define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */ /*----------------------------------------------------------------------- - * NAND FLASH - *----------------------------------------------------------------------*/ -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) -#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ - -/*----------------------------------------------------------------------- * GPIO Setup *----------------------------------------------------------------------*/ /*----------------------------------------------------------------------- -- cgit v1.1 From 298035df4948b113d29ac0e694717d34b95bc5dc Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Wed, 31 Oct 2007 11:21:29 -0500 Subject: NET: Cosmetic changes Signed-off-by: Larry Johnson Signed-off-by: Ben Warren --- include/miiphy.h | 92 ++++++++++++++++++++++++++------------------------------ 1 file changed, 42 insertions(+), 50 deletions(-) (limited to 'include') diff --git a/include/miiphy.h b/include/miiphy.h index 71716b0..42f2ad0 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -26,56 +26,48 @@ | | Author: Mark Wisner | -| Change Activity- -| -| Date Description of Change BY -| --------- --------------------- --- -| 04-May-99 Created MKW -| 07-Jul-99 Added full duplex support MKW -| 08-Sep-01 Tweaks gvb -| +----------------------------------------------------------------------------*/ #ifndef _miiphy_h_ #define _miiphy_h_ #include -int miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value); -int miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value); -int miiphy_info(char *devname, unsigned char addr, unsigned int *oui, - unsigned char *model, unsigned char *rev); -int miiphy_reset(char *devname, unsigned char addr); -int miiphy_speed(char *devname, unsigned char addr); -int miiphy_duplex(char *devname, unsigned char addr); +int miiphy_read (char *devname, unsigned char addr, unsigned char reg, + unsigned short *value); +int miiphy_write (char *devname, unsigned char addr, unsigned char reg, + unsigned short value); +int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, + unsigned char *model, unsigned char *rev); +int miiphy_reset (char *devname, unsigned char addr); +int miiphy_speed (char *devname, unsigned char addr); +int miiphy_duplex (char *devname, unsigned char addr); #ifdef CFG_FAULT_ECHO_LINK_DOWN -int miiphy_link(char *devname, unsigned char addr); +int miiphy_link (char *devname, unsigned char addr); #endif -void miiphy_init(void); +void miiphy_init (void); -void miiphy_register(char *devname, - int (* read)(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value), - int (* write)(char *devname, unsigned char addr, - unsigned char reg, unsigned short value)); +void miiphy_register (char *devname, + int (*read) (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value), + int (*write) (char *devname, unsigned char addr, + unsigned char reg, unsigned short value)); -int miiphy_set_current_dev(char *devname); -char *miiphy_get_current_dev(void); +int miiphy_set_current_dev (char *devname); +char *miiphy_get_current_dev (void); -void miiphy_listdev(void); +void miiphy_listdev (void); #define BB_MII_DEVNAME "bbmii" int bb_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); + unsigned char reg, unsigned short *value); int bb_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value); + unsigned char reg, unsigned short value); /* phy seed setup */ #define AUTO 99 -#define _1000BASET 1000 +#define _1000BASET 1000 #define _100BASET 100 #define _10BASET 10 #define HALF 22 @@ -90,9 +82,9 @@ int bb_miiphy_write (char *devname, unsigned char addr, #define PHY_ANLPAR 0x05 #define PHY_ANER 0x06 #define PHY_ANNPTR 0x07 -#define PHY_ANLPNP 0x08 -#define PHY_1000BTCR 0x09 -#define PHY_1000BTSR 0x0A +#define PHY_ANLPNP 0x08 +#define PHY_1000BTCR 0x09 +#define PHY_1000BTSR 0x0A #define PHY_PHYSTS 0x10 #define PHY_MIPSCR 0x11 #define PHY_MIPGSR 0x12 @@ -115,10 +107,10 @@ int bb_miiphy_write (char *devname, unsigned char addr, #define PHY_BMCR_DPLX 0x0100 #define PHY_BMCR_COL_TST 0x0080 -#define PHY_BMCR_SPEED_MASK 0x2040 -#define PHY_BMCR_1000_MBPS 0x0040 -#define PHY_BMCR_100_MBPS 0x2000 -#define PHY_BMCR_10_MBPS 0x0000 +#define PHY_BMCR_SPEED_MASK 0x2040 +#define PHY_BMCR_1000_MBPS 0x0040 +#define PHY_BMCR_100_MBPS 0x2000 +#define PHY_BMCR_10_MBPS 0x0000 /* phy BMSR */ #define PHY_BMSR_100T4 0x8000 @@ -143,18 +135,18 @@ int bb_miiphy_write (char *devname, unsigned char addr, #define PHY_ANLPAR_TX 0x0080 #define PHY_ANLPAR_10FD 0x0040 #define PHY_ANLPAR_10 0x0020 -#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ - -#define PHY_ANLPAR_PSB_MASK 0x001f -#define PHY_ANLPAR_PSB_802_3 0x0001 -#define PHY_ANLPAR_PSB_802_9 0x0002 - -/* PHY_1000BTSR */ -#define PHY_1000BTSR_MSCF 0x8000 -#define PHY_1000BTSR_MSCR 0x4000 -#define PHY_1000BTSR_LRS 0x2000 -#define PHY_1000BTSR_RRS 0x1000 -#define PHY_1000BTSR_1000FD 0x0800 -#define PHY_1000BTSR_1000HD 0x0400 +#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ + +#define PHY_ANLPAR_PSB_MASK 0x001f +#define PHY_ANLPAR_PSB_802_3 0x0001 +#define PHY_ANLPAR_PSB_802_9 0x0002 + +/* phy 1000BTSR */ +#define PHY_1000BTSR_MSCF 0x8000 +#define PHY_1000BTSR_MSCR 0x4000 +#define PHY_1000BTSR_LRS 0x2000 +#define PHY_1000BTSR_RRS 0x1000 +#define PHY_1000BTSR_1000FD 0x0800 +#define PHY_1000BTSR_1000HD 0x0400 #endif -- cgit v1.1 From 71bc6e6474fea8ef481b9b45d1edd7ad1f6dfbbd Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Thu, 1 Nov 2007 08:46:50 -0500 Subject: NET: Add Ethernet 1000BASE-X support for PPC4xx This patch adds support for 1000BASE-X to functions "miiphy_speed ()" and "miiphy_duplex()". It also adds function "miiphy_is_1000base_x ()", which returns non-zero iff the PHY registers are configured for 1000BASE-X. The "mii info" command is modified to distinguish between 1000BASE-T and -X. Signed-off-by: Larry Johnson Signed-off-by: Ben Warren --- include/miiphy.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include') diff --git a/include/miiphy.h b/include/miiphy.h index 42f2ad0..5518a0a 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -41,6 +41,7 @@ int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, int miiphy_reset (char *devname, unsigned char addr); int miiphy_speed (char *devname, unsigned char addr); int miiphy_duplex (char *devname, unsigned char addr); +int miiphy_is_1000base_x (char *devname, unsigned char addr); #ifdef CFG_FAULT_ECHO_LINK_DOWN int miiphy_link (char *devname, unsigned char addr); #endif @@ -85,6 +86,7 @@ int bb_miiphy_write (char *devname, unsigned char addr, #define PHY_ANLPNP 0x08 #define PHY_1000BTCR 0x09 #define PHY_1000BTSR 0x0A +#define PHY_EXSR 0x0F #define PHY_PHYSTS 0x10 #define PHY_MIPSCR 0x11 #define PHY_MIPGSR 0x12 @@ -118,6 +120,7 @@ int bb_miiphy_write (char *devname, unsigned char addr, #define PHY_BMSR_100TXH 0x2000 #define PHY_BMSR_10TF 0x1000 #define PHY_BMSR_10TH 0x0800 +#define PHY_BMSR_EXT_STAT 0x0100 #define PHY_BMSR_PRE_SUP 0x0040 #define PHY_BMSR_AUTN_COMP 0x0020 #define PHY_BMSR_RF 0x0010 @@ -130,17 +133,30 @@ int bb_miiphy_write (char *devname, unsigned char addr, #define PHY_ANLPAR_NP 0x8000 #define PHY_ANLPAR_ACK 0x4000 #define PHY_ANLPAR_RF 0x2000 +#define PHY_ANLPAR_ASYMP 0x0800 +#define PHY_ANLPAR_PAUSE 0x0400 #define PHY_ANLPAR_T4 0x0200 #define PHY_ANLPAR_TXFD 0x0100 #define PHY_ANLPAR_TX 0x0080 #define PHY_ANLPAR_10FD 0x0040 #define PHY_ANLPAR_10 0x0020 #define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ +/* phy ANLPAR 1000BASE-X */ +#define PHY_X_ANLPAR_NP 0x8000 +#define PHY_X_ANLPAR_ACK 0x4000 +#define PHY_X_ANLPAR_RF_MASK 0x3000 +#define PHY_X_ANLPAR_PAUSE_MASK 0x0180 +#define PHY_X_ANLPAR_HD 0x0040 +#define PHY_X_ANLPAR_FD 0x0020 #define PHY_ANLPAR_PSB_MASK 0x001f #define PHY_ANLPAR_PSB_802_3 0x0001 #define PHY_ANLPAR_PSB_802_9 0x0002 +/* phy 1000BTCR */ +#define PHY_1000BTCR_1000FD 0x0200 +#define PHY_1000BTCR_1000HD 0x0100 + /* phy 1000BTSR */ #define PHY_1000BTSR_MSCF 0x8000 #define PHY_1000BTSR_MSCR 0x4000 @@ -149,4 +165,10 @@ int bb_miiphy_write (char *devname, unsigned char addr, #define PHY_1000BTSR_1000FD 0x0800 #define PHY_1000BTSR_1000HD 0x0400 +/* phy EXSR */ +#define PHY_EXSR_1000XF 0x8000 +#define PHY_EXSR_1000XH 0x4000 +#define PHY_EXSR_1000TF 0x2000 +#define PHY_EXSR_1000TH 0x1000 + #endif -- cgit v1.1 From 9f23ca334a6f5f021ef9e9d0fad9da80d63b2d56 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Mon, 29 Oct 2007 19:26:21 +0800 Subject: Unify pixis_reset altbank across board families Basically, refactor the CFG_PIXIS_VBOOT_MASK values into the separate board config files. Signed-off-by: Jason Jin Signed-off-by: Jon Loeliger --- include/configs/MPC8544DS.h | 1 + include/configs/MPC8641HPCN.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index f580cca..13e2a2c 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -198,6 +198,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ /* define to use L1 as initial stack */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index aa6dbc4..6f87240 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -201,6 +201,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -- cgit v1.1 From f3bceaab230b4748d0afc4109b6837308f018b40 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 26 Oct 2007 18:31:59 +0800 Subject: Fix the BAT definition of PCI IO on 8610 board The address in the BAT register is aligned with the BAT size. The original definition actually did not define BAT for PCIE2 IO. This patch fix this. Signed-off-by: Jason Jin --- include/configs/MPC8610HPCD.h | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index be3434a..8bbe447 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -361,28 +361,26 @@ #define CFG_IBAT1U CFG_DBAT1U /* - * BAT2 32M Cache-inhibited, guarded + * BAT2 16M Cache-inhibited, guarded * 0xe100_0000 1M PCI-1 I/O - * 0xe200_0000 1M PCI-Express 2 I/O - * */ #define CFG_DBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP) #define CFG_IBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U /* - * BAT3 1M Cache-inhibited, guarded + * BAT3 32M Cache-inhibited, guarded + * 0xe200_0000 1M PCI-Express 2 I/O * 0xe300_0000 1M PCI-Express 1 I/O - * */ -#define CFG_DBAT3L (CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ +#define CFG_DBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U (CFG_PCIE1_IO_PHYS | BATU_BL_1M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT3U (CFG_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT3U CFG_DBAT3U /* -- cgit v1.1 From 761421ccca80a9fb37b19c37aa61d46ef75e0647 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Mon, 29 Oct 2007 19:26:21 +0800 Subject: 8610: Actually enable pixis_reset CONFIGs Signed-off-by: Jason Jin --- include/configs/MPC8610HPCD.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 8bbe447..8b6b117 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -151,6 +151,7 @@ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ +#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ @@ -166,6 +167,7 @@ #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define CFG_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ -- cgit v1.1 From 1815338fbd1c0f94f8276d2891b99caa5a05f622 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 29 Oct 2007 13:57:53 -0500 Subject: 8610: Make some extra debug environment variables conditional. One may #define ENV_DEBUG to get them back again. Signed-off-by: York Sun --- include/configs/MPC8610HPCD.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 8b6b117..9fa42f3 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -587,7 +587,7 @@ "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" - +#ifdef ENV_DEBUG #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ @@ -632,6 +632,17 @@ PCI_ENV \ PCIE_ENV \ DMA_ENV +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ + "dtbaddr=c00000\0" \ + "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0" \ + "bdev=sda3\0" +#endif #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ -- cgit v1.1 From a877880c6949e948bd63cd6ea4e216573d2f53dd Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 29 Oct 2007 13:58:39 -0500 Subject: 8610: Add 8610 DIU display driver 1280x1024 and 1024x768 @ 32 bpp are supported now. DVI, Single-link LVDS, Double-link LVDS are all supported. Environmental variable "monitor" is used to specify monitor port. A new command "diufb" is introduced to reinitialize monitor and display a BMP file in the memory. So far, 1-bit, 4-bit, 8-bit and 24-bit BMP formats are supported. diufb init - initialize the diu driver Enable the port specified in the environmental variable "monitor" diufb addr - display bmp file in memory. The bmp image should be no bigger than the resolution, 1280x1024 for DVI and double-link LVDS, 1024x768 for single-link LVDS. Note, this driver allocate memory but doesn't free it after use It is written on purpose -- to avoid a failure of reallocation due to memory fragement. ECC of DDR is disabled for DIU performance. L2 data cache is also disabled. Signed-off-by: York Sun Signed-off-by: Jon loeliger --- include/configs/MPC8610HPCD.h | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 9fa42f3..00c94ef 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -21,6 +21,7 @@ #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ #ifdef RUN_DIAG #define CFG_DIAG_ADDR 0xff800000 #endif @@ -38,7 +39,7 @@ #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ #undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_NUM_DDR_CONTROLLERS 1 @@ -51,13 +52,14 @@ */ #define CFG_L2 #define L2_INIT 0 -#define L2_ENABLE (L2CR_L2E) +#define L2_ENABLE (L2CR_L2E |0x00100000 ) #ifndef CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_R 1 #undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ @@ -159,6 +161,7 @@ #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ #define PIXIS_VCTL 0x10 /* VELA Control Register */ #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ @@ -208,7 +211,7 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -474,6 +477,9 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ +/*DIU Configuration*/ +#define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ + /* * Miscellaneous configurable options */ @@ -621,7 +627,8 @@ "diuregs=md e002c000 1d\0" \ "dium=mw e002c01c\0" \ "diuerr=md e002c014 1\0" \ - "othbootargs=debug\0" \ + "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ + "monitor=0-DVI\0" \ "pmregs=md e00e1000 2b\0" \ "lawregs=md e0000c08 4b\0" \ "lbcregs=md e0005000 36\0" \ @@ -641,7 +648,9 @@ "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ "dtbaddr=c00000\0" \ "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0" \ - "bdev=sda3\0" + "bdev=sda3\0" \ + "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ + "monitor=0-DVI\0" #endif #define CONFIG_NFSBOOTCOMMAND \ -- cgit v1.1 From 070ba56115b4da63b46e974287fa4550d4023386 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 31 Oct 2007 14:59:04 -0500 Subject: 8610: Add console frame buffer support to FSL 8610 DIU driver. Add cfb console support to FSL 8610 DIU driver. Inspect board version from PIXIS to obtain correct pixel format. Use #define CONFIG_VIDEO in config file to enable fb console. To switch monitor, set monitor variable to 0 - DVI, 1 - Single link LVDS, 2 - Double link LVDS followed by "diufb init". Preserve logo bitmap at the top of the fb console. Signed-off-by: York Sun Signed-off-by: Jon Loeliger --- include/configs/MPC8610HPCD.h | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 00c94ef..f5d9c09 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -22,6 +22,15 @@ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ + +/* video */ +#undef CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif + #ifdef RUN_DIAG #define CFG_DIAG_ADDR 0xff800000 #endif @@ -314,15 +323,17 @@ #define CONFIG_EEPRO100 #define CONFIG_TULIP -#if 0 /* TODO */ /************************************************************ * USB support ************************************************************/ -#define CONFIG_USB_OHCI 1 +#define CONFIG_PCI_OHCI 1 +#define CONFIG_USB_OHCI_NEW 1 #define CONFIG_USB_KEYBOARD 1 #define CFG_DEVICE_DEREGISTER -#define CFG_USB_INTERRUPT_POLL 1 -#endif +#define CFG_USB_EVENT_POLL 1 +#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 +#define CFG_OHCI_SWAP_REG_ACCESS 1 #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 @@ -472,6 +483,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_SCSI #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_USB #endif -- cgit v1.1 From 248c7c14835f34d5d910b45e5600050e58ca6cab Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 7 Nov 2007 17:56:15 -0600 Subject: ColdFire: MCF532x - Update do_reset() using core reset Signed-off-by: TsiChungLiew --- include/asm-m68k/immap_5329.h | 3 ++- include/asm-m68k/m5329.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) mode change 100644 => 100755 include/asm-m68k/m5329.h (limited to 'include') diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h index 2a3980c..dd86e7d 100644 --- a/include/asm-m68k/immap_5329.h +++ b/include/asm-m68k/immap_5329.h @@ -57,7 +57,8 @@ #define MMAP_PWM 0xFC090000 #define MMAP_EPORT 0xFC094000 #define MMAP_WDOG 0xFC098000 -#define MMAP_CCM 0xFC0A0000 +#define MMAP_RCM 0xFC0A0000 +#define MMAP_CCM 0xFC0A0004 #define MMAP_GPIO 0xFC0A4000 #define MMAP_RTC 0xFC0A8000 #define MMAP_LCDC 0xFC0AC000 diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h old mode 100644 new mode 100755 index cd69fb0..3f05651 --- a/include/asm-m68k/m5329.h +++ b/include/asm-m68k/m5329.h @@ -246,6 +246,21 @@ #define CSCR_BSTW (0x00000008) /********************************************************************* +* Reset Controller Module (RCM) +*********************************************************************/ + +/* Bit definitions and macros for RCR */ +#define RCM_RCR_FRCRSTOUT (0x40) +#define RCM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for RSR */ +#define RCM_RSR_LOL (0x01) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_SOFT (0x20) + +/********************************************************************* * FlexCAN Module (CAN) *********************************************************************/ /* Bit definitions and macros for CAN_CANMCR */ -- cgit v1.1 From 225a24b5e062ad94627424508ae814f51dbe1a34 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 7 Nov 2007 18:00:54 -0600 Subject: ColdFire: MCF5445x - Update correct RAMBAR and missing linker files Signed-off-by: TsiChungLiew --- include/asm-m68k/m5445x.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h index 8b886b0..b2bfb69 100644 --- a/include/asm-m68k/m5445x.h +++ b/include/asm-m68k/m5445x.h @@ -792,8 +792,8 @@ #define GPIO_PAR_FEC_FEC0_MASK (0xF8) #define GPIO_PAR_FEC_FEC0_MII (0x07) #define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) -#define GPIO_PAR_FEC_FEC0_RMII_ATA (0x02) -#define GPIO_PAR_FEC_FEC0_ATA (0x01) +#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) +#define GPIO_PAR_FEC_FEC0_ULPI (0x01) #define GPIO_PAR_FEC_FEC0_GPIO (0x00) /* Bit definitions and macros for PAR_DMA */ -- cgit v1.1 From 09b26cf00d76d75fdf7fdc4b13e4dd929743bc21 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 8 Nov 2007 12:19:01 -0600 Subject: ColdFire: MCF5329 - revert include/asm-m68k/m5329.h file mode Signed-off-by: TsiChungLiew --- include/asm-m68k/m5329.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 include/asm-m68k/m5329.h (limited to 'include') diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h old mode 100755 new mode 100644 -- cgit v1.1 From 7d7cdea769a60b0a6e4c18bef7f9d648fd14b8d7 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 8 Nov 2007 12:31:11 -0600 Subject: ColdFire: MCF5329 - Add Reset structure to immap_5329.h Signed-off-by: TsiChungLiew --- include/asm-m68k/immap_5329.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h index dd86e7d..60ecd42 100644 --- a/include/asm-m68k/immap_5329.h +++ b/include/asm-m68k/immap_5329.h @@ -494,6 +494,11 @@ typedef struct ccm_ctrl { u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */ } ccm_t; +typedef struct rcm { + u8 rcr; + u8 rsr; +} rcm_t; + /* GPIO port registers */ typedef struct gpio_ctrl { /* Port Output Data Registers */ -- cgit v1.1 From 8d737a28152ec12873f8544cca1fb39a49e5e693 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 8 Nov 2007 12:50:18 -0600 Subject: ColdFire: MCF5329 - Remove reset registers from CCM Signed-off-by: TsiChungLiew --- include/asm-m68k/immap_5329.h | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h index 60ecd42..271c276 100644 --- a/include/asm-m68k/immap_5329.h +++ b/include/asm-m68k/immap_5329.h @@ -480,18 +480,15 @@ typedef struct wdog_ctrl { /*Chip configuration module registers */ typedef struct ccm_ctrl { - u8 rstctrl; /* 0x00 Reset Controller register */ - u8 rststat; /* 0x01 Reset Status register */ - u16 res1; /* 0x02 - 0x03 */ - u16 ccr; /* 0x04 Chip configuration register */ - u16 res2; /* 0x06 */ - u16 rcon; /* 0x08 Rreset configuration register */ - u16 cir; /* 0x0A Chip identification register */ - u32 res3; /* 0x0C */ - u16 misccr; /* 0x10 Miscellaneous control register */ - u16 cdr; /* 0x12 Clock divider register */ - u16 uhcsr; /* 0x14 USB Host controller status register */ - u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */ + u16 ccr; /* 0x00 Chip configuration register */ + u16 res2; /* 0x02 */ + u16 rcon; /* 0x04 Rreset configuration register */ + u16 cir; /* 0x06 Chip identification register */ + u32 res3; /* 0x08 */ + u16 misccr; /* 0x0A Miscellaneous control register */ + u16 cdr; /* 0x0C Clock divider register */ + u16 uhcsr; /* 0x10 USB Host controller status register */ + u16 uocsr; /* 0x12 USB On-the-Go Controller Status Reg */ } ccm_t; typedef struct rcm { -- cgit v1.1 From b53313dbfc74525d85f1e7e0102f902d5c863beb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 9 Nov 2007 12:19:58 +0100 Subject: ppc4xx: Remove In:/Out:/Err: boot output for AMCC Kilauea Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 07f7eff..ddd064a 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -358,6 +358,7 @@ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ /*----------------------------------------------------------------------- * PCI stuff -- cgit v1.1 From 2d14684341109a69616e4d6016cd61402d55086f Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 9 Nov 2007 15:37:53 +0100 Subject: ppc4xx: Use generic usb-ohci driver for sequoia board This patch makes the sequoia board use the generic usb-ohci driver instead of cpu/ppc4xx/usb_ohci.c. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 72f01d9..2af675a 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -301,8 +301,15 @@ /* USB */ #ifdef CONFIG_440EPX -#define CONFIG_USB_OHCI +#define CONFIG_USB_OHCI_NEW #define CONFIG_USB_STORAGE +#define CFG_OHCI_BE_CONTROLLER + +#undef CFG_USB_OHCI_BOARD_INIT +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST +#define CFG_USB_OHCI_SLOT_NAME "ppc440" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 /* Comment this out to enable USB 1.1 device */ #define USB_2_0_DEVICE -- cgit v1.1 From 1d8a49eca1c7bdc8db1c47a92f9014a29ead03ae Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Thu, 13 Sep 2007 18:52:28 +0800 Subject: Enable ULi1575 Ethernet support in 8610HPCD config Signed-off-by: Roy Zang Acked-by: Jon Loeliger --- include/configs/MPC8610HPCD.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index f5d9c09..ef1310f 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -312,16 +312,16 @@ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_NET_MULTI +#define CONFIG_CMD_NET #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#if 0 /* TODO */ -/* enable onboard uli network support */ -#endif - #define CONFIG_RTL8139 #define CONFIG_SK98 #define CONFIG_EEPRO100 #define CONFIG_TULIP +#ifdef CONFIG_TULIP +#define CONFIG_ETHADDR 00:E0:0C:00:00:01 +#endif /************************************************************ * USB support -- cgit v1.1 From 8ada0ebf38e4073beea0309188b25d82a112a2ae Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 15 Nov 2007 14:20:08 +0100 Subject: ppc4xx: AMCC Taihu board config file cleanup This patch makes the AMCC Taihu a little more compatible to the other AMCC eval boards. Signed-off-by: Stefan Roese --- include/configs/taihu.h | 44 +++++--------------------------------------- 1 file changed, 5 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/include/configs/taihu.h b/include/configs/taihu.h index c51468b..d012c60 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -80,6 +80,7 @@ "bootfile=/tftpboot/taihu/uImage\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "netdev=eth0\0" \ + "hostname=taihu\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -210,10 +211,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ /*----------------------------------------------------------------------- * I2C stuff @@ -328,7 +331,7 @@ unsigned char spi_read(void); /*----------------------------------------------------------------------- * PPC405 GPIO Configuration */ -#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \ +#define CFG_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ { \ /* GPIO Core 0 */ \ { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \ @@ -415,43 +418,6 @@ unsigned char spi_read(void); #define CFG_EBC_PB4AP 0x158FF600 #define CFG_EBC_PB4CR 0x5021A000 -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */ -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */ -#define CFG_GPIO0_ISR1L 0x15545440 -#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */ -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */ -#define CFG_GPIO0_ODR 0x00000000 /* open drain */ - -#define GPIO0 0 /* GPIO controller 0 */ - -/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */ - -#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE) -#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE) -#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE) -#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE) -#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE) - -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */ -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */ -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */ -#define GPIO_IS2(x) (x+GPIOx_IS1L) -#define GPIO_IS3(x) (x+GPIOx_IS1L) - #define CPLD_REG0_ADDR 0x50100000 #define CPLD_REG1_ADDR 0x50100001 /* -- cgit v1.1 From aee747f19b460a0e9da20ff21e90fdaac1cec359 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 15 Nov 2007 14:23:55 +0100 Subject: ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platforms - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese --- include/asm-ppc/gpio.h | 35 +++++++++++++++++++++++++++++++++++ include/configs/lwmon5.h | 2 +- include/configs/pcs440ep.h | 2 +- include/ppc405.h | 2 ++ include/ppc440.h | 28 ---------------------------- 5 files changed, 39 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h index c9b6a36..d0c3eba 100644 --- a/include/asm-ppc/gpio.h +++ b/include/asm-ppc/gpio.h @@ -21,6 +21,9 @@ * MA 02111-1307 USA */ +#ifndef __ASM_PPC_GPIO_H +#define __ASM_PPC_GPIO_H + /* 4xx PPC's have 2 GPIO controllers */ #if defined(CONFIG_405EZ) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -30,6 +33,36 @@ #define GPIO_GROUP_MAX 1 #endif +/* Offsets */ +#define GPIOx_OR 0x00 /* GPIO Output Register */ +#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ +#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ +#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ +#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ +#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ +#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ +#define GPIOx_IR 0x1C /* GPIO Input Register */ +#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ +#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ +#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ +#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ +#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ +#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ +#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ +#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ +#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ + +#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */ +#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */ +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ +#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ +#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ + +#define GPIO0 0 +#define GPIO1 1 + #define GPIO_MAX 32 #define GPIO_ALT1_SEL 0x40000000 #define GPIO_ALT2_SEL 0x80000000 @@ -56,3 +89,5 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val); void gpio_write_bit(int pin, int val); int gpio_read_out_bit(int pin); void gpio_set_chip_configuration(void); + +#endif /* __ASM_PPC_GPIO_H */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 3180617..9cb483d 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -414,7 +414,7 @@ /*----------------------------------------------------------------------- * PPC440 GPIO Configuration */ -#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index d467338..d66f4bd 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -365,7 +365,7 @@ /*----------------------------------------------------------------------- * PPC440 GPIO Configuration */ -#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ diff --git a/include/ppc405.h b/include/ppc405.h index 2c55917..e5051d4 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -1135,6 +1135,8 @@ #endif /* CONFIG_405EZ */ +#define GPIO0_BASE GPIO_BASE + #if defined(CONFIG_405EX) #define SDR0_SRST 0x0200 diff --git a/include/ppc440.h b/include/ppc440.h index 2f841fa..dfa3d2a 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3187,9 +3187,6 @@ /****************************************************************************** * GPIO macro register defines ******************************************************************************/ -#define GPIO0 0 -#define GPIO1 1 - #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) @@ -3205,31 +3202,6 @@ #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00) #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00) -/* Offsets */ -#define GPIOx_OR 0x00 /* GPIO Output Register */ -#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ -#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ -#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ -#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ -#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ -#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ -#define GPIOx_IR 0x1C /* GPIO Input Register */ -#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ -#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ -#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ -#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ -#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ -#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ -#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ -#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ -#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ - -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ -#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ -#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ - #define GPIO0_OR (GPIO0_BASE+0x0) #define GPIO0_TCR (GPIO0_BASE+0x4) #define GPIO0_OSRL (GPIO0_BASE+0x8) -- cgit v1.1 From c93945e8f9e300860d2bf73a2549ce5794f8bd00 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 15 Nov 2007 08:20:25 -0700 Subject: Revert "[MPC512x] Correct fixup relocation" This reverts commit 8d17979d0359492a822a0a409d26e3a3549b4cd4. Signed-off-by: Grant Likely --- include/common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index aca281b..5a63906 100644 --- a/include/common.h +++ b/include/common.h @@ -70,7 +70,6 @@ typedef volatile unsigned char vu_char; #elif defined(CONFIG_MPC512X) #include #include -#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC8220) #include #define CONFIG_RELOC_FIXUP_WORKS -- cgit v1.1 From 928fe33b24cdf382a8dc8687fed24b1961cdb5d6 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 15 Nov 2007 08:20:43 -0700 Subject: Revert "Correct fixup relocation for mpc83xx" This reverts commit 057004f4a4863554d56cc56268bfa7c7d9738e27. Signed-off-by: Grant Likely --- include/common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 5a63906..3973ed8 100644 --- a/include/common.h +++ b/include/common.h @@ -99,7 +99,6 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_MPC83XX #include #include -#define CONFIG_RELOC_FIXUP_WORKS #endif #ifdef CONFIG_4xx #include -- cgit v1.1 From 96279ab4cad60cb5972aa934fbe4845ac02cc75a Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 15 Nov 2007 08:20:50 -0700 Subject: Revert "Correct fixup relocation for mpc8260" This reverts commit 5af61b2f4b838a05f79be274f3e5a66edd2d9c96. Signed-off-by: Grant Likely --- include/common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 3973ed8..d763cc7 100644 --- a/include/common.h +++ b/include/common.h @@ -86,7 +86,6 @@ typedef volatile unsigned char vu_char; #define CONFIG_MPC8260 1 #endif #include -#define CONFIG_RELOC_FIXUP_WORKS #endif #ifdef CONFIG_MPC86xx #include -- cgit v1.1 From 70922342369e5e39b286fe21e768a239ca07a514 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 15 Nov 2007 08:20:57 -0700 Subject: Revert "Correct fixup relocation for mpc824x" This reverts commit f3a52fe05923935db86985daf9438e2f70ac39aa. Signed-off-by: Grant Likely --- include/common.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index d763cc7..8ba57e8 100644 --- a/include/common.h +++ b/include/common.h @@ -73,8 +73,6 @@ typedef volatile unsigned char vu_char; #elif defined(CONFIG_MPC8220) #include #define CONFIG_RELOC_FIXUP_WORKS -#elif defined(CONFIG_824X) -#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_8260) #if defined(CONFIG_MPC8247) \ || defined(CONFIG_MPC8248) \ -- cgit v1.1 From 139365fbe566d0fc619a1ed04452ec5388f0cef8 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 15 Nov 2007 08:21:04 -0700 Subject: Revert "Correct fixup relocation for mpc8220" This reverts commit a85dd254c0577fca13627c46e93fc2ad4c4f1f00. Signed-off-by: Grant Likely --- include/common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 8ba57e8..a4d1f8d 100644 --- a/include/common.h +++ b/include/common.h @@ -72,7 +72,6 @@ typedef volatile unsigned char vu_char; #include #elif defined(CONFIG_MPC8220) #include -#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_8260) #if defined(CONFIG_MPC8247) \ || defined(CONFIG_MPC8248) \ -- cgit v1.1 From e15633888a058aacb31a62d2cf1278e1e4c236ab Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 15 Nov 2007 08:24:32 -0700 Subject: Revert "Correct fixup relocation for MPC5xxx" This reverts commit 6f7576b20ecf0d040c3ac3b032b5cbc860e38a90. Signed-off-by: Grant Likely --- include/common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index a4d1f8d..4bfb8c5 100644 --- a/include/common.h +++ b/include/common.h @@ -66,7 +66,6 @@ typedef volatile unsigned char vu_char; #define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC5xxx) #include -#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC512X) #include #include -- cgit v1.1 From 955413f35f054a82e40042f1dbcf501c6a05719b Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 15 Nov 2007 08:27:52 -0700 Subject: Revert "Correct relocation fixup for mpc5xx" This reverts commit 3649cd99ba815b6601868735765602f00ef3692b. Signed-off-by: Grant Likely --- include/common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 4bfb8c5..63ac8b0 100644 --- a/include/common.h +++ b/include/common.h @@ -63,7 +63,6 @@ typedef volatile unsigned char vu_char; #endif #elif defined(CONFIG_5xx) #include -#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC5xxx) #include #elif defined(CONFIG_MPC512X) -- cgit v1.1 From 1b4aaffe4fb2a5e95d9111a5d94fd1f89215dce4 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Mon, 24 Sep 2007 09:05:30 -0600 Subject: Add .gitignore files Signed-off-by: Grant Likely Acked-by: Kim Phillips --- include/.gitignore | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 include/.gitignore (limited to 'include') diff --git a/include/.gitignore b/include/.gitignore new file mode 100644 index 0000000..d8fda80 --- /dev/null +++ b/include/.gitignore @@ -0,0 +1,6 @@ +/asm +/asm-ppc/arch +/bmp_logo.h +/config.h +/config.mk +/version_autogenerated.h -- cgit v1.1 From ecdcbd4f8c1f8cefd785752f4e7536aae2a4ecf9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 16 Nov 2007 14:00:59 +0100 Subject: ppc4xx: Update AMCC Makalu for board rev 1.1 This patch adds changes needed for Makalu rev 1.1: - Enable 2nd DDR2 bank resulting in 256MByte of SDRAM - Enable 2nd ethernet port EMAC1 - Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE) - Reset PCIe ports via GPIO upon bootup Signed-off-by: Stefan Roese --- include/configs/makalu.h | 78 ++++++++++++++++++++++++++++++------------------ 1 file changed, 49 insertions(+), 29 deletions(-) (limited to 'include') diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 3070779..aa421c1 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -44,11 +44,11 @@ * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_BASE 0xFC000000 #define CFG_FPGA_BASE 0xF0000000 #define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ #define CFG_MONITOR_BASE (TEXT_BASE) /*----------------------------------------------------------------------- @@ -113,7 +113,7 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CFG_MBYTES_SDRAM 128 +#define CFG_MBYTES_SDRAM 256 /*----------------------------------------------------------------------- * I2C @@ -150,7 +150,7 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY1_ADDR 2 +#define CONFIG_PHY1_ADDR 0 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ @@ -187,8 +187,8 @@ "bootfile=makalu/uImage\0" \ "fdt_file=makalu/makalu.dtb\0" \ "fdt_addr=400000\0" \ - "kernel_addr=fe000000\0" \ - "ramdisk_addr=fe200000\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc200000\0" \ "initrd_high=30000000\0" \ "load=tftp 200000 makalu/u-boot.bin\0" \ "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ @@ -282,6 +282,7 @@ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ /*----------------------------------------------------------------------- * PCI stuff @@ -323,7 +324,7 @@ *----------------------------------------------------------------------*/ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x04011000 -#define CFG_EBC_PB0CR 0xFE0BA000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit*/ +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 2 (CPLD) initialization */ #define CFG_EBC_PB2AP 0x9400C800 @@ -334,28 +335,47 @@ /*----------------------------------------------------------------------- * GPIO Setup *----------------------------------------------------------------------*/ -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EX specific) - * - * GPIO0[0-3] - EBC data 0-3 inputs/outputs - * GPIO0[4-7] - USB data 4-7 inputs/outputs - * GPIO0[8-11] - NFCE# 1-3 inputs/outputs, GPIO11: IRQ6 inputs - * GPIO0[12-15] - USB data 0-3 inputs/outputs - * GPIO0[16-21] - UART0 control signal inputs/outputs - * - * GPIO0[22-25,27] - EBC control signal inputs/outputs - * GPIO0[26] - Instruction trace outputs - * GPIO0[28] - Float, N/C - * GPIO0[29-31] - DMA control signal inputs/outputs - */ -#define CFG_GPIO0_OSRL 0x00AA54AA -#define CFG_GPIO0_OSRH 0x55500000 -#define CFG_GPIO0_TSRL 0x00AA54AA -#define CFG_GPIO0_TSRH 0x55500000 -#define CFG_GPIO0_ISR1L 0x00005400 -#define CFG_GPIO0_ISR1H 0x55500000 -#define CFG_GPIO0_ISR2L 0x00550055 -#define CFG_GPIO0_ISR2H 0x00000000 +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS(1) NFCE(1) IRQ(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS(2) NFCE(2) IRQ(8) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS(3) NFCE(3) IRQ(9) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 IRQ(2) DMA_EOT1 */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 IRQ(1) DMA_REQ1 */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO31 IRQ(0) DMA_ACK1 */ \ +} \ +} + +#define CFG_GPIO_PCIE_RST 23 +#define CFG_GPIO_PCIE_CLKREQ 27 +#define CFG_GPIO_PCIE_WAKE 28 /* * Internal Definitions -- cgit v1.1 From f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 16 Nov 2007 14:16:54 +0100 Subject: ppc4xx: Enable 405EX PCIe UTL register configuration Till now the UTL registers on 405EX were not initialized but left with their default values. This patch new initializes some of the UTL registers on 405EX. Signed-off-by: Stefan Roese --- include/asm-ppc/4xx_pcie.h | 2 ++ include/common.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index ffe0770..4c03b05 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -203,6 +203,7 @@ /* * UTL register offsets */ +#define PEUTL_PBCTL 0x00 #define PEUTL_PBBSZ 0x20 #define PEUTL_OPDBSZ 0x68 #define PEUTL_IPHBSZ 0x70 @@ -210,6 +211,7 @@ #define PEUTL_OUTTR 0x90 #define PEUTL_INTR 0x98 #define PEUTL_PCTL 0xa0 +#define PEUTL_RCSTA 0xb0 #define PEUTL_RCIRQEN 0xb8 /* diff --git a/include/common.h b/include/common.h index 46ed6bd..77aed1a 100644 --- a/include/common.h +++ b/include/common.h @@ -516,10 +516,10 @@ void get_sys_info ( sys_info_t * ); # if defined(CONFIG_440SPE) unsigned long determine_sysper(void); unsigned long determine_pci_clock_per(void); - int ppc440spe_revB(void); # endif # endif typedef PPC4xx_SYS_INFO sys_info_t; +int ppc440spe_revB(void); void get_sys_info ( sys_info_t * ); #endif -- cgit v1.1 From db74b3c1c9481a6bffbf8cd445e5bcbf6908e836 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Mon, 29 Oct 2007 19:26:21 +0800 Subject: Unify pixis_reset altbank across board families Basically, refactor the CFG_PIXIS_VBOOT_MASK values into the separate board config files. Signed-off-by: Jason Jin Signed-off-by: Jon Loeliger --- include/configs/MPC8544DS.h | 1 + include/configs/MPC8641HPCN.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index f580cca..13e2a2c 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -198,6 +198,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ /* define to use L1 as initial stack */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index aa6dbc4..6f87240 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -201,6 +201,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -- cgit v1.1 From 5c15010efad980ad5498cc565fc1ed70df2f52b4 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 13 Nov 2007 09:11:05 +0100 Subject: Fixed mips_io_port_base build errors. This patch has been sent on: - 29 Sep 2007 Although mips_io_port_base is currently a part of IDE command, it is quite fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move it to MIPS general part, and introduce `set_io_port_base()' from Linux. This patch is triggered by multiple definition of `mips_io_port_base' build error on gth2 (and tb0229 also needs this fix.) board/gth2/libgth2.a(gth2.o): In function `log_serial_char': /home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base' common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here make: *** [u-boot] Error 1 Signed-off-by: Shinya Kuribayashi Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/asm-mips/io.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index cd4d5dc..1e060f7 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -71,7 +71,21 @@ * instruction, so the lower 16 bits must be zero. Should be true on * on any sane architecture; generic code does not use this assumption. */ -extern unsigned long mips_io_port_base; +extern const unsigned long mips_io_port_base; + +/* + * Gcc will generate code to load the value of mips_io_port_base after each + * function call which may be fairly wasteful in some cases. So we don't + * play quite by the book. We tell gcc mips_io_port_base is a long variable + * which solves the code generation issue. Now we need to violate the + * aliasing rules a little to make initialization possible and finally we + * will need the barrier() to fight side effects of the aliasing chat. + * This trickery will eventually collapse under gcc's optimizer. Oh well. + */ +static inline void set_io_port_base(unsigned long base) +{ + * (unsigned long *) &mips_io_port_base = base; +} /* * Thanks to James van Artsdalen for a better timing-fix than -- cgit v1.1 From 1c3dd43338a077165e7e0309cb3994e65d2bdbf8 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 13 Nov 2007 22:18:33 -0700 Subject: powerpc: Backout relocation changes. Ugh. I *hate* to back this change out, but these compiler flags don't work for relocation on all versions of GCC. I've not been able to reproduce the environment in my setup (and hence, not been able to find a combination that *does* work), so I've got no choice but to go back to the old gcc flags and linker script. Signed-off-by: Grant Likely --- include/common.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index aca281b..63ac8b0 100644 --- a/include/common.h +++ b/include/common.h @@ -63,19 +63,13 @@ typedef volatile unsigned char vu_char; #endif #elif defined(CONFIG_5xx) #include -#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC5xxx) #include -#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC512X) #include #include -#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC8220) #include -#define CONFIG_RELOC_FIXUP_WORKS -#elif defined(CONFIG_824X) -#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_8260) #if defined(CONFIG_MPC8247) \ || defined(CONFIG_MPC8248) \ @@ -87,7 +81,6 @@ typedef volatile unsigned char vu_char; #define CONFIG_MPC8260 1 #endif #include -#define CONFIG_RELOC_FIXUP_WORKS #endif #ifdef CONFIG_MPC86xx #include @@ -100,7 +93,6 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_MPC83XX #include #include -#define CONFIG_RELOC_FIXUP_WORKS #endif #ifdef CONFIG_4xx #include -- cgit v1.1 From fd329e6f05bbdfe6bd71b0e09f0c76d3b0a025a5 Mon Sep 17 00:00:00 2001 From: Luotao Fu Date: Wed, 14 Nov 2007 18:58:33 +0100 Subject: Fix the i2c frequency and default address in rsdproto board rsdproto board support has wrong I2C frequency and wrong return value handling. Signed-off-by: Luotao Fu --- include/configs/rsdproto.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h index 814082c..40a05fa 100644 --- a/include/configs/rsdproto.h +++ b/include/configs/rsdproto.h @@ -92,8 +92,8 @@ /* enable I2C */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x30 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -- cgit v1.1 From 9ea61b57968554eaf0f474ec7e088b17d367f474 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 17 Nov 2007 14:52:29 +0100 Subject: ppc4xx: Update AMCC Kilauea config file - Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE) Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 60 +++++++++++++++++++++++++++++------------------ 1 file changed, 37 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index ddd064a..b4144b3 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -430,29 +430,43 @@ /*----------------------------------------------------------------------- * GPIO Setup *----------------------------------------------------------------------*/ -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EX specific) - * - * GPIO0[0-3] - EBC data 0-3 inputs/outputs - * GPIO0[4-7] - USB data 4-7 inputs/outputs - * GPIO0[8-11] - NFCE# 1-3 inputs/outputs, GPIO11: IRQ6 inputs - * GPIO0[12-15] - USB data 0-3 inputs/outputs - * GPIO0[16-21] - UART0 control signal inputs/outputs - * - * GPIO0[22-25,27] - EBC control signal inputs/outputs - * GPIO0[26] - Instruction trace outputs - * GPIO0[28] - Float, N/C - * GPIO0[29-31] - DMA control signal inputs/outputs - */ -#define CFG_GPIO0_OSRL 0x00AA54AA -#define CFG_GPIO0_OSRH 0x21800000 -#define CFG_GPIO0_TSRL 0x00AA55AA -#define CFG_GPIO0_TSRH 0xA5A00000 - -#define CFG_GPIO0_ISR1L 0x00000100 -#define CFG_GPIO0_ISR1H 0x04000000 -#define CFG_GPIO0_ISR2L 0x00550055 -#define CFG_GPIO0_ISR2H 0x40100000 +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS(1) NFCE(1) IRQ(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS(2) NFCE(2) IRQ(8) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS(3) NFCE(3) IRQ(9) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_1}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_1}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 IRQ(2) DMA_EOT1 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 IRQ(1) DMA_REQ1 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 IRQ(0) DMA_ACK1 */ \ +} \ +} /* * Internal Definitions -- cgit v1.1 From e8da58f2bc092891e8cc92b927ed5c4bd0cb0cab Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 19 Nov 2007 12:59:14 +0100 Subject: Fix build problems with mp2usb board Signed-off-by: Wolfgang Denk --- include/asm-arm/arch-at91rm9200/hardware.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h index 8bb0c47..b868e38 100644 --- a/include/asm-arm/arch-at91rm9200/hardware.h +++ b/include/asm-arm/arch-at91rm9200/hardware.h @@ -24,8 +24,6 @@ #ifndef __ASSEMBLY__ #include "AT91RM9200.h" -#else -#include "AT91RM9200_inc.h" #endif /* Virtual and Physical base address for system peripherals */ -- cgit v1.1 From f30ad49b16bf998b03c1a5228b6c86369d61c258 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Mon, 19 Nov 2007 10:02:13 -0500 Subject: Move CONFIG_QE out of CONFIG_PCI wrap for MPC8568MDS CONFIG_QE shouldn't be in the wrap of CONFIG_PCI, fix it. Signed-off-by: Haiying Wang --- include/configs/MPC8568MDS.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 548e158..b9366cc 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -334,11 +334,6 @@ extern unsigned long get_clock_freq(void); #define CFG_SRIO_MEM_BASE 0xc0000000 -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - #ifdef CONFIG_QE /* * QE UEC ethernet configuration @@ -377,6 +372,11 @@ extern unsigned long get_clock_freq(void); #endif #endif /* CONFIG_QE */ +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -- cgit v1.1 From 68b88999da87ab88e71e1306192905be3450198e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 20 Nov 2007 15:02:26 -0600 Subject: 8610HPCD: Enable the 8610 Display Interface Unit Signed-off-by: Jon Loeliger --- include/configs/MPC8610HPCD.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index ef1310f..55df5aa 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -24,7 +24,7 @@ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ /* video */ -#undef CONFIG_VIDEO +#define CONFIG_VIDEO #if defined(CONFIG_VIDEO) #define CONFIG_CFB_CONSOLE -- cgit v1.1 From 4a43719a7738712811d822ca8125427b27a55cdc Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Mon, 24 Sep 2007 09:05:31 -0600 Subject: [BUILD] conditionally compile common/cmd_*.c in common/Makefile Modify common/Makefile to conditionally compile the cmd_*.c files based on the board config. Signed-off-by: Grant Likely --- include/configs/sbc2410x.h | 1 - include/configs/smdk2410.h | 1 - 2 files changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index b4a063a..9b05bd6 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -103,7 +103,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index ca404ff..18a036c 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -88,7 +88,6 @@ #include #define CONFIG_CMD_CACHE -#define CONFIG_CMD_REGINFO #define CONFIG_CMD_DATE #define CONFIG_CMD_ELF -- cgit v1.1 From a3c2933e02503fe36ade2c1b65af46f2b7a168e7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 24 Oct 2007 10:21:57 -0500 Subject: Removed some nonused fdt functions and moved fdt_find_and_setprop out of libfdt Removed: fdt_node_is_compatible fdt_find_node_by_type fdt_find_compatible_node To ease merge of newer libfdt as we aren't using them anywhere at this time. Also moved fdt_find_and_setprop out of libfdt into fdt_support.c for the same reason. Signed-off-by: Kumar Gala --- include/libfdt.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include') diff --git a/include/libfdt.h b/include/libfdt.h index 38c65a9..ba348a9 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -78,12 +78,6 @@ int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); int fdt_find_node_by_path(const void *fdt, const char *path); -int fdt_find_node_by_type(const void *fdt, int nodeoffset, const char *type); - -int fdt_node_is_compatible(const void *fdt, int nodeoffset, - const char *compat); -int fdt_find_compatible_node(const void *fdt, int nodeoffset, - const char *type, const char *compat); struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, const char *name, int *lenp); -- cgit v1.1 From e93becf80d732b64aef81b23e8b6ece02c40533d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 3 Nov 2007 19:46:28 -0500 Subject: Move do_fixup* for libfdt into common code Moved the generic fixup handling code out of cpu/mpc5xxx and cpu/mpc8260 into common/fdt_support.c and renamed: do_fixup() -> do_fixup_by_path() do_fixup_u32() -> do_fixup_by_path_u32() Signed-off-by: Kumar Gala --- include/fdt_support.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/fdt_support.h b/include/fdt_support.h index 60fa423..0314dfd 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -29,6 +29,10 @@ #include int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force); +void do_fixup_by_path(void *fdt, const char *path, const char *prop, + const void *val, int len, int create); +void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop, + u32 val, int create); #ifdef CONFIG_OF_HAS_UBOOT_ENV int fdt_env(void *fdt); -- cgit v1.1 From 8d04f02f6224e6983f4812ea4da704950ec8539c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 24 Oct 2007 11:04:22 -0500 Subject: Update libfdt from device tree compiler (dtc) Update libfdt to commit 8eaf5e358366017aa2e846c5038d1aa19958314e from the device tree compiler (dtc) project. Signed-off-by: Kumar Gala --- include/fdt.h | 51 ++-- include/libfdt.h | 711 +++++++++++++++++++++++++++++++++++++++++++++++++------ 2 files changed, 658 insertions(+), 104 deletions(-) (limited to 'include') diff --git a/include/fdt.h b/include/fdt.h index 3dd3aca..e00559a 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -1,44 +1,25 @@ -/* - * libfdt - Flat Device Tree manipulation - * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 of - * the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - #ifndef _FDT_H #define _FDT_H #ifndef __ASSEMBLY__ struct fdt_header { - uint32_t magic; /* magic word FDT_MAGIC */ - uint32_t totalsize; /* total size of DT block */ - uint32_t off_dt_struct; /* offset to structure */ - uint32_t off_dt_strings; /* offset to strings */ - uint32_t off_mem_rsvmap; /* offset to memory reserve map */ - uint32_t version; /* format version */ - uint32_t last_comp_version; /* last compatible version */ - - /* version 2 fields below */ - uint32_t boot_cpuid_phys; /* Which physical CPU id we're + uint32_t magic; /* magic word FDT_MAGIC */ + uint32_t totalsize; /* total size of DT block */ + uint32_t off_dt_struct; /* offset to structure */ + uint32_t off_dt_strings; /* offset to strings */ + uint32_t off_mem_rsvmap; /* offset to memory reserve map */ + uint32_t version; /* format version */ + uint32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + uint32_t boot_cpuid_phys; /* Which physical CPU id we're booting on */ /* version 3 fields below */ - uint32_t size_dt_strings; /* size of the strings block */ + uint32_t size_dt_strings; /* size of the strings block */ /* version 17 fields below */ - uint32_t size_dt_struct; /* size of the structure block */ + uint32_t size_dt_struct; /* size of the structure block */ }; struct fdt_reserve_entry { @@ -60,12 +41,12 @@ struct fdt_property { #endif /* !__ASSEMBLY */ -#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ #define FDT_TAGSIZE sizeof(uint32_t) -#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ -#define FDT_END_NODE 0x2 /* End node */ -#define FDT_PROP 0x3 /* Property: name off, +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, size, content */ #define FDT_NOP 0x4 /* nop */ #define FDT_END 0x9 diff --git a/include/libfdt.h b/include/libfdt.h index ba348a9..6b2fb92 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -1,148 +1,721 @@ +#ifndef _LIBFDT_H +#define _LIBFDT_H /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 of - * the License, or (at your option) any later version. + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: * - * This library is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef _LIBFDT_H -#define _LIBFDT_H - -#include #include +#include #define FDT_FIRST_SUPPORTED_VERSION 0x10 #define FDT_LAST_SUPPORTED_VERSION 0x11 /* Error codes: informative error codes */ #define FDT_ERR_NOTFOUND 1 + /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ #define FDT_ERR_EXISTS 2 + /* FDT_ERR_EXISTS: Attemped to create a node or property which + * already exists */ #define FDT_ERR_NOSPACE 3 + /* FDT_ERR_NOSPACE: Operation needed to expand the device + * tree, but its buffer did not have sufficient space to + * contain the expanded tree. Use fdt_open_into() to move the + * device tree to a buffer with more space. */ /* Error codes: codes for bad parameters */ #define FDT_ERR_BADOFFSET 4 + /* FDT_ERR_BADOFFSET: Function was passed a structure block + * offset which is out-of-bounds, or which points to an + * unsuitable part of the structure for the operation. */ #define FDT_ERR_BADPATH 5 -#define FDT_ERR_BADSTATE 6 + /* FDT_ERR_BADPATH: Function was passed a badly formatted path + * (e.g. missing a leading / for a function which requires an + * absolute path) */ +#define FDT_ERR_BADPHANDLE 6 + /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle + * value. phandle values of 0 and -1 are not permitted. */ +#define FDT_ERR_BADSTATE 7 + /* FDT_ERR_BADSTATE: Function was passed an incomplete device + * tree created by the sequential-write functions, which is + * not sufficiently complete for the requested operation. */ /* Error codes: codes for bad device tree blobs */ -#define FDT_ERR_TRUNCATED 7 -#define FDT_ERR_BADMAGIC 8 -#define FDT_ERR_BADVERSION 9 -#define FDT_ERR_BADSTRUCTURE 10 -#define FDT_ERR_BADLAYOUT 11 +#define FDT_ERR_TRUNCATED 8 + /* FDT_ERR_TRUNCATED: Structure block of the given device tree + * ends without an FDT_END tag. */ +#define FDT_ERR_BADMAGIC 9 + /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a + * device tree at all - it is missing the flattened device + * tree magic number. */ +#define FDT_ERR_BADVERSION 10 + /* FDT_ERR_BADVERSION: Given device tree has a version which + * can't be handled by the requested operation. For + * read-write functions, this may mean that fdt_open_into() is + * required to convert the tree to the expected version. */ +#define FDT_ERR_BADSTRUCTURE 11 + /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt + * structure block or other serious error (e.g. misnested + * nodes, or subnodes preceding properties). */ +#define FDT_ERR_BADLAYOUT 12 + /* FDT_ERR_BADLAYOUT: For read-write functions, the given + * device tree has it's sub-blocks in an order that the + * function can't handle (memory reserve map, then structure, + * then strings). Use fdt_open_into() to reorganize the tree + * into a form suitable for the read-write operations. */ + +/* "Can't happen" error indicating a bug in libfdt */ +#define FDT_ERR_INTERNAL 13 + /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. + * Should never be returned, if it is, it indicates a bug in + * libfdt itself. */ -#define FDT_ERR_MAX 11 +#define FDT_ERR_MAX 13 + +/**********************************************************************/ +/* Low-level functions (you probably don't need these) */ +/**********************************************************************/ + +const void *fdt_offset_ptr(const void *fdt, int offset, int checklen); +static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) +{ + return (void *)fdt_offset_ptr(fdt, offset, checklen); +} + +uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); + +/**********************************************************************/ +/* General functions */ +/**********************************************************************/ #define fdt_get_header(fdt, field) \ - (fdt32_to_cpu(((struct fdt_header *)(fdt))->field)) -#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) + (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) #define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) #define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) #define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) #define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) #define fdt_version(fdt) (fdt_get_header(fdt, version)) -#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) -#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) -#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) #define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) -#define fdt_set_header(fdt, field, val) \ - ((struct fdt_header *)(fdt))->field = cpu_to_fdt32(val) +#define __fdt_set_hdr(name) \ + static inline void fdt_set_##name(void *fdt, uint32_t val) \ + { \ + struct fdt_header *fdth = fdt; \ + fdth->name = cpu_to_fdt32(val); \ + } +__fdt_set_hdr(magic); +__fdt_set_hdr(totalsize); +__fdt_set_hdr(off_dt_struct); +__fdt_set_hdr(off_dt_strings); +__fdt_set_hdr(off_mem_rsvmap); +__fdt_set_hdr(version); +__fdt_set_hdr(last_comp_version); +__fdt_set_hdr(boot_cpuid_phys); +__fdt_set_hdr(size_dt_strings); +__fdt_set_hdr(size_dt_struct); +#undef __fdt_set_hdr +/** + * fdt_check_header - sanity check a device tree or possible device tree + * @fdt: pointer to data which might be a flattened device tree + * + * fdt_check_header() checks that the given buffer contains what + * appears to be a flattened device tree with sane information in its + * header. + * + * returns: + * 0, if the buffer appears to contain a valid device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings, as above + */ int fdt_check_header(const void *fdt); -void *fdt_offset_ptr(const void *fdt, int offset, int checklen); +/** + * fdt_move - move a device tree around in memory + * @fdt: pointer to the device tree to move + * @buf: pointer to memory where the device is to be moved + * @bufsize: size of the memory space at buf + * + * fdt_move() relocates, if possible, the device tree blob located at + * fdt to the buffer at buf of size bufsize. The buffer may overlap + * with the existing device tree blob at fdt. Therefore, + * fdt_move(fdt, fdt, fdt_totalsize(fdt)) + * should always succeed. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_move(const void *fdt, void *buf, int bufsize); -#define fdt_offset_ptr_typed(fdt, offset, var) \ - ((typeof(var))(fdt_offset_ptr((fdt), (offset), sizeof(*(var))))) +/**********************************************************************/ +/* Read-only functions */ +/**********************************************************************/ -int fdt_move(const void *fdt, void *buf, int bufsize); +/** + * fdt_string - retreive a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * + * fdt_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds + */ +const char *fdt_string(const void *fdt, int stroffset); -/* Read-only functions */ -char *fdt_string(const void *fdt, int stroffset); +/** + * fdt_num_mem_rsv - retreive the number of memory reserve map entries + * @fdt: pointer to the device tree blob + * + * Returns the number of entries in the device tree blob's memory + * reservation map. This does not include the terminating 0,0 entry + * or any other (0,0) entries reserved for expansion. + * + * returns: + * the number of entries + */ +int fdt_num_mem_rsv(const void *fdt); +/** + * fdt_get_mem_rsv - retreive one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: pointers to 64-bit variables + * + * On success, *address and *size will contain the address and size of + * the n-th reserve map entry from the device tree blob, in + * native-endian format. + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); + +/** + * fdt_subnode_offset_namelen - find a subnode based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_subnode_offset(), but only examine the first + * namelen characters of name for matching the subnode name. This is + * useful for finding subnodes based on a portion of a larger string, + * such as a full path. + */ int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, const char *name, int namelen); +/** + * fdt_subnode_offset - find a subnode of a given node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node at structure block + * offset parentoffset with the given name. name may include a unit + * address, in which case fdt_subnode_offset() will find the subnode + * with that unit address, or the unit address may be omitted, in + * which case fdt_subnode_offset() will find an arbitrary subnode + * whose name excluding unit address matches the given name. + * + * returns: + * structure block offset of the requested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); -int fdt_find_node_by_path(const void *fdt, const char *path); +/** + * fdt_path_offset - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * + * fdt_path_offset() finds a node of a given path in the device tree. + * Each path component may omit the unit address portion, but the + * results of this are undefined if any such path component is + * ambiguous (that is if there are multiple nodes at the relevant + * level matching the given component, differentiated only by unit + * address). + * + * returns: + * structure block offset of the node with the requested path (>=0), on success + * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_NOTFOUND, if the requested node does not exist + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_path_offset(const void *fdt, const char *path); + +/** + * fdt_get_name - retreive the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the starting node + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_name() retrieves the name (including unit address) of the + * device tree node at structure block offset nodeoffset. If lenp is + * non-NULL, the length of this name is also returned, in the integer + * pointed to by lenp. + * + * returns: + * pointer to the node's name, on success + * If lenp is non-NULL, *lenp contains the length of that name (>=0) + * NULL, on error + * if lenp is non-NULL *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); + +/** + * fdt_get_property - find a given property in a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property() retrieves a pointer to the fdt_property + * structure within the device tree blob corresponding to the property + * named 'name' of the node at offset nodeoffset. If lenp is + * non-NULL, the length of the property value also returned, in the + * integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, + const char *name, + int *lenp) +{ + return (struct fdt_property *)fdt_get_property(fdt, nodeoffset, + name, lenp); +} + +/** + * fdt_getprop - retrieve the value of a given property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline void *fdt_getprop_w(void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return (void *)fdt_getprop(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_get_phandle - retreive the phandle of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the node + * + * fdt_get_phandle() retrieves the phandle of the device tree node at + * structure block offset nodeoffset. + * + * returns: + * the phandle of the node at nodeoffset, on succes (!= 0, != -1) + * 0, if the node has no phandle, or another error occurs + */ +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); + +/** + * fdt_get_path - determine the full path of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose path to find + * @buf: character buffer to contain the returned path (will be overwritten) + * @buflen: size of the character buffer at buf + * + * fdt_get_path() computes the full path of the node at offset + * nodeoffset, and records that path in the buffer at buf. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * 0, on success + * buf contains the absolute path of the node at + * nodeoffset, as a NUL-terminated string. + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) + * characters and will not fit in the given buffer. + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); + +/** + * fdt_supernode_atdepth_offset - find a specific ancestor of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * @supernodedepth: depth of the ancestor to find + * @nodedepth: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_supernode_atdepth_offset() finds an ancestor of the given node + * at a specific depth from the root (where the root itself has depth + * 0, its immediate subnodes depth 1 and so forth). So + * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); + * will always return 0, the offset of the root node. If the node at + * nodeoffset has depth D, then: + * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); + * will return nodeoffset itself. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + + * structure block offset of the node at node offset's ancestor + * of depth supernodedepth (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag +* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth); + +/** + * fdt_node_depth - find the depth of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_node_depth() finds the depth of a given node. The root node + * has depth 0, its immediate subnodes depth 1 and so forth. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * depth of the node at nodeoffset (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_depth(const void *fdt, int nodeoffset); + +/** + * fdt_parent_offset - find the parent of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_parent_offset() locates the parent node of a given node (that + * is, it finds the offset of the node which contains the node at + * nodeoffset as a subnode). + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset, *twice*. + * + * returns: + * stucture block offset of the parent of the node at nodeoffset + * (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_parent_offset(const void *fdt, int nodeoffset); + +/** + * fdt_node_offset_by_prop_value - find nodes with a given property value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * + * fdt_node_offset_by_prop_value() returns the offset of the first + * node after startoffset, which has a property named propname whose + * value is of length proplen and has value equal to propval; or if + * startoffset is -1, the very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, + * propval, proplen); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, + * propval, proplen); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen); + +/** + * fdt_node_offset_by_phandle - find the node with a given phandle + * @fdt: pointer to the device tree blob + * @phandle: phandle value + * + * fdt_node_offset_by_prop_value() returns the offset of the node + * which has the given phandle value. If there is more than one node + * in the tree with the given phandle (an invalid tree), results are + * undefined. + * + * returns: + * structure block offset of the located node (>= 0), on success + * -FDT_ERR_NOTFOUND, no node with that phandle exists + * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); + +/** + * fdt_node_check_compatible: check a node's compatible property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @compatible: string to match against + * + * + * fdt_node_check_compatible() returns 0 if the given node contains a + * 'compatible' property with the given string as one of its elements, + * it returns non-zero otherwise, or on error. + * + * returns: + * 0, if the node has a 'compatible' property listing the given string + * 1, if the node has a 'compatible' property, but it does not list + * the given string + * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property + * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible); -struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, - const char *name, int *lenp); -void *fdt_getprop(const void *fdt, int nodeoffset, - const char *name, int *lenp); +/** + * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @compatible: 'compatible' string to match against + * + * fdt_node_offset_by_compatible() returns the offset of the first + * node after startoffset, which has a 'compatible' property which + * lists the given compatible string; or if startoffset is -1, the + * very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible); -uint32_t fdt_next_tag(const void *fdt, int offset, - int *nextoffset, char **namep); -int fdt_num_reservemap(void *fdt, int *used, int *total); -int fdt_get_reservemap(void *fdt, int n, struct fdt_reserve_entry *re); +/**********************************************************************/ +/* Write-in-place functions */ +/**********************************************************************/ -/* Write-in-place functions */ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, const void *val, int len); - -#define fdt_setprop_inplace_typed(fdt, nodeoffset, name, val) \ - ({ \ - typeof(val) x = val; \ - fdt_setprop_inplace(fdt, nodeoffset, name, &x, sizeof(x)); \ - }) +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + val = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); +} int fdt_nop_property(void *fdt, int nodeoffset, const char *name); int fdt_nop_node(void *fdt, int nodeoffset); -int fdt_insert_reservemap_entry(void *fdt, int n, uint64_t addr, uint64_t size); +/**********************************************************************/ +/* Sequential write functions */ +/**********************************************************************/ -/* Sequential-write functions */ int fdt_create(void *buf, int bufsize); int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); int fdt_finish_reservemap(void *fdt); int fdt_begin_node(void *fdt, const char *name); int fdt_property(void *fdt, const char *name, const void *val, int len); -#define fdt_property_typed(fdt, name, val) \ - ({ \ - typeof(val) x = (val); \ - fdt_property((fdt), (name), &x, sizeof(x)); \ - }) +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + val = cpu_to_fdt32(val); + return fdt_property(fdt, name, &val, sizeof(val)); +} #define fdt_property_string(fdt, name, str) \ fdt_property(fdt, name, str, strlen(str)+1) int fdt_end_node(void *fdt); int fdt_finish(void *fdt); -int fdt_replace_reservemap_entry(void *fdt, int n, uint64_t addr, uint64_t size); -/* Read-write functions */ -int fdt_open_into(void *fdt, void *buf, int bufsize); +/**********************************************************************/ +/* Read-write functions */ +/**********************************************************************/ + +int fdt_open_into(const void *fdt, void *buf, int bufsize); int fdt_pack(void *fdt); +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); +int fdt_del_mem_rsv(void *fdt, int n); + int fdt_setprop(void *fdt, int nodeoffset, const char *name, const void *val, int len); -#define fdt_setprop_typed(fdt, nodeoffset, name, val) \ - ({ \ - typeof(val) x = (val); \ - fdt_setprop((fdt), (nodeoffset), (name), &x, sizeof(x)); \ - }) +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + val = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); +} #define fdt_setprop_string(fdt, nodeoffset, name, str) \ fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) -int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, - const void *val, int len, int create); int fdt_delprop(void *fdt, int nodeoffset, const char *name); int fdt_add_subnode_namelen(void *fdt, int parentoffset, const char *name, int namelen); int fdt_add_subnode(void *fdt, int parentoffset, const char *name); int fdt_del_node(void *fdt, int nodeoffset); -/* Extra functions */ +/**********************************************************************/ +/* Debugging / informational functions */ +/**********************************************************************/ + const char *fdt_strerror(int errval); #endif /* _LIBFDT_H */ -- cgit v1.1 From ab544633abdd14f4dd5d92e500b73eb59ef57e67 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 21 Nov 2007 11:11:03 -0600 Subject: Add fdt_fixup_ethernet helper to set mac addresses Added a fixup helper that uses aliases to set mac addresses in the device tree based on the bd_t Signed-off-by: Kumar Gala --- include/fdt_support.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fdt_support.h b/include/fdt_support.h index 0314dfd..150dd2b 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -33,6 +33,7 @@ void do_fixup_by_path(void *fdt, const char *path, const char *prop, const void *val, int len, int create); void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop, u32 val, int create); +void fdt_fixup_ethernet(void *fdt, bd_t *bd); #ifdef CONFIG_OF_HAS_UBOOT_ENV int fdt_env(void *fdt); -- cgit v1.1 From 9eb77cea1fa12d5969eb26a1d1d81da381bd6b1c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 21 Nov 2007 13:30:15 -0600 Subject: Add additional fdt fixup helper functions Added the following fdt fixup helpers: * do_fixup_by_prop{_u32} - Find matching nodes by property name/value * do_fixup_by_compat{_u32} - Find matching nodes by compat The _u32 variants work the same only the property they are setting is know to be a 32-bit integer instead of a byte buffer. Signed-off-by: Kumar Gala --- include/fdt_support.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/fdt_support.h b/include/fdt_support.h index 150dd2b..8f781d4 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -33,6 +33,17 @@ void do_fixup_by_path(void *fdt, const char *path, const char *prop, const void *val, int len, int create); void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop, u32 val, int create); +void do_fixup_by_prop(void *fdt, + const char *pname, const void *pval, int plen, + const char *prop, const void *val, int len, + int create); +void do_fixup_by_prop_u32(void *fdt, + const char *pname, const void *pval, int plen, + const char *prop, u32 val, int create); +void do_fixup_by_compat(void *fdt, const char *compat, + const char *prop, const void *val, int len, int create); +void do_fixup_by_compat_u32(void *fdt, const char *compat, + const char *prop, u32 val, int create); void fdt_fixup_ethernet(void *fdt, bd_t *bd); #ifdef CONFIG_OF_HAS_UBOOT_ENV -- cgit v1.1 From ca1ce226287270bb01e25b8e3674c701f12edf19 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 26 Nov 2007 15:01:45 +0100 Subject: ppc4xx: Kilauea: Configure pin mux to use ext IRQ2 as interrupt Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index b4144b3..2bb5f24 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -462,7 +462,7 @@ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \ {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \ {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 IRQ(2) DMA_EOT1 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) DMA_EOT1 */ \ {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 IRQ(1) DMA_REQ1 */ \ {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 IRQ(0) DMA_ACK1 */ \ } \ -- cgit v1.1 From 63362cfc6baa97ae0e37ba2c6ece530fcac9f79e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 26 Nov 2007 15:06:14 +0100 Subject: ppc4xx: Makalu: Change EBC setup for CS0 to enable 400MHz usage As suggested by Senao, use a different EBC_PB0AP setup for 400MHz operation. Signed-off-by: Stefan Roese --- include/configs/makalu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/makalu.h b/include/configs/makalu.h index aa421c1..18e6daf 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -323,7 +323,7 @@ * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ /* Memory Bank 0 (NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x04011000 +#define CFG_EBC_PB0AP 0x08033700 #define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 2 (CPLD) initialization */ -- cgit v1.1 From a5f601fd1b1278deae5aa9fc27a232b0d1c1c788 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 26 Nov 2007 19:18:21 +0100 Subject: Cleanup coding style; update CHANGELOG Signed-off-by: Wolfgang Denk --- include/fdt.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/fdt.h b/include/fdt.h index e00559a..48ccfd9 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -4,22 +4,22 @@ #ifndef __ASSEMBLY__ struct fdt_header { - uint32_t magic; /* magic word FDT_MAGIC */ - uint32_t totalsize; /* total size of DT block */ - uint32_t off_dt_struct; /* offset to structure */ - uint32_t off_dt_strings; /* offset to strings */ - uint32_t off_mem_rsvmap; /* offset to memory reserve map */ - uint32_t version; /* format version */ - uint32_t last_comp_version; /* last compatible version */ - - /* version 2 fields below */ - uint32_t boot_cpuid_phys; /* Which physical CPU id we're + uint32_t magic; /* magic word FDT_MAGIC */ + uint32_t totalsize; /* total size of DT block */ + uint32_t off_dt_struct; /* offset to structure */ + uint32_t off_dt_strings; /* offset to strings */ + uint32_t off_mem_rsvmap; /* offset to memory reserve map */ + uint32_t version; /* format version */ + uint32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + uint32_t boot_cpuid_phys; /* Which physical CPU id we're booting on */ /* version 3 fields below */ - uint32_t size_dt_strings; /* size of the strings block */ + uint32_t size_dt_strings; /* size of the strings block */ /* version 17 fields below */ - uint32_t size_dt_struct; /* size of the structure block */ + uint32_t size_dt_struct; /* size of the structure block */ }; struct fdt_reserve_entry { @@ -41,12 +41,12 @@ struct fdt_property { #endif /* !__ASSEMBLY */ -#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ #define FDT_TAGSIZE sizeof(uint32_t) -#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ -#define FDT_END_NODE 0x2 /* End node */ -#define FDT_PROP 0x3 /* Property: name off, +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, size, content */ #define FDT_NOP 0x4 /* nop */ #define FDT_END 0x9 -- cgit v1.1 From 8be760903645af09871be50ad0a6f9ebb62b311d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 27 Nov 2007 11:57:35 +0100 Subject: ppc4xx: Kilauea & Makalu: Fix ext IRQ pin multiplexing After an error in the AMCC 405EX users manual now correctly configure IRQ2 (Kilauea)/IRQ0 (Makalu) as alternate 2 signal for external IRQ usage. Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 14 +++++++------- include/configs/makalu.h | 12 ++++++------ 2 files changed, 13 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 2bb5f24..98d745c 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -441,16 +441,16 @@ {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS(1) NFCE(1) IRQ(7) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS(2) NFCE(2) IRQ(8) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS(3) NFCE(3) IRQ(9) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \ {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_1}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_1}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \ @@ -462,9 +462,9 @@ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \ {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \ {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) DMA_EOT1 */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 IRQ(1) DMA_REQ1 */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 IRQ(0) DMA_ACK1 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \ } \ } diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 18e6daf..e04efb7 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -346,9 +346,9 @@ {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS(1) NFCE(1) IRQ(7) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS(2) NFCE(2) IRQ(8) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS(3) NFCE(3) IRQ(9) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \ {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ @@ -367,9 +367,9 @@ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \ {GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \ {GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 IRQ(2) DMA_EOT1 */ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 IRQ(1) DMA_REQ1 */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO31 IRQ(0) DMA_ACK1 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \ } \ } -- cgit v1.1 From a90921f71d225bf9e0f0fc7b8beadeb8001bf78a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 4 Dec 2007 16:29:48 +0100 Subject: ppc4xx: Yosemite/Yellowstone: Add DTT AD7414 support Signed-off-by: Stefan Roese --- include/configs/yosemite.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 2dde9be..a8eeff9 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -160,6 +160,14 @@ #define CFG_ENV_OFFSET 0x0 #endif /* CFG_ENV_IS_IN_EEPROM */ +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" @@ -273,6 +281,7 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG +#define CONFIG_CMD_DTT #define CONFIG_CMD_ELF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C -- cgit v1.1 From a27044b14a9e93678a82d7b35f202b93e7687abc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 6 Dec 2007 05:58:43 +0100 Subject: ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boards This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by setting the FIXD bit in the SDR0_MFR register. Here a description of the symptoms: Problem Description ------------------------------ If a DMA is performed between memory and PCI with the DMA 1 Controller using prefetch, and as a result uses a special purpose buffer selected by the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29), the first part of the transfer sequence is performed twice. The PPC440SPe PCI Controller requests more data than was needed such that in the case of enforce memory protection, a host CPU exception can occur. No data is corrupted, because data transfer is stopped in the PCI Controller. Prefetch enable is specified by setting DMA Configuration Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0. Behavior that may be observed in a running system --------------------------------------------------------------------------- 1. DMA performance is decreased because of the double access on the PCI bus interface. 2. If an illegal access to some address on the PCI bus is detected at the system level, a machine check or similar system error may occur. Workarounds Available ---------------------------------- 1. Do not program prefetch. Note that a prefetch command cannot be programmed without selecting a special purpose buffer. 2. To avoid crossing a physical boundary of the PCI slave device, add 512 bytes of address to the PCI address range. This patch was originally provided by Pravin M. Bathija from AMCC and slighly changed. Signed-off-by: Pravin M. Bathija Signed-off-by: Stefan Roese --- include/ppc440.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/ppc440.h b/include/ppc440.h index dfa3d2a..21e8836 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -813,6 +813,8 @@ #define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ + +#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ #endif /* CONFIG_440SPE */ /*----------------------------------------------------------------------------- -- cgit v1.1 From cf5933ba1e97a1cd8f5f24070e820f21d976eaeb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 6 Dec 2007 10:21:03 +0100 Subject: ADS5121 Board: fix compile problem. Signed-off-by: Wolfgang Denk --- include/configs/ads5121.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index bb1efdf..58060a8 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -231,7 +231,7 @@ #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #if 0 -#define CFG_I2C_NOPROBES {{0,0x69}} * Don't probe these addrs */ +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #endif /* -- cgit v1.1 From 3c9272813fad84c691d0e4989bb18a3ffebdebfc Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 26 Nov 2007 14:57:45 -0600 Subject: Add common memory fixup function Add the function fdt_fixup_memory() to fixup the /memory node of the fdt Signed-off-by: Kumar Gala --- include/fdt_support.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fdt_support.h b/include/fdt_support.h index 8f781d4..3d6c1a8 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -44,6 +44,7 @@ void do_fixup_by_compat(void *fdt, const char *compat, const char *prop, const void *val, int len, int create); void do_fixup_by_compat_u32(void *fdt, const char *compat, const char *prop, u32 val, int create); +int fdt_fixup_memory(void *blob, u64 start, u64 size); void fdt_fixup_ethernet(void *fdt, bd_t *bd); #ifdef CONFIG_OF_HAS_UBOOT_ENV -- cgit v1.1 From 81b20ccc2d795ae9a1199db5a50ad9c28d1e4d22 Mon Sep 17 00:00:00 2001 From: Michael Schwingen Date: Fri, 7 Dec 2007 23:35:02 +0100 Subject: CFI: support JEDEC flash roms in CFI-flash framework The following patch adds support for non-CFI flash ROMS, by hooking into the CFI flash code and using most of its code, as recently discussed here in the thread "Mixing CFI and non-CFI flashs". Signed-off-by: Michael Schwingen Signed-off-by: Stefan Roese --- include/flash.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/flash.h b/include/flash.h index b0bf733..6e252cc 100644 --- a/include/flash.h +++ b/include/flash.h @@ -52,6 +52,9 @@ typedef struct { ushort ext_addr; /* extended query table address */ ushort cfi_version; /* cfi version */ ushort cfi_offset; /* offset for cfi query */ + ulong addr_unlock1; /* unlock address 1 for AMD flash roms */ + ulong addr_unlock2; /* unlock address 2 for AMD flash roms */ + const char *name; /* human-readable name */ #endif } flash_info_t; @@ -101,6 +104,13 @@ extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offse extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len); #endif /* CFG_FLASH_PROTECTION */ +#ifdef CONFIG_FLASH_CFI_LEGACY +extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info); +extern int jedec_flash_match(flash_info_t *info, ulong base); +#define CFI_CMDSET_AMD_LEGACY 0xFFF0 +#endif + + /*----------------------------------------------------------------------- * return codes from flash_write(): */ -- cgit v1.1 From 7cfc12a7dcfdb350e2ab76db4dafcc30f7e77c2b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 8 Dec 2007 14:47:34 +0100 Subject: ppc4xx: 405EX: Correctly enable USB pins This patch selects the USB data pins in the 405EX GPIO and MFC (multi function control) registers. This is done for the AMCC Kilauea and Makalu eval boards. Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 4 ++-- include/configs/makalu.h | 16 ++++++++-------- include/ppc405.h | 13 +++++++++++++ 3 files changed, 23 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 98d745c..e3f24a44 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -447,8 +447,8 @@ {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ -{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_1}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ -{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_1}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \ {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index e04efb7..2871a6c 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -342,18 +342,18 @@ {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \ {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \ {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \ {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \ diff --git a/include/ppc405.h b/include/ppc405.h index e5051d4..b5ad38f 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -1574,6 +1574,19 @@ #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME 0x02000000 +#define SDR0_PFC1_U0ME 0x00080000 +#define SDR0_PFC1_U0IM 0x00040000 +#define SDR0_PFC1_SIS 0x00020000 +#define SDR0_PFC1_DMAAEN 0x00010000 +#define SDR0_PFC1_DMADEN 0x00008000 +#define SDR0_PFC1_USBEN 0x00004000 +#define SDR0_PFC1_AHBSWAP 0x00000020 +#define SDR0_PFC1_USBBIGEN 0x00000010 +#define SDR0_PFC1_GPT_FREQ 0x0000000f #endif #endif /* __PPC405_H__ */ -- cgit v1.1 From addce57e2e4c49e77ffb2020a84690713bb18b47 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 26 Nov 2007 17:12:24 -0600 Subject: Update MPC8544DS to use libfdt Updated the MPC8544DS config to use libfdt and assume use of aliases for ethernet, pci, and serial for the various fixups that are done. Signed-off-by: Kumar Gala --- include/configs/MPC8544DS.h | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 13e2a2c..fc0b9c2 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -251,13 +251,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8544@0" -#define OF_SOC "soc8544@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -- cgit v1.1 From 50c03c8cf494d91cdec39670d95337c743e16ec9 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 27 Nov 2007 22:42:34 -0600 Subject: Update MPC8544 DS config * Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2 * Removed some misc environment setup * Moved to using fdtfile & fdtaddr as fdt env var names * Enabled CONFIG_CMDLINE_EDITING Signed-off-by: Kumar Gala --- include/configs/MPC8544DS.h | 107 +++++--------------------------------------- 1 file changed, 12 insertions(+), 95 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index fc0b9c2..aeac35a 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -422,6 +422,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -471,10 +472,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETHADDR 00:E0:0C:02:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD #endif #define CONFIG_IPADDR 192.168.1.251 @@ -484,8 +481,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOOTFILE 8544ds/uImage.uboot #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ @@ -495,65 +492,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BAUDRATE 115200 -#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) -#define PCIE_ENV \ - "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ - "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ - "pcieerr=md ${a}020 1; md ${a}e00 e;" \ - "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ - "pci d.w $b.0 56 1;" \ - "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \ - "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \ - "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \ - "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \ - "pci w $b.0 130 ffffffff\0" \ - "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ - "pcie1regs=setenv a e000a; run pciereg\0" \ - "pcie2regs=setenv a e0009; run pciereg\0" \ - "pcie3regs=setenv a e000b; run pciereg\0" \ - "pcie1cfg=setenv b 3; run pciecfg\0" \ - "pcie2cfg=setenv b 5; run pciecfg\0" \ - "pcie3cfg=setenv b 0; run pciecfg\0" \ - "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ - "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \ - "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \ - "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \ - "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \ - "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0" -#else -#define PCIE_ENV "" -#endif - -#if defined(CONFIG_PCI1) -#define PCI_ENV \ - "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ - "echo e;md ${a}e00 9\0" \ - "pci1regs=setenv a e0008; run pcireg\0" \ - "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ - "pci d.w $b.0 56 1\0" \ - "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ - "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \ - "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \ - "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0" -#else -#define PCI_ENV "" -#endif - -#if defined(CONFIG_TSEC_ENET) -#define ENET_ENV \ - "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ - "md ${a}098 2\0" \ - "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ - "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ - "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ - "echo mib;md ${a}680 31\0" \ - "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ - "enet1regs=setenv a e0024; run enetreg\0" \ - "enet3regs=setenv a e0026; run enetreg\0" -#else -#define ENET_ENV "" -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ @@ -566,29 +504,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8544ds/ramdisk.uboot\0" \ - "dtbaddr=c00000\0" \ - "dtbfile=8544ds/mpc8544ds.dtb\0" \ - "bdev=sda3\0" \ - "eoi=mw e00400b0 0\0" \ - "iack=md e00400a0 1\0" \ - "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ - "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ - "ddrregs=setenv a e0002; run ddrreg\0" \ - "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ - "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ - "guregs=setenv a e00e0; run gureg\0" \ - "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ - "ecmregs=setenv a e0001; run ecmreg\0" \ - "lawregs=md e0000c08 4b\0" \ - "lbcregs=md e0005000 36\0" \ - "dma0regs=md e0021100 12\0" \ - "dma1regs=md e0021180 12\0" \ - "dma2regs=md e0021200 12\0" \ - "dma3regs=md e0021280 12\0" \ - PCIE_ENV \ - PCI_ENV \ - ENET_ENV - + "fdtaddr=c00000\0" \ + "fdtfile=8544ds/mpc8544ds.dtb\0" \ + "bdev=sda3\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -596,23 +514,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" - + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr $ramdiskaddr $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #endif /* __CONFIG_H */ -- cgit v1.1 From f59b55a5b8fcadaa99781ba48e7a38e956afa527 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 27 Nov 2007 23:25:02 -0600 Subject: Stop using immap_t for guts offset on 85xx In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala --- include/asm-ppc/immap_85xx.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 496fc72..df53bd2 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1617,6 +1617,9 @@ typedef struct ccsr_gur { char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; +#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) +#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) + #define PORDEVSR_PCI (0x00800000) /* PCI Mode */ typedef struct immap { @@ -1634,8 +1637,6 @@ typedef struct immap { ccsr_tsec_t im_tsec2; ccsr_pic_t im_pic; ccsr_cpm_t im_cpm; - ccsr_rio_t im_rio; - ccsr_gur_t im_gur; } immap_t; extern immap_t *immr; -- cgit v1.1 From aafeefbdb8b029f5ca2a195598d0a501a606eea9 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 28 Nov 2007 00:36:33 -0600 Subject: Stop using immap_t for cpm offset on 85xx In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers instead of getting it via &immap->im_cpm. Signed-off-by: Kumar Gala --- include/asm-ppc/immap_85xx.h | 4 +++- include/asm-ppc/iopin_85xx.h | 40 ++++++++++++++++++++-------------------- include/ioports.h | 2 +- 3 files changed, 24 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index df53bd2..393fdda 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1636,9 +1636,11 @@ typedef struct immap { ccsr_tsec_t im_tsec1; ccsr_tsec_t im_tsec2; ccsr_pic_t im_pic; - ccsr_cpm_t im_cpm; } immap_t; +#define CFG_MPC85xx_CPM_OFFSET (0x80000) +#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET) + extern immap_t *immr; #endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h index f854df6..daddb55 100644 --- a/include/asm-ppc/iopin_85xx.h +++ b/include/asm-ppc/iopin_85xx.h @@ -23,121 +23,121 @@ typedef struct { extern __inline__ void iopin_set_high (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_low (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_high (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_low (iopin_t * iopin) { - volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_out (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_in (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_out (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_in (iopin_t * iopin) { - volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_odr (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_act (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_odr (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_act (iopin_t * iopin) { - volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_ded (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_gen (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_ded (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_gen (iopin_t * iopin) { - volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } diff --git a/include/ioports.h b/include/ioports.h index cfba667..1134ea5 100644 --- a/include/ioports.h +++ b/include/ioports.h @@ -26,7 +26,7 @@ typedef struct { * a 0x20 byte boundary */ #ifdef CONFIG_MPC85xx -#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20)) +#define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20)) #else #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) #endif -- cgit v1.1 From 5ce715802f6c50dc78b3405b92f184b1e3710519 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 28 Nov 2007 22:40:31 -0600 Subject: Update MPC8560 ADS to use libfdt Updated the MPC8560 ADS config to use libfdt and assume use of aliases for ethernet, pci, and serial for the various fixups that are done. Signed-off-by: Kumar Gala --- include/configs/MPC8560ADS.h | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index a8f362f..a24ac15 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -289,13 +289,9 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8560@0" -#define OF_SOC "soc8560@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C @@ -525,6 +521,8 @@ #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 -- cgit v1.1 From 0fd5ec66b10521a057ad73e69ab5f0f9eafba255 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 28 Nov 2007 22:54:27 -0600 Subject: Update MPC8540 ADS to use libfdt Updated the MPC8540 ADS config to use libfdt and assume use of aliases for ethernet, pci, and serial for the various fixups that are done. Signed-off-by: Kumar Gala --- include/configs/MPC8540ADS.h | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index be603ac..006644d 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -298,13 +298,9 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8540@0" -#define OF_SOC "soc8540@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 -- cgit v1.1 From b90d25497625b90ffa3f2911a0895ca237556ff5 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 Nov 2007 00:11:44 -0600 Subject: Update MPC85xx CDS to use libfdt Updated the MPC85xx CDS config to use libfdt and assume use of aliases for ethernet, pci, and serial for the various fixups that are done. Signed-off-by: Kumar Gala --- include/configs/MPC8541CDS.h | 11 +++-------- include/configs/MPC8548CDS.h | 11 +++-------- include/configs/MPC8555CDS.h | 11 +++-------- 3 files changed, 9 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 8dda665..fc1b367 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -309,14 +309,9 @@ extern unsigned long get_clock_freq(void); #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8541@0" -#define OF_SOC "soc8541@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" -#define OF_PCI "pci@e0008000" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4edc7fd..95256f7 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -333,14 +333,9 @@ extern unsigned long get_clock_freq(void); #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8548@0" -#define OF_SOC "soc8548@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" -#define OF_PCI "pci@e0008000" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index c414bf0..76631c6 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -309,14 +309,9 @@ extern unsigned long get_clock_freq(void); #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8555@0" -#define OF_SOC "soc8555@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" -#define OF_PCI "pci@e0008000" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C -- cgit v1.1 From 1563f56e0c68f6920f956382d6d13bee3f01c0f7 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 14 Nov 2007 15:52:06 -0500 Subject: Add PCI Express support on MPC8568MDS Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala --- include/configs/MPC8568MDS.h | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index b9366cc..cf79257 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -33,7 +33,10 @@ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ -#define CONFIG_PCI +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI1 1 /* PCI controller */ +#define CONFIG_PCIE1 1 /* PCIE controller */ +#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE @@ -87,6 +90,9 @@ extern unsigned long get_clock_freq(void); #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) + /* * DDR Setup */ @@ -325,12 +331,12 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ -#define CFG_PEX_MEM_BASE 0xa0000000 -#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE -#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PEX_IO_BASE 0x00000000 -#define CFG_PEX_IO_PHYS 0xe2800000 -#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */ +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe2800000 +#define CFG_PCIE1_IO_SIZE 0x00800000 /* 8M */ #define CFG_SRIO_MEM_BASE 0xc0000000 @@ -383,6 +389,11 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + #endif /* CONFIG_PCI */ #ifndef CONFIG_NET_MULTI -- cgit v1.1 From c480861bf000156e6a3e932c258db59ff2212dd3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 Nov 2007 01:06:19 -0600 Subject: Update MPC8568 MDS to use libfdt Updated the MPC8568 MDS config to use libfdt and assume use of aliases for ethernet, pci, and serial for the various fixups that are done. Signed-off-by: Kumar Gala --- include/configs/MPC8568MDS.h | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index cf79257..2f4bc70 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -296,14 +296,9 @@ extern unsigned long get_clock_freq(void); #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8568@0" -#define OF_SOC "soc8568@e0000000" -#define OF_QE "qe@e0080000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * I2C -- cgit v1.1 From 04db400892da37b76a585e332a0c137954ad2015 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 Nov 2007 02:10:09 -0600 Subject: Stop using immap_t on 85xx In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala --- include/asm-ppc/immap_85xx.h | 44 ++++++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 393fdda..d769d70 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -720,11 +720,10 @@ typedef struct ccsr_tsec { } ccsr_tsec_t; /* - * PIC Registers(0x2_6000-0x4_0000-0x8_0000) + * PIC Registers(0x4_0000-0x8_0000) */ typedef struct ccsr_pic { - char res0[106496]; /* 0x26000-0x40000 */ - char res1[64]; + char res1[64]; /* 0x40000 */ uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ char res2[12]; uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ @@ -1617,30 +1616,27 @@ typedef struct ccsr_gur { char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; -#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) -#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) - #define PORDEVSR_PCI (0x00800000) /* PCI Mode */ -typedef struct immap { - ccsr_local_ecm_t im_local_ecm; - ccsr_ddr_t im_ddr; - ccsr_i2c_t im_i2c; - ccsr_duart_t im_duart; - ccsr_lbc_t im_lbc; - ccsr_pcix_t im_pcix; - ccsr_pcix_t im_pcix2; - char reserved[90112]; - ccsr_l2cache_t im_l2cache; - ccsr_dma_t im_dma; - ccsr_tsec_t im_tsec1; - ccsr_tsec_t im_tsec2; - ccsr_pic_t im_pic; -} immap_t; - +#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) +#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) +#define CFG_MPC85xx_ECM_OFFSET (0x0000) +#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET) +#define CFG_MPC85xx_DDR_OFFSET (0x2000) +#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET) +#define CFG_MPC85xx_LBC_OFFSET (0x5000) +#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET) +#define CFG_MPC85xx_PCIX_OFFSET (0x8000) +#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET) +#define CFG_MPC85xx_PCIX2_OFFSET (0x9000) +#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET) +#define CFG_MPC85xx_L2_OFFSET (0x20000) +#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET) +#define CFG_MPC85xx_DMA_OFFSET (0x21000) +#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET) +#define CFG_MPC85xx_PIC_OFFSET (0x40000) +#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET) #define CFG_MPC85xx_CPM_OFFSET (0x80000) #define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET) -extern immap_t *immr; - #endif /*__IMMAP_85xx__*/ -- cgit v1.1 From a853d56c59b33415304531443633808736acfc6e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 Nov 2007 02:18:59 -0600 Subject: Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx We already had defines for LAWAR_TRGT_IF_* that we should use rather than creating new ones. Also, added some missing defines for PCIE targets. Signed-off-by: Kumar Gala --- include/asm-ppc/mmu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index b3cfa9b..3d40332 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -413,7 +413,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_PEX 0x00200000 +#define LAWAR_TRGT_IF_PCIE1 0x00200000 +#define LAWAR_TRGT_IF_PCIE2 0x00100000 +#define LAWAR_TRGT_IF_PCIE3 0x00300000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 -- cgit v1.1 From 22abb2d2eaf7b795a6923c6273ec9cb53fda9a10 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 Nov 2007 10:34:28 -0600 Subject: Update Freescale MPC85xx ADS/CDS/MDS board config * Removed some misc environment setup * Enabled CONFIG_CMDLINE_EDITING Signed-off-by: Kumar Gala --- include/configs/MPC8540ADS.h | 1 + include/configs/MPC8541CDS.h | 1 + include/configs/MPC8548CDS.h | 90 +------------------------------------------- include/configs/MPC8555CDS.h | 1 + include/configs/MPC8560ADS.h | 1 + include/configs/MPC8568MDS.h | 1 + 6 files changed, 7 insertions(+), 88 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 006644d..55510f3 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -437,6 +437,7 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index fc1b367..d7eb5fa 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -429,6 +429,7 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 95256f7..eace283 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -490,6 +490,7 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -563,72 +564,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BAUDRATE 115200 -#if defined(CONFIG_PCIE1) -#define PCIE_ENV \ - "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ - "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ - "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ - "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ - "pci d $b.0 130 1\0" \ - "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \ - "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\ - "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ - "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ - "pcie1regs=setenv a e000a; run pciereg\0" \ - "pcie1cfg=setenv b 3; run pciecfg\0" \ - "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ - "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" -#else -#define PCIE_ENV "" -#endif - -#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) -#define PCI_ENV \ - "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ - "echo e;md ${a}e00 9\0" \ - "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \ - "pci d.w $b.0 56 1\0" \ - "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ - "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" -#else -#define PCI_ENV "" -#endif - -#if defined(CONFIG_PCI1) -#define PCI_ENV1 \ - "pci1regs=setenv a e0008; run pcireg\0" \ - "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \ - "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0" -#else -#define PCI_ENV1 "" -#endif - -#if defined(CONFIG_PCI2) -#define PCI_ENV2 \ - "pci2regs=setenv a e0009; run pcireg\0" \ - "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \ - "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0" -#else -#define PCI_ENV2 "" -#endif - -#if defined(CONFIG_TSEC_ENET) -#define ENET_ENV \ - "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ - "md ${a}098 2\0" \ - "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ - "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ - "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ - "echo mib;md ${a}680 31\0" \ - "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ - "enet1regs=setenv a e0024; run enetreg\0" \ - "enet2regs=setenv a e0025; run enetreg\0" \ - "enet3regs=setenv a e0026; run enetreg\0" \ - "enet4regs=setenv a e0027; run enetreg\0" -#else -#define ENET_ENV "" -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ @@ -642,28 +577,7 @@ extern unsigned long get_clock_freq(void); "ramdiskaddr=2000000\0" \ "ramdiskfile=ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ - "fdtfile=mpc8548cds.dtb\0" \ - "eoi=mw e00400b0 0\0" \ - "iack=md e00400a0 1\0" \ - "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ - "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ - "ddrregs=setenv a e0002; run ddrreg\0" \ - "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ - "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ - "guregs=setenv a e00e0; run gureg\0" \ - "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ - "ecmregs=setenv a e0001; run ecmreg\0" \ - "lawregs=md e0000c08 4b\0" \ - "lbcregs=md e0005000 36\0" \ - "dma0regs=md e0021100 12\0" \ - "dma1regs=md e0021180 12\0" \ - "dma2regs=md e0021200 12\0" \ - "dma3regs=md e0021280 12\0" \ - PCIE_ENV \ - PCI_ENV \ - PCI_ENV1 \ - PCI_ENV2 \ - ENET_ENV + "fdtfile=mpc8548cds.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 76631c6..8ae4ef0 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -429,6 +429,7 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index a24ac15..cdd8ad4 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -467,6 +467,7 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x1000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 2f4bc70..2cf48fb 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -458,6 +458,7 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -- cgit v1.1 From d435793229ce29a42797c1edc39f5b34f987f91a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 7 Dec 2007 04:59:26 -0600 Subject: Handle Asynchronous DDR clock on 85xx The MPC8572 introduces the concept of an asynchronous DDR clock with regards to the platform clock. Introduce get_ddr_freq() to report the DDR freq regardless of sync/async mode. Signed-off-by: Kumar Gala --- include/common.h | 1 + include/e500.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/common.h b/include/common.h index 63ac8b0..01957e3 100644 --- a/include/common.h +++ b/include/common.h @@ -497,6 +497,7 @@ ulong get_bus_freq (ulong); #if defined(CONFIG_MPC85xx) typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); +ulong get_ddr_freq (ulong); #endif #if defined(CONFIG_MPC86xx) typedef MPC86xx_SYS_INFO sys_info_t; diff --git a/include/e500.h b/include/e500.h index 8e3bf8c..0d73260 100644 --- a/include/e500.h +++ b/include/e500.h @@ -12,6 +12,7 @@ typedef struct { unsigned long freqProcessor; unsigned long freqSystemBus; + unsigned long freqDDRBus; } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ -- cgit v1.1 From 82ac8c97145a4c3bf8b3dbfad00fa96e920f9b9c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 7 Dec 2007 12:04:30 -0600 Subject: Update Freescale MPC85xx ADS/CDS/MDS board config * Enabled CONFIG_CMD_ELF Signed-off-by: Kumar Gala --- include/configs/MPC8540ADS.h | 1 + include/configs/MPC8541CDS.h | 1 + include/configs/MPC8544DS.h | 1 + include/configs/MPC8548CDS.h | 1 + include/configs/MPC8555CDS.h | 1 + include/configs/MPC8560ADS.h | 1 + include/configs/MPC8568MDS.h | 1 + 7 files changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 55510f3..35e1d63 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -420,6 +420,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index d7eb5fa..d2e7237 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -417,6 +417,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index aeac35a..b8cd50b 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -406,6 +406,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index eace283..95affa5 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -478,6 +478,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 8ae4ef0..90ef3d6 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -417,6 +417,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index cdd8ad4..d4e0de0 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -446,6 +446,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 2cf48fb..3822c1b 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -446,6 +446,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI -- cgit v1.1 From 8ff3de61fc5f9b3b21647bce081a3b7f710f0d4d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 7 Dec 2007 12:17:34 -0600 Subject: Handle MPC85xx PCIe reset errata (PCI-Ex 38) On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala --- include/asm-ppc/immap_fsl_pci.h | 4 +++- include/configs/MPC8544DS.h | 1 + include/configs/MPC8548CDS.h | 1 + include/configs/MPC8568MDS.h | 1 + 4 files changed, 6 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h index bd732b6..6715064 100644 --- a/include/asm-ppc/immap_fsl_pci.h +++ b/include/asm-ppc/immap_fsl_pci.h @@ -144,7 +144,9 @@ typedef struct ccsr_pci { u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ - char res23[456]; /* (- #x1000 #xe38) 456 */ + char res23[200]; + u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ + char res24[252]; } ccsr_fsl_pci_t; #endif /*__IMMAP_fsl_pci__*/ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index b8cd50b..545a76c 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -40,6 +40,7 @@ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 95affa5..3f382e5 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -42,6 +42,7 @@ #undef CONFIG_RIO #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 3822c1b..59f490e 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -37,6 +37,7 @@ #define CONFIG_PCI1 1 /* PCI controller */ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE -- cgit v1.1 From 42026c9cb3a76849b41e6e24abfb7b56807a5c1a Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 11 Dec 2007 13:59:57 +0100 Subject: CFI: synchronize command offsets with Linux CFI driver Fixes non-working CFI Flash on the Inka4x0 board. Signed-off-by: Bartlomiej Sieka --- include/flash.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/flash.h b/include/flash.h index 6e252cc..2ed1e20 100644 --- a/include/flash.h +++ b/include/flash.h @@ -80,6 +80,7 @@ typedef struct { #define FLASH_CFI_X8 0x00 #define FLASH_CFI_X16 0x01 #define FLASH_CFI_X8X16 0x02 +#define FLASH_CFI_X16X32 0x05 /* convert between bit value and numeric value */ #define CFI_FLASH_SHIFT_WIDTH 3 -- cgit v1.1 From 812711ce6b3a386125dcf0d6a59588e461abbb87 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Thu, 13 Dec 2007 12:56:31 +0100 Subject: Implement __raw_{read,write}[bwl] on all architectures This adds implementations of __raw_read[bwl] and __raw_write[bwl] to m68k, ppc, nios and nios2. The m68k and ppc implementations were taken from Linux. Signed-off-by: Haavard Skinnemoen --- include/asm-m68k/io.h | 14 ++++++++++++++ include/asm-nios/io.h | 8 ++++++++ include/asm-nios2/io.h | 8 ++++++++ include/asm-ppc/io.h | 32 +++++++++++++++++++++++++++++++- 4 files changed, 61 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index e14a581..29b3972 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -28,6 +28,20 @@ #include +/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates + * two accesses to memory, which may be undesirable for some devices. + */ +#define __raw_readb(addr) \ + ({ u8 __v = (*(volatile u8 *) (addr)); __v; }) +#define __raw_readw(addr) \ + ({ u16 __v = (*(volatile u16 *) (addr)); __v; }) +#define __raw_readl(addr) \ + ({ u32 __v = (*(volatile u32 *) (addr)); __v; }) + +#define __raw_writeb(addr,b) (void)((*(volatile u8 *) (addr)) = (b)) +#define __raw_writew(addr,w) (void)((*(volatile u16 *) (addr)) = (w)) +#define __raw_writel(addr,l) (void)((*(volatile u32 *) (addr)) = (l)) + #define readb(addr) in_8((volatile u8 *)(addr)) #define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) #if !defined(__BIG_ENDIAN) diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h index d77695a..08e46a3 100644 --- a/include/asm-nios/io.h +++ b/include/asm-nios/io.h @@ -23,6 +23,14 @@ #ifndef __ASM_NIOS_IO_H_ #define __ASM_NIOS_IO_H_ +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + #define readb(addr)\ ({unsigned char val;\ asm volatile( " pfxio 0 \n"\ diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index 5bb5322..54cbd57 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -33,6 +33,14 @@ extern unsigned char inb (unsigned char *port); extern unsigned short inw (unsigned short *port); extern unsigned inl (unsigned port); +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + #define readb(addr)\ ({unsigned char val;\ asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 11dfa1c..86fe8dc 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -121,13 +121,43 @@ static inline void isync(void) #define iobarrier_w() eieio() /* + * Non ordered and non-swapping "raw" accessors + */ +#define __iomem +#define PCI_FIX_ADDR(addr) (addr) + +static inline unsigned char __raw_readb(const volatile void __iomem *addr) +{ + return *(volatile unsigned char *)PCI_FIX_ADDR(addr); +} +static inline unsigned short __raw_readw(const volatile void __iomem *addr) +{ + return *(volatile unsigned short *)PCI_FIX_ADDR(addr); +} +static inline unsigned int __raw_readl(const volatile void __iomem *addr) +{ + return *(volatile unsigned int *)PCI_FIX_ADDR(addr); +} +static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) +{ + *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v; +} +static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) +{ + *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v; +} +static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) +{ + *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v; +} + +/* * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. * * Read operations have additional twi & isync to make sure the read * is actually performed (i.e. the data has come back) before we start * executing any following instructions. */ -#define __iomem extern inline int in_8(const volatile unsigned char __iomem *addr) { int ret; -- cgit v1.1 From 4d7d6936eb29af7cca330937808312aa5f61454d Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Thu, 13 Dec 2007 12:56:33 +0100 Subject: Introduce map_physmem() and unmap_physmem() map_physmem() returns a virtual address which can be used to access a given physical address without involving the cache. unmap_physmem() should be called when the virtual address returned by map_physmem() is no longer needed. This patch adds a stub implementation which simply returns the physical address cast to a uchar * for all architectures except AVR32, which converts the physical address to an uncached virtual mapping. unmap_physmem() is a no-op on all architectures, but if any architecture needs to do such mappings through the TLB, this is the hook where those TLB entries can be invalidated. Signed-off-by: Haavard Skinnemoen --- include/asm-arm/io.h | 26 ++++++++++++++++++++++++++ include/asm-avr32/io.h | 32 ++++++++++++++++++++++++++++++++ include/asm-blackfin/io.h | 26 ++++++++++++++++++++++++++ include/asm-i386/io.h | 26 ++++++++++++++++++++++++++ include/asm-m68k/io.h | 27 +++++++++++++++++++++++++++ include/asm-microblaze/io.h | 26 ++++++++++++++++++++++++++ include/asm-mips/io.h | 26 ++++++++++++++++++++++++++ include/asm-nios/io.h | 26 ++++++++++++++++++++++++++ include/asm-nios2/io.h | 26 ++++++++++++++++++++++++++ include/asm-ppc/io.h | 26 ++++++++++++++++++++++++++ 10 files changed, 267 insertions(+) (limited to 'include') diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index 47c18e7..029b7f9 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -34,6 +34,32 @@ static inline void sync(void) } /* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +/* * Generic virtual read/write. Note that we don't support half-word * read/writes. We define __arch_*[bl] here, and leave __arch_*w * to the architecture specific code. diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h index 3c0d569..ba14674 100644 --- a/include/asm-avr32/io.h +++ b/include/asm-avr32/io.h @@ -93,4 +93,36 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + * + * This implementation works for memory below 512MiB (flash, etc.) as + * well as above 3.5GiB (internal peripherals.) + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (1 << 7) +#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) +#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0)) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + if (flags == MAP_WRBACK) + return (void *)P1SEGADDR(paddr); + else + return (void *)P2SEGADDR(paddr); +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long len) +{ + +} + #endif /* __ASM_AVR32_IO_H */ diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 332d2c6..512e13d 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -41,6 +41,32 @@ static inline void sync(void) } /* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +/* * These are for ISA/PCI shared memory _only_ and should never be used * on any other type of memory, including Zorro memory. They are meant to * access the bus in the bus byte order which is little-endian!. diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h index e64d788..db4f442 100644 --- a/include/asm-i386/io.h +++ b/include/asm-i386/io.h @@ -205,4 +205,30 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 29b3972..91d7592 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -232,4 +232,31 @@ static inline void sync(void) * compatibility (CFI driver) */ } + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* __ASM_M68K_IO_H__ */ diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h index 1c77ade..90d1842 100644 --- a/include/asm-microblaze/io.h +++ b/include/asm-microblaze/io.h @@ -129,4 +129,30 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* __MICROBLAZE_IO_H__ */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 1e060f7..e27d1f1 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -465,4 +465,30 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* _ASM_IO_H */ diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h index 08e46a3..6fc339f 100644 --- a/include/asm-nios/io.h +++ b/include/asm-nios/io.h @@ -109,4 +109,30 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* __ASM_NIOS_IO_H_ */ diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index 54cbd57..a52b95c 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -29,6 +29,32 @@ static inline void sync(void) __asm__ __volatile__ ("sync" : : : "memory"); } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + extern unsigned char inb (unsigned char *port); extern unsigned short inw (unsigned short *port); extern unsigned inl (unsigned port); diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 86fe8dc..91c9c1e 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -238,4 +238,30 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif -- cgit v1.1 From 36f28f8a9605ee5dcfa330482cfc62171261af97 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 29 Oct 2007 13:09:56 +0100 Subject: AVR32: Rename at32ap7000 -> at32ap700x The SoC-specific code for all the AT32AP700x CPUs is practically identical; the only difference is that some chips have less features than others. By doing this rename, we can add support for the AP7000 derivatives simply by making some features conditional. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap7000/clk.h | 70 -------- include/asm-avr32/arch-at32ap7000/gpio.h | 212 ---------------------- include/asm-avr32/arch-at32ap7000/hmatrix2.h | 232 ------------------------- include/asm-avr32/arch-at32ap7000/memory-map.h | 66 ------- include/asm-avr32/arch-at32ap7000/mmc.h | 96 ---------- include/asm-avr32/arch-at32ap700x/clk.h | 70 ++++++++ include/asm-avr32/arch-at32ap700x/gpio.h | 212 ++++++++++++++++++++++ include/asm-avr32/arch-at32ap700x/hmatrix2.h | 232 +++++++++++++++++++++++++ include/asm-avr32/arch-at32ap700x/memory-map.h | 66 +++++++ include/asm-avr32/arch-at32ap700x/mmc.h | 96 ++++++++++ 10 files changed, 676 insertions(+), 676 deletions(-) delete mode 100644 include/asm-avr32/arch-at32ap7000/clk.h delete mode 100644 include/asm-avr32/arch-at32ap7000/gpio.h delete mode 100644 include/asm-avr32/arch-at32ap7000/hmatrix2.h delete mode 100644 include/asm-avr32/arch-at32ap7000/memory-map.h delete mode 100644 include/asm-avr32/arch-at32ap7000/mmc.h create mode 100644 include/asm-avr32/arch-at32ap700x/clk.h create mode 100644 include/asm-avr32/arch-at32ap700x/gpio.h create mode 100644 include/asm-avr32/arch-at32ap700x/hmatrix2.h create mode 100644 include/asm-avr32/arch-at32ap700x/memory-map.h create mode 100644 include/asm-avr32/arch-at32ap700x/mmc.h (limited to 'include') diff --git a/include/asm-avr32/arch-at32ap7000/clk.h b/include/asm-avr32/arch-at32ap7000/clk.h deleted file mode 100644 index 7e20d97..0000000 --- a/include/asm-avr32/arch-at32ap7000/clk.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ARCH_CLK_H__ -#define __ASM_AVR32_ARCH_CLK_H__ - -#ifdef CONFIG_PLL -#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) -#else -#define MAIN_CLK_RATE (CFG_OSC0_HZ) -#endif - -static inline unsigned long get_cpu_clk_rate(void) -{ - return MAIN_CLK_RATE >> CFG_CLKDIV_CPU; -} -static inline unsigned long get_hsb_clk_rate(void) -{ - return MAIN_CLK_RATE >> CFG_CLKDIV_HSB; -} -static inline unsigned long get_pba_clk_rate(void) -{ - return MAIN_CLK_RATE >> CFG_CLKDIV_PBA; -} -static inline unsigned long get_pbb_clk_rate(void) -{ - return MAIN_CLK_RATE >> CFG_CLKDIV_PBB; -} - -/* Accessors for specific devices. More will be added as needed. */ -static inline unsigned long get_sdram_clk_rate(void) -{ - return get_hsb_clk_rate(); -} -static inline unsigned long get_usart_clk_rate(unsigned int dev_id) -{ - return get_pba_clk_rate(); -} -static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) -{ - return get_pbb_clk_rate(); -} -static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) -{ - return get_hsb_clk_rate(); -} -static inline unsigned long get_mci_clk_rate(void) -{ - return get_pbb_clk_rate(); -} - -#endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/gpio.h b/include/asm-avr32/arch-at32ap7000/gpio.h deleted file mode 100644 index e4812d4..0000000 --- a/include/asm-avr32/arch-at32ap7000/gpio.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ARCH_GPIO_H__ -#define __ASM_AVR32_ARCH_GPIO_H__ - -#include - -#define NR_GPIO_CONTROLLERS 5 - -/* - * Pin numbers identifying specific GPIO pins on the chip. - */ -#define GPIO_PIOA_BASE (0) -#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0) -#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1) -#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2) -#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3) -#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4) -#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5) -#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6) -#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7) -#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8) -#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9) -#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10) -#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11) -#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12) -#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13) -#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14) -#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15) -#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16) -#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17) -#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18) -#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19) -#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20) -#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21) -#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22) -#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23) -#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24) -#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25) -#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26) -#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27) -#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28) -#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29) -#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30) -#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31) - -#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) -#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0) -#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1) -#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2) -#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3) -#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4) -#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5) -#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6) -#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7) -#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8) -#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9) -#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10) -#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11) -#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12) -#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13) -#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14) -#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15) -#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16) -#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17) -#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18) -#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19) -#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20) -#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21) -#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22) -#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23) -#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24) -#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25) -#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26) -#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27) -#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28) -#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29) -#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30) - -#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) -#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0) -#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1) -#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2) -#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3) -#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4) -#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5) -#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6) -#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7) -#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8) -#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9) -#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10) -#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11) -#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12) -#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13) -#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14) -#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15) -#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16) -#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17) -#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18) -#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19) -#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20) -#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21) -#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22) -#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23) -#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24) -#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25) -#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26) -#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27) -#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28) -#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29) -#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30) -#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31) - -#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) -#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0) -#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1) -#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2) -#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3) -#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4) -#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5) -#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6) -#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7) -#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8) -#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9) -#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10) -#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11) -#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12) -#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13) -#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14) -#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15) -#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16) -#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17) - -#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) -#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0) -#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1) -#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2) -#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3) -#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4) -#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5) -#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6) -#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7) -#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8) -#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9) -#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10) -#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11) -#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12) -#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13) -#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14) -#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15) -#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16) -#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17) -#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18) -#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19) -#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20) -#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21) -#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22) -#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23) -#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24) -#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25) -#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26) - -static inline void *gpio_pin_to_addr(unsigned int pin) -{ - switch (pin >> 5) { - case 0: - return (void *)PIOA_BASE; - case 1: - return (void *)PIOB_BASE; - case 2: - return (void *)PIOC_BASE; - case 3: - return (void *)PIOD_BASE; - case 4: - return (void *)PIOE_BASE; - default: - return NULL; - } -} - -void gpio_select_periph_A(unsigned int pin, int use_pullup); -void gpio_select_periph_B(unsigned int pin, int use_pullup); - -void gpio_enable_ebi(void); -void gpio_enable_usart0(void); -void gpio_enable_usart1(void); -void gpio_enable_usart2(void); -void gpio_enable_usart3(void); -void gpio_enable_macb0(void); -void gpio_enable_macb1(void); -void gpio_enable_mmci(void); - -#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h deleted file mode 100644 index b0e787a..0000000 --- a/include/asm-avr32/arch-at32ap7000/hmatrix2.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Register definition for the High-speed Bus Matrix - */ -#ifndef __ASM_AVR32_HMATRIX2_H__ -#define __ASM_AVR32_HMATRIX2_H__ - -/* HMATRIX2 register offsets */ -#define HMATRIX2_MCFG0 0x0000 -#define HMATRIX2_MCFG1 0x0004 -#define HMATRIX2_MCFG2 0x0008 -#define HMATRIX2_MCFG3 0x000c -#define HMATRIX2_MCFG4 0x0010 -#define HMATRIX2_MCFG5 0x0014 -#define HMATRIX2_MCFG6 0x0018 -#define HMATRIX2_MCFG7 0x001c -#define HMATRIX2_MCFG8 0x0020 -#define HMATRIX2_MCFG9 0x0024 -#define HMATRIX2_MCFG10 0x0028 -#define HMATRIX2_MCFG11 0x002c -#define HMATRIX2_MCFG12 0x0030 -#define HMATRIX2_MCFG13 0x0034 -#define HMATRIX2_MCFG14 0x0038 -#define HMATRIX2_MCFG15 0x003c -#define HMATRIX2_SCFG0 0x0040 -#define HMATRIX2_SCFG1 0x0044 -#define HMATRIX2_SCFG2 0x0048 -#define HMATRIX2_SCFG3 0x004c -#define HMATRIX2_SCFG4 0x0050 -#define HMATRIX2_SCFG5 0x0054 -#define HMATRIX2_SCFG6 0x0058 -#define HMATRIX2_SCFG7 0x005c -#define HMATRIX2_SCFG8 0x0060 -#define HMATRIX2_SCFG9 0x0064 -#define HMATRIX2_SCFG10 0x0068 -#define HMATRIX2_SCFG11 0x006c -#define HMATRIX2_SCFG12 0x0070 -#define HMATRIX2_SCFG13 0x0074 -#define HMATRIX2_SCFG14 0x0078 -#define HMATRIX2_SCFG15 0x007c -#define HMATRIX2_PRAS0 0x0080 -#define HMATRIX2_PRBS0 0x0084 -#define HMATRIX2_PRAS1 0x0088 -#define HMATRIX2_PRBS1 0x008c -#define HMATRIX2_PRAS2 0x0090 -#define HMATRIX2_PRBS2 0x0094 -#define HMATRIX2_PRAS3 0x0098 -#define HMATRIX2_PRBS3 0x009c -#define HMATRIX2_PRAS4 0x00a0 -#define HMATRIX2_PRBS4 0x00a4 -#define HMATRIX2_PRAS5 0x00a8 -#define HMATRIX2_PRBS5 0x00ac -#define HMATRIX2_PRAS6 0x00b0 -#define HMATRIX2_PRBS6 0x00b4 -#define HMATRIX2_PRAS7 0x00b8 -#define HMATRIX2_PRBS7 0x00bc -#define HMATRIX2_PRAS8 0x00c0 -#define HMATRIX2_PRBS8 0x00c4 -#define HMATRIX2_PRAS9 0x00c8 -#define HMATRIX2_PRBS9 0x00cc -#define HMATRIX2_PRAS10 0x00d0 -#define HMATRIX2_PRBS10 0x00d4 -#define HMATRIX2_PRAS11 0x00d8 -#define HMATRIX2_PRBS11 0x00dc -#define HMATRIX2_PRAS12 0x00e0 -#define HMATRIX2_PRBS12 0x00e4 -#define HMATRIX2_PRAS13 0x00e8 -#define HMATRIX2_PRBS13 0x00ec -#define HMATRIX2_PRAS14 0x00f0 -#define HMATRIX2_PRBS14 0x00f4 -#define HMATRIX2_PRAS15 0x00f8 -#define HMATRIX2_PRBS15 0x00fc -#define HMATRIX2_MRCR 0x0100 -#define HMATRIX2_SFR0 0x0110 -#define HMATRIX2_SFR1 0x0114 -#define HMATRIX2_SFR2 0x0118 -#define HMATRIX2_SFR3 0x011c -#define HMATRIX2_SFR4 0x0120 -#define HMATRIX2_SFR5 0x0124 -#define HMATRIX2_SFR6 0x0128 -#define HMATRIX2_SFR7 0x012c -#define HMATRIX2_SFR8 0x0130 -#define HMATRIX2_SFR9 0x0134 -#define HMATRIX2_SFR10 0x0138 -#define HMATRIX2_SFR11 0x013c -#define HMATRIX2_SFR12 0x0140 -#define HMATRIX2_SFR13 0x0144 -#define HMATRIX2_SFR14 0x0148 -#define HMATRIX2_SFR15 0x014c -#define HMATRIX2_VERSION 0x01fc - -/* Bitfields in MCFG0 */ -#define HMATRIX2_ULBT_OFFSET 0 -#define HMATRIX2_ULBT_SIZE 3 - -/* Bitfields in SCFG0 */ -#define HMATRIX2_SLOT_CYCLE_OFFSET 0 -#define HMATRIX2_SLOT_CYCLE_SIZE 8 -#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16 -#define HMATRIX2_DEFMSTR_TYPE_SIZE 2 -#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18 -#define HMATRIX2_FIXED_DEFMSTR_SIZE 4 -#define HMATRIX2_ARBT_OFFSET 24 -#define HMATRIX2_ARBT_SIZE 2 - -/* Bitfields in PRAS0 */ -#define HMATRIX2_M0PR_OFFSET 0 -#define HMATRIX2_M0PR_SIZE 4 -#define HMATRIX2_M1PR_OFFSET 4 -#define HMATRIX2_M1PR_SIZE 4 -#define HMATRIX2_M2PR_OFFSET 8 -#define HMATRIX2_M2PR_SIZE 4 -#define HMATRIX2_M3PR_OFFSET 12 -#define HMATRIX2_M3PR_SIZE 4 -#define HMATRIX2_M4PR_OFFSET 16 -#define HMATRIX2_M4PR_SIZE 4 -#define HMATRIX2_M5PR_OFFSET 20 -#define HMATRIX2_M5PR_SIZE 4 -#define HMATRIX2_M6PR_OFFSET 24 -#define HMATRIX2_M6PR_SIZE 4 -#define HMATRIX2_M7PR_OFFSET 28 -#define HMATRIX2_M7PR_SIZE 4 - -/* Bitfields in PRBS0 */ -#define HMATRIX2_M8PR_OFFSET 0 -#define HMATRIX2_M8PR_SIZE 4 -#define HMATRIX2_M9PR_OFFSET 4 -#define HMATRIX2_M9PR_SIZE 4 -#define HMATRIX2_M10PR_OFFSET 8 -#define HMATRIX2_M10PR_SIZE 4 -#define HMATRIX2_M11PR_OFFSET 12 -#define HMATRIX2_M11PR_SIZE 4 -#define HMATRIX2_M12PR_OFFSET 16 -#define HMATRIX2_M12PR_SIZE 4 -#define HMATRIX2_M13PR_OFFSET 20 -#define HMATRIX2_M13PR_SIZE 4 -#define HMATRIX2_M14PR_OFFSET 24 -#define HMATRIX2_M14PR_SIZE 4 -#define HMATRIX2_M15PR_OFFSET 28 -#define HMATRIX2_M15PR_SIZE 4 - -/* Bitfields in MRCR */ -#define HMATRIX2_RBC0_OFFSET 0 -#define HMATRIX2_RBC0_SIZE 1 -#define HMATRIX2_RBC1_OFFSET 1 -#define HMATRIX2_RBC1_SIZE 1 -#define HMATRIX2_RBC2_OFFSET 2 -#define HMATRIX2_RBC2_SIZE 1 -#define HMATRIX2_RBC3_OFFSET 3 -#define HMATRIX2_RBC3_SIZE 1 -#define HMATRIX2_RBC4_OFFSET 4 -#define HMATRIX2_RBC4_SIZE 1 -#define HMATRIX2_RBC5_OFFSET 5 -#define HMATRIX2_RBC5_SIZE 1 -#define HMATRIX2_RBC6_OFFSET 6 -#define HMATRIX2_RBC6_SIZE 1 -#define HMATRIX2_RBC7_OFFSET 7 -#define HMATRIX2_RBC7_SIZE 1 -#define HMATRIX2_RBC8_OFFSET 8 -#define HMATRIX2_RBC8_SIZE 1 -#define HMATRIX2_RBC9_OFFSET 9 -#define HMATRIX2_RBC9_SIZE 1 -#define HMATRIX2_RBC10_OFFSET 10 -#define HMATRIX2_RBC10_SIZE 1 -#define HMATRIX2_RBC11_OFFSET 11 -#define HMATRIX2_RBC11_SIZE 1 -#define HMATRIX2_RBC12_OFFSET 12 -#define HMATRIX2_RBC12_SIZE 1 -#define HMATRIX2_RBC13_OFFSET 13 -#define HMATRIX2_RBC13_SIZE 1 -#define HMATRIX2_RBC14_OFFSET 14 -#define HMATRIX2_RBC14_SIZE 1 -#define HMATRIX2_RBC15_OFFSET 15 -#define HMATRIX2_RBC15_SIZE 1 - -/* Bitfields in SFR0 */ -#define HMATRIX2_SFR_OFFSET 0 -#define HMATRIX2_SFR_SIZE 32 - -/* Bitfields in SFR4 */ -#define HMATRIX2_CS1A_OFFSET 1 -#define HMATRIX2_CS1A_SIZE 1 -#define HMATRIX2_CS3A_OFFSET 3 -#define HMATRIX2_CS3A_SIZE 1 -#define HMATRIX2_CS4A_OFFSET 4 -#define HMATRIX2_CS4A_SIZE 1 -#define HMATRIX2_CS5A_OFFSET 5 -#define HMATRIX2_CS5A_SIZE 1 -#define HMATRIX2_DBPUC_OFFSET 8 -#define HMATRIX2_DBPUC_SIZE 1 - -/* Bitfields in VERSION */ -#define HMATRIX2_VERSION_OFFSET 0 -#define HMATRIX2_VERSION_SIZE 12 -#define HMATRIX2_MFN_OFFSET 16 -#define HMATRIX2_MFN_SIZE 3 - -/* Constants for ULBT */ -#define HMATRIX2_ULBT_INFINITE 0 -#define HMATRIX2_ULBT_SINGLE 1 -#define HMATRIX2_ULBT_FOUR_BEAT 2 -#define HMATRIX2_ULBT_SIXTEEN_BEAT 4 - -/* Constants for DEFMSTR_TYPE */ -#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0 -#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1 -#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2 - -/* Constants for ARBT */ -#define HMATRIX2_ARBT_ROUND_ROBIN 0 -#define HMATRIX2_ARBT_FIXED_PRIORITY 1 - -/* Bit manipulation macros */ -#define HMATRIX2_BIT(name) \ - (1 << HMATRIX2_##name##_OFFSET) -#define HMATRIX2_BF(name,value) \ - (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \ - << HMATRIX2_##name##_OFFSET) -#define HMATRIX2_BFEXT(name,value) \ - (((value) >> HMATRIX2_##name##_OFFSET) \ - & ((1 << HMATRIX2_##name##_SIZE) - 1)) -#define HMATRIX2_BFINS(name,value,old) \ - (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \ - << HMATRIX2_##name##_OFFSET)) \ - | HMATRIX2_BF(name,value)) - -/* Register access macros */ -#define hmatrix2_readl(reg) \ - readl((void *)HMATRIX_BASE + HMATRIX2_##reg) -#define hmatrix2_writel(reg,value) \ - writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg) - -#endif /* __ASM_AVR32_HMATRIX2_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h deleted file mode 100644 index 5513e88..0000000 --- a/include/asm-avr32/arch-at32ap7000/memory-map.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __AT32AP7000_MEMORY_MAP_H__ -#define __AT32AP7000_MEMORY_MAP_H__ - -/* Devices on the High Speed Bus (HSB) */ -#define LCDC_BASE 0xFF000000 -#define DMAC_BASE 0xFF200000 -#define USB_FIFO 0xFF300000 - -/* Devices on Peripheral Bus A (PBA) */ -#define SPI0_BASE 0xFFE00000 -#define SPI1_BASE 0xFFE00400 -#define TWI_BASE 0xFFE00800 -#define USART0_BASE 0xFFE00C00 -#define USART1_BASE 0xFFE01000 -#define USART2_BASE 0xFFE01400 -#define USART3_BASE 0xFFE01800 -#define SSC0_BASE 0xFFE01C00 -#define SSC1_BASE 0xFFE02000 -#define SSC2_BASE 0xFFE02400 -#define PIOA_BASE 0xFFE02800 -#define PIOB_BASE 0xFFE02C00 -#define PIOC_BASE 0xFFE03000 -#define PIOD_BASE 0xFFE03400 -#define PIOE_BASE 0xFFE03800 -#define PSIF_BASE 0xFFE03C00 - -/* Devices on Peripheral Bus B (PBB) */ -#define SM_BASE 0xFFF00000 -#define INTC_BASE 0xFFF00400 -#define HMATRIX_BASE 0xFFF00800 -#define TIMER0_BASE 0xFFF00C00 -#define TIMER1_BASE 0xFFF01000 -#define PWM_BASE 0xFFF01400 -#define MACB0_BASE 0xFFF01800 -#define MACB1_BASE 0xFFF01C00 -#define DAC_BASE 0xFFF02000 -#define MMCI_BASE 0xFFF02400 -#define AUDIOC_BASE 0xFFF02800 -#define HISI_BASE 0xFFF02C00 -#define USB_BASE 0xFFF03000 -#define HSMC_BASE 0xFFF03400 -#define HSDRAMC_BASE 0xFFF03800 -#define ECC_BASE 0xFFF03C00 - -#endif /* __AT32AP7000_MEMORY_MAP_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/mmc.h b/include/asm-avr32/arch-at32ap7000/mmc.h deleted file mode 100644 index fcfbbb3..0000000 --- a/include/asm-avr32/arch-at32ap7000/mmc.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_MMC_H -#define __ASM_AVR32_MMC_H - -struct mmc_cid { - unsigned long psn; - unsigned short oid; - unsigned char mid; - unsigned char prv; - unsigned char mdt; - char pnm[7]; -}; - -struct mmc_csd -{ - u8 csd_structure:2, - spec_vers:4, - rsvd1:2; - u8 taac; - u8 nsac; - u8 tran_speed; - u16 ccc:12, - read_bl_len:4; - u64 read_bl_partial:1, - write_blk_misalign:1, - read_blk_misalign:1, - dsr_imp:1, - rsvd2:2, - c_size:12, - vdd_r_curr_min:3, - vdd_r_curr_max:3, - vdd_w_curr_min:3, - vdd_w_curr_max:3, - c_size_mult:3, - sector_size:5, - erase_grp_size:5, - wp_grp_size:5, - wp_grp_enable:1, - default_ecc:2, - r2w_factor:3, - write_bl_len:4, - write_bl_partial:1, - rsvd3:5; - u8 file_format_grp:1, - copy:1, - perm_write_protect:1, - tmp_write_protect:1, - file_format:2, - ecc:2; - u8 crc:7; - u8 one:1; -}; - -/* MMC Command numbers */ -#define MMC_CMD_GO_IDLE_STATE 0 -#define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 -#define MMC_CMD_SET_RELATIVE_ADDR 3 -#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 -#define MMC_CMD_SET_DSR 4 -#define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 -#define MMC_CMD_SEND_STATUS 13 -#define MMC_CMD_SET_BLOCKLEN 16 -#define MMC_CMD_READ_SINGLE_BLOCK 17 -#define MMC_CMD_READ_MULTIPLE_BLOCK 18 -#define MMC_CMD_WRITE_BLOCK 24 -#define MMC_CMD_APP_CMD 55 - -#define MMC_ACMD_SD_SEND_OP_COND 41 - -#define R1_ILLEGAL_COMMAND (1 << 22) -#define R1_APP_CMD (1 << 5) - -#endif /* __ASM_AVR32_MMC_H */ diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h new file mode 100644 index 0000000..7e20d97 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_CLK_H__ +#define __ASM_AVR32_ARCH_CLK_H__ + +#ifdef CONFIG_PLL +#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#else +#define MAIN_CLK_RATE (CFG_OSC0_HZ) +#endif + +static inline unsigned long get_cpu_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_CPU; +} +static inline unsigned long get_hsb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_HSB; +} +static inline unsigned long get_pba_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_PBA; +} +static inline unsigned long get_pbb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_PBB; +} + +/* Accessors for specific devices. More will be added as needed. */ +static inline unsigned long get_sdram_clk_rate(void) +{ + return get_hsb_clk_rate(); +} +static inline unsigned long get_usart_clk_rate(unsigned int dev_id) +{ + return get_pba_clk_rate(); +} +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return get_pbb_clk_rate(); +} +static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) +{ + return get_hsb_clk_rate(); +} +static inline unsigned long get_mci_clk_rate(void) +{ + return get_pbb_clk_rate(); +} + +#endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h new file mode 100644 index 0000000..e4812d4 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/gpio.h @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_GPIO_H__ +#define __ASM_AVR32_ARCH_GPIO_H__ + +#include + +#define NR_GPIO_CONTROLLERS 5 + +/* + * Pin numbers identifying specific GPIO pins on the chip. + */ +#define GPIO_PIOA_BASE (0) +#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0) +#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1) +#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2) +#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3) +#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4) +#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5) +#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6) +#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7) +#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8) +#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9) +#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10) +#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11) +#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12) +#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13) +#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14) +#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15) +#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16) +#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17) +#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18) +#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19) +#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20) +#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21) +#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22) +#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23) +#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24) +#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25) +#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26) +#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27) +#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28) +#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29) +#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30) +#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31) + +#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) +#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0) +#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1) +#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2) +#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3) +#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4) +#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5) +#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6) +#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7) +#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8) +#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9) +#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10) +#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11) +#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12) +#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13) +#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14) +#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15) +#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16) +#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17) +#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18) +#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19) +#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20) +#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21) +#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22) +#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23) +#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24) +#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25) +#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26) +#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27) +#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28) +#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29) +#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30) + +#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) +#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0) +#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1) +#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2) +#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3) +#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4) +#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5) +#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6) +#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7) +#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8) +#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9) +#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10) +#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11) +#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12) +#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13) +#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14) +#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15) +#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16) +#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17) +#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18) +#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19) +#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20) +#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21) +#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22) +#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23) +#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24) +#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25) +#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26) +#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27) +#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28) +#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29) +#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30) +#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31) + +#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) +#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0) +#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1) +#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2) +#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3) +#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4) +#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5) +#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6) +#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7) +#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8) +#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9) +#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10) +#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11) +#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12) +#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13) +#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14) +#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15) +#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16) +#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17) + +#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) +#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0) +#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1) +#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2) +#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3) +#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4) +#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5) +#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6) +#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7) +#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8) +#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9) +#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10) +#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11) +#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12) +#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13) +#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14) +#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15) +#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16) +#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17) +#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18) +#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19) +#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20) +#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21) +#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22) +#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23) +#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24) +#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25) +#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26) + +static inline void *gpio_pin_to_addr(unsigned int pin) +{ + switch (pin >> 5) { + case 0: + return (void *)PIOA_BASE; + case 1: + return (void *)PIOB_BASE; + case 2: + return (void *)PIOC_BASE; + case 3: + return (void *)PIOD_BASE; + case 4: + return (void *)PIOE_BASE; + default: + return NULL; + } +} + +void gpio_select_periph_A(unsigned int pin, int use_pullup); +void gpio_select_periph_B(unsigned int pin, int use_pullup); + +void gpio_enable_ebi(void); +void gpio_enable_usart0(void); +void gpio_enable_usart1(void); +void gpio_enable_usart2(void); +void gpio_enable_usart3(void); +void gpio_enable_macb0(void); +void gpio_enable_macb1(void); +void gpio_enable_mmci(void); + +#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix2.h b/include/asm-avr32/arch-at32ap700x/hmatrix2.h new file mode 100644 index 0000000..b0e787a --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/hmatrix2.h @@ -0,0 +1,232 @@ +/* + * Register definition for the High-speed Bus Matrix + */ +#ifndef __ASM_AVR32_HMATRIX2_H__ +#define __ASM_AVR32_HMATRIX2_H__ + +/* HMATRIX2 register offsets */ +#define HMATRIX2_MCFG0 0x0000 +#define HMATRIX2_MCFG1 0x0004 +#define HMATRIX2_MCFG2 0x0008 +#define HMATRIX2_MCFG3 0x000c +#define HMATRIX2_MCFG4 0x0010 +#define HMATRIX2_MCFG5 0x0014 +#define HMATRIX2_MCFG6 0x0018 +#define HMATRIX2_MCFG7 0x001c +#define HMATRIX2_MCFG8 0x0020 +#define HMATRIX2_MCFG9 0x0024 +#define HMATRIX2_MCFG10 0x0028 +#define HMATRIX2_MCFG11 0x002c +#define HMATRIX2_MCFG12 0x0030 +#define HMATRIX2_MCFG13 0x0034 +#define HMATRIX2_MCFG14 0x0038 +#define HMATRIX2_MCFG15 0x003c +#define HMATRIX2_SCFG0 0x0040 +#define HMATRIX2_SCFG1 0x0044 +#define HMATRIX2_SCFG2 0x0048 +#define HMATRIX2_SCFG3 0x004c +#define HMATRIX2_SCFG4 0x0050 +#define HMATRIX2_SCFG5 0x0054 +#define HMATRIX2_SCFG6 0x0058 +#define HMATRIX2_SCFG7 0x005c +#define HMATRIX2_SCFG8 0x0060 +#define HMATRIX2_SCFG9 0x0064 +#define HMATRIX2_SCFG10 0x0068 +#define HMATRIX2_SCFG11 0x006c +#define HMATRIX2_SCFG12 0x0070 +#define HMATRIX2_SCFG13 0x0074 +#define HMATRIX2_SCFG14 0x0078 +#define HMATRIX2_SCFG15 0x007c +#define HMATRIX2_PRAS0 0x0080 +#define HMATRIX2_PRBS0 0x0084 +#define HMATRIX2_PRAS1 0x0088 +#define HMATRIX2_PRBS1 0x008c +#define HMATRIX2_PRAS2 0x0090 +#define HMATRIX2_PRBS2 0x0094 +#define HMATRIX2_PRAS3 0x0098 +#define HMATRIX2_PRBS3 0x009c +#define HMATRIX2_PRAS4 0x00a0 +#define HMATRIX2_PRBS4 0x00a4 +#define HMATRIX2_PRAS5 0x00a8 +#define HMATRIX2_PRBS5 0x00ac +#define HMATRIX2_PRAS6 0x00b0 +#define HMATRIX2_PRBS6 0x00b4 +#define HMATRIX2_PRAS7 0x00b8 +#define HMATRIX2_PRBS7 0x00bc +#define HMATRIX2_PRAS8 0x00c0 +#define HMATRIX2_PRBS8 0x00c4 +#define HMATRIX2_PRAS9 0x00c8 +#define HMATRIX2_PRBS9 0x00cc +#define HMATRIX2_PRAS10 0x00d0 +#define HMATRIX2_PRBS10 0x00d4 +#define HMATRIX2_PRAS11 0x00d8 +#define HMATRIX2_PRBS11 0x00dc +#define HMATRIX2_PRAS12 0x00e0 +#define HMATRIX2_PRBS12 0x00e4 +#define HMATRIX2_PRAS13 0x00e8 +#define HMATRIX2_PRBS13 0x00ec +#define HMATRIX2_PRAS14 0x00f0 +#define HMATRIX2_PRBS14 0x00f4 +#define HMATRIX2_PRAS15 0x00f8 +#define HMATRIX2_PRBS15 0x00fc +#define HMATRIX2_MRCR 0x0100 +#define HMATRIX2_SFR0 0x0110 +#define HMATRIX2_SFR1 0x0114 +#define HMATRIX2_SFR2 0x0118 +#define HMATRIX2_SFR3 0x011c +#define HMATRIX2_SFR4 0x0120 +#define HMATRIX2_SFR5 0x0124 +#define HMATRIX2_SFR6 0x0128 +#define HMATRIX2_SFR7 0x012c +#define HMATRIX2_SFR8 0x0130 +#define HMATRIX2_SFR9 0x0134 +#define HMATRIX2_SFR10 0x0138 +#define HMATRIX2_SFR11 0x013c +#define HMATRIX2_SFR12 0x0140 +#define HMATRIX2_SFR13 0x0144 +#define HMATRIX2_SFR14 0x0148 +#define HMATRIX2_SFR15 0x014c +#define HMATRIX2_VERSION 0x01fc + +/* Bitfields in MCFG0 */ +#define HMATRIX2_ULBT_OFFSET 0 +#define HMATRIX2_ULBT_SIZE 3 + +/* Bitfields in SCFG0 */ +#define HMATRIX2_SLOT_CYCLE_OFFSET 0 +#define HMATRIX2_SLOT_CYCLE_SIZE 8 +#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16 +#define HMATRIX2_DEFMSTR_TYPE_SIZE 2 +#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18 +#define HMATRIX2_FIXED_DEFMSTR_SIZE 4 +#define HMATRIX2_ARBT_OFFSET 24 +#define HMATRIX2_ARBT_SIZE 2 + +/* Bitfields in PRAS0 */ +#define HMATRIX2_M0PR_OFFSET 0 +#define HMATRIX2_M0PR_SIZE 4 +#define HMATRIX2_M1PR_OFFSET 4 +#define HMATRIX2_M1PR_SIZE 4 +#define HMATRIX2_M2PR_OFFSET 8 +#define HMATRIX2_M2PR_SIZE 4 +#define HMATRIX2_M3PR_OFFSET 12 +#define HMATRIX2_M3PR_SIZE 4 +#define HMATRIX2_M4PR_OFFSET 16 +#define HMATRIX2_M4PR_SIZE 4 +#define HMATRIX2_M5PR_OFFSET 20 +#define HMATRIX2_M5PR_SIZE 4 +#define HMATRIX2_M6PR_OFFSET 24 +#define HMATRIX2_M6PR_SIZE 4 +#define HMATRIX2_M7PR_OFFSET 28 +#define HMATRIX2_M7PR_SIZE 4 + +/* Bitfields in PRBS0 */ +#define HMATRIX2_M8PR_OFFSET 0 +#define HMATRIX2_M8PR_SIZE 4 +#define HMATRIX2_M9PR_OFFSET 4 +#define HMATRIX2_M9PR_SIZE 4 +#define HMATRIX2_M10PR_OFFSET 8 +#define HMATRIX2_M10PR_SIZE 4 +#define HMATRIX2_M11PR_OFFSET 12 +#define HMATRIX2_M11PR_SIZE 4 +#define HMATRIX2_M12PR_OFFSET 16 +#define HMATRIX2_M12PR_SIZE 4 +#define HMATRIX2_M13PR_OFFSET 20 +#define HMATRIX2_M13PR_SIZE 4 +#define HMATRIX2_M14PR_OFFSET 24 +#define HMATRIX2_M14PR_SIZE 4 +#define HMATRIX2_M15PR_OFFSET 28 +#define HMATRIX2_M15PR_SIZE 4 + +/* Bitfields in MRCR */ +#define HMATRIX2_RBC0_OFFSET 0 +#define HMATRIX2_RBC0_SIZE 1 +#define HMATRIX2_RBC1_OFFSET 1 +#define HMATRIX2_RBC1_SIZE 1 +#define HMATRIX2_RBC2_OFFSET 2 +#define HMATRIX2_RBC2_SIZE 1 +#define HMATRIX2_RBC3_OFFSET 3 +#define HMATRIX2_RBC3_SIZE 1 +#define HMATRIX2_RBC4_OFFSET 4 +#define HMATRIX2_RBC4_SIZE 1 +#define HMATRIX2_RBC5_OFFSET 5 +#define HMATRIX2_RBC5_SIZE 1 +#define HMATRIX2_RBC6_OFFSET 6 +#define HMATRIX2_RBC6_SIZE 1 +#define HMATRIX2_RBC7_OFFSET 7 +#define HMATRIX2_RBC7_SIZE 1 +#define HMATRIX2_RBC8_OFFSET 8 +#define HMATRIX2_RBC8_SIZE 1 +#define HMATRIX2_RBC9_OFFSET 9 +#define HMATRIX2_RBC9_SIZE 1 +#define HMATRIX2_RBC10_OFFSET 10 +#define HMATRIX2_RBC10_SIZE 1 +#define HMATRIX2_RBC11_OFFSET 11 +#define HMATRIX2_RBC11_SIZE 1 +#define HMATRIX2_RBC12_OFFSET 12 +#define HMATRIX2_RBC12_SIZE 1 +#define HMATRIX2_RBC13_OFFSET 13 +#define HMATRIX2_RBC13_SIZE 1 +#define HMATRIX2_RBC14_OFFSET 14 +#define HMATRIX2_RBC14_SIZE 1 +#define HMATRIX2_RBC15_OFFSET 15 +#define HMATRIX2_RBC15_SIZE 1 + +/* Bitfields in SFR0 */ +#define HMATRIX2_SFR_OFFSET 0 +#define HMATRIX2_SFR_SIZE 32 + +/* Bitfields in SFR4 */ +#define HMATRIX2_CS1A_OFFSET 1 +#define HMATRIX2_CS1A_SIZE 1 +#define HMATRIX2_CS3A_OFFSET 3 +#define HMATRIX2_CS3A_SIZE 1 +#define HMATRIX2_CS4A_OFFSET 4 +#define HMATRIX2_CS4A_SIZE 1 +#define HMATRIX2_CS5A_OFFSET 5 +#define HMATRIX2_CS5A_SIZE 1 +#define HMATRIX2_DBPUC_OFFSET 8 +#define HMATRIX2_DBPUC_SIZE 1 + +/* Bitfields in VERSION */ +#define HMATRIX2_VERSION_OFFSET 0 +#define HMATRIX2_VERSION_SIZE 12 +#define HMATRIX2_MFN_OFFSET 16 +#define HMATRIX2_MFN_SIZE 3 + +/* Constants for ULBT */ +#define HMATRIX2_ULBT_INFINITE 0 +#define HMATRIX2_ULBT_SINGLE 1 +#define HMATRIX2_ULBT_FOUR_BEAT 2 +#define HMATRIX2_ULBT_SIXTEEN_BEAT 4 + +/* Constants for DEFMSTR_TYPE */ +#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0 +#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1 +#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2 + +/* Constants for ARBT */ +#define HMATRIX2_ARBT_ROUND_ROBIN 0 +#define HMATRIX2_ARBT_FIXED_PRIORITY 1 + +/* Bit manipulation macros */ +#define HMATRIX2_BIT(name) \ + (1 << HMATRIX2_##name##_OFFSET) +#define HMATRIX2_BF(name,value) \ + (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \ + << HMATRIX2_##name##_OFFSET) +#define HMATRIX2_BFEXT(name,value) \ + (((value) >> HMATRIX2_##name##_OFFSET) \ + & ((1 << HMATRIX2_##name##_SIZE) - 1)) +#define HMATRIX2_BFINS(name,value,old) \ + (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \ + << HMATRIX2_##name##_OFFSET)) \ + | HMATRIX2_BF(name,value)) + +/* Register access macros */ +#define hmatrix2_readl(reg) \ + readl((void *)HMATRIX_BASE + HMATRIX2_##reg) +#define hmatrix2_writel(reg,value) \ + writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg) + +#endif /* __ASM_AVR32_HMATRIX2_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h new file mode 100644 index 0000000..5513e88 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/memory-map.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __AT32AP7000_MEMORY_MAP_H__ +#define __AT32AP7000_MEMORY_MAP_H__ + +/* Devices on the High Speed Bus (HSB) */ +#define LCDC_BASE 0xFF000000 +#define DMAC_BASE 0xFF200000 +#define USB_FIFO 0xFF300000 + +/* Devices on Peripheral Bus A (PBA) */ +#define SPI0_BASE 0xFFE00000 +#define SPI1_BASE 0xFFE00400 +#define TWI_BASE 0xFFE00800 +#define USART0_BASE 0xFFE00C00 +#define USART1_BASE 0xFFE01000 +#define USART2_BASE 0xFFE01400 +#define USART3_BASE 0xFFE01800 +#define SSC0_BASE 0xFFE01C00 +#define SSC1_BASE 0xFFE02000 +#define SSC2_BASE 0xFFE02400 +#define PIOA_BASE 0xFFE02800 +#define PIOB_BASE 0xFFE02C00 +#define PIOC_BASE 0xFFE03000 +#define PIOD_BASE 0xFFE03400 +#define PIOE_BASE 0xFFE03800 +#define PSIF_BASE 0xFFE03C00 + +/* Devices on Peripheral Bus B (PBB) */ +#define SM_BASE 0xFFF00000 +#define INTC_BASE 0xFFF00400 +#define HMATRIX_BASE 0xFFF00800 +#define TIMER0_BASE 0xFFF00C00 +#define TIMER1_BASE 0xFFF01000 +#define PWM_BASE 0xFFF01400 +#define MACB0_BASE 0xFFF01800 +#define MACB1_BASE 0xFFF01C00 +#define DAC_BASE 0xFFF02000 +#define MMCI_BASE 0xFFF02400 +#define AUDIOC_BASE 0xFFF02800 +#define HISI_BASE 0xFFF02C00 +#define USB_BASE 0xFFF03000 +#define HSMC_BASE 0xFFF03400 +#define HSDRAMC_BASE 0xFFF03800 +#define ECC_BASE 0xFFF03C00 + +#endif /* __AT32AP7000_MEMORY_MAP_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h new file mode 100644 index 0000000..fcfbbb3 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/mmc.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_MMC_H +#define __ASM_AVR32_MMC_H + +struct mmc_cid { + unsigned long psn; + unsigned short oid; + unsigned char mid; + unsigned char prv; + unsigned char mdt; + char pnm[7]; +}; + +struct mmc_csd +{ + u8 csd_structure:2, + spec_vers:4, + rsvd1:2; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc:12, + read_bl_len:4; + u64 read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + sector_size:5, + erase_grp_size:5, + wp_grp_size:5, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:5; + u8 file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; + u8 crc:7; + u8 one:1; +}; + +/* MMC Command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_APP_CMD 55 + +#define MMC_ACMD_SD_SEND_OP_COND 41 + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#endif /* __ASM_AVR32_MMC_H */ -- cgit v1.1 From 5fee84a794a51ec830548cda485a770efb018b92 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 29 Oct 2007 13:23:33 +0100 Subject: AVR32: Make some AT32AP700x peripherals optional Add a chip-features file providing definitions of the form AT32AP700x_CHIP_HAS_ to indicate the availability of the given peripheral on the currently selected chip. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap700x/chip-features.h | 34 +++++++++++++++++++++++ include/asm-avr32/arch-at32ap700x/clk.h | 8 ++++++ include/asm-avr32/arch-at32ap700x/gpio.h | 8 ++++++ 3 files changed, 50 insertions(+) create mode 100644 include/asm-avr32/arch-at32ap700x/chip-features.h (limited to 'include') diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h new file mode 100644 index 0000000..29b1fd6 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/chip-features.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__ +#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__ + +/* Currently, all the AP700x chips have these */ +#define AT32AP700x_CHIP_HAS_USART +#define AT32AP700x_CHIP_HAS_MMCI + +/* Only AP7000 has ethernet interface */ +#ifdef CONFIG_AT32AP7000 +#define AT32AP700x_CHIP_HAS_MACB +#endif + +#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index 7e20d97..ea84c08 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -22,6 +22,8 @@ #ifndef __ASM_AVR32_ARCH_CLK_H__ #define __ASM_AVR32_ARCH_CLK_H__ +#include + #ifdef CONFIG_PLL #define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) #else @@ -50,10 +52,13 @@ static inline unsigned long get_sdram_clk_rate(void) { return get_hsb_clk_rate(); } +#ifdef AT32AP700x_CHIP_HAS_USART static inline unsigned long get_usart_clk_rate(unsigned int dev_id) { return get_pba_clk_rate(); } +#endif +#ifdef AT32AP700x_CHIP_HAS_USART static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) { return get_pbb_clk_rate(); @@ -62,9 +67,12 @@ static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) { return get_hsb_clk_rate(); } +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI static inline unsigned long get_mci_clk_rate(void) { return get_pbb_clk_rate(); } +#endif #endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h index e4812d4..b10a3e4 100644 --- a/include/asm-avr32/arch-at32ap700x/gpio.h +++ b/include/asm-avr32/arch-at32ap700x/gpio.h @@ -22,6 +22,7 @@ #ifndef __ASM_AVR32_ARCH_GPIO_H__ #define __ASM_AVR32_ARCH_GPIO_H__ +#include #include #define NR_GPIO_CONTROLLERS 5 @@ -201,12 +202,19 @@ void gpio_select_periph_A(unsigned int pin, int use_pullup); void gpio_select_periph_B(unsigned int pin, int use_pullup); void gpio_enable_ebi(void); + +#ifdef AT32AP700x_CHIP_HAS_USART void gpio_enable_usart0(void); void gpio_enable_usart1(void); void gpio_enable_usart2(void); void gpio_enable_usart3(void); +#endif +#ifdef AT32AP700x_CHIP_HAS_MACB void gpio_enable_macb0(void); void gpio_enable_macb1(void); +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI void gpio_enable_mmci(void); +#endif #endif /* __ASM_AVR32_ARCH_GPIO_H__ */ -- cgit v1.1 From 667568db157f374b85abd7e03596ddd1f0b25681 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 29 Oct 2007 13:02:54 +0100 Subject: AVR32: Add support for the ATSTK1003 board ATSTK1003 is a daughterboard for ATSTK1000 with the AT32AP7001 CPU, which is a derivative of AT32AP7000. Signed-off-by: Haavard Skinnemoen --- include/configs/atstk1003.h | 184 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 184 insertions(+) create mode 100644 include/configs/atstk1003.h (limited to 'include') diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h new file mode 100644 index 0000000..194788b --- /dev/null +++ b/include/configs/atstk1003.h @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * Configuration settings for the ATSTK1003 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7001 1 +#define CONFIG_ATSTK1003 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz + */ +#define CFG_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz + */ +#define CFG_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz + */ +#define CFG_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz + */ +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#undef CONFIG_USART0 +#define CONFIG_USART1 1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mmcblk0p1 rootwait" + +#define CONFIG_BOOTCOMMAND \ + "mmcinit; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm" + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_PIO2 1 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Uboot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit v1.1 From 64ff2357b1727213803591813dbc779c924bf772 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 29 Oct 2007 13:02:54 +0100 Subject: AVR32: Add support for the ATSTK1004 board ATSTK1004 is a daughterboard for ATSTK1000 with the AT32AP7002 CPU, which is a derivative of AT32AP7000. Signed-off-by: Haavard Skinnemoen --- include/configs/atstk1004.h | 185 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 include/configs/atstk1004.h (limited to 'include') diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h new file mode 100644 index 0000000..1bad171 --- /dev/null +++ b/include/configs/atstk1004.h @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2007 Atmel Corporation + * + * Configuration settings for the ATSTK1003 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7002 1 +#define CONFIG_ATSTK1004 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz + */ +#define CFG_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz + */ +#define CFG_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz + */ +#define CFG_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz + */ +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#undef CONFIG_USART0 +#define CONFIG_USART1 1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mmcblk0p1 rootwait" + +#define CONFIG_BOOTCOMMAND \ + "mmcinit; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm" + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_PIO2 1 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 +#define CFG_SDRAM_16BIT 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Uboot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit v1.1 From 61fb15c516fef5631e305f1976d7b3a679725856 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 27 Dec 2007 01:52:50 +0100 Subject: Fix coding style issues; update CHANGELOG. Signed-off-by: Wolfgang Denk --- include/asm-sh/bitops.h | 67 +++++++++++++++++--------------------------- include/asm-sh/byteorder.h | 1 - include/asm-sh/cpu_sh7722.h | 18 ++++++------ include/asm-sh/cpu_sh7750.h | 2 +- include/asm-sh/posix_types.h | 2 +- include/asm-sh/u-boot.h | 2 -- include/configs/ms7722se.h | 11 ++++---- include/configs/ms7750se.h | 6 ++-- 8 files changed, 45 insertions(+), 64 deletions(-) (limited to 'include') diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h index 529d0f2..410fba4 100644 --- a/include/asm-sh/bitops.h +++ b/include/asm-sh/bitops.h @@ -2,7 +2,6 @@ #define __ASM_SH_BITOPS_H #ifdef __KERNEL__ -//#include #include /* For __swab32 */ #include @@ -99,8 +98,6 @@ static inline int test_and_change_bit(int nr, volatile void * addr) return retval; } -//#include - static inline unsigned long ffz(unsigned long word) { unsigned long result; @@ -121,46 +118,34 @@ static inline unsigned long ffz(unsigned long word) * * Undefined if no bit exists, so code should check against 0 first. */ -static inline int ffs(int x) +static inline int ffs (int x) { - int r = 1; - - if (!x) - return 0; - if (!(x & 0xffff)) { - x >>= 16; - r += 16; - } - if (!(x & 0xff)) { - x >>= 8; - r += 8; - } - if (!(x & 0xf)) { - x >>= 4; - r += 4; - } - if (!(x & 3)) { - x >>= 2; - r += 2; - } - if (!(x & 1)) { - x >>= 1; - r += 1; - } - return r; + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; } - -#if 0 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#endif #endif /* __KERNEL__ */ #endif /* __ASM_SH_BITOPS_H */ diff --git a/include/asm-sh/byteorder.h b/include/asm-sh/byteorder.h index 8836e65..25626a0 100644 --- a/include/asm-sh/byteorder.h +++ b/include/asm-sh/byteorder.h @@ -28,4 +28,3 @@ #endif #endif - diff --git a/include/asm-sh/cpu_sh7722.h b/include/asm-sh/cpu_sh7722.h index fb63c6e..13d4a77 100644 --- a/include/asm-sh/cpu_sh7722.h +++ b/include/asm-sh/cpu_sh7722.h @@ -31,13 +31,13 @@ #define INTEVT 0xFF000028 /* MMU */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define PASCR 0xFF000070 -#define IRMCR 0xFF000078 +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define PASCR 0xFF000070 +#define IRMCR 0xFF000078 /* CACHE */ #define CCR 0xFF00001C @@ -325,7 +325,7 @@ #define SPICR1 0xA4420030 /* SCIF */ -/* +/* #define SCSMR 0xFFE00000 #define SCBRR 0xFFE00004 #define SCSCR 0xFFE00008 @@ -1334,4 +1334,4 @@ #define SDDRL 0xFC11000A #define SDINT 0xFC110018 -#endif /* _ASM_CPU_SH7722_H_ */ +#endif /* _ASM_CPU_SH7722_H_ */ diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h index 9993e63..bb6461a 100644 --- a/include/asm-sh/cpu_sh7750.h +++ b/include/asm-sh/cpu_sh7750.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2007 Nobuhiro Iwamatsu * - * SH7750/SH7750S/SH7750R/SH7751/SH7751R + * SH7750/SH7750S/SH7750R/SH7751/SH7751R * Internal I/O register * * This program is free software; you can redistribute it and/or diff --git a/include/asm-sh/posix_types.h b/include/asm-sh/posix_types.h index 4bb9f7e..c9d9fb8 100644 --- a/include/asm-sh/posix_types.h +++ b/include/asm-sh/posix_types.h @@ -68,7 +68,7 @@ static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) #undef __FD_ISSET static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ +{ unsigned long __tmp = __fd / __NFDBITS; unsigned long __rem = __fd % __NFDBITS; return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; diff --git a/include/asm-sh/u-boot.h b/include/asm-sh/u-boot.h index c74e97c..b79644c 100644 --- a/include/asm-sh/u-boot.h +++ b/include/asm-sh/u-boot.h @@ -25,7 +25,6 @@ #ifndef __ASM_SH_U_BOOT_H_ #define __ASM_SH_U_BOOT_H_ - typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ unsigned long bi_memsize; /* size of DRAM memory in bytes */ @@ -41,4 +40,3 @@ typedef struct bd_info { } bd_t; #endif - diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 18e9851..ae0d018 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -25,7 +25,7 @@ #ifndef __MS7722SE_H #define __MS7722SE_H -#undef DEBUG +#undef DEBUG #define CONFIG_SH 1 #define CONFIG_SH4 1 #define CONFIG_CPU_SH7722 1 @@ -56,7 +56,6 @@ /* MEMORY */ #define MS7722SE_SDRAM_BASE (0x8C000000) #define MS7722SE_FLASH_BASE_1 (0xA0000000) -//#define MS7722SE_FLASH_BASE_1 (0xA1000000) #define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024) #define CFG_LONGHELP /* undef to save memory */ @@ -87,12 +86,12 @@ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */ -#define CFG_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image +#define CFG_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ #define CFG_MONITOR_LEN (128 * 1024) /* */ #define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ #define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ -#define CFG_BOOTMAPSZ (8 * 1024 * 1024) +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ #define CFG_FLASH_CFI @@ -102,7 +101,7 @@ #define CFG_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */ -#define CFG_MAX_FLASH_SECT 150 /* Max number of sectors on each +#define CFG_MAX_FLASH_SECT 150 /* Max number of sectors on each Flash chip */ /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */ @@ -131,7 +130,7 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 33333333 -#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ +#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) #endif /* __MS7722SE_H */ diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index 7925f20..3668156 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -37,7 +37,7 @@ /* * Command line configuration. */ -//#include +/*#include */ #define CONFIG_CMD_DFL #define CONFIG_CMD_FLASH @@ -56,7 +56,7 @@ #define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_SIZE (64 * 1024 * 1024) -#define CFG_LONGHELP +#define CFG_LONGHELP #define CFG_PROMPT "=> " #define CFG_CBSIZE 256 #define CFG_PBSIZE 256 @@ -71,7 +71,7 @@ /* NOR Flash */ /* #define CFG_FLASH_BASE (0xA1000000)*/ #define CFG_FLASH_BASE (0xA0000000) -#define CFG_MAX_FLASH_BANKS (1) /* Max number of +#define CFG_MAX_FLASH_BANKS (1) /* Max number of * Flash memory banks */ #define CFG_MAX_FLASH_SECT 142 -- cgit v1.1 From dabad4b9bc46908e301f73ce76b38b23626a96e9 Mon Sep 17 00:00:00 2001 From: Jens Gehrlein Date: Thu, 27 Sep 2007 14:54:46 +0200 Subject: TQM860M: Support for 10col SDRAMs, max. 128 MiB Signed-off-by: Martin Krause --- include/configs/TQM860M.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index fe3a2f0..44ad53e 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -368,7 +368,7 @@ */ #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ +#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ #define CFG_OR_TIMING_SDRAM 0x00000A00 @@ -444,7 +444,10 @@ #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - +/* 10 column SDRAM */ +#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* * Internal Definitions -- cgit v1.1 From 492c7049869348d31168de8dad89651315e468e0 Mon Sep 17 00:00:00 2001 From: Jens Gehrlein Date: Thu, 27 Sep 2007 14:54:46 +0200 Subject: TQM885D: fix SDRAM refresh At 133 MHz the current SDRAM refresh rate is too fast (measured 4 * 1.17 us). CFG_MAMR_PTA changes from 39 to 128. This result in a refresh rate of 4 * 7.8 us at the default clock 66 MHz. At 133 MHz the value will be then 4 * 3.8 us. This is a compromise until a new method is found to adjust the refresh rate. Signed-off-by: Martin Krause --- include/configs/TQM885D.h | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index f36b729..a8fbbfb 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -434,26 +434,30 @@ #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) /* - * Memory Periodic Timer Prescaler - * Periodic timer for refresh, start with refresh rate for 40 MHz clock - * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) + * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) + * + * CPUclock(MHz) * 31.2 + * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0 + * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 + * + * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us + * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us + * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us + * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us + * + * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will + * be met also in the default configuration, i.e. if environment variable + * 'cpuclk' is not set. */ -#define CFG_MAMR_PTA 39 +#define CFG_MAMR_PTA 128 /* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + * Memory Periodic Timer Prescaler Register (MPTPR) values. */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ +/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 +/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* * MAMR settings for SDRAM -- cgit v1.1 From b988b8cd443989be65161888eea0127ad03f846f Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Wed, 26 Sep 2007 17:55:56 +0200 Subject: TQM885D: use calculated cpuclk instead of measuring it On the TQM885D the measurement of cpuclk with the PIT reference timer ist not necessary. Since all module variants use the same external 10 MHz oscillator, the cpuclk only depends on the PLL configuration - which is readable by software. Signed-off-by: Martin Krause --- include/configs/TQM885D.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'include') diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index a8fbbfb..dd26d54 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -46,13 +46,6 @@ /* (it will be used if there is no */ /* 'cpuclk' variable with valid value) */ -#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */ - /* (function measure_gclk() */ - /* will be called) */ -#ifdef CFG_MEASURE_CPUCLK -#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ -#endif - #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -- cgit v1.1 From 22d1a56cbfb0bff34f477b4db6a55d076d829b83 Mon Sep 17 00:00:00 2001 From: Jens Gehrlein Date: Wed, 26 Sep 2007 17:55:54 +0200 Subject: TQM885D: Exchanged SDRAM timing by a more relaxed timing. CAS-Latency=2, Write Recovery Time tWR=2 The max. supported bus frequency is 66 MHz. Therefore, changed threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz. Signed-off-by: Martin Krause --- include/configs/TQM885D.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index dd26d54..e0c6965 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -42,7 +42,7 @@ #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ #define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ #define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */ +#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ /* (it will be used if there is no */ /* 'cpuclk' variable with valid value) */ -- cgit v1.1 From 11d9eec479b470eab9242ab937fca70a876d9376 Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Wed, 26 Sep 2007 17:55:56 +0200 Subject: TQM885D: adjust for doubled flash sector size + some minor fixes Signed-off-by: Martin Krause --- include/common.h | 9 +++++---- include/configs/TQM885D.h | 20 +++++++++++++------- 2 files changed, 18 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 63ac8b0..04195ab 100644 --- a/include/common.h +++ b/include/common.h @@ -129,20 +129,21 @@ typedef void (interrupt_handler_t)(void *); /* * enable common handling for all TQM8xxL/M boards: - * - CONFIG_TQM8xxM will be defined for all TQM8xxM and TQM885D boards + * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards + * and for the TQM885D board */ #if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) || \ - defined(CONFIG_TQM885D) + defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) # ifndef CONFIG_TQM8xxM # define CONFIG_TQM8xxM # endif #endif #if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) + defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \ + defined(CONFIG_TQM885D) # ifndef CONFIG_TQM8xxL # define CONFIG_TQM8xxL # endif diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index e0c6965..5bbb8e7 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -76,9 +76,15 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM866M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "bootfile=/tftpboot/TQM885D/uImage\0" \ + "fdt_addr=400C0000\0" \ + "kernel_addr=40100000\0" \ + "ramdisk_addr=40280000\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=protect off 40000000 +${filesize};" \ + "erase 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "protect on 40000000 +${filesize}\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -137,7 +143,7 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ +#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ #define CONFIG_TIMESTAMP /* but print image timestmps */ @@ -223,7 +229,7 @@ #define CFG_FLASH_BASE 0x40000000 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -243,8 +249,8 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -- cgit v1.1 From e318d9e9021a0af7508171f84ed09d0e79f0284e Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Thu, 27 Sep 2007 11:10:08 +0200 Subject: TQM8xx: use the CFI flash driver on all TQM8xx boards Signed-off-by: Martin Krause --- include/configs/HMI10.h | 12 ++++++++---- include/configs/TQM823L.h | 12 ++++++++---- include/configs/TQM823M.h | 14 +++++++++----- include/configs/TQM850L.h | 12 ++++++++---- include/configs/TQM850M.h | 14 +++++++++----- include/configs/TQM855L.h | 12 ++++++++---- include/configs/TQM855M.h | 14 +++++++++----- include/configs/TQM860L.h | 12 ++++++++---- include/configs/TQM860M.h | 13 ++++++++----- include/configs/TQM862L.h | 13 ++++++++----- include/configs/TQM862M.h | 15 +++++++++------ include/configs/TQM866M.h | 13 ++++++++----- include/configs/TQM885D.h | 12 ++++++++---- include/configs/virtlab2.h | 12 ++++++++---- 14 files changed, 116 insertions(+), 64 deletions(-) (limited to 'include') diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h index 02ae5d0..f8b0262 100644 --- a/include/configs/HMI10.h +++ b/include/configs/HMI10.h @@ -224,11 +224,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 7a38010..be5b4d3 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -192,11 +192,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index e8b6a80..a0c01b6 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -188,15 +188,19 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index beeca63..f51b12e 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -179,11 +179,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index d5609c1..a725e71 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -177,15 +177,19 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index e35b5b2..16dc3eb 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -183,11 +183,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index cd5212e..c4b4599 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -217,15 +217,19 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index d5838db..ac22c1e 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -186,11 +186,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 44ad53e..8601de1 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -189,11 +189,14 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index f09d3d1..2bf4a2a 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -186,14 +186,17 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 039aa3a..d42ffc9 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -186,16 +186,19 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index ca3c166..d7e5eeb 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -232,11 +232,14 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index 5bbb8e7..8a3aa4b 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -241,11 +241,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index edae6f4..827a28f 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -193,11 +193,15 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -- cgit v1.1 From 33ed73bc0e38d0f2b5c183d4629d8f207e5b9994 Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Mon, 12 Nov 2007 10:56:17 +0100 Subject: Some configuration updates for the TQM5200 based TB5200 board: - enable command line history - increase malloc space (because of bigger flash sectors) Signed-off-by: Martin Krause --- include/configs/TB5200.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 1c6a9ae..ae8d9ab 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -335,7 +335,7 @@ #else #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ #endif /* CONFIG_TQM5200_B */ -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ +#define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* @@ -392,6 +392,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -- cgit v1.1 From 136288847e3b04f2ff357a067ad45e10afa0a24c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 13 Dec 2007 14:52:53 +0100 Subject: ppc4xx: Bring 4xx fdt support up-to-date This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 3 +-- include/configs/sequoia.h | 6 ++++++ 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index e3f24a44..bec9fde 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -519,7 +519,6 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,405EX@0" +#define OF_CPU "cpu@0" #endif /* __CONFIG_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 2af675a..58acbc0 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -487,4 +487,10 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define OF_CPU "cpu@0" + #endif /* __CONFIG_H */ -- cgit v1.1 From 052440b022ca8981d39b6f8c10d1aa6326f47480 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Klotzb=C3=BCcher?= Date: Fri, 23 Nov 2007 13:09:18 +0100 Subject: ppc4xx: Add CONFIG_BOOTP_SUBNETMASK to Sequoia board config When using dhcp/bootp the "netmask" environment variable is not set because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is desireable, so the following patch adds this this option to the board config. Signed-off-by: Markus Klotzbuecher Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 58acbc0..419ee73 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -329,6 +329,7 @@ #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK /* -- cgit v1.1 From 328a340392a5df9aaf00792be989df73e750859e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 18 Dec 2007 08:44:51 +0100 Subject: ppc4xx: fdt: Cleanup setup of cpu node setup Now the cpu node setup ("timebase-frequency" and "clock-frequency") is without using the absolute path to the cpu node. This makes it possible to use this U-Boot version with both versions of cpu-node naming "cpu@0" and the former "PowerPC,440EPx@0". Signed-off-by: Stefan Roese --- include/configs/kilauea.h | 1 - include/configs/sequoia.h | 1 - 2 files changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index bec9fde..f3e8601 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -519,6 +519,5 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "cpu@0" #endif /* __CONFIG_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 419ee73..48a64e3 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -492,6 +492,5 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "cpu@0" #endif /* __CONFIG_H */ -- cgit v1.1 From bf8324e4a50758daff8cddd04c6a2ff8ed775bea Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 19 Dec 2007 09:05:40 +0100 Subject: ppc4xx: Add fdt support to AMCC Katmai eval board Signed-off-by: Stefan Roese --- include/configs/katmai.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 2eed941..0aa4f2d 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -193,8 +193,14 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ + "net_nfs_fdt=tftp 200000 ${bootfile};" \ + "tftp ${fdt_addr} ${fdt_file};" \ + "run nfsargs addip addtty;" \ + "bootm 200000 - ${fdt_addr}\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=katmai/uImage\0" \ + "fdt_file=katmai/katmai.dtb\0" \ + "fdt_addr=400000\0" \ "kernel_addr=fff10000\0" \ "ramdisk_addr=fff20000\0" \ "initrd_high=30000000\0" \ @@ -445,4 +451,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ -- cgit v1.1 From b0265b576bb8fa9465f99e99c323768b562fadc2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 21 Dec 2007 07:51:29 +0100 Subject: ppc4xx: Update Makalu fdt support Signed-off-by: Stefan Roese --- include/configs/makalu.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 2871a6c..8f8e867 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -394,6 +394,4 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,405EX@0" - #endif /* __CONFIG_H */ -- cgit v1.1 From 42d55ea0bde06e47d5a3b49b0d91002acd8e5708 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 22 Dec 2007 12:20:09 +0100 Subject: ppc4xx: Move virtual address of POST cache test to bigger address On Sequoia & LWMON5 the virtual address of the POST cache test is now moved to a bigger address. This enables usage of more memory on those boards. Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 2 +- include/configs/sequoia.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 9cb483d..5210024 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -153,7 +153,7 @@ CFG_POST_SPR | \ CFG_POST_UART) -#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ +#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CONFIG_LOGBUFFER #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 48a64e3..1f72b54 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -377,7 +377,7 @@ #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CONFIG_LOGBUFFER -#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ +#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ -- cgit v1.1 From 9e2c347151db5ae8acf5f18b99493cd53e6637e3 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Thu, 27 Dec 2007 09:52:17 -0500 Subject: Add driver for National Semiconductor LM73 temperature sensor This driver is based on the driver for the LM75. Signed-off-by: Larry Johnson --- include/dtt.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dtt.h b/include/dtt.h index 2e8c690..4e8aaad 100644 --- a/include/dtt.h +++ b/include/dtt.h @@ -31,7 +31,8 @@ defined(CONFIG_DTT_DS1621) || \ defined(CONFIG_DTT_DS1775) || \ defined(CONFIG_DTT_LM81) || \ - defined(CONFIG_DTT_ADM1021) + defined(CONFIG_DTT_ADM1021) || \ + defined(CONFIG_DTT_LM73) #define CONFIG_DTT /* We have a DTT */ @@ -119,4 +120,13 @@ extern int dtt_get_temp(int sensor); #define DTT_ADM1021_DEVID 0x41 #endif +#if defined(CONFIG_DTT_LM73) +#define DTT_READ_TEMP 0x0 +#define DTT_CONFIG 0x1 +#define DTT_TEMP_HIGH 0x2 +#define DTT_TEMP_LOW 0x3 +#define DTT_CONTROL 0x4 +#define DTT_ID 0x7 +#endif + #endif /* _DTT_H_ */ -- cgit v1.1 From c46f53333b22b1f9098676bea8884fc7db820cf3 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sat, 22 Dec 2007 15:15:13 -0500 Subject: Add definitions for 440EPx/GRx SDRAM controller to ppc440.h This patch adds the Denali SDRAM controller definitions to "ppc440.h". It also fixes two typos in the definitions, so the board-specific "sdram.h" files containing these definitions are also fixed to avoid compiler warnings. Signed-off-by: Larry Johnson --- include/ppc440.h | 514 +++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 466 insertions(+), 48 deletions(-) (limited to 'include') diff --git a/include/ppc440.h b/include/ppc440.h index 21e8836..90e56b0 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -19,6 +19,30 @@ | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +----------------------------------------------------------------------------*/ +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef __PPC440_H__ #define __PPC440_H__ @@ -186,54 +210,6 @@ #define sdr_plbtr 0x4200 #define sdr_mfr 0x4300 /* SDR0_MFR reg */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */ -#define DDR0_00 0x00 -#define DDR0_01 0x01 -#define DDR0_02 0x02 -#define DDR0_03 0x03 -#define DDR0_04 0x04 -#define DDR0_05 0x05 -#define DDR0_06 0x06 -#define DDR0_07 0x07 -#define DDR0_08 0x08 -#define DDR0_09 0x09 -#define DDR0_10 0x0A -#define DDR0_11 0x0B -#define DDR0_12 0x0C -#define DDR0_13 0x0D -#define DDR0_14 0x0E -#define DDR0_15 0x0F -#define DDR0_16 0x10 -#define DDR0_17 0x11 -#define DDR0_18 0x12 -#define DDR0_19 0x13 -#define DDR0_20 0x14 -#define DDR0_21 0x15 -#define DDR0_22 0x16 -#define DDR0_23 0x17 -#define DDR0_24 0x18 -#define DDR0_25 0x19 -#define DDR0_26 0x1A -#define DDR0_27 0x1B -#define DDR0_28 0x1C -#define DDR0_29 0x1D -#define DDR0_30 0x1E -#define DDR0_31 0x1F -#define DDR0_32 0x20 -#define DDR0_33 0x21 -#define DDR0_34 0x22 -#define DDR0_35 0x23 -#define DDR0_36 0x24 -#define DDR0_37 0x25 -#define DDR0_38 0x26 -#define DDR0_39 0x27 -#define DDR0_40 0x28 -#define DDR0_41 0x29 -#define DDR0_42 0x2A -#define DDR0_43 0x2B -#define DDR0_44 0x2C -#endif /*CONFIG_440EPX*/ - /*----------------------------------------------------------------------------- | SDRAM Controller +----------------------------------------------------------------------------*/ @@ -817,6 +793,448 @@ #define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ #endif /* CONFIG_440SPE */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +/*----------------------------------------------------------------------------- + | SDRAM Controller + +----------------------------------------------------------------------------*/ +#define DDR0_00 0x00 +#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ +#define DDR0_00_INT_ACK_ALL 0x7F000000 +#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +/* Status */ +#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ +/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT0 0x00010000 +/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT1 0x00020000 +/* Bit2. Single correctable ECC event detected */ +#define DDR0_00_INT_STATUS_BIT2 0x00040000 +/* Bit3. Multiple correctable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT3 0x00080000 +/* Bit4. Single uncorrectable ECC event detected. */ +#define DDR0_00_INT_STATUS_BIT4 0x00100000 +/* Bit5. Multiple uncorrectable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT5 0x00200000 +/* Bit6. DRAM initialization complete. */ +#define DDR0_00_INT_STATUS_BIT6 0x00400000 +/* Bit7. Logical OR of all lower bits. */ +#define DDR0_00_INT_STATUS_BIT7 0x00800000 + +#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 +#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_00_DLL_START_POINT_MASK 0x0000007F +#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_01 0x01 +#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 +#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 +#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ +#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_01_INT_MASK_MASK 0x000000FF +#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) +#define DDR0_01_INT_MASK_ALL_ON 0x000000FF +#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 + +#define DDR0_02 0x02 +#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ +#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) +#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) +#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ +#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ +#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_02_START_MASK 0x00000001 +#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) +#define DDR0_02_START_OFF 0x00000000 +#define DDR0_02_START_ON 0x00000001 + +#define DDR0_03 0x03 +#define DDR0_03_BSTLEN_MASK 0x07000000 +#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_03_CASLAT_MASK 0x00070000 +#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 +#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_03_INITAREF_MASK 0x0000000F +#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_04 0x04 +#define DDR0_04_TRC_MASK 0x1F000000 +#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_04_TRRD_MASK 0x00070000 +#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_04_TRTP_MASK 0x00000700 +#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) + +#define DDR0_05 0x05 +#define DDR0_05_TMRD_MASK 0x1F000000 +#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_05_TEMRS_MASK 0x00070000 +#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_05_TRP_MASK 0x00000F00 +#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_05_TRAS_MIN_MASK 0x000000FF +#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#define DDR0_06 0x06 +#define DDR0_06_WRITEINTERP_MASK 0x01000000 +#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_06_TWTR_MASK 0x00070000 +#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_06_TDLL_MASK 0x0000FF00 +#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_06_TRFC_MASK 0x0000007F +#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_07 0x07 +#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 +#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_07_TFAW_MASK 0x001F0000 +#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 +#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_07_AREFRESH_MASK 0x00000001 +#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_08 0x08 +#define DDR0_08_WRLAT_MASK 0x07000000 +#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_08_TCPD_MASK 0x00FF0000 +#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_08_DQS_N_EN_MASK 0x00000100 +#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 +#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_09 0x09 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_09_RTT_0_MASK 0x00030000 +#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 +#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F +#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_10 0x0A +#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ +#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_10_CS_MAP_MASK 0x00000300 +#define DDR0_10_CS_MAP_NO_MEM 0x00000000 +#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 +#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 +#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F +#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) + +#define DDR0_11 0x0B +#define DDR0_11_SREFRESH_MASK 0x01000000 +#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_11_TXSNR_MASK 0x00FF0000 +#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_11_TXSR_MASK 0x0000FF00 +#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) + +#define DDR0_12 0x0C +#define DDR0_12_TCKE_MASK 0x0000007 +#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) +#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) + +#define DDR0_14 0x0E +#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 +#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_14_REDUC_MASK 0x00010000 +#define DDR0_14_REDUC_64BITS 0x00000000 +#define DDR0_14_REDUC_32BITS 0x00010000 +#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 +#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) + +#define DDR0_17 0x11 +#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 +#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ +#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 +#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 +#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ +#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) + +#define DDR0_18 0x12 +#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 +#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 +#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 +#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F +#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_19 0x13 +#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 +#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 +#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 +#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F +#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_20 0x14 +#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 +#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 +#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 +#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F +#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_21 0x15 +#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 +#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 +#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 +#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F +#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_22 0x16 +#define DDR0_22_CTRL_RAW_MASK 0x03000000 +#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ +#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct */ +#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ +#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ +#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 +#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F +#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_23 0x17 +#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 +#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ +#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ +#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ +#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_24 0x18 +#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 +#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 +#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 +#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 +#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) +#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) + +#define DDR0_25 0x19 +#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ +#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ +#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define DDR0_26 0x1A +#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 +#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_26_TREF_MASK 0x00003FFF +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) + +#define DDR0_27 0x1B +#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 +#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_27_TINIT_MASK 0x0000FFFF +#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_28 0x1C +#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 +#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF +#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) + +#define DDR0_31 0x1F +#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF +#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_32 0x20 +#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_33 0x21 +#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_34 0x22 +#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_35 0x23 +#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_36 0x24 +#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_37 0x25 +#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_38 0x26 +#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_39 0x27 +#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_40 0x28 +#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_41 0x29 +#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_42 0x2A +#define DDR0_42_ADDR_PINS_MASK 0x07000000 +#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F +#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_43 0x2B +#define DDR0_43_TWR_MASK 0x07000000 +#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_43_APREBIT_MASK 0x000F0000 +#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 +#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 +#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_44 0x2C +#define DDR0_44_TRCD_MASK 0x000000FF +#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#endif /* CONFIG_440EPX */ + /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ -- cgit v1.1 From 87dc096829e6a6363f4fdd73653b0093a85adbe0 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sat, 22 Dec 2007 15:16:25 -0500 Subject: Add configuration file for Korat board This patch supplies the configuration file for the Korat PPC440EPx- processor board. Signed-off-by: Larry Johnson --- include/configs/korat.h | 376 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 376 insertions(+) create mode 100644 include/configs/korat.h (limited to 'include') diff --git a/include/configs/korat.h b/include/configs/korat.h new file mode 100644 index 0000000..1ea7d48 --- /dev/null +++ b/include/configs/korat.h @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2007 + * Larry Johnson, lrj@acm.org + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * korat.h - configuration for Korat board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333333 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Manufacturer's information serial EEPROM parameters + *----------------------------------------------------------------------*/ +#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */ +#define MAN_SERIAL_NO_FIELD 2 +#define MAN_SERIAL_NO_LENGTH 13 +#define MAN_MAC_ADDR_FIELD 3 +#define MAN_MAC_ADDR_LENGTH 17 + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 +#define CFG_CPLD_BASE 0xc0000000 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */ +#undef CFG_INIT_RAM_DCACHE +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */ +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */ +#define CONFIG_DDR_ECC /* Use ECC when available */ +#define SPD_EEPROM_ADDRESS {0x50} +#define CONFIG_PROG_SDRAM_TLB +#define CFG_DRAM_TEST + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C RTC */ +#define CONFIG_RTC_M41T60 1 +#define CFG_I2C_RTC_ADDR 0x68 + +/* I2C SYSMON (LM73) */ +#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */ +#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_MIN_TEMP -30 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME korat +#define CFG_BOOTFILE "bootfile=/tftpboot/korat/uImage\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CFG_BOOTFILE \ + CFG_ROOTPATH \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ + "cp.b 200000 FFFA0000 60000\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ +#define CONFIG_PHY_DYNAMIC_ANEG 1 + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 3 + +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_I2C_CMD_TREE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_USB + +/* POST support */ +#define CONFIG_POST (CFG_POST_CACHE | \ + CFG_POST_CPU | \ + CFG_POST_ECC | \ + CFG_POST_ETHER | \ + CFG_POST_FPU | \ + CFG_POST_I2C | \ + CFG_POST_MEMORY | \ + CFG_POST_RTC | \ + CFG_POST_SPR | \ + CFG_POST_UART) + +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0xC8000000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +#define CONFIG_SUPPORT_VFAT + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x04017300 +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0x000DA000) + +/* Memory Bank 1 (NOR-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x04017300 +#define CFG_EBC_PB1CR (0xF8000000 | 0x000DA000) + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x04017300 +#define CFG_EBC_PB2CR (CFG_CPLD_BASE | 0x00038000) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ -- cgit v1.1 From b568fd25574181a3b12ae3d66b2913903442cb83 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Thu, 27 Dec 2007 17:03:46 +0100 Subject: Remove CPCI440 board This board never left prototyping state and it became a millstone round my neck. So remove it. Signed-off-by: Matthias Fuchs --- include/configs/CPCI440.h | 287 ---------------------------------------------- 1 file changed, 287 deletions(-) delete mode 100644 include/configs/CPCI440.h (limited to 'include') diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h deleted file mode 100644 index eb47cd7..0000000 --- a/include/configs/CPCI440.h +++ /dev/null @@ -1,287 +0,0 @@ -/* - * (C) Copyright 2002 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * board/config_CPCI440.h - configuration for esd CPCI-440 board - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_CPCI440 1 /* Board is ebony */ -#define CONFIG_440GP 1 /* Specifc GP support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#if 1 -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#else -#define CFG_MONITOR_BASE 0x01fc0000 /* start of monitor */ -#endif -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ - -#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#if 1 /* test-only */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#undef CFG_FLASH_BASE -#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/ - -#else /* test-only */ - -#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ -#define CFG_MAX_FLASH_SECT 32 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#endif - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#if 0 /* test-only */ -#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ - -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) -#else - -#if 0 /* test-only */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ -#else -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -#endif - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#if 0 /* test-only */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#endif - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#if 0 -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ -- cgit v1.1 From b56bd0fcfc1c73db722e3462c8a9bf607ba7775e Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 28 Dec 2007 17:10:42 +0100 Subject: ppc4xx: Maintenance patch for VOH405 boards - add EEPROM write protection - initialize NAND GPIOs - use correct io accessors - slow down I2C clock to 100kHz - enable ext. I2C bus - cleanup Signed-off-by: Matthias Fuchs --- include/configs/VOH405.h | 31 +++++++++++-------------------- 1 file changed, 11 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 3a413f5..3ca928e 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -52,9 +52,13 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ @@ -204,8 +208,6 @@ #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ -#define CONFIG_ATAPI 1 /* ATAPI for Travelstar */ - #define CFG_ATA_BASE_ADDR 0xF0100000 #define CFG_ATA_IDE0_OFFSET 0x0000 #define CFG_ATA_IDE1_OFFSET 0x0010 @@ -244,11 +246,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -281,19 +278,12 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#if 0 /* test-only */ -/* CAT24WC08/16... */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#else +#define CFG_EEPROM_WREN 1 + /* CAT24WC32/64... */ #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ @@ -301,7 +291,6 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ /* 32 byte page write mode using*/ /* last 5 bits of the address */ -#endif #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE @@ -400,18 +389,20 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO */ -#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRH 0x00000550 #define CFG_GPIO0_OSRL 0x00000110 #define CFG_GPIO0_ISR1H 0x00000000 #define CFG_GPIO0_ISR1L 0x15555440 #define CFG_GPIO0_TSRH 0x00000000 #define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FE0017 +#define CFG_GPIO0_TCR 0x777E0017 #define CFG_DUART_RST (0x80000000 >> 14) #define CFG_LCD_ENDIAN (0x80000000 >> 7) +#define CFG_IIC_ON (0x80000000 >> 8) #define CFG_LCD0_RST (0x80000000 >> 30) #define CFG_LCD1_RST (0x80000000 >> 31) +#define CFG_EEPROM_WP (0x80000000 >> 0) /* * Internal Definitions -- cgit v1.1 From f6e0f1f61896ce7729ba1bcea2ffbd138d3947f5 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 28 Dec 2007 17:10:36 +0100 Subject: ppc4xx: Add EEPROM write protection for PLU405 boards + misc. updates - add EEPROM write protection for esd PLU405 boards. - initialize NAND GPIOs - use correct io accessors - cleanup Signed-off-by: Matthias Fuchs --- include/configs/PLU405.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 6b16654..0bd77c0 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -288,6 +288,7 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ +#define CFG_EEPROM_WREN 1 /* CAT24WC08/16... */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ @@ -379,15 +380,16 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRH 0x00000550 #define CFG_GPIO0_OSRL 0x00000110 #define CFG_GPIO0_ISR1H 0x00000000 #define CFG_GPIO0_ISR1L 0x15555445 #define CFG_GPIO0_TSRH 0x00000000 #define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FE0014 +#define CFG_GPIO0_TCR 0x77FE0014 #define CFG_DUART_RST (0x80000000 >> 14) +#define CFG_EEPROM_WP (0x80000000 >> 0) /* * Internal Definitions -- cgit v1.1 From 8ba132cab18ae438b6dd5b0214c28a8fc0d976e5 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 28 Dec 2007 17:07:24 +0100 Subject: ppc4xx: Complete PMC440 board support This patch brings the PMC440 board configuration file. Finally it enables the PMC440 board support. Signed-off-by: Matthias Fuchs --- include/configs/PMC440.h | 522 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 522 insertions(+) create mode 100644 include/configs/PMC440.h (limited to 'include') diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h new file mode 100644 index 0000000..3d2ed1e --- /dev/null +++ b/include/configs/PMC440.h @@ -0,0 +1,522 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. + * Based on the sequoia configuration file. + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * PMC440.h - configuration for esd PMC440 boards + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ + +#define CONFIG_SYS_CLK_FREQ 33333400 + +#define CONFIG_4xx_DCACHE /* enable dcache */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */ + +#define CONFIG_PRAM 0 /* use pram variable to overwrite */ + +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 +#define CFG_PCI_MEMSIZE 0x80000000 /* 2GB! */ + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 +#define CFG_FPGA_BASE0 0xef000000 /* 32 bit */ +#define CFG_FPGA_BASE1 0xef100000 /* 16 bit */ + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +#undef CONFIG_UART1_CONSOLE /* console on front panel */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ +#endif + +/*----------------------------------------------------------------------- + * RTC + *----------------------------------------------------------------------*/ +#define CONFIG_RTC_RX8025 + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */ +#endif + +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 4k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 4kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + * On 440EPx the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from cache, I experienced problems accessing + * the NAND controller. sr - 2006-08-25 + */ +#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ +#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ +#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ +#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ + +/* + * Now the NAND chip has to be defined (no autodetection used!) + */ +#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ +#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ + +#define CFG_NAND_ECCSIZE 256 +#define CFG_NAND_ECCBYTES 3 +#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) +#define CFG_NAND_OOBSIZE 16 +#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) +#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} + +#ifdef CFG_ENV_IS_IN_NAND +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/sequoia/u-boot-nand.lds for details. + */ +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (256) /* 256MB */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#endif + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CONFIG_I2C_CMD_TREE 1 +#define CONFIG_I2C_MULTI_BUS 1 + +#define CFG_I2C_MULTI_EEPROMS + +#define CFG_I2C_EEPROM_ADDR 0x54 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 + +#define CFG_EEPROM_WREN 1 +#define CFG_I2C_BOOT_EEPROM_ADDR 0x52 + +/* + * standard dtt sensor configuration - bottom bit will determine local or + * remote sensor of the TMP401 + */ +#define CONFIG_DTT_SENSORS { 0, 1 } + +/* + * The PMC440 uses a TI TMP401 temperature sensor. This part + * is basically compatible to the ADM1021 that is supported + * by U-Boot. + * + * - i2c addr 0x4c + * - conversion rate 0x02 = 0.25 conversions/second + * - ALERT ouput disabled + * - local temp sensor enabled, min set to 0 deg, max set to 70 deg + * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg + */ +#define CONFIG_DTT_ADM1021 +#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} } + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME pmc440 +#define CFG_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk_410/ppc_4xx\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CFG_BOOTFILE \ + CFG_ROOTPATH \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \ + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ + "cp.b 200000 FFFA0000 60000\0" \ + "" + +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_STORAGE +#define CFG_OHCI_BE_CONTROLLER + +#define CFG_USB_OHCI_BOARD_INIT 1 +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST +#define CFG_USB_OHCI_SLOT_NAME "ppc440" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#include + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +/* POST support */ +/* ethernet POST sometimes freezes the CPU. + * So disable it for now until issue is solved + */ +#if 0 +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_FPU | \ + CFG_POST_ETHER | \ + CFG_POST_SPR) +#else +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_FPU | \ + CFG_POST_SPR) +#endif + +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) + +/* esd expects pram at end of physical memory. + * So no logbuffer at the moment. + */ +#if 0 +#define CONFIG_LOGBUFFER +#endif +#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +#define CONFIG_SUPPORT_VFAT + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#undef CONFIG_AUTOBOOT_DELAY_STR +#define CONFIG_AUTOBOOT_STOP_STR " " + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +/* PCI identification */ +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */ +#define CFG_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */ +#define CFG_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC +#define CFG_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FPGA stuff + *----------------------------------------------------------------------*/ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN2 +#define CONFIG_FPGA_SPARTAN3 + +#define CONFIG_FPGA_COUNT 2 +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ + +/* + * On Sequoia CS0 and CS3 are switched when configuring for NAND booting + */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_NAND_CS 2 /* NAND chip connected to CSx */ + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03017200 +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) + +/* Memory Bank 2 (NAND-FLASH) initialization */ +#define CFG_EBC_PB2AP 0x018003c0 +#define CFG_EBC_PB2CR (CFG_NAND_ADDR | 0x1c000) +#else +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ +/* Memory Bank 2 (NOR-FLASH) initialization */ +#define CFG_EBC_PB2AP 0x03017200 +#define CFG_EBC_PB2CR (CFG_FLASH_BASE | 0xda000) + +/* Memory Bank 0 (NAND-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x018003c0 +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) +#endif + +/* Memory Bank 4 (FPGA / 32Bit) initialization */ +#define CFG_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */ +#define CFG_EBC_PB4CR (CFG_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */ + +/* Memory Bank 5 (FPGA / 16Bit) initialization */ +#define CFG_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */ +#define CFG_EBC_PB5CR (CFG_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#endif /* __CONFIG_H */ -- cgit v1.1 From 3dfd708cc1b2a966ad454ca9ed125dd17dbadbcc Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 2 Jan 2008 12:38:43 +0100 Subject: Minor coding style cleanup. Signed-off-by: Wolfgang Denk --- include/libfdt.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/libfdt.h b/include/libfdt.h index 6b2fb92..8253ccf 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -544,7 +544,7 @@ int fdt_parent_offset(const void *fdt, int nodeoffset); * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, * propval, proplen); * while (offset != -FDT_ERR_NOTFOUND) { - * // other code here + * /* other code here */ * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, * propval, proplen); * } @@ -629,7 +629,7 @@ int fdt_node_check_compatible(const void *fdt, int nodeoffset, * idiom can be used: * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); * while (offset != -FDT_ERR_NOTFOUND) { - * // other code here + * /* other code here */ * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); * } * -- cgit v1.1 From 1182e9f8e3b92fc372d64943293de53daa2e26cf Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 2 Jan 2008 15:58:44 +0100 Subject: Fix compile problem introduced by "cleanup" commit 3dfd708c Signed-off-by: Wolfgang Denk --- include/libfdt.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/libfdt.h b/include/libfdt.h index 8253ccf..8050049 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -544,7 +544,7 @@ int fdt_parent_offset(const void *fdt, int nodeoffset); * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, * propval, proplen); * while (offset != -FDT_ERR_NOTFOUND) { - * /* other code here */ + * ... other code here ... * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, * propval, proplen); * } @@ -629,7 +629,7 @@ int fdt_node_check_compatible(const void *fdt, int nodeoffset, * idiom can be used: * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); * while (offset != -FDT_ERR_NOTFOUND) { - * /* other code here */ + * ... other code here ... * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); * } * -- cgit v1.1 From ea9f7395ec362584e5e4f266bd0b0c4422cf6a4c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 28 Nov 2007 14:47:18 -0600 Subject: Convert MPC8641HPCN to use libfdt. Assumes the presence of the aliases node in the DTS to locate the ethernet, pci and serial nodes for fixups. Use consistent fdtaddr and fdtfile in environment variables. Signed-off-by: Jon Loeliger --- include/configs/MPC8641HPCN.h | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 6f87240..0fc6521 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -267,13 +267,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * Pass open firmware flat tree to kernel */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 -#define OF_CPU "PowerPC,8641@0" -#define OF_SOC "soc8641@f8000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 @@ -645,8 +642,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ - "dtbaddr=c00000\0" \ - "dtbfile=mpc8641_hpcn.dtb\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=mpc8641_hpcn.dtb\0" \ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ "maxcpus=2" @@ -658,16 +655,16 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr $ramdiskaddr $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND -- cgit v1.1 From 61d3421bdea090bd0399b14c3e10a3bebcc8d5ff Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 4 Dec 2007 10:53:34 -0600 Subject: Don't slam #undef DEBUG in the 8641HPCN config file. Doing so prevents it from being individually set and useful in other files. Signed-off-by: Jon Loeliger --- include/configs/MPC8641HPCN.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 0fc6521..575bbae 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -38,7 +38,6 @@ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -#undef DEBUG #ifdef RUN_DIAG #define CFG_DIAG_ADDR 0xff800000 -- cgit v1.1