From 36ad18a6db0eec546b83e6500ceb7593be53a1ed Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Mon, 27 Aug 2012 19:38:59 -0500 Subject: libfdt: Add support for appending the values to a existing property Some properties may contain multiple values, these values may need to be added to the property respectively. this patch provides this functionality. The main purpose of fdt_append_prop() is to append the values to a existing property, or create a new property if it dose not exist. Signed-off-by: Minghuan Lian Signed-off-by: David Gibson --- include/libfdt.h | 95 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) (limited to 'include') diff --git a/include/libfdt.h b/include/libfdt.h index de82ed5..78798e8 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -1134,6 +1134,101 @@ static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) /** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_cell - append a single cell value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_cell() appends the given cell value (converting to + * big-endian if necessary) to the value of the named property in the + * given node, or creates a new property with that value if it does + * not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + val = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** * fdt_delprop - delete a property * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to nop -- cgit v1.1 From 24fa0e588e68dfb4b15d1e94c543c9301d226902 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 27 Aug 2012 19:39:00 -0500 Subject: libfdt: Add helpers for 64-bit integer properties In device trees in the world, properties consisting of a single 64-bit integer are not as common as those consisting of a single 32-bit, cell sized integer, but they're common enough that they're worth including convenience functions for. This patch adds helper wrappers of fdt_setprop_inplace(), fdt_setprop() and fdt_appendprop() for handling 64-bit integer quantities in properties. For better consistency with the names of these new *_u64() functions we also add *_u32() functions as alternative names for the existing *_cell() functions handling 32-bit integers. Signed-off-by: David Gibson --- include/libfdt.h | 193 ++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 170 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/include/libfdt.h b/include/libfdt.h index 78798e8..4589c5f 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -852,17 +852,17 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, const void *val, int len); /** - * fdt_setprop_inplace_cell - change the value of a single-cell property + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change * @name: name of the property to change - * @val: cell (32-bit integer) value to replace the property with + * @val: 32-bit integer value to replace the property with * - * fdt_setprop_inplace_cell() replaces the value of a given property - * with the 32-bit integer cell value in val, converting val to - * big-endian if necessary. This function cannot change the size of a - * property, and so will only work if the property already exists and - * has length 4. + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. * * This function will alter only the bytes in the blob which contain * the given property value, and will not alter or move any other part @@ -871,7 +871,7 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, * returns: * 0, on success * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 - * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_NOTFOUND, node does not have the named property * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag * -FDT_ERR_BADMAGIC, * -FDT_ERR_BADVERSION, @@ -879,14 +879,60 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, * -FDT_ERR_BADSTRUCTURE, * -FDT_ERR_TRUNCATED, standard meanings */ -static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, - const char *name, uint32_t val) +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) { val = cpu_to_fdt32(val); return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); } /** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + val = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + +/** * fdt_nop_property - replace a property with nop tags * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to nop @@ -945,11 +991,20 @@ int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); int fdt_finish_reservemap(void *fdt); int fdt_begin_node(void *fdt, const char *name); int fdt_property(void *fdt, const char *name, const void *val, int len); -static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) { val = cpu_to_fdt32(val); return fdt_property(fdt, name, &val, sizeof(val)); } +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + val = cpu_to_fdt64(val); + return fdt_property(fdt, name, &val, sizeof(val)); +} +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} #define fdt_property_string(fdt, name, str) \ fdt_property(fdt, name, str, strlen(str)+1) int fdt_end_node(void *fdt); @@ -1068,14 +1123,14 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, const void *val, int len); /** - * fdt_setprop_cell - set a property to a single cell value + * fdt_setprop_u32 - set a property to a 32-bit integer * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change * @name: name of the property to change * @val: 32-bit integer value for the property (native endian) * - * fdt_setprop_cell() sets the value of the named property in the - * given node to the given cell value (converting to big-endian if + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if * necessary), or creates a new property with that value if it does * not already exist. * @@ -1095,14 +1150,60 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, * -FDT_ERR_BADLAYOUT, * -FDT_ERR_TRUNCATED, standard meanings */ -static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, - uint32_t val) +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) { val = cpu_to_fdt32(val); return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); } /** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + val = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + +/** * fdt_setprop_string - set a property to a string value * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change @@ -1164,16 +1265,16 @@ int fdt_appendprop(void *fdt, int nodeoffset, const char *name, const void *val, int len); /** - * fdt_appendprop_cell - append a single cell value to a property + * fdt_appendprop_u32 - append a 32-bit integer value to a property * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change * @name: name of the property to change * @val: 32-bit integer value to append to the property (native endian) * - * fdt_appendprop_cell() appends the given cell value (converting to - * big-endian if necessary) to the value of the named property in the - * given node, or creates a new property with that value if it does - * not already exist. + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. * * This function may insert data into the blob, and will therefore * change the offsets of some existing nodes. @@ -1191,14 +1292,60 @@ int fdt_appendprop(void *fdt, int nodeoffset, const char *name, * -FDT_ERR_BADLAYOUT, * -FDT_ERR_TRUNCATED, standard meanings */ -static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, - const char *name, uint32_t val) +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) { val = cpu_to_fdt32(val); return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); } /** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + val = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + +/** * fdt_appendprop_string - append a string to a property * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change -- cgit v1.1 From 8ac88f2d2818c8efc1558626a4e7fb47dcc18987 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 17 Aug 2012 10:34:39 +0000 Subject: fdt: Check for a token to skip auto-hash validation Allow the itb file to declare to u-boot that its hash should not be checked automatically on bootm or iminfo. This allows an image to either be checked automatically or to include a script which may check it otherwise (such as after part of the itb has been relocated to RAM by the script). Signed-off-by: Joe Hershberger --- include/image.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index e5f6649..4e5863f 100644 --- a/include/image.h +++ b/include/image.h @@ -511,6 +511,7 @@ static inline int image_check_target_arch(const image_header_t *hdr) #define FIT_HASH_NODENAME "hash" #define FIT_ALGO_PROP "algo" #define FIT_VALUE_PROP "value" +#define FIT_IGNORE_PROP "uboot-ignore" /* image node */ #define FIT_DATA_PROP "data" @@ -595,6 +596,9 @@ int fit_image_get_data(const void *fit, int noffset, int fit_image_hash_get_algo(const void *fit, int noffset, char **algo); int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value, int *value_len); +#ifndef USE_HOSTCC +int fit_image_hash_get_ignore(const void *fit, int noffset, int *ignore); +#endif int fit_set_timestamp(void *fit, int noffset, time_t timestamp); int fit_set_hashes(void *fit); -- cgit v1.1 From c71b64f3617b5a4362c6e4e0aefdd66d6ac6affd Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Mon, 15 Oct 2012 22:24:36 -0400 Subject: libfdt: Add helper function to create a trivial, empty tree The libfdt read/write functions are now usable enough that it's become a moderately common pattern to use them to build and manipulate a device tree from scratch. For example, we do so ourself in our rw_tree1 testcase, and qemu is starting to use this model when building device trees for some targets such as e500. However, the read/write functions require some sort of valid tree to begin with, so this necessitates either having a trivial canned dtb to begin with or, more commonly, creating an empty tree using the serial-write functions first. This patch adds a helper function which uses the serial-write functions to create a trivial, empty but complete and valid tree in a supplied buffer, ready for manipulation with the read/write functions. Signed-off-by: David Gibson From git://git.jdl.com/software/dtc.git patch hash be6026838 with adaptations to include/libfdt.h and lib/libfdt/Makefile for the U-Boot environment. Signed-off-by: Gerald Van Baren --- include/libfdt.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/libfdt.h b/include/libfdt.h index 4589c5f..c93ae28 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -1014,6 +1014,7 @@ int fdt_finish(void *fdt); /* Read-write functions */ /**********************************************************************/ +int fdt_create_empty_tree(void *buf, int bufsize); int fdt_open_into(const void *fdt, void *buf, int bufsize); int fdt_pack(void *fdt); -- cgit v1.1 From b1af67fe5e019bbfaca9ca4ec7086fbdb69c440a Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:56 +0000 Subject: i2c: sh_i2c.c: support iccl and icch extension R-mobile SoC (at least SH73A0) has extension bits to store 8th bit of iccl and icch. This patch add support for the extentin bits. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- include/configs/kzm9g.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 3a882e3..0132e9d 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -154,6 +154,7 @@ /* I2C */ #define CONFIG_CMD_I2C #define CONFIG_SH_I2C 1 +#define CONFIG_SH_I2C_8BIT #define CONFIG_HARD_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_MAX_I2C_BUS (2) -- cgit v1.1 From 3ce2703d8f11b0b5c28409d8335f36bef258831b Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:58 +0000 Subject: i2c: sh_i2c.c: adjust for SH73A0 Adjust i2c_raw_read() in sh_i2c.c to work for SH73A0. After this patch, "i2c md" and "i2c mw" command on U-Boot work properly on KZM-A9-GT board. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- include/configs/kzm9g.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 0132e9d..75b9257 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -163,7 +163,7 @@ #define CONFIG_SYS_I2C_SLAVE (0x7F) #define CONFIG_SH_I2C_DATA_HIGH (4) #define CONFIG_SH_I2C_DATA_LOW (5) -#define CONFIG_SH_I2C_CLOCK (41666666) +#define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */ #define CONFIG_SH_I2C_BASE0 (0xE6820000) #define CONFIG_SH_I2C_BASE1 (0xE6822000) -- cgit v1.1 From 020ec727a6bda10f47d69926814d476c0085e8a9 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:59 +0000 Subject: i2c: sh_i2c.c: support I2C2, I2C3 and I2C4 sh_i2c.c support I2C0 and I2C1. This patch extends it to I2C4. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- include/configs/kzm9g.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 75b9257..4898fb6 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -157,7 +157,7 @@ #define CONFIG_SH_I2C_8BIT #define CONFIG_HARD_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS (2) +#define CONFIG_SYS_MAX_I2C_BUS (5) #define CONFIG_SYS_I2C_MODULE #define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */ #define CONFIG_SYS_I2C_SLAVE (0x7F) @@ -166,5 +166,8 @@ #define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */ #define CONFIG_SH_I2C_BASE0 (0xE6820000) #define CONFIG_SH_I2C_BASE1 (0xE6822000) +#define CONFIG_SH_I2C_BASE2 (0xE6824000) +#define CONFIG_SH_I2C_BASE3 (0xE6826000) +#define CONFIG_SH_I2C_BASE4 (0xE6828000) #endif /* __KZM9G_H */ -- cgit v1.1 From 34cda7a0d89297e450106951d554b56ed4c1fd3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Da=C5=82ek?= Date: Mon, 15 Oct 2012 07:46:54 +0000 Subject: h2200: Add support for iPAQ h2200 palmtop Add basic support for HP iPAQ h2200 palmtop. h2200 palmtop was targeted to general consumers. It has 64 MB of RAM, 32 MB flash. No intergrated Wi-Fi nor Ethernet. Based on Intel PXA255 processor. It was shipped with Windows CE 4.2 operating system. Signed-off-by: Lukasz Dalek --- include/configs/h2200.h | 157 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 include/configs/h2200.h (limited to 'include') diff --git a/include/configs/h2200.h b/include/configs/h2200.h new file mode 100644 index 0000000..ef14dd3 --- /dev/null +++ b/include/configs/h2200.h @@ -0,0 +1,157 @@ +/* + * iPAQ h2200 board configuration + * + * Copyright (C) 2012 Lukasz Dalek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define MACH_TYPE_H2200 341 +#define CONFIG_MACH_TYPE MACH_TYPE_H2200 + +#define CONFIG_CPU_PXA25X 1 +#define CONFIG_BOARD_H2200 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE + +#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 + +#define CONFIG_ENV_SIZE 0x00040000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ + +/* + * iPAQ 1st stage bootloader loads 2nd stage bootloader + * at address 0xa0040000 but bootloader requires header + * which is 0x1000 long. + * + * --- Header begin --- + * .word 0xea0003fe ; b 0x1000 + * + * .org 0x40 + * .ascii "ECEC" + * + * .org 0x1000 + * --- Header end --- + */ + +#define CONFIG_SYS_TEXT_BASE 0xa0041000 + +/* + * Static chips + */ + +#define CONFIG_SYS_MSC0_VAL 0x246c7ffc +#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 +#define CONFIG_SYS_MSC2_VAL 0x7ff07ff0 + +/* + * PCMCIA and CF Interfaces + */ + +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00000000 +#define CONFIG_SYS_MCMEM1_VAL 0x00000000 +#define CONFIG_SYS_MCATT0_VAL 0x00000000 +#define CONFIG_SYS_MCATT1_VAL 0x00000000 +#define CONFIG_SYS_MCIO0_VAL 0x00000000 +#define CONFIG_SYS_MCIO1_VAL 0x00000000 + +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00040004 + +#define CONFIG_SYS_MDREFR_VAL 0x0099E018 +#define CONFIG_SYS_MDCNFG_VAL 0x01C801CB +#define CONFIG_SYS_MDMRS_VAL 0x00220022 + +#define CONFIG_SYS_PSSR_VAL 0x00000000 +#define CONFIG_SYS_CKEN 0x00004840 +#define CONFIG_SYS_CCCR 0x00000161 + +/* + * GPIOs + */ + +#define CONFIG_SYS_GPSR0_VAL 0x01000000 +#define CONFIG_SYS_GPSR1_VAL 0x00000000 +#define CONFIG_SYS_GPSR2_VAL 0x00010000 + +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 + +#define CONFIG_SYS_GPDR0_VAL 0xF7E38C00 +#define CONFIG_SYS_GPDR1_VAL 0xBCFFBF83 +#define CONFIG_SYS_GPDR2_VAL 0x000157FF + +#define CONFIG_SYS_GAFR0_L_VAL 0x80401000 +#define CONFIG_SYS_GAFR0_U_VAL 0x00000112 +#define CONFIG_SYS_GAFR1_L_VAL 0x600A9550 +#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA +#define CONFIG_SYS_GAFR2_L_VAL 0x20000000 +#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 + +/* + * Serial port + */ + +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART +#define CONFIG_CONS_INDEX 3 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 } + +#define CONFIG_CMD_IMPORTENV 1 +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_RUN +#define CONFIG_CMD_IMI + +#define CONFIG_FIT +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "> " +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "$ " + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_BOOTARGS "root=/dev/ram0 ro console=ttyS0,115200n8" + +#endif /* __CONFIG_H */ -- cgit v1.1 From ff9b0cb8b4804ed372c09b8aad2a984b396596b2 Mon Sep 17 00:00:00 2001 From: Zhi-zhou Zhang Date: Tue, 16 Oct 2012 15:02:08 +0200 Subject: MIPS: qemu_mips: move CONFIG_SYS_TEXT_BASE to qemu-mips.h We define CONFIG_SYS_TEXT_BASE in board's specified header file. So config.mk is useless, then remove it. Signed-off-by: Zhizhou Zhang --- include/configs/qemu-mips.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index b8b9705..f45f78b 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -137,6 +137,7 @@ */ /* The following #defines are needed to get flash environment right */ +#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) -- cgit v1.1 From 32afad783eb5a372c276fcb9fb30dfb838615909 Mon Sep 17 00:00:00 2001 From: Zhi-zhou Zhang Date: Tue, 16 Oct 2012 15:02:08 +0200 Subject: MIPS: add board qemu-mips64 support Both big-endian and little-endian are tested with below commands: Rom version: (Default, Now we config it as rom version) qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic Ram version: qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic Signed-off-by: Zhizhou Zhang Signed-off-by: Daniel Schwierzeck --- include/configs/qemu-mips64.h | 175 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 include/configs/qemu-mips64.h (limited to 'include') diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h new file mode 100644 index 0000000..82647e2 --- /dev/null +++ b/include/configs/qemu-mips64.h @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for qemu-mips64 target. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS64 /* MIPS64 CPU core */ +#define CONFIG_QEMU_MIPS +#define CONFIG_MISC_INIT_R + +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "panic=1\0" \ + "bootfile=/tftpboot/vmlinux\0" \ + "load=tftp ffffffff80500000 ${u-boot}\0" \ + "" + +#define CONFIG_BOOTCOMMAND "bootp;bootelf" + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_DHCP + +#define CONFIG_DRIVER_NE2000 +#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300 + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 115200 +#define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8 +#define CONFIG_CONS_INDEX 1 + +#define CONFIG_CMD_IDE +#define CONFIG_DOS_PARTITION + +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_BASE_ADDR 0xffffffffb4000000 + +#define CONFIG_SYS_IDE_MAXDEVICE 4 + +#define CONFIG_CMD_RARP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +/* Monitor Command Prompt */ +#if defined(CONFIG_SYS_LITTLE_ENDIAN) +#define CONFIG_SYS_PROMPT "qemu-mips64el # " +#else +#define CONFIG_SYS_PROMPT "qemu-mips64 # " +#endif + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +#define CONFIG_SYS_MALLOC_LEN 128*1024 + +#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 + +#define CONFIG_SYS_MHZ 132 + +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_HZ 1000 + +/* Cached addr */ +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000 + +#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000 +#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +/* The following #defines are needed to get flash environment right */ +#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* Rom version */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (192 << 10) + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +/* We boot from this flash, selected with dip switch */ +#define CONFIG_SYS_FLASH_BASE 0xffffffffbfc00000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) + +/* Address and size of Primary Environment Sector */ +#define CONFIG_ENV_SIZE 0x8000 + +#define CONFIG_ENV_OVERWRITE 1 + +#define MEM_SIZE 128 + +#define CONFIG_LZMA + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */ -- cgit v1.1 From 6b2eba1b7cd661fc6b2b0e0d4d039d1c299e2e07 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Tue, 16 Oct 2012 15:02:08 +0200 Subject: MIPS: qemu_mips.h: cleanup coding style and checkpatch.pl issues Signed-off-by: Daniel Schwierzeck --- include/configs/qemu-mips.h | 54 ++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index f45f78b..5bc7b0d 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -28,14 +28,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ -#define CONFIG_QEMU_MIPS 1 +#define CONFIG_MIPS32 /* MIPS32 CPU core */ +#define CONFIG_QEMU_MIPS #define CONFIG_MISC_INIT_R -/*IP address is default used by Qemu*/ -#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */ -#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */ - #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ #define CONFIG_BAUDRATE 115200 @@ -74,31 +70,31 @@ #define CONFIG_CMD_DHCP #define CONFIG_DRIVER_NE2000 -#define CONFIG_DRIVER_NE2000_BASE (0xb4000300) +#define CONFIG_DRIVER_NE2000_BASE 0xb4000300 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK 115200 -#define CONFIG_SYS_NS16550_COM1 (0xb40003f8) -#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 0xb40003f8 +#define CONFIG_CONS_INDEX 1 #define CONFIG_CMD_IDE #define CONFIG_DOS_PARTITION #define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0) -#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170) -#define CONFIG_SYS_ATA_DATA_OFFSET (0) -#define CONFIG_SYS_ATA_REG_OFFSET (0) -#define CONFIG_SYS_ATA_BASE_ADDR (0xb4000000) +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 -#define CONFIG_SYS_IDE_MAXDEVICE (4) +#define CONFIG_SYS_IDE_MAXDEVICE 4 /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ /* Monitor Command Prompt */ #if defined(CONFIG_SYS_LITTLE_ENDIAN) @@ -111,9 +107,12 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN 128*1024 @@ -125,9 +124,11 @@ #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ +/* Cached addr */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x81000000 #define CONFIG_SYS_MEMTEST_START 0x80100000 #define CONFIG_SYS_MEMTEST_END 0x80800000 @@ -135,7 +136,6 @@ /*----------------------------------------------------------------------- * FLASH and environment organization */ - /* The following #defines are needed to get flash environment right */ #define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE @@ -147,11 +147,11 @@ #define CONFIG_SYS_FLASH_BASE 0xbfc00000 #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) /* Address and size of Primary Environment Sector */ @@ -161,8 +161,6 @@ #define MEM_SIZE 128 -#undef CONFIG_MEMSIZE_IN_BYTES - #define CONFIG_LZMA /*----------------------------------------------------------------------- -- cgit v1.1 From b9f4bc34ac0ee40f8d6a952036b4cd62b854aa74 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 8 Oct 2012 04:11:38 +0000 Subject: Remove lh7a40x cpu and serial driver Since commit 957731ed (ARM: remove broken "lpd7a40x" boards), lh7a40x cpu and serial driver have become unused. Remove them. Signed-off-by: Albert ARIBAUD --- include/lh7a400.h | 75 ------------- include/lh7a404.h | 83 -------------- include/lh7a40x.h | 279 ------------------------------------------------ include/lpd7a400_cpld.h | 195 --------------------------------- 4 files changed, 632 deletions(-) delete mode 100644 include/lh7a400.h delete mode 100644 include/lh7a404.h delete mode 100644 include/lh7a40x.h delete mode 100644 include/lpd7a400_cpld.h (limited to 'include') diff --git a/include/lh7a400.h b/include/lh7a400.h deleted file mode 100644 index d1e70a2..0000000 --- a/include/lh7a400.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * lh7a400 SoC interface - */ - -#ifndef __LH7A400_H__ -#define __LH7A400_H__ - -#include "lh7a40x.h" - -/* Interrupt Controller (userguide 8.2.1) */ -typedef struct { - volatile u32 intsr; - volatile u32 intrsr; - volatile u32 intens; - volatile u32 intenc; - volatile u32 rsvd1; - volatile u32 rsvd2; - volatile u32 rsvd3; -} /*__attribute__((__packed__))*/ lh7a400_interrupt_t; -#define LH7A400_INTERRUPT_BASE (0x80000500) -#define LH7A400_INTERRUPT_PTR ((lh7a400_interrupt_t*) LH7A400_INTERRUPT_BASE) - -/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */ -typedef struct { - lh7a40x_dmachan_t chan[15]; - volatile u32 glblint; - volatile u32 rsvd1; - volatile u32 rsvd2; - volatile u32 rsvd3; -} /*__attribute__((__packed__))*/ lh7a400_dma_t; - -#define LH7A400_DMA_BASE (0x80002800) -#define DMA_USBTX_OFFSET (0x000) -#define DMA_USBRX_OFFSET (0x040) -#define DMA_MMCTX_OFFSET (0x080) -#define DMA_MMCRX_OFFSET (0x0C0) -#define DMA_AC97_BASE (0x80002A00) - -#define LH7A400_DMA_PTR ((lh7a400_dma_t*) LH7A400_DMA_BASE) -#define LH7A400_DMA_USBTX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBTX_OFFSET)) -#define LH7A400_DMA_USBRX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBRX_OFFSET)) -#define LH7A400_DMA_MMCTX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCTX_OFFSET)) -#define LH7A400_DMA_MMCRX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCRX_OFFSET)) -#define LH7A400_AC97RX(n) \ - ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \ - ((2*n) * sizeof(lh7a400_dmachan_t)))) -#define LH7A400_AC97TX(n) \ - ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \ - (((2*n)+1) * sizeof(lh7a400_dmachan_t)))) - -#endif /* __LH7A400_H__ */ diff --git a/include/lh7a404.h b/include/lh7a404.h deleted file mode 100644 index 4098af3..0000000 --- a/include/lh7a404.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * lh7a404 SoC interface - */ - -#ifndef __LH7A404_H__ -#define __LH7A404_H__ - -#include "lh7a40x.h" - -/* Interrupt Controller (userguide 8.2.1) */ -typedef struct { - volatile u32 irqstatus; - volatile u32 fiqstatus; - volatile u32 rawintr; - volatile u32 intsel; - volatile u32 inten; - volatile u32 intenclr; - volatile u32 softint; - volatile u32 softintclr; - volatile u32 protect; - volatile u32 unused1; - volatile u32 unused2; - volatile u32 vectaddr; - volatile u32 nvaddr; - volatile u32 unused3[32]; - volatile u32 vad[16]; - volatile u32 unused4[44]; - volatile u32 vectcntl[16]; - volatile u32 unused5[44]; - volatile u32 itcr; - volatile u32 itip1; - volatile u32 itip2; - volatile u32 itop1; - volatile u32 itop2; - volatile u32 unused6[333]; - volatile u32 periphid[4]; - volatile u32 pcellid[4]; -} /*__attribute__((__packed__))*/ lh7a404_vic_t; -#define LH7A404_VIC_BASE (0x80008000) -#define LH7A400_VIC_PTR(x) ((lh7a404_vic_t*)(LH7A400_VIC_BASE + (x*0x2000))) - - -typedef struct { - lh7a40x_dmachan_t m2p0_tx; - lh7a40x_dmachan_t m2p1_rx; - lh7a40x_dmachan_t m2p2_tx; - lh7a40x_dmachan_t m2p3_rx; - lh7a40x_dmachan_t m2m0; - lh7a40x_dmachan_t m2m1; - lh7a40x_dmachan_t unused1; - lh7a40x_dmachan_t unused2; - lh7a40x_dmachan_t m2p5_rx; - lh7a40x_dmachan_t m2p4_tx; - lh7a40x_dmachan_t m2p7_rx; - lh7a40x_dmachan_t m2p6_tx; - lh7a40x_dmachan_t m2p9_rx; - lh7a40x_dmachan_t m2p8_tx; - volatile u32 chanarb; - volatile u32 glblint; -} /*__attribute__((__packed__))*/ lh7a400_dma_t; - - -#endif /* __LH7A404_H__ */ diff --git a/include/lh7a40x.h b/include/lh7a40x.h deleted file mode 100644 index 09a463c..0000000 --- a/include/lh7a40x.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * lh7a40x SoC series common interface - */ - -#ifndef __LH7A40X_H__ -#define __LH7A40X_H__ - -/* (SMC) Static Memory Controller (usersguide 4.2.1) */ -typedef struct { - volatile u32 attib; - volatile u32 com; - volatile u32 io; - volatile u32 rsvd1; -} /*__attribute__((__packed__))*/ lh7a40x_pccard_t; - -typedef struct { - volatile u32 bcr[8]; - lh7a40x_pccard_t pccard[2]; - volatile u32 pcmciacon; -} /*__attribute__((__packed__))*/ lh7a40x_smc_t; -#define LH7A40X_SMC_BASE (0x80002000) -#define LH7A40X_SMC_PTR ((lh7a40x_smc_t*) LH7A40X_SMC_BASE) - -/* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */ -typedef struct { - volatile u32 rsvd1; - volatile u32 gblcnfg; - volatile u32 rfshtmr; - volatile u32 bootstat; - volatile u32 sdcsc[4]; -} /*__attribute__((__packed__))*/ lh7a40x_sdmc_t; -#define LH7A40X_SDMC_BASE (0x80002400) -#define LH7A40X_SDMC_PTR ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE) - -/* (CSC) Clock and State Controller (userguide 6.2.1) */ -typedef struct { - volatile u32 pwrsr; - volatile u32 pwrcnt; - volatile u32 halt; - volatile u32 stby; - volatile u32 bleoi; - volatile u32 mceoi; - volatile u32 teoi; - volatile u32 stfclr; - volatile u32 clkset; - volatile u32 scrreg[2]; - volatile u32 rsvd1; - volatile u32 usbreset; -} /*__attribute__((__packed__))*/ lh7a40x_csc_t; -#define LH7A40X_STPWR_BASE (0x80000400) -#define LH7A40X_CSC_PTR ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE) - -#define CLKSET_SMCROM (0x01000000) -#define CLKSET_PS (0x000C0000) -#define CLKSET_PS_0 (0x00000000) -#define CLKSET_PS_1 (0x00040000) -#define CLKSET_PS_2 (0x00080000) -#define CLKSET_PS_3 (0x000C0000) -#define CLKSET_PCLKDIV (0x00030000) -#define CLKSET_PCLKDIV_2 (0x00000000) -#define CLKSET_PCLKDIV_4 (0x00010000) -#define CLKSET_PCLKDIV_8 (0x00020000) -#define CLKSET_MAINDIV2 (0x0000f800) -#define CLKSET_MAINDIV1 (0x00000780) -#define CLKSET_PREDIV (0x0000007C) -#define CLKSET_HCLKDIV (0x00000003) - -/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */ -typedef struct { - volatile u32 maxcnt; - volatile u32 base; - volatile u32 current; - volatile u32 rsvd1; -} lh7a40x_dmabuf_t; - -typedef struct { - volatile u32 control; - volatile u32 interrupt; - volatile u32 rsvd1; - volatile u32 status; - volatile u32 rsvd2; - volatile u32 remain; - volatile u32 rsvd3; - volatile u32 rsvd4; - lh7a40x_dmabuf_t buf[2]; -} /*__attribute__((__packed__))*/ lh7a40x_dmachan_t; - - -/* (WDT) Watchdog Timer (userguide 11.2.1) */ -typedef struct { - volatile u32 ctl; - volatile u32 rst; - volatile u32 status; - volatile u32 count[4]; -} /*__attribute__((__packed__))*/ lh7a40x_wdt_t; -#define LH7A40X_WDT_BASE (0x80001400) -#define LH7A40X_WDT_PTR ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE) - -/* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */ -typedef struct { - volatile u32 rtcdr; - volatile u32 rtclr; - volatile u32 rtcmr; - volatile u32 unk1; - volatile u32 rtcstat_eoi; - volatile u32 rtccr; - volatile u32 rsvd1[58]; -} /*__attribute__((__packed__))*/ lh7a40x_rtc_t; -#define LH7A40X_RTC_BASE (0x80000D00) -#define LH7A40X_RTC_PTR ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE) - -/* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */ -typedef struct { - volatile u32 load; - volatile u32 value; - volatile u32 control; - volatile u32 tceoi; -} /*__attribute__((__packed__))*/ lh7a40x_timer_t; - -typedef struct { - lh7a40x_timer_t timer1; - volatile u32 rsvd1[4]; - lh7a40x_timer_t timer2; - volatile u32 unk1[4]; - volatile u32 bzcon; - volatile u32 unk2[15]; - lh7a40x_timer_t timer3; - /*volatile u32 rsvd2;*/ -} /*__attribute__((__packed__))*/ lh7a40x_timers_t; -#define LH7A40X_TIMERS_BASE (0x80000C00) -#define LH7A40X_TIMERS_PTR ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE) - -#define TIMER_EN (0x00000080) -#define TIMER_PER (0x00000040) -#define TIMER_FREE (0x00000000) -#define TIMER_CLK508K (0x00000008) -#define TIMER_CLK2K (0x00000000) - -/* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */ -typedef struct { - volatile u32 cr0; - volatile u32 cr1; - volatile u32 irr_roeoi; - volatile u32 dr; - volatile u32 cpr; - volatile u32 sr; - /*volatile u32 rsvd1[58];*/ -} /*__attribute__((__packed__))*/ lh7a40x_ssp_t; -#define LH7A40X_SSP_BASE (0x80000B00) -#define LH7A40X_SSP_PTR ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE) - -/* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */ -typedef struct { - volatile u32 data; - volatile u32 fcon; - volatile u32 brcon; - volatile u32 con; - volatile u32 status; - volatile u32 rawisr; - volatile u32 inten; - volatile u32 isr; - volatile u32 rsvd1[56]; -} /*__attribute__((__packed__))*/ lh7a40x_uart_t; -#define LH7A40X_UART_BASE (0x80000600) -#define LH7A40X_UART_PTR(n) \ - ((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t)))) - -#define UART_BE (0x00000800) /* the rx error bits */ -#define UART_OE (0x00000400) -#define UART_PE (0x00000200) -#define UART_FE (0x00000100) - -#define UART_WLEN (0x00000060) /* fcon bits */ -#define UART_WLEN_8 (0x00000060) -#define UART_WLEN_7 (0x00000040) -#define UART_WLEN_6 (0x00000020) -#define UART_WLEN_5 (0x00000000) -#define UART_FEN (0x00000010) -#define UART_STP2 (0x00000008) -#define UART_STP2_2 (0x00000008) -#define UART_STP2_1 (0x00000000) -#define UART_EPS (0x00000004) -#define UART_EPS_EVEN (0x00000004) -#define UART_EPS_ODD (0x00000000) -#define UART_PEN (0x00000002) -#define UART_BRK (0x00000001) - -#define UART_BAUDDIV (0x0000ffff) /* brcon bits */ - -#define UART_SIRBD (0x00000080) /* con bits */ -#define UART_LBE (0x00000040) -#define UART_MXP (0x00000020) -#define UART_TXP (0x00000010) -#define UART_RXP (0x00000008) -#define UART_SIRLP (0x00000004) -#define UART_SIRD (0x00000002) -#define UART_EN (0x00000001) - -#define UART_TXFE (0x00000080) /* status bits */ -#define UART_RXFF (0x00000040) -#define UART_TXFF (0x00000020) -#define UART_RXFE (0x00000010) -#define UART_BUSY (0x00000008) -#define UART_DCD (0x00000004) -#define UART_DSR (0x00000002) -#define UART_CTS (0x00000001) - -#define UART_MSEOI (0xfffffff0) /* rawisr interrupt bits */ - -#define UART_RTI (0x00000008) /* generic interrupt bits */ -#define UART_MI (0x00000004) -#define UART_TI (0x00000002) -#define UART_RI (0x00000001) - -/* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */ -typedef struct { - volatile u32 pad; - volatile u32 pbd; - volatile u32 pcd; - volatile u32 pdd; - volatile u32 padd; - volatile u32 pbdd; - volatile u32 pcdd; - volatile u32 pddd; - volatile u32 ped; - volatile u32 pedd; - volatile u32 kbdctl; - volatile u32 pinmux; - volatile u32 pfd; - volatile u32 pfdd; - volatile u32 pgd; - volatile u32 pgdd; - volatile u32 phd; - volatile u32 phdd; - volatile u32 rsvd1; - volatile u32 inttype1; - volatile u32 inttype2; - volatile u32 gpiofeoi; - volatile u32 gpiointen; - volatile u32 intstatus; - volatile u32 rawintstatus; - volatile u32 gpiodb; - volatile u32 papd; - volatile u32 pbpd; - volatile u32 pcpd; - volatile u32 pdpd; - volatile u32 pepd; - volatile u32 pfpd; - volatile u32 pgpd; - volatile u32 phpd; -} /*__attribute__((__packed__))*/ lh7a40x_gpioint_t; -#define LH7A40X_GPIOINT_BASE (0x80000E00) -#define LH7A40X_GPIOINT_PTR ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE) - -/* Embedded SRAM */ -#define CONFIG_SYS_SRAM_BASE (0xB0000000) -#define CONFIG_SYS_SRAM_SIZE (80*1024) /* 80kB */ - -#endif /* __LH7A40X_H__ */ diff --git a/include/lpd7a400_cpld.h b/include/lpd7a400_cpld.h deleted file mode 100644 index c70af09..0000000 --- a/include/lpd7a400_cpld.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Logic lh7a400-10 Card Engine CPLD interface - */ - -#ifndef __LPD7A400_CPLD_H_ -#define __LPD7A400_CPLD_H_ - - -/* - * IO Controller Address and Register Definitions - * - using LH7A400-10 Card Engine IO Controller Specification - * (logic PN: 70000079) - */ - -/*------------------------------------------------------------------ - * Slow Peripherals (nCS6) - */ -#define LPD7A400_CPLD_CF (0x60200000) -#define LPD7A400_CPLD_ISA (0x60400000) - -/*------------------------------------------------------------------ - * Fast Peripherals (nCS7) - * - * The CPLD directs access to 0x70000000-0x701fffff to the onboard - * ethernet controller - */ -#define LPD7A400_CPLD_WLAN_BASE (0x70000000) - -/* All registers are 8 bit */ -#define LPD7A400_CPLD_CECTL_REG (0x70200000) -#define LPD7A400_CPLD_SPIDATA_REG (0x70600000) -#define LPD7A400_CPLD_SPICTL_REG (0x70800000) -#define LPD7A400_CPLD_EEPSPI_REG (0x70a00000) -#define LPD7A400_CPLD_INTMASK_REG (0x70c00000) -#define LPD7A400_CPLD_MODE_REG (0x70e00000) -#define LPD7A400_CPLD_FLASH_REG (0x71000000) -#define LPD7A400_CPLD_PWRMG_REG (0x71200000) -#define LPD7A400_CPLD_REV_REG (0x71400000) -#define LPD7A400_CPLD_EXTGPIO_REG (0x71600000) -#define LPD7A400_CPLD_GPIODATA_REG (0x71800000) -#define LPD7A400_CPLD_GPIODIR_REG (0x71a00000) - -#define LPD7A400_CPLD_REGPTR (volatile u8*) - -/* Card Engine Control Register (section 3.1.2) */ -#define CECTL_SWINT (0x80) /* Software settable interrupt source - (routed to uP PF3) - 0 = generate interrupt, 1 = do not */ -#define CECTL_OCMSK (0x40) /* USB1 connection interrupt mask - 0 = not masked, 1 = masked */ -#define CECTL_PDRV (0x20) /* PCC_nDRV output - 0 = active, 1 = inactive */ -#define CECTL_USB1C (0x10) /* USB1 connection interrupt - 0 = active, 1 = inactive */ -#define CECTL_USB1P (0x08) /* USB1 Power enable - 0 = enabled, 1 = disabled */ -#define CECTL_AWKP (0x04) /* Auto-Wakeup enable - 0 = enabled, 1 = disabled */ -#define CECTL_LCDV (0x02) /* LCD VEE enable - 0 = disabled, 1 = enabled */ -#define CECTL_WLPE (0x01) /* Wired LAN power enable - 0 = enabled, 1 = disabled */ - -/* SPI Control Register (section 3.1.5) */ -#define SPICTL_SPLD (0x20) /* SPI load (R) - 0 = data reg. has not been loaded, shift - count has not been reset - 1 = data reg. loaded, shift count reset */ -#define SPICTL_SPST (0x10) /* SPI start (RW) - 0 = don't load data reg. and reset shift count - 1 = ready to load data reg and reset shift count */ -#define SPICTL_SPDN (0x08) /* SPI done (R) - 0 = not done - 1 = access done */ -#define SPICTL_SPRW (0x04) /* SPI read/write (RW) - 0 = SPI write access - 1 = SPI read access */ -#define SPICTL_STCS (0x02) /* SPI touch chip select (RW) - 0 = not selected - 1 = selected */ -#define SPICTL_SCCS (0x01) /* SPI CODEC chip select (RW) {not used} - 0 = not selected - 1 = selected */ - -/* EEPROM SPI Interface Register (section 3.1.6) */ -#define EEPSPI_EECS (0x08) /* EEPROM chip select (RW) - 0 = not selected - 1 = selected */ -#define EEPSPI_EECK (0x04) /* EEPROM SPI clock (RW) */ -#define EEPSPI_EETX (0x02) /* EEPROM SPI tx data (RW) */ -#define EEPSPI_EERX (0x01) /* EEPROM SPI rx data (R) */ - -/* Interrupt/Mask Register (section 3.1.7) */ -#define INTMASK_CMSK (0x80) /* CPLD_nIRQD interrupt mask (RW) - 0 = not masked - 1 = masked */ -#define INTMASK_CIRQ (0x40) /* interrupt signal to CPLD (R) - 0 = interrupt active - 1 = no interrupt */ -#define INTMASK_PIRQ (0x10) /* legacy, no effect */ -#define INTMASK_TMSK (0x08) /* Touch chip interrupt mask (RW) - 0 = not masked - 1 = masked */ -#define INTMASK_WMSK (0x04) /* Wired LAN interrupt mask (RW) - 0 = not masked - 1 = masked */ -#define INTMASK_TIRQ (0x02) /* Touch chip interrupt request (R) - 0 = interrupt active - 1 = no interrupt */ -#define INTMASK_WIRQ (0x01) /* Wired LAN interrupt request (R) - 0 = interrupt active - 1 = no interrupt */ - -/* Mode Register (section 3.1.8) */ -#define MODE_VS1 (0x80) /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R) - 0 = active slot VS1 pin is low - 1 = active slot VS1 pin is high */ -#define MODE_CD2 (0x40) /* PCMCIA Card Detect 2 input (PCC_nCD2) (R) - 0 = active slot CD2 is low - 1 = active slot CD2 is high */ -#define MODE_IOIS16 (0x20) /* PCMCIA IOIS16 input (PCC_nIOIS16) (R) - 0 = 16 bit access area - 1 = 8 bit access area */ -#define MODE_CD1 (0x10) /* PCMCIA Card Detect 1 input (PCC_nCD1) (R) - 0 = active slot CD1 is low - 1 = active slot CD1 is high */ -#define MODE_upMODE3 (0x08) /* Mode Pin 3 (R) - 0 = off-board boot device - 1 = on-board boot device (flash) */ -#define MODE_upMODE2 (0x04) /* Mode Pin 2 (R) (LH7A400 Little Endian only) - 0 = big endian - 1 = little endian */ -#define MODE_upMODE1 (0x02) /* Mode Pin 1 and Mode Pin 2 (R) */ -#define MODE_upMODE0 (0x01) /* - bus width at boot */ - - -/* Flash Register (section 3.1.9) */ -#define FLASH_FPOP (0x08) /* Flash populated (RW) - 0 = populated, 1 = not */ -#define FLASH_FST2 (0x04) /* Flash status (R) (RY/BY# pin for upper 16 bit chip - 0 = busy, 1 = ready */ -#define FLASH_FST1 (0x02) /* Flash status (R) (RY/BY# pin for lower 16 bit chip - 0 = busy, 1 = ready */ -#define FLASH_FPEN (0x01) /* Flash program enable (RW) - 0 = flash write protected - 1 = programming enabled */ - -/* Power Management Register (section 3.1.10) - * - when either of these is low an unmaskable interrupt to cpu - * is generated - */ -#define PWRMG_STBY (0x10) /* state of nSTANDBY signal to CPLD (R) - 0 = low, 1 = high */ -#define PWRMG_SPND (0x04) /* state of nSUSPEND signal to CPLD (R) - 0 = low, 1 = high */ - - -/* Extended GPIO Register (section 3.1.12) */ -#define EXTGPIO_STATUS1 (0x04) /* Status 1 output (RW) (uP_STATUS_1) - 0 = set pin low, 1 = set pin high */ -#define EXTGPIO_STATUS2 (0x02) /* Status 2 output (RW) (uP_STATUS_2) - 0 = set pin low, 1 = set pin high */ -#define EXTGPIO_GPIO1 (0x01) /* General purpose output (RW) (CPLD_GPIO_1) - 0 = set pin low, 1 = set pin high */ - -/* GPIO Data Register (section 3.1.13) */ -#define GPIODATA_GPIO2 (0x01) /* General purpose input/output (RW) (CPLD_GPIO_2) - 0 = set low (output) / read low (input) - 1 = set high (output) / read high (input) */ - -/* GPIO Direction Register (section 3.1.14) */ -#define GPIODIR_GPDR0 (0x01) /* GPIO2 direction (RW) - 0 = output, 1 = input */ - -#endif /* __LH7A400_H__ */ -- cgit v1.1 From 1db7377a70a8d931c32648e717695133120d5456 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Thu, 13 Sep 2012 22:22:04 +0000 Subject: mmc: at91: add multi block read/write support. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the at91sam9263, the mmc hardware support multi blocks read/write. So this driver enable it. Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- include/atmel_mci.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/atmel_mci.h b/include/atmel_mci.h index 3dd5d67..c711881 100644 --- a/include/atmel_mci.h +++ b/include/atmel_mci.h @@ -38,7 +38,7 @@ typedef struct atmel_mci { u32 sdcr; /* 0x0c */ u32 argr; /* 0x10 */ u32 cmdr; /* 0x14 */ - u32 _18; /* 0x18 */ + u32 blkr; /* 0x18 */ u32 _1c; /* 0x1c */ u32 rspr; /* 0x20 */ u32 rspr1; /* 0x24 */ @@ -118,6 +118,11 @@ typedef struct atmel_mci { #define MMCI_TRTYP_OFFSET 19 #define MMCI_TRTYP_SIZE 2 +/* Bitfields in BLKR */ +/* MMCI_BLKLEN_OFFSET/SIZE already defined in MR */ +#define MMCI_BCNT_OFFSET 0 +#define MMCI_BCNT_SIZE 16 + /* Bitfields in RSPRx */ #define MMCI_RSP_OFFSET 0 #define MMCI_RSP_SIZE 32 -- cgit v1.1 From 3a49cd7e1a26af6708b05d4877bb0254a08dded3 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Thu, 13 Sep 2012 22:22:05 +0000 Subject: ARM: at91sam9x5: enable MCI0 support for 9x5ek board. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- include/configs/at91sam9x5ek.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index cbdc3e9..71f765b 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -89,6 +89,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NAND #define CONFIG_CMD_SF +#define CONFIG_CMD_MMC /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 @@ -138,6 +139,15 @@ #define CONFIG_CMD_UBIFS #endif +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_CMD_FAT +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define CONFIG_DOS_PARTITION +#endif + /* Ethernet */ #define CONFIG_MACB #define CONFIG_RMII -- cgit v1.1 From bfa5b71408da629493838668e4df0ca9d12107bb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 19 Sep 2012 03:18:53 +0000 Subject: mpc82xx: Remove BMW board port As the board seems to be unmaintained for some time, lets remove the support in mainline completely. Signed-off-by: Stefan Roese Cc: Marek Vasut Cc: James F. Dougherty Cc: Wolfgang Denk Acked-by: Marek Vasut --- include/configs/BMW.h | 302 -------------------------------------------------- 1 file changed, 302 deletions(-) delete mode 100644 include/configs/BMW.h (limited to 'include') diff --git a/include/configs/BMW.h b/include/configs/BMW.h deleted file mode 100644 index 633e9bd..0000000 --- a/include/configs/BMW.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the CU824 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_BMW 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */ -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */ -#define DOC_PASSIVE_PROBE 1 -#define CONFIG_SYS_DOC_SUPPORT_2000 1 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1 -#define CONFIG_SYS_DOC_SHORT_TIMEOUT 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - - -#if 0 -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */ -#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM } - -/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the - * reset vector is actually located at FFB00100, but the 8245 - * takes care of us. - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */ - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_ETH_DEV_FN 0x7800 -#define CONFIG_SYS_ETH_IOBASE 0x00104000 - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 0xf -#define CONFIG_SYS_ROMFAL 0x1f -#define CONFIG_SYS_DBUS_SIZE 0x3 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 0 /* FIXME: was 192 */ - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 3 /* SDMODE Burst length */ -#define CONFIG_SYS_ACTORW 0xa /* FIXME was 2 */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 - -#define CONFIG_SYS_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ - -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_PCI 1 /* Include PCI support */ -#undef CONFIG_PCI_PNP - -/* PCI Memory space(s) */ -#define PCI_MEM_SPACE1_START 0x80000000 -#define PCI_MEM_SPACE2_START 0xfd000000 - -/* ROM Spaces */ -#include "../board/bmw/bmw.h" - -/* BAT configuration */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1 -#define CONFIG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */ -#define CONFIG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */ -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ -- cgit v1.1 From bfb7d7a3d61ff23f9dd265a56e8b5cac5bbfd76e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 6 Oct 2012 14:07:01 +0000 Subject: serial: Implement default_serial_puts() U-Boot contains a lot of duplicit implementations of serial_puts() call which just pipes single characters into the port in loop. Implement function that does this behavior into common code, so others can make easy use of it. This function is called default_serial_puts() and it's sole purpose is to call putc() in loop on the whole string passed to it. Signed-off-by: Marek Vasut Cc: Marek Vasut Cc: Tom Rini --- include/serial.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/serial.h b/include/serial.h index a8d23f5..14f863e 100644 --- a/include/serial.h +++ b/include/serial.h @@ -20,6 +20,8 @@ struct serial_device { struct serial_device *next; }; +void default_serial_puts(const char *s); + extern struct serial_device serial_smc_device; extern struct serial_device serial_scc_device; extern struct serial_device *default_serial_console(void); -- cgit v1.1 From 8d1165e11a7aad00a2bbb05f20bacf021f6d1c12 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Tue, 9 Oct 2012 07:01:56 +0000 Subject: split mpc8xx hooks from cmd_ide.c move most of mpc8xx hooks from cmd_ide.c into ide_preinit() and newly created ide_init_postreset() (invoked after calling ide_reset after ide_preinit), some cleanup to make checkpatch happy, enable IDE init hooks in configs of affected boards. confusingly, these hooks are used by more than just mpc8xx-based boards, and therefore are placed in arch/ppc/lib/ note: checkpatch still emits warnings about using volatile Signed-off-by: Pavel Herrmann --- include/configs/CPC45.h | 1 + include/configs/ICU862.h | 1 + include/configs/IVML24.h | 2 ++ include/configs/IVMS8.h | 2 ++ include/configs/KUP4K.h | 1 + include/configs/KUP4X.h | 1 + include/configs/MBX.h | 1 + include/configs/NETTA.h | 1 + include/configs/NSCU.h | 1 + include/configs/R360MPI.h | 1 + include/configs/RPXClassic.h | 1 + include/configs/RPXlite.h | 1 + include/configs/RPXlite_DW.h | 1 + include/configs/RRvision.h | 1 + include/configs/SPD823TS.h | 2 ++ include/configs/TK885D.h | 1 + include/configs/TQM823L.h | 1 + include/configs/TQM823M.h | 1 + include/configs/TQM850L.h | 1 + include/configs/TQM850M.h | 1 + include/configs/TQM855L.h | 1 + include/configs/TQM855M.h | 1 + include/configs/TQM860L.h | 1 + include/configs/TQM860M.h | 1 + include/configs/TQM862L.h | 1 + include/configs/TQM862M.h | 1 + include/configs/TQM866M.h | 1 + include/configs/TQM885D.h | 1 + include/configs/atc.h | 1 + include/configs/c2mon.h | 1 + include/configs/lwmon.h | 1 + include/configs/quantum.h | 1 + include/configs/svm_sc8xx.h | 2 ++ include/configs/uc100.h | 1 + include/configs/virtlab2.h | 1 + include/ide.h | 8 ++++++++ 36 files changed, 47 insertions(+) (limited to 'include') diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index fc226f1..e102c36 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -480,6 +480,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index 81f219c..b58b6f6 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -349,6 +349,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h index f98a66b..092fcf0 100644 --- a/include/configs/IVML24.h +++ b/include/configs/IVML24.h @@ -318,6 +318,8 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ +#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h index d6e9b23..38837ca 100644 --- a/include/configs/IVMS8.h +++ b/include/configs/IVMS8.h @@ -312,6 +312,8 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ +#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index c0035e6..dae9b8c 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -353,6 +353,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h index 5084ccc..cceee96 100644 --- a/include/configs/KUP4X.h +++ b/include/configs/KUP4X.h @@ -366,6 +366,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/MBX.h b/include/configs/MBX.h index e8d0cd7..7145cc4 100644 --- a/include/configs/MBX.h +++ b/include/configs/MBX.h @@ -276,6 +276,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 604938d..074e01f 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -629,6 +629,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index 9f462f4..f4184fc 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -318,6 +318,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index 9befacb..868a0b8 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -329,6 +329,7 @@ */ #if 1 +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h index b215c2d..3595200 100644 --- a/include/configs/RPXClassic.h +++ b/include/configs/RPXClassic.h @@ -314,6 +314,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index 8ffb014..563abea 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -249,6 +249,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index f8bcf0f..67ab1e9 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -335,6 +335,7 @@ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index 671d521..e2b22f0 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -329,6 +329,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index cffeb11..72ea217 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -303,6 +303,8 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ +#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ #define CONFIG_IDE_LED 1 /* LED for ide supported */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h index 4176c7f..623cb66 100644 --- a/include/configs/TK885D.h +++ b/include/configs/TK885D.h @@ -343,6 +343,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index a01b4a6..9fac5d1 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -335,6 +335,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 1da4acd..932f158 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -331,6 +331,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 1c054f0..eb08de2 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -320,6 +320,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index 46066df..bf3a76c 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -322,6 +322,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index dd2da94..43dd643 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -324,6 +324,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 95bc4d9..e7fd2db 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -359,6 +359,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 487666c..81e1b91 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -323,6 +323,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index e8b77ea..ed496a1 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -324,6 +324,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 334b7ec..1559336 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -327,6 +327,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 1e2ad40..61dcf62 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -328,6 +328,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index a13c16a..7d0ae99 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -356,6 +356,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index 7df76fb..7941631 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -341,6 +341,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/atc.h b/include/configs/atc.h index 75f950b9..538a167 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -482,6 +482,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h index 566c42b..41ff008 100644 --- a/include/configs/c2mon.h +++ b/include/configs/c2mon.h @@ -302,6 +302,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index ab86053..df49781 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -494,6 +494,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/quantum.h b/include/configs/quantum.h index 4f24651..072bd9c 100644 --- a/include/configs/quantum.h +++ b/include/configs/quantum.h @@ -317,6 +317,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 91686d6..2b24997 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -359,6 +359,8 @@ #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ +#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ #define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ diff --git a/include/configs/uc100.h b/include/configs/uc100.h index 8c8fb5a..450c98b 100644 --- a/include/configs/uc100.h +++ b/include/configs/uc100.h @@ -331,6 +331,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index 4bb96cc..c2c0d1d 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -329,6 +329,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/ide.h b/include/ide.h index 95dcbdd..3a08425 100644 --- a/include/ide.h +++ b/include/ide.h @@ -54,6 +54,14 @@ void ide_init(void); ulong ide_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer); ulong ide_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer); +#ifdef CONFIG_IDE_PREINIT +int ide_preinit(void); +#endif + +#ifdef CONFIG_IDE_INIT_POSTRESET +int ide_init_postreset(void); +#endif + #if defined(CONFIG_OF_IDE_FIXUP) int ide_device_present(int dev); #endif -- cgit v1.1 From f5b82c0f9c34ded68e346a0fe7ad13c3ff63f573 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Tue, 9 Oct 2012 07:04:39 +0000 Subject: change all versions of input_data() and output_data() to global weak aliases This changes input_data() and friends from static function to global symbols under weak alias, to enable board specific overrides (and therefore get rid of board-specific code in cmd_ide.c) Also declare ide_bus_offset in the header file, so other files can use ATA_CURR_BASE as well. Signed-off-by: Pavel Herrmann --- include/ide.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/ide.h b/include/ide.h index 3a08425..695d08e 100644 --- a/include/ide.h +++ b/include/ide.h @@ -27,6 +27,7 @@ #define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS)) #define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) +extern ulong ide_bus_offset[]; #ifdef CONFIG_IDE_LED @@ -72,4 +73,14 @@ void ide_write_register(int dev, unsigned int port, unsigned char val); void ide_read_data(int dev, ulong *sect_buf, int words); void ide_write_data(int dev, ulong *sect_buf, int words); #endif + +/* + * I/O function overrides + */ +void ide_input_swap_data(int dev, ulong *sect_buf, int words); +void ide_input_data(int dev, ulong *sect_buf, int words); +void ide_output_data(int dev, const ulong *sect_buf, int words); +void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts); +void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts); + #endif /* _IDE_H */ -- cgit v1.1 From 12c79a957804c13c2ba8e6606990fd6bd1f55e9a Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Wed, 26 Sep 2012 11:43:54 +0000 Subject: powerpc: delete Wind River SBC8560/8540 support The sbc8548/60 (both similar, just variations in UART hardware) support has been removed from the linux kernel as of v3.6-rc1~132 so lets also now remove it from the u-boot tree as well. Signed-off-by: Paul Gortmaker --- include/configs/SBC8540.h | 428 ------------------------------------------ include/configs/sbc8560.h | 459 ---------------------------------------------- 2 files changed, 887 deletions(-) delete mode 100644 include/configs/SBC8540.h delete mode 100644 include/configs/sbc8560.h (limited to 'include') diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h deleted file mode 100644 index d448bf6..0000000 --- a/include/configs/SBC8540.h +++ /dev/null @@ -1,428 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * (C) Copyright 2004 Wind River Systems Inc . - * Added support for Wind River SBC8540 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * sbc8540 board configuration file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Top level Makefile configuration choices - */ -#ifdef CONFIG_66 -#define CONFIG_PCI_66 -#endif - -#define TSEC_DEBUG - -/* - * High Level Configuration Options - */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - -#define CONFIG_SYS_TEXT_BASE 0xfffc0000 - - -#define CONFIG_CPM2 1 /* has CPM2 */ - -#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ -#define CONFIG_MPC8540 1 - -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ - -/* DDR Setup */ -#define CONFIG_FSL_DDR1 -#undef CONFIG_FSL_DDR_INTERACTIVE -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_SPD - -#if defined(CONFIG_MPC85xx_REV1) -#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ -#endif - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */ - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7 - -#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CONFIG_SYS_OR2_PRELIM 0x00000000 - -#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1 - -#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ -#if 1 - #define CONFIG_SYS_OR5_PRELIM 0xff000ff7 -#else - #define CONFIG_SYS_OR5_PRELIM 0xff0000f0 -#endif - -#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7 -#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LSRT 0x20000000 -#define CONFIG_SYS_LBC_MRTPR 0x20000000 -#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 -#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 -#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#if 0 -#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */ -#else -#define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */ -#endif - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#if 0 -#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000) -#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000) -#else -/* SBC8540 uses internal COMM controller */ -#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500) -#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600) -#endif - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 - -#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 - -#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - -# define CONFIG_MPC85xx_TSEC1 -# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" -# define CONFIG_MII 1 /* MII PHY management */ -# define TSEC1_PHY_ADDR 25 -# define TSEC1_PHYIDX 0 -/* Options are: TSEC0 */ -# define CONFIG_ETHPRIME "TSEC0" - - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) - #define MDC_DECLARE MDIO_DECLARE - - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if 0 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ -#endif -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if 0 -/* XXX This doesn't work and I don't want to fix it */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) - #define CONFIG_SYS_RAMBOOT -#else - #undef CONFIG_SYS_RAMBOOT -#endif -#endif - -/* Environment */ -#if !defined(CONFIG_SYS_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_ENV_IS_NOWHERE - #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000) - #define CONFIG_ENV_SIZE 0x2000 - #else - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */ - #endif -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*Note: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a -# define CONFIG_HAS_ETH1 -# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b -# define CONFIG_HAS_ETH2 -# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c -#endif - -#define CONFIG_SERVERIP YourServerIP -#define CONFIG_IPADDR YourTargetIP -#define CONFIG_GATEWAYIP YourGatewayIP -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH "YourRootPath" -#define CONFIG_BOOTFILE "YourImageName" - -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h deleted file mode 100644 index 46d6098..0000000 --- a/include/configs/sbc8560.h +++ /dev/null @@ -1,459 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * (C) Copyright 2004 Wind River Systems Inc . - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * sbc8560 board configuration file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Top level Makefile configuration choices - */ -#ifdef CONFIG_66 -#define CONFIG_PCI_66 -#endif - -/* - * High Level Configuration Options - */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - -#define CONFIG_SYS_TEXT_BASE 0xfffc0000 - - -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ -#define CONFIG_MPC8560 1 - -/* XXX flagging this as something I might want to delete */ -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ - -/* DDR Setup */ -#define CONFIG_FSL_DDR1 -#undef CONFIG_FSL_DDR_INTERACTIVE -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_SPD - -#if defined(CONFIG_MPC85xx_REV1) -#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ -#endif - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */ - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7 - -#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CONFIG_SYS_OR2_PRELIM 0x00000000 - -#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1 - -#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ -#if 1 - #define CONFIG_SYS_OR5_PRELIM 0xff000ff7 -#else - #define CONFIG_SYS_OR5_PRELIM 0xff0000f0 -#endif - -#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7 -#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LSRT 0x20000000 -#define CONFIG_SYS_LBC_MRTPR 0x20000000 -#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 -#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 -#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */ -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000) -#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 - -#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 - -#ifdef CONFIG_TSEC_ENET - -#ifndef CONFIG_MII -#define CONFIG_MII 1 /* MII PHY management */ -#endif -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0x19 -#define TSEC2_PHY_ADDR 0x1a -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) - #define MDC_DECLARE MDIO_DECLARE - - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if 0 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ -#endif -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if 0 -/* XXX This doesn't work and I don't want to fix it */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) - #define CONFIG_SYS_RAMBOOT -#else - #undef CONFIG_SYS_RAMBOOT -#endif -#endif - -/* Environment */ -#if !defined(CONFIG_SYS_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_ENV_IS_NOWHERE - #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000) - #define CONFIG_ENV_SIZE 0x2000 - #else - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */ - #endif -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SBC8560=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -/* You can compile in a MAC address and your custom net settings by using - * the following syntax. Your board should be marked with the assigned - * MAC addresses directly on it. - * - * #define CONFIG_ETHADDR de:ad:be:ef:00:00 - * #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s! - * #define CONFIG_SERVERIP - * #define CONFIG_IPADDR - * #define CONFIG_GATEWAYIP - * #define CONFIG_NETMASK - */ - -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH "/home/ppc" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=sbc8560.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ -- cgit v1.1 From d731282e7c210bb002cc0a2f3859be4efd3120c7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Jul 2012 05:02:21 +0000 Subject: dm: wdt: arm: Move tnetv107x into drivers/watchdog/ Signed-off-by: Marek Vasut Cc: Oliver Brown Cc: Wolfgang Denk Cc: Albert Aribaud Cc: U-Boot DM --- include/configs/tnetv107x_evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h index 23cab88..d6371fc 100644 --- a/include/configs/tnetv107x_evm.h +++ b/include/configs/tnetv107x_evm.h @@ -32,6 +32,7 @@ #define CONFIG_ARM1176 #define CONFIG_TNETV107X #define CONFIG_TNETV107X_EVM +#define CONFIG_TNETV107X_WATCHDOG #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_DISABLE_TCM -- cgit v1.1 From fb24ffc086043530e1026cc9990955095125ea48 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Jul 2012 05:02:22 +0000 Subject: dm: Move s3c24xx USB driver to a proper place MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marek Vasut Cc: David Müller Cc: Minkyu Kang Cc: Wolfgang Denk Cc: Albert Aribaud Cc: U-Boot DM --- include/configs/VCMA9.h | 1 + include/configs/smdk2410.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 06adc94..fb7d922 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -124,6 +124,7 @@ /* USB support (currently only works with D-cache off) */ #define CONFIG_USB_OHCI +#define CONFIG_USB_OHCI_S3C24XX #define CONFIG_USB_KEYBOARD #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index 1c0978d..a8a56fd 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -66,6 +66,7 @@ * USB support (currently only works with D-cache off) ************************************************************/ #define CONFIG_USB_OHCI +#define CONFIG_USB_OHCI_S3C24XX #define CONFIG_USB_KEYBOARD #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION -- cgit v1.1 From de1f9ac854471ca84c7aa6d236badd3d18ca10f8 Mon Sep 17 00:00:00 2001 From: "402jagan@gmail.com" <402jagan@gmail.com> Date: Sun, 29 Jul 2012 04:26:08 +0000 Subject: versatile: board configs: Use buffered writes on flash This patch provides a support to use buffered writes on flash for versatile and vexpress boards. This will certainly increase the flash writes. Signed-off-by: Jagannadha Sutradharudu Teki <402jagan@gmail.com> --- include/configs/ca9x4_ct_vxp.h | 2 ++ include/configs/versatile.h | 1 + 2 files changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h index 312fd94..a7cd1d4 100644 --- a/include/configs/ca9x4_ct_vxp.h +++ b/include/configs/ca9x4_ct_vxp.h @@ -163,6 +163,8 @@ /* Room required on the stack for the environment data */ #define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ + /* * Amount of flash used for environment: * We don't know which end has the small erase blocks so we use the penultimate diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 38f5302..a65c676 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -230,6 +230,7 @@ #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ #endif #endif /* __CONFIG_H */ -- cgit v1.1 From ddd8418f7f390a39d460e6ab98e8e668f0cf617c Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 12 Oct 2012 08:48:51 +0000 Subject: env: cosmetic: Consilidate the default env definition There used to be a huge structure duplicated 3 times in the source. Signed-off-by: Joe Hershberger Signed-off-by: Tom Rini --- include/env_default.h | 135 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 include/env_default.h (limited to 'include') diff --git a/include/env_default.h b/include/env_default.h new file mode 100644 index 0000000..375e5ca --- /dev/null +++ b/include/env_default.h @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED +env_t environment __PPCENV__ = { + ENV_CRC, /* CRC Sum */ +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT + 1, /* Flags: valid */ +#endif + { +#elif defined(DEFAULT_ENV_INSTANCE_STATIC) +static char default_environment[] = { +#else +const uchar default_environment[] = { +#endif +#ifdef CONFIG_BOOTARGS + "bootargs=" CONFIG_BOOTARGS "\0" +#endif +#ifdef CONFIG_BOOTCOMMAND + "bootcmd=" CONFIG_BOOTCOMMAND "\0" +#endif +#ifdef CONFIG_RAMBOOTCOMMAND + "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" +#endif +#ifdef CONFIG_NFSBOOTCOMMAND + "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0" +#endif +#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) + "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" +#endif +#ifdef CONFIG_LOADS_ECHO + "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0" +#endif +#ifdef CONFIG_ETHADDR + "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" +#endif +#ifdef CONFIG_ETH1ADDR + "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" +#endif +#ifdef CONFIG_ETH2ADDR + "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" +#endif +#ifdef CONFIG_ETH3ADDR + "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0" +#endif +#ifdef CONFIG_ETH4ADDR + "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0" +#endif +#ifdef CONFIG_ETH5ADDR + "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0" +#endif +#ifdef CONFIG_ETHPRIME + "ethprime=" CONFIG_ETHPRIME "\0" +#endif +#ifdef CONFIG_IPADDR + "ipaddr=" __stringify(CONFIG_IPADDR) "\0" +#endif +#ifdef CONFIG_SERVERIP + "serverip=" __stringify(CONFIG_SERVERIP) "\0" +#endif +#ifdef CONFIG_SYS_AUTOLOAD + "autoload=" CONFIG_SYS_AUTOLOAD "\0" +#endif +#ifdef CONFIG_PREBOOT + "preboot=" CONFIG_PREBOOT "\0" +#endif +#ifdef CONFIG_ROOTPATH + "rootpath=" CONFIG_ROOTPATH "\0" +#endif +#ifdef CONFIG_GATEWAYIP + "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0" +#endif +#ifdef CONFIG_NETMASK + "netmask=" __stringify(CONFIG_NETMASK) "\0" +#endif +#ifdef CONFIG_HOSTNAME + "hostname=" __stringify(CONFIG_HOSTNAME) "\0" +#endif +#ifdef CONFIG_BOOTFILE + "bootfile=" CONFIG_BOOTFILE "\0" +#endif +#ifdef CONFIG_LOADADDR + "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" +#endif +#ifdef CONFIG_CLOCKS_IN_MHZ + "clocks_in_mhz=1\0" +#endif +#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) + "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" +#endif +#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG + "arch=" CONFIG_SYS_ARCH "\0" + "cpu=" CONFIG_SYS_CPU "\0" + "board=" CONFIG_SYS_BOARD "\0" +#ifdef CONFIG_SYS_VENDOR + "vendor=" CONFIG_SYS_VENDOR "\0" +#endif +#ifdef CONFIG_SYS_SOC + "soc=" CONFIG_SYS_SOC "\0" +#endif +#endif +#ifdef CONFIG_EXTRA_ENV_SETTINGS + CONFIG_EXTRA_ENV_SETTINGS +#endif + "\0" +#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED + } +#endif +}; -- cgit v1.1 From ef94f7fa64190876c08b68eb1b067c5e6d3085f5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2012 14:02:01 +0000 Subject: input: Use finer grain udelays while waitng for the i8042 keyboard buffer to empty On x86, the i8042 keyboard controller driver frequently waits for the keyboard input buffer to be empty to make sure the controller has had a chance to process the data it was given. The way the delay loop was structured, if the controller hadn't cleared the corresponding status bit immediately, it would wait 1ms before checking again. If the keyboard responded quickly but not instantly, the driver would still wait a full 1ms when perhaps 1us would have been sufficient. Because udelay is a busy wait anyway, this change decreases the delay between checks to 1us. Also, this change gets rid of a hardcoded 250ms delay. On Stumpy, this saves 100-150ms during boot. Signed-off-by: Gabe Black Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- include/i8042.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/i8042.h b/include/i8042.h index 1395289..aeb3f09 100644 --- a/include/i8042.h +++ b/include/i8042.h @@ -39,6 +39,12 @@ #define I8042_STATUS_REG (CONFIG_SYS_ISA_IO + 0x0064) /* keyboard status read */ #define I8042_COMMAND_REG (CONFIG_SYS_ISA_IO + 0x0064) /* keyboard ctrl write */ +enum { + /* Output register (I8042_DATA_REG) has data for system */ + I8042_STATUS_OUT_DATA = 1 << 0, + I8042_STATUS_IN_DATA = 1 << 1, +}; + #define KBD_US 0 /* default US layout */ #define KBD_GER 1 /* german layout */ -- cgit v1.1 From 45fe668f5f6065f37836d5e941f36418fa3676cd Mon Sep 17 00:00:00 2001 From: Louis Yung-Chieh Lo Date: Thu, 11 Oct 2012 15:15:51 +0000 Subject: input: i8042: Provide feature to disable keyboard before booting kernel The BIOS leaves the keyboard enabled during boot time so that any keystroke would interfere kernel driver initialization. Add a way to disable the keyboard to make sure no scancode will be generated during the boot time. Note that the keyboard will be re-enabled again after the kernel driver is up. This code can be called from the board functions. Signed-off-by: Louis Yung-Chieh Lo Signed-off-by: Louis Yung-Chieh Lo Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- include/i8042.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/i8042.h b/include/i8042.h index aeb3f09..c48c057 100644 --- a/include/i8042.h +++ b/include/i8042.h @@ -75,6 +75,19 @@ enum { /* exports */ +/** + * Flush all buffer from keyboard controller to host. + */ +void i8042_flush(void); + +/** + * Disables the keyboard so that key strokes no longer generate scancodes to + * the host. + * + * @return 0 if ok, -1 if keyboard input was found while disabling + */ +int i8042_disable(void); + int i8042_kbd_init(void); int i8042_tstc(void); int i8042_getc(void); -- cgit v1.1 From 44abe47debc783396ec48d929844dcf1106b72f3 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Thu, 11 Oct 2012 15:15:53 +0000 Subject: input: Add ANSI 3.64 escape sequence generation. To support Non-ASCII keys (ex, Fn, PgUp/Dn, arrow keys, ...), we need to translate key code into escape sequence. (Updated by sjg@chromium.org to move away from a function to store keycodes, so we can easily record how many were sent. We now need to return this from input_send_keycodes() so we know whether keys were generated.) Signed-off-by: Hung-Te Lin Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- include/input.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/input.h b/include/input.h index 0f4acb2..e90bb0b 100644 --- a/include/input.h +++ b/include/input.h @@ -84,6 +84,8 @@ struct stdio_dev; * @param config Input state * @param keycode List of key codes to examine * @param num_keycodes Number of key codes + * @return number of ascii characters sent, or 0 if none, or -1 for an + * internal error */ int input_send_keycodes(struct input_config *config, int keycode[], int count); -- cgit v1.1 From b660df3c9031ba2efded2d083c34f2ea5ff978ff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Aug 2012 15:19:06 +0000 Subject: COMMON: Implement common bounce buffer Implement common bounce buffer to be used on a less capable hardware. That includes hardware that can not do DMA from any address or such. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Andy Fleming Signed-off-by: Andy Fleming --- include/bouncebuf.h | 87 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 include/bouncebuf.h (limited to 'include') diff --git a/include/bouncebuf.h b/include/bouncebuf.h new file mode 100644 index 0000000..31021c5 --- /dev/null +++ b/include/bouncebuf.h @@ -0,0 +1,87 @@ +/* + * Generic bounce buffer implementation + * + * Copyright (C) 2012 Marek Vasut + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __INCLUDE_BOUNCEBUF_H__ +#define __INCLUDE_BOUNCEBUF_H__ + +/* + * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware. + * The source buffer is copied into the bounce buffer (if unaligned, otherwise + * the source buffer is used directly) upon start() call, then the operation + * requiring the aligned transfer happens, then the bounce buffer is lost upon + * stop() call. + */ +#define GEN_BB_READ (1 << 0) +/* + * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware. + * The source buffer starts in an undefined state upon start() call, then the + * operation requiring the aligned transfer happens, then the bounce buffer is + * copied into the destination buffer (if unaligned, otherwise destination + * buffer is used directly) upon stop() call. + */ +#define GEN_BB_WRITE (1 << 1) +/* + * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware. + * The source buffer is copied into the bounce buffer (if unaligned, otherwise + * the source buffer is used directly) upon start() call, then the operation + * requiring the aligned transfer happens, then the bounce buffer is copied + * into the destination buffer (if unaligned, otherwise destination buffer is + * used directly) upon stop() call. + */ +#define GEN_BB_RW (GEN_BB_READ | GEN_BB_WRITE) + +#ifdef CONFIG_BOUNCE_BUFFER +/** + * bounce_buffer_start() -- Start the bounce buffer session + * data: pointer to buffer to be aligned + * len: length of the buffer + * backup: pointer to backup buffer (the original value is stored here if + * needed + * flags: flags describing the transaction, see above. + */ +int bounce_buffer_start(void **data, size_t len, void **backup, uint8_t flags); +/** + * bounce_buffer_stop() -- Finish the bounce buffer session + * data: pointer to buffer that was aligned + * len: length of the buffer + * backup: pointer to backup buffer (the original value is stored here if + * needed + * flags: flags describing the transaction, see above. + */ +int bounce_buffer_stop(void **data, size_t len, void **backup, uint8_t flags); +#else +static inline int bounce_buffer_start(void **data, size_t len, void **backup, + uint8_t flags) +{ + return 0; +} + +static inline int bounce_buffer_stop(void **data, size_t len, void **backup, + uint8_t flags) +{ + return 0; +} +#endif + +#endif -- cgit v1.1 From 6dc71c8d2a3183a37624ef19a0532e7f827d868f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Aug 2012 15:19:08 +0000 Subject: MMC: MXS: Toggle the generic bounce buffer on the boards Flip the boards to use the generic bounce buffer instead of the MMC one. Signed-off-by: Marek Vasut Cc: Andy Fleming Cc: Fabio Estevam Signed-off-by: Andy Fleming --- include/configs/apx4devkit.h | 2 +- include/configs/m28evk.h | 2 +- include/configs/mx28evk.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index af0b714..6764b47 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -132,7 +132,7 @@ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_MMC_BOUNCE_BUFFER +#define CONFIG_BOUNCE_BUFFER #define CONFIG_MXS_MMC #endif diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index bdbb820..b49ec8c 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -135,7 +135,7 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#define CONFIG_MMC_BOUNCE_BUFFER +#define CONFIG_BOUNCE_BUFFER #define CONFIG_GENERIC_MMC #define CONFIG_MXS_MMC #endif diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 7cdbec6..1443833 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -142,7 +142,7 @@ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_MMC_BOUNCE_BUFFER +#define CONFIG_BOUNCE_BUFFER #define CONFIG_MXS_MMC #endif -- cgit v1.1 From 13243f2eafc4292917178051fe1bb5aab2774dca Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Thu, 20 Sep 2012 20:31:57 +0000 Subject: mmc: sdhci: Add a quirk to add delay during completion of sdhci_send_cmd MMC host controller requires a delay between every sdhci_send_cmd() execution. In s5p_mmc driver (s5p_sdhci replaces this driver), a delay of 1000us was provided after every mmc_send_cmd() call. Adding a quirk in current sdhci driver to replicate the behaviour. Without this delay, MMC initialization on Origen board fails with following error messages. Timeout for status update! mmc fail to send stop cmd Signed-off-by: Tushar Behera Signed-off-by: Jaehoon Chung Signed-off-by: Andy Fleming --- include/sdhci.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/sdhci.h b/include/sdhci.h index c0345ed..c44793d 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -224,6 +224,7 @@ #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) #define SDHCI_QUIRK_NO_CD (1 << 5) +#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) /* to make gcc happy */ struct sdhci_host; -- cgit v1.1 From 831f849f79f2c9fcaa6f85f4158296d2dbc3916c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 30 Sep 2012 10:09:49 +0000 Subject: mmc: pxa: Flip over the remaining boards to pxa_mmc_generic Some of the boards still used the old PXA_MMC driver instead of the new generic one. Use the new one instead so the old can be removed and the generic MMC framework can be properly used. Signed-off-by: Marek Vasut Cc: Andy Fleming Signed-off-by: Andy Fleming --- include/configs/lubbock.h | 3 ++- include/configs/palmtc.h | 3 ++- include/configs/pxa255_idp.h | 3 ++- include/configs/trizepsiv.h | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index ed64960..5886a15 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -130,7 +130,8 @@ #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ #ifdef CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_CMD_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 #endif diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index 6e8d8e9..9c948c5 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -77,7 +77,8 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_SYS_MMC_BASE 0xF0000000 #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 24c5363..5a15af6 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -245,7 +245,8 @@ #define RTC 1 /* enable 32KHz osc */ #ifdef CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_CMD_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 #endif diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index bc69c1e..c1bfe31 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -170,7 +170,8 @@ #define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ #ifdef CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_CMD_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 #endif -- cgit v1.1 From 757bff49ba3159d71ccacabdb68f8309b1eb6613 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Mon, 15 Oct 2012 19:10:29 +0000 Subject: mmc: dw-mmc: support DesignWare MMC Controller Support the DesginWare MMC Controller. Signed-off-by: Jaehoon Chung Signed-off-by: Kyungmin Park Signed-off-by: Rajeshawari Shinde Signed-off-by: Andy Fleming --- include/dwmmc.h | 191 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 191 insertions(+) create mode 100644 include/dwmmc.h (limited to 'include') diff --git a/include/dwmmc.h b/include/dwmmc.h new file mode 100644 index 0000000..c8b1d40 --- /dev/null +++ b/include/dwmmc.h @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __DWMMC_HW_H +#define __DWMMC_HW_H + +#include +#include + +#define DWMCI_CTRL 0x000 +#define DWMCI_PWREN 0x004 +#define DWMCI_CLKDIV 0x008 +#define DWMCI_CLKSRC 0x00C +#define DWMCI_CLKENA 0x010 +#define DWMCI_TMOUT 0x014 +#define DWMCI_CTYPE 0x018 +#define DWMCI_BLKSIZ 0x01C +#define DWMCI_BYTCNT 0x020 +#define DWMCI_INTMASK 0x024 +#define DWMCI_CMDARG 0x028 +#define DWMCI_CMD 0x02C +#define DWMCI_RESP0 0x030 +#define DWMCI_RESP1 0x034 +#define DWMCI_RESP2 0x038 +#define DWMCI_RESP3 0x03C +#define DWMCI_MINTSTS 0x040 +#define DWMCI_RINTSTS 0x044 +#define DWMCI_STATUS 0x048 +#define DWMCI_FIFOTH 0x04C +#define DWMCI_CDETECT 0x050 +#define DWMCI_WRTPRT 0x054 +#define DWMCI_GPIO 0x058 +#define DWMCI_TCMCNT 0x05C +#define DWMCI_TBBCNT 0x060 +#define DWMCI_DEBNCE 0x064 +#define DWMCI_USRID 0x068 +#define DWMCI_VERID 0x06C +#define DWMCI_HCON 0x070 +#define DWMCI_UHS_REG 0x074 +#define DWMCI_BMOD 0x080 +#define DWMCI_PLDMND 0x084 +#define DWMCI_DBADDR 0x088 +#define DWMCI_IDSTS 0x08C +#define DWMCI_IDINTEN 0x090 +#define DWMCI_DSCADDR 0x094 +#define DWMCI_BUFADDR 0x098 +#define DWMCI_DATA 0x200 + +/* Interrupt Mask register */ +#define DWMCI_INTMSK_ALL 0xffffffff +#define DWMCI_INTMSK_RE (1 << 1) +#define DWMCI_INTMSK_CDONE (1 << 2) +#define DWMCI_INTMSK_DTO (1 << 3) +#define DWMCI_INTMSK_TXDR (1 << 4) +#define DWMCI_INTMSK_RXDR (1 << 5) +#define DWMCI_INTMSK_DCRC (1 << 7) +#define DWMCI_INTMSK_RTO (1 << 8) +#define DWMCI_INTMSK_DRTO (1 << 9) +#define DWMCI_INTMSK_HTO (1 << 10) +#define DWMCI_INTMSK_FRUN (1 << 11) +#define DWMCI_INTMSK_HLE (1 << 12) +#define DWMCI_INTMSK_SBE (1 << 13) +#define DWMCI_INTMSK_ACD (1 << 14) +#define DWMCI_INTMSK_EBE (1 << 15) + +/* Raw interrupt Regsiter */ +#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ + DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) +#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) +/* CTRL register */ +#define DWMCI_CTRL_RESET (1 << 0) +#define DWMCI_CTRL_FIFO_RESET (1 << 1) +#define DWMCI_CTRL_DMA_RESET (1 << 2) +#define DWMCI_DMA_EN (1 << 5) +#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) +#define DWMCI_IDMAC_EN (1 << 25) +#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ + DWMCI_CTRL_DMA_RESET) + +/* CMD register */ +#define DWMCI_CMD_RESP_EXP (1 << 6) +#define DWMCI_CMD_RESP_LENGTH (1 << 7) +#define DWMCI_CMD_CHECK_CRC (1 << 8) +#define DWMCI_CMD_DATA_EXP (1 << 9) +#define DWMCI_CMD_RW (1 << 10) +#define DWMCI_CMD_SEND_STOP (1 << 12) +#define DWMCI_CMD_ABORT_STOP (1 << 14) +#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) +#define DWMCI_CMD_UPD_CLK (1 << 21) +#define DWMCI_CMD_USE_HOLD_REG (1 << 29) +#define DWMCI_CMD_START (1 << 31) + +/* CLKENA register */ +#define DWMCI_CLKEN_ENABLE (1 << 0) +#define DWMCI_CLKEN_LOW_PWR (1 << 16) + +/* Card-type registe */ +#define DWMCI_CTYPE_1BIT 0 +#define DWMCI_CTYPE_4BIT (1 << 0) +#define DWMCI_CTYPE_8BIT (1 << 16) + +/* Status Register */ +#define DWMCI_BUSY (1 << 9) + +/* FIFOTH Register */ +#define MSIZE(x) ((x) << 28) +#define RX_WMARK(x) ((x) << 16) +#define TX_WMARK(x) (x) + +#define DWMCI_IDMAC_OWN (1 << 31) +#define DWMCI_IDMAC_CH (1 << 4) +#define DWMCI_IDMAC_FS (1 << 3) +#define DWMCI_IDMAC_LD (1 << 2) + +/* Bus Mode Register */ +#define DWMCI_BMOD_IDMAC_RESET (1 << 0) +#define DWMCI_BMOD_IDMAC_FB (1 << 1) +#define DWMCI_BMOD_IDMAC_EN (1 << 7) + +struct dwmci_host { + char *name; + void *ioaddr; + unsigned int quirks; + unsigned int caps; + unsigned int version; + unsigned int clock; + unsigned int bus_hz; + int dev_index; + int buswidth; + u32 fifoth_val; + struct mmc *mmc; + + void (*clksel)(struct dwmci_host *host); + unsigned int (*mmc_clk)(int dev_index); +}; + +struct dwmci_idmac { + u32 flags; + u32 cnt; + u32 addr; + u32 next_addr; +}; + +static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) +{ + writel(val, host->ioaddr + reg); +} + +static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val) +{ + writew(val, host->ioaddr + reg); +} + +static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) +{ + writeb(val, host->ioaddr + reg); +} +static inline u32 dwmci_readl(struct dwmci_host *host, int reg) +{ + return readl(host->ioaddr + reg); +} + +static inline u16 dwmci_readw(struct dwmci_host *host, int reg) +{ + return readw(host->ioaddr + reg); +} + +static inline u8 dwmci_readb(struct dwmci_host *host, int reg) +{ + return readb(host->ioaddr + reg); +} + +int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); +#endif /* __DWMMC_HW_H */ -- cgit v1.1 From 42ebaae3a33b8393a37e7176234e71b5eada58d4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Oct 2012 10:27:02 +0000 Subject: common: Implement support for linker-generated arrays This patch adds support for linker-generated array. These arrays are a generalization of the U-Boot command declaration approach. Basically, the idea is to generate an array, where elements of the array are statically initialized at compile time and each element is declared separatelly at different place. Such array is assembled together into continuous piece of memory by linker and a pointer to it's first entry can then be retrieved via accessor. The actual implementation relies on placing any variable that is to represent an element of LG-array into particular subsection of the .u_boot_list linker section . The subsection is determined by user options. Once compiled, it is possible to dump all symbols placed in .u_boot_list section and the subsections in which they should be and generate appropriate bounds for each requested subsection of the .u_boot_list section. Each such subsection thus contains __start and __end entries at the begining and end respecitively. This allows for simple run-time traversing of the array, since the symbols are properly defined. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Mike Frysinger --- include/linker_lists.h | 148 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 include/linker_lists.h (limited to 'include') diff --git a/include/linker_lists.h b/include/linker_lists.h new file mode 100644 index 0000000..0b405d7 --- /dev/null +++ b/include/linker_lists.h @@ -0,0 +1,148 @@ +/* + * include/linker_lists.h + * + * Implementation of linker-generated arrays + * + * Copyright (C) 2012 Marek Vasut + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ +#ifndef __LINKER_LISTS_H__ +#define __LINKER_LISTS_H__ + +/** + * ll_entry_declare() - Declare linker-generated array entry + * @_type: Data type of the entry + * @_name: Name of the entry + * @_section_u: Subsection of u_boot_list in which this entry is placed + * (with underscores instead of dots, for name concatenation) + * @_section_d: Subsection of u_boot_list in which this entry is placed + * (with dots, for section concatenation) + * + * This macro declares a variable that is placed into a linker-generated + * array. This is a basic building block for more advanced use of linker- + * generated arrays. The user is expected to build their own macro wrapper + * around this one. + * + * A variable declared using this macro must be compile-time initialized + * and is as such placed into subsection of special section, .u_boot_list. + * The subsection is specified by the _section_[u,d] parameter, see below. + * The base name of the variable is _name, yet the actual variable is + * declared as concatenation of + * + * %_u_boot_list_ + @_section_u + _ + @_name + * + * which ensures name uniqueness. This variable shall never be refered + * directly though. + * + * Special precaution must be made when using this macro: + * 1) The _type must not contain the "static" keyword, otherwise the entry + * is not generated. + * + * 2) The @_section_u and @_section_d variables must match, the only difference + * is that in @_section_u is every dot "." character present in @_section_d + * replaced by a single underscore "_" character in @_section_u. The actual + * purpose of these parameters is to select proper subsection in the global + * .u_boot_list section. + * + * 3) In case a section is declared that contains some array elements AND a + * subsection of this section is declared and contains some elements, it is + * imperative that the elements are of the same type. + * + * 4) In case an outer section is declared that contains some array elements + * AND am inner subsection of this section is declared and contains some + * elements, then when traversing the outer section, even the elements of + * the inner sections are present in the array. + * + * Example: + * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = { + * .x = 3, + * .y = 4, + * }; + */ +#define ll_entry_declare(_type, _name, _section_u, _section_d) \ + _type _u_boot_list_##_section_u##_##_name __attribute__(( \ + unused, aligned(4), \ + section(".u_boot_list."#_section_d"."#_name))) + +/** + * ll_entry_start() - Point to first entry of linker-generated array + * @_type: Data type of the entry + * @_section_u: Subsection of u_boot_list in which this entry is placed + * (with underscores instead of dots) + * + * This function returns (_type *) pointer to the very first entry of a + * linker-generated array placed into subsection of .u_boot_list section + * specified by _section_u argument. + * + * Example: + * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub); + */ +#define ll_entry_start(_type, _section_u) \ + ({ \ + extern _type _u_boot_list_##_section_u##__start; \ + _type *_ll_result = &_u_boot_list_##_section_u##__start;\ + _ll_result; \ + }) + +/** + * ll_entry_count() - Return the number of elements in linker-generated array + * @_type: Data type of the entry + * @_section_u: Subsection of u_boot_list in which this entry is placed + * (with underscores instead of dots) + * + * This function returns the number of elements of a linker-generated array + * placed into subsection of .u_boot_list section specified by _section_u + * argument. The result is of an unsigned int type. + * + * Example: + * int i; + * const unsigned int count = ll_entry_count(struct my_sub_cmd, cmd_sub); + * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub); + * for (i = 0; i < count; i++, msc++) + * printf("Entry %i, x=%i y=%i\n", i, msc->x, msc->y); + */ +#define ll_entry_count(_type, _section_u) \ + ({ \ + extern _type _u_boot_list_##_section_u##__start; \ + extern _type _u_boot_list_##_section_u##__end; \ + unsigned int _ll_result = \ + &_u_boot_list_##_section_u##__end - \ + &_u_boot_list_##_section_u##__start; \ + _ll_result; \ + }) + + +/** + * ll_entry_get() - Retrieve entry from linker-generated array by name + * @_type: Data type of the entry + * @_name: Name of the entry + * @_section_u: Subsection of u_boot_list in which this entry is placed + * (with underscores instead of dots) + * + * This function returns a pointer to a particular entry in LG-array + * identified by the subsection of u_boot_list where the entry resides + * and it's name. + * + * Example: + * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = { + * .x = 3, + * .y = 4, + * }; + * ... + * struct my_sub_cmd *c = ll_entry_get(struct my_sub_cmd, my_sub_cmd, cmd_sub); + */ +#define ll_entry_get(_type, _name, _section_u) \ + ({ \ + extern _type _u_boot_list_##_section_u##_##_name; \ + _type *_ll_result = &_u_boot_list_##_section_u##_##_name;\ + _ll_result; \ + }) + +#endif /* __LINKER_LISTS_H__ */ -- cgit v1.1 From 6c7c946cadfafdea80eb930e3181085b907a0362 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Oct 2012 10:27:04 +0000 Subject: common: Convert the U-Boot commands to LG-arrays This patch converts the old method of creating a list of command onto the new LG-arrays code. The old u_boot_cmd section is converted to new u_boot_list_cmd subsection and LG-array macros used as needed. Minor adjustments had to be made to the common code to work with the LG-array macros, mostly the fixup_cmdtable() calls are now passed the ll_entry_start and ll_entry_count instead of linker-generated symbols. The command.c had to be adjusted as well so it would use the newly introduced LG-array API instead of directly using linker-generated symbols. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Mike Frysinger --- include/command.h | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/command.h b/include/command.h index 1f06aa1..24864d5 100644 --- a/include/command.h +++ b/include/command.h @@ -28,6 +28,7 @@ #define __COMMAND_H #include +#include #ifndef NULL #define NULL 0 @@ -153,9 +154,6 @@ int cmd_process(int flag, int argc, char * const argv[], #define CMD_FLAG_REPEAT 0x0001 /* repeat last command */ #define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */ -#define Struct_Section __attribute__((unused, section(".u_boot_cmd"), \ - aligned(4))) - #ifdef CONFIG_AUTO_COMPLETE # define _CMD_COMPLETE(x) x, #else @@ -167,18 +165,22 @@ int cmd_process(int flag, int argc, char * const argv[], # define _CMD_HELP(x) #endif -#define U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \ - {#name, maxargs, rep, cmd, usage, _CMD_HELP(help) _CMD_COMPLETE(comp)} +#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ + _usage, _help, _comp) \ + { #_name, _maxargs, _rep, _cmd, _usage, \ + _CMD_HELP(_help) _CMD_COMPLETE(_comp) } -#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \ - U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL) +#define U_BOOT_CMD_MKENT(_name, _maxargs, _rep, _cmd, _usage, _help) \ + U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ + _usage, _help, NULL) -#define U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \ - cmd_tbl_t __u_boot_cmd_##name Struct_Section = \ - U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) +#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \ + ll_entry_declare(cmd_tbl_t, _name, cmd, cmd) = \ + U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ + _usage, _help, _comp); -#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \ - U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL) +#define U_BOOT_CMD(_name, _maxargs, _rep, _cmd, _usage, _help) \ + U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL) #if defined(CONFIG_NEEDS_MANUAL_RELOC) void fixup_cmdtable(cmd_tbl_t *cmdtp, int size); -- cgit v1.1 From 8b493a52367623f36e628e4ab2cf8ee082b655e0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 17 Oct 2012 00:45:46 +0000 Subject: common: Discard the __u_boot_cmd section The command declaration now uses the new LG-array method to generate list of commands. Thus the __u_boot_cmd section is now superseded and redundant and therefore can be removed. Also, remove externed symbols associated with this section from include/command.h . Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Mike Frysinger --- include/command.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/command.h b/include/command.h index 24864d5..10bc260 100644 --- a/include/command.h +++ b/include/command.h @@ -62,8 +62,6 @@ struct cmd_tbl_s { typedef struct cmd_tbl_s cmd_tbl_t; -extern cmd_tbl_t __u_boot_cmd_start; -extern cmd_tbl_t __u_boot_cmd_end; #if defined(CONFIG_CMD_RUN) extern int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -- cgit v1.1 From 24a3fdd64d449c1acd4ccc3636f8bf02e903b6f8 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2012 14:26:06 +0000 Subject: ide: Add printf format string for CONFIG_SYS_64BIT_LBA option The size of an LBA type changes depending on this option. We need to use a different printf() string in each case, so create a define for this. Signed-off-by: Gabe Black Signed-off-by: Simon Glass --- include/ide.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/ide.h b/include/ide.h index 695d08e..158e1be 100644 --- a/include/ide.h +++ b/include/ide.h @@ -43,8 +43,10 @@ extern ulong ide_bus_offset[]; #ifdef CONFIG_SYS_64BIT_LBA typedef uint64_t lbaint_t; +#define LBAF "%llx" #else typedef ulong lbaint_t; +#define LBAF "%lx" #endif /* -- cgit v1.1 From 84cd93272e384bf26e8346f2153a0b46dfb7b434 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2012 14:26:11 +0000 Subject: fs: Add a Coreboot Filesystem (CBFS) driver and commands This change adds CBFS support and some commands to use it to u-boot. These commands are: cbfsinit - Initialize CBFS support and pull all metadata into RAM. The end of the ROM is an optional parameter which defaults to the standard 0xffffffff and can be used to support multiple CBFSes in a system. The last one set up with cbfsinit is the one that will be used. cbfsinfo - Print information from the CBFS header. cbfsls - Print out the size, type, and name of all the files in the current CBFS. Recognized types are translated into symbolic names. cbfsload - Load a file from CBFS into memory. Like the similar command for fat filesystems, you can optionally provide a maximum size. Support for CBFS is compiled in when the CONFIG_CMD_CBFS option is specified. The CBFS driver can also be used programmatically from within u-boot. If u-boot needs something out of CBFS very early before the heap is configured, it won't be able to use the normal CBFS support which caches some information in memory it allocates from the heap. The cbfs_file_find_uncached function searches a CBFS instance without touching the heap. Signed-off-by: Gabe Black Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- include/cbfs.h | 181 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 181 insertions(+) create mode 100644 include/cbfs.h (limited to 'include') diff --git a/include/cbfs.h b/include/cbfs.h new file mode 100644 index 0000000..6ea3f35 --- /dev/null +++ b/include/cbfs.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CBFS_H +#define __CBFS_H + +#include +#include + +enum cbfs_result { + CBFS_SUCCESS = 0, + CBFS_NOT_INITIALIZED, + CBFS_BAD_HEADER, + CBFS_BAD_FILE, + CBFS_FILE_NOT_FOUND +}; + +enum cbfs_filetype { + CBFS_TYPE_STAGE = 0x10, + CBFS_TYPE_PAYLOAD = 0x20, + CBFS_TYPE_OPTIONROM = 0x30, + CBFS_TYPE_BOOTSPLASH = 0x40, + CBFS_TYPE_RAW = 0x50, + CBFS_TYPE_VSA = 0x51, + CBFS_TYPE_MBI = 0x52, + CBFS_TYPE_MICROCODE = 0x53, + CBFS_COMPONENT_CMOS_DEFAULT = 0xaa, + CBFS_COMPONENT_CMOS_LAYOUT = 0x01aa +}; + +struct cbfs_header { + u32 magic; + u32 version; + u32 rom_size; + u32 boot_block_size; + u32 align; + u32 offset; + u32 pad[2]; +} __packed; + +struct cbfs_fileheader { + u8 magic[8]; + u32 len; + u32 type; + u32 checksum; + u32 offset; +} __packed; + +struct cbfs_cachenode { + struct cbfs_cachenode *next; + u32 type; + void *data; + u32 data_length; + char *name; + u32 name_length; + u32 checksum; +} __packed; + +extern enum cbfs_result file_cbfs_result; + +/* + * Return a string describing the most recent error condition. + * + * @return A pointer to the constant string. + */ +const char *file_cbfs_error(void); + +/* + * Initialize the CBFS driver and load metadata into RAM. + * + * @param end_of_rom Points to the end of the ROM the CBFS should be read + * from. + */ +void file_cbfs_init(uintptr_t end_of_rom); + +/* + * Get the header structure for the current CBFS. + * + * @return A pointer to the constant structure, or NULL if there is none. + */ +const struct cbfs_header *file_cbfs_get_header(void); + +/* + * Get a handle for the first file in CBFS. + * + * @return A handle for the first file in CBFS, NULL on error. + */ +const struct cbfs_cachenode *file_cbfs_get_first(void); + +/* + * Get a handle to the file after this one in CBFS. + * + * @param file A pointer to the handle to advance. + */ +void file_cbfs_get_next(const struct cbfs_cachenode **file); + +/* + * Find a file with a particular name in CBFS. + * + * @param name The name to search for. + * + * @return A handle to the file, or NULL on error. + */ +const struct cbfs_cachenode *file_cbfs_find(const char *name); + + +/***************************************************************************/ +/* All of the functions below can be used without first initializing CBFS. */ +/***************************************************************************/ + +/* + * Find a file with a particular name in CBFS without using the heap. + * + * @param end_of_rom Points to the end of the ROM the CBFS should be read + * from. + * @param name The name to search for. + * + * @return A handle to the file, or NULL on error. + */ +const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom, + const char *name); + +/* + * Get the name of a file in CBFS. + * + * @param file The handle to the file. + * + * @return The name of the file, NULL on error. + */ +const char *file_cbfs_name(const struct cbfs_cachenode *file); + +/* + * Get the size of a file in CBFS. + * + * @param file The handle to the file. + * + * @return The size of the file, zero on error. + */ +u32 file_cbfs_size(const struct cbfs_cachenode *file); + +/* + * Get the type of a file in CBFS. + * + * @param file The handle to the file. + * + * @return The type of the file, zero on error. + */ +u32 file_cbfs_type(const struct cbfs_cachenode *file); + +/* + * Read a file from CBFS into RAM + * + * @param file A handle to the file to read. + * @param buffer Where to read it into memory. + * + * @return If positive or zero, the number of characters read. If negative, an + * error occurred. + */ +long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer, + unsigned long maxsize); + +#endif /* __CBFS_H */ -- cgit v1.1 From af9f881a517ec54805419279885a661b762697d3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:26:12 +0000 Subject: config: Enable CBFS, ext4 for coreboot Enable Coreboot and EXT4 Filesystems on the coreboot board. Signed-off-by: Simon Glass --- include/configs/coreboot.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 0e89242..3df085b 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -92,6 +92,9 @@ #define CONFIG_MAC_PARTITION #define CONFIG_ISO_PARTITION /* Experimental */ +#define CONFIG_CMD_CBFS +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE /*----------------------------------------------------------------------- * Video Configuration -- cgit v1.1 From 11860d888cdc2be5da7b8738a067b84cd76e71c0 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 5 Oct 2012 09:48:53 +0000 Subject: powerpc/85xx: move SRIO configuration out of corenet_ds.h The P5040 does not have SRIO, so don't put the SRIO definitions in corenet_ds.h. They belong in the board-specific header files. Signed-off-by: Timur Tabi Signed-off-by: Andy Fleming --- include/configs/P3041DS.h | 4 ++++ include/configs/P4080DS.h | 4 ++++ include/configs/P5020DS.h | 4 ++++ include/configs/corenet_ds.h | 4 ---- 4 files changed, 12 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index 98e7a42..cf184e7 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -36,6 +36,10 @@ #define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index d6f2f5c..53979dd 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -33,6 +33,10 @@ #define CONFIG_MMC #define CONFIG_PCIE3 +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 8625f76..7018d7a 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -37,6 +37,10 @@ #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 8489d16..c41b039 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -76,10 +76,6 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ - #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE -- cgit v1.1 From 9e758758491b0d7a71bdf1db8cd860b599d7e657 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:19 +0000 Subject: powerpc/mpc85xx: Add T4240 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming Signed-off-by: Roy Zang Signed-off-by: Prabhakar Kushwaha Signed-off-by: Shengzhou Liu Signed-off-by: Andy Fleming --- include/fm_eth.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/fm_eth.h b/include/fm_eth.h index e56541d..5d80e49 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -30,13 +30,21 @@ enum fm_port { FM1_DTSEC3, FM1_DTSEC4, FM1_DTSEC5, + FM1_DTSEC6, + FM1_DTSEC9, + FM1_DTSEC10, FM1_10GEC1, + FM1_10GEC2, FM2_DTSEC1, FM2_DTSEC2, FM2_DTSEC3, FM2_DTSEC4, FM2_DTSEC5, + FM2_DTSEC6, + FM2_DTSEC9, + FM2_DTSEC10, FM2_10GEC1, + FM2_10GEC2, NUM_FM_PORTS, }; -- cgit v1.1 From 111fd19e3b9eb1005fd24ef09c163dd10103f5fa Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Mon, 8 Oct 2012 07:44:21 +0000 Subject: fm/mEMAC: add mEMAC frame work The multirate ethernet media access controller (mEMAC) interfaces to 10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface. Signed-off-by: Sandeep Singh Signed-off-by: Poonam Aggrwal Signed-off-by: Roy Zang Signed-off-by: Andy Fleming --- include/fm_eth.h | 45 +++++++++++++++++++++++++++++++++++++++++++-- include/fsl_mdio.h | 6 +++++- 2 files changed, 48 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/fm_eth.h b/include/fm_eth.h index 5d80e49..495765b 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -53,8 +53,15 @@ enum fm_eth_type { FM_ETH_10G_E, }; +#ifdef CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) +#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) +#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000) +#else #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) +#endif #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0" #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO" @@ -65,6 +72,33 @@ enum fm_eth_type { .phy_regs = (void *)pregs, \ .enet_if = PHY_INTERFACE_MODE_NONE, \ +#ifdef CONFIG_SYS_FMAN_V3 +#define FM_DTSEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_1G_E, \ + .port = FM##idx##_DTSEC##n, \ + .rx_port_id = RX_PORT_1G_BASE + n - 1, \ + .tx_port_id = TX_PORT_1G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1]),\ +} + +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1]),\ +} +#else #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \ @@ -90,7 +124,7 @@ enum fm_eth_type { .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, mac_10g[n-1]),\ } - +#endif struct fm_eth_info { u8 enabled; u8 fm; @@ -112,7 +146,14 @@ struct tgec_mdio_info { char *name; }; +struct memac_mdio_info { + struct memac_mdio_controller *regs; + char *name; +}; + int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info); +int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info); + int fm_standard_init(bd_t *bis); void fman_enet_init(void); void fdt_fixup_fman_ethernet(void *fdt); diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h index ea8b54b..e24e828 100644 --- a/include/fsl_mdio.h +++ b/include/fsl_mdio.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * Jun-jie Zhang * Mingkai Hu * @@ -51,6 +51,10 @@ int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, u16 value); +int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum, u16 value); +int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum); struct fsl_pq_mdio_info { struct tsec_mii_mng *regs; -- cgit v1.1 From ee52b188ca2c631427d197056ab7b71b9e23bde7 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 11 Oct 2012 07:13:37 +0000 Subject: powerpc/t4qds: Add T4QDS board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by: York Sun Signed-off-by: Andy Fleming Signed-off-by: Kumar Gala Signed-off-by: Prabhakar Kushwaha Signed-off-by: Shengzhou Liu Signed-off-by: Roy Zang Signed-off-by: Andy Fleming --- include/configs/T4240QDS.h | 35 ++ include/configs/t4qds.h | 875 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 910 insertions(+) create mode 100644 include/configs/T4240QDS.h create mode 100644 include/configs/t4qds.h (limited to 'include') diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h new file mode 100644 index 0000000..76b3ca6 --- /dev/null +++ b/include/configs/T4240QDS.h @@ -0,0 +1,35 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * T4240 QDS board configuration file + */ +#define CONFIG_T4240QDS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_T4240 + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "t4qds.h" diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h new file mode 100644 index 0000000..d58c24c --- /dev/null +++ b/include/configs/t4qds.h @@ -0,0 +1,875 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Corenet DS style board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +#define CONFIG_CMD_REGINFO + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E6500 +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1097) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif +#else /* CONFIG_SYS_NO_FLASH */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + + + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#if 0 +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#endif +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + +#define CONFIG_DDR_SPD +#define CONFIG_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ + FTIM0_NOR_TEADC(0x01) | \ + FTIM0_NOR_TEAHC(0x20)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ + FTIM2_NOR_TCH(0x0E) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x83 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#ifdef CONFIG_PHYS_64BIT +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) +#else +#define QIXIS_BASE_PHYS QIXIS_BASE +#endif + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x118000 +#define CONFIG_SYS_I2C2_OFFSET 0x118100 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ + +/* VSC Crossbar switches */ +#define CONFIG_VSC_CROSSBAR +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_VSC3316_FS 0xc +#define I2C_MUX_CH_VSC3316_BS 0xd +#define VSC3316_FSM_TX_ADDR 0x70 +#define VSC3316_FSM_RX_ADDR 0x71 + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ + +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ + +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 50 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 50 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 545KB (1089 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_TERANETICS +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#define XFI_CARD_PORT1_PHY_ADDR 0x1 /* tmp, FIXME below addr */ +#define XFI_CARD_PORT2_PHY_ADDR 0x2 +#define XFI_CARD_PORT3_PHY_ADDR 0x3 +#define XFI_CARD_PORT4_PHY_ADDR 0x4 +#define QSGMII_CARD_PHY_ADDR 0x5 +#define FM1_10GEC1_PHY_ADDR 0x6 +#define FM1_10GEC2_PHY_ADDR 0x7 +#define FM2_10GEC1_PHY_ADDR 0x8 +#define FM2_10GEC2_PHY_ADDR 0x9 +#endif + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* +* USB +*/ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=3way_4KB," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t4240qds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t4240qds/t4240qds.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +/* For emulation this causes u-boot to jump to the start of the proof point + app code automatically */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#endif + +#endif /* __CONFIG_H */ -- cgit v1.1 From 990e1a8ce1415b9010faccd1402d499e203ea2fb Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 11 Oct 2012 07:13:39 +0000 Subject: poweprc/85xx: add QMan frequency info and fdt fixup. Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel driver can use it to calculate the shaper prescaler and rate. Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- include/e500.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/e500.h b/include/e500.h index e1708b9..0ff8e89 100644 --- a/include/e500.h +++ b/include/e500.h @@ -18,6 +18,9 @@ typedef struct #ifdef CONFIG_SYS_DPAA_FMAN unsigned long freqFMan[CONFIG_SYS_NUM_FMAN]; #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + unsigned long freqQMAN; +#endif #ifdef CONFIG_SYS_DPAA_PME unsigned long freqPME; #endif -- cgit v1.1 From d8812bdbba21eefdf773ab3a42dcdf966d68ab92 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 12 Oct 2012 02:34:15 +0000 Subject: phylib: Enable SMSC LAN87xx PHY support LAN8720 PHY is used on Freescale C2X0QDS board. Signed-off-by: Mingkai Hu Signed-off-by: Andy Fleming --- include/config_phylib_all_drivers.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/config_phylib_all_drivers.h b/include/config_phylib_all_drivers.h index 1db7cec..12828c6 100644 --- a/include/config_phylib_all_drivers.h +++ b/include/config_phylib_all_drivers.h @@ -23,6 +23,7 @@ #define CONFIG_PHY_NATSEMI #define CONFIG_PHY_LXT #define CONFIG_PHY_ATHEROS +#define CONFIG_PHY_SMSC #ifdef CONFIG_PHYLIB_10G #define CONFIG_PHY_TERANETICS -- cgit v1.1 From 669681104daac2bfbdc733d7426b19e358eced8a Mon Sep 17 00:00:00 2001 From: Andrew Bradford Date: Mon, 1 Oct 2012 05:06:52 +0000 Subject: configs: Fix usage of mmc rescan Fix usage of 'mmc rescan' by many configs. Proper use is 'mmc dev ${mmcdev}; mmc rescan' to set the mmc device and then rescan the device. 'mmc rescan' itself does not take any arguments. Signed-off-by: Andrew Bradford --- include/configs/am335x_evm.h | 2 +- include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/cm_t35.h | 2 +- include/configs/devkit8000.h | 2 +- include/configs/igep00x0.h | 2 +- include/configs/mx28evk.h | 2 +- include/configs/mx51evk.h | 2 +- include/configs/mx53ard.h | 2 +- include/configs/mx53evk.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/mx53smd.h | 2 +- include/configs/mx6qarm2.h | 2 +- include/configs/mx6qsabrelite.h | 2 +- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_logic.h | 2 +- include/configs/omap3_overo.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/omap4_common.h | 2 +- include/configs/omap5_evm.h | 2 +- include/configs/tricorder.h | 2 +- 22 files changed, 22 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 339d4bd..9d80739 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -81,7 +81,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadbootenv; then " \ "echo Loaded environment from ${bootenv};" \ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 8ddeff4..20a3df5 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -209,7 +209,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 6980811..ce71d13 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -206,7 +206,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 46c556d..6f355c7 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -231,7 +231,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 1e65806..da3263f 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -233,7 +233,7 @@ "dhcp ${loadaddr}; " \ "run netargs; " \ "bootm ${loadaddr}\0" \ - "autoboot=if mmc rescan ${mmcdev}; then " \ + "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index b1071e8..c81ab76 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -180,7 +180,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadbootenv; then " \ "run importbootenv;" \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 7cdbec6..e188f02 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -313,7 +313,7 @@ "dhcp ${uimage}; bootm\0" #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 34b0783..dcae537 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -182,7 +182,7 @@ "dhcp ${uimage}; bootm\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index fea93b4..62cb42b 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -119,7 +119,7 @@ "dhcp ${uimage}; bootm\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 832050e..69937d8 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -132,7 +132,7 @@ "dhcp ${uimage}; bootm\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 6a6aaa1..55efeb7 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -140,7 +140,7 @@ "dhcp ${uimage}; bootm\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index ff2a290..9e83319 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -118,7 +118,7 @@ "dhcp ${uimage}; bootm\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 965bea3..fbc5162 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -106,7 +106,7 @@ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev};" \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index e7bf658..ec9ab26 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -164,7 +164,7 @@ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev};" \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index f79f996..7a3cc16 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -289,7 +289,7 @@ "userbutton_nonxm=gpio input 7;\0" /* "run userbutton" will return 1 (false) if is pressed and 0 (false) if not */ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run userbutton; then " \ "setenv bootenv uEnv.txt;" \ "else " \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 632a13f..f6e4236 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -162,7 +162,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index b975a6c..b2457d0 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -202,7 +202,7 @@ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ - "autoboot=if mmc rescan ${mmcdev}; then " \ + "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index f6d6f75..626cf7a 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -188,7 +188,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 891e6f4..e152055 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -198,7 +198,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index cbc9bdb..a32369a 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -165,7 +165,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 743edfd..623da77 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -167,7 +167,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 00d02e8..5859a73 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -201,7 +201,7 @@ "run nandargs; " \ "run loaduimage_ubi; " \ "bootm ${loadaddr}\0" \ - "autoboot=if mmc rescan ${mmcdev}; then " \ + "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ -- cgit v1.1 From 3530a35d747508e98976a1d86a6d3f9b31cb3fd2 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Sun, 7 Oct 2012 01:17:34 +0000 Subject: cm-t35: clean unused defines from config Neither cm-t35, nor cm-t3730 is using OneNAND or flash. Remove the related defines from config file. Signed-off-by: Igor Grinberg --- include/configs/cm_t35.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'include') diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 6f355c7..568ae8e 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -289,25 +289,15 @@ */ /* **** PISMO SUPPORT *** */ - /* Configure the PISMO */ #define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE -#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_ENV_IS_IN_NAND -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ - #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -- cgit v1.1 From 91eb52ade2d929015a86ade10314908c1a74973e Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:05 +0000 Subject: cosmetic: suvd3: align #defines Signed-off-by: Gerlando Falauto Signed-off-by: Kim Phillips --- include/configs/km/km8321-common.h | 2 +- include/configs/suvd3.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index 580b72f..8ad6fc3 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -115,7 +115,7 @@ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index ae19701..68680c5 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -33,9 +33,9 @@ #include "km/km8321-common.h" #define CONFIG_SYS_APP1_BASE 0xA0000000 -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -- cgit v1.1 From 8afad91f15880d34c7456159209b26918977c400 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:07 +0000 Subject: cleanup: introduce CONFIG_MPC830x Introduce a new configuration token CONFIG_MPC830x to be shared among mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor existing common code so to make future introduction of 8309 simpler. Signed-off-by: Gerlando Falauto Signed-off-by: Kim Phillips --- include/configs/MPC8308RDB.h | 1 + include/configs/mpc8308_p1m.h | 1 + include/mpc83xx.h | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index a1fbece..95a1885 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -30,6 +30,7 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 035a1b6..aa681f0 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -30,6 +30,7 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index a78f1a2..7a19740 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -969,7 +969,7 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 -- cgit v1.1 From a88731a6c23113c713351847d019d23df46f26d7 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:08 +0000 Subject: mpc83xx: add support for mpc8309 This processor, though very similar to other members of the PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides yet another feature set than any supported sibling. Signed-off-by: Gerlando Falauto Signed-off-by: Kim Phillips --- include/mpc83xx.h | 153 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) (limited to 'include') diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 7a19740..b295d6d 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -74,6 +74,7 @@ #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) #define SPR_8308 0x8100 +#define SPR_8309 0x8110 #define SPR_831X_FAMILY 0x80B #define SPR_8311 0x80B2 #define SPR_8313 0x80B0 @@ -389,6 +390,86 @@ #define SICRH_TSOBI1_V2P5 (1 << 1) #define SICRH_TSOBI2_V3P3 (0 << 0) #define SICRH_TSOBI2_V2P5 (1 << 0) + +#elif defined(CONFIG_MPC8309) +/* SICR_1 */ +#define SICR_1_UART1_UART1S (0 << (30-2)) +#define SICR_1_UART1_UART1RTS (1 << (30-2)) +#define SICR_1_I2C_I2C (0 << (30-4)) +#define SICR_1_I2C_CKSTOP (1 << (30-4)) +#define SICR_1_IRQ_A_IRQ (0 << (30-6)) +#define SICR_1_IRQ_A_MCP (1 << (30-6)) +#define SICR_1_IRQ_B_IRQ (0 << (30-8)) +#define SICR_1_IRQ_B_CKSTOP (1 << (30-8)) +#define SICR_1_GPIO_A_GPIO (0 << (30-10)) +#define SICR_1_GPIO_A_SD (2 << (30-10)) +#define SICR_1_GPIO_A_DDR (3 << (30-10)) +#define SICR_1_GPIO_B_GPIO (0 << (30-12)) +#define SICR_1_GPIO_B_SD (2 << (30-12)) +#define SICR_1_GPIO_B_QE (3 << (30-12)) +#define SICR_1_GPIO_C_GPIO (0 << (30-14)) +#define SICR_1_GPIO_C_CAN (1 << (30-14)) +#define SICR_1_GPIO_C_DDR (2 << (30-14)) +#define SICR_1_GPIO_C_LCS (3 << (30-14)) +#define SICR_1_GPIO_D_GPIO (0 << (30-16)) +#define SICR_1_GPIO_D_CAN (1 << (30-16)) +#define SICR_1_GPIO_D_DDR (2 << (30-16)) +#define SICR_1_GPIO_D_LCS (3 << (30-16)) +#define SICR_1_GPIO_E_GPIO (0 << (30-18)) +#define SICR_1_GPIO_E_CAN (1 << (30-18)) +#define SICR_1_GPIO_E_DDR (2 << (30-18)) +#define SICR_1_GPIO_E_LCS (3 << (30-18)) +#define SICR_1_GPIO_F_GPIO (0 << (30-20)) +#define SICR_1_GPIO_F_CAN (1 << (30-20)) +#define SICR_1_GPIO_F_CK (2 << (30-20)) +#define SICR_1_USB_A_USBDR (0 << (30-22)) +#define SICR_1_USB_A_UART2S (1 << (30-22)) +#define SICR_1_USB_B_USBDR (0 << (30-24)) +#define SICR_1_USB_B_UART2S (1 << (30-24)) +#define SICR_1_USB_B_UART2RTS (2 << (30-24)) +#define SICR_1_USB_C_USBDR (0 << (30-26)) +#define SICR_1_USB_C_QE_EXT (3 << (30-26)) +#define SICR_1_FEC1_FEC1 (0 << (30-28)) +#define SICR_1_FEC1_GTM (1 << (30-28)) +#define SICR_1_FEC1_GPIO (2 << (30-28)) +#define SICR_1_FEC2_FEC2 (0 << (30-30)) +#define SICR_1_FEC2_GTM (1 << (30-30)) +#define SICR_1_FEC2_GPIO (2 << (30-30)) +/* SICR_2 */ +#define SICR_2_FEC3_FEC3 (0 << (30-0)) +#define SICR_2_FEC3_TMR (1 << (30-0)) +#define SICR_2_FEC3_GPIO (2 << (30-0)) +#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2)) +#define SICR_2_HDLC1_A_GPIO (1 << (30-2)) +#define SICR_2_HDLC1_A_TDM1 (2 << (30-2)) +#define SICR_2_ELBC_A_LA (0 << (30-4)) +#define SICR_2_ELBC_B_LCLK (0 << (30-6)) +#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8)) +#define SICR_2_HDLC2_A_GPIO (0 << (30-8)) +#define SICR_2_HDLC2_A_TDM2 (0 << (30-8)) +/* bits 10-11 unused */ +#define SICR_2_USB_D_USBDR (0 << (30-12)) +#define SICR_2_USB_D_GPIO (2 << (30-12)) +#define SICR_2_USB_D_QE_BRG (3 << (30-12)) +#define SICR_2_PCI_PCI (0 << (30-14)) +#define SICR_2_PCI_CPCI_HS (2 << (30-14)) +#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16)) +#define SICR_2_HDLC1_B_GPIO (1 << (30-16)) +#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16)) +#define SICR_2_HDLC1_B_TDM1 (3 << (30-16)) +#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18)) +#define SICR_2_HDLC1_C_GPIO (1 << (30-18)) +#define SICR_2_HDLC1_C_TDM1 (2 << (30-18)) +#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20)) +#define SICR_2_HDLC2_B_GPIO (1 << (30-20)) +#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20)) +#define SICR_2_HDLC2_B_TDM2 (3 << (30-20)) +#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22)) +#define SICR_2_HDLC2_C_GPIO (1 << (30-22)) +#define SICR_2_HDLC2_C_TDM2 (2 << (30-22)) +#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22)) +#define SICR_2_QUIESCE_B (0 << (30-24)) + #endif /* @@ -580,6 +661,63 @@ #define HRCWL_SVCOD_DIV_8 0x10000000 #define HRCWL_SVCOD_DIV_2 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000 +#elif defined(CONFIG_MPC8309) + +#define HRCWL_CEVCOD 0x000000C0 +#define HRCWL_CEVCOD_SHIFT 6 +/* + * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012 + * these are different than with 8360, 832x + */ +#define HRCWL_CE_PLL_VCO_DIV_2 0x00000000 +#define HRCWL_CE_PLL_VCO_DIV_4 0x00000040 +#define HRCWL_CE_PLL_VCO_DIV_8 0x00000080 + +#define HRCWL_CEPDF 0x00000020 +#define HRCWL_CEPDF_SHIFT 5 +#define HRCWL_CE_PLL_DIV_1X1 0x00000000 +#define HRCWL_CE_PLL_DIV_2X1 0x00000020 + +#define HRCWL_CEPMF 0x0000001F +#define HRCWL_CEPMF_SHIFT 0 +#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 +#define HRCWL_CE_TO_PLL_1X2 0x00000002 +#define HRCWL_CE_TO_PLL_1X3 0x00000003 +#define HRCWL_CE_TO_PLL_1X4 0x00000004 +#define HRCWL_CE_TO_PLL_1X5 0x00000005 +#define HRCWL_CE_TO_PLL_1X6 0x00000006 +#define HRCWL_CE_TO_PLL_1X7 0x00000007 +#define HRCWL_CE_TO_PLL_1X8 0x00000008 +#define HRCWL_CE_TO_PLL_1X9 0x00000009 +#define HRCWL_CE_TO_PLL_1X10 0x0000000A +#define HRCWL_CE_TO_PLL_1X11 0x0000000B +#define HRCWL_CE_TO_PLL_1X12 0x0000000C +#define HRCWL_CE_TO_PLL_1X13 0x0000000D +#define HRCWL_CE_TO_PLL_1X14 0x0000000E +#define HRCWL_CE_TO_PLL_1X15 0x0000000F +#define HRCWL_CE_TO_PLL_1X16 0x00000010 +#define HRCWL_CE_TO_PLL_1X17 0x00000011 +#define HRCWL_CE_TO_PLL_1X18 0x00000012 +#define HRCWL_CE_TO_PLL_1X19 0x00000013 +#define HRCWL_CE_TO_PLL_1X20 0x00000014 +#define HRCWL_CE_TO_PLL_1X21 0x00000015 +#define HRCWL_CE_TO_PLL_1X22 0x00000016 +#define HRCWL_CE_TO_PLL_1X23 0x00000017 +#define HRCWL_CE_TO_PLL_1X24 0x00000018 +#define HRCWL_CE_TO_PLL_1X25 0x00000019 +#define HRCWL_CE_TO_PLL_1X26 0x0000001A +#define HRCWL_CE_TO_PLL_1X27 0x0000001B +#define HRCWL_CE_TO_PLL_1X28 0x0000001C +#define HRCWL_CE_TO_PLL_1X29 0x0000001D +#define HRCWL_CE_TO_PLL_1X30 0x0000001E +#define HRCWL_CE_TO_PLL_1X31 0x0000001F + +#define HRCWL_SVCOD 0x30000000 +#define HRCWL_SVCOD_SHIFT 28 +#define HRCWL_SVCOD_DIV_2 0x00000000 +#define HRCWL_SVCOD_DIV_4 0x10000000 +#define HRCWL_SVCOD_DIV_8 0x20000000 +#define HRCWL_SVCOD_DIV_1 0x30000000 #endif /* @@ -940,6 +1078,21 @@ #define SCCR_SATACM_1 0x00000055 #define SCCR_SATACM_2 0x000000aa #define SCCR_SATACM_3 0x000000ff +#elif defined(CONFIG_MPC8309) +/* SCCR bits - MPC8309 specific */ +#define SCCR_SDHCCM 0x0c000000 +#define SCCR_SDHCCM_SHIFT 26 +#define SCCR_SDHCCM_0 0x00000000 +#define SCCR_SDHCCM_1 0x04000000 +#define SCCR_SDHCCM_2 0x08000000 +#define SCCR_SDHCCM_3 0x0c000000 + +#define SCCR_USBDRCM 0x00c00000 +#define SCCR_USBDRCM_SHIFT 22 +#define SCCR_USBDRCM_0 0x00000000 +#define SCCR_USBDRCM_1 0x00400000 +#define SCCR_USBDRCM_2 0x00800000 +#define SCCR_USBDRCM_3 0x00c00000 #endif #define SCCR_PCIEXP1CM 0x00300000 -- cgit v1.1 From 6967840b83d06c7d56fb6ba6322393a9c254c27b Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:09 +0000 Subject: km83xx: add common support for km8309 boards Add support for Keymile boards based on mpc8309 (it would be only kmvect1 for now) Signed-off-by: Gerlando Falauto [#elseif -> #if to allow kmcoge5ne and kmeter1 to build successfully] Signed-off-by: Kim Phillips --- include/configs/km/km8309-common.h | 176 +++++++++++++++++++++++++++++++++++++ include/configs/km/km83xx-common.h | 6 ++ 2 files changed, 182 insertions(+) create mode 100644 include/configs/km/km8309-common.h (limited to 'include') diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h new file mode 100644 index 0000000..b36e892 --- /dev/null +++ b/include/configs/km/km8309-common.h @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2012 Keymile AG + * Gerlando Falauto + * + * Based on km8321-common.h, see respective copyright notice for credits + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_KM8309_COMMON_H +#define __CONFIG_KM8309_COMMON_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC830x 1 /* MPC830x family */ +#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" +#define CONFIG_CMD_DIAG 1 + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +/* at end of uboot partition, before env */ +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000 + +#define CONFIG_MISC_INIT_R + +/* + * System IO Config + */ +/* 0x14000180 SICR_1 */ +#define CONFIG_SYS_SICRL (0 \ + | SICR_1_UART1_UART1RTS \ + | SICR_1_I2C_CKSTOP \ + | SICR_1_IRQ_A_IRQ \ + | SICR_1_IRQ_B_IRQ \ + | SICR_1_GPIO_A_GPIO \ + | SICR_1_GPIO_B_GPIO \ + | SICR_1_GPIO_C_GPIO \ + | SICR_1_GPIO_D_GPIO \ + | SICR_1_GPIO_E_GPIO \ + | SICR_1_GPIO_F_GPIO \ + | SICR_1_USB_A_UART2S \ + | SICR_1_USB_B_UART2RTS \ + | SICR_1_FEC1_FEC1 \ + | SICR_1_FEC2_FEC2 \ + ) + +/* 0x00080400 SICR_2 */ +#define CONFIG_SYS_SICRH (0 \ + | SICR_2_FEC3_FEC3 \ + | SICR_2_HDLC1_A_HDLC1 \ + | SICR_2_ELBC_A_LA \ + | SICR_2_ELBC_B_LCLK \ + | SICR_2_HDLC2_A_HDLC2 \ + | SICR_2_USB_D_GPIO \ + | SICR_2_PCI_PCI \ + | SICR_2_HDLC1_B_HDLC1 \ + | SICR_2_HDLC1_C_HDLC1 \ + | SICR_2_HDLC2_B_GPIO \ + | SICR_2_HDLC2_C_HDLC2 \ + | SICR_2_QUIESCE_B \ + ) + +/* GPR_1 */ +#define CONFIG_SYS_GPR1 0x50008060 + +#define CONFIG_SYS_GP1DIR 0x00000000 +#define CONFIG_SYS_GP1ODR 0x00000000 +#define CONFIG_SYS_GP2DIR 0xFF000000 +#define CONFIG_SYS_GP2ODR 0x00000000 + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_RD_NEVER | \ + CSCONFIG_ODT_WR_ONLY_CURRENT | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_KM8309_COMMON_H */ diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 877d841..a9823d6 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -169,9 +169,15 @@ #define UEC_VERBOSE_DEBUG 1 #ifdef CONFIG_UEC_ETH1 +#if defined(CONFIG_MPC8309) +#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 +#else #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#endif #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -- cgit v1.1 From c4d22de817738e9f1f6a7c34664fc4ac112024a3 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:10 +0000 Subject: km83xx: add kmvect1 board Add support for the new kmvect1 board powered by the mpc8309 processor. As this board is very similar to the existing suvd3, instead of adding a new config header file, just add a new config option to suvd3.h Signed-off-by: Gerlando Falauto Signed-off-by: Kim Phillips --- include/configs/suvd3.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 68680c5..c50832c 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -23,14 +23,23 @@ /* * High Level Configuration Options */ -#define CONFIG_SUVD3 /* SUVD3 board specific */ -#define CONFIG_HOSTNAME suvd3 -#define CONFIG_KM_BOARD_NAME "suvd3" +/* This needs to be set prior to including km/km83xx-common.h */ #define CONFIG_SYS_TEXT_BASE 0xF0000000 +#if defined(CONFIG_SUVD3) /* SUVD3 board specific */ +#define CONFIG_HOSTNAME suvd3 +#define CONFIG_KM_BOARD_NAME "suvd3" /* include common defines/options for all 8321 Keymile boards */ #include "km/km8321-common.h" +#elif defined(CONFIG_KMVECT1) /* VECT1 board specific */ +#define CONFIG_HOSTNAME kmvect1 +#define CONFIG_KM_BOARD_NAME "kmvect1" +/* include common defines/options for all 8309 Keymile boards */ +#include "km/km8309-common.h" +#else +#error Supported boards are: SUVD3, KMVECT1 +#endif #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -- cgit v1.1 From 186fc4db263fc6332d6712be99a9a387087d29c7 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Thu, 18 Oct 2012 19:25:52 +0000 Subject: ColdFire: Add Freescale MCF54418TWR ColdFire development board support Add Freescale MCF54418TWR ColdFire development board support. Signed-off-by: TsiChung Liew Signed-off-by: Jason Jin Signed-off-by: Alison Wang --- include/configs/M54418TWR.h | 448 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 448 insertions(+) create mode 100644 include/configs/M54418TWR.h (limited to 'include') diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h new file mode 100644 index 0000000..6c96111 --- /dev/null +++ b/include/configs/M54418TWR.h @@ -0,0 +1,448 @@ +/* + * Configuation settings for the Freescale MCF54418 TWR board. + * + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M54418TWR_H +#define _M54418TWR_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF5441x /* define processor family */ +#define CONFIG_M54418 /* define processor type */ +#define CONFIG_M54418TWR /* M54418TWR board */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#undef CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_UBI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_NAND_YAFFS +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +/* + * NAND FLASH + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_JFFS2_NAND +#define CONFIG_NAND_FSL_NFC +#define CONFIG_SYS_NAND_BASE 0xFC0FC000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* Network configuration */ +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 +#define CONFIG_MII_INIT 1 +#define CONFIG_SYS_DISCOVER_PHY +#define CONFIG_SYS_RX_ETH_BUFFER 2 +#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN +#define CONFIG_SYS_TX_ETH_BUFFER 2 +#define CONFIG_HAS_ETH1 + +#define CONFIG_SYS_FEC0_PINMUX 0 +#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE +#define CONFIG_SYS_FEC1_PINMUX 0 +#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE +#define MCFFEC_TOUT_LOOP 50000 +#define CONFIG_SYS_FEC0_PHYADDR 0 +#define CONFIG_SYS_FEC1_PHYADDR 1 + +#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ + +#ifdef CONFIG_SYS_NAND_BOOT +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ + "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ + "-(jffs2) console=ttyS0,115200" +#else +#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ + __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ + __stringify(CONFIG_IPADDR) " ip=" \ + __stringify(CONFIG_IPADDR) ":" \ + __stringify(CONFIG_SERVERIP)":" \ + __stringify(CONFIG_GATEWAYIP)": " \ + __stringify(CONFIG_NETMASK) \ + "::eth0:off:rw console=ttyS0,115200" +#endif + +#define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +#define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_IPADDR 192.168.1.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 + +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SYS_FEC_BUF_USE_SRAM +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +#ifndef CONFIG_SYS_DISCOVER_PHY +#define FECDUPLEX FULL +#define FECSPEED _100BASET +#define LINKSTATUS 1 +#else +#define LINKSTATUS 0 +#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#endif +#endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_HOSTNAME M54418TWR + +#if defined(CONFIG_CF_SBF) +/* ST Micro serial flash */ +#define CONFIG_SYS_LOAD_ADDR2 0x40010007 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "sbfhdr=sbfhdr.bin\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${sbfhdr};" \ + "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ + "upd=run load; run prog\0" \ + "prog=sf probe 0:1 1000000 3;" \ + "sf erase 0 40000;" \ + "sf write ${loadaddr} 0 40000;" \ + "save\0" \ + "" +#elif defined(CONFIG_SYS_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${u-boot};\0" \ + "upd=run load; run prog\0" \ + "prog=nand device 0;" \ + "nand erase 0 40000;" \ + "nb_update ${loadaddr} ${filesize};" \ + "save\0" \ + "" +#else +#define CONFIG_SYS_UBOOT_END 0x3FFFF +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off mram" " ;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" +#endif + +/* Realtime clock */ +#undef CONFIG_MCFRTC +#define CONFIG_RTC_MCFRRTC +#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2c */ +#undef CONFIG_FSL_I2C +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +/* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* DSPI and Serial Flash */ +#define CONFIG_CF_SPI +#define CONFIG_CF_DSPI +#define CONFIG_SERIAL_FLASH +#define CONFIG_HARD_SPI +#define CONFIG_SYS_SBFHDR_SIZE 0x7 +#ifdef CONFIG_CMD_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_ATMEL + +# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ + DSPI_CTAR_PCSSCK_1CLK | \ + DSPI_CTAR_PASC(0) | \ + DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | \ + DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(1)) +# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) +# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) +#endif + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 2048 /* 2048 KB */ + +/* HUSH */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_PROMPT "-> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +/* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 256 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) +#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) +#define CONFIG_SYS_DRAM_TEST + +#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) +#define CONFIG_SERIAL_BOOT +#endif + +#if defined(CONFIG_SERIAL_BOOT) +#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) +#else +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_MRAM 1 +#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ +#define CONFIG_ENV_SIZE 0x1000 +#endif + +#if defined(CONFIG_CF_SBF) +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_ENV_SPI_CS 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#endif +#if defined(CONFIG_SYS_NAND_BOOT) +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#endif +#undef CONFIG_ENV_OVERWRITE + +/* FLASH organization */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +#undef CONFIG_SYS_FLASH_CFI +#ifdef CONFIG_SYS_FLASH_CFI + +#define CONFIG_FLASH_CFI_DRIVER 1 +/* Max size that the board might have */ +#define CONFIG_SYS_FLASH_SIZE 0x1000000 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 270 +/* "Real" (hardware) sectors protection */ +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } +#else +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 270 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 0 +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_OFFSET (0x800000) +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nand0=m54418twr.nand" + +#define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ + "7m(kernel)," \ + "-(rootfs)" + +#endif + +#ifdef CONFIG_CMD_UBI +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts command */ +#define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ +#define CONFIG_RBTREE +#define MTDIDS_DEFAULT "nand0=NAND" +#define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ + "-(ubi)" +#endif +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + +#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 12) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash 16MB + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ + + /* Flash */ +#define CONFIG_SYS_CS0_BASE 0x00000000 +#define CONFIG_SYS_CS0_MASK 0x000F0101 +#define CONFIG_SYS_CS0_CTRL 0x00001D60 + +#endif /* _M54418TWR_H */ -- cgit v1.1 From e47c9e8608df6c95b6a324925573bac12045e059 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 16 Oct 2012 04:07:03 +0000 Subject: OMAP3: updated pinmux and environment for new revision of mcx board The mcx board was slightly modified and the pinmux must be updated. There is no need to support the old board, that becomes obsolete. Signed-off-by: Stefano Babic --- include/configs/mcx.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 359522a..d3061a2 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -256,22 +256,24 @@ "run nandargs; " \ "ubi part nand0,4;" \ "ubi readvol ${loadaddr} kernel;" \ - "run addip addtty addmtd addfb addeth addmisc;" \ + "run addtty addmtd addfb addeth addmisc;" \ "bootm ${loadaddr}\0" \ - "swupdate_args=setenv bootargs ubi.mtd=6 root=ubi0:fs_recovery "\ - "rootfstype=ubifs quiet loglevel=1 " \ - "consoleblank=0 ${swupdate_misc}\0" \ + "swupdate_args=setenv bootargs root=/dev/ram " \ + "quiet loglevel=1 " \ + "consoleblank=0 ${swupdate_misc}\0" \ "swupdate=echo Running Sw-Update...;" \ "if printenv mtdparts;then echo Starting SwUpdate...; " \ "else mtdparts default;fi; " \ "ubi part nand0,5;" \ "ubi readvol 0x82000000 kernel_recovery;" \ + "ubi part nand0,6;" \ + "ubi readvol 0x84000000 fs_recovery;" \ "run swupdate_args; " \ "setenv bootargs ${bootargs} " \ "${mtdparts} " \ "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ "omapdss.def_disp=lcd;" \ - "bootm ${loadaddr}\0" + "bootm 0x82000000 0x84000000\0" #define CONFIG_BOOTCOMMAND \ "run nandboot" -- cgit v1.1 From 8c735b990989bcd3909081aff7e6913222ac38e9 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 16 Oct 2012 04:07:04 +0000 Subject: OMAP3: mcx: updated to new hardware revision Some GPIOs differ in the new revision board. Previous revision are considered obsolete and they will not anymore supported. Signed-off-by: Stefano Babic --- include/configs/mcx.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/mcx.h b/include/configs/mcx.h index d3061a2..96e1059 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -115,8 +115,7 @@ #define CONFIG_USB_ULPI #define CONFIG_USB_ULPI_VIEWPORT_OMAP /*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 -#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 /* commands to include */ -- cgit v1.1 From 8f1fae26a7fb4c0c2897f2f086fe8a3e1da58a9a Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sat, 20 Oct 2012 23:56:07 +0000 Subject: OMAP3: add video support to the mcx board Add video support to the board with the display focaltech etm070003dh6. Signed-off-by: Stefano Babic --- include/configs/mcx.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 96e1059..bf49cc1 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -181,7 +181,7 @@ #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ /* Environment information */ -#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" @@ -257,6 +257,10 @@ "ubi readvol ${loadaddr} kernel;" \ "run addtty addmtd addfb addeth addmisc;" \ "bootm ${loadaddr}\0" \ + "preboot=ubi part nand0,7;" \ + "ubi readvol ${loadaddr} splash;" \ + "bmp display ${loadaddr};" \ + "gpio set 55\0" \ "swupdate_args=setenv bootargs root=/dev/ram " \ "quiet loglevel=1 " \ "consoleblank=0 ${swupdate_misc}\0" \ @@ -303,6 +307,7 @@ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ /* address */ +#define CONFIG_PREBOOT /* * AM3517 has 12 GP timers, they can be driven by the system clock @@ -422,4 +427,13 @@ #define CONFIG_NET_RETRY_COUNT 10 #endif +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_OMAP3 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + #endif /* __CONFIG_H */ -- cgit v1.1 From 69916bcf71766d85cc6a7131a1d5716a724a8475 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 16 Oct 2012 13:06:07 +0000 Subject: am33xx: Add SPI SPL as an option Add the required config.mk logic for this SoC as well as the BOOT_DEVICE define. Finally, enable the options on the am335x_evm. Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 9d80739..58d62d0 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -218,6 +218,13 @@ #define CONFIG_SPL_NET_SUPPORT #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" #define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* -- cgit v1.1 From 5e8f98319d8582d6a066610b5f1ec9b1a3f79704 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 17 Oct 2012 06:44:59 +0000 Subject: FAT: implement fat_set_blk_dev(), convert cmd_fat.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the FAT filesystem API more consistent with other block-based filesystems. If in the future standard multi-filesystem commands such as "ls" or "load" are implemented, having FAT work the same way as other filesystems will be necessary. Convert cmd_fat.c to the new API, so the code looks more like other files implementing the same commands for other filesystems. Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau --- include/fat.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fat.h b/include/fat.h index cc85b06..706cd7a 100644 --- a/include/fat.h +++ b/include/fat.h @@ -212,6 +212,7 @@ long file_fat_read_at(const char *filename, unsigned long pos, void *buffer, unsigned long maxsize); long file_fat_read(const char *filename, void *buffer, unsigned long maxsize); const char *file_getfsname(int idx); +int fat_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); int fat_register_device(block_dev_desc_t *dev_desc, int part_no); int file_fat_write(const char *filename, void *buffer, unsigned long maxsize); -- cgit v1.1 From c3f8318f33eb4eb79b3b5c5204a438d499572de0 Mon Sep 17 00:00:00 2001 From: Andrew Bradford Date: Thu, 25 Oct 2012 08:21:32 -0400 Subject: am335x_evm: Enable use of UART{1,2,3,4,5} Add targets of am335x_evm_uart{1,2,3,4,5} to have serial input/output on UART{1,2,3,4,5} for use with the Beaglebone RS232 cape, am335x_evm daughterboard, and other custom configurations. Modify target for am335x_evm to include SERIAL1 and CONS_INDEX=1 options in order to clarify UART selection requirements. Signed-off-by: Andrew Bradford --- include/configs/am335x_evm.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 58d62d0..cdb6697 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -158,9 +158,15 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SERIAL_MULTI #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* I2C Configuration */ #define CONFIG_I2C @@ -182,11 +188,7 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 -#define CONFIG_CONS_INDEX 1 +#define CONFIG_ENV_OVERWRITE 1 #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_ENV_IS_NOWHERE -- cgit v1.1 From 6f62f4207112013852be87dc2b9c7c570eba11c9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 08:54:08 +0000 Subject: arm: Remove support for lpc2292 This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut --- include/flash.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/flash.h b/include/flash.h index 6d70bdd..7db599e 100644 --- a/include/flash.h +++ b/include/flash.h @@ -348,7 +348,6 @@ extern flash_info_t *flash_get_info(ulong base); #define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ -#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */ #define NUMONYX_256MBIT 0x8922 /* Numonyx P33/30 256MBit 65nm */ /*----------------------------------------------------------------------- -- cgit v1.1 From f2e0801565b7106da0f96784389c397794ce3906 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 08:54:11 +0000 Subject: stdio: Remove the CLPS7111 serial driver This driver is no longer used, remove it. Signed-off-by: Marek Vasut --- include/clps7111.h | 276 ----------------------------------------------------- 1 file changed, 276 deletions(-) delete mode 100644 include/clps7111.h (limited to 'include') diff --git a/include/clps7111.h b/include/clps7111.h deleted file mode 100644 index baf6007..0000000 --- a/include/clps7111.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * linux/include/asm-arm/hardware/clps7111.h - * - * This file contains the hardware definitions of the CLPS7111 internal - * registers. - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_HARDWARE_CLPS7111_H -#define __ASM_HARDWARE_CLPS7111_H - -#define CLPS7111_PHYS_BASE (0x80000000) - -#ifndef __ASSEMBLY__ -#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) -#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) -#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) -#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) -#endif - -#define PADR (0x0000) -#define PBDR (0x0001) -#define PDDR (0x0003) -#define PADDR (0x0040) -#define PBDDR (0x0041) -#define PDDDR (0x0043) -#define PEDR (0x0080) -#define PEDDR (0x00c0) -#define SYSCON1 (0x0100) -#define SYSFLG1 (0x0140) -#define MEMCFG1 (0x0180) -#define MEMCFG2 (0x01c0) -#define DRFPR (0x0200) -#define INTSR1 (0x0240) -#define INTMR1 (0x0280) -#define LCDCON (0x02c0) -#define TC1D (0x0300) -#define TC2D (0x0340) -#define RTCDR (0x0380) -#define RTCMR (0x03c0) -#define PMPCON (0x0400) -#define CODR (0x0440) -#define UARTDR1 (0x0480) -#define UBRLCR1 (0x04c0) -#define SYNCIO (0x0500) -#define PALLSW (0x0540) -#define PALMSW (0x0580) -#define STFCLR (0x05c0) -#define BLEOI (0x0600) -#define MCEOI (0x0640) -#define TEOI (0x0680) -#define TC1EOI (0x06c0) -#define TC2EOI (0x0700) -#define RTCEOI (0x0740) -#define UMSEOI (0x0780) -#define COEOI (0x07c0) -#define HALT (0x0800) -#define STDBY (0x0840) - -#define FBADDR (0x1000) -#define SYSCON2 (0x1100) -#define SYSFLG2 (0x1140) -#define INTSR2 (0x1240) -#define INTMR2 (0x1280) -#define UARTDR2 (0x1480) -#define UBRLCR2 (0x14c0) -#define SS2DR (0x1500) -#define SRXEOF (0x1600) -#define SS2POP (0x16c0) -#define KBDEOI (0x1700) - -/* common bits: SYSCON1 / SYSCON2 */ -#define SYSCON_UARTEN (1 << 8) - -#define SYSCON1_KBDSCAN(x) ((x) & 15) -#define SYSCON1_KBDSCANMASK (15) -#define SYSCON1_TC1M (1 << 4) -#define SYSCON1_TC1S (1 << 5) -#define SYSCON1_TC2M (1 << 6) -#define SYSCON1_TC2S (1 << 7) -#define SYSCON1_UART1EN SYSCON_UARTEN -#define SYSCON1_BZTOG (1 << 9) -#define SYSCON1_BZMOD (1 << 10) -#define SYSCON1_DBGEN (1 << 11) -#define SYSCON1_LCDEN (1 << 12) -#define SYSCON1_CDENTX (1 << 13) -#define SYSCON1_CDENRX (1 << 14) -#define SYSCON1_SIREN (1 << 15) -#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) -#define SYSCON1_ADCKSEL_MASK (3 << 16) -#define SYSCON1_EXCKEN (1 << 18) -#define SYSCON1_WAKEDIS (1 << 19) -#define SYSCON1_IRTXM (1 << 20) - -/* common bits: SYSFLG1 / SYSFLG2 */ -#define SYSFLG_UBUSY (1 << 11) -#define SYSFLG_URXFE (1 << 22) -#define SYSFLG_UTXFF (1 << 23) - -#define SYSFLG1_MCDR (1 << 0) -#define SYSFLG1_DCDET (1 << 1) -#define SYSFLG1_WUDR (1 << 2) -#define SYSFLG1_WUON (1 << 3) -#define SYSFLG1_CTS (1 << 8) -#define SYSFLG1_DSR (1 << 9) -#define SYSFLG1_DCD (1 << 10) -#define SYSFLG1_UBUSY SYSFLG_UBUSY -#define SYSFLG1_NBFLG (1 << 12) -#define SYSFLG1_RSTFLG (1 << 13) -#define SYSFLG1_PFFLG (1 << 14) -#define SYSFLG1_CLDFLG (1 << 15) -#define SYSFLG1_URXFE SYSFLG_URXFE -#define SYSFLG1_UTXFF SYSFLG_UTXFF -#define SYSFLG1_CRXFE (1 << 24) -#define SYSFLG1_CTXFF (1 << 25) -#define SYSFLG1_SSIBUSY (1 << 26) -#define SYSFLG1_ID (1 << 29) - -#define SYSFLG2_SSRXOF (1 << 0) -#define SYSFLG2_RESVAL (1 << 1) -#define SYSFLG2_RESFRM (1 << 2) -#define SYSFLG2_SS2RXFE (1 << 3) -#define SYSFLG2_SS2TXFF (1 << 4) -#define SYSFLG2_SS2TXUF (1 << 5) -#define SYSFLG2_CKMODE (1 << 6) -#define SYSFLG2_UBUSY SYSFLG_UBUSY -#define SYSFLG2_URXFE SYSFLG_URXFE -#define SYSFLG2_UTXFF SYSFLG_UTXFF - -#define LCDCON_GSEN (1 << 30) -#define LCDCON_GSMD (1 << 31) - -#define SYSCON2_SERSEL (1 << 0) -#define SYSCON2_KBD6 (1 << 1) -#define SYSCON2_DRAMZ (1 << 2) -#define SYSCON2_KBWEN (1 << 3) -#define SYSCON2_SS2TXEN (1 << 4) -#define SYSCON2_PCCARD1 (1 << 5) -#define SYSCON2_PCCARD2 (1 << 6) -#define SYSCON2_SS2RXEN (1 << 7) -#define SYSCON2_UART2EN SYSCON_UARTEN -#define SYSCON2_SS2MAEN (1 << 9) -#define SYSCON2_OSTB (1 << 12) -#define SYSCON2_CLKENSL (1 << 13) -#define SYSCON2_BUZFREQ (1 << 14) - -/* common bits: UARTDR1 / UARTDR2 */ -#define UARTDR_FRMERR (1 << 8) -#define UARTDR_PARERR (1 << 9) -#define UARTDR_OVERR (1 << 10) - -/* common bits: UBRLCR1 / UBRLCR2 */ -#define UBRLCR_BAUD_MASK ((1 << 12) - 1) -#define UBRLCR_BREAK (1 << 12) -#define UBRLCR_PRTEN (1 << 13) -#define UBRLCR_EVENPRT (1 << 14) -#define UBRLCR_XSTOP (1 << 15) -#define UBRLCR_FIFOEN (1 << 16) -#define UBRLCR_WRDLEN5 (0 << 17) -#define UBRLCR_WRDLEN6 (1 << 17) -#define UBRLCR_WRDLEN7 (2 << 17) -#define UBRLCR_WRDLEN8 (3 << 17) -#define UBRLCR_WRDLEN_MASK (3 << 17) - -#define SYNCIO_SMCKEN (1 << 13) -#define SYNCIO_TXFRMEN (1 << 14) - -#define SYSCON3 0x2200 /* System Control register 3 ----------------------- */ -#define ADCCON 0x00000001 /* ADC configuration */ -#define CLKCTL 0x00000006 /* processor clock control */ -#define CLKCTL_18 0x0 /* 18.432 MHz */ -#define CLKCTL_36 0x2 /* 36.864 MHz */ -#define CLKCTL_49 0x4 /* 49.152 MHz */ -#define CLKCTL_73 0x6 /* 73.728 MHz */ -#define MCPSEL 0x00000008 /* MCP select */ -#define ADCCKNSEN 0x000010 /* ADC clock sense */ -#define VERSN 0x000000e0 /* additional version bits */ -#define VERSN_SHIFT 5 -#define FASTWAKE 0x0000100 /* Wakeup clock select: 0=8Hz, 1=4kHz */ - -#define INTSR3 0x2240 /* Interrupt Status register 3 --------------------- */ -#define MCPINT 0x00000001 /* MCP interface interrupt (FIQ) */ - -#define INTMR3 0x2280 /* Interrupt Mask register 3 ----------------------- */ -#define LEDFLSH 0x22C0 /* LED Flash control register ---------------------- */ -#define LEDFLSH_RATE 0x03 /* flash rate */ -#define LEDFLSH_RATE_SHIFT 0 -#define LEDFLSH_DUTY 0x3c /* duty ratio */ -#define LEDFLSH_DUTY_SHIFT 2 -#define LEDFLSH_ENABLE 0x40 /* enable */ - -#define IO_START CLPS7111_PHYS_BASE - -#define IO(offset) (IO_START + (offset)) - -#define IO_BYTE(offset) (*(volatile unsigned char *)(IO_START + (offset))) -#define IO_WORD(offset) (*(volatile unsigned long *)(IO_START + (offset))) - -#define IO_PADR IO_BYTE(PADR) -#define IO_PBDR IO_BYTE(PBDR) -#define IO_PDDR IO_BYTE(PDDR) -#define IO_PADDR IO_BYTE(PADDR) -#define IO_PBDDR IO_BYTE(PBDDR) -#define IO_PDDDR IO_BYTE(PDDDR) -#define IO_PEDR IO_BYTE(PEDR) -#define IO_PEDDR IO_BYTE(PEDDR) -#define IO_SYSCON IO_WORD(SYSCON) -#define IO_SYSFLG IO_WORD(SYSFLG) -#define IO_MEMCFG1 IO_WORD(MEMCFG1) -#define IO_MEMCFG2 IO_WORD(MEMCFG2) -#define IO_DRFPR IO_WORD(DRFPR) -#define IO_INTSR IO_WORD(INTSR) -#define IO_INTMR IO_WORD(INTMR) -#define IO_LCDCON IO_WORD(LCDCON) -#define IO_TC1D IO_WORD(TC1D) -#define IO_TC2D IO_WORD(TC2D) -#define IO_RTCDR IO_WORD(RTCDR) -#define IO_RTCMR IO_WORD(RTCMR) -#define IO_PMPCON IO_WORD(PMPCON) -#define IO_CODR IO_BYTE(CODR) -#define IO_UARTDR IO_WORD(UARTDR) -#define IO_UBRLCR IO_WORD(UBRLCR) -#define IO_SYNCIO IO_WORD(SYNCIO) -#define IO_PALLSW IO_WORD(PALLSW) -#define IO_PALMSW IO_WORD(PALMSW) -#define IO_STFCLR IO_WORD(STFCLR) -#define IO_BLEOI IO_WORD(BLEOI) -#define IO_MCEOI IO_WORD(MCEOI) -#define IO_TEOI IO_WORD(TEOI) -#define IO_TC1EOI IO_WORD(TC1EOI) -#define IO_TC2EOI IO_WORD(TC2EOI) -#define IO_RTCEOI IO_WORD(RTCEOI) -#define IO_UMSEOI IO_WORD(UMSEOI) -#define IO_COEOI IO_WORD(COEOI) -#define IO_HALT IO_WORD(HALT) -#define IO_STDBY IO_WORD(STDBY) -#define IO_SYSCON1 IO_WORD(SYSCON1) -#define IO_SYSFLG1 IO_WORD(SYSFLG1) -#define IO_INTSR1 IO_WORD(INTSR1) -#define IO_INTMR1 IO_WORD(INTMR1) -#define IO_UARTDR1 IO_WORD(UARTDR1) -#define IO_UBRLCR1 IO_WORD(UBRLCR1) -#define IO_FRBADDR IO_WORD(FRBADDR) -#define IO_SYSCON2 IO_WORD(SYSCON2) -#define IO_SYSFLG2 IO_WORD(SYSFLG2) -#define IO_INTSR2 IO_WORD(INTSR2) -#define IO_INTMR2 IO_WORD(INTMR2) -#define IO_UARTDR2 IO_WORD(UARTDR2) -#define IO_UBRLCR2 IO_WORD(UBRLCR2) -#define IO_KBDEOI IO_WORD(KBDEOI) - -#define IO_MCCR IO_WORD(MCCR) -#define IO_MCDR0 IO_WORD(MCDR0) -#define IO_MCDR1 IO_WORD(MCDR1) -#define IO_MCDR2 IO_WORD(MCDR2) -#define IO_MCSR IO_WORD(MCSR) -#define IO_SYSCON3 IO_WORD(SYSCON3) -#define IO_INTSR3 IO_WORD(INTSR3) -#define IO_INTMR3 IO_WORD(INTMR3) -#define IO_LEDFLSH IO_WORD(LEDFLSH) - -#endif /* __ASM_HARDWARE_CLPS7111_H */ -- cgit v1.1 From 53c41548a9fd7f0595c81c47e1ac3d9671d753e4 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Thu, 18 Oct 2012 10:15:45 +0000 Subject: arm: arm925t: remove SX1 board SX1 does not build properly by itself, is not built as part of MAKEALL arm or MAKEALL -a arm, and is only present in Makefile, not boards.cfg. As it also has no entry in MAINTAINERS, it is orphan and non-functional. Remove it. Signed-off-by: Albert ARIBAUD --- include/configs/SX1.h | 189 -------------------------------------------------- 1 file changed, 189 deletions(-) delete mode 100644 include/configs/SX1.h (limited to 'include') diff --git a/include/configs/SX1.h b/include/configs/SX1.h deleted file mode 100644 index 93d031c..0000000 --- a/include/configs/SX1.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ -#define CONFIG_OMAP_SX1 1 /* a SX1 Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* the SX1 has 12MHz input clock */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SX1 */ - -/* - * USB device configuration - */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 - -#define CONFIG_USBD_VENDORID 0x1234 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Siemens" -#define CONFIG_USBD_PRODUCT_NAME "SX1" - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP1510_I2C - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_I2C - -#undef CONFIG_CMD_NET - - -#include - -#define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw" -#ifdef CONFIG_STDOUT_USBTTY -#define CONFIG_PREBOOT "setenv stdout usbtty;setenv stdin usbtty" -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SX1# " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - * V1 - * PHYS_FLASH_SIZE_1 (16 << 10) 16 MB - * PHYS_FLASH_SIZE_2 (8 << 10) 8 MB - * V2 only 1 flash - * PHYS_FLASH_SIZE_1 (32 << 10) 32 MB - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ -#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, PHYS_FLASH_2 } - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_SIZE_REDUND 0x20000 -#define CONFIG_ENV_OFFSET_REDUND 0x40000 - -#endif /* __CONFIG_H */ -- cgit v1.1 From 1b0757eceddf037aad99ab59217a3a5c215e15d1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 24 Oct 2012 02:36:15 +0000 Subject: PPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM) These boards have long reached EOL, and there has been no indication of any active users of such hardware for years. Get rid of the dead weight. Signed-off-by: Wolfgang Denk Cc: Wolfgang Grandegger --- include/commproc.h | 131 +-------- include/configs/AMX860.h | 299 -------------------- include/configs/ETX094.h | 357 ------------------------ include/configs/IAD210.h | 381 ------------------------- include/configs/LANTEC.h | 358 ------------------------ include/configs/SCM.h | 710 ----------------------------------------------- include/configs/c2mon.h | 417 ---------------------------- include/pcmcia.h | 2 - include/status_led.h | 36 --- 9 files changed, 5 insertions(+), 2686 deletions(-) delete mode 100644 include/configs/AMX860.h delete mode 100644 include/configs/ETX094.h delete mode 100644 include/configs/IAD210.h delete mode 100644 include/configs/LANTEC.h delete mode 100644 include/configs/SCM.h delete mode 100644 include/configs/c2mon.h (limited to 'include') diff --git a/include/commproc.h b/include/commproc.h index 8b8cc45..7ca28c8 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -466,39 +466,6 @@ typedef struct scc_enet { #endif /* MPC860ADS */ -/*** AMX860 **********************************************/ - -#if defined(CONFIG_AMX860) - -/* This ENET stuff is for the AMX860 with ethernet on SCC1. - */ - -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 - -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0400) -#define PA_ENET_RCLK ((ushort)0x0800) - -#define PB_ENET_TENA ((uint)0x00001000) - -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003e) - -/* 68160 PHY control */ - -#define PB_ENET_ETHLOOP ((uint)0x00020000) -#define PB_ENET_TPFLDL ((uint)0x00010000) -#define PB_ENET_TPSQEL ((uint)0x00008000) -#define PD_ENET_ETH_EN ((ushort)0x0004) - -#endif /* CONFIG_AMX860 */ - /*** BSEIP **********************************************************/ #ifdef CONFIG_BSEIP @@ -547,38 +514,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00003400) #endif /* CONFIG_FLAGADM */ -/*** C2MON **********************************************************/ - -#ifdef CONFIG_C2MON - -# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */ -# error "Ethernet on SCC not supported on C2MON Board!" -# else /* Use FEC for Fast Ethernet */ - -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -# endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_C2MON */ - -/*********************************************************************/ - /*** ELPT860 *********************************************************/ #ifdef CONFIG_ELPT860 @@ -828,33 +763,6 @@ typedef struct scc_enet { #endif /* CONFIG_HERMES */ -/*** IAD210 **********************************************************/ - -/* The IAD210 uses the FEC on a MPC860P for Ethernet */ - -#if defined(CONFIG_IAD210) - -# define FEC_ENET /* use FEC for Ethernet */ -# undef SCC_ENET - -# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */ -# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */ -# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */ -# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */ -# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */ -# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */ -# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */ -# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */ -# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */ -# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */ -# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */ -# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */ -# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */ - -# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */ - -#endif /* CONFIG_IAD210 */ - /*** ICU862 **********************************************************/ #if defined(CONFIG_ICU862) @@ -954,34 +862,6 @@ typedef struct scc_enet { #endif /* CONFIG_KUP4K */ - -/*** LANTEC *********************************************************/ - -#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2 -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000FF00) -#define SICR_ENET_CLKRT ((uint)0x00002E00) -#endif /* CONFIG_LANTEC v2 */ - /*** LWMON **********************************************************/ #if defined(CONFIG_LWMON) @@ -1373,15 +1253,14 @@ typedef struct scc_enet { #endif /* CONFIG_SXNI855T */ -/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/ +/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ - defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \ - defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \ - defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \ - defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \ - (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2) + defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \ + defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ + defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \ + defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2) /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h deleted file mode 100644 index e7a6c80..0000000 --- a/include/configs/AMX860.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_AMX860 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#undef CONFIG_8xx_CONS_SMC1 /* Console is on SCC2 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_8xx_CONS_SCC2 1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 5000000 /* 5 MHz in */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" /* autoboot command */ - -#undef CONFIG_BOOTARGS - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * U-Boot for AMX board supports two types of memory extension - * modules: one that provides 4 MB flash memory, and another one with - * 16 MB EDO DRAM. - * - * The flash module swaps the CS0 and CS1 signals: if the module is - * installed, CS0 is connected to Flash on the module and CS1 is - * connected to the on-board Flash. This means that you must intall - * U-Boot when the Flash module is plugged in, if you plan to use - * it. - * - * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT - * must be defined. The DRAM module uses CS1. - * - * Only one of these modules may be installed at a time. If U-Boot - * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not - * work if the Flash extension module is installed instead of the - * DRAM module. - */ -#define CONFIG_AMX_RAM_EXT /* 16Mb Ext. DRAM module support */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - * - * Use 4 MB for without and 8 MB with 16 MB DRAM extension module - * (CONFIG_AMX_RAM_EXT) - */ -#ifdef CONFIG_AMX_RAM_EXT -# define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#else -# define CONFIG_SYS_BOOTMAPSZ (4 << 20) /* Initial Memory map for Linux */ -#endif -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#ifndef CONFIG_AMX_RAM_EXT -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ -#endif - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -/* 0x00000800 0x00000400 0x00000100 0x00000030 0x00000004 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#define CONFIG_SYS_OR0_PRELIM 0xFFC00954 /* Real values for the board */ -#define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */ - -#ifndef CONFIG_AMX_RAM_EXT -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM 0xFFC00954 /* Real values for the board */ -#define CONFIG_SYS_BR1_PRELIM 0x60000001 /* Real values for the board */ -#endif - -/* DSP ("Glue") Xilinx */ -#define CONFIG_SYS_OR6_PRELIM 0xFFFF8000 /* 32kB, 15 waits, cs after addr, no bursts */ -#define CONFIG_SYS_BR6_PRELIM 0x60000401 /* use GPCM for CS generation, 8 bit port */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h deleted file mode 100644 index 2703625..0000000 --- a/include/configs/ETX094.h +++ /dev/null @@ -1,357 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_ETX094 1 /* ...on a ETX_094 board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 57600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */ -#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ -#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */ - -#define CONFIG_ETHADDR 08:00:06:00:00:00 - -#ifdef CONFIG_ETHADDR -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_RAMBOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \ - "U-Boot_version=U-Boot-1.0.x-Date " \ - "panic=1 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#define CONFIG_NFSBOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_FLASH_16BIT -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ -#else -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \ - OR_SCY_2_CLK | OR_TRLX ) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#ifdef CONFIG_FLASH_16BIT /* 16 bit data port */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) -#else /* 32 bit data port */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) -#endif /* CONFIG_FLASH_16BIT */ - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 23 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) - -#endif /* __CONFIG_H */ diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h deleted file mode 100644 index 94b05dc..0000000 --- a/include/configs/IAD210.h +++ /dev/null @@ -1,381 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - - -# ifdef DEBUG -# warning DEBUG Defined -# endif /* DEBUG */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC860 1 -#define CONFIG_IAD210 1 /* ...on a IAD210 module */ -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_SYS_TEXT_BASE 0x08000000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#undef CONFIG_8xx_CONS_SMC1 -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 - - -# define MPC8XX_FACT 16 -# define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if can't use get_gclk_freq */ -# define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 0 -# define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -/* using this define saves us updating another source file */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -#undef CONFIG_BOOTARGS -/* #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -*/ - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs" \ - "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -# define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -# define CONFIG_MII 1 -# define CONFIG_SYS_DISCOVER_PHY 1 -# define CONFIG_FEC_UTOPIA 1 -# define CONFIG_ETHADDR 08:00:06:26:A2:6D -# define CONFIG_IPADDR 192.168.28.128 -# define CONFIG_SERVERIP 139.10.137.138 -# define CONFIG_SYS_DISCOVER_PHY 1 - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -# define CONFIG_SYS_I2C_SPEED 50000 -# define CONFIG_SYS_I2C_SLAVE 0xDD -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if defined(DEBUG) -# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -# define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif - -# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -# define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 - -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 ) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ -#define CONFIG_SYS_RCCR 0x0020 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0xF8000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xF8000000 /* OR addr mask */ - -/* FLASH timing: - TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ - OR_SCY_3_CLK | OR_EHTR) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 124 /* start with divider for 64 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X) - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h deleted file mode 100644 index c3855c3..0000000 --- a/include/configs/LANTEC.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2001 - * Torsten Stevens, FHG IMS, stevens@ims.fhg.de - * Bruno Achauer, Exet AG, bruno@exet-ag.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - * [derived from config_TQM850L.h] - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* - * Port assignments (CONFIG_LANTEC == 1): - * - SMC1: J11 (MDB) ? - * - SMC2: J6 (Feature connector) - * - SCC2: J9 (RJ45) - * - SCC3: J8 (Sub-D9) - * - * Port assignments (CONFIG_LANTEC == 2): TBD - */ - - -#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ -#define CONFIG_8xx_CONS_SCC3 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_XIMG - -#if !(CONFIG_LANTEC >= 2) - #undef CONFIG_CMD_DATE - #undef CONFIG_CMD_NET -#endif - - -#if CONFIG_LANTEC >= 2 -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK) - -/*----------------------------------------------------------------------- - * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX] - *----------------------------------------------------------------------- - */ -#define CONFIG_8xx_GCLK_FREQ 33000000 - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ - /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 - /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/5 and OR0/5 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ - OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR5_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM) - -#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL \ - ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/SCM.h b/include/configs/SCM.h deleted file mode 100644 index 87d52ba..0000000 --- a/include/configs/SCM.h +++ /dev/null @@ -1,710 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ -#define CONFIG_SCM 1 /* ...on a System Controller Module */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#if (CONFIG_TQM8260 <= 100) -# error "TQM8260 module revison not supported" -#endif - -/* We use a TQM8260 module with a 300MHz CPU */ -#define CONFIG_300MHz - -/* Define 60x busmode only if your TQM8260 has L2 cache! */ -#ifdef CONFIG_L2_CACHE -# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */ -#else -# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */ -#endif - -/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */ -#ifdef CONFIG_300MHz -# define CONFIG_BUSMODE_60x -#endif - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK12 - * - Tx-CLK is CLK11 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifndef CONFIG_300MHz -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 83333000 /* in Hz */ -#endif - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_BSP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH1_BASE 0x60000000 -#define CONFIG_SYS_FLASH0_SIZE 32 -#define CONFIG_SYS_FLASH1_SIZE 32 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to EEPROM later */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -/* Final version: environment in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_ENV_OFFSET 0 -#define CONFIG_ENV_SIZE 2048 -#endif - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if defined(CONFIG_266MHz) -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0111) -#elif defined(CONFIG_300MHz) -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0110) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#ifdef CONFIG_BUSMODE_60x -#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ - BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ -#else -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CONFIG_SYS_INIT_LOCAL_SDRAM - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ -#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - - /* SDRAM on TQM8260 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 -#define CONFIG_SYS_LSRT 0x20 -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - -/* Bank 2 - Local bus SDRAM - */ -#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL - -#define SDRAM_BASE2_PRELIM 0x80000000 - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - -#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#define CONFIG_SYS_CAN0_BASE 0xc0000000 -#define CONFIG_SYS_CAN1_BASE 0xc0008000 -#define CONFIG_SYS_FIOX_BASE 0xc0010000 -#define CONFIG_SYS_FDOHM_BASE 0xc0018000 -#define CONFIG_SYS_EXTPROM_BASE 0xc2000000 - -#define CONFIG_SYS_CAN_SIZE 0x00000100 -#define CONFIG_SYS_FIOX_SIZE 0x00000020 -#define CONFIG_SYS_FDOHM_SIZE 0x00002000 -#define CONFIG_SYS_EXTPROM_BANK_SIZE 0x01000000 - -#define EXT_EEPROM_MAX_FLASH_BANKS 0x02 - -/* CS3 - CAN 0 - */ -#define CONFIG_SYS_CAN0_BR3 ((CONFIG_SYS_CAN0_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMA |\ - BRx_V) - -#define CONFIG_SYS_CAN0_OR3 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_4IDLE) - -/* CS4 - CAN 1 - */ -#define CONFIG_SYS_CAN1_BR4 ((CONFIG_SYS_CAN1_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMA |\ - BRx_V) - -#define CONFIG_SYS_CAN1_OR4 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_4IDLE) - -/* CS5 - Extended PROM (16MB optional) - */ -#define CONFIG_SYS_EXTPROM_BR5 ((CONFIG_SYS_EXTPROM_BASE & BRx_BA_MSK)|\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_EXTPROM_OR5 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -/* CS6 - Extended PROM (16MB optional) - */ -#define CONFIG_SYS_EXTPROM_BR6 (((CONFIG_SYS_EXTPROM_BASE + \ - CONFIG_SYS_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_EXTPROM_OR6 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -/* CS7 - FPGA FIOX: Glue Logic - */ -#define CONFIG_SYS_FIOX_BR7 ((CONFIG_SYS_FIOX_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_FIOX_OR7 (P2SZ_TO_AM(CONFIG_SYS_FIOX_SIZE) |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -/* CS8 - FPGA DOH Master - */ -#define CONFIG_SYS_FDOHM_BR8 ((CONFIG_SYS_FDOHM_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_FDOHM_OR8 (P2SZ_TO_AM(CONFIG_SYS_FDOHM_SIZE) |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - - -/* FPGA configuration */ -#define CONFIG_SYS_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */ -#define CONFIG_SYS_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */ -#define CONFIG_SYS_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */ - -#define CONFIG_SYS_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */ -#define CONFIG_SYS_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */ -#define CONFIG_SYS_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h deleted file mode 100644 index 41ff008..0000000 --- a/include/configs/c2mon.h +++ /dev/null @@ -1,417 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_C2MON 1 /* ...on a C2MON module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_FEC_ENET 1 /* Use Fast Ethernet Controller */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CONFIG_SYS_PLPRCR \ - ( (5-1)< Date: Thu, 25 Oct 2012 15:27:37 +0800 Subject: ColdFire: Remove save env in NAND support for M54418TWR board. This patch remove the env saving in NAND as so far the NAND driver is not ported to the M54418TWR platform. Signed-off-by: Jason Jin --- include/configs/M54418TWR.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 6c96111..3be2f8e 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -350,7 +350,7 @@ #endif #if defined(CONFIG_SYS_NAND_BOOT) #define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_OFFSET 0x80000 #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 -- cgit v1.1 From 6bbda88384948808dd4050624a6c27d6d63265a1 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sun, 7 Oct 2012 11:36:06 +0000 Subject: tegra: add Colibri T20 board support This adds board support for the Toradex Colibri T20 module. Working functions: - SD card boot - USB boot - Network - NAND environment Signed-off-by: Lucas Stach Signed-off-by: Tom Warren --- include/configs/colibri_t20_iris.h | 83 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 include/configs/colibri_t20_iris.h (limited to 'include') diff --git a/include/configs/colibri_t20_iris.h b/include/configs/colibri_t20_iris.h new file mode 100644 index 0000000..0e5f281 --- /dev/null +++ b/include/configs/colibri_t20_iris.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2012 Lucas Stach + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* Enable FDT support */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra20-colibri_t20_iris +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra20 (Colibri) # " +#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20 on Iris" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_TEGRA_UARTA_SDIO1 +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* SD/MMC support */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* File system support */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* USB host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING + +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_2M) +#undef CONFIG_ENV_SIZE /* undef size from tegra20-common.h */ +#define CONFIG_ENV_SIZE (SZ_64K) + +/* Debug commands */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CACHE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ -- cgit v1.1 From 7f1b767aea949d954e75fa635968a9d315d2e7ff Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 20 Sep 2012 09:29:03 +0000 Subject: ARM: tegra: define CONFIG_SYS_BOOTMAPSZ This define indicates the size of the memory region where it is safe to place data passed to the Linux kernel (ATAGs, DTB, initrd). The value needs to be: a) Less than or equal to RAM size. b) Small enough that the area is not within the kernel's highmem region, since the kernel cannot access ATAGs/DTB/initrd from highmem. c) Large enough to hold the kernel+DTB+initrd. 256M seems large enough for (c) in most circumstances, and small enough to satisfy (a) and (b) across any possible Tegra board. Note that the user can override this value via environment variable "bootm_mapsize" if needed. The advantage of defining BOOTMAPSZ is that we no longer need to define variable fdt_high in the default environment. Previously, we defined this to prevent the DTB from being relocated to the very end of RAM, which on most Tegra systems is within highmem, and hence which would cause boot failures. A user can still define this variable themselves if they want the FDT to be either left in-place wherever loaded, or copied to some other specific location. Similarly, there should no longer be a strict requirement for the user to define initrd_high if using an initrd. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/tegra-common-post.h | 1 - include/configs/tegra20-common.h | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 9698c23..5d1d3dd 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -143,7 +143,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ "fdt_load=0x01000000\0" \ - "fdt_high=01100000\0" \ BOOTCMDS_COMMON /* overrides for SPL build here */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index dc7444d..70c5cfb 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -171,6 +171,8 @@ #define CONFIG_SYS_TEXT_BASE 0x0010c000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ + #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ -- cgit v1.1 From 938176a48274361c0b86b237ff6c0953a08233b3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 2 Oct 2012 09:26:51 +0000 Subject: ARM: tegra: use standard variables to define load addresses Currently, Tegra's default environment uses non-standard variables to define where boot scripts should load the kernel, FDT, and initrd. This change both changes the variable names to match those described in U-Boot's README, and shuffles their values around a little so that the values make a little more sense; see comments in the patch for rationale behind the values chosen. Note that this patch does remove the old non-standard variable "fdt_load" from the default environment, so this patch requires people to change their boot scripts. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra-common-post.h | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 5d1d3dd..6835155 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -95,8 +95,6 @@ #endif #define BOOTCMDS_COMMON \ - "scriptaddr=0x400000\0" \ - \ "rootpart=1\0" \ \ "script_boot=" \ @@ -140,9 +138,36 @@ #endif +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x10000000\0" \ + "kernel_addr_r=0x01000000\0" \ + "fdt_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ - "fdt_load=0x01000000\0" \ + MEM_LAYOUT_ENV_SETTINGS \ BOOTCMDS_COMMON /* overrides for SPL build here */ -- cgit v1.1 From 699c40e8789cfbb5c3ca4ef2849a4bd051ff79bb Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 12 Oct 2012 09:45:48 +0000 Subject: ARM: tegra: Harmony: enable ULPI USB port The ULPI port is routed onto pins on the mini PCI Express connector. A standard breakout board may be used to access the port. * Add required DT entries to configure the ULPI port. * Setup up the ULPI pinmux in the board code. * Enable multiple USB controller and ULPI support in the board config. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/harmony.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/harmony.h b/include/configs/harmony.h index d582ae1..040bfe4 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -72,8 +72,11 @@ #define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */ /* USB Host support */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB -- cgit v1.1 From e73c7cdd1ea152f35f6cf2bc850362cd859f36b6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 12 Oct 2012 09:45:49 +0000 Subject: ARM: tegra: Seaboard: enable multiple USB ports The device tree already contains the required configuration for both the USB1 and USB3 ports. Enable the required configuration options to enable both these ports, which in turn allows the USB1 port to be used. Note that on a true Seaboard, this port is typically used as a device port hosting Tegra's USB recovery protocol. However, on the Springbank derivative, this port is the only external USB port, so we enable it as a host port so that USB peripherals may be used. Enabling this port in U-Boot as a host port doesn't prevent the port from reverting to a device port when the CPU is reset into recovery mode. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/seaboard.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 0727a4c..74d3b94 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -81,6 +81,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA #define CONFIG_USB_STORAGE -- cgit v1.1 From a833b95039a08cd52980f95564b567c8b3138cfe Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sun, 7 Oct 2012 11:29:38 +0000 Subject: tegra: nand: make ONFI detection work Add the missing bits to the Tegra NAND driver to make ONFI detection work properly. Also add it to the Tegra default config, as it seems to be a reasonable thing to have it available on all boards that use any kind of NAND. Signed-off-by: Lucas Stach Acked-by: Scott Wood Signed-off-by: Tom Warren --- include/configs/tegra20-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 70c5cfb..272c46e 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -200,5 +200,6 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" #define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION #endif /* __TEGRA20_COMMON_H */ -- cgit v1.1 From 644a69ec85a73b4d24c3a7b0369da76e2c336bce Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:19:34 +0000 Subject: ARM: tegra: derive CONFIG_SPL_MAX_SIZE instead of hard-coding it For Tegra, the SPL and main U-Boot are concatenated together to form a single memory image. Hence, the maximum SPL size is the different in TEXT_BASE for SPL and main U-Boot. Instead of manually calculating SPL_MAX_SIZE based on those two TEXT_BASE, which can lead to errors if one TEXT_BASE is changed without updating SPL_MAX_SIZE, simply perform the calculation automatically. Signed-off-by: Stephen Warren Acked-by: Simon Glass Acked-by: Allen Martin Tested-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra20-common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 272c46e..5b048e0 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -188,7 +188,8 @@ #define CONFIG_SPL #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x00108000 -#define CONFIG_SPL_MAX_SIZE 0x00004000 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SPL_TEXT_BASE) #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 #define CONFIG_SPL_STACK 0x000ffffc -- cgit v1.1 From b2f9893826c48f2653d4a1ffaff8623fdec22303 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 19 Oct 2012 21:08:23 +0000 Subject: tegra: move to common SPL framework Change tegra SPL to use common SPL framework. Any tegra specific initialization is now done in spl_board_init() instead of board_init_f()/board_init_r(). Only one SPL boot target is supported on tegra, which is boot to RAM image. jump_to_image_no_args() must be overridden on tegra so the host CPU can be initialized. Signed-off-by: Allen Martin Acked-by: Stephen Warren Tested-by: Stephen Warren Tested-by: Lucas Stach Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra20-common.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 5b048e0..15bd9bb 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -169,6 +169,7 @@ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_TEXT_BASE 0x0010c000 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ @@ -186,6 +187,9 @@ /* Defines for SPL */ #define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x00108000 #define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \ -- cgit v1.1 From 03e2ecf6b83e43803f7eed9547d0973b7eb1c8fc Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:43:50 +0000 Subject: fs: separate CONFIG_FS_{FAT, EXT4} from CONFIG_CMD_{FAT, EXT*} MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the FAT and ext4 filesystem implementations build if CONFIG_FS_{FAT,EXT4} are defined, rather than basing the build on whether CONFIG_CMD_{FAT,EXT*} are defined. This will allow the filesystems to be built separately from the filesystem-specific commands that use them. This paves the way for the creation of filesystem-generic commands that used the filesystems, without requiring the filesystem- specific commands. Minor documentation changes are made for this change. The new config options are automatically selected by the old config options to retain backwards-compatibility. Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau --- include/config_fallbacks.h | 13 +++++++++++++ include/ext4fs.h | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 430890c..bfb9680 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -13,4 +13,17 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif +#if defined(CONFIG_CMD_FAT) && !defined(CONFIG_FS_FAT) +#define CONFIG_FS_FAT +#endif + +#if (defined(CONFIG_CMD_EXT4) || defined(CONFIG_CMD_EXT2)) && \ + !defined(CONFIG_FS_EXT4) +#define CONFIG_FS_EXT4 +#endif + +#if defined(CONFIG_CMD_EXT4_WRITE) && !defined(CONFIG_EXT4_WRITE) +#define CONFIG_EXT4_WRITE +#endif + #endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/ext4fs.h b/include/ext4fs.h index 23298fc..3b59d15 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -116,7 +116,7 @@ struct ext_filesystem { extern struct ext2_data *ext4fs_root; extern struct ext2fs_node *ext4fs_file; -#if defined(CONFIG_CMD_EXT4_WRITE) +#if defined(CONFIG_EXT4_WRITE) extern struct ext2_inode *g_parent_inode; extern int gd_index; extern int gindex; -- cgit v1.1 From 045fa1e1142552799ad3203e9e0bc22a11e866ea Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:43:51 +0000 Subject: fs: add filesystem switch libary, implement ls and fsload commands Implement "ls" and "fsload" commands that act like {fat,ext2}{ls,load}, and transparently handle either file-system. This scheme could easily be extended to other filesystem types; I only didn't do it for zfs because I don't have any filesystems of that type to test with. Replace the implementation of {fat,ext[24]}{ls,load} with this new code too. Signed-off-by: Stephen Warren --- include/ext_common.h | 3 --- include/fs.h | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 3 deletions(-) create mode 100644 include/fs.h (limited to 'include') diff --git a/include/ext_common.h b/include/ext_common.h index ce73857..86373a6 100644 --- a/include/ext_common.h +++ b/include/ext_common.h @@ -195,7 +195,4 @@ int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc, int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); -int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]); -int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); #endif diff --git a/include/fs.h b/include/fs.h new file mode 100644 index 0000000..f396d84 --- /dev/null +++ b/include/fs.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef _FS_H +#define _FS_H + +#include + +#define FS_TYPE_ANY 0 +#define FS_TYPE_FAT 1 +#define FS_TYPE_EXT 2 + +/* + * Tell the fs layer which block device an partition to use for future + * commands. This also internally identifies the filesystem that is present + * within the partition. The identification process may be limited to a + * specific filesystem type by passing FS_* in the fstype parameter. + * + * Returns 0 on success. + * Returns non-zero if there is an error accessing the disk or partition, or + * no known filesystem type could be recognized on it. + */ +int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype); + +/* + * Print the list of files on the partition previously set by fs_set_blk_dev(), + * in directory "dirname". + * + * Returns 0 on success. Returns non-zero on error. + */ +int fs_ls(const char *dirname); + +/* + * Read file "filename" from the partition previously set by fs_set_blk_dev(), + * to address "addr", starting at byte offset "offset", and reading "len" + * bytes. "offset" may be 0 to read from the start of the file. "len" may be + * 0 to read the entire file. Note that not all filesystem types support + * either/both offset!=0 or len!=0. + * + * Returns number of bytes read on success. Returns <= 0 on error. + */ +int fs_read(const char *filename, ulong addr, int offset, int len); + +/* + * Common implementation for various filesystem commands, optionally limited + * to a specific filesystem type via the fstype parameter. + */ +int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype); +int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype); + +#endif /* _FS_H */ -- cgit v1.1 From 318e70e2447d2706b27e7d3b66a6dbc54ec01e7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 19 Oct 2012 02:00:06 +0000 Subject: Add power bus message definitions in twl4030.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Code copied from linux kernel 3.0.0 from file include/linux/i2c/twl.h * commit 6523b148b44be38d89c2ee9865d34da30d9f5f1c Signed-off-by: Pali Rohár --- include/twl4030.h | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) (limited to 'include') diff --git a/include/twl4030.h b/include/twl4030.h index 9cd32ab..0c17f59 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -151,6 +151,103 @@ #define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1) #define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0) +/* Power bus message definitions */ + +/* The TWL4030/5030 splits its power-management resources (the various + * regulators, clock and reset lines) into 3 processor groups - P1, P2 and + * P3. These groups can then be configured to transition between sleep, wait-on + * and active states by sending messages to the power bus. See Section 5.4.2 + * Power Resources of TWL4030 TRM + */ + +/* Processor groups */ +#define DEV_GRP_NULL 0x0 +#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ +#define DEV_GRP_P2 0x2 /* P2: all Modem devices */ +#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ + +/* Resource groups */ +#define RES_GRP_RES 0x0 /* Reserved */ +#define RES_GRP_PP 0x1 /* Power providers */ +#define RES_GRP_RC 0x2 /* Reset and control */ +#define RES_GRP_PP_RC 0x3 +#define RES_GRP_PR 0x4 /* Power references */ +#define RES_GRP_PP_PR 0x5 +#define RES_GRP_RC_PR 0x6 +#define RES_GRP_ALL 0x7 /* All resource groups */ + +#define RES_TYPE2_R0 0x0 + +#define RES_TYPE_ALL 0x7 + +/* Resource states */ +#define RES_STATE_WRST 0xF +#define RES_STATE_ACTIVE 0xE +#define RES_STATE_SLEEP 0x8 +#define RES_STATE_OFF 0x0 + +/* Power resources */ + +/* Power providers */ +#define RES_VAUX1 1 +#define RES_VAUX2 2 +#define RES_VAUX3 3 +#define RES_VAUX4 4 +#define RES_VMMC1 5 +#define RES_VMMC2 6 +#define RES_VPLL1 7 +#define RES_VPLL2 8 +#define RES_VSIM 9 +#define RES_VDAC 10 +#define RES_VINTANA1 11 +#define RES_VINTANA2 12 +#define RES_VINTDIG 13 +#define RES_VIO 14 +#define RES_VDD1 15 +#define RES_VDD2 16 +#define RES_VUSB_1V5 17 +#define RES_VUSB_1V8 18 +#define RES_VUSB_3V1 19 +#define RES_VUSBCP 20 +#define RES_REGEN 21 +/* Reset and control */ +#define RES_NRES_PWRON 22 +#define RES_CLKEN 23 +#define RES_SYSEN 24 +#define RES_HFCLKOUT 25 +#define RES_32KCLKOUT 26 +#define RES_RESET 27 +/* Power Reference */ +#define RES_Main_Ref 28 + +#define TOTAL_RESOURCES 28 +/* + * Power Bus Message Format ... these can be sent individually by Linux, + * but are usually part of downloaded scripts that are run when various + * power events are triggered. + * + * Broadcast Message (16 Bits): + * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] + * RES_STATE[3:0] + * + * Singular Message (16 Bits): + * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] + */ + +#define MSG_BROADCAST(devgrp, grp, type, type2, state) \ + ((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \ + | (type) << 4 | (state)) + +#define MSG_SINGULAR(devgrp, id, state) \ + ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) + +#define MSG_BROADCAST_ALL(devgrp, state) \ + ((devgrp) << 5 | (state)) + +#define MSG_BROADCAST_REF MSG_BROADCAST_ALL +#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL +#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL + /* Power Managment Receiver */ #define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B #define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C @@ -311,6 +408,7 @@ #define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03 #define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02 #define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03 +#define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03 /* Device Selection in PM Receiver Module */ #define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20 -- cgit v1.1 From ed407be53e1e8f0be90d5723ca71ab1c37e2eed8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 29 Oct 2012 07:54:01 +0000 Subject: New board support: Nokia RX-51 aka N900 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on previous work by: Alistair Buxton Signed-off-by: Pali Rohár Cc: Ивайло Димитров --- include/configs/nokia_rx51.h | 452 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 452 insertions(+) create mode 100644 include/configs/nokia_rx51.h (limited to 'include') diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h new file mode 100644 index 0000000..8506604 --- /dev/null +++ b/include/configs/nokia_rx51.h @@ -0,0 +1,452 @@ +/* + * (C) Copyright 2011-2012 + * Pali Rohár + * + * (C) Copyright 2010 + * Alistair Buxton + * + * Derived from Beagle Board code: + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff + * Syed Mohammed Khasim + * + * Configuration settings for the Nokia RX-51 aka N900. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3430 /* which is in a 3430 */ +#define CONFIG_OMAP3_RX51 /* working with RX51 */ +#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ + +#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 + +/* + * Nokia X-Loader loading secondary image to address 0x80400000 + * NOLO loading boot image to random place, so it doesn't really + * matter what we set this to. We have to copy u-boot to this address + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include /* get chip and board defs */ +#include +#include +#include + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R +#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */ + +#define CONFIG_CMDLINE_TAG /* enable passing kernel command line string */ +#define CONFIG_INITRD_TAG /* enable passing initrd */ +#define CONFIG_REVISION_TAG /* enable passing revision tag*/ +#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_UBI_SIZE (512 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \ + (128 << 10)) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 on RX-51 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* USB */ +#define CONFIG_MUSB_UDC +#define CONFIG_MUSB_HDC +#define CONFIG_USB_OMAP3 +#define CONFIG_TWL4030_USB + +/* USB device configuration */ +#define CONFIG_USB_DEVICE +#define CONFIG_USBD_VENDORID 0x0421 +#define CONFIG_USBD_PRODUCTID 0x01c8 +#define CONFIG_USBD_MANUFACTURER "Nokia" +#define CONFIG_USBD_PRODUCT_NAME "N900" + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_NO_FLASH + +/* commands to include */ +#include + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_EXT4 /* EXT4 Support */ +#define CONFIG_CMD_FAT /* FAT support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_GPIO /* Enable gpio command */ + +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ + +#define CONFIG_CMD_CLEAR /* ANSI terminal clear screen command */ + +#ifdef ONENAND_SUPPORT + +#define CONFIG_CMD_ONENAND /* ONENAND support */ +#define CONFIG_CMD_MTDPARTS /* mtd parts support */ + +#ifdef UBIFS_SUPPORT +#define CONFIG_CMD_UBI /* UBI Support */ +#define CONFIG_CMD_UBIFS /* UBIFS Support */ +#endif + +#endif + +/* commands not needed from config_cmd_default.h */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ +#undef CONFIG_CMD_SAVEENV /* saveenv */ +#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ + +#define CONFIG_OMAP3_SPI +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_DRIVER_OMAP34XX_I2C + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED +#define CONFIG_TWL4030_KEYPAD + +#define CONFIG_OMAP_GPIO +#define GPIO_SLIDE 71 + +/* + * Board ONENAND Info. + */ + +#define PART1_NAME "bootloader" +#define PART1_SIZE 128 +#define PART1_MULL 1024 +#define PART1_SUFF "k" +#define PART1_OFFS 0x00000000 +#define PART1_MASK 0x00000003 + +#define PART2_NAME "config" +#define PART2_SIZE 384 +#define PART2_MULL 1024 +#define PART2_SUFF "k" +#define PART2_OFFS 0x00020000 +#define PART2_MASK 0x00000000 + +#define PART3_NAME "log" +#define PART3_SIZE 256 +#define PART3_MULL 1024 +#define PART3_SUFF "k" +#define PART3_OFFS 0x00080000 +#define PART3_MASK 0x00000000 + +#define PART4_NAME "kernel" +#define PART4_SIZE 2 +#define PART4_MULL 1024*1024 +#define PART4_SUFF "m" +#define PART4_OFFS 0x000c0000 +#define PART4_MASK 0x00000000 + +#define PART5_NAME "initfs" +#define PART5_SIZE 2 +#define PART5_MULL 1024*1024 +#define PART5_SUFF "m" +#define PART5_OFFS 0x002c0000 +#define PART5_MASK 0x00000000 + +#define PART6_NAME "rootfs" +#define PART6_SIZE 257280 +#define PART6_MULL 1024 +#define PART6_SUFF "k" +#define PART6_OFFS 0x004c0000 +#define PART6_MASK 0x00000000 + +#ifdef ONENAND_SUPPORT + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +#ifdef UBIFS_SUPPORT +#define CONFIG_RBTREE +#define CONFIG_LZO +#endif + +#define MTDIDS_DEFAULT "onenand0=onenand" +#define MTDPARTS_DEFAULT "mtdparts=onenand:" \ + __stringify(PART1_SIZE) PART1_SUFF "(" PART1_NAME ")ro," \ + __stringify(PART2_SIZE) PART2_SUFF "(" PART2_NAME ")," \ + __stringify(PART3_SIZE) PART3_SUFF "(" PART3_NAME ")," \ + __stringify(PART4_SIZE) PART4_SUFF "(" PART4_NAME ")," \ + __stringify(PART5_SIZE) PART5_SUFF "(" PART5_NAME ")," \ + "-(" PART6_NAME ")" + +#endif + +/* Watchdog support */ +#define CONFIG_HW_WATCHDOG + +/* + * Framebuffer + */ +/* Video console */ +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_CFB_CONSOLE_ANSI /* Enable ANSI escape codes in framebuffer */ +#define CONFIG_VIDEO_LOGO +#define VIDEO_FB_16BPP_PIXEL_SWAP +#define VIDEO_FB_16BPP_WORD_SWAP +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN + +/* functions for cfb_console */ +#define VIDEO_KBD_INIT_FCT rx51_kp_init() +#define VIDEO_TSTC_FCT rx51_kp_tstc +#define VIDEO_GETC_FCT rx51_kp_getc +#ifndef __ASSEMBLY__ +int rx51_kp_init(void); +int rx51_kp_tstc(void); +int rx51_kp_getc(void); +#endif + +#ifndef MTDPARTS_DEFAULT +#define MTDPARTS_DEFAULT +#endif + +/* Environment information */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "usbtty=cdc_acm\0" \ + "stdin=vga\0" \ + "stdout=vga\0" \ + "stderr=vga\0" \ + "setcon=setenv stdin ${con};" \ + "setenv stdout ${con};" \ + "setenv stderr ${con}\0" \ + "sercon=setenv con serial; run setcon\0" \ + "usbcon=setenv con usbtty; run setcon\0" \ + "vgacon=setenv con vga; run setcon\0" \ + "slide=gpio input " __stringify(GPIO_SLIDE) "\0" \ + "switchmmc=mmc dev ${mmcnum}\0" \ + "kernaddr=0x82008000\0" \ + "initrdaddr=0x84008000\0" \ + "scriptaddr=0x86008000\0" \ + "fileload=${mmctype}load mmc ${mmcnum}:${mmcpart} " \ + "${loadaddr} ${mmcfile}\0" \ + "kernload=setenv loadaddr ${kernaddr};" \ + "setenv mmcfile ${mmckernfile};" \ + "run fileload\0" \ + "initrdload=setenv loadaddr ${initrdaddr};" \ + "setenv mmcfile ${mmcinitrdfile};" \ + "run fileload\0" \ + "scriptload=setenv loadaddr ${scriptaddr};" \ + "setenv mmcfile ${mmcscriptfile};" \ + "run fileload\0" \ + "scriptboot=echo Running ${mmcscriptfile} from mmc " \ + "${mmcnum}:${mmcpart} ...; source ${scriptaddr}\0" \ + "kernboot=echo Booting ${mmckernfile} from mmc " \ + "${mmcnum}:${mmcpart} ...; bootm ${kernaddr}\0" \ + "kerninitrdboot=echo Booting ${mmckernfile} ${mmcinitrdfile} from mmc "\ + "${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr}\0" \ + "attachboot=echo Booting attached kernel image ...;" \ + "setenv setup_omap_atag 1;" \ + "bootm ${attkernaddr};" \ + "setenv setup_omap_atag\0" \ + "trymmcscriptboot=if run switchmmc; then " \ + "if run scriptload; then " \ + "run scriptboot;" \ + "fi;" \ + "fi\0" \ + "trymmckernboot=if run switchmmc; then " \ + "if run kernload; then " \ + "run kernboot;" \ + "fi;" \ + "fi\0" \ + "trymmckerninitrdboot=if run switchmmc; then " \ + "if run initrdload; then " \ + "if run kernload; then " \ + "run kerninitrdboot;" \ + "fi;" \ + "fi; " \ + "fi\0" \ + "trymmcpartboot=setenv mmcscriptfile boot.scr; run trymmcscriptboot;" \ + "setenv mmckernfile uImage; run trymmckernboot\0" \ + "trymmcallpartboot=setenv mmcpart 1; run trymmcpartboot;" \ + "setenv mmcpart 2; run trymmcpartboot;" \ + "setenv mmcpart 3; run trymmcpartboot;" \ + "setenv mmcpart 4; run trymmcpartboot\0" \ + "trymmcboot=if run switchmmc; then " \ + "setenv mmctype fat;" \ + "run trymmcallpartboot;" \ + "setenv mmctype ext2;" \ + "run trymmcallpartboot;" \ + "setenv mmctype ext4;" \ + "run trymmcallpartboot;" \ + "fi\0" \ + "emmcboot=setenv mmcnum 1; run trymmcboot\0" \ + "sdboot=setenv mmcnum 0; run trymmcboot\0" \ + "" + +#define CONFIG_PREBOOT \ + "if run slide; then true; else run attachboot; fi;" \ + "echo Extra commands:;" \ + "echo run sercon - Use serial port for control.;" \ + "echo run usbcon - Use usbtty for control.;" \ + "echo run vgacon - Use framebuffer/keyboard.;" \ + "echo run sdboot - Boot from SD card slot.;" \ + "echo run emmcboot - Boot internal eMMC memory.;" \ + "echo run attachboot - Boot attached kernel image.;" \ + "echo" + +#define CONFIG_BOOTCOMMAND \ + "run sdboot;" \ + "run emmcboot;" \ + "run attachboot;" \ + "echo" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "Nokia RX-51 # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)/*31MB*/ + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 + +/* + * FLASH and environment organization + */ + +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * Attached kernel image + */ + +#define SDRAM_SIZE 0x10000000 /* 256 MB */ +#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE) + +#define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */ +#define KERNEL_OFFSET 0x40000 /* 256 kB */ +#define KERNEL_MAXSIZE (IMAGE_MAXSIZE-KERNEL_OFFSET) +#define KERNEL_ADDRESS (SDRAM_END-KERNEL_MAXSIZE) + +/* Reserve protected RAM for attached kernel */ +#define CONFIG_PRAM ((KERNEL_MAXSIZE >> 10)+1) + +#endif /* __CONFIG_H */ -- cgit v1.1 From 843a7ee8c4b1e47fae41268d6b95306f7e6408f5 Mon Sep 17 00:00:00 2001 From: Raphael Assenat Date: Mon, 22 Oct 2012 05:23:46 +0000 Subject: eco5pk: Add new board and default config Signed-off-by: Raphael Assenat [trini: Squash boards.cfg / MAINTAINERS change into main patch] Signed-off-by: Tom Rini --- include/configs/eco5pk.h | 81 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 include/configs/eco5pk.h (limited to 'include') diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h new file mode 100644 index 0000000..b9ebf6a --- /dev/null +++ b/include/configs/eco5pk.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2012 8D Technologies inc. + * Based on mt_ventoux.h, original banner below: + * + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2009 TechNexion Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tam3517-common.h" + +#undef CONFIG_USB_EHCI +#undef CONFIG_USB_EHCI_OMAP +#undef CONFIG_USB_OMAP3 +#undef CONFIG_CMD_USB + +/* Our console port is port3 */ +#undef CONFIG_CONS_INDEX +#undef CONFIG_SYS_NS16550_COM1 +#undef CONFIG_SERIAL1 + +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 + +#define MACH_TYPE_ECO5_PK 4017 +#define CONFIG_MACH_TYPE MACH_TYPE_ECO5_PK + +#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "ECO5-PK # " +#define CONFIG_SYS_PROMPT V_PROMPT + +/* + * Set its own mtdparts, different from common + */ +#undef MTDIDS_DEFAULT +#undef MTDPARTS_DEFAULT +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(xloader-nand)," \ + "1024k(uboot-nand),256k(params-nand)," \ + "5120k(kernel),-(ubifs)" + +/* + * The arithmetic in tam3517.h is wrong for us and the kernel gets overwritten. + */ +#undef CONFIG_ENV_OFFSET_REDUND +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_SYS_ENV_SECT_SIZE) + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \ + "install_kernel=if dhcp $bootfile; then nand erase kernel;" \ + "nand write $fileaddr kernel; fi\0" \ + "mtdparts="MTDPARTS_DEFAULT"\0" \ + "serverip=192.168.142.60\0" + + +#endif /* __CONFIG_H */ -- cgit v1.1 From 60607c9de01afb53cb284cede3481d0167fc9df0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Wed, 17 Oct 2012 00:00:48 +0000 Subject: avr32: allow multi block mmc access for all boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 1db7377a70a8d931c32648e717695133120d5456 fixes the gen_atmel_mci driver to be able to use multi block access for avr32. Therefore remove the setting which forces single block access. This also adds a huge performace gain for mmc access: ---8<--- Loading file "/boot/uImage" from mmc device 0:1 1830666 bytes read in 1293 ms (1.3 MiB/s) --->8--- vs. ---8<--- Loading file "/boot/uImage" from mmc device 0:1 1830666 bytes read in 237 ms (7.4 MiB/s) --->8--- Signed-off-by: Andreas Bießmann Cc: haavard.skinnemoen@atmel.com Cc: hans-christian.egtvedt@atmel.com Cc: mpfj@mimc.co.uk Cc: alex.raimondi@miromico.ch Cc: julien.may@miromico.ch Cc: egtvedt@samfundet.no Cc: havard@skinnemoen.net --- include/configs/atngw100.h | 1 - include/configs/atngw100mkii.h | 1 - include/configs/atstk1002.h | 1 - include/configs/atstk1003.h | 1 - include/configs/atstk1004.h | 1 - include/configs/atstk1006.h | 1 - include/configs/favr-32-ezkit.h | 1 - include/configs/hammerhead.h | 1 - include/configs/mimc200.h | 1 - 9 files changed, 9 deletions(-) (limited to 'include') diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 5e3155d..6bd1397 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -130,7 +130,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_ATMEL_SPI #define CONFIG_SPI_FLASH diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index f85374f..998cb97 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -154,7 +154,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_ATMEL_SPI #define CONFIG_SPI_FLASH diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index bb426f1..c6b129a 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -153,7 +153,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index 817d943..67ff39b 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -137,7 +137,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index 5134b7f..a1d593b 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -137,7 +137,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index 29fdd12..280ecbc 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -153,7 +153,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h index 71d2473..1c8da9f 100644 --- a/include/configs/favr-32-ezkit.h +++ b/include/configs/favr-32-ezkit.h @@ -152,7 +152,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h index 532feb2..5570bdb 100644 --- a/include/configs/hammerhead.h +++ b/include/configs/hammerhead.h @@ -126,7 +126,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index d5797cb..8031a05 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -131,7 +131,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #if defined(CONFIG_LCD) #define CONFIG_CMD_BMP -- cgit v1.1 From 418b7f3aff3bf4c508b2a57ffc6dc7ca10f811aa Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 31 Oct 2012 11:17:28 +0000 Subject: Add board_name to CONFIG_ENV_VARS_UBOOT_CONFIG CONFIG_ENV_VARS_UBOOT_CONFIG creates environment variables indicating which configuration U-Boot was built for. Some U-Boot binaries run on multiple boards, and hence this information may not uniquley describe the HW that U-Boot is actually running on. Another patch introduces environment variable board_name to represent that. In order to avoid scripts having to check $board_name, use it if set, and then fall back to using $board, make CONFIG_ENV_VARS_UBOOT_CONFIG also set a default value for board_name, so that variable is always available. Signed-off-by: Stephen Warren Acked-by: Joe Hershberger --- include/env_default.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/env_default.h b/include/env_default.h index 375e5ca..a1db73a 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -118,6 +118,7 @@ const uchar default_environment[] = { "arch=" CONFIG_SYS_ARCH "\0" "cpu=" CONFIG_SYS_CPU "\0" "board=" CONFIG_SYS_BOARD "\0" + "board_name=" CONFIG_SYS_BOARD "\0" #ifdef CONFIG_SYS_VENDOR "vendor=" CONFIG_SYS_VENDOR "\0" #endif -- cgit v1.1 From 044fc14bcbcd2a344a2e63c083852fb4af82b96d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 24 Oct 2012 07:28:17 +0000 Subject: am335x_evm: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support We add CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and CONFIG_BOARD_LATE_INIT to set the variables and then fdtfile and findfdt to make us of this. It is now possible to do 'run findfdt' to have fdtfile be set to the value of the dtb file to load for the board we are running on. Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 58d62d0..6e9aada 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -29,6 +29,7 @@ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_NO_FLASH #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM @@ -46,11 +47,14 @@ /* set to negative value for no autoboot */ #define CONFIG_BOOTDELAY 1 +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x80F80000\0" \ "rdaddr=0x81000000\0" \ "bootfile=/boot/uImage\0" \ + "fdtfile=\0" \ "console=ttyO0,115200n8\0" \ "optargs=\0" \ "mmcdev=0\0" \ @@ -79,6 +83,13 @@ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ "bootm ${loadaddr}\0" \ + "findfdt="\ + "if test $board_name = A335BONE; then " \ + "setenv fdtfile am335x-bone.dtb; fi; " \ + "if test $board_name = A33515BB; then " \ + "setenv fdtfile am335x-evm.dtb; fi; " \ + "if test $board_name = A335X_SK; then " \ + "setenv fdtfile am335x-evmsk.dtb; fi\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ -- cgit v1.1 From c4fa493d3a822757af8fbcdc516e12bb7f72d071 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 Oct 2012 05:23:47 +0000 Subject: Support setenv_ulong() and setenv_addr() for powerpc This includes were outside an #ifdef CONFIG_PPC, but there is not reason to exclude powerpc from using them. Move the declaration outside the #ifdef. Signed-off-by: Simon Glass --- include/common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index b23e90b..12b3e03 100644 --- a/include/common.h +++ b/include/common.h @@ -345,9 +345,9 @@ int saveenv (void); int inline setenv (const char *, const char *); #else int setenv (const char *, const char *); +#endif /* CONFIG_PPC */ int setenv_ulong(const char *varname, ulong value); int setenv_addr(const char *varname, const void *addr); -#endif /* CONFIG_PPC */ #ifdef CONFIG_ARM # include # include -- cgit v1.1 From 447c031ba4b6b306bb3f77690af06f5d2ad0691b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 29 Oct 2012 05:23:48 +0000 Subject: scsi: Add function and env var to report number of scsi drives Add a new function to find out the number of available SCSI disks. Also set the 'scsidevs' environment variable after each scan. Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- include/scsi.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/scsi.h b/include/scsi.h index 89ae45f..9681d19 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -189,6 +189,8 @@ void scsi_low_level_init(int busdevfunc); void scsi_init(void); void scsi_scan(int mode); +/** @return the number of scsi disks */ +int scsi_get_disk_count(void); #define SCSI_IDENTIFY 0xC0 /* not used */ -- cgit v1.1 From 4e422bce8a51749ff3c67eec2c8caa6377cc35ee Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 29 Oct 2012 05:23:51 +0000 Subject: ahci: cosmetics and cleanup - print the correct speed - print all the AHCI capability flags (information taken from Linux kernel driver) - clean up some comments For example, this might show the following string: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode Signed-off-by: Stefan Reinauer Commit-Ready: Stefan Reinauer Signed-off-by: Simon Glass Tested-by: Stefan Reinauer --- include/ahci.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/ahci.h b/include/ahci.h index c4fb9e7..babbdc6 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -51,6 +51,7 @@ #define HOST_IRQ_STAT 0x08 /* interrupt status */ #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ +#define HOST_CAP2 0x24 /* host capabilities, extended */ /* HOST_CTL bits */ #define HOST_RESET (1 << 0) /* reset controller; self-clear */ -- cgit v1.1 From 19d1d41e844ea8525f527fd5301aba9eb3006241 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 29 Oct 2012 05:23:54 +0000 Subject: ahci: Make the AHCI code find the capacity of disks > 128 GB properly In the structure returned by the ATA identify device command, there are two fields which describe the device capacity. One is a 32 bit data type which reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data type which is for a 48 bit LBA. If the device doesn't support 48 bit LBAs, the small value is the only value with the correct size. If it supports more, if the number of sectors is small enough to fit into 28 bits, both fields reflect the correct value. If it's too large, the smaller field has 28 bits of 1s, 0xfffffff, and the other field has the correct value. The AHCI driver is implemented by attaching to the generic SCSI code and translating on the fly between SCSI binary data structures and AHCI data structures. It responds to requests to execute specific SCSI commands by executing the equivalent AHCI commands and then crafting a response which matches what a SCSI disk would send. The AHCI driver now considers both fields and chooses the correct one when implementing both the SCSI READ CAPACITY (10) and READ CAPACITY (16) commands. Signed-off-by: Gabe Black Signed-off-by: Simon Glass --- include/scsi.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/scsi.h b/include/scsi.h index 9681d19..9da764b 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -150,6 +150,8 @@ typedef struct SCSI_cmd_block{ #define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */ #define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */ #define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */ +#define SCSI_RD_CAPAC10 SCSI_RD_CAPAC /* Read Capacity (10) */ +#define SCSI_RD_CAPAC16 0x9e /* Read Capacity (16) */ #define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */ #define SCSI_READ_LONG 0x3E /* Read Long (O) */ #define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */ -- cgit v1.1 From 766b16fe180087d8c59a79a4f6a92d1a500fa524 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 29 Oct 2012 05:24:02 +0000 Subject: ahci: Perform SATA flush after disk write. Writes in u-boot are so rare, and the logic to know when is the last write and do a flush only there is sufficiently difficult. Just do a flush after every write. This incurs, usually, one extra flush when the rare writes do happen. Signed-off-by: Marc Jones Signed-off-by: Simon Glass --- include/ata.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/ata.h b/include/ata.h index 3b2d737..a614724 100644 --- a/include/ata.h +++ b/include/ata.h @@ -114,6 +114,9 @@ #define ATA_CMD_WRITE_EXT 0x34 /* Write Sectores (with retries) with 48bit addressing */ #define ATA_CMD_VRFY_EXT 0x42 /* Read Verify (with retries) with 48bit addressing */ +#define ATA_CMD_FLUSH 0xE7 /* Flush drive cache */ +#define ATA_CMD_FLUSH_EXT 0xEA /* Flush drive cache, with 48bit addressing */ + /* * ATAPI Commands */ -- cgit v1.1 From 51bdad67cb6738c5d0e78084cf3e3baa216f4d2f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 Oct 2012 05:24:05 +0000 Subject: x86: config: Enable AHCI support for coreboot Enable AHCI driver for Intel SATA devices. Signed-off-by: Simon Glass --- include/configs/coreboot.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include') diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 3df085b..cc95e2b 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -45,6 +45,28 @@ #undef CONFIG_WATCHDOG #undef CONFIG_HW_WATCHDOG +/* SATA AHCI storage */ + +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SYS_64BIT_LBA +#define CONFIG_SATA_INTEL 1 +#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + /*----------------------------------------------------------------------- * Real Time Clock Configuration */ -- cgit v1.1 From cc69cc002714422cbb551e3d6ebf7e2723c0c6de Mon Sep 17 00:00:00 2001 From: "Jens Scharsig (BuS Elektronik)" Date: Thu, 18 Oct 2012 21:41:10 +0000 Subject: arm: atmel: cpux9k2: add missing cache configs * add CONFIG_SYS_CACHELINE_SIZE to eb_cpux9k2 board config header * dissable dcache (CONFIG_SYS_DCACHE_OFF) for eb_cpux9k2 Signed-off-by: Jens Scharsig (BuS Elektronik) --- include/configs/eb_cpux9k2.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index 9371ec3..3be4929 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -43,6 +43,10 @@ #define MACH_TYPE_EB_CPUX9K2 1977 #define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2 + +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_DCACHE_OFF + /*--------------------------------------------------------------------------*/ #ifndef CONFIG_RAMBOOT #define CONFIG_SYS_TEXT_BASE 0x00000000 @@ -56,7 +60,6 @@ #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1 #define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */ - #define CONFIG_BOOT_RETRY_TIME 30 #define CONFIG_CMDLINE_EDITING -- cgit v1.1 From 3f83c87ee58d86e9a9d2e50b62f38c728bfb31f6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 30 Oct 2012 12:04:19 +0000 Subject: fs: fix number base behaviour change in fatload/ext*load MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 045fa1e "fs: add filesystem switch libary, implement ls and fsload commands" unified the implementation of fatload and ext*load with the new command fsload. However, this altered the interpretation of command-line numbers from always being base-16, to requiring a "0x" prefix for base-16 numbers. Enhance do_fsload() to allow commands to specify which base to use. Use base 0, thus requiring a "0x" prefix for the new fsload command. This feels much cleaner than assuming base 16. Use base 16 for the pre-existing fatload and ext*load to prevent a change in behaviour. Use base 16 exclusively for the loadaddr environment variable, since that variable is interpreted in multiple places, so we don't want the behaviour to change. Update command help text to make it clear where numbers are assumed to be hex, and where an explicit "0x" prefix is required. Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau --- include/fs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/fs.h b/include/fs.h index f396d84..c3ac7cc 100644 --- a/include/fs.h +++ b/include/fs.h @@ -58,7 +58,7 @@ int fs_read(const char *filename, ulong addr, int offset, int len); * to a specific filesystem type via the fstype parameter. */ int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - int fstype); + int fstype, int cmdline_base); int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); -- cgit v1.1 From f9b55e22856a97523074f3dc40ea5d196298756a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 31 Oct 2012 11:05:07 +0000 Subject: fs: rename fsload command to load When the generic filesystem load command "fsload" was written, I felt that "load" was too generic of a name for it, since many other similar commands already existed. However, it turns out that there is already an "fsload" command, so that name cannot be used. Rename the new "fsload" to plain "load" to avoid the conflict. At least anyone who's used a Basic interpreter should feel familiar with the name! Signed-off-by: Stephen Warren --- include/fs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/fs.h b/include/fs.h index c3ac7cc..4f30a38 100644 --- a/include/fs.h +++ b/include/fs.h @@ -57,7 +57,7 @@ int fs_read(const char *filename, ulong addr, int offset, int len); * Common implementation for various filesystem commands, optionally limited * to a specific filesystem type via the fstype parameter. */ -int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], +int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype, int cmdline_base); int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); -- cgit v1.1 From eef1cf2d5cf1cae5fb76713e912263dedf110aeb Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:23 +0000 Subject: include/linux/byteorder: import latest endian definitions from linux u-boot's byteorder headers did not contain endianness attributions for use with sparse, causing a lot of false positives. Import the kernel's latest definitions, and enable them by including compiler.h and types.h. They come with 'const' added for some swab functions, so fix those up, too: include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default] Also, note: u-boot's historic __BYTE_ORDER definition has been preserved (for the time being at least). We also remove ad-hoc barrier() definitions, since we're including compiler.h in files that hadn't in the past: macb.c:54:0: warning: "barrier" redefined [enabled by default] In addition, including compiler.h in byteorder changes the 'noinline' definition to expand to __attribute__((noinline)). This fixes arch/powerpc/lib/bootm.c: bootm.c:329:16: error: attribute '__attribute__': unknown attribute bootm.c:329:16: error: expected ')' before '__attribute__' bootm.c:329:25: error: expected identifier or '(' before ')' token powerpc sparse builds yield: include/common.h:356:22: error: marked inline, but without a definition the unknown-reason inlining without a definition is considered obsolete given it was part of the 2002 initial commit, and no arm version was 'fixed.' also fixed: ydirectenv.h:60:0: warning: "inline" redefined [enabled by default] and: Configuring for devconcenter - Board: intip, Options: DEVCONCENTER make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1 make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2 powerpc-fsl-linux-size: './u-boot': No such file 4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration': include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available 4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here and: In file included from crc32.c:50:0: crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration] crc32table.h:4:1: error: initializer element is not constant crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]') Signed-off-by: Kim Phillips [trini: Remove '#endif' in include/common.h around setenv portion] Signed-off-by: Tom Rini --- include/common.h | 4 - include/linux/byteorder/big_endian.h | 135 +++++++++++++++++++++----------- include/linux/byteorder/little_endian.h | 133 ++++++++++++++++++++----------- include/linux/byteorder/swab.h | 6 +- 4 files changed, 178 insertions(+), 100 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 12b3e03..5e3c5ee 100644 --- a/include/common.h +++ b/include/common.h @@ -341,11 +341,7 @@ char *getenv (const char *); int getenv_f (const char *name, char *buf, unsigned len); ulong getenv_ulong(const char *name, int base, ulong default_val); int saveenv (void); -#ifdef CONFIG_PPC /* ARM version to be fixed! */ -int inline setenv (const char *, const char *); -#else int setenv (const char *, const char *); -#endif /* CONFIG_PPC */ int setenv_ulong(const char *varname, ulong value); int setenv_addr(const char *varname, const void *addr); #ifdef CONFIG_ARM diff --git a/include/linux/byteorder/big_endian.h b/include/linux/byteorder/big_endian.h index 19b0c86..aaf7757 100644 --- a/include/linux/byteorder/big_endian.h +++ b/include/linux/byteorder/big_endian.h @@ -7,63 +7,104 @@ #ifndef __BIG_ENDIAN_BITFIELD #define __BIG_ENDIAN_BITFIELD #endif -#define __BYTE_ORDER __BIG_ENDIAN +#define __BYTE_ORDER __BIG_ENDIAN +#include +#include #include -#define __constant_htonl(x) ((__u32)(x)) -#define __constant_ntohl(x) ((__u32)(x)) -#define __constant_htons(x) ((__u16)(x)) -#define __constant_ntohs(x) ((__u16)(x)) -#define __constant_cpu_to_le64(x) ___swab64((x)) -#define __constant_le64_to_cpu(x) ___swab64((x)) -#define __constant_cpu_to_le32(x) ___swab32((x)) -#define __constant_le32_to_cpu(x) ___swab32((x)) -#define __constant_cpu_to_le16(x) ___swab16((x)) -#define __constant_le16_to_cpu(x) ___swab16((x)) -#define __constant_cpu_to_be64(x) ((__u64)(x)) -#define __constant_be64_to_cpu(x) ((__u64)(x)) -#define __constant_cpu_to_be32(x) ((__u32)(x)) -#define __constant_be32_to_cpu(x) ((__u32)(x)) -#define __constant_cpu_to_be16(x) ((__u16)(x)) -#define __constant_be16_to_cpu(x) ((__u16)(x)) -#define __cpu_to_le64(x) __swab64((x)) -#define __le64_to_cpu(x) __swab64((x)) -#define __cpu_to_le32(x) __swab32((x)) -#define __le32_to_cpu(x) __swab32((x)) -#define __cpu_to_le16(x) __swab16((x)) -#define __le16_to_cpu(x) __swab16((x)) -#define __cpu_to_be64(x) ((__u64)(x)) -#define __be64_to_cpu(x) ((__u64)(x)) -#define __cpu_to_be32(x) ((__u32)(x)) -#define __be32_to_cpu(x) ((__u32)(x)) -#define __cpu_to_be16(x) ((__u16)(x)) -#define __be16_to_cpu(x) ((__u16)(x)) -#define __cpu_to_le64p(x) __swab64p((x)) -#define __le64_to_cpup(x) __swab64p((x)) -#define __cpu_to_le32p(x) __swab32p((x)) -#define __le32_to_cpup(x) __swab32p((x)) -#define __cpu_to_le16p(x) __swab16p((x)) -#define __le16_to_cpup(x) __swab16p((x)) -#define __cpu_to_be64p(x) (*(__u64*)(x)) -#define __be64_to_cpup(x) (*(__u64*)(x)) -#define __cpu_to_be32p(x) (*(__u32*)(x)) -#define __be32_to_cpup(x) (*(__u32*)(x)) -#define __cpu_to_be16p(x) (*(__u16*)(x)) -#define __be16_to_cpup(x) (*(__u16*)(x)) +#define __constant_htonl(x) ((__force __be32)(__u32)(x)) +#define __constant_ntohl(x) ((__force __u32)(__be32)(x)) +#define __constant_htons(x) ((__force __be16)(__u16)(x)) +#define __constant_ntohs(x) ((__force __u16)(__be16)(x)) +#define __constant_cpu_to_le64(x) ((__force __le64)___constant_swab64((x))) +#define __constant_le64_to_cpu(x) ___constant_swab64((__force __u64)(__le64)(x)) +#define __constant_cpu_to_le32(x) ((__force __le32)___constant_swab32((x))) +#define __constant_le32_to_cpu(x) ___constant_swab32((__force __u32)(__le32)(x)) +#define __constant_cpu_to_le16(x) ((__force __le16)___constant_swab16((x))) +#define __constant_le16_to_cpu(x) ___constant_swab16((__force __u16)(__le16)(x)) +#define __constant_cpu_to_be64(x) ((__force __be64)(__u64)(x)) +#define __constant_be64_to_cpu(x) ((__force __u64)(__be64)(x)) +#define __constant_cpu_to_be32(x) ((__force __be32)(__u32)(x)) +#define __constant_be32_to_cpu(x) ((__force __u32)(__be32)(x)) +#define __constant_cpu_to_be16(x) ((__force __be16)(__u16)(x)) +#define __constant_be16_to_cpu(x) ((__force __u16)(__be16)(x)) +#define __cpu_to_le64(x) ((__force __le64)__swab64((x))) +#define __le64_to_cpu(x) __swab64((__force __u64)(__le64)(x)) +#define __cpu_to_le32(x) ((__force __le32)__swab32((x))) +#define __le32_to_cpu(x) __swab32((__force __u32)(__le32)(x)) +#define __cpu_to_le16(x) ((__force __le16)__swab16((x))) +#define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x)) +#define __cpu_to_be64(x) ((__force __be64)(__u64)(x)) +#define __be64_to_cpu(x) ((__force __u64)(__be64)(x)) +#define __cpu_to_be32(x) ((__force __be32)(__u32)(x)) +#define __be32_to_cpu(x) ((__force __u32)(__be32)(x)) +#define __cpu_to_be16(x) ((__force __be16)(__u16)(x)) +#define __be16_to_cpu(x) ((__force __u16)(__be16)(x)) + +static inline __le64 __cpu_to_le64p(const __u64 *p) +{ + return (__force __le64)__swab64p(p); +} +static inline __u64 __le64_to_cpup(const __le64 *p) +{ + return __swab64p((__u64 *)p); +} +static inline __le32 __cpu_to_le32p(const __u32 *p) +{ + return (__force __le32)__swab32p(p); +} +static inline __u32 __le32_to_cpup(const __le32 *p) +{ + return __swab32p((__u32 *)p); +} +static inline __le16 __cpu_to_le16p(const __u16 *p) +{ + return (__force __le16)__swab16p(p); +} +static inline __u16 __le16_to_cpup(const __le16 *p) +{ + return __swab16p((__u16 *)p); +} +static inline __be64 __cpu_to_be64p(const __u64 *p) +{ + return (__force __be64)*p; +} +static inline __u64 __be64_to_cpup(const __be64 *p) +{ + return (__force __u64)*p; +} +static inline __be32 __cpu_to_be32p(const __u32 *p) +{ + return (__force __be32)*p; +} +static inline __u32 __be32_to_cpup(const __be32 *p) +{ + return (__force __u32)*p; +} +static inline __be16 __cpu_to_be16p(const __u16 *p) +{ + return (__force __be16)*p; +} +static inline __u16 __be16_to_cpup(const __be16 *p) +{ + return (__force __u16)*p; +} #define __cpu_to_le64s(x) __swab64s((x)) #define __le64_to_cpus(x) __swab64s((x)) #define __cpu_to_le32s(x) __swab32s((x)) #define __le32_to_cpus(x) __swab32s((x)) #define __cpu_to_le16s(x) __swab16s((x)) #define __le16_to_cpus(x) __swab16s((x)) -#define __cpu_to_be64s(x) do {} while (0) -#define __be64_to_cpus(x) do {} while (0) -#define __cpu_to_be32s(x) do {} while (0) -#define __be32_to_cpus(x) do {} while (0) -#define __cpu_to_be16s(x) do {} while (0) -#define __be16_to_cpus(x) do {} while (0) +#define __cpu_to_be64s(x) do { (void)(x); } while (0) +#define __be64_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_be32s(x) do { (void)(x); } while (0) +#define __be32_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_be16s(x) do { (void)(x); } while (0) +#define __be16_to_cpus(x) do { (void)(x); } while (0) +#ifdef __KERNEL__ #include +#endif #endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ diff --git a/include/linux/byteorder/little_endian.h b/include/linux/byteorder/little_endian.h index a46f3ec..a4cb3bf 100644 --- a/include/linux/byteorder/little_endian.h +++ b/include/linux/byteorder/little_endian.h @@ -9,54 +9,93 @@ #endif #define __BYTE_ORDER __LITTLE_ENDIAN +#include +#include #include -#define __constant_htonl(x) ___constant_swab32((x)) -#define __constant_ntohl(x) ___constant_swab32((x)) -#define __constant_htons(x) ___constant_swab16((x)) -#define __constant_ntohs(x) ___constant_swab16((x)) -#define __constant_cpu_to_le64(x) ((__u64)(x)) -#define __constant_le64_to_cpu(x) ((__u64)(x)) -#define __constant_cpu_to_le32(x) ((__u32)(x)) -#define __constant_le32_to_cpu(x) ((__u32)(x)) -#define __constant_cpu_to_le16(x) ((__u16)(x)) -#define __constant_le16_to_cpu(x) ((__u16)(x)) -#define __constant_cpu_to_be64(x) ___constant_swab64((x)) -#define __constant_be64_to_cpu(x) ___constant_swab64((x)) -#define __constant_cpu_to_be32(x) ___constant_swab32((x)) -#define __constant_be32_to_cpu(x) ___constant_swab32((x)) -#define __constant_cpu_to_be16(x) ___constant_swab16((x)) -#define __constant_be16_to_cpu(x) ___constant_swab16((x)) -#define __cpu_to_le64(x) ((__u64)(x)) -#define __le64_to_cpu(x) ((__u64)(x)) -#define __cpu_to_le32(x) ((__u32)(x)) -#define __le32_to_cpu(x) ((__u32)(x)) -#define __cpu_to_le16(x) ((__u16)(x)) -#define __le16_to_cpu(x) ((__u16)(x)) -#define __cpu_to_be64(x) __swab64((x)) -#define __be64_to_cpu(x) __swab64((x)) -#define __cpu_to_be32(x) __swab32((x)) -#define __be32_to_cpu(x) __swab32((x)) -#define __cpu_to_be16(x) __swab16((x)) -#define __be16_to_cpu(x) __swab16((x)) -#define __cpu_to_le64p(x) (*(__u64*)(x)) -#define __le64_to_cpup(x) (*(__u64*)(x)) -#define __cpu_to_le32p(x) (*(__u32*)(x)) -#define __le32_to_cpup(x) (*(__u32*)(x)) -#define __cpu_to_le16p(x) (*(__u16*)(x)) -#define __le16_to_cpup(x) (*(__u16*)(x)) -#define __cpu_to_be64p(x) __swab64p((x)) -#define __be64_to_cpup(x) __swab64p((x)) -#define __cpu_to_be32p(x) __swab32p((x)) -#define __be32_to_cpup(x) __swab32p((x)) -#define __cpu_to_be16p(x) __swab16p((x)) -#define __be16_to_cpup(x) __swab16p((x)) -#define __cpu_to_le64s(x) do {} while (0) -#define __le64_to_cpus(x) do {} while (0) -#define __cpu_to_le32s(x) do {} while (0) -#define __le32_to_cpus(x) do {} while (0) -#define __cpu_to_le16s(x) do {} while (0) -#define __le16_to_cpus(x) do {} while (0) +#define __constant_htonl(x) ((__force __be32)___constant_swab32((x))) +#define __constant_ntohl(x) ___constant_swab32((__force __be32)(x)) +#define __constant_htons(x) ((__force __be16)___constant_swab16((x))) +#define __constant_ntohs(x) ___constant_swab16((__force __be16)(x)) +#define __constant_cpu_to_le64(x) ((__force __le64)(__u64)(x)) +#define __constant_le64_to_cpu(x) ((__force __u64)(__le64)(x)) +#define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x)) +#define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x)) +#define __constant_cpu_to_le16(x) ((__force __le16)(__u16)(x)) +#define __constant_le16_to_cpu(x) ((__force __u16)(__le16)(x)) +#define __constant_cpu_to_be64(x) ((__force __be64)___constant_swab64((x))) +#define __constant_be64_to_cpu(x) ___constant_swab64((__force __u64)(__be64)(x)) +#define __constant_cpu_to_be32(x) ((__force __be32)___constant_swab32((x))) +#define __constant_be32_to_cpu(x) ___constant_swab32((__force __u32)(__be32)(x)) +#define __constant_cpu_to_be16(x) ((__force __be16)___constant_swab16((x))) +#define __constant_be16_to_cpu(x) ___constant_swab16((__force __u16)(__be16)(x)) +#define __cpu_to_le64(x) ((__force __le64)(__u64)(x)) +#define __le64_to_cpu(x) ((__force __u64)(__le64)(x)) +#define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) +#define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) +#define __cpu_to_le16(x) ((__force __le16)(__u16)(x)) +#define __le16_to_cpu(x) ((__force __u16)(__le16)(x)) +#define __cpu_to_be64(x) ((__force __be64)__swab64((x))) +#define __be64_to_cpu(x) __swab64((__force __u64)(__be64)(x)) +#define __cpu_to_be32(x) ((__force __be32)__swab32((x))) +#define __be32_to_cpu(x) __swab32((__force __u32)(__be32)(x)) +#define __cpu_to_be16(x) ((__force __be16)__swab16((x))) +#define __be16_to_cpu(x) __swab16((__force __u16)(__be16)(x)) + +static inline __le64 __cpu_to_le64p(const __u64 *p) +{ + return (__force __le64)*p; +} +static inline __u64 __le64_to_cpup(const __le64 *p) +{ + return (__force __u64)*p; +} +static inline __le32 __cpu_to_le32p(const __u32 *p) +{ + return (__force __le32)*p; +} +static inline __u32 __le32_to_cpup(const __le32 *p) +{ + return (__force __u32)*p; +} +static inline __le16 __cpu_to_le16p(const __u16 *p) +{ + return (__force __le16)*p; +} +static inline __u16 __le16_to_cpup(const __le16 *p) +{ + return (__force __u16)*p; +} +static inline __be64 __cpu_to_be64p(const __u64 *p) +{ + return (__force __be64)__swab64p(p); +} +static inline __u64 __be64_to_cpup(const __be64 *p) +{ + return __swab64p((__u64 *)p); +} +static inline __be32 __cpu_to_be32p(const __u32 *p) +{ + return (__force __be32)__swab32p(p); +} +static inline __u32 __be32_to_cpup(const __be32 *p) +{ + return __swab32p((__u32 *)p); +} +static inline __be16 __cpu_to_be16p(const __u16 *p) +{ + return (__force __be16)__swab16p(p); +} +static inline __u16 __be16_to_cpup(const __be16 *p) +{ + return __swab16p((__u16 *)p); +} +#define __cpu_to_le64s(x) do { (void)(x); } while (0) +#define __le64_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_le32s(x) do { (void)(x); } while (0) +#define __le32_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_le16s(x) do { (void)(x); } while (0) +#define __le16_to_cpus(x) do { (void)(x); } while (0) #define __cpu_to_be64s(x) __swab64s((x)) #define __be64_to_cpus(x) __swab64s((x)) #define __cpu_to_be32s(x) __swab32s((x)) @@ -64,6 +103,8 @@ #define __cpu_to_be16s(x) __swab16s((x)) #define __be16_to_cpus(x) __swab16s((x)) +#ifdef __KERNEL__ #include +#endif #endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ diff --git a/include/linux/byteorder/swab.h b/include/linux/byteorder/swab.h index b1d570e..bb4a046 100644 --- a/include/linux/byteorder/swab.h +++ b/include/linux/byteorder/swab.h @@ -100,7 +100,7 @@ static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x) { return __arch__swab16(x); } -static __inline__ __u16 __swab16p(__u16 *x) +static __inline__ __u16 __swab16p(const __u16 *x) { return __arch__swab16p(x); } @@ -113,7 +113,7 @@ static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x) { return __arch__swab32(x); } -static __inline__ __u32 __swab32p(__u32 *x) +static __inline__ __u32 __swab32p(const __u32 *x) { return __arch__swab32p(x); } @@ -133,7 +133,7 @@ static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x) return __arch__swab64(x); # endif } -static __inline__ __u64 __swab64p(__u64 *x) +static __inline__ __u64 __swab64p(const __u64 *x) { return __arch__swab64p(x); } -- cgit v1.1 From 0d4c1c91bb2852ff6f4e46f40e72e74ec10599c5 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:24 +0000 Subject: include/linux/compat.h: fix warning: preprocessor token {__iomem, __user} redefined include/linux/compat.h:4:9: warning: preprocessor token __user redefined include/linux/compiler.h:7:10: this was the original definition include/linux/compat.h:5:9: warning: preprocessor token __iomem redefined include/linux/compiler.h:12:10: this was the original definition fixup __iomem, __user definitions in compat.h code appears to be placed there as a cover up from a code import from linux when u-boot didn't yet have a compiler.h, introduced by commit 932394ac43e2e778e664eeb6e456fecd0fae6e59 "Rewrite of NAND code based on what is in 2.6.12 Linux kernel". Signed-off-by: Kim Phillips --- include/linux/compat.h | 3 --- include/linux/mtd/mtd-abi.h | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/linux/compat.h b/include/linux/compat.h index 593b07f..e1338bf 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -1,9 +1,6 @@ #ifndef _LINUX_COMPAT_H_ #define _LINUX_COMPAT_H_ -#define __user -#define __iomem - #define ndelay(x) udelay(1) #define printk printf diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h index 5991157..8bdd231 100644 --- a/include/linux/mtd/mtd-abi.h +++ b/include/linux/mtd/mtd-abi.h @@ -11,6 +11,8 @@ #include #endif +#include + struct erase_info_user { uint32_t start; uint32_t length; -- cgit v1.1 From 25b26ec69fb5390ce08601189d8848fcef91b97c Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:25 +0000 Subject: include/linux/unaligned/generic.h: fix warning: preprocessor token __force redefined include/linux/unaligned/generic.h:5:9: warning: preprocessor token __force redefined include/linux/compiler.h:10:10: this was the original definition fixup __force definitions in compat.h code appears to be placed there as a cover up from a code import from linux when u-boot didn't yet have a compiler.h, introduced by commit b1b4e89a0f3b75854c39a62cae41bad56d210adf "Add LZO decompressor support". Signed-off-by: Kim Phillips --- include/linux/unaligned/generic.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/linux/unaligned/generic.h b/include/linux/unaligned/generic.h index cc688e1..02d97ff 100644 --- a/include/linux/unaligned/generic.h +++ b/include/linux/unaligned/generic.h @@ -1,9 +1,6 @@ #ifndef _LINUX_UNALIGNED_GENERIC_H #define _LINUX_UNALIGNED_GENERIC_H -/* define __force to nothing in U-Boot */ -#define __force - /* * Cause a link-time error if we try an unaligned access other than * 1,2,4 or 8 bytes long -- cgit v1.1 From aa9e891c6331555a75ddcb490fc61160ca7d1657 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:26 +0000 Subject: include/linux/stddef.h: avoid 'warning: preprocessor token offsetof redefined' hack to avoid: /opt/gcc-4.6.3-nolibc/powerpc-linux/bin/../lib/gcc/powerpc-linux/4.6.3/include/stddef.h:413:9: warning: preprocessor token offsetof redefined u-boot/include/linux/stddef.h:20:9: this was the original definition tried protecting with __KERNEL__, and #including compiler.h first. Even tried include dir reordering to no avail: +++ b/config.mk @@ -194,7 +194,11 @@ OBJCFLAGS += --gap-fill=0xff gccincdir := $(shell $(CC) -print-file-name=include) CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ - -D__KERNEL__ + -D__KERNEL__ \ + -I $(gccincdir) \ + -nostdinc + +# -isystem $(gccincdir) \ # Enable garbage collection of un-used sections for SPL ifeq ($(CONFIG_SPL_BUILD),y) @@ -227,8 +231,7 @@ CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include endif CPPFLAGS += -I$(TOPDIR)/include -CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ - -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) +CPPFLAGS += -fno-builtin -ffreestanding -pipe $(PLATFORM_CPPFLAGS) Signed-off-by: Kim Phillips --- include/linux/stddef.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/linux/stddef.h b/include/linux/stddef.h index 81e34c2..c540f61 100644 --- a/include/linux/stddef.h +++ b/include/linux/stddef.h @@ -12,7 +12,9 @@ #include #endif +#ifndef __CHECKER__ #undef offsetof #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#endif #endif -- cgit v1.1 From 2f220500a460ca197ec06aa280519509252ea1d8 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:30 +0000 Subject: include/image.h: sparse fixes include/image.h:378:1: warning: cast to restricted __be32 include/image.h:381:1: warning: cast to restricted __be32 include/image.h:382:1: warning: cast to restricted __be32 include/image.h:383:1: warning: cast to restricted __be32 fix by annotating image header integers big endian. Signed-off-by: Kim Phillips --- include/image.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/image.h b/include/image.h index 4e5863f..0a895f2 100644 --- a/include/image.h +++ b/include/image.h @@ -34,6 +34,7 @@ #define __IMAGE_H__ #include "compiler.h" +#include #ifdef USE_HOSTCC @@ -183,13 +184,13 @@ * all data in network byte order (aka natural aka bigendian). */ typedef struct image_header { - uint32_t ih_magic; /* Image Header Magic Number */ - uint32_t ih_hcrc; /* Image Header CRC Checksum */ - uint32_t ih_time; /* Image Creation Timestamp */ - uint32_t ih_size; /* Image Data Size */ - uint32_t ih_load; /* Data Load Address */ - uint32_t ih_ep; /* Entry Point Address */ - uint32_t ih_dcrc; /* Image Data CRC Checksum */ + __be32 ih_magic; /* Image Header Magic Number */ + __be32 ih_hcrc; /* Image Header CRC Checksum */ + __be32 ih_time; /* Image Creation Timestamp */ + __be32 ih_size; /* Image Data Size */ + __be32 ih_load; /* Data Load Address */ + __be32 ih_ep; /* Entry Point Address */ + __be32 ih_dcrc; /* Image Data CRC Checksum */ uint8_t ih_os; /* Operating System */ uint8_t ih_arch; /* CPU architecture */ uint8_t ih_type; /* Image Type */ -- cgit v1.1 From 0637059088a2579b3c0d67a5ca7d34dd7721204f Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:33 +0000 Subject: net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips --- include/net.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/net.h b/include/net.h index 3539336..970d4d1 100644 --- a/include/net.h +++ b/include/net.h @@ -102,12 +102,13 @@ extern int eth_register(struct eth_device* dev);/* Register network device */ extern int eth_unregister(struct eth_device *dev);/* Remove network device */ extern void eth_try_another(int first_restart); /* Change the device */ extern void eth_set_current(void); /* set nterface to ethcur var */ + /* get the current device MAC */ +extern struct eth_device *eth_current; + static inline __attribute__((always_inline)) struct eth_device *eth_get_dev(void) { - extern struct eth_device *eth_current; - return eth_current; } extern struct eth_device *eth_get_dev_by_name(const char *devname); @@ -517,10 +518,10 @@ enum net_loop_state { NETLOOP_SUCCESS, NETLOOP_FAIL }; +extern enum net_loop_state net_state; + static inline void net_set_state(enum net_loop_state state) { - extern enum net_loop_state net_state; - debug_cond(DEBUG_INT_STATE, "--- NetState set to %d\n", state); net_state = state; } -- cgit v1.1 From ee820b5e5b2a4145ef2266052acd306367051d4c Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:35 +0000 Subject: lib/zlib: sparse fixes define Z_NULL to (void *)0 include/u-boot/zlib.h to get rid of most of the NULL pointer warnings. inflate.c:942:1: warning: non-ANSI definition of function 'inflateEnd' inflate.c:9:1: warning: non-ANSI definition of function 'inflateReset' inflate.c:12:17: warning: Using plain integer as NULL pointer inflate.c:12:42: warning: Using plain integer as NULL pointer inflate.c:15:17: warning: Using plain integer as NULL pointer inflate.c:21:19: warning: Using plain integer as NULL pointer inflate.c:35:1: warning: non-ANSI definition of function 'inflateInit2_' inflate.c:38:20: warning: Using plain integer as NULL pointer inflate.c:41:17: warning: Using plain integer as NULL pointer inflate.c:42:17: warning: Using plain integer as NULL pointer inflate.c:50:18: warning: Using plain integer as NULL pointer inflate.c:65:23: warning: Using plain integer as NULL pointer inflate.c:69:21: warning: Using plain integer as NULL pointer inflate.c:78:1: warning: non-ANSI definition of function 'inflateInit_' inflate.c:86:1: warning: non-ANSI definition of function 'fixedtables' inflate.c:108:26: warning: Using plain integer as NULL pointer inflate.c:109:1: warning: non-ANSI definition of function 'updatewindow' inflate.c:112:30: warning: Using plain integer as NULL pointer inflate.c:339:1: warning: non-ANSI definition of function 'inflate' inflate.c:349:17: warning: Using plain integer as NULL pointer inflate.c:349:42: warning: Using plain integer as NULL pointer inflate.c:350:27: warning: Using plain integer as NULL pointer inflate.c:369:42: warning: Using plain integer as NULL pointer inflate.c:376:32: warning: Using plain integer as NULL pointer inflate.c:401:54: warning: Using plain integer as NULL pointer inflate.c:419:32: warning: Using plain integer as NULL pointer inflate.c:426:32: warning: Using plain integer as NULL pointer inflate.c:433:32: warning: Using plain integer as NULL pointer inflate.c:444:36: warning: Using plain integer as NULL pointer inflate.c:449:37: warning: Using plain integer as NULL pointer inflate.c:450:38: warning: Using plain integer as NULL pointer inflate.c:457:40: warning: Using plain integer as NULL pointer inflate.c:458:47: warning: Using plain integer as NULL pointer inflate.c:480:40: warning: Using plain integer as NULL pointer inflate.c:481:50: warning: Using plain integer as NULL pointer inflate.c:491:37: warning: Using plain integer as NULL pointer inflate.c:492:37: warning: Using plain integer as NULL pointer inflate.c:501:40: warning: Using plain integer as NULL pointer inflate.c:502:53: warning: Using plain integer as NULL pointer inflate.c:512:37: warning: Using plain integer as NULL pointer inflate.c:513:40: warning: Using plain integer as NULL pointer inflate.c:525:32: warning: Using plain integer as NULL pointer inflate.c:529:52: warning: Using plain integer as NULL pointer inflate.c:543:54: warning: Using plain integer as NULL pointer inflate.c:932:17: warning: Using plain integer as NULL pointer inflate.c:932:42: warning: Using plain integer as NULL pointer inflate.c:935:26: warning: Using plain integer as NULL pointer inflate.c:940:19: warning: Using plain integer as NULL pointer adler32.c:58:5: warning: non-ANSI definition of function 'adler32' adler32.c:81:16: warning: Using plain integer as NULL pointer zutil.c:53:9: warning: non-ANSI definition of function 'zcalloc' zutil.c:64:9: warning: non-ANSI definition of function 'zcfree' inffast.c:70:1: warning: non-ANSI definition of function 'inflate_fast' inftrees.c:33:1: warning: non-ANSI definition of function 'inflate_table' Signed-off-by: Kim Phillips --- include/u-boot/zlib.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/u-boot/zlib.h b/include/u-boot/zlib.h index b611fe7..e23ceb5 100644 --- a/include/u-boot/zlib.h +++ b/include/u-boot/zlib.h @@ -505,7 +505,7 @@ typedef gz_header FAR *gz_headerp; #define Z_DEFLATED 8 /* The deflate compression method (the only one supported in this version) */ -#define Z_NULL 0 /* for initializing zalloc, zfree, opaque */ +#define Z_NULL (void *)0 /* for initializing zalloc, zfree, opaque */ /* basic functions */ -- cgit v1.1 From 5811830fae92cf0a3bb11ead54ef1267464a1280 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Sep 2012 10:13:35 +0200 Subject: microblaze: Flush caches before enabling them Flushing caches is necessary because of soft reset which doesn't clear caches. Signed-off-by: Michal Simek Reviewed-by: Marek Vasut --- include/configs/microblaze-generic.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 721cd90..eed38c1 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -287,6 +287,10 @@ # undef CONFIG_DCACHE #endif +#ifndef XILINX_DCACHE_BYTE_SIZE +#define XILINX_DCACHE_BYTE_SIZE 32768 +#endif + /* * BOOTP options */ -- cgit v1.1