From 7fb0f596495395f26819e279acef80487360bfea Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 7 Nov 2014 12:37:52 +0100 Subject: arm: socfpga: Add Cadence QSPI support to config header With this driver enabled for SoCFPGA, access to SPI NOR flash is supported. The configuration (page size, timing info) will be taken from the DT. See socrates as an example. This QSPI supports depends on DT. So QSPI is only enabled if CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig). Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Cc: Pavel Machek Cc: Simon Glass Cc: Jagannadha Sutradharudu Teki --- include/configs/socfpga_common.h | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c4ac94d..2b7534b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -159,7 +159,7 @@ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ #endif - /* +/* * I2C support */ #define CONFIG_SYS_I2C @@ -187,6 +187,29 @@ unsigned int cm_get_l4_sp_clk_hz(void); #define CONFIG_CMD_I2C /* + * QSPI support + */ +#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ +#define CONFIG_CMD_DM +#define CONFIG_DM +#define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH +#define CONFIG_CADENCE_QSPI +/* Enable multiple SPI NOR flash manufacturers */ +#define CONFIG_SPI_FLASH /* SPI flash subsystem */ +#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ +#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ +#define CONFIG_SPI_FLASH_MTD +/* QSPI reference clock */ +#ifndef __ASSEMBLY__ +unsigned int cm_get_qspi_controller_clk_hz(void); +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() +#endif +#define CONFIG_CQSPI_DECODER 0 +#define CONFIG_CMD_SF +#endif + +/* * Serial Driver */ #define CONFIG_SYS_NS16550 -- cgit v1.1 From a6e7359181637f8186d1c1fe7acb442a263e8c40 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 7 Nov 2014 13:50:34 +0100 Subject: arm: socfpga: Add Designware (DW) SPI support to config header Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled. Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Cc: Pavel Machek --- include/configs/socfpga_common.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 2b7534b..afe363c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -209,6 +209,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CMD_SF #endif +#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */ +#define CONFIG_CMD_DM +#define CONFIG_DM +#define CONFIG_DM_SPI +#define CONFIG_DESIGNWARE_SPI +#ifndef __ASSEMBLY__ +unsigned int cm_get_spi_controller_clk_hz(void); +#define CONFIG_DW_SPI_REF_CLK cm_get_spi_controller_clk_hz() +#endif +#define CONFIG_CMD_SPI +#endif + /* * Serial Driver */ -- cgit v1.1 From f37a126692bf97bd77f49252db927f68ec45db43 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 16 Nov 2014 12:46:58 +0100 Subject: arm: socfpga: dts: altr,rst-mgr.h: Move to SPDX license identifiers Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Acked-by: Pavel Machek --- include/dt-bindings/reset/altr,rst-mgr.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h index 3f04908..351d8cd 100644 --- a/include/dt-bindings/reset/altr,rst-mgr.h +++ b/include/dt-bindings/reset/altr,rst-mgr.h @@ -1,14 +1,7 @@ /* * Copyright (c) 2014, Steffen Trumtrar * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H -- cgit v1.1 From 0edeba054b7fe4999f82ac9e422a71b0ed2e99a7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 16 Nov 2014 12:47:02 +0100 Subject: arm: socfpga: DW_SPI: Remove clock info from config header Remove the now unnecessary clocking info from the SoCFPGA config header. As this info in now used directly in the SPI driver itself. Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Acked-by: Pavel Machek --- include/configs/socfpga_common.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index afe363c..6bb9473 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -214,10 +214,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_DM #define CONFIG_DM_SPI #define CONFIG_DESIGNWARE_SPI -#ifndef __ASSEMBLY__ -unsigned int cm_get_spi_controller_clk_hz(void); -#define CONFIG_DW_SPI_REF_CLK cm_get_spi_controller_clk_hz() -#endif #define CONFIG_CMD_SPI #endif -- cgit v1.1