From f0ff4692ff3372dec55074a8eb444943ab095abb Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 15 Aug 2006 14:15:51 +0200
Subject: Add FPGA Altera Cyclone 2 support Patch by Heiko Schocher, 15 Aug
 2006

---
 include/ACEX1K.h | 19 +++++++++++++++++++
 include/altera.h |  4 ++++
 2 files changed, 23 insertions(+)

(limited to 'include')

diff --git a/include/ACEX1K.h b/include/ACEX1K.h
index f75c463..f249d64 100644
--- a/include/ACEX1K.h
+++ b/include/ACEX1K.h
@@ -35,6 +35,11 @@ extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize );
 extern int ACEX1K_info( Altera_desc *desc );
 extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off );
 
+extern int CYC2_load( Altera_desc *desc, void *image, size_t size );
+extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize );
+extern int CYC2_info( Altera_desc *desc );
+extern int CYC2_reloc( Altera_desc *desc, ulong reloc_off );
+
 /* Slave Serial Implementation function table */
 typedef struct {
 	Altera_pre_fn		pre;
@@ -48,6 +53,18 @@ typedef struct {
 	int			relocated;
 } Altera_ACEX1K_Passive_Serial_fns;
 
+/* Slave Serial Implementation function table */
+typedef struct {
+	Altera_pre_fn		pre;
+	Altera_config_fn	config;
+	Altera_status_fn	status;
+	Altera_done_fn		done;
+	Altera_write_fn		write;
+	Altera_abort_fn		abort;
+	Altera_post_fn		post;
+	int			relocated;
+} Altera_CYC2_Passive_Serial_fns;
+
 /* Device Image Sizes
  *********************************************************************/
 /* ACEX1K */
@@ -60,6 +77,8 @@ typedef struct {
 #endif
 #define Altera_EP1K100_SIZE  	(166965*8)
 
+#define Altera_EP2C35_SIZE	883905
+
 /* Descriptor Macros
  *********************************************************************/
 /* ACEX1K devices */
diff --git a/include/altera.h b/include/altera.h
index 74b6729..7b8cb4a 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -34,8 +34,10 @@
 /* Altera Model definitions
  *********************************************************************/
 #define CFG_ACEX1K		CFG_FPGA_DEV( 0x1 )
+#define CFG_CYCLON2		CFG_FPGA_DEV( 0x2 )
 
 #define CFG_ALTERA_ACEX1K	(CFG_FPGA_ALTERA | CFG_ACEX1K)
+#define CFG_ALTERA_CYCLON2	(CFG_FPGA_ALTERA | CFG_CYCLON2)
 /* Add new models here */
 
 /* Altera Interface definitions
@@ -56,6 +58,7 @@ typedef enum {				/* typedef Altera_iface */
 typedef enum {			/* typedef Altera_Family */
     min_altera_type,		/* insert all new types after this */
     Altera_ACEX1K,		/* ACEX1K Family */
+    Altera_CYC2,		/* CYCLONII Family */
 /* Add new models here */
     max_altera_type		/* insert all new types before this */
 } Altera_Family;		/* end, typedef Altera_Family */
@@ -84,6 +87,7 @@ typedef int (*Altera_status_fn)( int cookie );
 typedef int (*Altera_done_fn)( int cookie );
 typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
 typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
+typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie);
 typedef int (*Altera_abort_fn)( int cookie );
 typedef int (*Altera_post_fn)( int cookie );
 
-- 
cgit v1.1


From 899620c2d66d4eef3b2a0034d062e71d45d886c9 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 15 Aug 2006 14:22:35 +0200
Subject: Add initial support for the ALPR board from Prodrive NAND needs some
 additional testing Patch by Heiko Schocher, 15 Aug 2006

---
 include/configs/alpr.h | 393 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/ppc440.h       |   2 +-
 2 files changed, 394 insertions(+), 1 deletion(-)
 create mode 100644 include/configs/alpr.h

(limited to 'include')

diff --git a/include/configs/alpr.h b/include/configs/alpr.h
new file mode 100644
index 0000000..eeafcd6
--- /dev/null
+++ b/include/configs/alpr.h
@@ -0,0 +1,393 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ALPR		1	    /* Board is ebony		*/
+#define CONFIG_440GX		1	    /* Specifc GX support	*/
+#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
+#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
+#define CFG_FLASH_BASE	    0xffe00000	    /* start of FLASH		*/
+#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
+#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define	CFG_PCI_MEMSIZE	    0x40000000	    /* size of mapped pci memory */
+#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
+#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+
+
+#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM  1
+#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CFG_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE		115200
+#define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+#if 0 /* test-only */
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
+#undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
+#define CFG_SDRAM_TABLE	{ \
+		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
+		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs	*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (PCF8594C)
+ *----------------------------------------------------------------------*/
+#define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
+					/* 8 byte page write mode using */
+					/* last 3 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=alpr\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/alpr/uImage\0"				\
+	"kernel_addr=fff00000\0"					\
+	"ramdisk_addr=fff10000\0"					\
+	"load=tftp 100000 /tftpboot/alpr/u-boot.bin\0"			\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI	1
+#define CONFIG_PHY_ADDR		0x02	/* dummy setting, no EMAC0 used	*/
+#define CONFIG_PHY1_ADDR	0x03	/* dummy setting, no EMAC1 used	*/
+#define CONFIG_PHY2_ADDR	0x00	/* test-only: will be changed	*/
+#define CONFIG_PHY3_ADDR	0x01	/* PHY address for EMAC3	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#define CONFIG_88E1111_CLK_DELAY 1	/* set CLK delay on ALPR	*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#if 0 /* test-only */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SNTP	)
+#else
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_FPGA	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_REGINFO)
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_FPGA             CFG_ALTERA_CYCLON2
+#undef CFG_FPGA_CHECK_CTRLC
+#undef CFG_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_COUNT       1		/* Ich habe 2 ... aber in
+					Reihe geschaltet -> sollte gehen,
+					aufpassen mit Datasize ist jetzt
+					halt doppelt so gross ... Seite 306
+					ist das mit den multiple Device in PS
+					Mode erklaert ...*/
+
+
+/* FPGA program pin configuration */
+#define CFG_GPIO_CLK		18	/* FPGA clk pin (cpu output)		*/
+#define CFG_GPIO_DATA		19	/* FPGA data pin (cpu output)		*/
+#define CFG_GPIO_STATUS		20	/* FPGA status pin (cpu input)		*/
+#define CFG_GPIO_CONFIG		21	/* FPGA CONFIG pin (cpu output)		*/
+#define CFG_GPIO_CON_DON	22	/* FPGA CONFIG_DONE pin (cpu input)	*/
+
+#define CFG_GPIO_SEL_DPR	14	/* cpu output */
+#define CFG_GPIO_SEL_AVR	15	/* cpu output */
+#define CFG_GPIO_PROG_EN	23	/* cpu output */
+
+/*
+ * NAND-FLASH stuff
+ */
+#define CFG_MAX_NAND_DEVICE	2
+#define NAND_MAX_CHIPS		2
+#define CFG_NAND_BASE		0x50000000	/* NAND FLASH Base Address	*/
+
+#if 0
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 4
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH		CFG_FLASH_BASE
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
+/* Memory Bank 1 (NAND-FLASH) initialization			*/
+/*#define CFG_EBC_PB1AP		0x108f4380 */	/* TODO */
+/*#define CFG_EBC_PB1AP		0x7f854380 */	/* TODO */
+/*#define CFG_EBC_PB1AP		0x108553c0 */
+/*#define CFG_EBC_PB1AP		0x108053c0 */
+#define CFG_EBC_PB1AP		0x10810180
+
+/*#define CFG_EBC_PB1CR		(CFG_NAND_BASE | 0x18000) *//* BS=1MB,BU=R/W,BW=8bit */
+#define CFG_EBC_PB1CR		(CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		32768	/* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/ppc440.h b/include/ppc440.h
index d5a9f66..b81e34d 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -2631,7 +2631,7 @@
 #define GPIO0			0
 #define GPIO1			1
 
-#if defined(CONFIG_440GP)
+#if defined(CONFIG_440GP) || defined(CONFIG_440GX)
 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000700)
 
 #define GPIO0_OR               (GPIO0_BASE+0x0)
-- 
cgit v1.1


From f3443867e90d2979a7dd1c65b0d537777e1f9850 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Sat, 7 Oct 2006 11:30:52 +0200
Subject: Add CONFIG_BOARD_RESET to configure board specific reset function
 Patch by Stefan Roese, 07 Oct 2006

---
 include/configs/yellowstone.h | 1 +
 include/configs/yosemite.h    | 1 +
 2 files changed, 2 insertions(+)

(limited to 'include')

diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h
index ba27f37..58717f8 100644
--- a/include/configs/yellowstone.h
+++ b/include/configs/yellowstone.h
@@ -37,6 +37,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+#define CONFIG_BOARD_RESET	1	/* call board_reset()		*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 3d7b4a2..6e942ab 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -37,6 +37,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+#define CONFIG_BOARD_RESET	1	/* call board_reset()		*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
-- 
cgit v1.1


From 5bc528fa4da751d472397b308137238a6465afd2 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Sat, 7 Oct 2006 11:35:25 +0200
Subject: Update ALPR code (NAND support working now) Patch by Stefan Roese, 07
 Oct 2006

---
 include/configs/alpr.h | 101 +++++++++++++++----------------------------------
 1 file changed, 30 insertions(+), 71 deletions(-)

(limited to 'include')

diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index eeafcd6..c6731ba 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -31,8 +31,9 @@
 #define CONFIG_440GX		1	    /* Specifc GX support	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
+#define CONFIG_BOARD_RESET	1	    /* call board_reset()	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+#define CONFIG_SYS_CLK_FREQ	33333000    /* external freq to pll	*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
@@ -81,44 +82,28 @@
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-
-#if 0 /* test-only */
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
-#endif
-
-/*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
-#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE		/* FLASH bank #0	*/
 
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 
@@ -177,7 +162,7 @@
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
 	"flash_nfs=run nfsargs addip addtty;"				\
 		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip addtty;"				\
@@ -216,24 +201,10 @@
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
 #define CONFIG_88E1111_CLK_DELAY 1	/* set CLK delay on ALPR	*/
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 
-#if 0 /* test-only */
-#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
-				CFG_CMD_ASKENV	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_DIAG	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_NET	| \
-				CFG_CMD_NFS	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO	| \
-				CFG_CMD_SNTP	)
-#else
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
 				CFG_CMD_DHCP	| \
@@ -250,7 +221,6 @@
 				CFG_CMD_FPGA	| \
 				CFG_CMD_NAND	| \
 				CFG_CMD_REGINFO)
-#endif
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -279,15 +249,12 @@
 
 #define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -321,7 +288,6 @@
 					ist das mit den multiple Device in PS
 					Mode erklaert ...*/
 
-
 /* FPGA program pin configuration */
 #define CFG_GPIO_CLK		18	/* FPGA clk pin (cpu output)		*/
 #define CFG_GPIO_DATA		19	/* FPGA data pin (cpu output)		*/
@@ -336,14 +302,12 @@
 /*
  * NAND-FLASH stuff
  */
-#define CFG_MAX_NAND_DEVICE	2
-#define NAND_MAX_CHIPS		2
-#define CFG_NAND_BASE		0x50000000	/* NAND FLASH Base Address	*/
-
-#if 0
-#define CONFIG_MTD_DEBUG
-#define CONFIG_MTD_DEBUG_VERBOSE 4
-#endif
+#define CFG_MAX_NAND_DEVICE	4
+#define NAND_MAX_CHIPS		CFG_MAX_NAND_DEVICE
+#define CFG_NAND_BASE		0xF0000000	/* NAND FLASH Base Address	*/
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE + 0, CFG_NAND_BASE + 2,	\
+				  CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 }
+#define CFG_NAND_QUIET_TEST	1	/* don't warn upon unknown NAND flash	*/
 
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
@@ -353,14 +317,9 @@
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
 #define CFG_EBC_PB0AP		0x92015480
 #define CFG_EBC_PB0CR		(CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
-/* Memory Bank 1 (NAND-FLASH) initialization			*/
-/*#define CFG_EBC_PB1AP		0x108f4380 */	/* TODO */
-/*#define CFG_EBC_PB1AP		0x7f854380 */	/* TODO */
-/*#define CFG_EBC_PB1AP		0x108553c0 */
-/*#define CFG_EBC_PB1AP		0x108053c0 */
-#define CFG_EBC_PB1AP		0x10810180
-
-/*#define CFG_EBC_PB1CR		(CFG_NAND_BASE | 0x18000) *//* BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 1 (NAND-FLASH) initialization					*/
+#define CFG_EBC_PB1AP		0x01840380	/* TWT=3			*/
 #define CFG_EBC_PB1CR		(CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
 
 /*
-- 
cgit v1.1


From 91650b3e4de688038d4f71279c44858e3e2c6870 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Mon, 6 Nov 2006 17:06:36 +0100
Subject: Sequential accesses to non-existent memory must be synchronized, at
 least on G2 cores.

This fixes get_ram_size() problems on MPC5200 Rev. B boards.
---
 include/common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/common.h b/include/common.h
index 349d5cf..ac78d1c 100644
--- a/include/common.h
+++ b/include/common.h
@@ -270,7 +270,7 @@ int	misc_init_r   (void);
 void	jumptable_init(void);
 
 /* common/memsize.c */
-int	get_ram_size  (volatile long *, long);
+long	get_ram_size  (volatile long *, long);
 
 /* $(BOARD)/$(BOARD).c */
 void	reset_phy     (void);
-- 
cgit v1.1


From 44a47e6db2694841211f1c8fdbafd36992e9cd1a Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sat, 11 Nov 2006 22:43:00 +0100
Subject: Change the GPIO pin multiplexing configuration for V38B. The USB GPIO
 pin group is enabled for USB earlier (in cpu_init_f() instead of
 usb_lowlevel_init()).

---
 include/configs/v38b.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index cf2d031..deabc17 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -246,7 +246,7 @@
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x90000404
+#define CFG_GPS_PORT_CONFIG	0x90001404
 
 /*
  * Miscellaneous configurable options
-- 
cgit v1.1


From ce3f1a40c507afbab06c5eb58ccdc6713eda3245 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sat, 11 Nov 2006 22:48:22 +0100
Subject: Disable the watchdog in the default config for the V38B board.

---
 include/configs/v38b.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index deabc17..554a7a4 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -34,7 +34,7 @@
 #define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC */
 #define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM */
 
-#define CONFIG_HW_WATCHDOG		1	/* has watchdog */
+#undef CONFIG_HW_WATCHDOG			/* don't use watchdog */
 
 #define CONFIG_NETCONSOLE		1
 
-- 
cgit v1.1


From 260421a21e934a68d31fb6125b0fbd2631a8ca20 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 13 Nov 2006 13:55:24 +0100
Subject: [PATCH] CFI driver AMD Command Set Top boot geometry reversal, etc.
 [Updated]

   * Adds support for AMD command set Top Boot flash geometry reversal
   * Adds support for reading JEDEC Manufacturer ID and Device ID
   * Adds support for displaying command set, manufacturer id and
     device ids (flinfo)
   * Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO defined
   * Removes outdated change history (refer to git log instead)

Signed-off-by: Tolunay Orkun <listmember@orkun.us>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/flash.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/flash.h b/include/flash.h
index d91589a..9c57cbc 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -43,9 +43,14 @@ typedef struct {
 	ulong	write_tout;		/* maximum write timeout		*/
 	ulong	buffer_write_tout;	/* maximum buffer write timeout		*/
 	ushort	vendor;			/* the primary vendor id		*/
-	ushort	cmd_reset;		/* Vendor specific reset command	*/
+	ushort	cmd_reset;		/* vendor specific reset command	*/
 	ushort	interface;		/* used for x8/x16 adjustments		*/
 	ushort	legacy_unlock;		/* support Intel legacy (un)locking	*/
+	uchar	manufacturer_id;	/* manufacturer id			*/
+	ushort	device_id;		/* device id				*/
+	ushort	device_id2;		/* extended device id			*/
+	ushort	ext_addr;		/* extended query table address		*/
+	ushort	cfi_version;		/* cfi version				*/
 #endif
 } flash_info_t;
 
@@ -439,6 +444,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define FLASH_MAN_MT	0x00400000
 #define FLASH_MAN_SHARP 0x00500000
 #define FLASH_MAN_ATM	0x00600000
+#define FLASH_MAN_CFI	0x01000000
 
 
 #define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type	information	*/
-- 
cgit v1.1


From 4ef6251403f637841000e0fef9e832aa01339822 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 20 Nov 2006 20:39:52 +0100
Subject: [PATCH] Update AMCC Sequoia config file to support 64MByte NOR FLASH

Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/sequoia.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'include')

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 3a76315..1a460cd 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -53,7 +53,7 @@
 
 #define CFG_BOOT_BASE_ADDR	0xf0000000
 #define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH_BASE		0xfe000000	/* start of FLASH	*/
+#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
 #define CFG_MONITOR_BASE	TEXT_BASE
 #define CFG_NAND_ADDR		0xd0000000      /* NAND Flash		*/
 #define CFG_OCM_BASE		0xe0010000      /* ocm			*/
@@ -234,10 +234,10 @@
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"rootpath=/opt/eldk/ppc_4xxFP\0"					\
 	"bootfile=/tftpboot/sequoia/uImage\0"				\
-	"kernel_addr=FE000000\0"					\
-	"ramdisk_addr=FE180000\0"					\
+	"kernel_addr=FC000000\0"					\
+	"ramdisk_addr=FC180000\0"					\
 	"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0"		\
 	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
 		"cp.b 100000 FFFA0000 60000\0"			        \
@@ -378,7 +378,7 @@
 #define CFG_NAND_CS		3		/* NAND chip connected to CSx	*/
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
 #define CFG_EBC_PB0AP		0x03017300
-#define CFG_EBC_PB0CR		(CFG_FLASH | 0xba000)
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0xda000)
 
 /* Memory Bank 3 (NAND-FLASH) initialization					*/
 #define CFG_EBC_PB3AP		0x018003c0
@@ -387,7 +387,7 @@
 #define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
 /* Memory Bank 3 (NOR-FLASH) initialization					*/
 #define CFG_EBC_PB3AP		0x03017300
-#define CFG_EBC_PB3CR		(CFG_FLASH | 0xba000)
+#define CFG_EBC_PB3CR		(CFG_FLASH | 0xda000)
 
 /* Memory Bank 0 (NAND-FLASH) initialization					*/
 #define CFG_EBC_PB0AP		0x018003c0
-- 
cgit v1.1


From 78d620ebb5871d252270dedfad60c6568993b780 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@atlas.denx.de>
Date: Thu, 23 Nov 2006 22:58:58 +0100
Subject: Updates for TQM5200 modules: - fix off-by-one error in
 board/tqm5200/cam5200_flash.c error message - simplify "udate" definitions

---
 include/configs/TQM5200.h | 46 +++++++++++-----------------------------------
 1 file changed, 11 insertions(+), 35 deletions(-)

(limited to 'include')

diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 4bae103..08674ca 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -217,43 +217,19 @@
 
 #undef	CONFIG_BOOTARGS
 
-#ifdef CONFIG_STK52XX
-# if defined(CONFIG_TQM5200_B)
-#  if defined(CFG_LOWBOOT)
-#   define ENV_UPDT							\
-	"update=protect off FC000000 FC07FFFF;"				\
-		"erase FC000000 FC07FFFF;"				\
-		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 FC07FFFF\0"
-#  else	/* highboot */
-#   define ENV_UPDT							\
-	"update=protect off FFF00000 FFF7FFFF;"				\
-		"erase FFF00000 FFF7FFFF;"				\
+#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT)
+# define ENV_UPDT							\
+	"update=protect off FFF00000 +${filesize};"			\
+		"erase FFF00000 +${filesize};"				\
 		"cp.b 200000 FFF00000 ${filesize};"			\
-		"protect on FFF00000 FFF7FFFF\0"
-#  endif /* CFG_LOWBOOT */
-# else	/* !CONFIG_TQM5200_B */
-#  define ENV_UPDT							\
-	"update=protect off FC000000 FC05FFFF;"				\
-		"erase FC000000 FC05FFFF;"				\
-		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 FC05FFFF\0"
-# endif /* CONFIG_TQM5200_B */
-#elif defined (CONFIG_CAM5200)
-#   define ENV_UPDT							\
-	"update=protect off FC000000 FC03FFFF;"				\
-		"erase FC000000 FC03FFFF;"				\
-		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 FC03FFFF\0"
-#elif defined (CONFIG_FO300)
+		"protect on FFF00000 +${filesize}\0"
+#else	/* default lowboot configuration */
 #   define ENV_UPDT							\
-	"update=protect off FC000000 FC05FFFF;"				\
-		"erase FC000000 FC05FFFF;"				\
+	"update=protect off FC000000 +${filesize};"			\
+		"erase FC000000 +${filesize};"				\
 		"cp.b 200000 FC000000 ${filesize};"			\
-		"protect on FC000000 FC05FFFF\0"
-#else
-# error "Unknown Carrier Board"
-#endif	/* CONFIG_STK52XX */
+		"protect on FC000000 +${filesize}\0"
+#endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
@@ -432,7 +408,7 @@
  */
 #define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_SIZE		0x4000	/* 16 k - keep small for fast booting */
-#if defined(CONFIG_TQM5200_B)
+#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
 #define CFG_ENV_SECT_SIZE	0x40000
 #else
 #define CFG_ENV_SECT_SIZE	0x20000
-- 
cgit v1.1


From 1c2ce2262069510f31c7d3fd7efd3d58b8c0c148 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 27 Nov 2006 14:12:17 +0100
Subject: [PATCH] Update Prodrive ALPR board support (440GX)

Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/alpr.h | 96 +++++++++++++++++++++++---------------------------
 1 file changed, 45 insertions(+), 51 deletions(-)

(limited to 'include')

diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index c6731ba..60da820 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -31,25 +31,25 @@
 #define CONFIG_440GX		1	    /* Specifc GX support	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
-#define CONFIG_BOARD_RESET	1	    /* call board_reset()	*/
+#define CONFIG_LAST_STAGE_INIT	1	    /* call last_stage_init()	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ	33333000    /* external freq to pll	*/
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
-#define CFG_FLASH_BASE	    0xffe00000	    /* start of FLASH		*/
-#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
-#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
-#define	CFG_PCI_MEMSIZE	    0x40000000	    /* size of mapped pci memory */
-#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
-#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
-#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
-#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0			*/
+#define CFG_FLASH_BASE		0xffe00000	/* start of FLASH		*/
+#define CFG_MONITOR_BASE	0xfffc0000	/* start of monitor		*/
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory		*/
+#define	CFG_PCI_MEMSIZE		0x40000000	/* size of mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE	0xe0000000	/* internal peripherals		*/
+#define CFG_ISRAM_BASE		0xc0000000	/* internal SRAM		*/
+#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs		*/
+#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
 
 
 #define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
@@ -84,26 +84,13 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE		/* FLASH bank #0	*/
-
+#define CFG_FLASH_CFI		1	/* The flash is CFI compatible		*/
+#define CFG_FLASH_CFI_DRIVER	1	/* Use common CFI driver		*/
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
-
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
 
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 
@@ -154,7 +141,7 @@
 #undef	CONFIG_BOOTARGS
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
+	"netdev=eth3\0"							\
 	"hostname=alpr\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
@@ -162,18 +149,19 @@
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
+		"mem=193M\0"						\
 	"flash_nfs=run nfsargs addip addtty;"				\
 		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip addtty;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/alpr/uImage\0"				\
+	"rootpath=/opt/projects/alpr/nfs_root\0"			\
+	"bootfile=/alpr/uImage\0"					\
 	"kernel_addr=fff00000\0"					\
 	"ramdisk_addr=fff10000\0"					\
-	"load=tftp 100000 /tftpboot/alpr/u-boot.bin\0"			\
+	"load=tftp 100000 /alpr/u-boot/u-boot.bin\0"			\
 	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
 		"cp.b 100000 fffc0000 40000;"			        \
 		"setenv filesize;saveenv\0"				\
@@ -181,7 +169,7 @@
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define CONFIG_BOOTDELAY	2	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BAUDRATE		115200
 
@@ -192,8 +180,8 @@
 #define CONFIG_NET_MULTI	1
 #define CONFIG_PHY_ADDR		0x02	/* dummy setting, no EMAC0 used	*/
 #define CONFIG_PHY1_ADDR	0x03	/* dummy setting, no EMAC1 used	*/
-#define CONFIG_PHY2_ADDR	0x00	/* test-only: will be changed	*/
-#define CONFIG_PHY3_ADDR	0x01	/* PHY address for EMAC3	*/
+#define CONFIG_PHY2_ADDR	0x01	/* PHY address for EMAC2	*/
+#define CONFIG_PHY3_ADDR	0x02	/* PHY address for EMAC3	*/
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
@@ -251,9 +239,11 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_MX_CYCLIC     	1       /* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
+
+#define CFG_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -264,7 +254,7 @@
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
 #define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY	1       /* enable pci bootdelay variable*/
 
 /* Board-specific PCI */
 #define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
@@ -276,11 +266,10 @@
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
- *-----------------------------------------------------------------------
- */
+ *-----------------------------------------------------------------------*/
 #define CONFIG_FPGA             CFG_ALTERA_CYCLON2
-#undef CFG_FPGA_CHECK_CTRLC
-#undef CFG_FPGA_PROG_FEEDBACK
+#define CFG_FPGA_CHECK_CTRLC
+#define CFG_FPGA_PROG_FEEDBACK
 #define CONFIG_FPGA_COUNT       1		/* Ich habe 2 ... aber in
 					Reihe geschaltet -> sollte gehen,
 					aufpassen mit Datasize ist jetzt
@@ -299,9 +288,16 @@
 #define CFG_GPIO_SEL_AVR	15	/* cpu output */
 #define CFG_GPIO_PROG_EN	23	/* cpu output */
 
-/*
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup
+ *-----------------------------------------------------------------------*/
+#define CFG_GPIO_EREADY		(0x80000000 >> 26)
+#define CFG_GPIO_REV0		(0x80000000 >> 14)
+#define CFG_GPIO_REV1		(0x80000000 >> 15)
+
+/*-----------------------------------------------------------------------
  * NAND-FLASH stuff
- */
+ *-----------------------------------------------------------------------*/
 #define CFG_MAX_NAND_DEVICE	4
 #define NAND_MAX_CHIPS		CFG_MAX_NAND_DEVICE
 #define CFG_NAND_BASE		0xF0000000	/* NAND FLASH Base Address	*/
@@ -320,7 +316,7 @@
 
 /* Memory Bank 1 (NAND-FLASH) initialization					*/
 #define CFG_EBC_PB1AP		0x01840380	/* TWT=3			*/
-#define CFG_EBC_PB1CR		(CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
+#define CFG_EBC_PB1CR		(CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
 
 /*
  * For booting Linux, the board info and command line data
@@ -333,9 +329,7 @@
  */
 #define CFG_DCACHE_SIZE		32768	/* For AMCC 440 CPUs			*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
 
 /*
  * Internal Definitions
-- 
cgit v1.1


From ec0c2ec725aec9524a177a77ce75559e644a931a Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 27 Nov 2006 14:46:06 +0100
Subject: [PATCH] Remove testing 4xx enet PHY setup

Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/alpr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 60da820..bbe6b76 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -187,7 +187,7 @@
 #define CONFIG_HAS_ETH2
 #define CONFIG_HAS_ETH3
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
-#define CONFIG_88E1111_CLK_DELAY 1	/* set CLK delay on ALPR	*/
+#define CONFIG_M88E1111_PHY	1	/* needed for PHY specific setup*/
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 
-- 
cgit v1.1


From d1a72545296800b7e219f93104ad5836f0003d66 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 27 Nov 2006 17:34:10 +0100
Subject: [PATCH] Select NAND embedded environment from board configuration

The current NAND Bootloader setup forces the environment
variables to be in line with the bootloader. This change
enables the configuration to be made in the board include
file instead so that it can be individually enabled.

Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/sequoia.h | 1 +
 include/environment.h     | 3 +--
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 1a460cd..00b9222 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -102,6 +102,7 @@
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 #else
 #define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
+#define CFG_ENV_IS_EMBEDDED	1	/* use embedded environment */
 #endif
 
 /*-----------------------------------------------------------------------
diff --git a/include/environment.h b/include/environment.h
index 26b0712..af605ab 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -79,8 +79,7 @@
 # ifdef CFG_ENV_OFFSET_REDUND
 #  define CFG_REDUNDAND_ENVIRONMENT
 # endif
-# if defined(CONFIG_NAND_U_BOOT)
-/* Use embedded environment in NAND boot versions */
+# ifdef CFG_ENV_IS_EMBEDDED
 #  define ENV_IS_EMBEDDED	1
 # endif
 #endif /* CFG_ENV_IS_IN_NAND */
-- 
cgit v1.1