From ed9e4e427295623197d8dd76a1ca9ac15e085572 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 27 Oct 2014 11:31:32 -0700 Subject: mpc85xx/t208xqds: Adjust DDR timing parameters Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of 1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in case such DIMM comes available. Also update single-rank 1866 timing. Enable interactive debugging as well. Signed-off-by: York Sun CC: Shengzhou Liu --- include/configs/T208xQDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2f381e7..ebc32f2 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -234,7 +234,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 -#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 -- cgit v1.1