From debb7354d1ea4f694154818df5e5b523f5c1cc1d Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Wed, 26 Apr 2006 17:58:56 -0500
Subject: Initial support for MPC8641 HPCN board.

---
 include/configs/MPC8641HPCN.h | 629 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 629 insertions(+)
 create mode 100644 include/configs/MPC8641HPCN.h

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
new file mode 100644
index 0000000..8d2e088
--- /dev/null
+++ b/include/configs/MPC8641HPCN.h
@@ -0,0 +1,629 @@
+/*              
+ * Copyright 2004 Freescale Semiconductor.
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8641hpc3 board configuration file
+ *
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MPC86xx		1	/* MPC86xx */
+#define CONFIG_MPC8641		1	/* MPC8641 specific */
+#define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
+#define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
+#undef DEBUG                   
+
+//#define RUN_DIAG             1   
+#ifdef RUN_DIAG
+#define CFG_DIAG_ADDR        0xff800000
+#endif
+#define CFG_RESET_ADDRESS    0xfff00100
+
+//#define CONFIG_PCI
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+/*#define CONFIG_DDR_ECC	*/		/* only for ECC DDR module */
+/*#define CONFIG_DDR_DLL	*/		/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+
+#define CONFIG_ALTIVEC          1  
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ */
+
+#define CFG_L2          
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+//#define CONFIG_SYS_CLK_FREQ	33000000
+#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+/* JB - XXX - Are these available on 86xx? */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define MPC86xx_DDR_SDRAM_CLK_CNTL
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR parameters
+     */
+
+/* DDR I */
+#if 1
+    #define CFG_SDRAM_SIZE	256		/* DDR is 256MB */
+
+    #define CFG_DDR_CS0_BNDS	0x0000000F
+    #define CFG_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
+    #define CFG_DDR_EXT_REFRESH 0x00000000
+    #define CFG_DDR_TIMING_0    0x00260802
+    #define CFG_DDR_TIMING_1	0x39357322
+    #define CFG_DDR_TIMING_2	0x14904cc8
+    #define CFG_DDR_MODE_1	0x00480432
+    #define CFG_DDR_MODE_2	0x00000000
+    #define CFG_DDR_INTERVAL	0x06090100
+    #define CFG_DDR_DATA_INIT   0xdeadbeef
+    #define CFG_DDR_CLK_CTRL    0x03800000
+    #define CFG_DDR_OCD_CTRL    0x00000000  
+    #define CFG_DDR_OCD_STATUS  0x00000000  
+    #define CFG_DDR_CONTROL	0xe3008000	/* Type = DDR2 */
+    #define CFG_DDR_CONTROL2	0x04400000	
+
+    //Not used in fixed_sdram function
+
+    #define CFG_DDR_MODE	0x00000022
+    #define CFG_DDR_CS1_BNDS	0x00000000
+    #define CFG_DDR_CS2_BNDS	0x00000FFF  //Not done
+    #define CFG_DDR_CS3_BNDS	0x00000FFF  //Not done
+    #define CFG_DDR_CS4_BNDS	0x00000FFF  //Not done
+    #define CFG_DDR_CS5_BNDS	0x00000FFF  //Not done
+
+
+
+#endif
+#endif
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+//#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+//#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000
+ * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
+ * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
+ * However, when u-boot comes up, the flash_init needs hard start addresses
+ * to build its info table. For user convenience, we have the flash addresses
+ * as fe800000 and ff800000. That way, when we do flash operations, u-boot
+ * knows where the flash is and the user can download u-boot code from promjet to
+ * fef00000 <- more intuitive than fe700000. Note that, on switching the boot
+ * location, fef00000 becomes fff00000.
+*/
+#define CFG_FLASH_BASE          0xfe800000     /* start of FLASH 32M */
+#define CFG_FLASH_BASE2		0xff800000	
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+
+
+/*Sri: This looks like a good place to init all the Local Bus chip selects*/
+
+#define CFG_BR0_PRELIM		0xff001001	/* port size 16bit */
+#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Boot Flash area*/
+
+#define CFG_BR1_PRELIM		0xfe001001	/* port size 16bit */
+#define CFG_OR1_PRELIM		0xff006ff7	/* 16MB Alternate Boot Flash area*/
+
+#define CFG_BR2_PRELIM		0xf8201001	/* port size 16bit */
+#define CFG_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
+
+#define CFG_BR3_PRELIM		0xf8100801	/* port size 8bit */
+#define CFG_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
+
+#define PIXIS_BASE              0xf8100000      /* PIXIS registers*/
+#define PIXIS_ID                0x0               /* MPC8641HPCN Board ID at offset 0*/
+#define PIXIS_VER               0x1               /* MPC8641HPCN board version version at offset 1*/
+#define PIXIS_PVER              0x2               /* PIXIS FPGA version at offset 2*/
+#define PIXIS_RST               0x4               /* PIXIS Reset Control register*/
+#define PIXIS_AUX               0x6               /* PIXIS Auxiliary register; Scratch register */
+#define PIXIS_SPD               0x7               /* Register for SYSCLK speed */
+#define PIXIS_VCTL              0x10              /* VELA Control Register */
+#define PIXIS_VCFGEN0           0x12              /* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1           0x13              /* VELA Config Enable 1 */
+#define PIXIS_VBOOT             0x16              /* VELA VBOOT Register */
+#define PIXIS_VSPEED0           0x17              /* VELA VSpeed 0 */
+#define PIXIS_VSPEED1           0x18              /* VELA VSpeed 1 */
+#define PIXIS_VCLKH             0x19              /* VELA VCLKH register */
+#define PIXIS_VCLKL             0x1A              /* VELA VCLKL register */
+
+
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+//#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+/*#define CFG_HPCN_FLASH_CFI_DRIVER */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#if !defined(CFG_RAMBOOT)
+#define CONFIG_SPD_EEPROM        	/* Use SPD EEPROM for DDR setup*/
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_L1_INIT_RAM
+#undef CFG_INIT_RAM_LOCK 	
+#ifndef CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
+#else
+#define CFG_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
+#endif
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU   "PowerPC,8641@0"
+#define OF_SOC   "soc8641@f8000000"
+#define OF_TBCLK  (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH  "/soc8641@f8000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
+/* I2C */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/* RapidIO MMU */
+#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+//#define CFG_PCI1_MEM_BASE	0xd0000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+//#define CFG_PCI1_IO_BASE	0xe0000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+//#define CFG_PCI1_IO_BUS         0x00000000
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+/* For RTL8139 */
+#define _IO_BASE                0x00000000
+
+#define CFG_PCI2_MEM_BASE	0xa0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI2_IO_BASE	0xe3000000
+#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+
+// #define CFG_PCI1_MEM_BASE	0x80000000
+// #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+// #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+// #define CFG_PCI1_IO_BASE	0xe2000000
+// #define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+// #define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+
+
+#if defined(CONFIG_PCI)
+
+
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
+
+//#define CFG_SCSI_SCAN_BUS_REVERSE
+
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#define CONFIG_RTL8139
+
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+//#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+
+#define CONFIG_MPC86XX_TSEC1    1
+#define CONFIG_MPC86XX_TSEC1_NAME       "eTSEC1"
+#define CONFIG_MPC86XX_TSEC2    1
+#define CONFIG_MPC86XX_TSEC2_NAME       "eTSEC2"
+#define CONFIG_MPC86XX_TSEC3    1
+#define CONFIG_MPC86XX_TSEC3_NAME       "eTSEC3"
+#define CONFIG_MPC86XX_TSEC4    1
+#define CONFIG_MPC86XX_TSEC4_NAME       "eTSEC4"
+
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+
+/* BAT0         2G     Cacheable, non-guarded
+ * 0x0000_0000  2G     DDR
+ */
+//#define CFG_DBAT0L      (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0L      (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U      (0x0 | BATU_BL_512M | BATU_VS | BATU_VP)
+//#define CFG_IBAT0L      CFG_DBAT0L
+//#define CFG_IBAT0L      (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0L      (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U      CFG_DBAT0U
+
+/* BAT1         1G     Cache-inhibited, guarded
+ * 0x8000_0000  512M   PCI-Express 1 Memory
+ * 0xa000_0000  512M   PCI-Express 2 Memory
+ ** SS - Changed it for operating from 0xd0000000
+ */
+#define CFG_DBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U      (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U      CFG_DBAT1U
+
+/* BAT2         512M   Cache-inhibited, guarded
+ * 0xc000_0000  512M   RapidIO Memory
+ */
+#define CFG_DBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U      (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U      CFG_DBAT2U
+
+/* BAT3         4M     Cache-inhibited, guarded
+ * 0xf800_0000  4M     CCSR
+ */
+#define CFG_DBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U      (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U      CFG_DBAT3U
+
+/* BAT4         32M    Cache-inhibited, guarded
+ * 0xe200_0000  16M    PCI-Express 1 I/O
+ * 0xe300_0000  16M    PCI-Express 2 I/0
+ ** SS - Note that this is at 0xe0000000
+ */
+#define CFG_DBAT4L      (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U      (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L      (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U      CFG_DBAT4U
+
+/* BAT5         128K   Cacheable, non-guarded
+ * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L      CFG_DBAT5L
+#define CFG_IBAT5U      CFG_DBAT5U
+
+/* BAT6         32M    Cache-inhibited, guarded
+ * 0xfe00_0000  32M    FLASH
+ */
+#define CFG_DBAT6L      (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U      (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L      (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U      CFG_DBAT6U
+
+
+#define CFG_DBAT7L 0x00000000
+#define CFG_DBAT7U 0x00000000
+#define CFG_IBAT7L 0x00000000
+#define CFG_IBAT7U 0x00000000
+
+
+
+
+/*
+ * Environment
+ */
+ #ifndef CFG_RAMBOOT
+   #define CFG_ENV_IS_IN_FLASH	1
+   #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+   #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+   #define CFG_ENV_SIZE		0x2000
+ #else
+   #define CFG_NO_FLASH		1	/* Flash is not usable now */
+   #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+   #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+   #define CFG_ENV_SIZE		0x2000
+ #endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_IMLS	\
+				  | CFG_CMD_FLASH	\
+				  | CFG_CMD_LOADS))
+  #else
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				 | CFG_CMD_IMLS		\
+				 | CFG_CMD_FLASH	\
+				 | CFG_CMD_LOADS))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #else
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:E0:0C:00:00:01
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
+#endif
+
+#define   CONFIG_HAS_ETH1      1
+#define   CONFIG_HAS_ETH2      1
+#define   CONFIG_HAS_ETH3      1
+
+#define CONFIG_IPADDR    10.82.193.138
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		/opt/nfsroot
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_SERVERIP  10.82.193.104
+#define CONFIG_GATEWAYIP 10.82.193.254
+#define CONFIG_NETMASK   255.255.252.0
+
+#define CONFIG_LOADADDR  1000000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+//#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+#define CONFIG_BOOTARGS       "root=/dev/ram rw console=ttyS0,115200"
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=400000\0"						\
+   "ramdiskfile=your.ramdisk.u-boot\0"                                  \
+   "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \
+   "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \
+   "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \
+   "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \
+   "pex=run pexstat; run pex1; run pexd\0" \
+   "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+   "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+   "maxcpus=2"
+
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
-- 
cgit v1.1


From 5c9efb36a6b5431423f52888a0e3b4b515fe7eca Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Thu, 27 Apr 2006 10:15:16 -0500
Subject: Cleanup whitespaces and style issues. Removed //-style comments. Use
 80-column lines. Remove trailing whitespace. Remove dead code and debug
 cruft.

---
 include/configs/MPC8641HPCN.h | 203 +++++++++++++++++-------------------------
 1 file changed, 84 insertions(+), 119 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 8d2e088..76efd7c 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -1,5 +1,6 @@
-/*              
- * Copyright 2004 Freescale Semiconductor.
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -22,8 +23,7 @@
  */
 
 /*
- * mpc8641hpc3 board configuration file
- *
+ * MPC8641HPCN board configuration file
  *
  * Make sure you change the MAC address and other network params first,
  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
@@ -38,48 +38,38 @@
 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
-#undef DEBUG                   
+#undef DEBUG
 
-//#define RUN_DIAG             1   
 #ifdef RUN_DIAG
 #define CFG_DIAG_ADDR        0xff800000
 #endif
+
 #define CFG_RESET_ADDRESS    0xfff00100
 
-//#define CONFIG_PCI
+#undef CONFIG_PCI
+
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-/*#define CONFIG_DDR_ECC	*/		/* only for ECC DDR module */
-/*#define CONFIG_DDR_DLL	*/		/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
 
+#undef CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 #define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
+#define CONFIG_ALTIVEC          1
 
-#define CONFIG_ALTIVEC          1  
-/*-----------------------------------------------------------------------
+/*
  * L2CR setup -- make sure this is right for your board!
  */
-
-#define CFG_L2          
+#define CFG_L2
 #define L2_INIT		0
 #define L2_ENABLE	(L2CR_L2E)
 
 #ifndef CONFIG_SYS_CLK_FREQ
-//#define CONFIG_SYS_CLK_FREQ	33000000
 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
 #endif
 
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-/* JB - XXX - Are these available on 86xx? */
-#define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
-
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
 #undef	CFG_DRAM_TEST			/* memory test, takes time */
@@ -130,10 +120,10 @@
     #define CFG_DDR_INTERVAL	0x06090100
     #define CFG_DDR_DATA_INIT   0xdeadbeef
     #define CFG_DDR_CLK_CTRL    0x03800000
-    #define CFG_DDR_OCD_CTRL    0x00000000  
-    #define CFG_DDR_OCD_STATUS  0x00000000  
+    #define CFG_DDR_OCD_CTRL    0x00000000
+    #define CFG_DDR_OCD_STATUS  0x00000000
     #define CFG_DDR_CONTROL	0xe3008000	/* Type = DDR2 */
-    #define CFG_DDR_CONTROL2	0x04400000	
+    #define CFG_DDR_CONTROL2	0x04400000
 
     //Not used in fixed_sdram function
 
@@ -143,20 +133,12 @@
     #define CFG_DDR_CS3_BNDS	0x00000FFF  //Not done
     #define CFG_DDR_CS4_BNDS	0x00000FFF  //Not done
     #define CFG_DDR_CS5_BNDS	0x00000FFF  //Not done
-
-
-
 #endif
 #endif
 
 
 /*
- * SDRAM on the Local Bus
- */
-//#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-//#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
-
-/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000
+ * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000
  * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
  * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
  * However, when u-boot comes up, the flash_init needs hard start addresses
@@ -165,15 +147,12 @@
  * knows where the flash is and the user can download u-boot code from promjet to
  * fef00000 <- more intuitive than fe700000. Note that, on switching the boot
  * location, fef00000 becomes fff00000.
-*/
+ */
 #define CFG_FLASH_BASE          0xfe800000     /* start of FLASH 32M */
-#define CFG_FLASH_BASE2		0xff800000	
+#define CFG_FLASH_BASE2		0xff800000
 
 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
 
-
-/*Sri: This looks like a good place to init all the Local Bus chip selects*/
-
 #define CFG_BR0_PRELIM		0xff001001	/* port size 16bit */
 #define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Boot Flash area*/
 
@@ -186,25 +165,24 @@
 #define CFG_BR3_PRELIM		0xf8100801	/* port size 8bit */
 #define CFG_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
 
-#define PIXIS_BASE              0xf8100000      /* PIXIS registers*/
-#define PIXIS_ID                0x0               /* MPC8641HPCN Board ID at offset 0*/
-#define PIXIS_VER               0x1               /* MPC8641HPCN board version version at offset 1*/
-#define PIXIS_PVER              0x2               /* PIXIS FPGA version at offset 2*/
-#define PIXIS_RST               0x4               /* PIXIS Reset Control register*/
-#define PIXIS_AUX               0x6               /* PIXIS Auxiliary register; Scratch register */
-#define PIXIS_SPD               0x7               /* Register for SYSCLK speed */
-#define PIXIS_VCTL              0x10              /* VELA Control Register */
-#define PIXIS_VCFGEN0           0x12              /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1           0x13              /* VELA Config Enable 1 */
-#define PIXIS_VBOOT             0x16              /* VELA VBOOT Register */
-#define PIXIS_VSPEED0           0x17              /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1           0x18              /* VELA VSpeed 1 */
-#define PIXIS_VCLKH             0x19              /* VELA VCLKH register */
-#define PIXIS_VCLKL             0x1A              /* VELA VCLKL register */
 
+#define PIXIS_BASE	0xf8100000      /* PIXIS registers */
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
 
 #define CFG_MAX_FLASH_BANKS	2		/* number of banks */
-//#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
 #define CFG_MAX_FLASH_SECT	128		/* sectors per device */
 
 #undef	CFG_FLASH_CHECKSUM
@@ -212,11 +190,9 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
 
-/*#define CFG_HPCN_FLASH_CFI_DRIVER */
 #define CFG_FLASH_CFI
 #define CFG_FLASH_EMPTY_INFO
 
-
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
 #else
@@ -230,7 +206,7 @@
 #undef CONFIG_CLOCKS_IN_MHZ
 
 #define CONFIG_L1_INIT_RAM
-#undef CFG_INIT_RAM_LOCK 	
+#undef CFG_INIT_RAM_LOCK
 #ifndef CFG_INIT_RAM_LOCK
 #define CFG_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
 #else
@@ -265,20 +241,22 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
 
 /* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
+#define OF_FLAT_TREE_MAX_SIZE	8192
 
-#define OF_CPU   "PowerPC,8641@0"
-#define OF_SOC   "soc8641@f8000000"
-#define OF_TBCLK  (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH  "/soc8641@f8000000/serial@4500"
+#define OF_CPU		"PowerPC,8641@0"
+#define OF_SOC		"soc8641@f8000000"
+#define OF_TBCLK	(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH	"/soc8641@f8000000/serial@4500"
 
-#define CFG_64BIT_VSPRINTF 1
-#define CFG_64BIT_STRTOUL 1
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
 
 /* I2C */
 #define  CONFIG_HARD_I2C		/* I2C with hardware support*/
@@ -297,13 +275,10 @@
  * Addresses are mapped 1-1.
  */
 #define CFG_PCI1_MEM_BASE	0x80000000
-//#define CFG_PCI1_MEM_BASE	0xd0000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
 #define CFG_PCI1_IO_BASE	0xe2000000
-//#define CFG_PCI1_IO_BASE	0xe0000000
 #define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-//#define CFG_PCI1_IO_BUS         0x00000000
 #define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
 
 /* For RTL8139 */
@@ -316,29 +291,18 @@
 #define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
 #define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
 
-// #define CFG_PCI1_MEM_BASE	0x80000000
-// #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
-// #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-// #define CFG_PCI1_IO_BASE	0xe2000000
-// #define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-// #define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
-
-
 
 #if defined(CONFIG_PCI)
 
-
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
-//#define CFG_SCSI_SCAN_BUS_REVERSE
-
+#undef CFG_SCSI_SCAN_BUS_REVERSE
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
 
 #define CONFIG_RTL8139
 
-
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
@@ -349,7 +313,6 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-//#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
@@ -371,7 +334,6 @@
 #define CONFIG_MPC86XX_TSEC4    1
 #define CONFIG_MPC86XX_TSEC4_NAME       "eTSEC4"
 
-
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC3_PHY_ADDR		2
@@ -389,12 +351,10 @@
 /* BAT0         2G     Cacheable, non-guarded
  * 0x0000_0000  2G     DDR
  */
-//#define CFG_DBAT0L      (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_DBAT0L      (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE)
-#define CFG_DBAT0U      (0x0 | BATU_BL_512M | BATU_VS | BATU_VP)
-//#define CFG_IBAT0L      CFG_DBAT0L
-//#define CFG_IBAT0L      (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0L      (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
+#define CFG_DBAT0L      ( BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE )
+#define CFG_DBAT0U      ( BATU_BL_512M | BATU_VS | BATU_VP )
+#define CFG_IBAT0L      ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
 #define CFG_IBAT0U      CFG_DBAT0U
 
 /* BAT1         1G     Cache-inhibited, guarded
@@ -402,7 +362,8 @@
  * 0xa000_0000  512M   PCI-Express 2 Memory
  ** SS - Changed it for operating from 0xd0000000
  */
-#define CFG_DBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1L      ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT1U      (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CFG_IBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT1U      CFG_DBAT1U
@@ -410,7 +371,8 @@
 /* BAT2         512M   Cache-inhibited, guarded
  * 0xc000_0000  512M   RapidIO Memory
  */
-#define CFG_DBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT2U      (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
 #define CFG_IBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT2U      CFG_DBAT2U
@@ -418,7 +380,8 @@
 /* BAT3         4M     Cache-inhibited, guarded
  * 0xf800_0000  4M     CCSR
  */
-#define CFG_DBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3L      ( CFG_CCSRBAR | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT3U      (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
 #define CFG_IBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT3U      CFG_DBAT3U
@@ -428,7 +391,8 @@
  * 0xe300_0000  16M    PCI-Express 2 I/0
  ** SS - Note that this is at 0xe0000000
  */
-#define CFG_DBAT4L      (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4L      ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT4U      (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 #define CFG_IBAT4L      (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT4U      CFG_DBAT4U
@@ -444,12 +408,12 @@
 /* BAT6         32M    Cache-inhibited, guarded
  * 0xfe00_0000  32M    FLASH
  */
-#define CFG_DBAT6L      (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6L      ( CFG_FLASH_BASE | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT6U      (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 #define CFG_IBAT6L      (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CFG_IBAT6U      CFG_DBAT6U
 
-
 #define CFG_DBAT7L 0x00000000
 #define CFG_DBAT7U 0x00000000
 #define CFG_IBAT7L 0x00000000
@@ -461,17 +425,17 @@
 /*
  * Environment
  */
- #ifndef CFG_RAMBOOT
-   #define CFG_ENV_IS_IN_FLASH	1
-   #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-   #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
-   #define CFG_ENV_SIZE		0x2000
- #else
-   #define CFG_NO_FLASH		1	/* Flash is not usable now */
-   #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-   #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-   #define CFG_ENV_SIZE		0x2000
- #endif
+#ifndef CFG_RAMBOOT
+    #define CFG_ENV_IS_IN_FLASH	1
+    #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+    #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+    #define CFG_ENV_SIZE		0x2000
+#else
+    #define CFG_NO_FLASH		1	/* Flash is not usable now */
+    #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+    #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+    #define CFG_ENV_SIZE		0x2000
+#endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
@@ -572,24 +536,25 @@
 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 #endif
 
-#define   CONFIG_HAS_ETH1      1
-#define   CONFIG_HAS_ETH2      1
-#define   CONFIG_HAS_ETH3      1
+#define CONFIG_HAS_ETH1		1
+#define CONFIG_HAS_ETH2		1
+#define CONFIG_HAS_ETH3		1
 
-#define CONFIG_IPADDR    10.82.193.138
+#define CONFIG_IPADDR	10.82.193.138
 
 #define CONFIG_HOSTNAME		unknown
 #define CONFIG_ROOTPATH		/opt/nfsroot
 #define CONFIG_BOOTFILE		uImage
 
-#define CONFIG_SERVERIP  10.82.193.104
-#define CONFIG_GATEWAYIP 10.82.193.254
-#define CONFIG_NETMASK   255.255.252.0
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	10.82.193.104
+#define CONFIG_NETMASK		255.255.255.0
 
-#define CONFIG_LOADADDR  1000000	/* default location for tftp and bootm */
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
 
 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
-//#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+//#undef  CONFIG_BOOTARGS	/* the boot command will set bootargs */
 #define CONFIG_BOOTARGS       "root=/dev/ram rw console=ttyS0,115200"
 
 #define CONFIG_BAUDRATE	115200
@@ -599,7 +564,7 @@
    "consoledev=ttyS0\0"                                                 \
    "ramdiskaddr=400000\0"						\
    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
-   "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \
+   "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\
    "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \
    "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \
    "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \
-- 
cgit v1.1


From 18b6c8cd8af6cc7f35180cedc4adb3236cc1a1b8 Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Tue, 9 May 2006 08:23:49 -0500
Subject: Get MPC8641HPCN flash images working.

    Enable the CFI driver.
    Remove bogus LAWBAR7 cruft.
    Use correct TEXT_BASE, Fixup load script.
    Enable SPD EEPROM during DDR setup.
    Use generic RFC 1918 IP addresses by default.
---
 include/configs/MPC8641HPCN.h | 30 ++++++++++++++----------------
 1 file changed, 14 insertions(+), 16 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 76efd7c..d4a28ed 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -51,6 +51,7 @@
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #undef CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 #define CONFIG_DDR_ECC			/* only for ECC DDR module */
@@ -102,11 +103,9 @@
 
 #else
     /*
-     * Manually set up DDR parameters
+     * Manually set up DDR1 parameters
      */
 
-/* DDR I */
-#if 1
     #define CFG_SDRAM_SIZE	256		/* DDR is 256MB */
 
     #define CFG_DDR_CS0_BNDS	0x0000000F
@@ -125,15 +124,14 @@
     #define CFG_DDR_CONTROL	0xe3008000	/* Type = DDR2 */
     #define CFG_DDR_CONTROL2	0x04400000
 
-    //Not used in fixed_sdram function
+    /* Not used in fixed_sdram function */
 
     #define CFG_DDR_MODE	0x00000022
     #define CFG_DDR_CS1_BNDS	0x00000000
-    #define CFG_DDR_CS2_BNDS	0x00000FFF  //Not done
-    #define CFG_DDR_CS3_BNDS	0x00000FFF  //Not done
-    #define CFG_DDR_CS4_BNDS	0x00000FFF  //Not done
-    #define CFG_DDR_CS5_BNDS	0x00000FFF  //Not done
-#endif
+    #define CFG_DDR_CS2_BNDS	0x00000FFF	/* Not done */
+    #define CFG_DDR_CS3_BNDS	0x00000FFF	/* Not done */
+    #define CFG_DDR_CS4_BNDS	0x00000FFF	/* Not done */
+    #define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
 #endif
 
 
@@ -190,6 +188,7 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
 
+#define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
 #define CFG_FLASH_EMPTY_INFO
 
@@ -199,14 +198,14 @@
 #undef  CFG_RAMBOOT
 #endif
 
-#if !defined(CFG_RAMBOOT)
-#define CONFIG_SPD_EEPROM        	/* Use SPD EEPROM for DDR setup*/
+#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT)
+#undef CONFIG_SPD_EEPROM        	/* Use SPD EEPROM for DDR setup*/
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
 #define CONFIG_L1_INIT_RAM
-#undef CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_LOCK	1
 #ifndef CFG_INIT_RAM_LOCK
 #define CFG_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
 #else
@@ -540,22 +539,21 @@
 #define CONFIG_HAS_ETH2		1
 #define CONFIG_HAS_ETH3		1
 
-#define CONFIG_IPADDR	10.82.193.138
+#define CONFIG_IPADDR		192.168.1.100
 
 #define CONFIG_HOSTNAME		unknown
 #define CONFIG_ROOTPATH		/opt/nfsroot
 #define CONFIG_BOOTFILE		uImage
 
 #define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	10.82.193.104
+#define CONFIG_GATEWAYIP	192.168.1.1
 #define CONFIG_NETMASK		255.255.255.0
 
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
-//#undef  CONFIG_BOOTARGS	/* the boot command will set bootargs */
-#define CONFIG_BOOTARGS       "root=/dev/ram rw console=ttyS0,115200"
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
 
-- 
cgit v1.1


From 586d1d5abd3e525f1e1d9b81e5a61a4da6b2fa3c Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@jdl.com>
Date: Fri, 19 May 2006 13:22:44 -0500
Subject: Update 86xx address map and LAWBARs.

---
 include/configs/MPC8641HPCN.h | 52 ++++++++++++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 20 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index d4a28ed..aaf99c1 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -136,15 +136,16 @@
 
 
 /*
- * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000
- * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
+ * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
+ * There is an 8MB flash.  In effect, the addresses from fe000000 to fe7fffff
  * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
  * However, when u-boot comes up, the flash_init needs hard start addresses
- * to build its info table. For user convenience, we have the flash addresses
- * as fe800000 and ff800000. That way, when we do flash operations, u-boot
- * knows where the flash is and the user can download u-boot code from promjet to
- * fef00000 <- more intuitive than fe700000. Note that, on switching the boot
- * location, fef00000 becomes fff00000.
+ * to build its info table.  For user convenience, the flash addresses is
+ * fe800000 and ff800000.  That way, u-boot knows where the flash is
+ * and the user can download u-boot code from promjet to fef00000, a
+ * more intuitive location than fe700000.
+ *
+ * Note that, on switching the boot location, fef00000 becomes fff00000.
  */
 #define CFG_FLASH_BASE          0xfe800000     /* start of FLASH 32M */
 #define CFG_FLASH_BASE2		0xff800000
@@ -257,14 +258,18 @@
 #define CFG_64BIT_VSPRINTF	1
 #define CFG_64BIT_STRTOUL	1
 
-/* I2C */
+/*
+ * I2C
+ */
 #define  CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
 
-/* RapidIO MMU */
+/*
+ * RapidIO MMU
+ */
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
 #define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
 #define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
@@ -347,19 +352,21 @@
 #endif	/* CONFIG_TSEC_ENET */
 
 
-/* BAT0         2G     Cacheable, non-guarded
+/*
+ * BAT0         2G     Cacheable, non-guarded
  * 0x0000_0000  2G     DDR
  */
 #define CFG_DBAT0L      ( BATL_PP_RW | BATL_CACHEINHIBIT \
 			| BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE )
-#define CFG_DBAT0U      ( BATU_BL_512M | BATU_VS | BATU_VP )
+#define CFG_DBAT0U      ( BATU_BL_2G | BATU_VS | BATU_VP )
 #define CFG_IBAT0L      ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
 #define CFG_IBAT0U      CFG_DBAT0U
 
-/* BAT1         1G     Cache-inhibited, guarded
+/*
+ * BAT1         1G     Cache-inhibited, guarded
  * 0x8000_0000  512M   PCI-Express 1 Memory
  * 0xa000_0000  512M   PCI-Express 2 Memory
- ** SS - Changed it for operating from 0xd0000000
+ *	Changed it for operating from 0xd0000000
  */
 #define CFG_DBAT1L      ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
@@ -367,7 +374,8 @@
 #define CFG_IBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT1U      CFG_DBAT1U
 
-/* BAT2         512M   Cache-inhibited, guarded
+/*
+ * BAT2         512M   Cache-inhibited, guarded
  * 0xc000_0000  512M   RapidIO Memory
  */
 #define CFG_DBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW \
@@ -376,7 +384,8 @@
 #define CFG_IBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT2U      CFG_DBAT2U
 
-/* BAT3         4M     Cache-inhibited, guarded
+/*
+ * BAT3         4M     Cache-inhibited, guarded
  * 0xf800_0000  4M     CCSR
  */
 #define CFG_DBAT3L      ( CFG_CCSRBAR | BATL_PP_RW \
@@ -385,10 +394,11 @@
 #define CFG_IBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT3U      CFG_DBAT3U
 
-/* BAT4         32M    Cache-inhibited, guarded
+/*
+ * BAT4         32M    Cache-inhibited, guarded
  * 0xe200_0000  16M    PCI-Express 1 I/O
  * 0xe300_0000  16M    PCI-Express 2 I/0
- ** SS - Note that this is at 0xe0000000
+ *    Note that this is at 0xe0000000
  */
 #define CFG_DBAT4L      ( CFG_PCI1_IO_BASE | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
@@ -396,7 +406,8 @@
 #define CFG_IBAT4L      (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT4U      CFG_DBAT4U
 
-/* BAT5         128K   Cacheable, non-guarded
+/*
+ * BAT5         128K   Cacheable, non-guarded
  * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
  */
 #define CFG_DBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
@@ -404,7 +415,8 @@
 #define CFG_IBAT5L      CFG_DBAT5L
 #define CFG_IBAT5U      CFG_DBAT5U
 
-/* BAT6         32M    Cache-inhibited, guarded
+/*
+ * BAT6         32M    Cache-inhibited, guarded
  * 0xfe00_0000  32M    FLASH
  */
 #define CFG_DBAT6L      ( CFG_FLASH_BASE | BATL_PP_RW \
@@ -427,7 +439,7 @@
 #ifndef CFG_RAMBOOT
     #define CFG_ENV_IS_IN_FLASH	1
     #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
-    #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+    #define CFG_ENV_SECT_SIZE		0x40000	/* 256K(one sector) for env */
     #define CFG_ENV_SIZE		0x2000
 #else
     #define CFG_NO_FLASH		1	/* Flash is not usable now */
-- 
cgit v1.1


From 9a655876e5995be80f49054e2509500e871e4d3a Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@jdl.com>
Date: Fri, 19 May 2006 13:26:34 -0500
Subject: Enable dual DDR controllers and interleaving.

---
 include/configs/MPC8641HPCN.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index aaf99c1..2a197be 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -57,6 +57,13 @@
 #define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS     2
+/* #define CONFIG_DDR_INTERLEAVE               1 */
+#define CACHE_LINE_INTERLEAVING		0x20000000
+#define PAGE_INTERLEAVING		0x21000000
+#define BANK_INTERLEAVING		0x22000000
+#define SUPER_BANK_INTERLEAVING		0x23000000
+
 
 #define CONFIG_ALTIVEC          1
 
@@ -99,7 +106,10 @@
     /*
      * Determine DDR configuration from I2C interface.
      */
-    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS1		0x51		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS2		0x52		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS3		0x53		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS4		0x54		/* DDR DIMM */
 
 #else
     /*
-- 
cgit v1.1


From fa7db9c377bc2353a17bf1d381d65a6c418728f0 Mon Sep 17 00:00:00 2001
From: Jin Zhengxiong-R64188 <Jason.Jin@freescale.com>
Date: Tue, 27 Jun 2006 18:11:54 +0800
Subject: Enable PCIE1 for MPC8641HPCN board

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
---
 include/configs/MPC8641HPCN.h | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 2a197be..4453171 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -46,7 +46,8 @@
 
 #define CFG_RESET_ADDRESS    0xfff00100
 
-#undef CONFIG_PCI
+/*#undef CONFIG_PCI*/
+#define CONFIG_PCI
 
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
@@ -209,8 +210,10 @@
 #undef  CFG_RAMBOOT
 #endif
 
-#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT)
-#undef CONFIG_SPD_EEPROM        	/* Use SPD EEPROM for DDR setup*/
+#if defined(CFG_RAMBOOT)
+#undef CFG_FLASH_CFI_DRIVER
+#undef CONFIG_SPD_EEPROM
+#define CFG_SDRAM_SIZE	256
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
@@ -295,6 +298,11 @@
 #define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
 #define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
 
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS      0x00000000
+#define CFG_PCI_MEMORY_PHYS     0x00000000
+#define CFG_PCI_MEMORY_SIZE     0x80000000
+
 /* For RTL8139 */
 #define _IO_BASE                0x00000000
 
@@ -429,10 +437,10 @@
  * BAT6         32M    Cache-inhibited, guarded
  * 0xfe00_0000  32M    FLASH
  */
-#define CFG_DBAT6L      ( CFG_FLASH_BASE | BATL_PP_RW \
+#define CFG_DBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U      (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT6L      (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT6U      ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CFG_IBAT6U      CFG_DBAT6U
 
 #define CFG_DBAT7L 0x00000000
-- 
cgit v1.1


From bc09cf3c2bfb8d54c659cbb332f79d0950982fd0 Mon Sep 17 00:00:00 2001
From: Jin Zhengxiong-R64188 <Jason.Jin@freescale.com>
Date: Tue, 27 Jun 2006 18:12:10 +0800
Subject: Fix RTL8139 in big endian

signed-off-by: Jason Jin <Jason.Jin@freescale.com>
signed-off-by: Wei Zhang <wei.zhang@freescale.com>
---
 include/configs/MPC8641HPCN.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 4453171..b089769 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -304,6 +304,7 @@
 #define CFG_PCI_MEMORY_SIZE     0x80000000
 
 /* For RTL8139 */
+#define KSEG1ADDR(x)		({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 #define _IO_BASE                0x00000000
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
-- 
cgit v1.1


From fcb28e763415e0e4e66b0f45842d1557ae198e5e Mon Sep 17 00:00:00 2001
From: Jin Zhengxiong <Jason.Jin@freescale.com>
Date: Thu, 13 Jul 2006 10:35:10 -0500
Subject: Fixed initrd issue by define big RAM

Signed-off-by:Jason Jin <Jason.jin@freescale.com>
---
 include/configs/MPC8641HPCN.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index b089769..aca2ecc 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -100,6 +100,7 @@
  */
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 
-- 
cgit v1.1


From bea3f28d285942bf3f7ab339ce85178ded544225 Mon Sep 17 00:00:00 2001
From: Haiying Wang <haiying.wang@freescale.com>
Date: Wed, 12 Jul 2006 10:48:05 -0400
Subject: Add support for reading and writing mac addresses to or from ID
 EEPROM.

Added code for reading and writing Mac addresses to/from ID EEPROM(0x57).
With attached patch, we can use command "mac/mac read/mac save/"
to read and write EEPROM under u-boot prompt.

U-boot will calculate the checksum of EEPROM while bootup,
if it is right, then u-boot will check whether the mac address
of eTSEC0/1/2/3 is availalbe (non-zero).

If there is mac address availabe in EEPROM, u-boot will use it,
otherewise, u-boot will use the mac address defined in
MPC8641HPCN.h. This matches the requirement to set unique mac address
for each TSEC port.

Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---
 include/configs/MPC8641HPCN.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index aca2ecc..7e91e64 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -146,6 +146,8 @@
     #define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
 #endif
 
+#define CFG_ID_EEPROM	1
+#define ID_EEPROM_ADDR 0x57
 
 /*
  * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
-- 
cgit v1.1


From 515ab8a62e8574e2babc6e8dcc43544ad221c5b2 Mon Sep 17 00:00:00 2001
From: John Traill <john.traill@freescale.com>
Date: Fri, 28 Jul 2006 08:16:06 +0100
Subject: Fix 8641HPCN timebase

---
 include/configs/MPC8641HPCN.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 7e91e64..15e9871 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -268,7 +268,7 @@
 
 #define OF_CPU		"PowerPC,8641@0"
 #define OF_SOC		"soc8641@f8000000"
-#define OF_TBCLK	(bd->bi_busfreq / 8)
+#define OF_TBCLK	(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH	"/soc8641@f8000000/serial@4500"
 
 #define CFG_64BIT_VSPRINTF	1
-- 
cgit v1.1


From 0e16387db1d4aacd5bf35cb6d7c1942765c0347b Mon Sep 17 00:00:00 2001
From: Matthew McClintock <msm@freescale.com>
Date: Wed, 28 Jun 2006 10:43:36 -0500
Subject: * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch
 by Jon Loeliger 17-Jan-2006

Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 include/configs/MPC8540ADS.h | 15 +++++++++++++++
 include/configs/MPC8541CDS.h | 12 ++++++++++++
 include/configs/MPC8548CDS.h | 12 ++++++++++++
 include/configs/MPC8555CDS.h | 12 ++++++++++++
 include/configs/MPC8560ADS.h | 12 ++++++++++++
 5 files changed, 63 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 131c832..d31a18b 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -293,6 +293,21 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8540@0"
+#define OF_SOC			"soc8540@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8540@e0000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
 /* I2C */
 #define  CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index c96b98b..86bcfe3 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8541@0"
+#define OF_SOC			"soc8541@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8541@e0000000/serial@4500"
+
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 4ca8bc3..b1f8a19 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -314,6 +314,18 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8548@0"
+#define OF_SOC			"soc8548@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8548@e0000000/serial@4500"
+
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index a44e3ec..b725dac 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8555@0"
+#define OF_SOC			"soc8555@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8555@e0000000/serial@4500"
+
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 2d5031b..1c684f2 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -290,6 +290,18 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8560@0"
+#define OF_SOC			"soc8560@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc8560@e0000000/serial@4500"
+
 /* I2C */
 #define  CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-- 
cgit v1.1


From c88f9fe66b64247e5b6a38410ba315ca25596d16 Mon Sep 17 00:00:00 2001
From: Matthew McClintock <msm@freescale.com>
Date: Wed, 28 Jun 2006 10:45:41 -0500
Subject: * Fixed PCI memory definitions Patch by Andy Fleming 17-Mar-2006

Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 include/configs/MPC8540ADS.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index d31a18b..81ee945 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -71,7 +71,7 @@
  */
 
 #ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	33000000
+#define CONFIG_SYS_CLK_FREQ	66000000
 #endif
 
 
@@ -327,9 +327,10 @@
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CFG_PCI1_IO_BASE	0x0
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x100000	/* 1M */
 
 #if defined(CONFIG_PCI)
 
-- 
cgit v1.1


From bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452 Mon Sep 17 00:00:00 2001
From: Matthew McClintock <msm@freescale.com>
Date: Wed, 28 Jun 2006 10:46:13 -0500
Subject: * Added VIA configuration table

* Added support for PCI2 on CDS
  Patch by Andy Fleming 17-Mar-2006

Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 include/configs/MPC8541CDS.h | 21 ++++++++-------------
 include/configs/MPC8548CDS.h | 23 +++++++++--------------
 include/configs/MPC8555CDS.h | 23 +++++++++--------------
 3 files changed, 26 insertions(+), 41 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 86bcfe3..f73caf0 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void);
 #define OF_CPU			"PowerPC,8541@0"
 #define OF_SOC			"soc8541@e0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH		"/soc8541@e0000000/serial@4500"
+#define OF_STDOUT_PATH		"/soc8541@e0000000/serial@4600"
 
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
@@ -335,32 +335,27 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x100000	/* 1M */
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
 #define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0xe3000000
-#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe2100000
+#define CFG_PCI2_IO_SIZE	0x100000	/* 1M */
 
 
 #if defined(CONFIG_PCI)
 
+#define CONFIG_MPC85XX_PCI2
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
-#if !defined(CONFIG_PCI_PNP)
-    #define PCI_ENET0_IOADDR      0xe0000000
-    #define PCI_ENET0_MEMADDR     0xe0000000
-    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
-#endif
-
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index b1f8a19..37b518c 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -324,7 +324,7 @@ extern unsigned long get_clock_freq(void);
 #define OF_CPU			"PowerPC,8548@0"
 #define OF_SOC			"soc8548@e0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH		"/soc8548@e0000000/serial@4500"
+#define OF_STDOUT_PATH		"/soc8548@e0000000/serial@4600"
 
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
@@ -341,32 +341,27 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
 #define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0xe3000000
-#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe2100000
+#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
 
 
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_85XX_PCI2
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
-#if !defined(CONFIG_PCI_PNP)
-    #define PCI_ENET0_IOADDR      0xe0000000
-    #define PCI_ENET0_MEMADDR     0xe0000000
-    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
-#endif
-
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
@@ -386,7 +381,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
 #define CONFIG_MPC85XX_TSEC3	1
 #define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC2"
-#define CONFIG_MPC85XX_TSEC4	1
+#undef CONFIG_MPC85XX_TSEC4
 #define CONFIG_MPC85XX_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index b725dac..b94e38a 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void);
 #define OF_CPU			"PowerPC,8555@0"
 #define OF_SOC			"soc8555@e0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH		"/soc8555@e0000000/serial@4500"
+#define OF_STDOUT_PATH		"/soc8555@e0000000/serial@4600"
 
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
@@ -335,33 +335,28 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI1_MEM_BASE	0x80000000
 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI1_IO_BASE	0xe2000000
-#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #define CFG_PCI2_MEM_BASE	0xa0000000
 #define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
 #define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
-#define CFG_PCI2_IO_BASE	0xe3000000
-#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe2100000
+#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
 
 
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#define CONFIG_MPC85XX_PCI2
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
-#if !defined(CONFIG_PCI_PNP)
-    #define PCI_ENET0_IOADDR      0xe0000000
-    #define PCI_ENET0_MEMADDR     0xe0000000
-    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
-- 
cgit v1.1


From 34c3c0e01dbf1f8cc2bd08de92f2b89ba84921eb Mon Sep 17 00:00:00 2001
From: Matthew McClintock <msm@freescale.com>
Date: Wed, 28 Jun 2006 10:47:03 -0500
Subject: * Switched default PCI speed for 8540 ADS back to 33MHz

* Added comments and a printf to warn that PCI-X won't
  work at 33MHz
  Patch by Andy Fleming 17-Mar-2006

Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 include/configs/MPC8540ADS.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 81ee945..8e4d2c9 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -68,10 +68,14 @@
  * The board, however, can run at 66MHz.  In any event, this value
  * must match the settings of some switches.  Details can be found
  * in the README.mpc85xxads.
+ *
+ * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
+ * 33MHz to accommodate, based on a PCI pin.
+ * Note that PCI-X won't work at 33MHz.
  */
 
 #ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	66000000
+#define CONFIG_SYS_CLK_FREQ	33000000
 #endif
 
 
-- 
cgit v1.1


From fecf1c7e4de1b2779edc18742b91c22bdc32b68b Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Mon, 14 Aug 2006 15:33:38 -0500
Subject: Fix BAT0 to actually be cacheable, non-guarded as documented.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 include/configs/MPC8641HPCN.h | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 15e9871..200a38f 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -378,10 +378,9 @@
  * BAT0         2G     Cacheable, non-guarded
  * 0x0000_0000  2G     DDR
  */
-#define CFG_DBAT0L      ( BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE )
-#define CFG_DBAT0U      ( BATU_BL_2G | BATU_VS | BATU_VP )
-#define CFG_IBAT0L      ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
+#define CFG_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
 #define CFG_IBAT0U      CFG_DBAT0U
 
 /*
-- 
cgit v1.1


From d8ea2acf5f137cae99417df4f573d036ee384668 Mon Sep 17 00:00:00 2001
From: Zhang Wei <wei.zhang@freescale.com>
Date: Wed, 23 Aug 2006 17:54:32 +0800
Subject: Add dtb boot-up parameter to default boot commands.

Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
---
 include/configs/MPC8641HPCN.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 200a38f..1f5e2df 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -595,6 +595,8 @@
    "consoledev=ttyS0\0"                                                 \
    "ramdiskaddr=400000\0"						\
    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
+   "dtbaddr=2000000\0"						\
+   "dtbfile=mpc8641_hpcn.dtb\0"                                  \
    "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\
    "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \
    "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \
@@ -611,14 +613,16 @@
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr"
+   "tftp $dtbaddr $dtbfile;"                                          \
+   "bootm $loadaddr - $dtbaddr"
 
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "                                  \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $ramdiskaddr $ramdiskfile;"                                    \
    "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr $ramdiskaddr"
+   "tftp $dtbaddr $dtbfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr $dtbaddr"
 
 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 
-- 
cgit v1.1


From dabf9ef8c10b4dead5ef2106ef742b1c06b542de Mon Sep 17 00:00:00 2001
From: Jin Zhengxiong <jason@bus.ap.freescale.net>
Date: Wed, 23 Aug 2006 19:15:12 +0800
Subject: Add AHCI define and sata support for MPC8641HPCN board.

Signed-off-by:Jason Jin<jason.jin@freescale.com>
---
 include/configs/MPC8641HPCN.h | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 1f5e2df..7097b3e 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -340,6 +340,17 @@
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID	4
+#define CFG_SCSI_MAX_LUN	1
+#define CFG_SCSI_MAX_DEVICE 	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
+#endif
+
 #endif	/* CONFIG_PCI */
 
 
@@ -477,7 +488,9 @@
     #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
 				 | CFG_CMD_PING		\
 				 | CFG_CMD_PCI		\
-				 | CFG_CMD_I2C)		\
+				 | CFG_CMD_I2C		\
+				 | CFG_CMD_SCSI		\
+				 | CFG_CMD_EXT2)	\
 				&			\
 				 ~(CFG_CMD_ENV		\
 				  | CFG_CMD_IMLS	\
@@ -486,7 +499,9 @@
   #else
     #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
 				 | CFG_CMD_PING		\
-				 | CFG_CMD_I2C)		\
+				 | CFG_CMD_I2C		\
+				 | CFG_CMD_SCSI		\
+				 | CGF_CMD_EXT2)	\
 				&			\
 				 ~(CFG_CMD_ENV		\
 				 | CFG_CMD_IMLS		\
@@ -498,7 +513,9 @@
     #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
 				| CFG_CMD_PCI		\
 				| CFG_CMD_PING		\
-				| CFG_CMD_I2C)
+				| CFG_CMD_I2C		\
+				| CFG_CMD_SCSI		\
+				| CFG_CMD_EXT2)
   #else
     #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
 				| CFG_CMD_PING		\
-- 
cgit v1.1


From 5567806b67d0ae83493aa8823ad3b6c914f581d7 Mon Sep 17 00:00:00 2001
From: Haiying Wang <haiying.wang@freescale.com>
Date: Fri, 25 Aug 2006 14:38:34 -0400
Subject: Change ramdiskaddr and dtbaddr Remove PEX fluff commands.

Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 include/configs/MPC8641HPCN.h | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 7097b3e..c704d46 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -610,15 +610,10 @@
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS0\0"                                                 \
-   "ramdiskaddr=400000\0"						\
+   "ramdiskaddr=2000000\0"						\
    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
-   "dtbaddr=2000000\0"						\
+   "dtbaddr=400000\0"						\
    "dtbfile=mpc8641_hpcn.dtb\0"                                  \
-   "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\
-   "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \
-   "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \
-   "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \
-   "pex=run pexstat; run pex1; run pexd\0" \
    "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
    "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
    "maxcpus=2"
-- 
cgit v1.1


From 09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3 Mon Sep 17 00:00:00 2001
From: Andy Fleming <afleming@freescale.com>
Date: Wed, 13 Sep 2006 10:34:18 -0500
Subject: Add support for eTSEC 3 & 4 on 8548 CDS

* Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS.
  This will only work on rev 1.3 boards (but doesn't break older boards)
* Cleaned up some comments to reflect the expanded role of tsec
  in other systems
---
 include/configs/MPC8548CDS.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 37b518c..767ab33 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -381,7 +381,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
 #define CONFIG_MPC85XX_TSEC3	1
 #define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC2"
-#undef CONFIG_MPC85XX_TSEC4
+#define CONFIG_MPC85XX_TSEC4	1
 #define CONFIG_MPC85XX_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
@@ -483,6 +483,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 #define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 #endif
 
 #define CONFIG_IPADDR    192.168.1.253
-- 
cgit v1.1


From 8272dc2f58f2473d8995fcc9b916440cfba080f0 Mon Sep 17 00:00:00 2001
From: Andy Fleming <afleming@freescale.com>
Date: Wed, 13 Sep 2006 10:33:35 -0500
Subject: Updated config headers to add default FDT-based booting

---
 include/configs/MPC8540ADS.h | 10 +++++++---
 include/configs/MPC8541CDS.h |  9 ++++++---
 include/configs/MPC8548CDS.h | 13 ++++++++-----
 include/configs/MPC8555CDS.h |  9 ++++++---
 4 files changed, 27 insertions(+), 14 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 8e4d2c9..31ffbaf 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -517,8 +517,10 @@
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS0\0"                                                 \
-   "ramdiskaddr=400000\0"						\
-   "ramdiskfile=your.ramdisk.u-boot\0"
+   "ramdiskaddr=600000\0"						\
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
@@ -526,13 +528,15 @@
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr"
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "                                  \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $ramdiskaddr $ramdiskfile;"                                    \
    "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
    "bootm $loadaddr $ramdiskaddr"
 
 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index f73caf0..2b87f1b 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void);
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS1\0"                                                 \
-   "ramdiskaddr=400000\0"                                               \
-   "ramdiskfile=your.ramdisk.u-boot\0"
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
@@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void);
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr"
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "                                  \
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 767ab33..03ab976 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -389,13 +389,11 @@ extern unsigned long get_clock_freq(void);
 #define TSEC2_PHY_ADDR		1
 #define TSEC3_PHY_ADDR		2
 #define TSEC4_PHY_ADDR		3
-#define FEC_PHY_ADDR		3
 
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define TSEC3_PHYIDX		0
 #define TSEC4_PHYIDX		0
-#define FEC_PHYIDX		0
 
 /* Options are: eTSEC[0-3] */
 #define CONFIG_ETHPRIME		"eTSEC0"
@@ -507,8 +505,11 @@ extern unsigned long get_clock_freq(void);
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS1\0"                                                 \
-   "ramdiskaddr=400000\0"                                               \
-   "ramdiskfile=your.ramdisk.u-boot\0"
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
+
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
@@ -516,7 +517,9 @@ extern unsigned long get_clock_freq(void);
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr"
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
 
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "                                  \
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index b94e38a..771a9d3 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void);
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS1\0"                                                 \
-   "ramdiskaddr=400000\0"                                               \
-   "ramdiskfile=your.ramdisk.u-boot\0"
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
@@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void);
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
       "console=$consoledev,$baudrate $othbootargs;"                     \
    "tftp $loadaddr $bootfile;"                                          \
-   "bootm $loadaddr"
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "                                  \
-- 
cgit v1.1


From 8b283dbb3a08d1b8d406bc15f119e081b3e2606a Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Tue, 10 Oct 2006 17:16:04 -0500
Subject: Fix whitespace issues.

---
 include/configs/MPC8641HPCN.h | 9 ---------
 1 file changed, 9 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index c704d46..6e883f7 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -85,7 +85,6 @@
 #define CFG_MEMTEST_START	0x00200000	/* memtest region */
 #define CFG_MEMTEST_END		0x00400000
 
-
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
@@ -94,7 +93,6 @@
 #define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
-
 /*
  * DDR Setup
  */
@@ -317,7 +315,6 @@
 #define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
 #define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
 
-
 #if defined(CONFIG_PCI)
 
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
@@ -353,7 +350,6 @@
 
 #endif	/* CONFIG_PCI */
 
-
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
@@ -384,7 +380,6 @@
 
 #endif	/* CONFIG_TSEC_ENET */
 
-
 /*
  * BAT0         2G     Cacheable, non-guarded
  * 0x0000_0000  2G     DDR
@@ -462,9 +457,6 @@
 #define CFG_IBAT7L 0x00000000
 #define CFG_IBAT7U 0x00000000
 
-
-
-
 /*
  * Environment
  */
@@ -572,7 +564,6 @@
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
-
 /*
  * Environment Configuration
  */
-- 
cgit v1.1


From 7237c033b02fe295880435f1eb80819a0c987532 Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Thu, 19 Oct 2006 11:02:16 -0500
Subject: Moved i2c driver out of cpu/mpc86xx/i2c.c into drivers/fsl_i2c.c

in an effort to begin to unify the umpteen FSL I2C drivers that
are all otherwise very similar.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 include/configs/MPC8641HPCN.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include/configs')

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 6e883f7..81bb7cf 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -279,6 +279,7 @@
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_OFFSET		0x3100
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
 
 /*
-- 
cgit v1.1


From 2047672684cf85cb6f96a1fbc993180aaaf19a99 Mon Sep 17 00:00:00 2001
From: Jon Loeliger <jdl@freescale.com>
Date: Fri, 20 Oct 2006 15:50:15 -0500
Subject: Converted all 85xx boards to use a common FSL I2C driver. Introduced
 COFIG_FSL_I2C to select the common FSL I2C driver. And removed hard i2c path
 from a few u-boot.lds scipts too. Minor whitespace cleanups along the way.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 include/configs/MPC8540ADS.h  | 8 ++++++--
 include/configs/MPC8540EVAL.h | 8 ++++++--
 include/configs/MPC8541CDS.h  | 8 ++++++--
 include/configs/MPC8548CDS.h  | 8 ++++++--
 include/configs/MPC8555CDS.h  | 8 ++++++--
 include/configs/MPC8560ADS.h  | 8 ++++++--
 include/configs/MPC8641HPCN.h | 5 +++--
 include/configs/PM854.h       | 8 ++++++--
 include/configs/PM856.h       | 8 ++++++--
 include/configs/SBC8540.h     | 8 ++++++--
 include/configs/TQM85xx.h     | 7 ++++++-
 include/configs/sbc8560.h     | 8 ++++++--
 include/configs/stxgp3.h      | 8 ++++++--
 13 files changed, 75 insertions(+), 25 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 31ffbaf..74a84f4 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -312,12 +312,16 @@
 #define CFG_64BIT_VSPRINTF	1
 #define CFG_64BIT_STRTOUL	1
 
-/* I2C */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /* RapidIO MMU */
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 1af9231..418a3a3 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -179,12 +179,16 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /* General PCI */
 #define CFG_PCI_MEM_BASE	0x80000000
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 2b87f1b..db389cf 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -320,13 +320,17 @@ extern unsigned long get_clock_freq(void);
 #define OF_TBCLK		(bd->bi_busfreq / 8)
 #define OF_STDOUT_PATH		"/soc8541@e0000000/serial@4600"
 
-/* I2C */
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_EEPROM_ADDR	0x57
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /*
  * General PCI
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 03ab976..be8f93f 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -326,13 +326,17 @@ extern unsigned long get_clock_freq(void);
 #define OF_TBCLK		(bd->bi_busfreq / 8)
 #define OF_STDOUT_PATH		"/soc8548@e0000000/serial@4600"
 
-/* I2C */
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_EEPROM_ADDR	0x57
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /*
  * General PCI
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 771a9d3..4c8b4e7 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -320,13 +320,17 @@ extern unsigned long get_clock_freq(void);
 #define OF_TBCLK		(bd->bi_busfreq / 8)
 #define OF_STDOUT_PATH		"/soc8555@e0000000/serial@4600"
 
-/* I2C */
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_EEPROM_ADDR	0x57
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /*
  * General PCI
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 1c684f2..835bf5c 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -302,12 +302,16 @@
 #define OF_TBCLK		(bd->bi_busfreq / 8)
 #define OF_STDOUT_PATH		"/soc8560@e0000000/serial@4500"
 
-/* I2C */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /* RapidIO MMU */
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 81bb7cf..246ac7f 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -275,12 +275,13 @@
 /*
  * I2C
  */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_OFFSET		0x3100
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3100
 
 /*
  * RapidIO MMU
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index da01186..4fb5440 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -193,12 +193,16 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /*
  * EEPROM configuration
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 4d83487..87ab934 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -190,12 +190,16 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 /*
  * EEPROM configuration
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 0451b20..f8e3397 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -214,12 +214,16 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 #define CFG_PCI_MEM_BASE	0xC0000000
 #define CFG_PCI_MEM_PHYS	0xC0000000
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index bc3b9aa..cce4624 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -192,12 +192,17 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
+#define CFG_I2C_OFFSET		0x3000
 
 /* I2C RTC */
 #define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 5a434dc..6e4fdb2 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -197,12 +197,16 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
 
 #define CFG_PCI_MEM_BASE	0xC0000000
 #define CFG_PCI_MEM_PHYS	0xC0000000
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index e218597..625cf20 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -172,8 +172,11 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
-/* I2C */
-#define  CONFIG_HARD_I2C    		/* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
@@ -183,6 +186,7 @@
 /* I did the 'if 0' so we could keep the syntax above if ever needed. */
 #undef CFG_I2C_NOPROBES
 #endif
+#define CFG_I2C_OFFSET		0x3000
 
 /* RapdIO Map configuration, mapped 1:1.
 */
-- 
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